How it Works
MSI
Loading...
MS-6741
Manual
81 pgs5.1 Mb0
Schematics
37 pgs768.83 Kb0
Schematics
37 pgs763.88 Kb0
User Manual
82 pgs4.89 Mb0

MSI MS-6741 Schematics

Download
Page 1
5
4
3
2
1
MS-6741
VIA (R) K8T400M(8385)/K8M400(8380) / VT8237 Chipset AMD PGA 754 Processor Schematics
*AMD PGA 754 Processor
D D
*VIA K8T800/K8M800 / VT8237 Chipset
(DDR 400 / AGP 8X / VLink 8X) *Winbond 83697HF-VF LPC I/O *VT6103 PHY 10 / 100 *VT6307 1394A Controler *AC'97 Codec ALC650 Codec *USB 2.0 support (integrated into VT8237) *AGP SLOT * 1 ( 8X )
*PCI SLOT * 3
C C
*DDR DIMM * 2
B B
Orcad Config
6741-B10 6741-B20 6741-B11
Versi on 0 C 06/11/2003 Update
Function Descript ion
MS-6741 0B Option:TLF MS-6741 0B With LAN.With 1394A. Option:MLF MSI Standard MS-6741 0B Option:T7FL
BOM BOM
ERP BOM
601-6741-Bxx 601-6741-Bxx 601-6741-B10
MS-6741 Ver:0B
Option L BOM (with LAN)
K8T800
8235CE
SMT5010 SMT5020
858
DIP
Total
942
Standard BOM (without LAN)
DIP
789
22 70
881
K8T800
8237CD
B10 Cfg
SMT5010 SMT5020
Total
Option L BOM (with LAN)
K8T800
SMT5010
808
8237CD
84DIP
898Total
Option L BOM (with LAN)
DIP
+VT8235CE
+VT8237CD
789
22 70
881
K8M800
8237CD
SMT5010 SMT5020
Total
With LAN. MSI Standard
With LAN. With 1394A. MSI Standard K8T800+VT8237CD
With 1394A.
K8T800 K8M800
76
Title Page
Cover Sheet 1 Block Diagram
8
Clock Synthesizer 7 System Memory
DDR Terminations R & C DDR Damping R & Bypass Cap. NB VIA K8T400M(HT)
VGA Connector SB VT8237
8SMT5020
Create Date.
06/11
PCI Connectors 1 & 2 & 3 1394a Controller AC97 Codec & ATA 66/100/133 RealTek RTL8101L Front & Rear USB Port LPC I/O W83697HF & Floppy Hardware monitor/Fan/BIOS Keyboard/Mouse & I/O Ports. CNR Riser 28 ACPI Power K8 Vcore power PowerOK Circuit BULK / Decoupling Power Generation Manual Parts
History
DDR DIMM 1 & 2 8
Audio Connector
/Front Panel
2 3GPIO SPEC 4,5,6AMD K8 -> 754 PGA Socket
9 10 11,12,13 14AGP SLOT 8X 15 16,17,18 19 20 21 22 23 24 25 26 27
29 30 31 32 33 34 35
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
Cover Sheet
MS-6741
1
Last Revision Date:
Wednesday, June 18, 2003
Sheet
Rev
0B
137
of
Page 2
5
Block Diagram
4
3
2
1
AMD K8
D D
Socket 754
DDR
HyperTransfer
DDR * 2
A
C C
G P
AGP 8X /Fast Write
VIA
K8T400M
R,G,B,HSYNC,VSYNC
VGA Connector
K8M400
10/100 BaseT Lan
MII Interface
VLINK
Dual ATA 100/133
IDE Slot ==>ATA66,100,133 *2
B B
PCI 2
PCI 1
PCI 3
PCI Bus
AC'97 Link
1394a
VIA
VT8235
VT8237
LPC BUS
VT8237 S-ATA
SUPER I/O W83697HF
SATA Connector
USB
X BUS
Onboard AC'97
A A
5
Codec
Dual USB 1.1 OHCI /2.0 EHCI 8 Ports ==> Front-Port *2 , Back-Port *2
4
3
ROM Floopy Parallel Serial
Title
Document Number
2
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
Keyboard
Mouse
Micro Star Restricted Secret
Block Diagram
MS-6741
Last Revision Date: Sheet
1
Rev
Wednesday, June 18, 2003
37
2
of
0B
Page 3
5
4
3
2
1
GPIO FUNCTION
VT8235 GPIO Function Define
INT#
INT#A INT#B INT#C INT#D
INT#B INT#C INT#D INT#A
INT#C INT#D INT#A INT#B
Default
GPI0
GPI1
EXTSMI#
RING#
LID#
BATLOW#
NA Pull up to VBATGPI0 (VBAT)
ATADET0=>Detect IDE1 ATA100/66
EXTSMI#
RING#
ATADET1=>Detect IDE2 ATA100/66
NA
PCI_PME#
GPI7
INTRUDER#
CPUMISS
AOLGP1
NA
NA
NA
THRM#
IORDY
IDSEL
AD16
AD17
AD18
AD19 PCICLK4INT#A
AD25INT#D 1394_PCLK
REQ#/GNT#
PREQ#1 PGNT#1
PREQ#2 PGNT#2
PREQ#3 PGNT#3
PREQ#4 PGNT#4
PREQ#5 PGNT#5
2
CLOCK
PCICLK1
PCICLK2
PCICLK3
Pull up / downFunction defineFunction
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VBAT
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VCC3NAGPI19/IORDY
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
GPIO Spec.
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
337
1
Rev
0B
of
D D
PIN NAME Function define
GPO0 (VSUS33)
GPO1/SUSA#(VSUS33)
GPO2/SUSB#(VSUS33)
GPO3/SUSST1#(VSUS33)
GPO4/SUSCLK(VSUS33)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/SLP#
GPO8/GPI8/IPBIN0
GPO9/GPI9/IPBIN1
C C
GPO10/GPI10/IPBRDFR
GPO11/GPI11/IPBRDCK
GPO12/GPI12/IPBOUT0
GPO13/GPI13/IPBOUT1
GPO14/GPI14/IPBTDFR
GPO15/GPI15/IPBTDCK
GPO16/SA16/STRAP
GPO17/SA17/STRAP
GPO18/SA18/STRAP
GPO19/SA19/STRAP
B B
GPO20/GPI20 /ACSDIN2/PCS0#/EI
GPO21/GPI21/ACSDIN3 /PCS1#/SLPBTN#
GPO22/GPI22/IOR#
GPO23/GPI23/IOW#
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOC GPO26/GPI26/SMBDT2
(VSUS33) GPO27/GPI27/SMBCK2
(VSUS33) GPO28/GPI28/
APICD0/APICCS# GPO29/GPI29/
A A
APICD1/APICACK#
GPO30/GPI30/GPIOD
GPO31/GPI31/GPIOE
Default Function
GPO0
SUSA#
SUSB#
SUSST1#
SUSCLK
CPUSTP#
PCISTP#
GPO7
GPI8
GPI9
GPI10
GPI11
GPI12
GPI13
GPI14
GPI15
SA16
SA17
SA18
SA19
GPI20
GPI21
GPI22
GPI23
GPI24
GPI25
SMBDT2
SMBCK2
SUSLED ( Power LED )
5V_STR Control on S5
SUSB#
SUSST#
NA
NA
NA
NA
NA
JBAT1
NA
NA
NA
NA
NA
NA
LDT Freq Strapping Bit0
LDT Freq Strapping Bit1
LDT Width (Low=8 Bit)
Fast Command (Low=Disable)
NA
NA
NA
NA
NA
NA
SMBDATA2/Slave SMBUS
SMBCLK2/Slave SMBUS
NA
NA
GPI30
GPI31
5
NA
NA
4
Pull up / down
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull down to GND
Pull down to GND
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
PIN NAME
GPI1 (VSUS33) GPI2/EXTSMI#
(VSUS33) GPI3/RING#
(VSUS33) GPI4/LID#
(VSUS33) GPI5/BATLOW#
(VSUS33) GPI6/PME#
GPI7/SMBALRT# GPI16/INTRUDER#
(VBAT) GPI17/CPUMISS
GPI18/AOLGP1/THRM#
PCI Routing
DEVICES
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 2
(MEDION 2nd)
1394
3
Page 4
5
C77 X_102P
VREF routed as 40~50 mils trace wide , Space>25 mils
D D
DDR_VREF{8}
VDD_25_SUS
Place near CPU in 1" , Routed => 5:10/Trace:Space , Same Length
DDR_VREF
R108 15RST R114 15RST
MD[63..0]{10}
C C
B B
MEMDM[7..0]{10}
A A
-MDQS[7..0]{10}
5
C52
X_102P
MEMZN MEMZP
MD63 MD62 MD61 MD60 MD59 MD58 MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
MEMDM7 MEMDM6 MEMDM5 MEMDM4 MEMDM3 MEMDM2 MEMDM1 MEMDM0
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
AE13
AG12
D14 C14
A16 B15 A12 B11 A17 A15 C13 A11 A10
C11
AC1 AC3
AC2 AD1 AE1 AE3
AG3
AJ4
AE2
AF1
AH3
AJ3 AJ5 AJ6
AJ7 AH9 AG5 AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12 AJ14 AJ16
A13
AA1 AG1 AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
B9 C7 A6
A9 A5 B5 C5 A4 E2 E1 A3 B3 E3
F1 G2 G1
L3
L1 G3
J2
L2 M1 W1 W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
VTT_SENSE
MEMVREF1 MEMZN
MEMZP
MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0
MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0
VTT_DDR_SUS
MEMORY INTERFACE
U8B
MEMRESET_L
MEMCLK_H7 MEMCLK_H6 MEMCLK_H5 MEMCLK_H4 MEMCLK_H3 MEMCLK_H2 MEMCLK_H1 MEMCLK_H0
MEMRASA_L MEMCASA_L
MEMBANKA1 MEMBANKA0
RSVD_MEMADDA15 RSVD_MEMADDA14
MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10
MEMRASB_L MEMCASB_L
MEMBANKB1 MEMBANKB0
RSVD_MEMADDB15 RSVD_MEMADDB14
MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10
MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0
4
VTT_A4 VTT_A1 VTT_A2 VTT_A3 VTT_B1 VTT_B2 VTT_B3 VTT_B4
MEMCKEA MEMCKEB
MEMCLK_L7 MEMCLK_L6 MEMCLK_L5 MEMCLK_L4 MEMCLK_L3 MEMCLK_L2 MEMCLK_L1 MEMCLK_L0
MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0
MEMWEA_L
MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0
MEMWEB_L
MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0
4
D17 A18 B17 C17 AF16 AG16 AH16 AJ17
AG10 AE8
AE7 D10
C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4
D8 C8 E8 E7 D6 E6 C4 E5
H5 D4 G5
K3 H3
E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5
H4 F5 F4
L5 J5
E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3
N3 N1 U3 V1 N2 P1 U1 U2
VTT_DDR_SUS
MCKE0 MCKE1
MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4
MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4 MAA3 MAA2 MAA1 MAA0
MAB13 MAB12 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0
MCKE0 {8,9} MCKE1 {8,9}
MEMCLK_H[7..0] {8,9} MEMCLK_L[7..0] {8,9}
-MCS3 {8,9}
-MCS2 {8,9}
-MCS1 {8,9}
-MCS0 {8,9}
-MSRASA {8,9}
-MSCASA {8,9}
-MSWEA {8,9} MEMBANKA1 {8,9}
MEMBANKA0 {8,9}
MAA[13..0] {8,9}
-MSRASB {8,9}
-MSCASB {8,9}
-MSWEB {8,9} MEMBANKB1 {8,9}
MEMBANKB0 {8,9}
MAB[13..0] {8,9}
3
2
1
VDD_12_A
C139
C444 X0.22u/BOT
U8A
W27
W26 AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25
W29 AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28
W25
D29 D27 D25 C28 C26 B29 B27
T25 R25 U27 U26 V25 U25
T27
T28 V29 U29 V27 V28 Y29
Y25 Y27
Y28 R27
R26
T29 R29
N12-7540010-A10
VLDT0_A6 VLDT0_A5 VLDT0_A4 VLDT0_A3 VLDT0_A2 VLDT0_A1 VLDT0_A0
L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0
L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0
L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0
VDD_12_A
CADIP[0..15]{11}
CLKIP1{11}
CLKIN1{11}
CLKIP0{11}
CLKIN0{11}
CTLIP0{11} CTLIN0{11}
VLDT0
R63 49.9RST R60 49.9RST
CADIP15
CADIN15
CADIP14
CADIN14
CADIP13
CADIN13
CADIP12
CADIN12
CADIP11
CADIN11
CADIP10
CADIN10
CADIP9
CADIN9
CADIP8
CADIN8
CADIP7
CADIN7
CADIP6
CADIN6
CADIP5
CADIN5
CADIP4
CADIN4
CADIP3
CADIN3 CADIN2
CADIP1
CADIN1
CADIP0
CADIN0
CTLIP1 CTLIN1
C182 X0.22u
C140 224P
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0
C138 224P
L0_CLKOUT_H1 L0_CLKOUT_H0
HYPER TRANSPORT - LINK0
C180 X0.22u
VLDT0_B6 VLDT0_B5 VLDT0_B4 VLDT0_B3 VLDT0_B2 VLDT0_B1 VLDT0_B0
L0_CLKOUT_L1 L0_CLKOUT_L0 L0_CTLOUT_H1
L0_CTLOUT_L1 L0_CTLOUT_H0 L0_CTLOUT_L0
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
3
2
http://www.msi.com.tw
C192
C181
224P
224P
AH29 AH27 AG28 AG26 AF29 AE28 AF25
N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29
J26 J27 J29 K29
N25 P25 P28 P27
CADOP15
CADON15
CADOP14
CADON14
CADOP13
CADON13
CADOP12
CADON12
CADOP11
CADON11
CADOP10
CADON10
CADOP9
CADON9
CADOP8
CADON8
CADOP7
CADON7
CADOP6
CADON6
CADOP5
CADON5
CADOP4
CADON4
CADOP3
CADON3
CADOP2CADIP2
CADON2
CADOP1
CADON1
CADOP0
CADON0
CLKOP1 CLKON1 CLKOP0 CLKON0
CTLOP0 CTLON0
224P
VLDT0
C59
475P/0805
CLKOP1 {11} CLKON1 {11} CLKOP0 {11} CLKON0 {11}
CTLOP0 {11} CTLON0 {11}
VLDT0 {5}
CADOP[0..15] {11} CADON[0..15] {11}CADIN[0..15]{11}
Micro Star Restricted Secret
K8 DDR & HT
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
437
1
Rev
0B
of
Page 5
5
4
3
VCCA_PLL trace length from the VR1 to the PGA must be 0.75".
2
1
Place al filters close to the PGA.
Keep all power and signal trce away from the VR1.
Place a cut in the GND plane around the
D D
LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil traces to exit ball field) and 500 mils long.
VDDA_25
FB1 180nH/1210
CPU_VDDA_25
C65 475P/0805
C58 3300p
VCCA_PLL regulator circuit.
C55 224P
VCC2_5
R163
C556 106P/1206
1K
R602 0
Near SB/VT8235
Q24 X_2N3904S
E C
R164
B
X_4.7K
THRM# {17,25,31}
VCC2_5
AH25
C51 X_102P
CPU_GD{31}
R64 44.2RST
C C
-LDTSTOP
PS_ON#A{29}
B B
HDT Connectors
DBREQ_L DBRDY TMS TCK TRST_L TDI
NC_AJ18 NC_AH18 NC_AG18 NC_AG17 NC_C19 NC_D18
A A
NC_D20 NC_B19 NC_C21
PS_ON#A
5
R66
Q6 NDS7002AS
R55 56 R56 1K
1 2 3 4 5 6 7 8
RN37 8P4R-56
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
R111 1K
VCC2_5
1K
Place near CPU in 1" , Routed => 5:10/Trace:Space , Same Length
VCC2_5
RN4 8P4R-1K
8P4R-1K RN49
VLDT0
VLDT0{4}
R61 44.2RST
8/28 AMD CHANGE THE PULL-UP POWER
VDD_25_SUS
4
C62 102P
C584
X_102P
C63
102P
VDD_25_SUS
VDDIO_SENSE
Near CPU in 0.5" .
-CPURST{29}
-LDTSTOP{11,18}
COREFB_H{30}
COREFB_L{30}
Differential , "10:10:5:10:10" .
CPUCLK0_H{7}
CPUCLK0_L{7}
3
C61 392P
C64 392P
VTT_DDR_SUS
VCC2_5
L0_REF1 L0_REF0
R62
R57 820 R58 820
R113 1K R105 1K
CPU_GD
VDDIO_SENSE
169RST
RN3
1 2
3 4
5 6
7 8
CLKIN_H
CLKIN_L
NC_AJ23 NC_AH23
DBRDY
TMS TCK TRST_L TDI
NC_C18
NC_A19
NC_AE23 NC_AF23 NC_AF22 NC_AF21
8P4R-1K
AJ25
AF20
AE18
AJ27
AF27
AE26
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
AG15
AH17
AJ28
AE23
AF23
AF22
AF21
AG2 AH1
AE21
AG4 AG6
AE9 AG9
A23 A24 B23
C16
C15 E20
E17 B21 A21
C18 A19 A28
AA2
B18
C20
C1 R3 D3
C6
VDDA1 VDDA2
RESET_L PWROK LDTSTOP_L
L0_REF1 L0_REF0
COREFB_H COREFB_L CORE_SENSE
VDDIOFB_H VDDIOFB_L VDDIO_SENSE
CLKIN_H CLKIN_L
NC_AJ23 NC_AH23
NC_AE24 NC_AF24
VTT_A5 VTT_B5
DBRDY NC_C15 TMS
TCK TRST_L TDI
NC_C18 NC_A19 KEY1
KEY0 NC_AE23
NC_AF23 NC_AF22 NC_AF21
FREE29
J3
FREE31 FREE33 FREE35 FREE1 FREE37 FREE4 FREE38 FREE41 FREE7 FREE11 FREE12 FREE13 FREE14 FREE40
U8C
THERMTRIP_L
THERMDA THERMDC
VID4 VID3 VID2 VID1 VID0
NC_AG18 NC_AH18 NC_AG17
NC_AJ18
G_FBCLKOUT_H
G_FBCLKOUT_L
DBREQ_L
NC_D20 NC_C21 NC_D18 NC_C19 NC_B19
TDO
NC_AF18
RSVD_SCL RSVD_SDA
FREE26 FREE28 FREE30 FREE32 FREE34 FREE36 FREE10 FREE18 FREE19 FREE42 FREE24 FREE25 FREE27
2
THERMTRIP_CPU_L
A20
THERMDA_CPU
A26 A27
VID4
AG13
VID3
AF14
VID2
AG14
VID1
AF15
VID0
AE15
NC_AG18
AG18
NC_AH18
AH18
NC_AG17
AG17
NC_AJ18
AJ18
FBCLKOUT_H
AH19 AJ19
AE19 D20
C21 D18 C19 B19
A22
AF18
D22 C22
B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9
R65
80.6RST
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L NC_D20
NC_C21 NC_D18 NC_C19 NC_B19
TDO
VID0 VID2 VID1 VID3
VID4
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
THERMDA_CPU {26}
VID[4..0] {30}
LAYOUT: Route FBCLKOUT_H/L d if fe re n ti al ly with 20/8/5/8/20 spacing and trace width. ( In CPU breakout => routed 5:5:5 )
8/28 AMD CHANGE THE PULL-UP POWER
VDD_25_SUS
R118 1K
VCC2_5
RN6
7 8 5 6 3 4 1 2
X_8P4R-4.7K
R59 X_4.7K
K8 HDT & MISC
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
C50
C90
104P
225P/0805
Rev
0B
537
of
Page 6
5
4
3
2
1
U8E
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
AG27
VSS9
D D
C C
B B
A A
AF2
AA8 AB9
AA10
AE16
G20 R20 U20
W20 AA20 AC20 AE20 AG20
AJ20
D21
H21
M21
AD21 AG21
G22
N22
R22
U22 AG29 AA22 AC22 AG22 AH22
AJ22
D23
H23
AB23 AD23 AG23
G24
N24
R24
U24
W24 AA24 AC24 AG24
AJ24
C25
D26
H26
M26
AD26 AF26 AH26
C27
D28
G28
H15 AB17 AD17
G18 AA18 AC18
D19
H19
AB19 AD19 AF19
N20
D2
VSS10 VSS11
W6
VSS12
Y7
VSS13 VSS14 VSS15 VSS16
J12
VSS17
B14
VSS18
Y15
VSS19 VSS20
J18
VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31
F21
VSS32 VSS33
K21
VSS34 VSS35
P21
VSS36
T21
VSS37
V21
VSS38
Y21
VSS39 VSS40 VSS41
B22
VSS42
E22
VSS43 VSS44
J22
VSS45
L22
VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56
F23
VSS57 VSS58
K23
VSS59
P23
VSS60
T23
VSS61
V23
VSS62
Y23
VSS63 VSS64 VSS65 VSS66
E24
VSS67 VSS68
J24
VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77
B25
VSS78 VSS79
B26
VSS80 VSS81 VSS82 VSS83
T26
VSS84
Y26
VSS85 VSS86 VSS87 VSS88 VSS89
B28
VSS90 VSS91 VSS92
F15
VSS187 VSS188 VSS206 VSS207
B16
VSS208 VSS209 VSS210 VSS211 VSS212
F19
VSS213 VSS214
K19
VSS215
Y19
VSS216 VSS217 VSS218 VSS219
J20
VSS220
L20
VSS221 VSS222
GROUND
5
VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS189 VSS190 VSS191 VSS192 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS223 VSS201 VSS202 VSS203 VSS204 VSS205
L28 R28 W28 AC28 AF28 AH28 C29 F2 H2 K2 M2 P2 T2 V2 Y2 AB2 AD2 AH2 B4 AH4 B6 G6 J6 L6 N6 R6 U6 AA6 AC6 AH6 F7 H7 K7 M7 P7 T7 V7 AB7 AD7 B8 G8 J8 L8 N8 R8 U8 W8 AC8 AH8 F9 H9 K9 M9 P9 T9 V9 Y9 AD9 B10 G10 J10 L10 N10 R10 U10 W10 AC10 AH10 F11 H11 K11 Y11 AB11 AD11 B12 G12 AA12 AC12 AH12 F13 H13 K13 Y13 AB13 AD13 AF17 G14 J14 AA14 AC14 AE14 D16 E15 K15 AB15 AD15 AH14 E16 G16 J16 AA16 AC16 AE29 AJ26 E18 F17 H17 K17 Y17
VCORE
AC15
AB14
AA15
AB16
AA17 AC17 AE17
AB18 AD18 AG19
AC19 AA19
AB20 AD20
AA21 AC21
AB22 AD22
AA23 AC23
AB24 AD24 AH24 AE25
GNDGND
W21
M22
G23
W23
M24
H18 B20 E21 H22
H24 F26
V10 G13 K14 Y14
G15
H16 K16 Y16
G17
F18 K18 Y18
E19 G19
F20 H20 K20 M20 P20 T20 V20 Y20
G21
N21 R21 U21
F22 K22
P22 T22 V22 Y22
E23
N23 R23 U23
B24 D24 F24 K24
P24 T24 V24 Y24
K26 P26 V26
U8D
L7
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6
J23
VDD7 VDD8 VDD9
N7
VDD10
L9
VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17
J15
VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24
J17
VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD39 VDD38
J19
VDD37 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50
J21
VDD51
L21
VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69
L23
VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD76 VDD77 VDD78 VDD79 VDD80 VDD81 VDD82 VDD83 VDD84 VDD85 VDD86 VDD87 VDD88 VDD89 VDD90 VDD91 VDD92
POWER
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO7 VDDIO8
VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VDDIO29 VDDIO30 VDDIO31 VDDIO32 VDDIO33 VDDIO34 VDDIO35 VDDIO36 VDDIO37 VDDIO38 VDDIO39 VDDIO40 VDDIO41 VDDIO42 VDDIO43 VDDIO44 VDDIO45 VDDIO46 VDDIO47 VDDIO48 VDDIO49 VDDIO50
VDDIO6
VDD96 VDD97 VDD98
VDD99 VDD100 VDD101 VDD102 VDD103 VDD104 VDD105 VDD106 VDD107 VDD108 VDD109 VDD110 VDD111 VDD112 VDD113 VDD114 VDD115 VDD116 VDD117 VDD118 VDD119 VDD120 VDD121 VDD122 VDD123 VDD124 VDD125 VDD126 VDD127 VDD128 VDD129 VDD130 VDD131 VDD132 VDD133
VDD93
VDD94
VDD95
VDD_25_SUS
E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4
N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28
4
VCORE
EMI
LAYOUT: Place 1 capacitor every 1-1.5"
VCORE
along VDD_CORE perimiter.
C30
102P
C117
X_6.8pF
LAYOUT: Place 6 EMI capsalong bottom right sid e of Clawhammer, 2 i n midd le of HT link, and 12 along
VCORE
C436
LAYOUT: Place beside processor.
VDD_25_SUS
C80
224P
C229
VDD_25_SUS
C56
C123
X_475P/0805
102P
102P
C109
C112
GND
bottom left side of Claw-
C440
C432
X_6.8pF/BOT
224P
C152
C156
475P/0805
GND
105P
X_6.8pF/BOT
224P
C164
C430
X_6.8pF/BOT
224P
C150
VDD_25_SUS
C221
3
X_6.8pF/BOT
224P
X_0.22uF
C434
C141
GND
<nopop>
hammer.
X_6.8pF/BOT
224P
C104
GND
X_0.22uF
C442
<nopop>
<nopop>
X_6.8pF/BOT
X_6.8pF/BOT
LAYOUT: Place beside DDR slots.
X_6.8pF/BOT
VDD_25_SUS
C74
473P
<nopop>
X_6.8pF/BOT
C130
GND
C439
C431
C433
VDD_25_SUS
105P
C115
C441
GND
C174
GND
<nopop>
X_6.8pF/BOT
LAYOUT: Place 1000pF capacitors between VRM & CPU.
473P
105P
2
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
K8 POWER & GND
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
Rev
0B
637
of
Page 7
5
VCC3
C301
FS0 FS1 FS2
CLKX1 CLKX2
FS3 HT_66_0
HT_66_1 HT_66_2
SEL_24 SMBDATA1
SMBCLK1
-SEL_66 SPREAD
104P
R237 10K R257 10K
Clock Synthesizer
D D
CLKVCC3
C289 104P
CLKVCC3
C284 104P
CLKVCC3
R604 10K C314 104P
CLKVCC3
C297 104P
CLKVCC3
C315 104P
C C
CLKVCC3
C320 104P
CLKVCC3
C298 104P
CLKVCC3
CLKVCC3
C296 104P
B B
46 47
2 5
32 33
9
10
16 15
19 20
29 30
27 38
39 35
34 43
42
U22
VDD_46 VSS_47
VDD_2 VSS_5
PD VSSF
VDD_9 VSS_10
VDD_16 VSS_15
VDD_19 VSS_20
VDD_29 VSS_30
VSS_27 VDD_38
VSS_39 VDD_35
VSS_34 VDDA
VSSA
ICS950403
FS0/REF0 FS1/REF1 FS2/REF2
XOUT
FS3/48MHZ
ModeB/PCI33_HT66_1
PCI33_HT66_2 PCI33_HT66_3
PCI33_10
PCI33_0 PCI33_1 PCI33_2 PCI33_3
PCI33_F PCI33_4 PCI33_5
24_48MHZ/SEL
SDATA
SCLK
CPUT_0
CPUC_0
CPUT_1
CPUC_1
ModeA/PCI33_HT66SEL
PCICLK6
RESET
XIN
1 48 45
3 4
31 7
8 11 12 13 14 17 18
23 21 22
28 26
25 41
40 37
36
6 24 44
4
FB4 X_120S/0805
CP8
X_COPPER
R474 22 R234 22 R239 22 R255 22
X1 14.318MHZ
R278 33
7 8 5 6 3 4 1 2 7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
R281 33
R271 15RST R275 15RST
C319 39P
GUICLK SB_OSC14 AUD_CLK APICCLK
C285 10P
C286 10P
RN70 8P4R-22
RN103 8P4R-22
RN77 8P4R-22
FP_RST# {29,31}
CLKVCC3
C313 475P/0805
GUICLK {12} SB_OSC14 {17} AUD_CLK {21} APICCLK {18}
VCLK GCLK_SLOT
GCLK_NB PCICLK6 PCICLK4 PCICLK1
PCICLK2 PCICLK3 1394_PCLK SB_PCLK
SIO48M
SMBDATA1 {8,17,18,28,31} SMBCLK1 {8,17,18,28,31}
CPUCLK0_H CPUCLK0_L
USBCLK_SB {16} VCLK {18} GCLK_SLOT {14}
GCLK_NB {12} PCICLK6 {25} PCICLK4 {19} PCICLK1 {19}
PCICLK2 {19} PCICLK3 {19} 1394_PCLK {20} SB_PCLK {18}
SIO48M {25}
CPUCLK0_H {5} CPUCLK0_L {5}
3
SEL_24
FS3 FS2 FS1 FS0
FS0 FS1 FS2 FS3
HT_66_0
VCLK GCLK_SLOT
GCLK_NB
USBCLK_SB SIO48M SB_OSC14 APICCLK
SB_PCLK 1394_PCLK PCICLK3 PCICLK2
PCICLK4 PCICLK6 PCICLK1
CPUCLK0_H CPUCLK0_L
C309 X_5P C312 X_5P
R284 10K
R285 10K R243 X10K R232 X_10K R233 X10K
R235 10K R238 10K R242 10K R286 X10K
R472 10K
CN23
7 8 5 6 3 4 1 2
X_8P4C-10P
C317 X_10P C322 X_10P C283 X_10P C294 X_10P
1 2 3 4 5 6 7 8
C311 X_10P C308 X_10P C468 X_10P
2
ModeAModeB Pin6 Pin7
CLKVCC3
00
0
1
0
1 11
HTTCLK0
HTTCLK0
HTTCLK0 HTTCLK0
SER_24 Pin28
24MHz
1
48MHz
0
CN24 X_8P4C-10P
Pin8 Pin11 HTTCLK1
HTTCLK1
HTTCLK2
HTTCLK2
PCICLK7 PCICLK8 HTTCLK1
PCICLK8
1
PCICLK9
HTTCLK3
PCICLK9 PCICLK9
Input Configuration
FS1
FS2
FS2
111
1
1
0
1 1
0 1 1
A A
0
0 0
0 0
0
Clock Generator Output
FS0
CPU (MHz)
200 0 1 0
166.66
133.33
100 10 0 10 1 0
5
180
X1 input
X1 input
Hi-Z
PCI33 (MHz)
33.33
33.33
33.33
33.33
36.56220
30.00 X1/6 X1/6 Hi-Z
PCI33_HT66 (MHz)
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
73.12
60.00 X1/6 X1/3 Hi-Z
4
Comment
Normal Hammer operation Reserved Athlon compatible Athlon compatible ICS OverClock ICS UnderClock Bypass mode Bypass mode Tri-state mode
3
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Clock Synthesizer
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
737
1
Rev
0B
of
Micro Star Restricted Secret
Page 8
5
VDD_25_SUS
DDR_VREF
DR_MD[63..0]
R173 4.7K
-MSWEA{4,9}
DR_MD0 DR_MD1 DR_MD2 DR_MD3 DR_MD4 DR_MD5 DR_MD6 DR_MD7 DR_MD8 DR_MD9 DR_MD10 DR_MD11 DR_MD12 DR_MD13 DR_MD14 DR_MD15 DR_MD16 DR_MD17 DR_MD18 DR_MD19 DR_MD20 DR_MD21 DR_MD22 DR_MD23 DR_MD24 DR_MD25 DR_MD26 DR_MD27 DR_MD28 DR_MD29 DR_MD30 DR_MD31 DR_MD32 DR_MD33 DR_MD34 DR_MD35 DR_MD36 DR_MD37 DR_MD38 DR_MD39 DR_MD40 DR_MD41 DR_MD42 DR_MD43 DR_MD44 DR_MD45 DR_MD46 DR_MD47 DR_MD48 DR_MD49 DR_MD50 DR_MD51 DR_MD52 DR_MD53 DR_MD54 DR_MD55 DR_MD56 DR_MD57 DR_MD58 DR_MD59 DR_MD60 DR_MD61 DR_MD62 DR_MD63
WP1
-MSWEA
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
DR_MD[63..0]{9,10}
D D
C C
B B
Place 104p Cap. near the DIMM
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
SLAVE ADDRESS = 1010000B
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
3111826344250586674818993
4
SYSTEM MEMORY
104
112
128
136
143
156
164
172
1801582
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
184
PIN
DDR DIMM
SOCKET
NC(RESET#)
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
100
116
124
132
139
145
152
160
176
VDDID
VDDQ15
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
A11 A12 A13
BA0 BA1 BA2 SCL
SDA
SA0 SA1 SA2
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
NC5
CKE0 CKE1 CAS# RAS#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
VSS21
184
VDDSPD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
157 158 71 163
5 14 25 36 56 67 78 86 47
167 48
43 41 130 37 32 125 29 122 27 141 118 115 103
59 52 113 92 91 181 182 183
44 45 49 51 134 135 142 144
16 17 137 138 76 75
173 10
MCKE0
21
MCKE1
111
-MSCASA
65
-MSRASA
154
DR_MEMDM0
97
DR_MEMDM1
107
DR_MEMDM2
119
DR_MEMDM3
129
DR_MEMDM4
149
DR_MEMDM5
159
DR_MEMDM6
169
DR_MEMDM7
177 140
DDR1 DDR400-CH
-MCS0
-MCS1
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
MAA13 MAA0
MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12
SMBCLK1 SMBDATA1
MEMCLK_H5 MEMCLK_L5 MEMCLK_H0 MEMCLK_L0 MEMCLK_H7 MEMCLK_L7
3
-MCS0 {4,9}
-MCS1 {4,9}
-DR_MDQS0 {9,10}
-DR_MDQS1 {9,10}
-DR_MDQS2 {9,10}
-DR_MDQS3 {9,10}
-DR_MDQS4 {9,10}
-DR_MDQS5 {9,10}
-DR_MDQS6 {9,10}
-DR_MDQS7 {9,10}
MAA[13..0]
MAA[13..0] {4,9}
MEMBANKA0 {4,9} MEMBANKA1 {4,9}
SMBCLK1 {7,17,18,28,31} SMBDATA1 {7,17,18,28,31}
MEMCLK_H5 {4,9} MEMCLK_L5 {4,9} MEMCLK_H0 {4,9} MEMCLK_L0 {4,9} MEMCLK_H7 {4,9} MEMCLK_L7 {4,9}
MCKE0 {4,9} MCKE1 {4,9}
-MSCASA {4,9}
-MSRASA {4,9}
Place 104p and 1000p Cap. near the DIMM
DR_MEMDM[7..0]
VDD_25_SUS
R175 4.7K
-MSWEB{4,9}
C43 104P
DR_MEMDM[7..0] {9,10}
DR_MD0 DR_MD1 DR_MD2 DR_MD3 DR_MD4 DR_MD5 DR_MD6 DR_MD7 DR_MD8 DR_MD9 DR_MD10 DR_MD11 DR_MD12 DR_MD13 DR_MD14 DR_MD15 DR_MD16 DR_MD17 DR_MD18 DR_MD19 DR_MD20 DR_MD21 DR_MD22 DR_MD23 DR_MD24 DR_MD25 DR_MD26 DR_MD27 DR_MD28 DR_MD29 DR_MD30 DR_MD31 DR_MD32 DR_MD33 DR_MD34 DR_MD35 DR_MD36 DR_MD37 DR_MD38 DR_MD39 DR_MD40 DR_MD41 DR_MD42 DR_MD43 DR_MD44 DR_MD45 DR_MD46 DR_MD47 DR_MD48 DR_MD49 DR_MD50 DR_MD51 DR_MD52 DR_MD53 DR_MD54 DR_MD55 DR_MD56 DR_MD57 DR_MD58 DR_MD59 DR_MD60 DR_MD61 DR_MD62 DR_MD63
WP2
-MSWEB
DDR_VREF
C31 X_102P
2
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VDDQ2
VSS8
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
SLAVE ADDRESS = 1010001B
102
NC4
VSS0
VSS1
3111826344250586674818993
104
112
128
136
143
156
164
172
1801582
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
184
PIN
DDR DIMM
SOCKET
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
NC(RESET#)
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
100
116
124
132
139
145
152
160
176
VDDID
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
BA0 BA1 BA2 SCL SDA SA0 SA1 SA2
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
NC5
CKE0 CKE1 CAS# RAS#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
184
VDDSPD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A11 A12 A13
157 158 71 163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86 47
167 48
43 41 130 37 32 125 29 122 27 141 118 115 103
59 52 113 92 91 181 182 183
44 45 49 51 134 135 142 144
MEMCLK_H4
16
MEMCLK_L4
17
MEMCLK_H1
137
MEMCLK_L1
138
MEMCLK_H6
76
MEMCLK_L6
75 173
10 21
111 65 154
DR_MEMDM0
97
DR_MEMDM1
107
DR_MEMDM2
119
DR_MEMDM3
129
DR_MEMDM4
149
DR_MEMDM5
159
DR_MEMDM6
169
DR_MEMDM7
177 140
DDR2 DDR400-CH
-MCS2
-MCS3
MAB13 MAB0
MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12
SMBCLK1 SMBDATA1
MCKE0 MCKE1
-MSCASB
-MSRASB
1
-MCS2 {4,9}
-MCS3 {4,9}
MEMBANKB0 {4,9} MEMBANKB1 {4,9}
VDD_25_SUS
-MSCASB {4,9}
-MSRASB {4,9}
MAB[13..0] {4,9}
MEMCLK_H4 {4,9} MEMCLK_L4 {4,9} MEMCLK_H1 {4,9} MEMCLK_L1 {4,9} MEMCLK_H6 {4,9} MEMCLK_L6 {4,9}
VDD_25_SUS
A A
R54 1KST
R52 1KST
C48 104P
DDR_VREF
C32 104P
5
DDR_VREF {4}
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
4
3
2
http://www.msi.com.tw
System Memory : DDR DIMM 1
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
837
Rev
0B
of
Page 9
5
4
3
2
1
DDR Terminations
Ver:0B
VTT_DDR_SUS VTT_DDR_SUS
D D
DR_MD59
DR_MD63 DR_MD58 DR_MD62
-DR_MDQS7
DR_MEMDM7 DR_MD57 DR_MD61 DR_MD56
DR_MD60 DR_MD51 DR_MD55 DR_MD50
C C
B B
-MSCASA{4,8}
-MSCASB{4,8}
-MSRASA{4,8}
-MSRASB{4,8}
DR_MD54
-DR_MDQS6 DR_MEMDM6 MAA13
MAB13 DR_MD53 DR_MD52 DR_MD49
DR_MD48 DR_MD47 DR_MD46 DR_MD43
DR_MD42 DR_MEMDM5
-DR_MDQS5
-MCS0
-MCS0{4,8}
-MCS2
-MCS2{4,8}
-MCS3
-MCS3{4,8}
-MCS1
-MCS1{4,8}
-MSCASA
DR_MD41
-MSWEB
-MSWEB{4,8}
-MSCASB DR_MD45
-MSWEA{4,8}
-MSWEA
-MSRASA
-MSRASB DR_MD44
R174 47
RN66 8P4R-47
7 8 5 6 3 4 1 2
RN63 8P4R-47
7 8 5 6 3 4 1 2
RN60 8P4R-47
7 8 5 6 3 4 1 2
RN57 8P4R-47
7 8 5 6 3 4 1 2
RN56 8P4R-47
7 8 5 6 3 4 1 2
RN54 8P4R-47
7 8 5 6 3 4 1 2
RN52 8P4R-47
7 8 5 6 3 4 1 2
RN50 8P4R-47
7 8 5 6 3 4 1 2
RN47 8P4R-47
7 8 5 6 3 4 1 2
RN46 8P4R-47
7 8 5 6 3 4 1 2
MEMBANKA0{4,8}
MEMBANKB0{4,8}
MEMBANKB1{4,8} MEMBANKA1{4,8}
DR_MD40 DR_MD39 DR_MD35
DR_MD38 DR_MD34 DR_MEMDM4
-DR_MDQS4 DR_MD37 DR_MD33 DR_MD36
DR_MD32
MAB10
MAB0 MAA10 MAA0
MAA1 MAB1 MAB2 MAA2
DR_MD31 DR_MD27 DR_MD30 DR_MD26
MAB3 MAA3 DR_MEMDM3 MAA4
-DR_MDQS3 DR_MD25 MAB4 MAA6
DR_MD29 DR_MD28 MAA5 MAA8
DR_MD24 MAB6 MAB5 DR_MD19
VTT_DDR_SUS
RN43 8P4R-47
7 8 5 6 3 4 1 2
RN41 8P4R-47
7 8 5 6 3 4 1 2
RN36 8P4R-47
7 8 5 6 3 4 1 2
RN33 8P4R-47
7 8 5 6 3 4 1 2
RN31 8P4R-47
7 8 5 6 3 4 1 2
RN30 8P4R-47
7 8 5 6 3 4 1 2
RN29 8P4R-47
7 8 5 6 3 4 1 2
RN27 8P4R-47
7 8 5 6 3 4 1 2
RN25 8P4R-47
7 8 5 6 3 4 1 2
RN24 8P4R-47
7 8 5 6 3 4 1 2
RN22 8P4R-47
7 8 5 6 3 4 1 2
-MCS2
-MCS2{4,8}
DR_MD23 MAA7 MAA9 MAA11
MAA12 MAB7 MAB8 DR_MD22
DR_MD18 MAB9 DR_MEMDM2 MAB11
DR_MD21
-DR_MDQS2 DR_MD17 MAB12
DR_MD16 DR_MD20
MCKE0{4,8} MCKE1{4,8}
DR_MD11 DR_MD10 DR_MD15 DR_MD14
DR_MEMDM1 DR_MD13
-DR_MDQS1 DR_MD12
DR_MD9 DR_MD8 DR_MD3 DR_MD7
DR_MD2 DR_MD6
-DR_MDQS0 DR_MEMDM0
DR_MD1 DR_MD5 DR_MD4 DR_MD0
RN20 8P4R-47
7 8 5 6 3 4 1 2
RN19 8P4R-47
7 8 5 6 3 4 1 2
RN17 8P4R-47
7 8 5 6 3 4 1 2
RN15 8P4R-47
7 8 5 6 3 4 1 2
RN13 8P4R-47
7 8 5 6 3 4 1 2
RN11 8P4R-47
7 8 5 6 3 4 1 2
RN9 8P4R-47
7 8 5 6 3 4 1 2
RN7 8P4R-47
7 8 5 6 3 4 1 2
RN5 8P4R-47
7 8 5 6 3 4 1 2
RN2 8P4R-47
7 8 5 6 3 4 1 2
-MSCASB{4,8}
-MSCASA{4,8}
-MSRASB{4,8}
-MSRASA{4,8}
-MSWEA{4,8}
-MSWEB{4,8}
MEMBANKB1{4,8}
MEMBANKA1{4,8}
MEMBANKB0{4,8}
MEMBANKA0{4,8}
-MCS3
-MCS3{4,8}
-MCS0{4,8}
-MCS1{4,8}
MCKE1{4,8}
MCKE0{4,8}
MAB13 MAA13
MAB12 MAA12 MAB11 MAA11
MAB1 MAA1
MAB3 MAA3 MAB2 MAA2
MAB6
MAA6 MAB4 MAA4
MAB8 MAA8 MAA5 MAB5
MAA0
MAA10
MAB0 MAB10
-MSCASB
-MCS0
-MSCASA
-MCS1
MAA9 MAB9 MAB7 MAA7
-MSRASB
-MSRASA
-MSWEA
-MSWEB
CN20
8P4C-22P CN4
8P4C-22P CN11
8P4C-22P CN10
8P4C-22P CN8
8P4C-22P CN6
8P4C-22P CN13
8P4C-22P CN19
8P4C-22P CN5
8P4C-22P CN18
8P4C-22P CN16
8P4C-22P CN2
8P4C-22P
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
A A
MEMCLK_H5 MEMCLK_H4 MEMCLK_H7 MEMCLK_H6 MEMCLK_H1 MEMCLK_H0
5
R85 120RST R80 120RST R110 120RST R109 120RST R96 120RST R97 120RST
MEMCLK_L5 MEMCLK_L4 MEMCLK_L7
MEMCLK_L1 MEMCLK_L0
MEMCLK_L[7..0]{4,8}
MEMCLK_H[7..0]{4,8}
-DR_MDQS[7..0]{8,10}
4
MEMCLK_L[7..0] MEMCLK_H[7..0]MEMCLK_L6
-DR_MDQS[7..0]
3
DR_MD19
DR_MD[63..0]{8,10}
MAB[13..0]{4,8} MAA[13..0]{4,8}
DR_MEMDM[7..0]{8,10}
DR_MD[63..0] MAB[13..0] MAA[13..0]
DR_MEMDM[7..0]
2
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
DDR Terminations Bank 0
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
Rev
0B
937
of
Page 10
5
4
3
2
1
LAYOUT: Place on backside,
DDR Terminations
D D
C C
B B
RN8 8P4R-10
MD0
1 2
MD4
3 4
MD5
5 6
MD1
7 8
RN10 8P4R-10
MEMDM0 DR_MEMDM0
1 2
-MDQS0
3 4
MD2
5 6
MD6
7 8
RN12 8P4R-10
MD7
1 2
MD3
3 4
MD8
5 6
MD9
7 8
RN14 8P4R-10
MD12
1 2
-MDQS1 -DR_MDQS1
3 4
MEMDM1 DR_MEMDM1
5 6
MD13 DR_MD13
7 8
RN16 8P4R-10
MD14
1 2
MD15
3 4
MD10
5 6
MD11
7 8
RN21 8P4R-10
MD21 DR_MD21
1 2
MEMDM2 DR_MEMDM2
3 4
MD18 DR_MD18
5 6
MD22 DR_MD22
7 8
RN18 8P4R-10
MD20
1 2
MD16
3 4
-MDQS2
5 6
MD17
7 8
RN23 8P4R-10
MD23
1 2
MD19 DR_MD19
3 4
MD24
5 6
MD28 DR_MD28
7 8
RN26 8P4R-10
MD29
1 2
MD25
3 4
-MDQS3
5 6
MEMDM3 DR_MEMDM3
7 8
DR_MD0 DR_MD4 DR_MD5 DR_MD1
-DR_MDQS0 DR_MD2 DR_MD6
DR_MD7 DR_MD3 DR_MD8 DR_MD9
DR_MD12
DR_MD14 DR_MD15 DR_MD10 DR_MD11
DR_MD20 DR_MD16
-DR_MDQS2 DR_MD17
DR_MD23 DR_MD24
DR_MD29 DR_MD25
-DR_MDQS3
RN28 8P4R-10
MD26
1 2
MD30
3 4
MD27
5 6
MD31
7 8
RN40 8P4R-10
MD32
1 2
MD36
3 4
MD33
5 6
MD37
7 8
RN42 8P4R-10
-MDQS4 -DR_MDQS4
1 2
MEMDM4 DR_MEMDM4
3 4
MD34 DR_MD34
5 6
MD38 DR_MD38
7 8
RN45 8P4R-10
MD35 DR_MD35
1 2
MD39
3 4
MD40
5 6
MD44
7 8
RN48 8P4R-10
MD45
1 2
MD41
3 4
-MDQS5 -DR_MDQS5
5 6
MEMDM5 DR_MEMDM5
7 8
RN51 8P4R-10
MD42 DR_MD42
1 2
MD43
3 4
MD46 DR_MD46
5 6
MD47
7 8
RN53 8P4R-10
MD48 DR_MD48
1 2
MD49
3 4
MD52 DR_MD52
5 6
MD53 DR_MD53
7 8
RN55 8P4R-10
MEMDM6
1 2
-MDQS6
3 4
MD54
5 6
MD50 DR_MD50
7 8
RN58 8P4R-10
MD55
1 2
MD51
3 4
MD60
5 6
MD56 DR_MD56
7 8
RN62 8P4R-10
MD61
1 2
MD57
3 4
MEMDM7 DR_MEMDM7
5 6
-MDQS7 -DR_MDQS7
7 8
RN64 8P4R-10
MD62 DR_MD62
1 2
MD58
3 4
MD63
5 6
MD59
7 8
DR_MD26 DR_MD30 DR_MD27 DR_MD31
DR_MD32 DR_MD36 DR_MD33 DR_MD37
DR_MD39 DR_MD40 DR_MD44
DR_MD45 DR_MD41
DR_MD43 DR_MD47
DR_MD49
DR_MEMDM6
-DR_MDQS6 DR_MD54
DR_MD55 DR_MD51 DR_MD60
DR_MD61 DR_MD57
DR_MD58 DR_MD63 DR_MD59
evenly spaced around VTT fill.
VDD_25_SUS
VTT_DDR_SUS
C45
X_0.22uF
<nopop>
C177
X_0.22uF
<nopop>
C227
X_0.22uF
<nopop>
C226
X_0.22uF
<nopop>
C47
X_0.22uF
<nopop>
VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS
C44
105P C57
104P C68
104P
C71
104P
C78
104P C85
104P
VTT_DDR_SUS
C40
C49
105P
104P
VTT_DDR_SUS
104P
C587
105P
C588
C589
105P
C60
C151
104P
105P
C70
C155
105P
104P
C75
C159
104P
105P
C93
104P C101
104P
C110
104P C118
104P
C121
104P
C125
104P
C129
104P
C81
C161
105P
104P
LAYOUT: Locate close to Cla wham mer soc ket .
VTT_DDR_SUS
C53
475P/1206
GND
C88
C167
104P
105P
C96
C170
105P
104P
C107
C173
C132
104P C134
104P C142
104P C149
104P C153
104P C157
104P C160
104P
104P
105P
C113
C178
105P
104P
C119
C196
104P
105P
C124
C203
104P
104P
104P
104P
104P
104P
105P
104P
C165
C169
C172
C176
C183
C193
C126
C210
C16
224P
VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS
C200
104P
C207
104P
C213
104P
C215
104P
C218
104P
C223
104P
105P
104P
105P
C131
C214
104P
C133
C216
104P
105P
C137
C219
105P
104P
C147
GND
C225
104P
105P
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS
GND
in a single line along VTT island.
LAYOUT: Add 100pF and 1000pF on VTT fill near Clawhammer and near DIMMs (both sides).
5
-MDQS[7..0]
-DR_MDQS[7..0] DR_MD[63..0] MD[63..0]
MEMDM[7..0]
DR_MEMDM[7..0]
VTT_DDR_SUS
C39
C233
102P
C232
100P
C66
224P
102P
VTT_DDR_SUS
GND
C143 475P/0805
4
3
C175 475P/0805
C206 475P/0805
C34
X_475P/0805
GND
C241 475P/0805
2
-MDQS[7..0]{4}
-DR_MDQS[7..0]{8,9}
A A
DR_MD[63..0]{8,9}
MD[63..0]{4}
MEMDM[7..0]{4}
DR_MEMDM[7..0]{8,9}
VTT_DDR_SUS
224P
C148
GND
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
DDR Terminations Bank 1
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
10 37
of
Rev
0B
Page 11
A
AVDD2
A10
A24
A25
A26A9B10
M24
G24 M26
M25
G26
M22
G23
T26 P24 P26
K24 K26 H24 H26 R24 R22 N24 N22 L22
L24 F24 R26
P25 N26
K25 H25 R23
P22 N23
K22 H22
L26 L23
F25 B11
A12 D25
D26 C26
U24 U25 U26 V21 V22 V23 V24 V25 V26
C22
AVDD2
RCADP0 RCADP1 RCADP2 RCADP3 RCADP4 RCADP5 RCADP6 RCADP7 RCADP8 RCADP9 RCADP10 RCADP11 RCADP12
J24
RCADP13
J22
RCADP14 RCADP15
RCLKP0 RCLKP1
RCTLP RCADN0
RCADN1 RCADN2 RCADN3 RCADN4
J26
RCADN5 RCADN6 RCADN7 RCADN8 RCADN9 RCADN10 RCADN11 RCADN12
J23
RCADN13 RCADN14 RCADN15
RCLKN0 RCLKN1
RCTLN LDTRST
LDTSTP RPCOMP
RNCOMP RTCOMP
VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT
AGND2
VSS
C21
A23
From Claw Hammer
4 4
CADOP[0..15]{4}
CLKOP0{4} CLKOP1{4}
CTLOP0{4}
CADON[0..15]{4}
3 3
CLKON0{4} CLKON1{4}
CTLON0{4}
-LDTRST{29}
-LDTSTOP{5,18}
2 2
CADOP0 CADOP1 CADOP2 CADOP3 CADOP4 CADOP5 CADOP6 CADOP7 CADOP8 CADOP9 CADOP10 CADOP11 CADOP12 CADOP13 CADOP14 CADOP15
CLKOP0 CLKOP1
CTLOP0
CADON0 CADON1 CADON2 CADON3 CADON4 CADON5 CADON6 CADON7 CADON8 CADON9 CADON10 CADON11 CADON12 CADON13 CADON14 CADON15
CLKON0 CLKON1
CTLON0
-LDTRST
-LDTSTOP RPCOMP
PNCOMP RTCOMP
VDD_12_A
B23
B24
B25
U14A
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VSS
VSS
VSS
VSS
VSS
VSS
A8
B8
B13
VSS
VSS
VSS
B15
B21
B22C8D8
B17
B19
B26B9C10
VLDT
VLDT
VSS
VSS
D6
D12
VLDT
VSS
C11
D14
VLDT
VSS
C23
D16
VLDT
VSS
B
C24
C25C9D10
VLDT
VSS
D18
D20
D11
VLDT
VLDT
VLDT
VSS
VSS
VSS
E5E6E8F7F8
VLDT
VSS
D22
VLDT
VSS
D23
VLDT
VSS
D24D9E10
VLDT
VSS
F12
C
K8T400M HT Interface
VDD_12_A
E11
E21
E22
E23
E24E9F10
F11
F15
F16
F19
F20
F21
F22
F23
G21
G22
H21
J11
J12
J13
J14
J15
J16
J17
K18
K21
VLDT
VSS
VLDT
VLDT
TCADP0 TCADP1 TCADP2 TCADP3 TCADP4 TCADP5 TCADP6 TCADP7 TCADP8
TCADP9 TCADP10 TCADP11 TCADP12 TCADP13 TCADP14 TCADP15
TCADN0
TCADN1
TCADN2
TCADN3
TCADN4
TCADN5
TCADN6
TCADN7
TCADN8
TCADN9 TCADN10 TCADN11 TCADN12 TCADN13 TCADN14 TCADN15
TCLKN0
TCLKN1
VSS
VSS
L11
L12
VLDT
VLDT
TCLKP0 TCLKP1
TCTLP
TCTLN
VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT VLDT
VSS
VSS
L13
L18
VLDT
VLDT
CADIP0
B12
CADIP1
A13
CADIP2
B14
CADIP3
A15
CADIP4
A17
CADIP5
B18
CADIP6
A19
CADIP7
B20
CADIP8
E12
CADIP9
D13
CADIP10
E14
CADIP11
D15
CADIP12
D17
CADIP13
E18
CADIP14
D19
CADIP15
E20
CLKIP0
B16
CLKIP1
E16
CTLIP0
A21
CADIN0
C12
CADIN1
A14
CADIN2
C14
CADIN3
A16
CADIN4
A18
CADIN5
C18
CADIN6
A20
CADIN7
C20
CADIN8
E13
CADIN9
C13
CADIN10
E15
CADIN11
C15
CADIN12
C17
CADIN13
E19
CADIN14
C19
CADIN15
D21
CLKIN0
C16
CLKIN1
E17
CTLIN0
A22
VDD_12_A
L21 M18 N18 N21 P18 P21 R18 T18 T21 T22 T23 T24 T25 U18 U21 U22 U23
VSS
VSS
L14
L15
K8T400M
J10
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F13
F14
F17
F18
F26
G25H1H23
J2
J3
J18
VSS
VSS
VSS
VSS
VSS
J21
J25
K4G1K10
VSS
VSS
VSS
VSS
VSS
VSS
K12
K16
K17
K23H2L10
K15
K13
K14
K11
To Claw Hammer
CADIP[0..15] {4}
CLKIP0 {4} CLKIP1 {4}
CTLIP0 {4}
CADIN[0..15] {4}
CLKIN0 {4} CLKIN1 {4}
CTLIN0 {4}
D
E
For K8M400 Only
AVDD2
VDD3
PNCOMP RTCOMP
RPCOMP
21
FB26
C550
301S
102P
C163 104P C166 104P
Around NB
R128 49.9RST R120 100RST R127 49.9RST
C551 105P
VDD_12_A
VDD_12_A
1 1
Title
Size Document Number Rev
C
A
B
C
D
Date: Sheet
<OrgName>
NORTH BRIDGE K8T400M (HT)
MS-6741
E
0B
11 37Wednesday, June 18, 2003
of
Page 12
A
B
K8T400M AGP 8X ,V-Link, Misc. Control
C
D
E
VDDQ
4 4
ST0{14} ST1{14} ST2{14}
GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31
GC/BE#0 GC/BE#1 GC/BE#2 GC/BE#3
AD_STBS0 AD_STBF0
AD_STBS1 AD_STBF1
SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7
SB_STBS SB_STBF
ST0 ST1 ST2
AGPPCOMP AGPNCOMP
AGPVREF_GC
DBIL DBIH
A
GAD[0..31]{14}
3 3
GC/BE#[3..0]{14}
AD_STBS0{14} AD_STBF0{14}
AD_STBS1{14} AD_STBF1{14}
GFRAME{14}
GIRDY{14}
GTRDY{14}
GDEVSEL{14}
GSTOP{14}
GPAR{14}
RBF{14}
WBF{14}
GREQ{14}
2 2
GGNT{14}
GSERR{14}
GCLK_NB{7}
SBA[7..0]{14}
SB_STBS{14} SB_STBF{14}
AGPVREF_GC{14}
1 1
AGP8XDET#{14}
DBIL{14}
DBIH{14}
AF18
GD0/FPD10
AD18
GD1/FPD11
AE18
GD2/FPDVICLK
AF17
GD3/FPD09
AD17
GD4/FPD08
AD16
GD5/FPD07
AE16
GD6/FPD06
AF16
GD7/FPD05
AF14
GD8/FPDVIDET
AD14
GD9/FPDVIHS
AD13
GD10/FPD01
AE13
GD11/FPD23
AF13
GD12/FPD00
AD12
GD13/FPD22
AF12
GD14/FPD21
AE12
GD15/FPD20
AD10
GD16/FPD18
AE10
GD17/FPD17
AF10
GD18/FPD16
AD9
GD19/FPDE
AF9
GD20/FPD14
AF8
GD21/FPCLK
AE9
GD22/FPD13
AD8
GD23/FPD15
AF6
GD24/DVP1D09
AD7
GD25
AE6
GD26/DVP1D10
AD5
GD27
AF5
GD28/DVP1D07
AF4
GD29/DVP1D06
AE4
GD30/DVP1D08
AD4
GD31/DVP1D04
AD15
GCBE0/FPD03
AF11
GCBE1/SB_DA
AD11
GCBE2/FPD19
AC7
GCBE3/DVP1D11
AF15
ADSTB0S/FPD02
AE15
ADSTB0F/FPD04
AF7
ADSTB1S/FPDET
AE7
ADSTB1F/FPD12
AC9
GFRAME/FPHS
AC10
GIRDY/SB_CK
AC14
GTRDY
AC11
GDEVSEL/FPVS
AC12
GSTOP/FPDVICLK_N
AC16
GPAR/FPDVIVS
AD6
RBF
AC1
WBF/FPCLK_N
Y1
GREQ/DVI_DDCCK
AA3
GGNT/DVI_DDCDA
AC15
GSERR/FPDVIDE
A11
GCLK
AC2
SBA0/DVP1VS
AC3
SBA1/DVP1DE
AD1
SBA2/DVP1D00
AD2
SBA3/DVP1HS
AF2
SBA4/DVP1D05
AD3
SBA5/DVP1D03
AE3
SBA6/DVP1CLK
AF3
SBA7/DVP1CLK_N
AE1
SB_STBS/DVP1D02
AF1
SB_STBF/DVP1D01
AA2
ST0
AA1
ST1/DVP1DET
AB1
ST2
V1
AGPPCOMP
W1
AGPNCOMP
AC13
AGPVREF0
AC6
AGPVREF1
Y2
AGP8XDET
AC4
DBIL
AC5
DBIH
U1
VCCQQ
VCC4/NC
VCC4/NC
VCC4/NC
VSSQQ
VSS
VSS
VSS
VSS
T1
R12
R13
R14
R15
R11
VSS
VSS
VSS
VSS
VSS
VSS
VDD3
AGPVREF_GC
M5K8M9L8N9P9R9
N5
L5K9L9
J9
VCC4/NC
VCC4/NC
VSS
VCC4/NC
VSS
P23R1R2R3R4R5R10
VCC4/NC
VCC4/NC
VCC4/NC
VSS
VSS
VSS
P15
P16
P17
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VSS
VSS
VSS
VSS
VSS
VSS
N25P5P10
P11
P12
P13
P14
VCC4/NC
VSS
N17
VCC4/NC
VSS
N16
VCC4/NC
VSS
N15
VCC4/NC
VSS
N14
VCC4/NC
VSS
N13
VCC4/NC
VSS
VCC4/NC
VSS
N12
G2G3G4G5H3H4H5J4J5
VCC4/NC
VSS
N11
F6F2F5E1F4
VCC4/NC
VSS
M23
N10
VCC4/NC
VSS
VCC4/NC
VSS
M21
F1K5E4E2E3
F3
VCC4/NC
D1
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
UPSTB UPSTB
DNSTB DNSTB
UPCMD DNCMD
LVREF
LCOMPP
PWRGD
PCIRST TESTIN
SUSTAT
DEBUG
AR/NC AG/NC
RSET/NC HSYNC/NC VSYNC/NC
XIN/NC
INTA/NC
BISTIN/NC
SPCLK1/NC SPCLK2/NC
SPD1/NC SPD2/NC
TVD00/DVP0D00/NC TVD01/DVP0D01/NC TVD02/DVP0D02/NC TVD03/DVP0D03/NC TVD04/DVP0D04/NC TVD05/DVP0D05/NC TVD06/DVP0D06/NC TVD07/DVP0D07/NC TVD08/DVP0D08/NC TVD09/DVP0D09/NC TVD10/DVP0D10/NC TVD11/DVP0D11/NC
TVCLKIN/DVP0DET/NC
TVDE/DVP0DE/NC TVHS/DVP0HS/NC TVVS/DVP0VS/NC
TVCLK/DVP0DCLK/NC
GPO0/NC GPOUT/NC
VSS
VSS
VSS
VSS
VSS
M17
VSS
M16
M15
M14
M13
M12
M11
VSS
VSS
M10
U14B
VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7
VBE
VPAR
AB/NC
VSS
L25
AD20 AD21 AF24 AE24 AE19 AF20 AD24 AF25
AE21 AF19
AE23 AF23
AF22 AD22
AF26 AD23
AF21 AD19 AE26 AD25 AC26 AD26 AC17
B3 A3 A2
C4 A1 B1
C6 E7
D3 P2
C2 P1 C1
J1 K2 K3 L4 K1 L2 L3 M4 L1 M2 M3 M1
P4 N1 N4 N3
VLAD0 VLAD1 VLAD2 VLAD3 VLAD4 VLAD5 VLAD6 VLAD7
LVREF_NB
LCOMPP
TESTIN
DEBUG
RSET
VLAD[0..7] {18}
VBE0# {18} VPAR {18}
UPSTB {18} UPSTB# {18}
DNSTB {18} DNSTB# {18}
UPCMD {18} DNCMD {18}
C209 X_102P
PWROK_NB# {17}
PCIRST1# {20,25,31}
SUSST# {17}
R160 X10K R154 10K
AR {15} AG {15} AB {15}
R486 140RST
HSYNC {15} VSYNC {15}
GUICLK {7} PIRQ#A {14,16,19}
DDCCLK {15} DDCDATA {15}
LAYOUT: Place caps as close NB as possible
TESTIN
AGPNCOMP AGPPCOMP
LCOMPP
VCC2_5
For K8M400 Only
Ver:0B
1
VCC3 VDD3
3 5 7
Note: When use K8T400M, this power circuit for analog power should be NOPOPed.
P3
N2 D2
VSS
VSS
L17
L16
K8T400M
B
C
D
C462 105P/B C243 105P
VCC2_5
R166 4.7K
VDDQ
R161 60.4RST R156 60.4RST
R165 360RST
VCC2_5
R150 3KST
C197 104P
LVREF_NB
R155 1KST
RN115
0/0805/B
2 4
RN116
6
8P4R-0
8
Title
NORTH BRIDGE K8T400M (AGP & VLINK)
Size Document Number Rev
Custom
Date: Sheet
C202 104P
<OrgName>
MS-6741
12 37Wednesday, June 18, 2003
E
of
0B
Page 13
A
VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AA4 AA5 AB11 AB12 AB13 AB14 AB7 AB8 M8 N8 T2 T3 T4 T5 T8 T9 U2 U3 U4 U5 U8 U9 V10 V11 V12 V13 V2 V3 V4 V8 V9 W2 W3 W4 W9 Y3 Y4 Y5
AA21 AA22 AA23 AA24 AA25 AA26 AB21 AB22 AB23 AB24 AB25 AB26 F9 H10 H11 H12 H15 H16 H8 H9 J8 K19 L19 M19 P8 R19 R8 T19 U19 V18 V19 W10 W11 W12 W13 W14 W19 Y20 Y21 Y22 Y23 Y24 Y25 Y26
AB16 AC8 AC22 AC23 AC24 AE2 AE5 AE8 AE11 AE14 AE17 AE20 AE22 AE25
VDDQ
VDD
VSUSNB
C1 X_102P
AVDD1
RGBPLL
4 4
GND_RGBPLL
RGBPLL
GND_RGBPLL DAC_PLL
GND_DAC
DAC_PLL
3 3
2 2
1 1
GND_DAC
VDD
A
AC25
E25 E26
AB17 AB18 AB19 AB20 AC18 AC19 AC20 AC21
V14 V15 V16
V17 W15 W16 W17 W18
R16
R17
R21
R25
T10
T11
T12
T13
T14
T15
T16
T17
U10
U11
U12
U13
U14
U15
U16
U17
W21 W22 W23 W24 W25 W26 AB2 AB3 AB4 AB5 AB6 AB9
AB10 AB15
D5 A5 C5 B5
A6 B6
B2 C3 D4
A4 B4
A7 D7
B7 C7
V5
W5
U14C
VSUS15/VSUS25
AVDD1 AGND1
VCCPLL1/NC VCCPLL2/NC GNDPLL1/NC GNDPLL2/NC
VCCPLL3/NC GNDPLL3/NC
DACVDD/NC GNDDAC1/NC GNDDAC2/NC
VCCRGB/NC GNDRGB/NC
NC NC
VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2
VSS/NC VSS/NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
K8T400M
B
K8T400M Power and Ground Connections
VCC2_5
C459 X_104P/BOT C450 X_102P/BOT
VDD
C461 X_102P/BOT C453 X_104P/BOT C456 X_104P/BOT
LAYOUT : Popualte caps on the bottom side of NB.
C460 X_104P/BOT C458 X_104P/BOT C455 X_104P/BOT
For K8M800 Only
VDD
FB28 301S
FB29 301S
VDD3
FB30 301S
FB31 301S
VDD3
FB32 301S
Note: When use K8T400M, these power circuit for GFX analog power should be NOPOPed.
B
C
VDD_12_A
C454 X_0.22u/B C449 475P/1206/B C452 X_0.22u/BOT
C457 X_0.22u/BOT
C446 X_0.22u/BOT
LAYOUT: Place caps on the bottom of NB
VDDQ
RGBPLL
C463
C552
105P
102P
GND_RGBPLL
DAC_PLL
C465
C464
105P
102P
GND_DAC
AVDD1
C467
C466
105P
102P
C
D
Title
Size Document Number Rev
Custom
D
Date: Sheet
<OrgName>
NORTH BRIDGE K8T400M (POWER/GND)
MS-6741
E
0B
13 37Wednesday, June 18, 2003
E
of
Page 14
5
4
3
2
1
3VDUAL
R203
4.7K
B
PIRQ#A {12,16,19} PCIRST# {16,31} GGNT {12}
DBIH {12} WBF {12}
SB_STBS {12}
AD_STBS1 {12}
GFRAME {12}GIRDY{12}
GTRDY {12} GSTOP {12} PCI_PME# {17,19,20,25}
GPAR {12}
AD_STBS0 {12}
AGPVREF_GC {12}
1 : 4X 0 : 8X
3VDUALVCC3
R192
4.7K
Q34 2N3904S
E C
R168 10K
SUSB# {17,31}
C358 X_33P
Q28
B
2N3904S
E C
VDDQ VCC3 3VDUAL VCC5 VCC12
+12V
R170 1K
2
C282
VDDQ
GAD[0..31] SBA[7..0]
GC/BE#[3..0]
C277 104P
C21
105P
C276 104P
105P
C235
GAD[0..31]{12}
SBA[7..0]{12}
GC/BE#[3..0]{12}
VDDQ
105P
Add-in Card Power
Imax
2.0A
6.0A
0.75A
2.0A
1.0A
VDDQ
DS
Q29 NDS7002AS
G
R172 200RST
V_Min V_MaxVUnits
1.425 1.575
3.15 3.45
3.15 3.45
4.75 5.25
11.4 12.6
R171
8.2K
GPERR
Title
Document Number
Micro Star Restricted Secret
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
AGP PRO Slot
MS-6741
Last Revision Date: Sheet
V V V V
Wednesday, June 18, 2003
14 37
1
of
Rev
0B
GREQ ST0
ST2 RBF
DBIL SBA0
SBA2 SB_STBF
SBA4 SBA6
GAD31 GAD29
GAD27 GAD25
AD_STBF1 GAD23
GAD21 GAD19
GAD17 GC/BE#2
GIRDY
GDEVSEL GPERR GSERR
GC/BE#1 GAD14
GAD12 GAD10
GAD8 AD_STBF0
GAD7 GAD5
GAD3 GAD1
VREF_CG
DS
VCC3
G
Q41 NDS7002AS
VDDQ
VCC
AGP1
B1
-OVRCNT
B2
5V
B3
5V
B4
USB+
B5
GND
B6
-INTB
B7
CLK
B8
-REQ
B9
3.3V
B10
ST0
B11
ST2
B12
-RBF
B13
GND
B14
RESERVED
B15
SBA0
B16
3.3V
B17
SBA2
B18
SB_STB
B19
GND
B20
SBA4
B21
SBA6
B22
RSVD/KEY
B23
GND/KEY
B24
AUX3V/KEY
B25
3.3V/KEY
B26
AD31
B27
AD29
B28
3.3V
B29
AD27
B30
AD25
B31
GND
B32
AD_STB1
B33
AD23
B34
VDDQ
B35
AD21
B36
AD19
B37
GND
B38
AD17
B39
C/-BE2
B40
VDDQ
B41
-IRDY
B42
AUX3V/KEY
B43
GND/KEY
B44
RSVD/KEY
B45
3.3V/KEY
B46
-DEVSEL
B47
VDDQ
B48
-PERR
B49
GND
B50
-SERR
B51
C/-BE1
B52
VDDQ
B53
AD14
B54
AD12
B55
GND
B56
AD10
B57
AD8
B58
VDDQ
B59
AD_STB0
B60
AD7
B61
GND
B62
AD5
B63
AD3
B64
VDDQ
B65
AD1
B66
VREF_CG
AGP8X-R
VCC3
+12V
R169 1K
AGP8XDET_GC#
DS
G
1 : 4X 0 : 8X 1 : 4X
4
-TYPEDET
RESERVED
RESERVED
-SB_STB
RSVD/KEY
GND/KEY
RSVD/KEY
3.3V/KEY
-AD_STB1 C/-BE3
-FRAME
RSVD/KEY
GND/KEY
RSVD/KEY
3.3V/KEY
C/-BE0
-AD_STB0
VREF_GC
R145
4.7K
Q26 NDS7002AS
AGP8XDET#
R167 10K
12V
USB-
GND
-INTA
-RST
-GNT
3.3V ST1
-PIPE GND
-WBF
SBA1
3.3V
SBA3
GND
SBA5 SBA7
AD30 AD28
3.3V AD26 AD24
GND
VDDQ
AD22 AD20
GND AD18 AD16
VDDQ
-TRDY
-STOP
-PME
GND
PAR
AD15
VDDQ
AD13 AD11
GND
AD9
VDDQ
AD6
GND
AD4 AD2
VDDQ
AD0
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66
0 : 8X
VDDQ
+12V
AGP8XDET# {12}
AGP8XDET_GC# AGPGND
GGNT ST1
WBF SBA1
SBA3 SB_STBS
SBA5 SBA7
GAD30 GAD28
GAD26 GAD24
AD_STBS1 GC/BE#3
GAD22 GAD20
GAD18 GAD16
GFRAME
GTRDY GSTOP
R228 0
GPAR GAD15
GAD13 GAD11
GAD9 GC/BE#0
AD_STBS0 GAD6
GAD4 GAD2
GAD0 AGPVREF_GC
3
AGP8XDET_GC#
AGP PRO Connector
D D
C279 104P
PIRQ#B{16,19}
GREQ{12}
ST0{12} ST1 {12} ST2{12}
RBF{12}
DBIL{12}
SB_STBF{12}
3VDUAL
AD_STBF1{12}
GDEVSEL{12}
GSERR{12}
AD_STBF0{12}
VDDQ
R230
3.32KST R229
1.47KST
R231
1.02KST
5
GCLK_SLOT{7}
C C
B B
4X : 0.75V 8X : 0.35V
A A
VREF_CG
C471 105P
Page 15
A
B
C
D
E
D20
4 4
AB AG AR
3
3
1
1
2
2
4 5
45
7
7 8 6
VCC
8 6
VVSYNC VHSYNC
DN006S
VCC
F5
1.1A-microSMD110-S
VCC
POLY SWITCH
CB11 104P
AR{12} AG{12}
3 3
AB{12}
C513
C512
R477 75
R478 75
R479 75
22P
22P
FB12 30S FB14 30S FB16 30S
C514 22P
C515 22P
C516 22P
C517 22P
16
10
6 1 7 2 8 3 9 4
5
JVGA1
11 12 13 14 15
R475
1.8K
R476
1.8K
DDCDATA {12}
DDCCLK {12}
17
YCN15F-003-1
VCC
R480
4.7K
2 2
VSYNC{12}
R482 0
VVSYNC
R481 27
R483
4.7K
VCC
HSYNC{12}
R485 0
VHSYNC
R484 27
C518 22P
C519 22P
Trace Note:
1.The 5V traces should be 20 mils to VGA/DFP
1 1
A
B
C
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Micro Star Restricted Secret
VGA Connector
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
D
of
15 37
E
Rev
0B
Page 16
A
B
C
D
E
VCC3
AD[31..0]{19,20}
4 4
3 3
C_BE#[3..0]{19,20}
2 2
1 1
AD[31..0]
C_BE#[3..0]
FRAME#{19,20}
DEVSEL#{19,20}
IRDY#{19,20} TRDY#{19,20} STOP#{19,20} SERR#{19}
PAR{19,20}
PERR#{19,20}
PCIRST#{14,31}
PIRQ#A{12,14,19} PIRQ#B{14,19} PIRQ#C{19} PIRQ#D{19,20}
PREQ#1{19} PREQ#2{19} PREQ#3{19} PREQ#4{19} PREQ#5{20}
PGNT#1{19} PGNT#2{19} PGNT#3{19} PGNT#4{19} PGNT#5{20}
A
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C_BE#0 C_BE#1 C_BE#2 C_BE#3
FRAME# DEVSEL# IRDY# TRDY# STOP# SERR# PAR PERR#
PCIRST#
PIRQ#A PIRQ#B PIRQ#C PIRQ#D PIRQ#E PIRQ#F PIRQ#G PIRQ#H
PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 PREQ#5
PGNT#0 PGNT#1 PGNT#2 PGNT#3 PGNT#4 PGNT#5
H9
H10
H12J8K8L8M8N8P8R8R19
G2
AD0
J4
AD1
J3
AD2
H3
AD3
F1
AD4
G1
AD5
H4
AD6
F2
AD7
E1
AD8
G3
AD9
E3
AD10
D1
AD11
G4
AD12
D2
AD13
D3
AD14
F3
AD15
K3
AD16
L3
AD17
K2
AD18
K1
AD19
M4
AD20
L2
AD21
N4
AD22
L1
AD23
M2
AD24
M1
AD25
P4
AD26
N3
AD27
N2
AD28
N1
AD29
P1
AD30
P2
AD31
E2
CBE0
C1
CBE1
L4
CBE2
M3
CBE3
J1
FRAME
H2
DEVSEL
J2
IRDY
H1
TRDY
K4
STOP
C2
SERR
F4
PAR
C3
PERR
R1
PCIRST
A4
INTA
B4
INTB
B5
INTC
C4
INTD
D4
INTE
E4
INTF
A3
INTG
B3
INTH
A5
REQ0
B6
REQ1
C5
REQ2
D5
REQ3
P3
REQ4
R3
REQ5
A6
GNT0
D6
GNT1
C6
GNT2
E5
GNT3
R4
GNT4
R2
GNT5
GND
GND
A1A2B1
H11
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
GND
GND
GND
GND
GND
GND
E8
F25
GND
H23
J21
J25B2A17
B
A13
USBGND
USBGND
A15
T8
T19
U19V8V19
U8
V21W9W10
W11
W17
W18
W19
W21
Y21
W8
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
KBCK/KA20G
KBDT/KBRC
MSDT/IRQ12
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
A19
A21
B13
B15
B17
B19
B21
C13
C14
C15
C16
C17
C18
C19
C20
C21
D13
D15
D17
D19
D21
E13
E15
E17
E19
E21
H13
USBVDD USBVDD USBVDD USBVDD USBVDD USBVDD USBVDD USBVDD USBVDD USBVDD USBVDD USBVDD
USBSUS25
PLLVDDA PLLVDDA
PLLGNDA PLLGNDA
USBP0+
USBP0-
USBP1+
USBP1-
USBP2+
USBP2-
USBP3+
USBP3-
USBP4+
USBP4-
USBP5+
USBP5-
USBP6+
USBP6-
USBP7+
USBP7-
USBOC0 USBOC1 USBOC2 USBOC3 USBOC4 USBOC5 USBOC6 USBOC7
USBCLK
USB REXT
UDPWR
UDPWREN
MSCK/IRQ1
USBGND
USBGND
USBGND
H15
H16
H14
USBGND
H18
H17
U27A
A22 B22 C22 D22 E22 F22 J13 J14 J15 J16 J17 J18
C24
A23 B23
D23 C23
E20 D20 A20 B20 E18 D18 A18 B18 D16 E16 A16 B16 D14 E14 A14 B14
C26 D24 B26 C25 B24 A24 A26 A25
E23 B25 D26
D25
W3 V1 W1 W2
USBGND
VT8235-CE
USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4
USBREXT
CB18 104P
USBVCCA
USBGNDA USBP0
USBN0 USBP1 USBN1 USBP2 USBN2 USBP3 USBN3 USBP4 USBN4 USBP5 USBN5 USBP6 USBN6 USBP7 USBN7
USBCLK_SB
R487
5.11KST R6 10K
KBCLK# {27} KBDAT# {27} MSCLK# {27} MSDAT# {27}
+
CB21 104P
PGNT#5 PGNT#0
C
EC44 X_ELS10/16-B
C520
104P
near SB
VCC2_5
CB22 105P
R606 820RST
PLOCK#{19}
R403 2.7K R435 2.7K
3VDUAL
VSUS2_5
CB19 104P
USBP0 {24} USBN0 {24} USBP1 {24} USBN1 {24} USBP2 {24} USBN2 {24} USBP3 {24} USBN3 {24} USBP4 {24} USBN4 {24} USBP5 {24} USBN5 {24} USBP6 {24} USBN6 {24} USBP7 {24} USBN7 {24}
USB_OC#1 {24} USB_OC#2 {24} USB_OC#3 {24}
USBCLK_SB {7}
RN90
DEVSEL# TRDY# PIRQ#C IRDY# FRAME#
SERR# PERR# STOP# PLOCK#
PREQ#0 PREQ#5
8P4R-2.7K
1 2 3 4 5 6 7 8
RN91 8P4R-2.7K
1 2 3 4 5 6 7 8
R401 2.7K R402 2.7K
VCC3
D
VCC3
104PCB13 104PCB14 104PCB15 104PCB16 104P/BCB20
VCC VCC
PIRQ#D PIRQ#B
PIRQ#A
PIRQ#E PIRQ#H PIRQ#G PIRQ#F
RN97 8P4R-2.7K
1 2 3 4 5 6 7 8
RN106 8P4R-2.7K
1 2 3 4 5 6 7 8
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
VT8237 Part 1
MS-6741
Last Revision Date: Sheet
E
Rev
0B
Wednesday, June 18, 2003
16 37
of
Page 17
A
J9
J10
J11
K9L9J12
L18
PDD[15..0]{22}
4 4
SDD[15..0]{22}
3 3
Using external PHY
2 2
VCC2_5
1 1
PDD[15..0] PDD0
PDREQ{22}
PDDACK#{22}
PDIOR#{22} PDIOW#{22} PIORDY{22}
PDCS#1{22}
PDCS#3{22}
PDA0{22} PDA1{22} PDA2{22}
IRQ14{22}
SDD[15..0]
SDREQ{22}
SDDACK#{22}
SDIOR#{22} SDIOW#{22} SIORDY{22}
SDCS#1{22}
SDCS#3{22}
SDA0{22} SDA1{22} SDA2{22}
IRQ15{22}
STXP_1 STXN_1
SRXN_1 SRXP_1
STXP_2 STXN_2
SRXN_2 SRXP_2
near chipset
VT8237
CP23
12
FB22 X_601S
C536 104P
CP24
12
FB23 X_601S
PDREQ PDDACK# PDIOR# PDIOW# PIORDY PDCS#1 PDCS#3 PDA0 PDA1 PDA2 IRQ14
SDREQ
SDDACK#
SDIOR# SDIOW# SIORDY
SDCS#1
SDCS#3
IRQ15
X_104PC523
R502 X_360RST
STXP1
103PC525
STXN1
103PC526
SRXN1
122PC527
SRXP1
122PC528
STXP2
103PC529
STXN2
103PC530
SRXN2
122PC531
SRXP2
122PC533
near chipset
+2.5VSATA
C537 105P
A
PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8
PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
SDA0 SDA1 SDA2
SIDEVREF SIDECOMP
CM2 475P/0805
GNDSATA
AA22
Y24 AA26 AA25 AB26 AC26 AC23 AD25 AD26 AC24 AC25 AB24 AB23 AA24
Y26 AA23
Y23
V24
W26
Y25
Y22
V22
V23
W23
V25
W24
AD24 AC20
AB20 AC21 AE18 AF18 AD18 AD19 AF19 AE20 AF20 AD20 AE21 AF21 AD21 AD22 AF22
AD17 AD23 AF23 AE23 AF17 AF25 AF26 AF24 AC22 AE24 AE26
AC19 AB21 AB13
AC13 AF13
AE13 AB15
AC15 AF15
AE15
W12 W13 W14 W15 W16
AC17 AC11 AB17 AB11
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
PDDREQ PDDACK PDIOR PDIOW PDRDY PDCS1 PDCS3 PDA0 PDA1 PDA2 IRQ14
SDD0/TBC1 SDD1/VALID SDD2 SDD3/RXD2 SDD4/RXD3 SDD5/RXD4 SDD6/RBC0 SDD7/RBC1 SDD8/RXD5 SDD9/RXD6 SDD10/RXD7 SDD11/RXD8 SDD12/RXD9 SDD13/TXD0 SDD14/TXD1 SDD15/TXD2
SDDRQ/RXD1 SDDACK/TBC0 SDIOR/TXD4 SDIOW/TXD3 SDRDY/RXD0 SDCS1/TXD8 SDCS3/TXD9 SDA0/TXD6 SDA1/TXD5 SDA2/TXD7 IRQ15
SVREF SCOMPP STXP1
STXN1 SRXN1
SRXP1 STXP2
STXN2 SRXN2
SRXP2 VDDATS
VDDATS VDDATS VDDATS VDDATS
VDDAS VDDAS VDDAS VDDAS
AB14
VDD
GNDATS
AC14
M9
VDD
VDD
VDD
VDD
VDD
VDD
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
AD12
AD13
AD14
AD15
AD16
AE12
B
M18N9N18P9P18R9R18T9T18U9U18V9V10
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDAS
GNDAS
GNDAS
GNDAS
AF14
AE14
AE16
AF12
AF16
AC16
AC12
AB16
AB12
B
VDD
VDD
F6F7J5K5P5
VDD
GND
V11
VDD
GND
V12
VDD
GND
C
3VDUALVCC2_5
VSUS2_5
AA4
AB4
AB5
AB6
T4
V13
V14
V15
V16
V17
V18
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
L13
L14
L11
L12
R5
VT8237
VT8237
U4
U27B
VSUS25
VSUS33
ACSDIN3/SLP_BTN
GND
L15
VSUS25
VSUS33
VSUS33
VSUS33
AOLGP/THRM
GPIOA/Strap1 GPIOB/Strap2 GPIOC/Strap0 GPIOD/Strap3
GND
GND
GND
L16
M11
M12
PDDACK#
1 - Disable external SATA PHY
PDCS#1
SATA master/slave mode 1 - Disable 0 - Enable
ACBITCLK
ACSDIN0 ACSDIN1 ACSDIN2
ACSYNC
ACSDO
ACRST
PME
BATLOW
CPUMISS
RING
SUSST1
EXTSMI
SMBALRT
PWRBTN
PWROK CLKRUN CPUSTP
PCISTP
INTRUDER
SUSCLK SMBCK1
SMBDT1 SMBCK2
SMBDT2
SUSA SUSB
SUSC
GPI0
GPI1 GPO0 GPO1
SERIRQ
SPKR
OSC
TPO
TEST
VDDA0
GNDA0
SREXT
SXO/Strap4
SXI/Strap5
VDDA33 GNDA33
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M13
M14
M15
K18
R290 10K
R292 10K R294 X_10K
LID
GND
VT8235-CE
T1 U3 V2 U1 V3 T2 U2 T3
W4 V4 Y1 Y2 Y3 Y4 AA1 AB1 AC1 AD2 AF1 AB7 AC7 AD6
AE1 AB3 AC4
AB2 AC3
AD1 AA2
AD3 AF2
AE2 AC2 AA3 AE3 AE5 AD5 AF5 AC6
AD9 AF8 AB8
AF9 AE9
AC10 AB10 AD11 AE10 AF10 AE11 AF11 W5
V5 M16 N11 N12 N13 N14 N15 N16
AC_BITCLK AC_SDIN0 AC_SDIN1 AC_SDIN2
AC_SDIN3 ACSYNC ACSDO ACRST
PCI_PME#
BATLOW#
CPUMISS
RI#
SUSST#
THRM#
EXTSMI# SMBALRT#
ATADET1
PWRBTN#_S
PWROK_NB#
CLKRUN#
CPUSTP# PCISTP#
INTRUDER
SUSCLK
SMBCLK1
SMBDATA1
SMBCLK2
SMBDATA2
SUSA#
SUSB#
SUSC#
GPI0
ATADET0
SUSLED
GPO1 PCISTP#
GPIOA
GPIOB
GPIOC
GPIOD
SERIRQ
SPKR
SB_OSC14
TPO
TEST
VDDA0
SREXT
SXO SXI
VDDA33
VCC3
VCC3
VCC3
C
AC_SYNC
1
2
AC_SDOUT
3
4
5
6
7
8
PCI_PME# {14,19,20,25}
SUSST# {12} THRM# {5,25,31}
ATADET1 {22} PWROK_NB# {12}
SMBCLK1 {7,8,18,28,31} SMBDATA1 {7,8,18,28,31}
SUSB# {14,31} SUSC# {31}
ATADET0 {22}
SERIRQ {25} SPKR {29} SB_OSC14 {7}
VCC2_5
R503
1.02KST
C532 104P
VT8235
R509
4.7K C534
15P
VCC2_5
CM1 475P/0805
AC_RST#
RN107 8P4R-22
C524
104P
FB21 X_601S
1 2
CP22
SXO SXI
X2
1 2
YCRY25H
VT8237
STXP_1 STXN_1
SRXN_1 SRXP_1
103P/BC521 103P/BC522 104PCB26 104P/BCB27
AC_BITCLK {21,28} AC_SDIN0 {21,28} AC_SDIN1 {28}
AC_SYNC {21,28} AC_SDOUT {21,28} AC_RST# {21,28}
VCC3
C231 X_47P
VT8235 CE
*"SXO" =>0/1:Enable/disable auto reboot
*"SXI" => LPC ROM 1/0:Enable/Disbale
C535
R510
15P
4.7K
SATA1
8 1 2
3 4 5
6 7 9
SATACONN
D
VT8237
*"ACSYNC" => LPC FWH Command
0 - Enable FWH 1 - Disable FWH(Default)
ACSYNC
R488 4.7K
R371 4.7K
GPI0
INTRUDER
SUSLED SUSCLK EXTSMI# CPUMISS RI#
BATLOW# PCI_PME# PWROK_NB# PWBTIN# ATADET1 SMBALRT#
GPO1 SUSB# SUSC# ATADET0 SPKR SERIRQ CPUSTP#
TPO
R372 1M
AC_SDIN0
7
AC_SDIN2
5
AC_SDIN1
3
AC_SDIN3
1
TEST
R362 4.7K R342 4.7K
CLKRUN#
R496 X_4.7K
1 3 5
SUSST#
THRM#
*"SPKR" => CPU Freq. Adjust Setting
7 1 3 5 7 1 3 5 7
R71 X_4.7K R373 X_4.7K R400 X_4.7K R497 X_4.7K
1 3 5 7
1 - Disable (Default) 0 - Enable
VT8235
SMBCLK2
8
SMBDATA2
6
SMBDATA1
4
SMBCLK1
2
C230 X_47P
RN93 8P4R-1K
VT8237
8
STXP_2 STXN_2
SRXN_2 SRXP_2
D
1 2
3 4 5
6 7 9
8 6 4 2
2 4 6 8 2 4 6 8 2 4 6 8
2 4 6 8
R499 4.7K
7 5 3 1
SATA2
SATACONN
VCC3
VBAT
RN98 8P4R-4.7K
3VDUAL
RN108 8P4R-4.7K
RN99 8P4R-4.7K
RN100 8P4R-4.7K
VCC3
RN109 8P4R-4.7K
3VDUAL
VCC3
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
E
*"SA[17:16]" => LDT Frequency 00 - 200MHz (Default) 01 - 400MHz 10 - 600MHz 11 - 800MHz
*"SA18" => LDT Width
0 - 8-Bit (Default) 1 - 16-Bit
*"SA19" => Fast command
0 - Disable (Default) 1 - Enable
GPIOD GPIOC GPIOA GPIOB
RN121
8P4R-4.7K
1 3 5 7
(VD[2])
(VD[3])
2 4 6 8
Ver:0B
Strapping
*"PDA1/SDA1" = > External loop test mode
0 - Disable (Default) 1 - Enable
*"PDA2/SDA2" => ROMSIP Select
0 - Disable 1 - Enable(Default)
*"-SDCS3" => Test Mode Select
0 - Disable (Default) 1 - Enable
*"EEDI/-S D C S1 " = > EEPR O M Se le c t
0 - BIOS Porting - ACR 1 - External EEPROM (On-b oard)(Default)
R507 1K
(VD[5])
(VD[6])
(VD[7])
VCC3
VCC3
PWRBTN#_S
C538 X_104P
R498 1K
R501 1K
VCC3
R500 1K
R525 1K R504 1K
R506 X_10K
R74 1K R543 1K
R76 1K R508 1K
ACSDO
R512 4.7K
0/1:Enable/disable auto reboot
R513 68
VT8237
PWBTIN#
Micro Star Restricted Secret
VT8237 Part 1
MS-6741
Last Revision Date: Sheet
E
(VD[1:0])
SA17
(VD[1])
SA18
(VD[2])
SA16
(VD[0])
SA19
(VD[3])
PDA1
VT8237
SDA1
VT8235
PDA2
VT8237
SDA2
VT8235
PDCS#3
VT8237
SDCS#3
VT8235
SDCS#1
VT8235
PDA0
VT8237
(VD[4])
SDA0
VT8235
PWBTIN# {29}
Rev
0B
Wednesday, June 18, 2003
of
17 37
Page 18
A
VLAD[0..7]{12}
4 4
VBE0#{12}
UPCMD{12} DNCMD{12}
UPSTB{12}
UPSTB#{12}
3 3
2 2
ALL_PWRGD31}
1 1
DNSTB{12}
DNSTB#{12}
R523 360RST
VCLK{7}
LPC_AD0{25} LPC_AD1{25} LPC_AD2{25} LPC_AD3{25}
LPC_FRAME#{25}
LPC_REQ#{25}
RSMRST#{31}
1 2
C377
3 4
10P
VPAR{12}
VLREF_SB VCOMPP_SB VCLK
LPC_FRAME#
LPC_REQ#
ALL_PWRGD
RSMRST#
VBAT
X1
YCRY32.768C Y3
VLAD0 VLAD1 VLAD2 VLAD3 VLAD4 VLAD5 VLAD6 VLAD7
VBE0# UPCMD
DNCMD UPSTB
UPSTB# DNSTB
DNSTB#
VPAR
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
C406 X_103P
C370 10P
A
H25
VD0
G26
VD1
K26
VD2
J23
VD3
F26
VD4
G25
VD5
K22
VD6
K24
VD7
E24
VD8
G23
VD9
L26
VD10
L25
VD11
E26
VD12
E25
VD13
L24
VD14
M26
VD15
G24
VBE
K23
UPCMD
K25
DNCMD
J26
UPSTB
J24
UPSTB
H26
DNSTB
H24
DNSTB
F24
VPAR
H22
VLREF
J22
VCOMPP
L22
VCLK
F23
VIOUT
G22
VIIN
AD8
LAD0
AF7
LAD1
AE7
LAD2
AD7
LAD3
AF6
LFRM
AE6
LREQ0
AE8
LREQ1
AC5
PWRGD
AD4
RSMRST
AF4
VBAT
AE4 AF3
RTCX1 RTCX2
X2
L23
N21
N22
N23
N24
N25
N26
P22
P23
P24
P25
L21
K21
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
GND
GND
GND
GND
GND
GND
GND
P11
P12
P13
P14
P15
P16
R11
P26
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
GND
GND
GND
GND
GND
R15
R14
R13
R12
R16
R21
B
VSUS2_5
E11E9E10
GND
AE17
D12
MIISUS25
GND
AE19
E12
MIISUS25
GND
AE22
GND
AE25
AA9
D9
GND
AB18
MIIVCC
MIIVCC
MIIVCC
MIIVCC
AGPBZ/GPI6
APICD0/APICCS
APICD1/APICACK
GND
GND
GND
GND
T21
AA10
K19
MCRS MCOL
MTXENA
MTXD0 MTXD1 MTXD2 MTXD3
MTXCLK
MRXER
MRXCLK
MRXDV MRXD0 MRXD1 MRXD2 MRXD3
MDCK
MDIO
PHYRST
EECS EEDO
EEDI
EECK
RAMVCC
RAMGND
FERR
A20M
IGNNE
INIT
INTR
NMI SMI
STPCLK
SLP GHI
DPSLP
VGATE
VIDSEL
VRDSLP
PCICLK
APICCLK
PLLVCC
PLLGND
U27C
A11 B11
C11 A10 B10 B9 A9 C10
D10 C9 D8 C8 B8 A8 C7
A7 B7
D7 D11
B12 A12 C12
E7
E6 U24
U26 T24 R26 T25 T26 U25 R24 V26 R22 P21
AC9 AC8 AB9 AD10
R23 U23 R25
T23 T22 U22
VT8235-CE
M24
M21
M22
M23
M25
L19
M19
N19
P19AA21
VCCVK
VCCVK
VCCVK
VCCVK
VCCVKGND
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
GND
GND
GND
GND
W25
AB19
AB22
AB25
GND
AC18
GND
GND
T11
GND
GND
GND
GND
GND
GND
T12
T16
T15
T14
T13
W22
B
C
MII_CRS MII_COL
MTXEN
RN85D
MTXD0 MTXD1
RN85A
MTXD2
RN85B
MTXD3
MII_TXCLK MII_RXER
MII_RXCLK MII_RXDV
MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3
MMDC
MMDIO MMRST#
MII_EECS#
MII_EEDO
MII_EEDI
MII_EECK
+2.5VRAM
GND_RAM
FERR# A20M# IGNNE# CPUINIT# INTR NMI_SB SMI# STPCLK# SLP# GHI# DPSLP#
VGATE VIDSEL VRDSLP AGPBZ#
SB_PCLK
APICCLK APICD0#
APICD1# +2.5VSBPLL GND_SBPLL
C
JCDP1
SM_DATA
SM_CLK
INT
KEY
PWR_GD
YJ1X5-1
R311 33
R320 33 R316 33
R550 33
SMBDATA1
1 2 3 4 5
MII_CRS {23} MII_COL {23}
7 8 5 6 1 2 3 4
CB30
104P
SMBCLK1
ALL_PWRGD
R603 1K
SMBDATA1 {7,8,17,28,31} SMBCLK1 {7,8,17,28,31}
MII_TXEN
MII_TXD0 MII_TXD2
MII_TXD3
MII_RXER {23} MII_RXCLK {23} MII_RXDV {23} MII_RXD0 {23} MII_RXD1 {23} MII_RXD2 {23} MII_RXD3 {23}
MII_MDC
MII_MDIO
MII_RST#
MII_EECS# {23} MII_EEDO {23} MII_EEDI {23} MII_EECK {23}
R522 2.2 CB29 105P
Ver:0B
0B:SLP# connect to -LDTSTOP
R524 0
SATAACT# {29}
SB_PCLK {7} APICCLK {7}
CP25
12
FB24
X_601S
X_601S
FB25
12
CP26
Ver:0B
8P4R-33
MII_TXEN {23} MII_TXD0 {23} MII_TXD1 {23} MII_TXD2 {23} MII_TXD3 {23} MII_TXCLK {23}
MII_MDC {23} MII_MDIO {23}
MII_RST# {23}
VCC2_5
-LDTSTOP {5,11}
VCC2_5
D
ALL_PWRGD
VGATE
MII Lan
MMDIO MII_EEDIMII_TXD1 MTXEN
IGNNE# A20M# INTR SMI#
CPUINIT# NMI_SB STPCLK#
FERR# SLP# APICD0# APICD1# APICCLK
DPSLP# GHI#
AGPBZ# VIDSEL
VRDSLP
NOTEBOOK SIGNALS
R381 1K
5VSB
R380 3K
R379
VBAT1 YBA3V
1K
VLREF_SB is 0.65V
VCC2_5
K8T800 will be 0.625V(R250=1KST)
K8M800 will be 0.45V(R250=665RST)
R248 3KST
VLREF_SB
R250 1KST
vdd/4=0.625volt
D
R514 X_4.7K R515 4.7K
104P CB28
R317 1.5K R78 10KRN85C R310 10K
RN69
1 2 3 4 5 6 7 8
X_8P4R-680(OPT) RN72
1 2 3 4 5 6 7 8
X_8P4R-680(OPT) R252 1K R253 4.7K R256 330 R254 330 R264 X_4.7K
R268 4.7K R272 4.7K
R321 4.7K
R267 4.7K
R249 4.7K
12
D14
BAT54C
3
C292 104P
C302 104P
Title
Document Number
VCC33VDUALVCC2_5
VCC3
3VDUAL
VT8237
*"EEDI" => Eliminate Lan EEPROM 0/1:Disable/Enable
VCC3
JBAT1(1-2)
YJUMPER-MG
JBAT1 YJ103
1
VBAT
2
R526 1K
3
C389
103P
Micro Star Restricted Secret
VT8237 Part 1
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
VBAT
MS-6741
E
Last Revision Date:
Wednesday, June 18, 2003
Sheet
18 37
E
Rev
0B
of
Page 19
5
PCI Connectors
VCC3
D D
PIRQ#B{14,16}
PIRQ#D{16,20}
PCICLK1{7}
C C
IRDY#{16,20}
DEVSEL#{16,20}
PLOCK#{16}
PERR#{16,20} SERR#{16}
B B
-12V
PIRQ#B PIRQ#C PIRQ#D
PCICLK1 PREQ#1 AD31
AD29 AD27
AD25 C_BE#3
AD23 AD21
AD19 AD17
C_BE#2 IRDY# DEVSEL# PLOCK#
PERR# SERR# C_BE#1
AD14 AD12
AD10
AD7 AD5
AD3
PCI1
B1
-12V
B2
TCK
B3
GND
B4
TDO
B5
+5V
B6
+5V
B7
INTB#
B8
INTD#
B9
PRSNT1#
B10
RSVD2
B11
PRSNT2#
B12
GND
B13
GND
B14
RSVD5
B15
GND
B16
CLK
B17
GND
B18
REQ#
B19
+5V
B20
AD31
B21
AD29
B22
GND
B23
AD27
B24
AD25
B25
+3.3V
B26
C/BE3#
B27
AD23
B28
GND
B29
AD21
B30
AD19
B31
+3.3V
B32
AD17
B33
C/BE2#
B34
GND
B35
IRDY#
B36
+3.3V
B37
DEVSEL#
B38
GND
B39
LOCK#
B40
PERR#
B41
+3.3V
B42
SERR#
B43
+3.3V
B44
C/BE1#
B45
AD14
B46
GND
B47
AD12
B48
AD10
B49
GND
B52
AD8
B53
AD7
B54
+3.3V
B55
AD5
B56
AD3
B57
GND
B58
AD1
B59
+5V
B60
ACK64#
B61
+5V
B62
+5V
YSLOT120
TRST#
+12V
TMS
INTA#
INTC# RSVD1 RSVD3
GND GND
RSVD4
RST#
GNT#
GND
RSVD6
AD30
+3.3V
AD28 AD26
GND
AD24
IDSEL#
+3.3V
AD22 AD20
GND AD18 AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR AD15
+3.3V
AD13 AD11
GND
C/BE0#
+3.3V
GND
REQ64#
+5V
+5V +5V
+5V
AD9
AD6 AD4
AD2 AD0 +5V
+5V +5V
TDI
IDSEL= AD16 INT#= A, B, C, D
VCC3
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
PIRQ#A
3VDUAL
PCIRST2# PGNT#1 PCI_PME#
AD30 AD28
AD26 AD24
AD16 AD22
AD20 AD18
AD16 FRAME# TRDY# STOP#
PAR AD15
AD13 AD11
AD9
C_BE#0AD8 AD6
AD4 AD2
AD0AD1
3VDUAL
4
AD[31..0]{16,20}
C_BE#[3..0]{16,20}
C274 X_104P
AD[31..0]
C_BE#[3..0]
PIRQ#A {12,14,16} PIRQ#C {16}
PCIRST2# {31}
PCI_PME# {14,17,20,25}
FRAME# {16,20} TRDY# {16,20} STOP# {16,20}
PAR {16,20}
PREQ#4
PCICLK4{7} PCICLK2{7}
PIRQ#C PIRQ#A
PCICLK4 PCICLK2 PREQ#2 AD31
AD29 AD27
AD25 C_BE#3
AD23 AD21
AD19 AD17
C_BE#2 IRDY# DEVSEL# PLOCK#
PERR# SERR# C_BE#1
AD14 AD12
AD10
AD8 AD7
AD5 AD3
AD1
-12V
R328 0
VCC3
VCC VCC+12VVCCVCC
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
IDSEL= AD17 INT#= B, C, D, A
3
PCI2
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSVD2 PRSNT2# GND GND RSVD5 GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND
AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V
YSLOT120-B
TRST#
+12V TMS
INTA#
INTC# RSVD1 RSVD3
GND GND
RSVD4
RST# GNT#
GND
RSVD6
AD30 +3.3V AD28 AD26
GND
AD24
IDSEL#
+3.3V AD22 AD20
GND AD18 AD16 +3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR AD15 +3.3V AD13 AD11
GND
AD9
C/BE0#
+3.3V
AD6 AD4
GND
AD2 AD0
REQ64#
2
3VDUAL
VCC3
+12V
A1 A2 A3 A4
TDI
A5
+5V
+5V +5V
+5V
+5V +5V
+5V
PIRQ#B
A6
PIRQ#D
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
R329 22 R352 22
3VDUAL
PCIRST2# PGNT#2 PCI_PME#
AD30 AD28
AD26 AD24
AD17 AD22
AD20 AD18
AD16 FRAME# TRDY# STOP# SDONE1
PAR AD15
AD13 AD11
AD9
C_BE#0 AD6
AD4 AD2
AD0
R330 100
PIRQ#A PGNT#4
PCICLK3{7}
AD19
PIRQ#D PIRQ#B
PCICLK3 PREQ#3 AD31
AD29 AD27
AD25 C_BE#3
AD23 AD21
AD19 AD17
C_BE#2 IRDY# DEVSEL# PLOCK#
PERR# SERR# C_BE#1
AD14 AD12
AD10
AD8 AD7
AD3 AD1
-12V
VCC
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
PCI3
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSVD2 PRSNT2# GND GND RSVD5 GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND
AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V
YSLOT120
C356 X_104P
TRST#
+12V
TMS
INTA#
INTC# RSVD1 RSVD3
GND GND
RSVD4
RST# GNT#
GND
RSVD6
AD30
+3.3V
AD28 AD26 GND AD24
IDSEL#
+3.3V
AD22 AD20 GND AD18 AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD15
+3.3V
AD13 AD11 GND
C/BE0#
+3.3V
GND
REQ64#
+5V
+5V +5V
+5V
AD9
AD6 AD4
AD2 AD0 +5V
+5V +5V
1
VCC3VCC3
VCC
+12V
A1 A2 A3 A4
TDI
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
PIRQ#C PIRQ#A
3VDUAL
PCIRST2# PGNT#3 PCI_PME#
AD30 AD28
AD26 AD24
AD18 AD22
AD20 AD18
AD16 FRAME# TRDY# STOP#
PAR AD15
AD13 AD11
AD9
C_BE#0 AD6
AD4AD5 AD2
AD0
IDSEL= AD18 INT#= C, D, A, B
IDSEL= AD19
RN92
PGNT#2 PGNT#3 PGNT#4
1 2 3 4 5 6 7 8
PGNT#1{16} PREQ#1{16} PGNT#2{16}
A A
PGNT#3{16} PREQ#3{16}
5
8P4R-2.7K
PREQ#1PGNT#1 PREQ#2
PREQ#2{16}
PREQ#3 PREQ#4
PREQ#4{16}PGNT#4{16}
4
RN96
7 8 5 6 3 4 1 2
8P4R-2.7K
VCCVCC3
INT#= A
3
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
PCI Connector 1 & 2
MS-6741
Last Revision Date: Sheet
1
Wednesday, June 18, 2003
19 37
Rev
0B
of
Page 20
5
1394a OHCI Link Layer Controller
D D
P3VA
AD[31..0]
C_BE#[3..0]
FRAME#{16,19}
IRDY#{16,19}
TRDY#{16,19}
STOP#{16,19}
DEVSEL#{16,19}
PREQ#5{16} PGNT#5{16}
PERR#{16,19}
PIRQ#D{16,19}
1394_PCLK{7}
C384 X_10P
PCI_PME#
VCC3
PAR{16,19}
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
C_BE#3 C_BE#2 C_BE#1 C_BE#0
PAR FRAME# IRDY# TRDY# STOP#
R366 100
DEVSEL#
PREQ#5 PGNT#5 PERR# PIRQ#D
1394_PCLK 1394_RST#
R305 X_0 R306
4.7K
97
AD31
98
AD30
99
AD29
100
AD28
101
AD27
104
AD26
105
AD25
106
AD24
109
AD23
110
AD22
112
AD21
116
AD20
117
AD19
118
AD18
119
AD17
120
AD16
5
AD15
6
AD14
7
AD13
10
AD12
11
AD11
12
AD10
13
AD9
14
AD8
17
AD7
18
AD6
19
AD5
21
AD4
22
AD3
23
AD2
27
AD1
28
AD0
107
CBE3#
122
CBE2#
4
CBE1#
15
CBE0#
3
PAR
123
FRAME#
124
IRDY#
126
TRDY#
128
STOP#
108
IDSEL
127
DEVSEL#
96
REQ#
95
GNT#
2
PERR#
91
INTA#
93
PCICLK
92
PCIRST#
37
PME#
AD[31..0]{16,19}
C C
C_BE#[3..0]{16,19}
AD25
PCIRST1#{12,25,31}
B B
PCI_PME#{14,17,19,25}
102
VDD1
VSS1
94
4
113
103
125
VDD2
VSS2
111
8
VDD3
VSS3
121
VCC3
20
VDD4
VSS4
1
33
VDD5
VSS5
9
VDD6
VSS6
16
114
VSS7
26
VDDC1
VSS9 VDDC2
VSS8
34 35
24
RAMVDD
GNDATX0
59
GNDARX0
GNDARX1
64
69
68
GNDATX2
GNDARX2
GNDATX1
83
82
39
PVDD1
49
PVDD2
25
P3VA
62
65
VDDATX0
VDDARX0
VSSC1
RAMVSS
115
76
75
VDDATX1
VDDARX1
VSSC2
36
90
41
89
XTPBIAS0
XTPA0P
XTPA0M
VDDATX2
VDDARX2
XTPB0P
XTPB0M
XTPBIAS1
XTPA1P
XTPA1M
XTPB1P
XTPB1M
XTPBIAS2
XTPA2P
XTPA2M
XTPB2P
XTPB2M
XCPS
XREXT
D6/CMCJMP
PHYRESET
CTL0/PC0JMP CTL1/PC1JMP
D7/PC2JMP
LINKON/TSIJMP
LREQ/TSOJMP
MODE0 MODE1
SCLK
LPS/CMC
SCL/EECK
SDA/EEDI
EEDO EECS
PGND2
PGND1
VT6307-CD
50
B07-0630704-V01
U28
NC
XO
D5 D4 D3 D2 D1 D0
XI
3
74 73 72 71 70
81 80 79 78 77
88 87 86 85 84
63
66
52 58
54 55 53
57 56 51 48 47 46 45 44 43 42 40 38 67
32 31 30 29
60
61
+12V
BRS340-S-CASE403-03
TPBIAS0 TPA0+ TPA0­TPB0+ TPB0-
TPBIAS1 TPA1+ TPA1­TPB1+ TPB1-
R363 11KST R364 1KST
C354
104P
R318 2K
EECK EEDI
R353 1M
D2
A C
EC7
EL47/50V-2.5
Ver:0B
R561
4.7K C365 10P
Y2 24MHz
C364
2
For MSI 1394 Back-pinheader
CPWR_B
C94
+
X_102P
TPBIAS0
R68
4.99KST 270P
C72
For MSI 1394 Front-pinheader
+12V
CPWR_F
R368 6.34KST C380 47P
P3VA
Eeprom Select
4.7K Remove
P3VA
10P
24C02 93C46S
D16
BRS340-S-CASE403-03
A C
EC41
+
X_47U/50V EC40 EL470/16V-3.5
Near 1394 Controllor .
C397 270P R397 4.99KST
R307 510
+
EECK EEDI
F1
YFUSE2AS-P
C76334P
R72 54.9RST R75 54.9RST R67 54.9RST R70 54.9RST
Near 1394 Controllor .
CPWR_F
YFUSE2AS-P
C417 X_102P
Every 1394-port should support
1.5A current .
R390 54.9RST R391 54.9RST R392 54.9RST
R393 54.9RST C398 334P
U26
6
SCLK
5
SDA
7
WP
24C02S
M33-24C01A3-A26
VCC
GND
1
Every 1394-port should support
CPWR_0
TPA0+ TPA0­TPB0+ TPB0-
F3
VCC3
8 1
A0
2
A1
3
A2
4
1.5A current .
14 13 12 11
10
PGND
CPWR_1
C392 103P
TPB1­TPB1+ TPA1­TPA1+TPBIAS1
I1394_USB1B
9
PWR TPA+
TPA­TPB+ TPB-
GND
I1394+USBx2-D20-BK
C352 104P
VCC3
EC30
X_22U/6.3V/S
A A
+
VCC3
5
C331 104P
L17
X_L02-8008044-J07
1 2
C340 104P
C341 104P
CP10
C381 104P
C333 104P
P3VA
C376 104P
C332 104P
C379 104P
IDSEL= AD25 INT#= D
C357
104P
4
J1394_1
12
KEY
34 56 78 910
YJ205-1-HG
N31-2051201-H06
TPB1+ TPB1­CPWR_1
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
3
2
http://www.msi.com.tw
TPA1-TPA1+
CPWR_1
Every 1394-port should support
1.5A current .
Micro Star Restricted Secret
1394a Link Layer Controller
MS-6741
Last Revision Date: Sheet
1
Rev
0B
Wednesday, June 18, 2003
of
20 37
Page 21
AC650 AC97 CODEC
Ver:0B
VCC3
R564
C561
10K
AUD_CLK{7}
AC_SDOUT7,28} AC_BITCLK7,28}
AC_SDIN017,28} AC_SYNC17,28}
AC_RST#{17,28}
AUDIO CODE CD IN HEADERS
103P
R566 10K
R360 22 C369 22P
R565 10
21
C383 104P
XTL_IN XTL_OUT
C363 104P
R349 33
VCC3
+5VR
JSP1
123
YJ103-B
N32-1030071-H06
C17 E_102P
1 2 3 4
5 6 7 8
9 10 11
12
DVDD1 XTL_IN XTL_OUT DVSS1
SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET#
PC_BEEP
R568 0
SPDIFO
4847464544424140394338
NC
NC
TEST6
TEST5
PHONE
AUXL
AUXR
1314151617181920212223
+12V
+
C325
R343
X_4.7K
1 2 1 2
FMIC_IN
12
12
C368 102P
FMIC
C371 105P
SPEAKER_R SPEAKER_L
R369 Reserved for 9760 Stereo MIC
12
12
C375
C374
473P
105P
EC34 ELS10/16-B
+
EC33 ELS10/16-B
12
C339 104P
+5VR
VREF_OUT
FB7 X_80S
+
FB6 X_80S
R369 1K
12
C367
R516
102P
4.7K
U30
37
36
LOUTR
LINL
24
LOUTL
NC NC
VRDA VRAD
AFILT2 AFILT1
NC
VREF
AVSS1
AVDD1
LINR
ALC650-F
35 34
33 32
31 30
29 28 27 26
25
CB6 104P
+5VR
TEST4
TEST2
TEST1
AVSS2
VIDEOL
VIDEOR
CDL
DACOUTR
CDGND
CDR
DACOUTL
MIC1
AVDD2
MIC2
MONO
1 2
LINE_ROUT LINE_LOUT
C382 105P
VREF_OUT
1 2
+5VR
CB7
104P
CT15 X_105P/0805
FMIC
12
C362 104P
104P
EC28
X_10U/16V/S
AUDIO CODE REGULATORS
U24 YLT1087S-0.8A
3 2
VIN VOUT
ADJ
1
R277 100RST
R276
300RST
SPEAKER OUT JACK
LINE_OUTR
LINE_OUTL
C507 E_560P
C508 E_560P
6 7 8
9 17 15
+
J2B
Line-Out
Middle
PJ1X3-BGR
EC26
ELS10/16-B
+5VR
C307 X_104P
CD IN
R531
4.7K
R533
4.7K
CDL
1 2
CDGND
3 4
CD-D1x4-BK-SBTJ
JCD1
CDR
Intel Front Audio Connector
+5VR
E_102PC540
FMIC_IN
1
R532 0
SPEAKER_R LINE_OUTR
SPEAKER_L
12
12
C505
E_102P
MIC
3 4
MICPWR VCC5
5
FLINE OUTR
7
HPON
9 10
FLINE OUTL LINE NEXT L
JAUD1
C506
D2x5-1:3-BK
E_102P
JC-D2-GN
LINE NEXT R
AF1
AG1 JC-D2-GN
GND
C337 105P C336 105P C335 105P
2
6
8
12 12 12
+5VR
LINE_OUTL
CDLX CDGNDX CDRX
C541 104P
C353 105P/0805
C346 105P/0805
1 2
1 2
C349 105P/0805
VREF_OUT
105P/0805
VREF_OUT
C348
12
MIC2
C539 X_103P
R312 X_4.7K
R315 1K
1 2 1 2
R315 Reserved for ALC650 BASS/CENTER
DECOUPLING CAPACITOR
CP12
1 2
CP11
1 2
FB5 X_0
C391 E_104P
R528 33K R529 33K
R313 4.7K
R314 1K
1 2 1 2
MIC2_IN
MIC_IN
C245 X_104P
LINE_R
LINE_L
C253 E_560P
C554 102P
PGND
C555 102P
C252 E_560P
10 11 12 13 18 16
1 2 4 5 3
14
J2C
Line-In
Top
PJ1X3-BGR
J2A
Mic
Bottom
PJ1X3-BGR
Ver:0B
C56222P
YCRY24.576H
C56322P
X3
XTL_IN
R567 1M
XTL_OUT
Micro Star Restricted Secret
Title
AC97 Codec ALC202A/650
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
21 37
Rev
0B
of
Page 22
5
4
3
2
1
RN74
12 34 56
PDDACK#_R
78
8P4R-22
R261 22 R260 22
RN73
8P4R-22
R385 22 R384 22
Q63
DS
NDS7002AS
G
RX2 0
RY2 0
RN75
8P4R-22
RN71
8P4R-22 RN76
8P4R-22 RN78
8P4R-22
R557
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
78 56 34 12
4.7K
SDA0_R
PDA0_RPDA1_I
PDD_14 PDD_0
PDIOW#_R
PDCS#1_R PDCS#3_R
PDD_1
PDD_10PDD10 PDD_4 PDD_11 PDD_3
PDD_7 PDD_8PDD8
PDA2_R PDA0_R PDA1_R
ATADET1_R ATADET0_R
Micro Star Restricted Secret
ATA 33/66/100 Connector
MS-6741
Last Revision Date: Sheet
1
HDDRST#
Rev
0B
Wednesday, June 18, 2003
of
22 37
SDCS#1 SDCS#3
Q45 NDS7002AS
G
SDA1_R
PDA1_R
RX?
RY?
RN79
8P4R-22 RN81
8P4R-22
R299 22 R298 22
RN83
8P4R-22
RN82
8P4R-22
RN84
8P4R-22
RN87
8P4R-22
RN86
8P4R-22
R273
4.7K
R545R544
22
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
SDA2_R PDD_9 IRQ14_R
IRQ15_R
SDCS#1_R SDCS#3_R
SDD_15
SDREQ_R
SDD_3
HDDRST#
Layout Placement11
0B Reserved.
SDA0_I
R556 0
PDA0_I
SDA0_R
R558 0
PDA0_RPDA1_R
2
PDREQ{17} PDIOR#{17} PIORDY{17}
PDDACK#{17}
PDIOW#{17}
PDCS#1{17} PDCS#3{17}
PDA2{17}
PDA0{17}
PDA1{17}
ATADET1{17} ATADET0{17}
13
2
13
2
PDREQ PDREQ_R PDIOR# PDIOR#_R PIORDY PIORDY_R PDDACK#
PDD14 PDD15 PDD_15 PDD0 PDIOW#
PDCS#1 PDCS#3
PDD12 PDD_12 PDD2 PDD_2 PDD13 PDD_13 PDD1
PDD4 PDD11 PDD3
PDD7 PDD6 PDD_6
PDD5 PDD_5
PDA2 PDA0 PDA1
ATADET1 ATADET0
SDA0_I
PDA0_I
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
ATA 33/66/100 Connector
PRIMARY IDE CONN.
R216
D D
HDDRST#{31}
IDEACTP#{29}
HDDRST#
33
PDD_7 PDD_6 PDD_5 PDD_4 PDD_3 PDD_2 PDD_1 PDD_0
PDREQ_R PDIOW#_R PDIOR#_R PIORDY_R PDDACK#_R IRQ14_R PDA1_I PDA0_I PDA2_R PDCS#1_R IDEACTP#
IDE1
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
YJ220-Y-1
PDD_8 PDD_9 PDD_10 PDD_11 PDD_12 PDD_13 PDD_14 PDD_15
ATADET0_R PDCS#3_R
PDD[15..0]{17}
SDD[15..0]{17}
C404 X_473P
PDD[15..0]
SDD[15..0]
SDA0{17} SDA2{17}
IRQ14{17}
SDIOW#{17}
SDDACK#{17}
IRQ15{17}
SDA1{17}
SDCS#1{17} SDCS#3{17}
SDIOR#{17}
SDA0 SDA0_R SDA2 PDD9 IRQ14
SDIOW# SDIOW#_R SDDACK# SDDACK#_R IRQ15 SDA1 SDA1_R
SDD12 SDD_12 SDD14 SDD_14 SDD15 SDIOR# SDIOR#_R
SDD7 SDD_7 SDD8 SDD_8 SDD9 SDD_9 SDD13 SDD_13
RESVD
SDD4 SDD_4
C C
SECONDARY IDE CONN.
R209
HDDRST#
B B
IDEACTS#{29}
33
SDD_7 SDD_6 SDD_5 SDD_4 SDD_11 SDD_3 SDD_12 SDD_2 SDD_1 SDD_14 SDD_0 SDD_15
SDREQ_R SDIOW#_R SDIOR#_R SIORDY_R SDDACK#_R IRQ15_R SDA1_I SDA0_I SDCS#1_R IDEACTS#
IDE2
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
YJ220-Y-1
SDD_8 SDD_9 SDD_10
SDD_13
ATADET1_R SDA2_R SDCS#3_R
C405 X_473P
R544 0
SDA1_I
PDA1_I
SIORDY{17}
SDREQ{17}
13
2
RESVD
SDA1_R
13
R545
VCC
PIORDY_R
SIORDY_R
A A
IDEACTP#
IDEACTS#
IRQ14_R IRQ15_R
R125 4.7K
R126 4.7K
R131 10K
R124 10K
R130 8.2K R123 8.2K
PDREQ_R
SDREQ_R
PDD_7
SDD_7
ATADET0_R
ATADET1_R
R258 5.6K
R122 5.6K
R283 4.7K
R220 4.7K
R404 15K
R405 15K
0
2
SDA1_I
For VT8237 please stuff on (2-3) and RX1&2 For VT8235 please stuff on (1-2) and RY1&2
SDD6 SDD_6 SDD10 SDD_10 SDD11 SDD_11
SIORDY SIORDY_R SDD5 SDD_5 SDD0 SDD_0
SDREQ SDD2 SDD_2 SDD1 SDD_1 SDD3
DS
RX1 0
RY1 0
R556 R558
33
5
4
3
Page 23
5
Fast Ethernet 1-Port PHY
3VDUAL
D D
31
38
42
47
24
13
7
MII_TXD0{18} MII_TXD1{18} MII_TXD2{18} MII_TXD3{18} MII_TXEN{18}
C C
MII_MDC{18}
MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 MII_TXEN
TXCLK RXD0
RXD1 RXD2 RXD3 RXDV RXER
RXCLK CRS
COL MII_MDC
MDIO
17
TXD0
18
TXD1
19
TXD2
20
TXD3
16
TXEN
14
TXER
15
TXC
6
RXD0/PHYAD4
5
RXD1/PHYAD3
4
RXD2/PHYAD2
3
RXD3/PHYAD1
9
RXDV/BYPOSC
11
RXER/ISO
10
RXC
22
CRS/RPTR
21
COL/SYMB
2
MDC
1
MDIO
VDD
VDD
VDDC
VDDTX
VDDRX
VDDPLL
VDDOSC
LED0/TEST#
LED1/SPD100
LED2/DUPLEX
LED3/NWAYEN
INT#/PHYAD0
GNDTXC
GNDRX
GND
GND
GNDC
23
12
8
GNDPLL
GNDTX
GNDOSC
35
36
39
43
44
RX+
TX+
REXT
SD/FXEN
PD#
RST#
VT6103
U20
RX-
TX-
XO
4
3VDUAL
R205 49.9RST
TX-
R204 49.9RST
TX+
R208 49.9RST
RX-
R207 49.9RST
RX+
RX-
32
RX+
33
TX-
40
TX+
41
ACT_LED
26
SP_100
27
R219 10K
28
R227 10K
29 25
R206 6.49KST
37 34 30 48
C246
XI
106P/0805
46
XI
XO
45
C280 22P
3VDUAL
MII_RST# {18}
Y1
25MHZ
C268 22P
3V_LAN
TX+ TX-
RX+ RX-
C257 103P
3VDUAL
C254
104P
C500
X103P
C244
103P
3
FB3 80S
2 1 3
6 8 7
ACT_LED
SP_100
TDC TD+ TD-
RD+ RD­RDC
3V_LAN
U17
CMT
TX+
TX-
RX+
RX-
RXC
TS6121C
2
3VDUAL
R146
R151
10K
10K
3VDUAL
LAN_USB1B
15 16 14
11 9 10
123456
78
RN59
8P4R-75
20 19 16 12 15 11 14 10 13
9 18 17
GREEN­GREEN+
AMBER­AMBER+
LAN_USB+RJ45
TDP TDN RDP NC NC RDN NC NC
1
3VDUAL
MII_RXD3{18} MII_RXD2{18} MII_RXD1{18} MII_RXD0{18}
B B
A A
MII_RXDV{18}
MII_RXCLK{18}
MII_RXER{18}
MII_TXCLK{18}
MII_COL{18} MII_CRS{18}
MII_MDIO{18}
5
MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
MII_RXDV MII_RXCLK
MII_RXER
MII_TXCLK MII_COL
MII_CRS
MII_MDIO MDIO
1
RN68
3
8P4R-33
5 7
R244 33 R245 33
R246 33
R247 33 R240 33
R241 33
R551 33
RXD3
2
RXD2
4
RXD1
6
RXD0
8
RXDV RXCLK
RXER
TXCLK COL
CRS
4
C290 104P
MII_EEDI{18}
MII_EECK{18}
MII_EECS#{18}
C291 104P
MII_EEDI MII_EECK MII_EECS#
C288 104P
C255 104P
EEPROM
3 2 1
6 7
3
C258 104P
U25
DI SK
VCC
CS
GND
NC NC
93C46S
C256
EC21
104P
104P
MII_EEDO
4
DO
8 5
MII_EEDO {18}
VCC3
PGND
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Fast Ethernet / 1-Port PHY
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
23 37
1
Rev
0B
of
Page 24
5
POWER CIRCUIT FOR USB PORT 0,1
FS1
1.5A-miniSMDC200-S
R73
D D
USB_OC#1{16} USB_OC#2{16}
USBN1{16}
USBP1{16}
USBN0{16}
C C
USBP0{16}
USBN3{16}
B B
USBP3{16}
USBN2{16}
USBP2{16}
47K
C338 104P
USBN1
USBP1
USBN0
USBP0
USBN3
USBP3
USBN2
USBP2
R77 56K
KBVCC
+
EC5
C42
EL470/10V-3.5
X_105P
PGND
NEAR USB CONNECTOR
L7
4 3
1 2
L8
4 3
1 2
L11
4 3
1 2
L12
4 3
1 2
X90ohm_0603
X90ohm_0603
X90ohm_0603
X90ohm_0603
POWER CIRCUIT FOR USB PORT 2,3
5V_STR5V_STR
REAR USB PORT
A A
5
4
FS2
1.5A-miniSMDC200-S
USB_D1­USB_D1+
USB_D0­USB_D0+
87
PGND
USB_D3­USB_D3+
USB_D2­USB_D2+
87
PGND
4
R138 47K
C347 104P
R140 56K
214365
CN3
X_8P4C-47P
214365
CN21
X_8P4C-47P
SVCC0
+
EC11
C187
EL470/10V-3.5
X_105P
PGND
NEAR USB CONNECTOR
KBVCC
I1394_USB1A
5 6 7 8
UP
1 2 3 4
DOWN
I1394+USBx2-D20-BK
PGND
SVCC0
CP16 CP5 CP6
LAN_USB1A
5 6 7 8
UP
1 2 3 4
DOWN
LAN_USB+RJ45
PGND
1 2 1 2
3
POWER CIRCUIT FOR USB PORT 4,5
F4
1.5A-miniSMDC200-S
USBN5{16} USBP5{16}
USBN4{16} USBP4{16}
USBN7{16} USBP7{16}
USBN6{16} USBP6{16}
3
C345 104P
R424 47K
R425 56K
FRONT USB PORT
FRONT PANEL USB CONNECTOR FOR USB PORT 4,5
USBN5
USBP5
USBN4
USBP4
FRONT PANEL USB CONNECTOR FOR USB PORT 6,7
USBN7
USBP7
USBN6
USBP6
15 16 17 18 19 20 21 22
12
PGND
21 22 23 24 25 26 27 28
PGND
5V_STR
USB_OC#3{16}
SVCC1
+
C13
C422
E_104P
X_105P
NEAR USB CONNECTOR
12
1 2
1 2
1 2
EC39 EL470/10V-3.5
43
L22 X_90ohm_0805
L21 X_90ohm_0805
4 3
L24
X_90ohm_0805
4 3
L26
X_90ohm_0805
4 3
2
NEAR USB CONNECTOR
NEAR USB CONNECTOR
2
USB_D5­USB_D5+
USB_D4­USB_D4+
214365
USB_D7­USB_D7+
USB_D6­USB_D6+
214365
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
USBP4 USBN4 USBN5 USBP5
USBN0 USBP0 USBN1 USBP1
USBP2 USBN2 USBP3 USBN3
USBP6 USBN6 USBP7 USBN7
INTEL USB 2.0 (Yellow)
SVCC1
87
CN25 X_8P4C-47P
N31-2051131-C09
INTEL USB 2.0 (Yellow)
SVCC1
87
CN26 X_8P4C-47P
Micro Star Restricted Secret
N32-2051091-H06
Rear USB Port
MS-6741
1
8P4R-15K RN102
1 2 3 4 5 6 7 8
8P4R-15K
RN104
1 2 3 4 5 6 7 8
8P4R-15K
RN105
1 2 3 4 5 6 7 8
8P4R-15K
RN114
1 2 3 4 5 6 7 8
JUSB1
12 34 56 78
10
JUSB2
12 34 56 78
10
Last Revision Date: Sheet
1
USB_OC#3
USB_OC#3
Rev
0B
Wednesday, June 18, 2003
of
24 37
Page 25
5
4
3
2
1
Super I/O
VCC
VSS
VSS
VSB
VBAT
102
VBAT
DRVDEN0
INDEX#
MOA#
DSB# DSA#
MOB#
DIR#
STEP#
WRDATA#
WE#
TRACK0#
WP#
RDDATA#
HEAD#
DSKCHG#
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
SLCT
BUSY
ACK#
SLIN#
INIT#
ERR#
AFD# STB#
IRRX
CIRRX
IRTX
DCDA# DSRA#
SINA
RTSA#
SOUTA
CTSA#
DTRA#
RIA# DCDB# DSRB#
SINB
RTSB#
SOUTB
CTSB#
DTRB#
RIB#
CLKIN
PME#
CASEOPEN#
BEEP
OVT#/SMI#
MEMW#/GP52
MEMR#/GP53
ROMCS#/GP54
W83697HF-VB
FLOPPY DISK HEADER
FDD1
U16
PE
DRVDEN0
1
INDEX#
2
MOA#
3
DSB#
4
DSA#
6
MOB#
7
DIR#
8
STEP#
9
WRDATA#
10
WE#
11
TRACK0#
12
WP#
13
RDDATA#
14
HEAD#
15
DSKCHG#
16
PD0
42
PD1
41
PD2
40
PD3
39
PD4
38
PD5
37
PD6
36
PD7
35 29 30 31 32 34 43 33 44 46
IRRX
64 100
IRTX
65
53 48 51 49 52 47 50 54 62 56 59 57
SOUTB
61 55 58 63
17 98 101 118 117
MEMW#
97
MEMR#
96
ROMCS#
95
PD[7..0]
RSLCT {27} RPE {27} RBUSY {27} RACK# {27} RSLIN# {27} RINIT# {27} RERR# {27} RAFD# {27} RSTB# {27}
DCDA# {27} DSRA# {27} SINA {27} RTSA# {27} SOUTA {27} CTSA# {27} DTRA# {27} RIA# {27}
SIO48M {7} CHASISS {26}
BEEP {26}
MEMW# {26} MEMR# {26} ROMCS# {26}
PD[7..0] {27}
R176 X_0
R182 0
THRM#
12 34 56 78
910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334
YJ217-C-1
PCI_PME# {14,17,19,20}
THRM# {5,17,31}
VCC
R144
SOUTB
4.7K
Power-on strap, enable 48MHz
VCC
R183
RXD
X_4.7K
VCC
R184
TXD
X_4.7K
MSI/Intel IR HEADER
JIR1
VCC
1 3 5 6
CUT
NA +5V IRTX IRRX
XJIR1
GND
2
4
IRRXIRTX
VCC3
D D
LPC_REQ#{18}
C C
B B
R410
4.7K
TXD RXD
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 XA17 XA18
28 19 21 20 27
26 25 24 23
125 123 128 121 126 124 127 122 120 119
106 103 104 112 111 110 109 105 108 107
116 114 115 113
94 93 92 91 89 88 87 86
85 84 83 82 81 80 79 78 77 76 74 73 72 71 70 69 68 67 66
LRESET# LCLK SERIRQ LDRQ# LFRAME#
LAD0 LAD1 LAD2 LAD3
GPBX/GP13 GPAY/GP15 GPAS1/GP10 GSAS2/GP17 GPAX/GP12 GPBY/GP14 GPBS1/GP11 GPBS2/GP16 MSO/GP50 MSI/GP51
VREF VTIN2 VTIN1 AGND
-5VIN
-12VIN +12VIN AVCC +3.3VIN VCORE
FANPWM1 FANIO1 FANPWM2 FANIO2
XD0/GP20 XD1/GP21 XD2/GP22 XD3/GP23 XD4/GP24 XD5/GP25 XD6/GP26 XD7/GP27
XA0/GP30 XA1/GP31 XA2/GP32 XA3/GP33 XA4/GP34 XA5/GP35 XA6/GP36 XA7/GP37 XA8/GP40 XA9/GP41 XA10/GP42 XA11/GP43 XA12/GP44 XA13/GP45 XA14/GP46 XA15/GP47 XA16/GP55 XA17/GP56 XA18/GP57
PCIRST1#{12,20,31}
PCICLK6{7}
SERIRQ{17}
LPC_FRAME#{18}
LPC_AD0{18} LPC_AD1{18} LPC_AD2{18} LPC_AD3{18}
VREF{26} VTIN2{26} VTIN1{26}
-5VIN{26}
-12VIN{26} +12VIN{26} VAVCC{26}
VCC3
VCORE
FANPWM1{26}
FANIO1{26} FANIO2{26}
XD[7..0]{26}
XD[7..0]
XA[17..0]
XA[17..0]{26}
XA18{26,31}
VCC3 VCC 5VSB
5
457599
22
VCC
VCC
VCC3
SIO
VSS
186090
5VSBVBAT
VCC
Distribute near the VCC power pin of the LPC
VCC
A A
C228
104P
C394 104P
C212 104P
VCC3
C238 104P
C236 104P
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
Winbond W697HF
MS-6741
C234 105P
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
C194 104P
of
25 37
Rev
0B
Page 26
5
4
3
2
1
Hardware Monitor
XA[17..0]
XA18{25,31} MEMR# {25}
XD3 XD2 XD1 XD0 XD7 XD6 XD5 XD4
D D
C C
B B
VREF
VREF
+12V
-12V
-5V
FANPWM1{25}
R187
10KST
R607
30KST
R190 28KST R191 232KST R181 120KST
R9
X_470
RT1
YT103SC-1N
SMD
THERMDA_CPU
R15 10K
R186 10KST
R10 1K
Q4
X_NDS7002AS
SYSTEM Therm al
R188 56KST
R5 X_4.7K
X_SI2303DS
VTIN2 {25}
THERMDA_CPU {5}
CPU Thermal
VTIN1 {25}
R189 56KST
VREF
+12V
Q3
VCC
+12VIN {25}
-12VIN {25}
-5VIN {25}
VREF {25}
+
EC2 X_ELS10/16V-B
RESVD
L13 X_08S/0805
135
7
RN120
8P4R-0
246
8
1 2
R8
4.7K
CFAN1
3 2 1
YJ103-BO
D1 1N4148S
A C
21
CP4
R51
27K
VAVCC
C237 104P
R53 10K
VAVCC {25}
FANIO1 {25}
XA[17..0]{25} XD[7..0] {25}
SYSTEM ROM
XA0
12
XA1
11
XA2
10
XA3 XA4 XA5 XA6 XA7 XA8
27
XA9
26
XA10
23
XA11
25
XA12 XA13
28
XA14
29
XA15 XA16 XA17
XA18
VCC
ROMCS# MEMR# MEMW#
R180 X_0
R179
4.7K
RN65 8P4R-4.7K
7 8 5 6 3 4 1 2 7 8 5 6 3 4 1 2
RN61 8P4R-4.7K
7 8 5 6 3 4 1 2
RN67 8P4R-4.7K
30
U19
A0 A1 A2
9
A3
8
A4
7
A5
6
A6
5
A7 A8 A9 A10 A11
4
A12 A13 A14
3
A15
2
A16 A17
1 22
A18 CE#
BIOS-SOCKET
VCC
VCC
OE#
PGM#
GND
D0 D1 D2 D3 D4 D5 D6 D7
XD[7..0]
XD0
13
XD1
14
XD2
15
XD3
17
XD4
18
XD5
19
XD6
20
XD7
21
VCC
CB31
C242 104P
32
ROMCS#
24 31 16
MEMR# MEMW#
X_106P/0805
R185
4.7K
ROMCS# {25} MEMW# {25}
VCC
CPU FAN
+12V
D11 X_1N4148S
R325
A C
4.7K
SFAN1
3
A A
EC29
+
X_ELS10/16V-B
2 1
YJ103-BO
R326
27K
R324 10K
FANIO2 {25}
SYSTEM FAN
5
4
3
Chasiss Intrusion Header
VBAT VCC
R177
JCI1
XYJ102
2M
1 2
CHASISS {25}
2
R415 10K
BEEP{25}
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
Hardware Monitor
B
MS-6741
Q48 2N3904S
E C
Last Revision Date:
Wednesday, June 18, 2003
Sheet
26 37
1
ALARM {29}
Rev
0B
of
Page 27
5
LPT / COM PORTS
R132 4.7K
PRND7 PRND6 PRND5 PRND4
PRND3 PRND2 PRND1 PRND0
KBGND
RSTB# PRND0 PRND1 RINIT# PRND2 PRND3 PRND4 PRND5 PRND6 PRND7 RACK# RBUSY RPE RSLCT
1 2 3 4 5 6 7 8
9 10 11 12 13
1 3 5 7 1 3 5 7
RN39 8P4R-33
RN35 8P4R-33
2 4 6 8 2 4 6 8
RERR#
RACK# RBUSY RPE RSLCT
RINIT# RSLIN# RSTB# RAFD#
PRND0 PRND1 PRND2 PRND3 PRND4 PRND5 PRND6 PRND7PD7
RERR#{25}
RACK#{25}
D D
C C
B B
RBUSY{25}
RSLCT{25}
RINIT#{25}
RSLIN#{25}
RSTB#{25}
RAFD#{25}
PD[7..0]{25}
For EMI
RSLCT RPE RBUSY RACK#
RERR# RAFD# RSTB# RSLIN#
PRND0 PRND1 PRND2 PRND3
PRND4 PRND5 PRND6 PRND7
RINIT#
RPE{25}
PD[7..0]
PD0 PD1 PD2 PD3 PD4 PD5 PD6
21 43 65 87
21 43 65 87
21 43 65 87
21 43 65 87
KBGND
CN12 8P4C-180P
CN17 8P4C-180P
CN15 8P4C-180P
CN14 8P4C-180P
C162 180P
4
D6
AC
VCC
-12V
RTSA#{25} DTRA#{25}
SOUTA{25}
1 2 3 4 6 7 8 9510 1 2 3 4 6 7 8 9510
51
52
14 15 16 17 18 19 20 21 22 23 24 25 48
KBGND
RAFD# RERR#
RSLIN#
LPT1 N51-25F0041-F02
1N4148S
RN34 10P8R-4.7K
RN32 10P8R-4.7K
C145
X_104p
VCC
C120
104P
NRTSA NDSRA# NCTSA# NRIA#
NRIA# NCTSA# NDSRA# NSINA NDCDA#
RTSA# DTRA# SOUTA
3
D4 1N4148S
CN7
8P4C-180P
U10
20
VCC
2
RIN1
3
RIN2
4
RIN3
7
RIN4
9
RIN5
16
DIN1
15
DIN2
13
DIN3
11
GND
75232-1
-12VC +12VC
21 43 65 87
ROUT1 ROUT2 ROUT3 ROUT4 ROUT5
DOUT1 DOUT2 DOUT3
+12V
NDCDA# NSOUTA NSINA NDTRA
KBGND
+12VC
1
V+
V-
19 18 17 14 12
5 6 8 10
C122
8P4C-180P
104P
CN9
RIA# CTSA# DSRA# SINA DCDA#
NRTSA NDTRA NSOUTA
-12VC
D3 1N4148S
21 43 65 87
RIA# {25} CTSA# {25} DSRA# {25} SINA {25} DCDA# {25}
2 1
X_80S/0805
KBGND
2
NDCDA#
NSINA NSOUTA NDTRA
1 2 3 4 5
11 10
NDSRA#
6
NRTSA
7
NCTSA#
8
NRIA#
9
COM1 COM-D9-GN
1
KBGND
C144 X_104P
CP17
1 2
L9
CP3
12
CP1 CP2
1 2 1 2
KBGND
Keyboard/Mouse Ports
MSDAT#{16} MSCLK#{16}
KBDAT#{16} KBCLK#{16}
MSDAT#
A A
KBDAT# MSCLK# KBCLK#
5
MSDAT# MSCLK#
KBDAT# KBCLK#
RN1
1 2 3 4 5 6 7 8
8P4R-4.7K
L2 301S L5 301S
L4 301S L6 301S
KBVCC
R20 330
KBGND
21 21
21 21
XKBCLK1 XMSCLK1 XKBDAT1 XMSDAT1
XMSDAT1
XMSCLK1
XKBDAT1 XKBCLK1
1 2 3 4 5 6 7 8
4
CN1
8P4C-180P
STACKED PS2 CONNECTOR
JKBMS1
KBGND
7
8 11 12
1
2
5
6
MS
KB
YMD12P-1
10
9 4
3
KBGND
KBVCC
KBGND KBGND
1 2
CP15
3
C9
X_39P
C8 X_104P
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
LPT / COM Port
MS-6741
Last Revision Date: Sheet
1
Wednesday, June 18, 2003
27 37
Rev
0B
of
Page 28
5
CNR Riser / DELD
4
3
2
1
D D
5VSB
-12V
C C
VCC3
VCC3
SMBCLK1{7,8,17,18,31}
AC_SYNC{17,21} AC_SDOUT{17,21} AC_BITCLK{17,21}
B B
SMBCLK1
CNR1
B1
MII_MDIO
B2
MII_COL
B3
MII_TXCLK
B4
GND1
B5
MII_RXER
B6
MII_TXD3
B7
GND2
B8
MII_TXD1
B9
MII_TXEN
B10
GND3
B11
MII_RXD2
B12
MII_RXD0
B13
GND4
B14
RESV6
B15
+5VDUAL
B16
USB_OC#
B17
GND5
B18
-12V
B19
+3.3VD
B20
GND6
B21
EE_DOUT
B22
EE_SHCLK
B23
GND7
B24
SMB_A0
B25
SMB_SCL
B26
PRIMARY_DN#
B27
GND8
B28
AC97_SYNC
B29
AC97_SDATA_OUT
B30
AC97_BITCLK
YSLOT60
MII_MDC
MII_CRS
GND9
MII_RXDV
MII_RXCLK
GND10 MII_TXD2 MII_TXD0
GND11
LAN_CLK MII_RXD1 MII_RXD3
USB+
GND12
USB­+12V
GND13
+3.3VDUAL
+5VD
GND14
EE_DIN
EE_CS SMB_A1 SMB_A2
SMB_SDA
AC97_RESET#
RESV12 AC97_SDATA_IN1 AC97_SDATA_IN0
GND15
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
3VDUAL
+12V
VCC
VCC3
AC_RST#
C553
X_104P
SMBDATA1 {7,8,17,18,31} AC_RST# {17,21}
AC_SDIN1 {17} AC_SDIN0 {17,21}
Micro Star Restricted Secret
A A
Title
CNR Riser
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
http://www.msi.com.tw
2
MS-6741
Last Revision Date: Sheet
Wednesday, June 18, 2003
28 37
1
of
Rev
0B
Page 29
5
4
3
2
1
FRONT PANEL
VCC
R398
FP_RST#
D24 1N4148S D13 1N4148S
D12 1N4148S
C399
E_181P
330
C401 104P
A C A C
A C
D D
FP_RST#{7,31}
C C
HDDLED
For MSI / Intel Front Panel
HDD+ PLED1
HDDLED
PLED2 PLED1
ALARM{26}
SPKR{17}
SATAACT# {18} IDEACTP# {22}
IDEACTS# {22}
ESD Protect
JFP2
1
HDD+
3
HDD-
5 6
RESET- PWSW+
7
RESET+
9
NC
JFP1 JFP1
1 2
GND SPEAKER
3
SLED
5
PLED
JFP2
R420
B
2.2K
E C
Q49 2N3904S
VCC3 VCC
2
PLED
4
SLED
8
PWSW-
4
BUZ+
6
BUZ-
8
VCCSPK
R416 220/0805
PLED2
R394 100
VCC
SPK
C403
SPK SPK2
104P
PLED1 {31} PLED2 {31} PWBTIN# {17}
C400 104P
R419
0
VCC
BUZZER BZ1
POWER OK Circuits
Power On Sequence.
PSON#
PS_OUT#
PW_OK
EN_DDR
EN_VDDA_25
EN_VCORE
PG_VCORE
EN_VDD_12_A
CPU_GD
ALL_PWRGD
C509
C510
C511
104P
104P
104P
B B
VCC2_5
VCC3
C98
VCC
104P
5VSB +12V
VCC
R98
4.7K
C127 104P
PW_OK
PW_OK {31}
3
3.3V
3.3V
GND GND GND
5V_SB
VCC3
1 2 3 4
5V
5 6
5V
7 8 9 10
12V
JWR1
11
3.3V
-12V
PS_OUT#{31} PS_ON#A{5}
A A
R31 0
5
PS_OUT#
-5V
VCC
12 13 14 15 16 17 18 19 20
-12V GND PS_ON GND GND GND
-5V 5V 5V
ATX-PCON
4
PW_OK
ALL_PWRGD{18,31}
R149
330
-LDTRST{11}
ALL_PWRGD
VSUS2_5
1 2
147
U3A
74LVC07S
147
3 4
U3B
74LVC07S
2
VSUS2_5
R46 330
-CPURST {5}
JHT1
1 2
X_YJ102
R48 X_100
Reserved for Hyper-Transport Reset Test .
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
Micro Star Restricted Secret
Power OK Circuits
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
of
29 37
Rev
0B
Page 30
5
4
3
2
1
K8 Voltage Regular Module
D D
VCC
C560
22PC27
COREFB_L{5}
PG_VCORE
C23 562P
R41 1KST
VDIFF
IDROOP
COREFB_H{5}
X_104P
VID4 VID3 VID2 VID1 VID0
COMP FB_ISL
FS_ISL
24
3 4 5 6 7
22 23
9
10
12 11
R464
4.7K
VCC
R628 270K
VCORE_EN#
VID[4..0]{5}
C585 X_104P
R37 10KST
R44 0
R617 10K
VCORE GND
R619 154KST
COMP1
R14 51RST
VCORE_EN#{31}
C C
PG_VCORE{31}
VCC
Droop Compensation
+12V
U5 ISL6569CB
I32-6569B02-I11
EN VID4
VID3 VID2 VID1 VID0 PGOOD
FS/DIS
COMP
FB
VDIFF IDROOP
CHOK1 1.1uH/25A
C590 X_39p/50V
VCC
16
VCC
18
GND
15
GND
1
GND
20
PWM1
21
ISEN1
19
PWM2
17
ISEN2
8
OFS
2
OVP
13
VSEN
14
RGND
OFS : Voltage up offset , 1K Ohm =10mV
ISEN1
ISEN2
OFS
CB1 105P/0805
R13 3KST
R38 3KST
Offset Adjustment
CT4 820u/25V
R50 0
CT10 820u/25V
+12V
R49
5.1/0805
VDD_P0
CB2 105P/0805-25V
+12V
R620
5.1/0805
VDD_P1
CB32 105P/0805-25V
VDD_12_VRM
CT12 820u/25V
14
3
PWM1
1
5 9
6
PWM2
2
CT16 820u/25V
U6A HIP6602B_#A
I33-6602B03-I11
VCC
BOOT1
PHASE1
GND
PWM1
U6B
PVCC U_G2
BOOT2
PHASE2
PGND
PWM2
HIP6602B_#B
C179
C84
475P/1206-16V
475P/1206-16V
PBT1
U_G1
12
U_G1
11
R616
4.7
13
L_G1 L_G1A
4
L_G1
PBT2
10
R621
4.7
8
L_G2
7
L_G2
BOOT1
C36 104P
BOOT2
C37 104P
R135
2.2/0805
R83
2.2/0805
R99 0/0805R45 51RST
R117 0/0805
U_G1A
PHASE1
U_G2AU_G2
PHASE2
L_G2A
CB5 105P/0805/16V
DS
G
Q20 09N03/DPACK
DS
G
DS
G
DS
G
Q19 06N03
CB4 105P/0805/16V
Q10 09N03/DPACK
Q14 06N03
R629
X_2.2
C35 X_102P
R630
X_2.2
C38 X_102P
L_G1A
L_G2A
DS
Q52 06N03
G
DS
Q53 06N03
G
CHOK2
0.8u-20%
CHOK3
0.8u-20%
VCORE
0.8V~1.55V/42A
B B
VID4 VID3 VID2 VID1 VID0 Vout 1 1 1 1 0 0.800 1 1 1 0 1 0.825 1 1 1 0 0 0.850 1 1 0 1 1 0.875 1 1 0 1 0 0.900 1 1 0 0 1 0.925 1 1 0 0 0 0.950
R14 ORIGNAL 154KST R11-1543T13-Y01
POWER FREQENCY ADIUSTING
R11-0304T13-Y01300KRST
VID4 VID3 VID2 VID1 VID0 Vout 0 1 1 1 0 1.200 0 1 1 0 1 1.225 0 1 1 0 0 1.250 0 1 0 1 1 1.275 0 1 0 1 0 1300 0 1 0 0 1 1.325 0 1 0 0 0 1.350
0 0 1 1 1 1.3751 0 1 1 1 0.975 1 0 1 1 0 1.000 1 0 1 0 1 1.025
A A
1 0 1 0 0 1.050 1 0 0 1 1 1.075 1 0 0 1 0 1.100 1 0 0 0 1 1.125 1 0 0 0 0 1.150 0 1 1 1 1 1.175
5
0 0 1 1 0 1.400
0 0 1 0 1 1.425
0 0 1 0 0 1.450
0 0 0 1 1 1.475
0 0 0 1 0 1.500
0 0 0 0 1 1.525
0 0 0 0 0 1.550
1 1 1 1 1 Shutdown
4
VCORE
CT2
1500U/6.3V
CT9 1500U/6.3V
MOSFET Heat-Sink
60MIL
+12V
C25
104P
Near to Vcore Input-Chock ( CHOK1 )
CT5 1500U/6.3V
CT11 1500U/6.3V
JPW1
3
4
D2x2
RT2
YT472S-1N
2
VCC
U42A LM393_#A
I72-LM39303-T07
84
3
+
2
-
U42B LM393_#A
I72-LM39303-T07
84
5
+
6
-
R622
Q76
2N7002S
1
Q77
2N7002S
7
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
X270KST
R626
X300KST
Micro Star Restricted Secret
VCC
FS_ISL
K8 CORE POWER
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
C591 X104P/X7R
30 37
of
Rev
0B
CT7 1500U/6.3V
CT13 1500U/6.3V
GND
12V
GND
12V
CT8 1500U/6.3V
CT17 1500U/6.3V
1
2
3
VCC
R624 2KRST
4.64KST
2.8KRST
R623
1.82KST
R625
R627
Page 31
8
3VSB MODE SELECT
3VSB MODE DUAL MOSFET
D D
C C
SINGLE MOSFET
VDIMM LINEAR OR PWM SELECT
VDIMM MODE
LINEAR REGULATOR
PWM REGULATOR
FRONT PANEL RESET BUTTON PCIRST# INPUT
PCIRST# BUFFER OUTPUT
3VDLDEC# PULL LOW PULL HIGH
EXTRAM PULL LOW PULL HIGH
PCI SOLT PCIRST# BUFFER OUTPUT
VDDA_25
VDDA_25 To CPU Copper trace width > 50mils .
R32 4.7K
SUSB#{14,17}
THE TWO BLOCK CHOICE ONE SUPPORT SYSTEM POWER CONTROL
B B
To CPU Copper trace width > 250mils , Fill island behind DIMM > 400mils .
B
DDR_VTT 1. 25V
VREF1
VOUT
VINVREF2
GND
VDD_25_SUS
18 2 3 4
R593
5VSB
7 6 5
C575 C0.1U16Y
U40
ENABLE VCNTL BOOT_SEL
W83310DS
7
PLED1{29}
PLED2{29}
2N3904S
R577
4.7K
FP_RST#{7,29}
PCIRST#{14,16} HDDRST#{22} PCIRST1#{12,20,25}
PG_VCORE{30}
VCORE_EN#{30}
1.25VREF{33} PCIRST2#{19}
VCC3
VDDA_25
CLOSE TO CHIP
5VSB
CE
Q1 2N3904S
Ic=200mA Vebo=6V Vceo=40V
R33
4.7K
PS_OUT#{29}
PS_IN#
CD100U16EL11
5VSB
DDR TERMINATION
R590 100R
100R
VTT_DDR_SUS
12
12
+
+
EC61
EC60
1000U/6.3V
1000U/6.3V
5VSB
R569
330
2N3904S
Q65
VCC3
Q64
EC52
C576 C0.1U16Y
R571
4.7K
5VSB
R573
330R
R575
4.7K
VCC3
VCC
R578
R579
330
330
VCC
12
+
C569 475P/0805
R34 1K
C54 104P
5VSB
DDR AND DDR II VOLT SELECT
DDRTYPE PULL LOW PULL HIGH
5VSB
5VSB
C570 104P
C571 104P
R587 R588 4.7K
R574
R576
R570
X_1KR
R572
10K
X_1KR
10K
10 11 12
5VSB
VDIMM
2.5V
1.8V
3VDLDEC#
EXTRAM
1
FP_RST#
2
PCIRST#
3
HDD_RST#
4
DEV_RST#
5
VDD_GD
6
VDD_EN
7
1.25VREF
8
VCC5
9
SLOT_RST# VCC3
2.5VDDA AGND0
C573 474P-X7R
X_4.7KR
6
C582 102P
48
1314151617181920212223
C574 104P
I2C_CLK
CPU_PWGD
CHIP_PWGD
PLED1/EXTRAM
PLED0/3VDLDEC#
PSIN#
PSOUT#
MEMBTSS5VSB
R591
2.2KR1%
X_C1U16Y0805
5
4
3
2
1
LINEAR MODE
R375
VSUS2_5
R47
4.7K
C0.1U16Y
3738394041424344454647
S3#
S5#
GND
5VSB
PWR_OK
RSMRST#
I2C_DATA
CHRPMP
5VUSB_DRV
VAGP_DRV VAGP_SEN
WD_DET
1.2VLDT_DRV
1.2VLDT_SEN TMP_FAULT#
DDRTYPE
VDIMM_LSEN
VDIMM_LDRV
VDIMM_HSEN
VDIMM_HDRV
3VSB_SEN
3VSB_DRV
24
P3055LD
G
R592
1KR1%
G
C577
VCC3
R7
THESE OUTPUT AND INPUT PIN MUST
4.7K
BE PULL HIGH
CPU_GD {5} ALL_PWRGD {18,29} SMBCLK1 {7,8,17,18,28} SMBDATA1 {7,8,17,18,28} RSMRST# {18} SUSC# {17} SUSB# {14,17} PW_OK {29}
5VSB
C564
AGND1
5V_DRV
WATCHING DOG TIMER SELECT
Q38
Q39
C1 C2
VCC3
S
D D
P3055LD
S
+
U39
36 35 34 33 32 31 30 29 28 27 26 25
MS-6
WD_DET
PULL HIGH
EC55
+
VDD_25_SUS
EC65 1000U/6.3V
C2 X_102P
C565
C0.1U16X
5VSB_DRV 5V_DRV
R582 X10K
5VSB
1000U/6.3V
EC56
+
1000U/6.3V
CHARGE PUMP VOLTAGE
9VSB
OUTPUT
C567
105P/0805
R583 10K
C583 102P
TIMER
OFFPULL LOW ON
THE VDIMM_HSEN IN LINEAR MODE
DDRTYPE
DDR DDR II
DDR 2.5V
THIS POINT VOLT CAN'T SETTING BELOW 2.9V
CPU PWR_GD OUTPUT CHIP PWR_GD OUTPUT I2C BUS I2C BUS CONNECT TO SOUTH BRIDGE RSMRST# SIGNAL SOUTH BRIDGE POWER CONTROL(SLP_S4# OR SUSB#) SIGNAL SOUTH BRIDGE POWER CONTROL(SLP_S3# OR SUSC#) SIGNAL ATX POWER OK INPUT
VCC
C566 X_C2200P16X C568 X_C2200P16X
R580
XA18 {25,26}
X_0
THRM# {5,17,25}
CONNECT TO CPU
THE TWO MODE ONLY ONE MODE PRESENT
SINGLE MODE DUAL MODE
THIS MODE SELECT BY PIN 47 PULL HIGH 5VSB
VDIMM_HSEN VREF
C586
3VDUAL
X_102P
2.0V
1.7V
3VDUAL
12
+
EC58
CD470U10EL11.5
3VDUAL
10K
5VSB
Q43
8
1
7
2 3
6
4 5
NN-P07D03LV_SO8
G
Q67 45N03
D S
G
VCC3
Q22
4 5 3
6 7
2
8
1
NN-P07D03LV_SO8
+
EC54 1000U/6.3V
3VSB REGULATE BY 5VSB AND VCC3
5V_DRV 3VSB_DRV
12
+
EC59
CD470U10EL11.5
VDD_12_A
Routed as pour to CPU width > 250mils .
THIS MODE SELECT BY PIN 47 PULL LOW
VCC3
Q44
1 2 3 4 5
NN-P07D03LV_SO8
VCC3
RSMRST# {18}
C390 105P
+
1000U/6.3V
EC47
5V_DUAL
5V_STR
D
Q37 P3055LD
VDDQ
S
VDDQ
EC43
+
1000U/6.3V
VDD_12_A
5VSB 8 7 6
+
EC57 1000U/6.3V
A A
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
8
7
6
5
4
3
2
http://www.msi.com.tw
ACPI POWER CONTOLLER (MS-6)
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
31 37
of
Rev
0B
Page 32
5
4
3
2
1
BULK / Decopuling
VCORE
D D
C557 226P/1206
CPU
Place on inside of CPU Cavity ( 5 *
0.22uF/0603 X7R high-freq decoupling Cap. )
C C
VCORE
106P/1206
B B
VCORE
Buck-decoupling Mid-Freq. decoupling Cap. ( 7 * 4.7uF / 1206 X7R )
106P/1206
C97
C89
C558 226P/1206
C128
C79 224P
106P/1206
106P/1206
C91
C105
224P
224P
C92
C86 106P/1206
Place on CPU Solder side
VCORE
C437
C99
X_0.22u/BOT
224P
C108
224P
X_107P/B
X_107P/B
C438
C435
C73 X_0.22u/BOT
X_104P/BOT
VCORE
C429
X_104P/BOT
VDD_25_SUS
C154 104P
VDDQ
C250
104P
VDDQ
C281
105P/0805
VCC2_5
C318
X_104P
VCC2_5
C217
105P/0805
VCORE
C445
X_104P/BOT
C428
X_104P/BOT
C46 104P
C191
104P
C189
105P/0805
C261
X_104P
C327
105P/0805
C448
VDD_12_A
C447
X_104P/BOT
C201
C87
104P
X_104P
K8T400M
C278
C199 105P
104P
C204 X_104P
C240
X_105P/0805
C443 X_104P/BOT
VCC3
DDR
C208 X_104P
C451 X_104P/BOT
C326 X_104P
For EMI
VCC3
C388
C330
X_104P
X_104P
VCC3
C402 X_104P
VCC
SYSTEM
5VSB VCC
C271
C4
104P
104P
VCC3
3VDUAL
C24 X_104P
C419 X_104P
C265 104P
C259 104P
C275
C273
104P
104P
+12V -12V
C3
104P
C355 X_104P
C67
C41 104P
C361 104P
VCC
VCC3
-5V
C366 X_104P
C321 X_104P
C359 104P
104P
C95
C334
104P
C136
104P
VCC3
VCC
C102 X_104P
C224 X_104P
C393
X_104P
VCC3
VCC2_5
C323 X_104P
C266 X_104P
VCC3
C5 E_104P C6 E_104P C7 E_104P C10 E_104P C11 E_104P C12 E_104P
VSUS2_5
12
+
VCC
+
EC24
ELS10/16-B
EC27 X_1000U/6.3V
VCC3
EC17
+
1000U/6.3V
VTT_DDR_SUSVDD_25_SUS
C168
X_104P
+
X_1000U/6.3V
EC31
LAYOUT: Locate close to Clawhammer socket.
A A
VTT_DDR_SUS
+
+
C171
C33
X_100u-16V
X_100u-16V
GND
5
VTT_DDR_SUS
EC19
EL470/10V-3.5
12
+
LAYOUT: Place one 1210 10uF capacitor on each end of the VTT island.
VTT_DDR_SUS
12
12
+
CT6 ELS10/16V-B
4
+
CT14 X_ELS10/16V-B
GND
VDD_25_SUS
+
+
EC9
EC6
EL470/10V-3.5
3
X_EL100/16V-2.5
2
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan http://www.msi.com.tw
BULK / Decopuling
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
32 37
1
Rev
0B
of
Page 33
System Voltage Regulator
9VSB
R594 1K
1.25VREF{31}
1.25VREF
103P
C578
R597
110RST
84
3
+
2
-
R596 120RST
U41A LM358_#B
VCC3
EC66
+
1000U/6.3V
D
Q74 P3055LD
1
G
Dual Layout Footprint
S
VCC2_5
+
VCC2_5=1.25X(R596+R597)/R597
EC16 EL470/10V-3.5
3VDUAL
VT8235 Suspend 2.5V power
1
2
A C
D15 1N4001S
3 5 7
VSUS2_5 VSUSNB
C28 104P
A C
D22 X_1N4148S
D23 SC431L
RN89
4
8P4R-0
6 8
R537 100RST
2
R538
3 1
499RST
K8M800 used.
R599
1.25VREF
1K
C581
X_103P
VDD=VCC1_5
9VSB
U41B
84
LM358_#B
5
+
6
-
R600
R601
100RST
499RST
7
105P/0805
G
C220
VCC2_5
D
S
Q75 P3055LS
VDD
+
EC15 EL470/10V-3.5
K8T800 used.
8 6 4 2
K8M800 used.
VDD=VCC2_5
7
VDDVCC2_5
5 3 1
RN119 8P4R-0
RN118 0/0805/B
VDD=VCC1_5
R608
VDDVDDQ
0/B R609 0/B R610 0/0805/B R611 0/0805/B
Title Document Number
Micro Star Restricted Secret
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
System Voltage Regulators
MS-6702
Last Revision Date:
Wednesday, June 18, 2003
Sheet
33 37
of
Rev
0D
Page 34
5
K8 CPU Power
4
NB & SB & AGP Power
3
2
1
Other Power
DDR SideCPU Side
K8 Vcore -> "VCORE" (42A)
D D
VDDA_2.5 Power -> "VDDA_25" (0.11A)
DDR Power -> "VDD_25_SUS" (9.5A)
DDR-VTTPower ->
HT Power -> "VDD_12_A"&"VLDT0"
"VTT_DDR_SUS" (5.21A)
NB & SB Core-Power
-> "VCC2_5" (?A)
NB & SB Core-Suspend Power -> "VSUS2_5" (?A)
NB AGP8X Power -> "VDDQ" (1.5A)
5VDU
3VDU
DDR_3VDUAL
9VSB
(2A)
ATX Power Supply
VSUS2_5
-> SB
C C
+5VSB
5VDUAL 3VDUAL
VCC
P3VA -> For 1394
Charge Pump
-> 9VSB
B B
+12V
VCORE -> K8 CPU
+5VR -> Audio
DDR_25_SUS
-> DDR
DDR_3VDUAL
VDDA_25 -> K8 CPU(I/O)
VCC3
VDDQ
A A
-> AGP
VTT_DDR_SUS
-> DDR
-12V
5
VCC2_5 -> NB & SB ( VLINK )
4
VDD_12_A
-> HT
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
3
2
http://www.msi.com.tw
Power Generation
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
1
34 37
Rev
0B
of
Page 35
5
4
3
2
1
T2
1 2
X_YJ102
FM22
5 6 7 8
5 6 7 8
5 6 7 8
X
X_FM
Impedance Test
T1
1 2
X_YJ102
FM5
FM23
X
X
X_FM
X_FM
MH7
X_150 Drill / 300 Pad
1 2 3 4
MH4
X_150 Drill / 300 Pad
1 2 3 4
(NPTH)
9
(NPTH)
5 6 7 8
5 6 7 8
PGND
9
D D
PCB1
U8_1
U14_1
MSI
DDR
CPU Retention
P01-674100C-C48
P01-674100B-C48
VBAT1_1
YSKTBT
C C
B B
FM12
X
FM17
X
X_FM
X_FM
FM3
FM16
X
X_FM
X
X_FM
HEATSINK
FM13
FM10
X
X
X_FM
X_FM
FM20
FM9
X
X_FM
X
X_FM
HS2
TO252MOS_Heatsink
E31-0500261-K08
FM14
FM18
X
X
X_FM
FM6
FM7
X
X
X_FM
X_FM
X_FM
HS1
TO252MOS_Heatsink
E31-0500261-K08
FM19
FM2
X
X
X_FM
FM8
FM11
X
X
X_FM
X_FM
X_FM
MH6
X_150 Drill / 300 Pad
1 2 3 4
MH5
X_150 Drill / 300 Pad
1 2 3 4
MH3
X_150 Drill / 300 Pad
1 2 3 4
(NPTH)
(NPTH)
(NPTH)
FM21
X
X_FM
FM15
X
X_FM
5 6 7 8
9
5 6 7 8
9
5 6 7 8
9
VCC
FM1
X
X_FM
FM4
X
X_FM
MH2
X_150 Drill / 300 Pad
1 2 3
(NPTH)
4
MH8
X_150 Drill / 300 Pad
1 2 3
(NPTH)
4
MH1
X_150 Drill / 300 Pad
1 2 3
(NPTH)
4
FM24
X
X_FM
9
9
9
KBGND
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
Manual Parts
MS-6741
Last Revision Date:
Wednesday, June 18, 2003
Sheet
35 37
1
Rev
0B
of
Page 36
5
4
3
2
1
Revision Initial ver:0A on 09/09/2002
Revision Initial ver:0B on MS-6707
P-7 U22 change from CY28330 to CY28331 nee to more pciclk
P-11 NB K8T400M ver change from 0.4 to 0.9 J18 need to pull down to gnd P-14 PWM change from 2 phases to 3 phases circuit change P-15 To add 105p cap to Vref_cg
D D
P-18 remove MII LAN interfase P-22 modify codec circuit remove some connectors P-25 Change lan to RTL8101L P-32~P35 ACPI circuit modify
0A Revision History (Changes from MS-6707 Rev 0B)
Sheet
16~18
23
Change South Bridge from VT8235 to VT8237.
Change Lan Controler from RTL8101L to VT6103 PHY.
Desciption
Ap. Date
11/18
12/04
Add One Front Port USB Connector.
24
Add one VGA Connector for K8M400 Reserved.
15
C C
Reserved C-MEDIA AC'97 Codec Circuit.
21
Add CNR Riser Circuit.
28 11/22
Change Power Sequence Solution.
31
11/18
12/04
12/04
0B Revision History (Changes from MS-6741 Rev 0A)
Sheet
-LDTSTOP must be connect to SB DPSLP# for NB Rev:CD
18
and connect to SLP# for NB Rev:CE & K8M400.
Add PDA0 & SDA0 Isolated.
22
B B
Add VT8237 CTL_PLED1# Reseved for S5 Control.
17
Remove R100,D5,Q2,C15,R29
29
Desciption
Change Pull-Up Power form +12V to VCC on R465.
30
Change D28 to a Resistor connect to VCC. Add Resistor Capacitors back on Address
and Control Signals for AMD Request.
Add Crystal and AC filter to avoid that
21 04/01
CNR Problem.
Ap. Date
01/03
01/03
01/03
01/17
01/17
01/2209
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
History
MS-6741
1
Last Revision Date:
Wednesday, June 18, 2003
Sheet
36 37
of
Rev
0B
Page 37
5
VT8235CE
4
3
2
1
D D
C C
R544(1-2) 0 R545(1-2) 0 R556(1-2) 0 R558(1-2) 0
VT8237CD
R544(2-3) 0 R545(2-3) 0 R556(2-3) 0 R558(2-3) 0
U19_X W49F002UP
U27_X
VIA
R524(2-3) 0 R524(1-2) 0
K8M800
U14_X
VT8237CD
K8M800
VT8237CD
U19_Y
W29C040P-90
B B
K8M800
1 3 5 7
R250_X 665RST
2 4 6 8
RN89_X 8P4R-100
Micro Star Restricted Secret
A A
Title
Manual Parts
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
http://www.msi.com.tw
2
MS-6741
Last Revision Date: Sheet
Wednesday, June 18, 2003
37 37
1
of
Rev
0B
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use