MSI MS-6599 Schematics
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4
3
2
1
D
D
HARAPPA-7
CPU :
Chip Set :
Remarks :
C
Project Name:EAGLE
PBA Name :
PCB Code :
BA41-10003A
Dev. Step :MP
Revision :
B
TR DATE :12/19/2001
1.1
Pentium 4 478 pin/Northwood
BROOKDALE(i845)
uATX/DDR DRAM
Revision History
Rev
Date
Description
Sheet
C
Parts
B
DRAW CHECK
S.P.Lee
A
4
12/19/2001 12/19/2001 12/19/2001
3
J.G.Lim
APPROVAL
H.J.Hwang
A
SAMSUNG
ELECTRONICS
2
1
SAMSUNG PROPRIETARY
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4
3 2
1
DD
C
B
2001/11/27 MP1.0
2001/12/07 MP1.1
Cap.s for ICT Test
A
SAMSUNG
ELECTRONICS
C
B
A
4
3
12
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4
3
12
D
GENERIC BYPASS
1 SITE PER SSO IN
EVERY 3-4 ALONG TRACE
SHOULD BE ON DEVICE PG
EVERY 3-4 ALONG TRACE
SPECIFIC DEVICE DECOUPLESPECIFIC DEVICE DECOUPLE
SHOULD BE ON DEVICE PG
BETWEEN MCH AND DIMM
D
DDR Signal Termnation deCAP
C
GENERIC PLANE BYPASS
1 SITE PER 4SQ IN
PLACE MCH
B
C
B
A
GENERIC PLANE BYPASS
1 SITE PER 4SQ IN
4
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2
1
A
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4
3
2
1
D
C
B
D
C
B
A
SAMSUNG
ELECTRONICS
4
3
2
1
A
SAMSUNG PROPRIETARY
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4
3
2
1
D
C
B
D
C
B
A
SAMSUNG
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4
3
2 1
A
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4
3
2
1
D
C
B
D
C
B
A
SAMSUNG
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4
3
2
1
A
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23
1
D
C C
B B
D
A
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3
12
A
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4
3
2
1
D D
C
B
A A
SAMSUNG
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C
B
3
2
14
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34 1
2
D
C
B
D
C
B
A
SAMSUNG
ELECTRONICS
3
24
1
A
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34 1
2
D
C
B
D
C
B
2.2K
A A
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4
3
2
1
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4
3
2 1
D
(GPIO13)
(GPIO12)
C
_GPIO33
_GPIO34
B
D
C
B
*
A
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ELECTRONICS
4 2
3
1
A
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4
3
2
1
D
C
B
D
C
B
A
SAMSUNG
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4
3 1
2
A
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