MSI MS-6597 Schematics
Cover Sheet 1
Block Diagram
AMD 462pins SocketA CPU - Power 4
1
2
3AMD 462pins SocketA CPU - Signals
(MS-6597)
Nvidia (R) Crush11(nForce IGP 64) + MCP2/2H Chipset
Version: 0C
AMD Althon/Duron/Morgan/Palomino Socket 462 Processor
CRUSH11 - Host Signals 5
CRUSH11 - Memory Signals 6
CRUSH11 - AGP , LDT Signals & PLL DELAY 7
CRUSH11 - Power & CPU VID Select
MCP2 - CPU & PCI & LDT & IDE Signals
8
9
CPU:
AMD Duron/Morgan/Athlon & XP Processor
System Chipset:
Nvidia nForce IGP 64 (North Bridge)
MCP2/2H Wep (South Bridge)
MCP2 - MAC & USB & LPC & AC'97 Signals
10
On Board Chipset:
LPC I/O - W83627HF
11
BIOS -- LPC EEPROM
AC97 Audio
A A
LAN & LPC Flash EEPROM
DDR System Memory
12
13
14
AC'97 Codec -- ALC202A
LPC Super I/O -- W83627HF-AW
LAN -- ICS1893 PHY
I1394 -- FW803 PHY
AGP 1.5V Slot, LDT Regulator & COM2 15
Expansion Slots:
PCI Slots
16
AGP2.0 SLOT (1.5V) * 1
ATA33/66/100 IDE & Video Connectors
FAN & USB Connectors
I1394 PHY & Connectors
17
18
19
PCI2.2 SLOT * 3
PWM Controller:
L6911D
ATX & Front Panel
ACPI (MS5) Controller
VRM 9.0 - L6911D
GPIO
Power Delivery Map & MANUAL
Revision History 1
20
21
22
23
24
25
ACPI:
1
MS5
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
COVER SHEET
(MS-6597)
125Wednesday, September 04, 2002
of
0B
1
VRM 9.0
L6911D
Single Phase
PWM
AGP 1.5V
Connector
Analog
Video
(66MHz)
4X w/Fast Wri t e
462-Pin Socket Process or
K7 FSB
(100/133MHz)
CRUSH 11
64bit DDR
(200/266 MHz)
Block Diagram
2 DDR
DIMM
Modules
(1+1)
Out
LDT Link
(200 MHz)
IDE Primary
UltraDMA 33/66/100
PCI CNTRL
PCI Slot 1
PCI Slot 2
PCI Slot 3
IDE Secondary
MCP-2
A A
USB Port 0
PCI ADDR/DATA
PCI (33MHz)
USB Port 1
USB Port 2
USB Port 3
USB
(48MHz)
LPC Bus
(24MHz)
USB Port 4
USB Port 5
ALC202A
AC'97 Codec
10/100BaseT
ICS1893
AC'97 Link
MII
(14.318MHz)
(2.5/25 MHz)
(33MHz)
Flash
LPC SIO
W83627HF-AW
Keyboard
Mouse
1
Floopy Parallel Serial
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
BLOCK DIAGRAM
(MS-6597)
225Monday, August 05, 2002
of
0B
8
SDATA#[0..63]{5}
D D
C C
B B
DICLK#[0..3]{5}
DIVAL#{5}
DOCLK#[0..3]{5}
AIN#[2..14]{5}
A A
AICLK#{5}
CFWDRST{5}
CONNECT{5}
PROCRDY{5}
8
SDATA#0
SDATA#1
SDATA#2
SDATA#3
SDATA#4
SDATA#5
SDATA#6
SDATA#7
SDATA#8
SDATA#9
SDATA#10
SDATA#11
SDATA#12
SDATA#13
SDATA#14
SDATA#15
SDATA#16
SDATA#17
SDATA#18
SDATA#19
SDATA#20
SDATA#21
SDATA#22
SDATA#23
SDATA#24
SDATA#25
SDATA#26
SDATA#27
SDATA#28
SDATA#29
SDATA#30
SDATA#31
SDATA#32
SDATA#33
SDATA#34
SDATA#35
SDATA#36
SDATA#37
SDATA#38
SDATA#39
SDATA#40
SDATA#41
SDATA#42
SDATA#43
SDATA#44
SDATA#45
SDATA#46
SDATA#47
SDATA#48
SDATA#49
SDATA#50
SDATA#51
SDATA#52
SDATA#53
SDATA#54
SDATA#55
SDATA#56
SDATA#57
SDATA#58
SDATA#59
SDATA#60
SDATA#61
SDATA#62
SDATA#63
DICLK#0
DICLK#1
DICLK#2
DICLK#3
DOCLK#0
DOCLK#1
DOCLK#2
DOCLK#3
DOVAL#
AIN#0
AIN#1
AIN#2
AIN#3
AIN#4
AIN#5
AIN#6
AIN#7
AIN#8
AIN#9
AIN#10
AIN#11
AIN#12
AIN#13
AIN#14
FILVAL#
AA35
W37
W35
Y35
U35
U33
S37
S33
AA33
AE37
AC33
AC37
Y37
AA37
AC35
S35
Q37
Q35
N37
J33
G33
G37
E37
G35
Q33
N33
L33
N35
L37
J37
A37
E35
E31
E29
A27
A25
E21
C23
C27
A23
A35
C35
C33
C31
A29
C29
E23
C25
E17
E13
E11
C15
A13
C21
A21
E19
C19
C17
A11
A17
A15
W33
J35
E27
E15
AN33
AE35
C37
A33
C11
AL31
AJ29
AL29
AG33
AJ37
AL35
AE33
AJ35
AG37
AL33
AN37
AL37
AG35
AN29
AN35
AN31
AJ33
AJ21
AL23
AN23
AJ31
7
CPU SIGNAL BLOCK
U13A
SDATA0
SDATA1
SDATA2
SDATA3
SDATA4
SDATA5
SDATA6
SDATA7
SDATA8
SDATA9
SDATA10
SDATA11
SDATA12
SDATA13
SDATA14
SDATA15
SDATA16
SDATA17
SDATA18
SDATA19
SDATA20
SDATA21
SDATA22
SDATA23
SDATA24
SDATA25
SDATA26
SDATA27
SDATA28
SDATA29
SDATA30
SDATA31
SDATA32
SDATA33
SDATA34
SDATA35
SDATA36
SDATA37
SDATA38
SDATA39
SDATA40
SDATA41
SDATA42
SDATA43
SDATA44
SDATA45
SDATA46
SDATA47
SDATA48
SDATA49
SDATA50
SDATA51
E9
SDATA52
SDATA53
C9
SDATA54
A9
SDATA55
SDATA56
SDATA57
SDATA58
SDATA59
SDATA60
SDATA61
SDATA62
SDATA63
SDATAINCLK0
SDATAINCLK1
SDATAINCLK2
SDATAINCLK3
SDATAINVAL
SDATAOUTCLK0
SDATAOUTCLK1
SDATAOUTCLK2
SDATAOUTCLK3
SDTATOUTVAL
SADDIN0
SADDIN1
SADDIN2
SADDIN3
SADDIN4
SADDIN5
SADDIN6
SADDIN7
SADDIN8
SADDIN9
SADDIN10
SADDIN11
SADDIN12
SADDIN13
SADDIN14
SADDINCLK
CLKFWDRST
CONNECT
PROCRDY
SFILLVAL
N12-4620011-F02
**All CPU interface are 2.5V tolerant**
7
PICD0/BYPASSCLK
PICD1/BYPASSCLK
SYSVREFMODE
PLLBYPASSCLK
PLLBYPASSCLK
Part 1
462-Pin Socket
A20M
FERR
INTR
IGNNE
RESET
STPCLK
PWROK
PICCLK
COREFB-
COREFB+
CLKIN
CLKIN
RSTCLK
RSTCLK
K7CLKOUT
K7CLKOUT
ANALOG
VREF_SYS
PLLBYPASS
PLLMON1
PLLMON2
PLLTEST
SCANCLK1
SCANCLK2
SCANINTEVAL
SCANSHIFTEN
DBRDY
DBREQ
FLUSH
TCK
TDO
TMS
TRST
VID0
VID1
VID2
VID3
VID4
FID0
FID1
FID2
FID3
SCHECK0
SCHECK1
SCHECK2
SCHECK3
SCHECK4
SCHECK5
SCHECK6
SCHECK7
SADDOUT0
SADDOUT1
SADDOUT2
SADDOUT3
SADDOUT4
SADDOUT5
SADDOUT6
SADDOUT7
SADDOUT8
SADDOUT9
SADDOUT10
SADDOUT11
SADDOUT12
SADDOUT13
SADDOUT14
SADDOUTCLK
6
INIT
NMI
SMI
6
5
4
3
2
1
CPU PULL-UP / DOWN BLOCK
A20M#
AE1
FERR#
AG1
CPUINIT#
AJ3
INTR
AL1
IGNNE#
AJ1
NMI
AN3
CPURST#
AG3
SMI#
AN5
STPCLK#
AC1
R29 22
AE3
C49 X_10p
APICCLK_CPU
N1
APICD0#
N3
APICD1#
N5
COREFB#
AG13
COREFB
AG11
CPUCLK_R
AN17
CPUCLK#_R
AL17
AN19
AL19
CLKOUT
AL21
CLKOUT#
AN21
AJ13
VREFMODE
AA5
VREF_SYS
W5
ZN
AC5
ZN
ZP
TDI
AE5
AJ25
AN15
AL15
AN13
AL13
AC3
S1
S5
S3
Q5
AA1
AA3
AL3
Q1
U1
U5
Q3
U3
L1
L3
L5
L7
J7
W1
W3
Y1
Y3
U37
Y33
L35
E33
E25
A31
C13
A19
J1
J3
C7
A7
E5
A5
E7
C1
C5
C3
G1
E1
A3
G5
G3
E3
ZP
PLLBP#
PLBYCLK
PLBYCLK#
PLLMON1
PLLMON2
PLLTEST#
SCANCLK1
SCANCLK2
SINTVAL
SSHIFTEN
DBREQ#
FLUSH#
CPU_TCK
CPU_TDI
CPU_TMS
CPU_TRST#
VIDA0
VIDA1
VIDA2
VIDA3
VIDA4
FID0
FID1
FID2
FID3
AOUT#2
AOUT#3
AOUT#4
AOUT#5
AOUT#6
AOUT#7
AOUT#8
AOUT#9
AOUT#10
AOUT#11
AOUT#12
AOUT#13
AOUT#14
A20M# {9}
FERR# {9}
CPUINIT# {9}
INTR {9}
IGNNE# {9}
NMI {9}
CPURST# {5,9}
SMI# {9}
STPCLK# {9}
CPU_OK
APICCLK_CPU {5}
APICD0# {9}
APICD1# {9}
AOCLK# {5}
CPU_OK {20,21}
VIDA[0..4] {11,22}
FID[0..3] {5}
AOUT#[2..14] {5}
5
NMI
INTR
SMI#
CPUINIT#
STPCLK#
A20M#
IGNNE#
CPURST#
PLLTEST#
DBREQ#
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R15 510
R19 510
1 2
3 4
5 6
7 8
RN12
510
RN3
680
RN6
680
VCORE
VCORE
AIN#0
AIN#1
PLLMON1
PLLMON2
FLUSH#
PLLBP#
CPU_OK
FERR#
SCANCLK2
SSHIFTEN
SINTVAL
SCANCLK1
FILVAL#
DOVAL#
X_4.7u-0805(S/S)C598 R42 10K
R101 680
R95 680
R52 56
R44 56
R20 680
R90 680
R7 680
R115 270
R109 270
RN13
1 2
3 4
5 6
7 8
270
COREFB
4.7u-0805(S/S)C600
COREFB#
VCORE
R48 0X_4.7u-0805(S/S)C601
PLBYCLK
PLBYCLK#
VREFMODE
R65 100
R64 100
R57 100
R54 100
R34 X_1K
R36 56.2RSTR31 270
VREFMODE=Low=No voltage scaling
VCOREVCORE
Put in Solder
CPU SYSCLK BLOCK CPU K7CLKOUT BLOCK
CPUCLK{5}
CPUCLK_R
CPUCLK#_R
CPUCLK#{5}
680pC89 R67 X_60.4RST
R68
X_301RST
680pC105
R69 X_60.4RST
CLOSE SOCKET462
VCORE
CPU SYSCLK REFERNCE BLOCK
VCORE
C59
0.047u
R50
110RST
R49
110RST
VREF_SYS
0.5 * VCORE
C64
10u-0805
C58
0.1u
CLOSE SOCKET462
4
CPU Clock Multiplier
FID2
1 2
FID1
FID0
FID3
3 4
5 6
7 8
RN4
4.7K
CFID[3:0] => CPU Clock Multiplier
CPU ZN / ZP BLOCK
ZN
R39 40.2RST
ZP
R38 56.2RST
CLOSE SOCKET462
match the transmission line
Push-pull compensation circuit
MSI
Title
Size Document Number Rev
3
Date: Sheet
VCORE
CLKOUT
CLKOUT#
* Trace lengths of CLKOUT and
CLKOUT# are between 2" and
3"
R78 100
R77 100
R74 100
R73 100
CPU APIC BLOCK
VCORE
APICD0#
APICD1#
APICCLK_CPU
R11 220
R13 220
R174 X_453RST
MICRO-STAR INt'L CO., LTD.
AMD Socket462 CPU (Signal)
(MS-6597)
2
VCORE
VCORE
VCORE
VCORE
VCORE
VCC2_5
0B
325Monday, August 05, 2002
of
1
8
PLACE ONE CAP
CLOSE TO PIN M8
H12
H16
H20
H24M8P30R8T30V8X30Z8AB30
D D
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VCC_SRAM1
VCC_SRAM2
VCC_SRAM3
VCC_SRAM4
VCC_SRAM5
VCC_SRAM6
VCC_SRAM7
VCC_SRAM8
VCC_SRAM9
VCC_SRAM11
VCC_SRAM13
VCC_SRAM14
VCC_SRAM16
VCC_SRAM17
VCC_SRAM19
VCC_SRAM20
VCC_SRAM21
VCC_SRAM22
VCC_SRAM23
VCC_SRAM24
VCC_SRAM25
VCC_SRAM26
VCC_SRAM27
VCC_SRAM28
VCC_SRAM29
VCC_SRAM30
VCC_SRAM31
KEY4
KEY6
KEY8
KEY10
KEY12
KEY14
KEY16
KEY18
VSS1
VSS2
VSS3
VSS4
H14
H18
H22
H26
M30P8R30T8V30X8Z30
VSS5
VCC_CORE6
VSS6
AD30
AD8
AF10
AF28
AF30
AF32
AF6
AF8
AH30
AH8
AJ9
AK8
AL9
AM8
F30
F8
H10
H28
H30
H32
H6
H8
K30
K8
C C
B B
AJ7
AL7
AN7
G25
G17
G9
N7
Y7
AG7
AG15
AG29
PLACE ONE CAP
CLOSE TO PIN P8
VCC_CORE7
VSS7
VCC_CORE8
VSS8
VCC_CORE9
VSS9
AF14
VCC_CORE10
VCC_CORE11
VCC_CORE12
VCC_CORE13
VSS10
VSS11
VSS12
VSS13
AB8
AF12
7
CPU VOLTAGE BLOCK
AF18
AF22
AF26
AM34
AK36
AK34
AK30
AK26
AK22
AK18
AK14
AK10
AL5
AH26
AM30
AH22
VCC_CORE14
VCC_CORE15
VCC_CORE16
VCC_CORE17
VCC_CORE18
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
VCC_CORE27
VCC_CORE28
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS25
VSS26
VSS27
VSS28
VSS29
AF16
AF20
AF24
AM36
AK32
AK28
AK24
AK20
AK16
AK12
AK4
AK2
AH36
AM32
AH34
AH32
6
AH18
AH14
AH10
AH4
AH2
AF36
AF34
AD6
AM26
AD4
AD2
AB36
AB34
AB32Z6Z4Z2X36
X34
AM22
X32V6V4V2T36
VCC_CORE29
VCC_CORE30
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
462-Pin Socket
Part 2
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
AH28
AH24
AH20
AH16
AH12
AF4
AF2
AD36
AD34
AD32
AB6
AB4
AB2
Z36
Z34
Z32X6AM28X4X2
V36
V34
T34
T32R6R4R2AM18
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VSS54
VSS55
VSS56
VSS57
V32T6T4T2R36
5
VCC_CORE56
VCC_CORE57
VSS58
VSS59
R34
AM24
P36
VCC_CORE58
VCC_CORE59
VCC_CORE60
VCC_CORE61
VSS60
VSS61
VSS62
VSS63
R32P6P4P2M36
P34
P32M4M6M2K36
VCC_CORE62
VCC_CORE63
VSS64
VSS65
M34
VCC_CORE64
VCC_CORE65
VCC_CORE66
VSS66
VSS67
VSS68
M32K6K4K2AM20
VCC_CORE67
VSS69
K34
VCC_CORE68
VSS70
K32H4H2
VCC_CORE69
VCC_CORE70
VSS71
VSS72
H36
H34
4
AM14
F36
F34
F32
F28
F24
F20
F16
F12
D32
D28
AM10
D24
D20
D16
D12D8D4D2B36
VCC_CORE71
VCC_CORE72
VCC_CORE73
VCC_CORE74
VCC_CORE75
VCC_CORE76
VCC_CORE77
VCC_CORE78
VCC_CORE79
VCC_CORE80
VCC_CORE81
VCC_CORE82
VCC_CORE83
VCC_CORE84
VCC_CORE85
VCC_CORE86
VCC_CORE87
VCC_CORE88
VCC_CORE89
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
F26
F22
F18
F14
F10F6F4F2AM16
D36
D34
D30
D26
D22
D18
D14
D10D6B34
3
VCCA_PLLVCORE
0 ~ 100 mA (50mA)
2.25 ~ 2.75 V
B32
AM2
B28
B24
B20
B16
B12B8B4
AJ5
AC7
AJ23
U13B
N12-4620011-F02
VCC_Z
VCC_A
AA31
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VCC_CORE94
VCC_CORE95
VCC_CORE96
VCC_CORE97
VCC_CORE98
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
AM12
B30
B26
B22
B18
B14
B10B6B2
NC1
VCC_CORE99
VCC_CORE100
VCC_CORE101
VSS101
VSS102
VSS103
AM4
AK6
BP0_CUT
BP1_CUT
BP2_CUT
BP3_CUT
VSS104
AM6
NC2
NC3
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC42
NC43
NC44
NC45
AE7
AC31
AE31
AG23
AG25
AG31
AG5
AJ11
AJ15
AJ17
AJ19
AJ27
AL11
AN11
AN9
G11
G13
G27
G29
G31
J31
J5
L31
N31
Q31
S31
S7
U31
U7
W31
W7
Y31
Y5
AG19
G21
AG21
G19
AN27
AL27
AN25
AL25
VSS_Z
2
U13C
AO1
GND
AO2
GND
AO3
GND
AO4
GND
YY1
GND
YY2
GND
YY3
GND
YY4
GND
YY5
GND
YY6
GND
YY7
GND
YY8
GND
YY9
GND
YY10
GND
N12-4620011-F02
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
YY24
YY23
YY22
YY21
YY20
YY19
YY18
YY17
YY16
YY15
YY14
YY13
YY12
YY11
XX1
XX2
For 1.5GHz CPU Fan Holes
C24
X_1000p
VCCA_PLL trace length from the regulator to
the PGA must less be 0.75"
THERMDP# {11}
THERMDN# {11}
Place all filters close to the PGA
Keep all power and signal trace away from
the regulator
Place a cut in GND plane aro un d th e
VCCA_PLL regulator circuit
CPU DECOUPLING CAPACITORS
C103
X_0.1u
C152
0.1u
C151
X_0.1u
C75
0.1u
C147
X_0.1u
C106
0.1u
C99
0.1u
C55
0.1u
C102
0.1u
C116
0.1u
C20 0.1u
C107 0.1u
C213 0.1u
VCC2_5
C6
0.1u
C17
X_0.1u
C22
0.1u
C347
0.1u
C26
X_0.1u
VCC5
C146
39p
1 2
3 4
5 6
7 8
RN16
100
2.50V Reference
C138
39p
VR1
SC431CSK
VCORE VCORE VCOREVCORE VCORE VCORE
C97
39p
C98
39p
C169
39p
C31
39p
C180
39p
C127
39p
C85
39p
C176
39p
C45
A A
39p
C161
39p
C181
39p
C192
X_39p
C50
39p
C142
39p
C587
X_39p(S/S)
C586
X_39p(S/S)
C611
X_39p(S/S)
C591
X_39p(S/S)
C592
X_39p(S/S)
C593
X_39p(S/S)
C594
X_39p(S/S)
C595
X_39p(S/S)
C599
X_39p(S/S)
Put around inside plane of SocketA
on Bottom side
EMI Decoupling
C597
X_39p(S/S)
C602
X_39p(S/S)
C613
X_39p(S/S)
C605
X_39p(S/S)
C606
X_39p(S/S)
C607
X_39p(S/S)
C608
X_39p(S/S)
VCORE VCORE
C609
X_39p(S/S)
C610
X_39p(S/S)
C614
X_39p(S/S)
C615
X_39p(S/S)
C588
X_39p(S/S)
C596
X_39p(S/S)
C620
X_39p(S/S)
C622
X_39p(S/S)
C621
X_39p(S/S)
C618
X_56p(S/S)
C590
X_56p(S/S)
C604
X_56p(S/S)
C616
X_56p(S/S)
C619
X_56p(S/S)
C603
56p(S/S)
C617
X_56p(S/S)
C589
X_56p(S/S)
C612
X_56p(S/S)
C123
X_0.1u
C150
0.1u
C68
0.1u
C100
0.1u
C80
0.1u
C154
0.1u
C144
0.1u
C117
0.1u
C61
0.1u
C101
0.1u
VCC5 VCC3
C242 0.1u
C12 0.1u
C529 0.1u
C10 0.1u
C60
0.1u
C145
0.1u
C63
X_0.1u
C125
X_0.1u
C148
0.1u
C90
0.1u
C94
0.1u
C149
X_0.1u
C74
X_0.1u
C62
0.1u
VCC3 VCORE
VCC5 VCORE
Put inside SocketA
8
7
6
5
4
3
CPU PLL VOLTAGE BLOCK
(40mils trace / 60 mils space)
VCC_PLL
2
3 1
L6 80-0805
R91
0
R97
C157
X_0
0.1u
Used when spec changed
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
2
2.5V
Max 150 mA
Design for 100 mA
C137
1000p
EC14
4.7u-0805
C131
39p
AMD Socket462 CPU (Power)
(MS-6597)
425Wednesday, September 04, 2002
1
C124
39p
VCCA_PLL
0B
of
8
7
6
5
4
3
2
1
SYSTEM DATA-IN-CLK NOISE L/C BLOCKCRUSH 11 HOST SIGNA LS
SDATA#[0..63]{3}
D D
C C
B B
R190 10RST
CPURST#{3,9}
SDATA#0
SDATA#1
SDATA#2
SDATA#3
SDATA#4
SDATA#5
SDATA#6
SDATA#7
SDATA#8
SDATA#9
SDATA#10
SDATA#11
SDATA#12
SDATA#13
SDATA#14
SDATA#15
SDATA#16
SDATA#17
SDATA#18
SDATA#19
SDATA#20
SDATA#21
SDATA#22
SDATA#23
SDATA#24
SDATA#25
SDATA#26
SDATA#27
SDATA#28
SDATA#29
SDATA#30
SDATA#31
SDATA#32
SDATA#33
SDATA#34
SDATA#35
SDATA#36
SDATA#37
SDATA#38
SDATA#39
SDATA#40
SDATA#41
SDATA#42
SDATA#43
SDATA#44
SDATA#45
SDATA#46
SDATA#47
SDATA#48
SDATA#49
SDATA#50
SDATA#51
SDATA#52
SDATA#53
SDATA#54
SDATA#55
SDATA#56
SDATA#57
SDATA#58
SDATA#59
SDATA#60
SDATA#61
SDATA#62
SDATA#63
CPU_FBO
CPU_FBI
AA3
AA2
AA6
AA4
AC5
AB3
AB2
AG2
AG3
AF3
AH5
W6
Y3
W2
W4
V4
V6
Y5
Y4
U6
W5
U4
V2
R6
T2
P6
R3
R2
U5
T6
T5
T4
V3
U3
N2
P4
N4
M6
M3
L6
H4
H5
K6
J2
N3
P3
P5
N5
M2
M4
J4
J6
G4
D1
E3
D3
C1
E2
A1
C2
J3
H6
G5
G2
G3
D2
F3
F5
K2
L3
U7A
CRUSH 11
SDATA0#
SDATA1#
SDATA2#
SDATA3#
SDATA4#
SDATA5#
SDATA6#
SDATA7#
SDATA8#
SDATA9#
SDATA10#
SDATA11#
SDATA12#
SDATA13#
SDATA14#
SDATA15#
SDATA16#
SDATA17#
SDATA18#
SDATA19#
SDATA20#
SDATA21#
SDATA22#
SDATA23#
SDATA24#
SDATA25#
SDATA26#
SDATA27#
SDATA28#
SDATA29#
SDATA30#
SDATA31#
SDATA32#
SDATA33#
SDATA34#
SDATA35#
SDATA36#
SDATA37#
SDATA38#
SDATA39#
SDATA40#
SDATA41#
SDATA42#
SDATA43#
SDATA44#
SDATA45#
SDATA46#
SDATA47#
SDATA48#
SDATA49#
SDATA50#
SDATA51#
SDATA52#
SDATA53#
SDATA54#
SDATA55#
SDATA56#
SDATA57#
SDATA58#
SDATA59#
SDATA60#
SDATA61#
SDATA62#
SDATA63#
CPUCLKFB_OUT
CPUCLKFB_IN
CPU_RST#
NC
NC
NC
CRUSH11
PART 1
HOST INTERFACE
SADDIN2#
SADDIN3#
SADDIN4#
SADDIN5#
SADDIN6#
SADDIN7#
SADDIN8#
SADDIN9#
SADDIN10#
SADDIN11#
SADDIN12#
SADDIN13#
SADDIN14#
SADDINCLK#
SDATAINCLK0#
SDATAINCLK1#
SDATAINCLK2#
SDATAINCLK3#
SDATAINVAL#
CPUFID0
CPUFID1
CPUFID2
CPUFID3
CPU_VREF1
CPU_VREF2
SADDOUT2#
SADDOUT3#
SADDOUT4#
SADDOUT5#
SADDOUT6#
SADDOUT7#
SADDOUT8#
SADDOUT9#
SADDOUT10#
SADDOUT11#
SADDOUT12#
SADDOUT13#
SADDOUT14#
SADDOUTCLK#
SDATAOUTCLK0#
SDATAOUTCLK1#
SDATAOUTCLK2#
SDATAOUTCLK3#
CPU_CLKFWDRST
CPU_CONNECT
CPU_PROCRDY
APICCLK_CPU
APICCLK_MCP
SYSCLK
SYSCLK#
AD2
AB6
AD4
AD3
AC4
AB5
AD6
AE5
AC6
AB4
AF4
AE4
AG4
AC3
W3
R4
K3
F2
AE6
L5
K5
K4
L4
H3
AF5
B2
A2
C4
B4
F4
C6
B3
A5
C7
D6
B5
A4
D7
C5
Y6
T3
N6
G6
AG6
AF6
AG5
AH2
AH4
AE3
AE2
AIN#2
AIN#3
AIN#4
AIN#5
AIN#6
AIN#7
AIN#8
AIN#9
AIN#10
AIN#11
AIN#12
AIN#13
AIN#14
SAICLK#
SDICLK#0
SDICLK#1
SDICLK#2
SDICLK#3
FID0
FID1
FID2
FID3
CPUREF1_NB
CPUREF_NB
AOUT#2
AOUT#3
AOUT#4
AOUT#5
AOUT#6
AOUT#7
AOUT#8
AOUT#9
AOUT#10
AOUT#11
AOUT#12
AOUT#13
AOUT#14
DOCLK#0
DOCLK#1
DOCLK#2
DOCLK#3
ACLK_CPU
ACLK_MCP
CCLK
CCLK#
DIVAL# {3}
AOCLK# {3}
CFWDRST {3}
CONNECT {3}
PROCRDY {3}
R191 22C269 10p
R197 22
R183 10RST
C260 15p
R182 10RST
C255 15p
AIN#[2..14] {3}
FID[0..3] {3}
AOUT#[2..14] {3}
DOCLK#[0..3] {3}
APICCLK_CPU {3}
APICCLK_MCP {9}
CPUCLK {3}
CPUCLK# {3}
SAICLK#
SDICLK#0
SDICLK#1
SDICLK#2
SDICLK#3
CPUREF1_NB
VDDQ MEM_STRVDDQ MEM_STR MEM_STR
SLP_S3#{10,21}
L25 10nH L22 10nH
L23 10nH L16 10nH
L17 10nH L11 10nH
L15 10nH L10 10nH
L13 10nH L8 10nH
SICLK#
SICLK#0
SICLK#1
SICLK#2
CLK must less DATA 1.5inchs
REFERNCE VOLTAGE BLOCK
Set PO_VREF to
50% of VCORE
C194
1000p
C193
0.1u
R161
110RST
R162
110RST
Crush 11 Decoupling Capacitors
C403
0.1u
C371
0.1u
C370
0.1u
C404
0.1u
U24A
X_74LCX14-SOIC14
1 2
(3VDUAL) (3VDUAL)
C369
0.1u
C307
0.1u
C368
0.1u
C405
0.1u
SLP_S3 DLY_S3
C230 5p
C219 5p
C198 5p
C195 5p
C188 5p
CPUREF_NB
C243
0.1u
C256
0.1u
C232
0.1u
C160
0.1u
S3 Delay Block
R501 0
R506 X_8.2K
C582
X_0.01u
DICLK#0
DICLK#1
DICLK#2
DICLK#3SICLK#3
Set PO_VREF to
50% of VCORE
C247
1000p
C129
0.1u
C308
0.1u
C221
0.1u
C197
0.1u
U24B
X_74LCX14-SOIC14
3 4
R511 X_0
AICLK# {3}
DICLK#[0..3] {3}
VCOREVCORE
C263
0.1u
C324
0.1u
C292
0.1u
C314
0.1u
R184
110RST
R187
110RST
DLY_S3# {11}
BELONG TO CLKFWD GROUP[SADDIN] MATCH W/IN +/-10MILS OF GROUP 5/15, CLK:10/30
A A
BELONG TO CLKFWD GROUP[SADDOUT] MATCH W/IN +/-10MILS OF GROUP 5/15, CLK:10/30
BELONG TO CLKFWD GROUP;MATCHED TO INDIVIDUAL CLKFWD GROUP
RESPECTIVELY.[SDATA0], [SDATA1], [SDATA2],[SDATA3] W/IN+/-10MILS OF GROUP
8
7
6
MSI
Title
Size Document Number Rev
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Crush11 Host Signals
(MS-6597)
2
525Wednesday, September 04, 2002
0B
of
1
8
7
}
7
6
5
4
3
2
1
CRUSH 11 MEMORY SIGNALS
B7C9B11
C13C8B8
C11
C12
B13
B14
D19
B20
C14
C16
D17
D18
C21
C22
C24
C26
C19
B22
C25
B25
B26
B28
B31
A31
C27
C28
B30
C33
D33
F33
G32
K33
E33
F32
J33
J32
L32
N32
U32
V32
K32
M32
V33
W33
W32
AA33
AE33
AF32
Y32
AA32
AD32
AE32
AH33
AL34
AP34
AL32
AG33
AG32
AN34
AN33
MDQ_A0
MDQ_A1
MDQ_A2
MDQ_A3
MDQ_A4
MDQ_A5
MDQ_A6
MDQ_A7
MDQ_A8
MDQ_B4
MDQ_B4
MDQ_B5
MDQ_B5
MDQ_B6
D10
MDQ_B6
MDQ_B7
D11
MDQ_B7
MDQ_B8
F11
MDQ_B8
MDQ_A9
MDQ_B9
D12
MDQ_B9
MDQ_A10
MDQ_B10
F14
D15
MDQ_B10
MDQ_B11
MDQ_A11
MDQ_A12
MDQ_B11
MDQ_B12
E12
MDQ_B12
MDQ_A13
MDQ_B13
F12
D14
MDQ_B13
MDQ_B14
MDQ_A14
MDQ_A15
MDQ_B14
MDQ_B15
E14
MDQ_B15
MDQ_A16
MDQ_A17
MDQ_A18
MDQ_A19
MDQ_A20
MDQ_A21
MDQ_A22
MDQ_A23
MDQ_A24
MDQ_A25
MDQ_A26
MDQ_A27
MDQ_A28
MDQ_A29
CRUSH11
PART 2
SYSTEM MEMORY
MDQ_B16
MDQ_B17
MDQ_B18
MDQ_B19
MDQ_B20
MDQ_B21
MDQ_B22
MDQ_B23
MDQ_B24
MDQ_B25
MDQ_B26
MDQ_B27
MDQ_B28
MDQ_B29
F16
F17
D22
E24
F15
F18
E23
F25
F26
E27
E32
F31
D27
D29
J31
MDQ_B16
MDQ_B17
MDQ_B19
MDQ_B18
MDQ_B20
MDQ_B21
MDQ_B22
MDQ_B23
MDQ_B25
MDQ_B24
MDQ_B26
MDQ_B27
MDQ_B29
MDQ_B28
MDQ_B30
MDQ_A30
MDQ_A31
MDQ_B30
MDQ_B31
J30
MDQ_B31
MDQ_A32
MDQ_B32
M29
P29
MDQ_B33
MDQ_B32
MDQ_A33
MDQ_A34
MDQ_B33
MDQ_B34
P31
MDQ_B34
MDQ_A35
MDQ_B35
T29
M30
MDQ_B36
MDQ_B35
MDQ_A36
MDQ_A37
MDQ_B36
MDQ_B37
N31
MDQ_B37
MDQ_A38
MDQ_B38
R31
R29
MDQ_B39
MDQ_B38
MDQ_A39
MDQ_A40
MDQ_B39
MDQ_B40
V31
MDQ_B40
MDQ_A41
MDQ_B41
V30
AA29
MDQ_B41
MDQ_B42
MDQ_A42
MDQ_A43
MDQ_B42
MDQ_B43
AB29
MDQ_B43
MDQ_A44
MDQ_B44
U29
MDQ_B45
MDQ_B44
MDQ_A45
MDQ_B45
V29
MDQ_B46
MDQ_A46
MDQ_B46
AA30
MDQ_A47
MDQ_B47
AC31
AC29
MDQ_B47
MDQ_B48
MDQ_A48
MDQ_A49
MDQ_B48
MDQ_B49
AC30
MDQ_B49
MDQ_A50
MDQ_B50
AF29
AG31
MDQ_B51
MDQ_B50
MDQ_A51
MDQ_A52
MDQ_B51
MDQ_B52
AD31
MDQ_B52
MDQ_A53
MDQ_B53
AD29
AD30
MDQ_B53
MDQ_B54
MDQ_A54
MDQ_A55
MDQ_B54
MDQ_B55
AE29
MDQ_B55
MDQ_A56
MDQ_B56
AG29
AG30
MDQ_B56
MDQ_B57
MDQ_A57
MDQ_A58
MDQ_B57
MDQ_B58
AJ30
MDQ_B58
MDQ_A59
MDQ_A60
MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7
MDQS_B0
MDQS_B1
MDQS_B2
MDQS_B3
MDQS_B4
MDQS_B5
MDQS_B6
MDQS_B7
MBA_B0
MBA_B1
MCLK_B0
MCLK_B0#
MCLK_B1
MCLK_B1#
MCLK_B2
MCLK_B2#
MCLK_B3
MCLK_B3#
MCLK_B4
MCLK_B4#
MCLK_B5
MCLK_B5#
MRAS_B#
MWE_B#
MCKE_B
MCS_B0#
MCS_B1#
MCS_B2#
MCS_B3#
MDQ_B59
MDQ_B60
AK31
AF30
MDQ_B61
MDQ_B59
MDQ_B60
MDQ_A61
MDQ_A62
MA_B0
MA_B1
MA_B2
MA_B3
MA_B4
MA_B5
MA_B6
MA_B7
MA_B8
MA_B9
MA_B10
MA_B11
MA_B12
MDQ_B61
MDQ_B62
AH31
AJ31
MDQ_B62
MDQ_B63
MDQ_A63
MDQ_B63
AJ29
D9
F13
F20
H31
P30
Y30
AE31
AH29
F9
D13
F19
D28
N29
AA31
AF31
AK32
K31
H30
H29
C31
F28
D26
D25
F22
F23
D21
L31
D20
E17
R30
L29
C34
D34
B17
C18
AH32
AJ32
B33
B34
B19
C20
AK34
AK33
U31
U30
E15
Y29
AB31
W31
Y31
U7B
CRUSH 11
MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7
MDQS_B0
MDQS_B1
MDQS_B2
MDQS_B3
MDQS_B4
MDQS_B5
MDQS_B6
MDQS_B7
MA_B0
MA_B1
MA_B2
MA_B3
MA_B4
MA_B5
MA_B6
MA_B7
MA_B8
MA_B9
MA_B10
MA_B11
MA_B12
MDQM_B[0..7] {14}
MDQS_B[0..7] {14}
MA_B[0..12] {14}
MBA_B0 {14}
MBA_B1 {14}
MCLK_B0 {14}
MCLK_B#0 {14}
MCLK_B1 {14}
MCLK_B#1 {14}
MCLK_B2 {14}
MCLK_B#2 {14}
MCAS_B# {14}
MRAS_B# {14}
MWE_B# {14}
MCKE_B {14}
MCS_B#0 {14}
MCS_B#1 {14}
MCS_B#2 {14}
MCS_B#3 {14}
D D
MA_A[0..12]{14}
C C
MBA_A0{14}
MBA_A1{14}
MCLK_A0{14}
MCLK_A#0{14}
MCLK_A1{14}
MCLK_A#1{14}
MCLK_A2{14}
MCLK_A#2{14}
MCAS_A#{14}
MRAS_A#{14}
MWE_A#{14}
MCKE_A{14}
MEM_STR
R242 X_0
R245 X_0
R204 2K
R200 10K
DDR2_VREF
MCS_B#2 CS_A#0
MCS_B#3
PCIRST#0
,9,11
B B
Put in Solder
MDQ_B[0..63]{14}
C10
MDQM_A0
D16
MDQM_A1
B23
MDQM_A2
B29
MDQM_A3
H32
MDQM_A4
T32
MDQM_A5
AC32
MDQM_A6
AL33
MDQM_A7
B10
MDQS_A0
C15
MDQS_A1
C23
MDQS_A2
C29
MDQS_A3
G33
MDQS_A4
T33
MDQS_A5
AD33
MDQS_A6
AM33
MA_A0
MA_A1
MA_A2
MA_A3
MA_A4
MA_A5
MA_A6
MA_A7
MA_A8
MA_A9
MA_A10
MA_A11
MA_A12
CS_A#1
PRST#1
0.1u(S/S)C631
0.1u(S/S)C630
MDQS_A7
J29
MA_A0
G31
MA_A1
D32
MA_A2
C30
MA_A3
F27
MA_A4
F24
MA_A5
E26
MA_A6
D23
MA_A7
D24
MA_A8
F21
MA_A9
K29
MA_A10
E21
MA_A11
E18
MA_A12
T31
MBA_A0
L30
MBA_A1
A32
MCLK_A0
B32
MCLK_A0#
B16
MCLK_A1
C17
MCLK_A1#
AB33
MCLK_A2
AB32
MCLK_A2#
R33
MCAS_A#
M33
MRAS_A#
N33
MWE_A#
E20
MCKE_A
P32
MCS_A0#
R32 W29
MCS_A1# MCAS_B#
C32
STR_EN#
M31
MEM_VREF
MDQ_B0
MDQ_B1
MDQ_B2
MDQ_B3
D8E9F10
E11E8F8
MDQ_B0
MDQ_B3
MDQ_B1
MDQ_B2
DDR Terminational Resisitors
MDQ_B16
MDQ_B17
MDQ_B18
MDQ_B19
MDQ_B20
MDQ_B21
MDQ_B22
MDQ_B23
MDQ_B41
MDQ_B42
MDQ_B45
MDQ_B46
MDQ_B52
MDQ_B53
MDQS_B2
MDQS_B3
MDQS_B5
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B5
MDQ_B24
MDQ_B28
MDQ_B29
MDQ_B25
MDQ_B30
MDQ_B26
MDQ_B27
MDQ_B31
MDQ_B32
MDQ_B36
MDQ_B33
MDQ_B37
MDQS_B4
MDQ_B34
MDQM_B4
MDQ_B38
MDQ_B39
MDQ_B35
MDQ_B40
MDQ_B44
MCKE_A
MCKE_B
R72 100
R75 100
R96 100
R110 100
R70 100
R82 100
R99 100
R107 100
R206 100
R219 100
R202 100
R221 100
R243 100
R241 100
R81 100
R120 100
R215 100
R40 100
R88 100
R127 100
R210 100
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R79 100
R76 100
RN23
100
RN24
100
RN28
100
RN31
100
RN34
100
DDR REFENCE VOLTAGE
MEM_STR
R27
110RST
DDR2_VREF
R26
110RST
Put near DIMM
MDQ_B14
MDQ_B15
MDQ_B10
MDQ_B11
MDQ_B0
MDQ_B4
MDQ_B1
MDQS_B0
MDQ_B5
MDQ_B6
MDQM_B0
MDQ_B2
MDQ_B7
MDQ_B3
MDQ_B8
MDQ_B9
MDQS_B1
MDQ_B13
MDQ_B12
MDQ_B43
MDQ_B47
MDQ_B48
MDQ_B49
MDQ_B55
MDQM_B6
MDQ_B54
MDQS_B6
MDQ_B61
MDQ_B60
MDQ_B50
MDQM_B7
MDQ_B51
MDQ_B63
MDQ_B62
MDQ_B56
MDQ_B57
MDQ_B58
MDQS_B7
MDQ_B59
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
DDR2_VREF {14}
VTT_DDR2VTT_DDR2
RN78
100
RN5
100
RN9
100
RN10
100
RN11
100
RN38
100
RN41
100
RN42
100
RN44
100
RN45
100
30mils Trace/45mils Space
A A
MSI
Title
Size Document Number Rev
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Crush11 Memory Signals
(MS-6597)
2
625Wednesday, September 04, 2002
0B
of
1
8
7
6
5
4
3
2
1
CRUSH 11 AGP & LDT SIGNALS
GAD[0..31]{15}
D D
C C
GC_BE#[0..3]{15}
AD_STB0{15}
AD_STB#0{15}
AD_STB1{15}
AD_STB#1{15}
GFRAME#{15}
GDEVSEL#{15}
GIRDY#{15}
GTRDY#{15}
GSTOP#{15}
GPAR{15}
GREQ#{15}
GGNT#{15}
SB_STB{15}
SB_STB#{15}
SBA[0..7]{15}
B B
ST[0..2]{15}
PIPE#{15}
RBF#{15}
WBF#{15}
VREF4X_IN{15}
AGPCLK{15}
R212 22
CRUSH 11 Strapping Resistors
A A
C318 X_1u-0805
LDT_RSET
TEST
8
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC_BE#0
GC_BE#1
GC_BE#2
GC_BE#3
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
ST0
ST1
ST2
VREF4X_IN
R231 22
10pC287
GCLK
4.7pC302 X_10pC297
GCLK_FBI
GCLK_FBO
0.1uC312
R255 49.9RST
R192 10K
AL19
AJ19
AL18
AM19
AN19
AJ18
AL17
AK18
AL16
AM17
AJ16
AL15
AN17
AJ15
AK15
AM16
AL13
AN13
AJ13
AL12
AM12
AM11
AJ12
AK12
AK11
AJ11
AN10
AM9
AL10
AN8
AM8
AK10
AM18
AN16
AM13
AL11
AK17
AJ17
AM10
AN11
AN14
AM14
AK14
AJ14
AM15
AL14
AM5
AM4
AL8
AL7
AK8
AL6
AJ8
AM7
AN7
AJ9
AL9
AK9
AM3
AK6
AN5
AK7
AP5
AM6
AN20
AP4
AL3
AN4
VREF4X_IN
U7C
AGP_AD0
AGP_AD1
CRUSH11
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
INTERFACE
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_CBE0#
AGP_CBE1#
AGP_CBE2#
AGP_CBE3#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_FRAME#
AGP_DEVESEL#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_REQ#
AGP_GNT#
AGP_SBSTB
AGP_SBSTB#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_PIPE#
AGP_RBF#
AGP_WBF#
AGP_VREF
AGP_CLK
AGP_CLK_FB_IN
AGP_CLK_FB_OUT
CRUSH 11
7
PART 3
AGP 4X,
VIDEO,
AND
LDT
VDD
C319
0.1u
LDT_RSET
LDT_RST#
LDT_RX_CLK
LDT_RX_CLK#
LDT_RXD0
LTD_RXD0#
LDT_RXD1
LTD_RXD1#
LDT_RXD2
LTD_RXD2#
LDT_RXD3
LTD_RXD3#
LDT_RXD4
LTD_RXD4#
LDT_RXD5
LTD_RXD5#
LDT_RXD6
LTD_RXD6#
LDT_RXD7
LTD_RXD7#
LDT_RXD8
LTD_RXD8#
LDT_TX_CLK
LDT_TX_CLK#
LDT_TXD0
LDT_TXD0#
LDT_TXD1
LDT_TXD1#
LDT_TXD2
LDT_TXD2#
LDT_TXD3
LDT_TXD3#
LDT_TXD4
LDT_TXD4#
LDT_TXD5
LDT_TXD5#
LDT_TXD6
LDT_TXD6#
LDT_TXD7
LDT_TXD7#
LDT_TXD8
LDT_TXD8#
TEST
INTR_OUT#
PCI_RST#
CLK14318IN
VDD_PLL
VDD_DAC
DACGND
DACVREF
DACRSET
RED
GREEN
BLUE
HSYNC
VSYNC
C385
0.1u
LDT_RSET
AM28
AJ3
AN23
AM24
AJ21
AK21
AN22
AM23
AL23
AK24
AM25
AN25
AL21
AM22
AL22
AK23
AJ22
AJ23
AL24
AL25
AL26
AM26
AM30
AL29
AN32
AP32
AP31
AN31
AM29
AN28
AK26
AL27
AN30
AN29
AL28
AK27
AJ27
AJ26
AJ25
AJ24
AM27
AN26
TEST
AK3
AK2
AN3
AJ4
VDD_PLL_C12
AK1
C266
1000p
VDD_DAC
AP3
C284
1000p
AM1
DVREF
6
RSET
R
G
B
HSYNC
VSYNC
C278 0.01u
R208 124RST
R228 0
R226 0
R222 0
R207 33
R209 33
AL1
AP2
AN2
AP1
AN1
AL2
AM2
PIN AM1 "rounted GND"
Connect each routed GND to GND plane at
one point only(one via)
Use surface mount caps, and placed closed a s p os si b l e t o
power pins with short, wide direct connections.
LDT_RST# {9}
LDT_RX_CLK {9}
LDT_RX_CLK# {9}
LDT_RXD0 {9}
LDT_RXD#0 {9}
LDT_RXD1 {9}
LDT_RXD#1 {9}
LDT_RXD2 {9}
LDT_RXD#2 {9}
LDT_RXD3 {9}
LDT_RXD#3 {9}
LDT_RXD4 {9}
LDT_RXD#4 {9}
LDT_RXD5 {9}
LDT_RXD#5 {9}
LDT_RXD6 {9}
LDT_RXD#6 {9}
LDT_RXD7 {9}
LDT_RXD#7 {9}
LDT_RXD8 {9}
LDT_RXD#8 {9}
LDT_TX_CLK {9}
LDT_TX_CLK# {9}
LDT_TXD0 {9}
LDT_TXD#0 {9}
LDT_TXD1 {9}
LDT_TXD#1 {9}
LDT_TXD2 {9}
LDT_TXD#2 {9}
LDT_TXD3 {9}
LDT_TXD#3 {9}
LDT_TXD4 {9}
LDT_TXD#4 {9}
LDT_TXD5 {9}
LDT_TXD#5 {9}
LDT_TXD6 {9}
LDT_TXD#6 {9}
LDT_TXD7 {9}
LDT_TXD#7 {9}
LDT_TXD8 {9}
LDT_TXD#8 {9}
PIRQ#E {9,16}
PCIRST#0 {6,9,11}
CLK14M {10}
L42 80-0805
C296
C289
4.7u-0805
0.1u
X_10pC299
X_10pC291
C298
0.1u
CRT_R {17}
CRT_G {17}
CRT_B {17}
CRT_HSYNC {17}
CRT_VSYNC {17}
5
VCC3
PWOK{20,21}
VCORE
VDD
1
2
3
1
2
3
1
2
3
MH7
(NPTH)
4
MH4
(NPTH)
4
MH9
(NPTH)
4
R480 10KST
R488
X_14.7KST
R481 4.75KST
R490
30.1KST
R478 12.1KST
R487
30.1KST
5
6
7
8
9
5
6
7
8
9
5
6
7
8
9
4
5VSB
R479
10K
R483 4.7K
Q43
2N3904S
C574
1u
Q41
2N3904S
C571
2.2u
Q42
2N3904S
C572
1u
Mounting Holes Location Reference Hold
MH5
1
2
3
1
2
3
1
2
3
MH6
MH10
(NPTH)
4
(NPTH)
4
(NPTH)
4
5
6
7
8
9
5
6
7
8
9
5
6
7
8
9
PLL Delay Block
+12V
R507
10K
C573
1000p
Q40
YFET-NDS7002AS
MH1
1
2
3
MH8
1
2
3
3
(NPTH)
4
(NPTH)
4
8
9
8
9
VCC3
Q37
YFET-NDS7002AS
R411 0
VCC3
Q44
YFET-NDS7002AS
R486 18.7KST Q45
R510 56.2KST
5
6
7
5
6
7
C575
1000p
R414 X_0
CP13 X_COPPER
FB9 X_80-0805
C494
4.7u-0805
0.1u
C585
1000p
CP8 X_COPPER
FB5 X_80-0805
C270
C281
4.7u-0805
0.1u
R495
10KST
R512
30.1KST
12
12
FM6
FM7
X_FM
X_FM
12
12
FM16
FM13
X_FM
X_FM
12
12
FM3
FM9
X_FM
X_FM
MSI
Title
Size Document Number Rev
Date: Sheet
Crush11 AGP , LDT Signals & PLL DELAY
2
3VDUAL
VDD_PLL_MCP {9}
C488
CLOSE TO MCP2
VDD_PLL_C12
C259
0.1u
CLOSE TO C11
VCC3
R505
4.7K
R508 1K
C579
1u
12
FM10
X_FM
12
FM15
X_FM
C576
0.33u
C561
0.33u
12
12
12
FM4
X_FM
FM14
X_FM
FM8
X_FM
2N3904S
Q39
2N3904S
12
FM5
X_FM
12
FM12
X_FM
12
FM11
X_FM
MICRO-STAR INt'L CO., LTD.
(MS-6597)
Q38
2N3904S
12
12
12
12
725Wednesday, September 04, 2002
1
PLL_RST {20}
12
FM2
X_FM
12
FM18
X_FM
12
FM22
X_FM
12
FM20
X_FM
of
FM1
X_FM
FM17
X_FM
FM21
X_FM
FM19
X_FM
0B
8
7
6
5
4
3
2
1
30 mils Trace / 40 mils Space
V21
V22
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AB16
VDD_2P5
VDD_3P30
VDD_3P31
VDD_CLK
VDD_CLK
VTT_CPU
VTT_CPU
VTT_CPU
VTT_CPU
VTT_CPU
VTT_CPU
VTT_CPU
VTT_CPU
VTT_CPU
VTT_CPU
VTT_CPU
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V20
R14
GND
GND
R15
GND
GND
R16
GND
GND
R17
GND
GND
R18
GND
GND
R19
GND
GND
R20
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CRUSH11
PART 4
Power and GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T17
T18
T19
T20
T21
T22
U13
R21
T13
GND
6
T14
GND
T15
T16
GND
GND
U14
GND
GND
U15
GND
GND
U16
GND
GND
U17
GND
GND
U18
GND
GND
U19
FB3 0-0805
VCC2_5
FB4 80-0805
VCC3
D D
VCORE
VCORE
C231
0.1u
C624
C623
39p(S/S)
39p(S/S)
L28 80-0805
C253
0.1u
C627
39p(S/S)
C250
39p
C245
0.1u
C237
0.1u
C273
0.1u
C261
0.1u
C225
0.1u
C218
0.1u
C275
0.1u
C271
0.1u
C241
0.1u
C204
0.1u
C211
0.1u
Put in Solder
VDDQ
MEM_STR
C C
VDD
C325
0.1u
B B
C313
0.1u
C227
0.1u
C648
0.1u
C235
0.1u
C304
0.1u
C626
0.1u(S/S)
C306
0.1u
C252
0.1u
C317
0.1u
Put in Solder
C629
0.1u(S/S)
C300
0.1u
C265
0.1u
C320
0.1u
C632
0.1u(S/S)
C293
0.1u
C288
0.1u
C310
0.1u
0.1u(S/S)
C625
Put in Solder
C635
0.1u(S/S)
C633
0.1u(S/S)
0.1u(S/S)
C628
C634
0.1u(S/S)
C636
0.1u(S/S)
CRUSH 11 POWER SIGNALS
A A
8
U7D
AH3
AJ5
AK4
AF1
AF2
A3
F1
H1
H2
M1
P1
P2
V1
Y1
Y2
AD1
AN6
AN12
AN18
AP6
AP10
AP12
AP16
AP18
A7
A10
A12
A16
A18
A22
A24
A28
A33
B12
B18
B24
F34
H33
H34
M34
P33
P34
V34
Y33
Y34
AD34
AF33
AF34
AM34
AJ20
AJ28
AK20
AK28
AK29
AL20
AL30
AM20
AM21
AM31
AM32
AN21
AN24
AP21
AP24
AP28
AP33
N13
N14
N15
N20
N21
N22
P13
P22
R13
R22
Y13
Y22
AA13
AA22
AB13
AB14
AB15
AB20
AB21
AB22
CRUSH 11
7
GND
GND
U20
GND
GND
U21
GND
GND
U22
GND
GND
V13
5
GND
GND
V14
GND
GND
AB17
AJ6
GND
GND
AB19
V19
GND
GND
AB18
N16
GND
GND
AC33
N17
GND
GND
AC34
N18
GND
GND
AE30
N19
GND
GND
AG34
P14
GND
GND
AH30
AJ33
AJ34
V18
V17
V16
V15
AJ1AJ2
AK22
GND
AK25
GND
GND
P18
GND
GND
P19
GND
GND
P20
GND
GND
P21
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AK30
AL31
AN27
AP22
AP25
AP27
AP30
AJ7
AJ10
AK5
AK13
AK16
AK19
AL4
AL5
AN9
AN15
AP7
AP9
AP13
AP15
AP19
B1
C3
D4
D5
E1
E4
E5
E6
E7
F6
F7
J1
J5
L1
L2
M5
R1
R5
U1
U2
V5
AA1
AA5
AC1
AC2
AD5
AG1
AH6
A6
A9
A13
A15
A19
A21
A25
A27
A30
A34
B6
B9
B15
B21
B27
D30
D31
E10
E13
E16
E19
E22
E25
E28
E29
E30
E31
E34
F29
F30
G29
G30
J34
K30
L33
L34
N30
R34
T30
U33
U34
W30
AA34
AB30
4
3
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Crush11 Power Signals
(MS-6597)
2
825Monday, August 05, 2002
0B
of
1
GND
GND
GND
GND
P15
P16
P17
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