5
4
3
2
1
MS-6568 VER:0A
CPU: AMD Socket-462 Processor
CONTENT
Chipset: SiS 740
D D
LPC I/O: W83697HF
AC'97 CODEC:Realtek ALC201A
SIS 961A SOUTH BRIDGE
Cover Page
Block Diagram
Clock Gen.& Clock Buffer
AMD Socket A
SiS 740 Host / AGP 7
Expansion:
GPIO Table on SIS961
GPIO_0
GPIO_1
C C
GPIO_3
GPIO_4
GPIO_5 I/O
GPIO_6
GPI_7
GPI_8 RESUME
GPI_9
GPI_10
GPIO_11
GPIO_13
GPIO_14
GPIO_15
GPIO_16
B B
GPIO_17
GPIO_18
GPIO_19
GPIO_20
I/O
I/O
I/OGPIO_2
I/O
I/O
I/O
I/O
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O RESUME
I/O
I/O
PCI Slot * 3
CNR Slot * 1
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME SMBCLK
RESUME
Pull-Up
Pull-Up
THERM#
EXTSMI#
Pull-UpMAIN
PREQ#5(Pull-Up)
PGNT#5(Pull-Up)
LPCPME#
RING
RESERVED
RESERVED
RESERVED
Pull-UpGPIO_12
Flash Rom protection H: Disable, L: Enable
Pull-Up
KBDAT
KBCLK
MSDAT
MSCLK
SMBDAT
Pull-Up
SiS 740 Memory
SIS 740Mutiol/POWER
SIS 961A SOUTH BRIDGE
DDR SLOT 1,2
DDR TERMINATOR
PCI Slot 1,2
PCI Slot 3,SiS 301DH
LAN 8100BL
IDE Connector
USB Connector
KB/MS/R45 Connector
AC'97 CODEC
Audio Connector
CNR Slot
LPC I/O W83697HF 23
Flash & FAN & H/WMonitor
Parallel Port
Serial Port
Model option table
Model type Function BOM Config
MS6568
MS6568
Option:STD(W/TV) Cfg6568-00A-STD
Cfg6568-00A-AOption:A(w/o TV)
ERP BOM No.
501/601-6568-A10
PWM ST6911D
ACPI Contorller
Front Panel&ATX power CONN.
Decoupling Capacitor 30
PAGE
1
2
3
4,5,6
8
9
10,11
12
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
Cover Sheet
MS-6568
Last Revision Date:
Thursday, November 29, 2001
Sheet
1
130
Rev
0A
of
5
4
3
2
1
MS-6568 Block Diagram
D D
VRM 9.0
APICCLK0
K7 462-Pin Socket Processor
ADDR(In-Out)
PWR-MNG
DATA
CPUCLK
CPUCLK#
INT & PWR-MNG
Clock
DDRCLK[0..5]
DDRCLK-[0..5]
FWDCLK_DDR from SiS740
VGA CONN
SIS740
C C
B B
TV-OUT
301HD
301REFCLK
IDE Primary
IDE Secondary
USB Port 1
USB Port 2
USB Port 3
USB Port 4
UltraDMA
33/66/100
USB
961PCLK
OSCI
VOSCIN
SIS961
740CCLK
Hyper Zip
740DCLK
ZCLK0
ZCLK1
PCI CNTRL
PCI ADDR/DATA
APICCLK1
2 DDR
Modules
PC-266
PCI 2.2
PCI Conn 2
PCI Conn 1
PCI Conn 3
PCI
LAN
8100BL
PCICLK[1..4]
LPC
Onboard
AC'97 Link
AC'97 Codec
CNR
A A
5
I/O set to 48MHz
SIOPCLK
SIO24M
4
WINBOND
W83697HF
Floopy
3
Parallel
Serial
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Block Diagram
MS-6568
Last Revision Date:
Thursday, November 15, 2001
Sheet
1
230
Rev
0A
of
5
4
3
2
1
By-Pass Capacitors Place near to the Clock Buffer
VCC3_3
D D
1 2
C461
0.1u
L51
X_120S_0805
CP12
X_COPPER
C378
X_4.7U_0805
C386
0.1u
C401
0.1u
C397
CP11 X_COPPER
0.1u
CP16 X_COPPER
CLK3_3V
C328
0.1u
CLKCORE2_5V
C359
0.1u
CP10
VCC2_5
C271
0.1u
X_COPPER
L47
1 2
X_120S_0805
C355
0.1u
C342
0.1u
CLK2_5V
C396
0.1u
C362
0.1u
C399
10p
C400
C C
10p
Y2
14.318MHz
U13A
17
VDDPCI
10
VDDAGP
27
AVDD48
50
AVDDcore
56
AVDDCore
5
GND
6
GND
13
GND
18
GND
24
GND
30
GND
37
GND
48
GND
55
GND
8
VDDLAPIC
29
2.5VDDL/3.3VDD
38
2.5VDDL/3.3VDD
46
2.5VDDL/3.3VDD
51
2.5VDDL/3.3VDD
3
Xin
4
Xout
1:These pins have 2X driver strength.
*:These input have 120K internal pull-up resistor to VDD
CPU_T0/CPU_0
CPUCLKT1/CPU1
SDRAM_OUT
1/FS2/PCICLK_F
1/FS3/PCICLK0
FS4/PCICLK1
1/FS0/REF0
1/FS1/REF1
1*/CPUSEL/48M
*DDRSEL/24_48M
ICS950003AF(MAIN CLOCK)
CPU_C0
1/IOAPIC
AGPCLK0
AGPCLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
RESET#
54
53
52
7
49
11
12
14
15
16
19
20
21
22
1
2
26
DDRSEL
25
pin 25 set to 48MHz
9
FS2
FS3
FS4
FS0
FS1
R202 10
R203 10
R204 0
R261 10
R262 10
R211 22
R263 22
R264 22
R280 10
R267 10
RN95 10_8P4R
7 8
5 6
3 4
1 2
R265 33
R281 33
R266 33
R275 22
R272 22
CPUCLK
CPUCLK#
740CCLK
APICCLK0
APICCLK1
740DCLK
ZCLK0
ZCLK1
961PCLK
SIOPCLK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VOSCIN
OSCI
UCLK48MK7SEL
SIO24M
CPUCLK 4
CPUCLK# 4
740CCLK 6
APICCLK0 4
APICCLK1 10
740DCLK 7
ZCLK0 8
ZCLK1 9
961PCLK 9
SIOPCLK 23
PCICLK1 14
PCICLK2 14
PCICLK3 15
PCICLK4 16
VOSCIN 6
OSCI 10
301REFCLK 15
UCLK48M 11
SIO24M 23
740CCLK
CPUCLK
CPUCLK#
740DCLK
APICCLK0
APICCLK1
SIOPCLK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
UCLK48M
SIO24M
961PCLK
ZCLK1
ZCLK0
OSCI
VOSCIN
301REFCLK
C327 X_10p
C325 X_10p
C326 X_10p
C329 X_10p
C422 10p
C423 10p
C429 X_10p
CN13
7 8
5 6
3 4
1 2
X_8P4C-10P
C433 10p
C432 10p
C437 X_10p
C426 X_10p
C425 X_10p
C438 10p
C427 10p
C428 10p
This pin has 120K pull up to Vdd. -->
This pin has 120K pull up to Vdd. -->
This pin has 120K pull up to Vdd. -->
This pin has 120K pull down -->
This pin has 120K pull down -->
This pin has 120K pull down -->
This pin has 120K pull down -->
B B
R282 X_10K
K7SEL
R274 X_10K
DDRSEL
FS3
R258 X_10K
FS4
FS1
FS2
FS0
RN94
1 2
3 4
5 6
7 8
X_10K_8P4R
VCC3_3
VCC3_3
VCC3_3
U13B
R212 10
DDRT1
43
DDRC1
42
DDRT2
41
DDRC2
40
DDRT3
39
DDRC3
36
DDRT4
35
DDRC4
34
DDRT5
33
DDRC5
32
SDATA10,12,22,28
FWDCLK_DDR7
SDATA
SCLK
SCLK10,12,22,28
FWDCLK_DDR
23
SDATA
28
SCLK
47
BUF_IN
DDRT6
DDRC6
DDRT0
31
45
R213 10
-R_DCLK4
R205 10
R_DCLK1
R206 10
-R_DCLK1
R207 10
R_DCLK0 DDRCLK0
R208 10
-R_DCLK0
R209 10
R_DCLK2
R210 10
-R_DCLK2
R194 10
R_DCLK3
R201 10
-R_DCLK3
R215 10
R_DCLK5
R225 10
-R_DCLK5
DDRCLK[0..5]
R_DCLK4
44
DDRCLK-[0..5]
A A
5
ICS950003AF(MAIN CLOCK)
4
DDRCLK4
DDRCLK-4
DDRCLK1
DDRCLK-1
DDRCLK-0
DDRCLK2
DDRCLK-2
DDRCLK3
DDRCLK-3
DDRCLK5
DDRCLK-5
DDRCLK[0..5] 12
DDRCLK-[0..5] 12
3
By-Pass Capacitors Place near to the Clock Buffer
DDRCLK2
DDRCLK1
DDRCLK0
DDRCLK3
DDRCLK5
DDRCLK4
DDRCLK-2
DDRCLK-1
DDRCLK-0
DDRCLK-3
DDRCLK-5
DDRCLK-4
C322 X_10p
1 2
C318 X_10p
1 2
C320 X_10p
1 2
C336 X_10p
1 2
C346 X_10p
1 2
C330 X_10p
1 2
C323 X_10p
1 2
C319 X_10p
1 2
C321 X_10p
1 2
C340 X_10p
1 2
C354 X_10p
1 2
C331 X_10p
1 2
2
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
Clock Generator
MS-6568
Last Revision Date:
Thursday, November 29, 2001
Sheet
330
1
Rev
0A
of
5
AMD 462PGA Socket - Signals
AA35
W37
W35
Y35
U35
U33
S37
S33
AA33
AE37
AC33
AC37
Y37
AA37
AC35
S35
Q37
Q35
N37
J33
G33
G37
E37
G35
Q33
N33
L33
N35
L37
J37
A37
E35
E31
E29
A27
A25
E21
C23
C27
A23
A35
C35
C33
C31
A29
C29
E23
C25
E17
E13
E11
C15
A13
C21
A21
E19
C19
C17
A11
A17
A15
W33
J35
E27
E15
AN33
AE35
C37
A33
C11
AL31
AJ29
AL29
AG33
AJ37
AL35
AE33
AJ35
AG37
AL33
AN37
AL37
AG35
AN29
AN35
AN31
AJ33
AJ21
AL23
AN23
AJ31
E9
C9
A9
CPU1A
SDATA0
SDATA1
SDATA2
SDATA3
SDATA4
SDATA5
SDATA6
SDATA7
SDATA8
SDATA9
SDATA10
SDATA11
SDATA12
SDATA13
SDATA14
SDATA15
SDATA16
SDATA17
SDATA18
SDATA19
SDATA20
SDATA21
SDATA22
SDATA23
SDATA24
SDATA25
SDATA26
SDATA27
SDATA28
SDATA29
SDATA30
SDATA31
SDATA32
SDATA33
SDATA34
SDATA35
SDATA36
SDATA37
SDATA38
SDATA39
SDATA40
SDATA41
SDATA42
SDATA43
SDATA44
SDATA45
SDATA46
SDATA47
SDATA48
SDATA49
SDATA50
SDATA51
SDATA52
SDATA53
SDATA54
SDATA55
SDATA56
SDATA57
SDATA58
SDATA59
SDATA60
SDATA61
SDATA62
SDATA63
SDATAINCLK0
SDATAINCLK1
SDATAINCLK2
SDATAINCLK3
SDATAINVAL
SDATAOUTCLK0
SDATAOUTCLK1
SDATAOUTCLK2
SDATAOUTCLK3
SDTATOUTVAL
SADDIN0
SADDIN1
SADDIN2
SADDIN3
SADDIN4
SADDIN5
SADDIN6
SADDIN7
SADDIN8
SADDIN9
SADDIN10
SADDIN11
SADDIN12
SADDIN13
SADDIN14
SADDINCLK
CLKFWDRST
CONNECT
PROCRDY
SFILLVAL
PGA-D462
5
SDATA#0
SDATA#1
SDATA#2
SDATA#3
SDATA#4
SDATA#5
SDATA#6
SDATA#7
SDATA#8
SDATA#9
SDATA#10
SDATA#11
SDATA#12
SDATA#13
SDATA#14
SDATA#15
SDATA#16
SDATA#17
SDATA#18
SDATA#19
SDATA#20
SDATA#21
SDATA#22
SDATA#23
SDATA#24
SDATA#25
SDATA#26
SDATA#27
SDATA#28
SDATA#29
SDATA#30
SDATA#31
SDATA#32
SDATA#33
SDATA#34
SDATA#35
SDATA#36
SDATA#37
SDATA#38
SDATA#39
SDATA#40
SDATA#41
SDATA#42
SDATA#43
SDATA#44
SDATA#45
SDATA#46
SDATA#47
SDATA#48
SDATA#49
SDATA#50
SDATA#51
SDATA#52
SDATA#53
SDATA#54
SDATA#55
SDATA#56
SDATA#57
SDATA#58
SDATA#59
SDATA#60
SDATA#61
SDATA#62
SDATA#63
SDINCLK#0
SDINCLK#1
SDINCLK#2
SDINCLK#3
SDIVAL#
SDOCLK#0
SDOCLK#1
SDOCLK#2
SDOCLK#3
SDOVAL#
SADI#0
SADI#1
SADI#2
SADI#3
SADI#4
SADI#5
SADI#6
SADI#7
SADI#8
SADI#9
SADI#10
SADI#11
SADI#12
SADI#13
SADI#14
SDINCLK#
CFWDRST
CONNECT
PROCRDY
SFILLVAL#
SDATA#[0..63]6
D D
C C
B B
SDOCLK#[0..3]6
SADI#[2..14]6
A A
SDIVAL#6
CFWDRST6
CONNECT6
PROCRDY6
4
A20M
FERR
INIT
INTR
IGNNE
NMI
RESET
SMI
STPCLK
PWROK
PICCLK
PICD0/BYPASSCLK
PICD1/BYPASSCLK
COREFB-
COREFB+
CLKIN
CLKIN
RSTCLK
RSTCLK
K7CLKOUT
K7CLKOUT
ANALOG
SYSVREFMODE
VREF_SYS
PLLBYPASS
PLLBYPASSCLK
PLLBYPASSCLK
PLLMON1
PLLMON2
PLLTEST
SCANCLK1
SCANCLK2
SCANINTEVAL
SCANSHIFTEN
DBRDY
DBREQ
FLUSH
TCK
TDO
TMS
TRST
VID0
VID1
VID2
VID3
VID4
FID0
FID1
FID2
FID3
SCHECK0
SCHECK1
SCHECK2
SCHECK3
SCHECK4
SCHECK5
SCHECK6
SCHECK7
SADDOUT0
SADDOUT1
SADDOUT2
SADDOUT3
SADDOUT4
SADDOUT5
SADDOUT6
SADDOUT7
SADDOUT8
SADDOUT9
SADDOUT10
SADDOUT11
SADDOUT12
SADDOUT13
SADDOUT14
SADDOUTCLK
4
3
SADDINCLK#
SDATAINCLK#0
CPURST# 5,6
C6
33p
CPU_PWOK
C65
0.1u
3
SDATAINCLK#1
SDATAINCLK#2
SDATAINCLK#3
APICD010
APICD110
SDINCLK#
SDINCLK#0
SDINCLK#1
SDINCLK#2
SDINCLK#3
SADI#0
SFILLVAL#
SADI#1
SDOVAL#
VREFMODE
CPU APIC BLOCK
APICD0
APICD1
A20M#
AE1
FERR
AG1
HINIT#
AJ3
INTR
AL1
IGNNE#
AJ1
NMI
AN3
CPURST#
AG3
SMI#
AN5
STPCLK#
AC1
CPU_PWOK
AE3
APICCLK0
N1
APICD0
N3
APICD1
N5
COREFB-
AG13
COREFB+
AG11
SYSCLK
AN17
SYSCLK#
AL17
AN19
AL19
K7CLKOUT
AL21
K7CLKOUT#
AN21
AJ13
VREFMODE
AA5
VREF_SYS
W5
ZN
AC5
ZN
ZP
TDI
AE5
AJ25
AN15
AL15
AN13
AL13
AC3
S1
S5
S3
Q5
AA1
AA3
AL3
Q1
U1
U5
Q3
U3
L1
L3
L5
L7
J7
W1
W3
Y1
Y3
U37
Y33
L35
E33
E25
A31
C13
A19
J1
J3
C7
A7
E5
A5
E7
C1
C5
C3
G1
E1
A3
G5
G3
E3
ZP
PLLBP#
PLLBYCLK
PLLBYCLK#
PLLMON1
PLLMON2
PLLTEST#
SCANCLK1
SCANCLK2
SINTVAL
SSHIFTEN
DBREQ#
FLUSH#
TCK
TDI
TMS
TRST#
VID0
VID1
VID2
VID3
VID4
FID0
FID1
FID2
FID3
SADO#2
SADO#3
SADO#4
SADO#5
SADO#6
SADO#7
SADO#8
SADO#9
SADO#10
SADO#11
SADO#12
SADO#13
SADO#14
SADOCLK#
A20M# 5,10
HINIT# 5,10
INTR 5,10
IGNNE# 5,10
NMI 5,10
SMI# 5,10
STPCLK# 5,10
CPU_PWOK 28
APICCLK0 3
APICD0 10
APICD1 10
COREFB- 27
COREFB+ 27
PLLBP# 5
PLLBYCLK 5
PLLBYCLK# 5
PLLMON1 5
PLLMON2 5
PLLTEST# 5
SCANCLK1 5
SCANCLK2 5
SINTVAL 5
SSHIFTEN 5
DBREQ# 5
FLUSH# 5
TCK 5
TDI 5
TMS 5
TRST# 5
VID[0..4] 27
FID[0..3] 8
SADO#[2..14] 6
SADOCLK# 6
L25
10nH
L20
10nH
L16
10nH
L13
10nH
L12
10nH
SADDINCLK# 6
SDATAINCLK#[0..3] 6
RN34
7 8
5 6
3 4
1 2
270_8P4R
R6 270
R38 330
R36 330
L26
10nH
C207
5p
L22
10nH
C197
5p
L18
10nH
C181
5p
L14
10nH
C158
5p
L15
10nH
C156
5p
2
V_CORE
VCC2_5
SADDINCLK#
SDATAINCLK#0
SDATAINCLK#1
SDATAINCLK#2
SDATAINCLK#3
2
VCC3_3
C
E
R28
4.7K
1
Q7
2N3904
CPU FERR BLOCK
V_CORE
R39
4.7K
FERR
B
CPU SYSCLK BLOCK
CPUCLK3
SYSCLK
SYSCLK#
C67 680p
C72 680p
CPUCLK#3
R62 60.4_1%
R61
301_1%
R71 60.4_1%
Near socket-A
CPU SYSCLK REFERNCE BLOCK
V_CORE
0.5 * VCORE
VREF_SYS
C45
C60
473p
C55
0.1u
103p
CPU ZN / ZP BLOCK
ZN
R50 40.2_1%
ZP
R49 56.2
match the transmission line
Push-pull compensation circuit
V_CORE
CPU K7CLKOUT BLOCK
K7CLKOUT#
K7CLKOUT
* Trace lengths of CLKOUT and -CLKOUT
are between 2" and 3"
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
RN27
1 2
3 4
5 6
7 8
100_8P4R
Micro Star Restricted Secret
Socket A_Signal
MS-6568
Last Revision Date:
Monday, November 26, 2001
Sheet
1
FERR# 10
V_CORE
R58
100_1%
R57
100_1%
V_CORE
430
of
Rev
0A
5
4
3
2
1
B12B8B4
VCC_CORE98
VCC_CORE99
VCC_CORE100
AJ5
VCC_CORE101
VCCA_PLL
AC7
VCC_Z
NC1
NC2
NC3
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC42
NC43
NC44
NC45
BP0_CUT
BP1_CUT
BP2_CUT
BP3_CUT
0~100 mA
2.25~2.75V
CPU1B
AJ23
VCC_A
AA31
AC31
AE31
AG23
AG25
AG31
AG5
AJ11
AJ15
AJ17
AJ19
AJ27
AL11
AN11
AN9
G11
G13
G27
G29
G31
J31
J5
L31
N31
Q31
S31
S7
U31
U7
W31
W7
Y31
Y5
AG19
G21
AG21
G19
AN27
AL27
AN25
AL25
VCCA_PLL
R59 X_0
R51 0
C96 1u_0 805
VTIN2 23,24
P_THERMADC 24
AMD 462PGA Socket -
V_CORE
Power
H12
H16
H20
H24M8P30R8T30V8X30Z8AB30
D D
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VCC_SRAM1
VCC_SRAM2
VCC_SRAM3
VCC_SRAM4
VCC_SRAM5
VCC_SRAM6
VCC_SRAM7
VCC_SRAM8
VCC_SRAM9
VCC_SRAM11
VCC_SRAM13
VCC_SRAM14
VCC_SRAM16
VCC_SRAM17
VCC_SRAM19
VCC_SRAM20
VCC_SRAM21
VCC_SRAM22
VCC_SRAM23
VCC_SRAM24
VCC_SRAM25
VCC_SRAM26
VCC_SRAM27
VCC_SRAM28
VCC_SRAM29
VCC_SRAM30
VCC_SRAM31
KEY4
KEY6
KEY8
KEY10
KEY12
KEY14
KEY16
KEY18
VCC_CORE6
AD30
AD8
AF10
AF28
AF30
AF32
AF6
AF8
AH30
AH8
AJ9
AK8
AL9
AM8
F30
F8
H10
H28
H30
H32
H6
H8
C C
K30
AJ7
AL7
AN7
G25
G17
AG7
AG15
AG29
K8
G9
N7
Y7
VCC_CORE7
VCC_CORE8
VCC_CORE9
VCC_CORE10
AF14
AF18
AF22
AF26
AM34
AK36
AK34
AK30
AK26
AK22
AK18
AK14
AK10
AL5
AH26
AM30
AH22
AH18
AH14
AH10
AH4
AH2
AF36
AF34
AD6
AM26
AD4
AD2
AB36
AB34
AB32Z6Z4Z2X36
X34
AM22
X32V6V4V2T36
T34
T32R6R4R2AM18
P36
P34
P32M4M6M2K36
K34
K32H4H2
AM14
F36
F34
F32
F28
F24
F20
F16
F12
D32
D28
AM10
D24
D20
D16
D12D8D4D2B36
B32
AM2
B28
B24
B20
B16
VCC_CORE11
VCC_CORE12
VCC_CORE13
VCC_CORE14
VCC_CORE15
VCC_CORE16
VCC_CORE17
VCC_CORE18
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
VCC_CORE27
VCC_CORE28
VCC_CORE29
VCC_CORE30
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VCC_CORE56
VCC_CORE57
VCC_CORE58
VCC_CORE59
VCC_CORE60
VCC_CORE61
VCC_CORE62
VCC_CORE63
VCC_CORE64
VCC_CORE65
VCC_CORE66
VCC_CORE67
VCC_CORE68
VCC_CORE69
VCC_CORE70
VCC_CORE71
VCC_CORE72
VCC_CORE73
VCC_CORE74
VCC_CORE75
VCC_CORE76
VCC_CORE77
VCC_CORE78
VCC_CORE79
VCC_CORE80
VCC_CORE81
VCC_CORE82
VCC_CORE83
VCC_CORE84
VCC_CORE85
VCC_CORE86
VCC_CORE87
VCC_CORE88
VCC_CORE89
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VCC_CORE94
VCC_CORE95
VCC_CORE96
VCC_CORE97
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS_Z
H14
H18
H22
H26
M30P8R30T8V30X8Z30
B B
CPU DECOUPLING CAPACITORS
V_CORE
A A
V_CORE
C110 224P
C107 224P C74 39P
C76 224 P
C47 224 P
C51 224 P
C50 224 P
C148 224P
C108 224P
C106 224P
C66 224P
C81 224P
C77 224P
C49 224P
C100 224P
V_CORE
C90 224P
C70 224P
C93 224P
5
AB8
AF12
AF16
AF20
AF24
AM36
AK32
AK28
AK24
AK20
AK16
AK12
AK4
AK2
AH36
AM32
AH34
AH32
AH28
V_CORE
C53 33p
C173 33p
C172 33p
C48 33p
V_CORE V_CORE
C40 33p
C85 33p
C193 33p
C71 33p
C112 33p
C111 33p
V_CORE
DECOUPLING CAPACITOR INSIDE SOCKET
4
AH24
AH20
AH16
AH12
C83 106P/1206
C73 106P/1206
C113 106P/1206
C58 106P/1206
C102 106P/1206
C56 106P/1206
C101 106P/1206
C57 106P/1206
AF4
AF2
AD36
AD34
AD32
AB6
AB4
AB2
Z36
Z34
Z32X6AM28X4X2
C89 39P
C82 39P
C162 39P
C218 39P
C37 39P
C109 39P
V36
V34
V32T6T4T2R36
place on solder side
inside socket
V_CORE
C489 X_224P
C483 X_224P
C485 X_33p
C487 X_224P
C490 X_39P
C484 X_224P
C495 X_224P
C494 X_33p
C492 X_33p
C488 X_33p
C493 X_33p
C486 X_33p
C491 X_33p
R34
AM24
R32P6P4P2M36
M34
M32K6K4K2AM20
H36
H34
F26
F22
F18
F14
F10F6F4F2AM16
D36
D34
D30
D26
D22
D18
D14
D10D6B34
AM12
B30
B26
B22
B18
B14
B10B6B2
AM4
AK6
AM6
AE7
PGA-D462
**All CPU interface are
2.5V tolerant**
CPU PULL-UP / DOWN BLOCK
PLLTEST#4
IGNNE#
IGNNE#4,10
CPURST#4,6
STPCLK#4,10
PLLMON14
PLLMON24
PLLBYCLK4
PLLBYCLK#4
3
CPURST#
A20M#
A20M#4,10
STPCLK#
HINIT#
HINIT#4,10
SMI#
SMI#4,10
INTR
INTR4,10
NMI
NMI4,10
FLUSH#
FLUSH#4
PLLBP#
PLLBP#4
PLLMON1
PLLMON2
PLLBYCLK
PLLBYCLK#
RN3
1 2
3 4
5 6
7 8
680_8P4R
RN16
1 2
3 4
5 6
7 8
680_8P4R
R42 680
R82 680
R54 56
R55 56
RN21
1 2
3 4
5 6
7 8
100_8P4R
V_CORE
2
DBREQ#4
SCANCLK14
SCANCLK24
Title
Document Number
PLLTEST#
DBREQ#
TCK
TCK4
TMS
TMS4
TDI
TDI4
TRST#
TRST#4
SINTVAL
SINTVAL4
SCANCLK1
SCANCLK2
SSHIFTEN4
SSHIFTEN
Micro Star Restricted Secret
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
RN4
1 2
3 4
5 6
7 8
510_8P4R
RN6
1 2
3 4
5 6
7 8
510_8P4R
1 2
3 4
5 6
7 8
Socket A_Power
MS-6568
Last Revision Date:
Monday, November 26, 2001
Sheet
1
V_CORE
RN5
270_8P4R
530
of
Rev
0A
5
SiS 740 Host
SDATA#1
SDATA#2
SDATA#0
SDATA#4
SDATA#5
SDATA#3
SDATA#7
SDATA#6
SDATA#8
SDATA#11
SDATA#10
SDATA#9
4
SDATA#12
SDATA#14
SDATA#13
SDATA#15
SDATA#16
SDATA#17
SDATA#20
SDATA#18
SDATA#19
SDATA#22
SDATA#21
SDATA#23
SDATA#25
SDATA#24
SDATA#27
SDATA#26
SDATA#29
SDATA#28
SDATA#30
SDATA#31
SDATA#33
SDATA#32
SDATA#34
SDATA#36
SDATA#35
SDATA#38
SDATA#37
SDATA#39
SDATA#42
SDATA#41
SDATA#40
3
SDATA#45
SDATA#44
SDATA#43
SDATA#46
SDATA#48
SDATA#47
SDATA#51
SDATA#49
SDATA#50
SDATA#54
SDATA#52
SDATA#53
SDATA#56
SDATA#57
SDATA#55
SDATA#58
SDATA#59
SDATA#60
SDATA#63
SDATA#61
SDATA#62
2
Haedware strapping
1
CSYNC = 1 : VB voltage select 3.3V
RSYNC = 1 : VGA interface function enable
LSYNC = 0 : Disable external panel link
VBCTL0 = 0 : Select NTSC
VBCTL1 = 0 : ZCLK PLL/DLL Circuit Enable
SDATA#[0..63]
SADI#[2..14]
SADO#[2..14]
B17
E19
C18
A17
C19
B19
A19
A20
E17
A15
D17
B16
E18
C17
A16
D19
B21
A21
B22
A22
B24
A23
A25
A24
C20
C21
E21
E20
D21
D22
C24
C23
E24
E23
E22
F23
H23
G22
F25
G26
C26
B26
C25
D26
E25
E26
F22
F24
H22
L26
K22
J23
L22
K24
L23
L24
G24
H26
H25
H24
J25
J22
J26
SDATA#57
SDATA#58
SDATA#59
J24
SDATA#60
SDATA#61
SDATA#62
SDATA#63
ROUT
GOUT
BOUT
HSYNC
VSYNC
INT#A
VOSCI
DDC1DATA
DDC1CLK
VRSET
VCOMP
VVBWN
CSYNC
RSYNC
LSYNC
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
DACAVDD1
DACAVSS1
DACAVDD2
DACAVSS2
VBCLK
VBGCLK
VBGCLKN
VBHCLK
VBDE
VBCAD
DDC2CLK
DDC2DATA
VBHSYNC
VBVSYNC
VBCTL0
VBCTL1
VBD0
VBD1
VBD2
VBD3
VBD4
VBD5
VBD6
VBD7
VBD8
VBD9
VBD10
VBD11
B8
A8
A9
D7
C7
C5
A3
B7
A7
E10
D9
C9
C4
A2
B3
B5
A5
A4
B4
E9
C8
B9
C10
D2
C1
B1
B2
D1
G5
D5
E5
C2
E4
D3
D4
F2
F3
H5
F1
G3
G4
G1
G2
E1
E2
F4
E3
D D
VDDREFA
VSSREFA
VDDREFB
VSSREFB
HSTLREFA
HSTLREFB
740CCLK3
SDIVAL#4
CPURST#4,5
PROCRDY4
CONNECT4
CFWDRST4
SADDINCLK#4
SADOCLK#4
C C
B B
740CCLK
SDIVAL#
CPURST#
PROCRDY
CONNECT
CFWDRST
SADDINCLK#
SADDOUTCLK#
SDATAINCLK#0
SDATAINCLK#1
SDATAINCLK#2
SDATAINCLK#3
SDOCLK#0
SDOCLK#1
SDOCLK#2
SDOCLK#3
SADI#2
SADI#3
SADI#4
SADI#5
SADI#6
SADI#7
SADI#8
SADI#9
SADI#10
SADI#11
SADI#12
SADI#13
SADI#14
SADO#2
SADO#3
SADO#4
SADO#5
SADO#6
SADO#7 VBCTL0
SADO#8
SADO#9
SADO#10
SADO#11
SADO#12
SADO#13
SADO#14
CPUCLKAVDD
CPUCLKAVSS
CPUPHYAVDD
CPUPHYAVSS
S2KCOMPPD
S2KCOMPND
N22
VDDREFA
M23
VSSREFA
E15
VDDREFB
D16
VSSREFB
M22
HSTLVREFA
E16
HSTLVREFB
T24
CPUCLK
E14
SDATAINVAL#
C6
CPURST#
E11
PROCRDY
D11
CONNECT
E12
CLKFWDRST
A13
SADDINCLK#
R26
SADDOUTCLK#
A18
SDATAINCLK#0
C22
SDATAINCLK#1
F26
SDATAINCLK#2
K26
SDATAINCLK#3
C16
SDATAOUTCLK#0
A26
SDATAOUTCLK#1
D24
SDATAOUTCLK#2
L25
SDATAOUTCLK#3
A14
SADDIN#2
C14
SADDIN#3
B13
SADDIN#4
C15
SADDIN#5
D14
SADDIN#6
D13
SADDIN#7
E13
SADDIN#8
A12
SADDIN#9
C13
SADDIN#10
B14
SADDIN#11
C11
SADDIN#12
C12
SADDIN#13
B11
SADDIN#14
M25
SADDOUT#2
M26
SADDOUT#3
P23
SADDOUT#4
N26
SADDOUT#5
M24
SADDOUT#6
R24
SADDOUT#7
N24
SADDOUT#8
P24
SADDOUT#9
R23
SADDOUT#10
P22
SADDOUT#11
P25
SADDOUT#12
P26
SADDOUT#13
R25
SADDOUT#14
U26
CPUCLKAVDD
T26
CPUCLKAVSS
A10
CPUPHYAVDD
A11
CPUPHYAVSS
T22
S2KCOMPPD
R22
S2KCOMPND
U9A
SIS740
SDATA#0
SDATA#1
SDATA#2
SDATA#3
SDATA#4
SDATA#5
SDATA#6
SDATA#7
SDATA#8
SDATA#9
SDATA#10
SDATA#11
SDATA#12
SDATA#13
SDATA#14
SDATA#15
SDATA#16
SDATA#17
SDATA#18
SDATA#19
SDATA#20
SDATA#21
SDATA#22
SDATA#23
SDATA#24
SDATA#25
SDATA#26
SDATA#27
SDATA#28
SDATA#29
SDATA#30
SDATA#31
SDATA#32
SDATA#33
SDATA#34
SDATA#35
SDATA#36
SDATA#37
SDATA#38
SDATA#39
SDATA#40
SDATA#41
SDATA#42
SDATA#43
SDATA#44
SDATA#45
SDATA#46
SDATA#47
SDATA#48
SDATA#49
SDATA#50
SDATA#51
SDATA#52
SDATA#53
SDATA#54
SDATA#55
SDATA#56
SDATAINCLK#[0..3]
SDOCLK#[0..3]
L32 300S/0603
1 2
L34 300S/0603
G
1 2
L33 300S/0603
B
1 2
HSYNC
R154
33
33
R153
INTA#
VOSCIN
R150 100
put near VGA connector
R151 100
VRSET
VCOMP
VVBWN
CSYNC
RSYNC
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
DACAVDD2
DACAVSS2
DACAVDD2
DACAVSS2
VBCLK
R158
VBHCLK
VBDE
VBCAD
VBHSYNC
VBVSYNC
VBCTL1
VBD0
VBD1
VBD2
VBD3
VBD4
VBD5
VBD6
VBD7
VBD8
VBD9
VBD10
VBD11
VSYNC
0
HSYNC 18
VSYNC 18
INTA# 9,14,15
VOSCIN 3
SPD2 18
SPCLK2 18
VBCLK 15
VBGCLK 15
VBHCLK 15
VBDE 15
VBCAD 15
VBHSYNC 15
VBVSYNC 15
VBCTL0 15
VBCTL1 15
VBD0 15
VBD1 15
VBD2 15
VBD3 15
VBD4 15
VBD5 15
VBD6 15
VBD7 15
VBD8 15
VBD9 15
VBD10 15
VBD11 15
SDATA#[0..63] 4
SADI#[2..14] 4
SADO#[2..14] 4
SDATAINCLK#[0..3] 4
SDOCLK#[0..3] 4
ARR
AR 18
AG
AG 18
AB
AB 18
CSYNC
RSYNC
VRSET
S2KCOMPND
S2KCOMPPD
DCLKAVDD
C285
103p
DCLKAVSS
ECLKAVDD
8.07mA
ECLKAVSS
VBCAD
VBCAD15
VBHCLK
VBHCLK15
R166 4.7K
R157 4.7K
R137 130_1%
R103 40.2_1%
R104 40.2_1%
1 2
C259
300S/0603
0.1u
1 2
C260
300S/0603
0.1u
VCC3_3
V_CORE
VCC3_3
L36
C217
0.1u
VCC3_3
L35
C280
0.1u
VCOMP
C229 0.1u
VVBWN
C235 0.1u
DACAVDD2
DACAVSS2
SiS 740 Host/VGA
MS-6568
C228
0.1u
Last Revision Date:
Tuesday, November 27, 2001
Sheet
630
1
C171
103p
C163
X_103P
C175
X_102p
Put near VGA connector
HSTLREFA
2
R110
0.1u
60.4_1%
740CCLK
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
C160
SHOULD NOT BE CROSS POWER PLANE
Micro Star Restricted Secret
VCC3_3 V_CORE
R99 0
A A
VCC3_3
R139 0
C293
0.1u
C161
0.1u
C222
0.1u
5
C176
X_103P
C223
X_103P
CPUCLKAVDD
CPUCLKAVSS
CPUPHYAVDD
CPUPHYAVSS
VCC1_8
VCC1_8
R98 0
R130 0
C213
0.1u
C159
0.1u
C214
0.1u
VDDREFA
C174
X_103P
VSSREFA
VDDREFB
C209
X_103P
VSSREFB
4
V_CORE
R148
100_1%
R146
100_1%
C239
103p
C240
X_103P
HSTLREFB
C241
X_102p
V_CORE
R102
100_1%
R106
100_1%
3
L30
1 2
C233
300S_0805
103p
10U/16VS
of
VCC1_8
EC17
Rev
0A
5
DMD5
DMD1
DMD4 MD4
DMD0
DMD2
DMD6
DDQM0
D D
C C
DDQS0
DMD8
DMD12
DMD7
DMD3
DMD11
DMD10
DMD15
DMD14
DDQS1
DDQM1
DMD13 DQS0
DMD9
DDQS2
DMD17
DMD16
DMD20
DMD22
DDQM2
DMD21
DMD18
DMD28
DMD24
DMD23
DMD19
DMD27
DMD31
DMD30
DMD26
DMD29
DMD25
DDQS3
DMD33
DMD37
DMD36
DMD32
DMD38
B B
A A
DDQM4
DDQS4
DMD40
DMD44
DMD35
DMD39
DDQS5
DDQM5
DMD45
DMD41
DMD47
DMD46
DMD43
DMD42
DMD55
DMD54
DDQS6
DDQM6
DMD53
DMD52
DMD49
DMD48
DMD56
DMD60
DMD51
DMD50
RN10 10-8P4R
1 2
3 4
5 6
7 8
RN12 10-8P4R
1 2
3 4
5 6
7 8
RN15 10-8P4R
1 2
3 4
5 6
7 8
RN22 10-8P4R
1 2
3 4
5 6
7 8
RN18 10-8P4R
1 2
3 4
5 6
7 8
RN30 10-8P4R
1 2
3 4
5 6
7 8
RN33 10-8P4R
1 2
3 4
5 6
7 8
RN37 10-8P4R
1 2
3 4
5 6
7 8
RN42 10-8P4R
1 2
3 4
5 6
7 8
RN40 10-8P4R
1 2
3 4
5 6
7 8
RN53 10-8P4R
1 2
3 4
5 6
7 8
RN56 10-8P4R
1 2
3 4
5 6
7 8
RN58 10-8P4R
1 2
3 4
5 6
7 8
RN61 10-8P4R
1 2
3 4
5 6
7 8
RN64 10-8P4R
1 2
3 4
5 6
7 8
RN68 10-8P4R
1 2
3 4
5 6
7 8
RN66 10-8P4R
1 2
3 4
5 6
7 8
RN73 10-8P4R
1 2
3 4
5 6
7 8
5
MD5
MD1
MD0
MD2
MD6
DQM0
DQS0
MD8
MD12
MD7
MD3
MD11
MD10
MD15
MD14
DQS1
DQM1
MD13
MD9
DQS2
MD17
MD16
MD20
MD22
DQM2
MD21
MD18
MD28
MD24
MD23
MD19
MD27
MD31
MD30
MD26
DQM3DDQM3
MD29
MD25
DQS3
MD33
MD37
MD36
MD32
MD38
MD34DMD34
DQM4
DQS4
MD40
MD44
MD35
MD39
DQS5
DQM5
MD45
MD41
MD47
MD46
MD43
MD42
MD55
MD54
DQS6
DQM6
MD53
MD52
MD49
MD48
MD56
MD60
MD51
MD50
DDQS7
DDQM7
DMD57
DMD61
DMD59
DMD63
DMD62
DMD58
4
RN76 10-8P4R
1 2
3 4
5 6
7 8
RN81 10-8P4R
1 2
3 4
5 6
7 8
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
DQM0
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
DQM1
DQS1
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
DQM2
DQS2
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM3
DQS3
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM4
DQS4
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
DQM5
DQS5
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
DQS6
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM7
DQS7
4
U25
U22
W26
U24
U23
W25
W24
W23
AA24
W22
AB26
AB24
AA25
AA26
AA23
AC25
AC24
AB22
AA22
AC26
AC23
AD24
AD25
AD26
AB19
AD19
AE18
AE17
AD20
AE20
AF18
AD17
AD18
AF19
AF13
AF12
AD11
AD10
AD12
AE12
AC11
AF10
AE11
AF11
AE5
AF3
AE3
AD3
AD5
AF4
AD4
AF1
AC5
AF2
AA5
AD1
AB4
AB1
AE1
AD2
AB3
AB2
AC3
AC1
AA3
AA1
V22
V24
V26
Y24
Y22
Y26
W1
W5
W3
Y4
Y3
Y2
Y5
Y1
DQS7
DQM7
MD57
MD61
MD59
MD63
MD62
MD58
U9B
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
DQM0
CSB#0/DQS0
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
DQM1
CSB#1/DQS1
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
DQM2
CSB#2/DQS2
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM3
CSB#3/DQS3
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM4
CSB#4/DQS4
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
DQM5
CSB#5/DQS5
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
CSB#6/DQS6
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM7
CSB#7/DQS7
SIS740
3
SiS 740 Memory
MA0
AE14
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
RAMW#A
SRAS#A
SCAS#A
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
RAMW#B
SRAS#B
SCAS#B
CSA#0
CSA#1
CSA#2
CSA#3
CSA#4
CSA#5
DDRVREFA
DDRVSSREFA
DDRVREFB
DDRVSSREFB
SDRCLKI
FWDSDCLKO
SDCLK
AVDDSDCLK
AVSSSDCLK
AVDDDDCLK
AVSSDDCLK
CKE0
CKE1
CKE2
CKE3
CKE4
CKE5
MA1
AC14
MA2
AD15
MA3
AF16
MA4
AB16
MA5
AE21
MA6
AF20
MA7
AF22
MA8
AC20
MA9
AF23
MA10
AD13
MA11
AE9
MA12
AC12
MA13
AD23
MA14
AF24
WE#
AE8
RAS#
AC9
CAS#
AC8
AF14
AC15
AD16
AF17
AB17
AD21
AF21
AD22
AC21
AE23
AD14
AF9
AB13
AE24
AF25
AF8
AD9
AD8
AF7
CS-1
AD7
CS-2
AE6
CS-3
AD6
AC6
AB7
DDRVREFA
AF6
DDRVSSREFA
AF5
DDRVREFB
AE26
DDRVSSREFB
AF26
AF15
AE15
740DCLK
R1
SDAVDD
U1
SDAVSS
U2
DDRAVDD
T2
DDRAVSS
T1
740CKE0
V5
740CKE1
V4
740CKE2
U5
740CKE3
V3
V2
V1
3
DMD[0..63]
DDQM[0..7]
DMA[0..14]
DDQS[0..7]
DCS-[0..3]
CKE[0..3]
R123 0
R122 0
R125 0
CS-0
CS-1
CS-3
CS-2
DWE#
DRAS#
DCAS#
RN62
1 2
3 4
5 6
7 8
0_8P4R
RN24
22
FWDCLK_DDR
C198
10p
CKE1
CKE0
CKE2
R121
740DCLK 3
740CKE1
1 2
740CKE0
3 4
740CKE3 CKE3
5 6
740CKE2
7 8
0
S3AUXSW# 28
2
DWE- 12,13
DRAS- 12,13
DCAS- 12,13
DCS-0CS-0
DCS-1
DCS-3
DCS-2
FWDCLK_DDR 3
RN25
1 2
3 4
5 6
7 8
470_8P4R
R179 470
2
DMD[0..63] 12,13
DDQM[0..7] 12,13
DMA[0..14] 12,13
DDQS[0..7] 12,13
DCS-[0..3] 12,13
CKE[0..3] 12
V_DIMM
RN46 0_8P4R
MA2
1 2
MA3
3 4
MA1
5 6
MA0
7 8
RN36 0_8P4R
MA8
1 2
MA5
3 4
MA6
5 6
MA4
7 8
MA11 DMA11
R116 0
MA10
R101 0
MA12
R105 0
MA14
1 2
MA13
3 4
MA9
5 6
MA7 DMA7
7 8
RN31 0_8P4R
DDRVREFA
DDRVSSREFA
DDRVREFB
DDRVSSREFB
SDAVDD
C257
SDAVSS
0.1u
DDRAVDD
C266
DDRAVSS
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
0.1u
Micro Star Restricted Secret
SiS 740 Memory
1
DMA2
DMA3
DMA1
DMA0
DMA8
DMA5
DMA6
DMA4
DMA10
DMA12
DMA14
DMA13
DMA9
C226
X_0.1u
C227
0.1u
C166
X_0.1u
C178
0.1u
CP8
X_COPPER
L39
1 2
X_300S/0603
C268
X_103P
CP7
X_COPPER
L38
1 2
X_300S/0603
C267
X_103P
MS-6568
Last Revision Date:
Monday, November 26, 2001
Sheet
730
1
VCC2_5
VCC2_5
R140
R141
R109
R111
of
150_1%
150_1%
150_1%
150_1%
VCC3_3
VCC3_3
Rev
C153
0.1u
0A
5
SiS 740 Power
V_CORE
D D
VCC1_8
C C
VCC2_5
B B
A A
VCC3_3
VCC1_8SBY
VCC3SBY
D10
D12
D15
D18
D20
D23
G11
G19
G23
H11
H12
H13
H14
H15
H16
H19
H20
M19
K18
K23
N19
N23
P19
T23
H18
M18
P18
U18
U19
V11
V12
V14
V15
W15
T18
T19
U20
V19
V23
W12
W13
W14
W16
W18
W19
W20
Y11
Y14
Y16
Y18
Y20
Y23
AA4
AB5
AB6
AB8
AB11
AB12
AC18
AB18
AB23
AC4
AC7
AC10
AC13
AC16
AC19
AC22
L19
J19
J20
J11
J12
J14
J15
J18
W9
W4
W8
H9
M9
P9
V8
V9
V7
Y8
Y9
K8
G9
H8
T9
T8
J8
J9
J7
U9D
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
S2KOVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDM
OVDDV
OVDDV
OVDD
OVDD
AUX1.8
AUX3.3
SIS740
5
S2KPVDD
S2KPVDD
S2KPVDD
S2KPVDD
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
PVDDZ
PVDD
PVDD
PVDD
PVDD
PVDD
PVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
OVSSM
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
L18
J13
J16
N18
J4
L4
M7
M8
N4
N8
N9
P8
R9
K9
R8
V13
V16
V18
W11
B10
B12
B15
B18
B20
B23
B25
D25
G25
K25
L11
L12
L13
L14
L15
L16
M13
M14
M15
M16
N13
N14
N15
N16
N25
P12
P13
P14
P15
P16
R11
R12
T25
R13
R14
R15
R16
T11
T12
T13
T14
T15
T16
V25
W2
Y25
AA2
AB9
AB10
AB14
AB15
AC17
AB20
AB21
AB25
AC2
AE2
AE4
AE7
AE10
AE13
AE16
AE19
AE22
AE25
H2
K2
M11
M12
N2
N11
N12
P11
VCC1_8
VCC3_3
4
V_CORE
VCC1_8
VCC2_5
VCC3_3
4
SiS 740 Mutiol / AUX
ZCLK0
ZCLK03
ZSTB0
ZSTB-0
ZSTB1
ZSTB-1
Z1XAVDD
Z1XAVSS
Z4XAVDD
Z4XAVSS
VDDZCMP
ZCMP_N
ZCMP_P
VSSZCMP
ZVREF
ZVSSREF
ZUREQ
ZUREQ9
ZDREQ
ZDREQ9
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
C170
0.1u
C253
0.1u
C185
0.1u
C165
0.1u
C270
0.1u
C243
0.1u
Component Side
C180
C155
0.1u
C149
0.1u
0.1u
C208
0.1u
C131
0.1u
C287
0.1u
C146
0.1u
CLOSED TO VCCM PLANE OF 740
C46
C12
0.1u
C157
0.1u
1u_0805
C244
0.1u
C284
0.1u
R2
L1
L2
J1
J2
R4
R3
T4
T3
P5
P2
P4
P3
P1
N1
N5
N3
M1
M2
M3
M4
M5
L3
K1
K3
L5
K4
K5
J3
H1
H3
J5
H4
C254
103p
U9C
SIS740
ZCLK
ZSTB0
ZSTB#0
ZSTB1
ZSTB#1
Z1XAVDD
Z1XAVSS
Z4XAVDD
Z4XAVSS
VDDZCMP
ZCMP_N
ZCMP_P
VSSZCMP
ZVREF
ZVSSREF
ZUREQ
ZDREQ
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
C186
0.1u
C144
0.1u
ZAD[0..15]9
ZSTB[0..1]9
ZSTB-[0..1]9
C150
0.1u
3
3
C94
1u_0805
ZAD[0..15]
ZSTB[0..1]
ZSTB-[0..1]
TESTMODE0
TESTMODE1
TESTMODE2
TRAP0
TRAP1
TRAP2
TRAP3
ENTEST
DLLENN
DRAM_SEL
PCIRST#
AUXOK
PWPOK
C104
1u_0805
Solder Side
V_CORE
C496
0.1u
VCC3_3
C504
0.1u
VCC1_8
C498
0.1u
2
1 2
3 4
5 6
7 8
C272
103p
1 2
3 4
5 6
7 8
RN80
680_8P4R
VCC3_3
TRAP0
TRAP1
TRAP2
TRAP3
R164 X_4.7K
C3
R170 4.7K
E7
R171 X_4.7K
E6
TRAP0
B6
TRAP1
A6
TRAP2
E8
TRAP3
D6
ENTEST
F5
CPUDLLENN
D8
DRAM_SEL
R5
AUXOK
PWROK
C256
0.1u
C278
0.1u
PCIRST1#
U3
U4
T5
TESTMODE[1:0]
System Clock Speed
This field defines the speed of the
system clock received by SiS740.
00:100MHz
01: 66MHz
10: 90MHz
11:133MHz
VCC1_8SBY
VCC3_3
CPUCLK SDCLK PLL/DLL Circuit Enable
DDR/SDR SDRAM Selection = 1: DDR SDRAM
PCIRST1# 23,28
AUXOK 10,28
PWROK 10,27,28
VCC3SBY
C279
0.1u
C255
0.1u
CLOSED TO VCCM PLANE OF 740
C503
C499
103p
C497
103p
C506
0.1u
0.1u
C505
0.1u
C508
1u_0805
C501
103p
C507
103p
VCC2_5
C509
0.1u
C502
1u_0805
C500
1u_0805
2
RN84
10K_8P4R
F_FID0
F_FID1
F_FID2
F_FID3
Z1XAVDD
6.49mA
Z1XAVSS
Z4XAVDD
7.92mA
Z4XAVSS
35.4mA
VDDZCMP
ZCMP_N
R156 56
ZCMP_P
R159 56
VSSZCMP
CPUDLLENN
DRAM_SEL
ENTEST
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
1
VCC2_5
123456
10K
L37
300S/0603
L40
300S/0603
L31
C263
X_0.1u
C282
0.1u
78
FID[0..3]
VCC3_3
VCC3_3
VCC1_8
VCC1_8
VCC3_3
Q12
G
D S
X_YFET-NDS7002AS
Q13
G
D S
X_YFET-NDS7002AS
Q10
G
D S
X_YFET-NDS7002AS
Q11
G
D S
X_YFET-NDS7002AS
FID[0..3]4
C264
0.1u
C252
0.1u
ZVREF
ZVSSREF
R177 X_4.7K
R160 4.7K
R165 0
R93
1 2
C265
103p
1 2
C269
103p
1 2
300S/0603
C262
0.1u
Micro Star Restricted Secret
SiS 740 PCI / IDE
MS-6568
Last Revision Date:
Monday, November 26, 2001
Sheet
830
1
of
VCC2_5
RN43
680_8P4R
FID0
FID1
FID2
FID3
C286
0.1u
C283
0.1u
C306
0.1u
R161
150_1%
R178
150_1%
VCC3SBY
Rev
0A
5
SiS 740 PCI and IDE
AD[0..31]14,15,16
D D
C/BE#[0..3]14,15,16
C C
B B
961PCLK3
ZAD[0..15]8
ZSTB[0..1]8
ZSTB-[0..1]8
A A
INTB#
INTA#
INTC#
INTD#
ZAD[0..15]
ZSTB[0..1]
ZSTB-[0..1]
RN102
1 2
3 4
5 6
7 8
8.2K_8P4R
5
AD[0..31]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
SERR#
PAR
INTA#
INTB#
INTC#
INTD#
PREQ#0
PREQ#1
PREQ#3
PREQ#4
PGNT#0
PGNT#1
PGNT#2
PGNT#3
TP1
1
X_T_P
R303 33
ZCLK1
ZSTB0
ZSTB-0
ZSTB1
ZSTB-1
ZUREQ
ZDREQ
SVDDZCMP
SZCMP_N
SZCMP_P
SVSSZCMP
SZVREF
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3
1
961PCLK
SB_PCIRST
C/BE#[0..3]
FRAME#14,15,16
DEVSEL#14,15,16
IRDY#14,15,16
TRDY#14,15,16
STOP#14,15,16
SERR#14,15,16
PAR14,15,16
INTA#6,14,15
INTB#14,15
INTC#14,15,16
INTD#14,15
PREQ#014
PREQ#114
PREQ#214,15
PREQ#314,16
PREQ#414
PGNT#014
PGNT#114
PGNT#215
PGNT#316
PLOCK#
PLOCK#14,15
PCIRST#28
ZCLK13
C443
X_10p
ZUREQ8
ZDREQ8
VCC3_3
V20
N19
N20
K20
K19
N16
N17
R19
N18
R18
P18
R20
P20
V1
U3
R5
T3
U2
U1
T2
P5
T1
R1
R3
R2
P4
P3
P2
N5
L2
L5
L4
L1
K1
L3
K2
K5
J1
J2
K4
J3
H1
H2
J4
J5
P1
M4
K3
M3
N1
M1
M2
N4
M5
N3
E3
F4
E2
G4
F3
H5
E1
F2
F1
H4
G3
G2
G1
H3
N2
Y2
C3
4
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#1
C/BE#2
C/BE#3
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
SERR#
PAR
INT#A
INT#B
INT#C
INT#D
PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4
PLOCK#
PCICLK
PCIRST#
ZCLK
ZSTB0
ZSTB0#
ZSTB1
ZSTB1#
ZUREQ
ZDREQ
VDDZCMP
ZCMP_N
ZCMP_P
VSSZCMP
VZREF
ZVSSREF
4
PCI
MuTIOL
U15A
U10
IDA0
V9
IDA1
W8
IDA2
T9
IDA3
Y7
IDA4
V7
IDA5
Y6
IDA6
Y5
IDA7
W6
IDA8
U8
IDA9
W7
IDA10
V8
IDA11
U9
IDA12
Y8
IDA13
T10
IDA14
W9
IDA15
W11
IDSAA0
U11
IDSAA1
T11
IDSAA2
V12
IDECSA#0
T12
IDECSA#1
IDE1,IDE2
ICHRDYA
IDREQA
IIRQA
CBLIDA
IIOR#A
IIOW#A
IDACK#A
IDEAVDD
IDEAVSSC/BE#0
IDB0
IDB1
IDB2
IDB3
IDB4
IDB5
IDB6
IDB7
IDB8
IDB9
IDB10
IDB11
IDB12
IDB13
IDB14
IDB15
IDSAB0
IDSAB1
IDSAB2
IDECSB#0
IDECSB#1
ICHRDYB
IDREQB
IIRQB
CBLIDB
IIOR#B
IIOW#B
IDACK#B
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
Z4XAVDD
Z4XAVSS
Z1XAVDD
Z1XAVSS
SIS961
W10
V10
Y11
U12
V11
Y9
Y10
Y3
Y4R4
Y16
V15
U14
W14
V13
T13
Y13
Y12
W12
W13
U13
Y14
V14
W15
Y15
U15
V17
T15
Y18
W18
U16
W17
Y17
T16
U17
T14
W16
V16
M18
M19
M17
M16
M20
L16
L20
L18
K18
J20
K17
K16
H20
J18
H19
H18
T20
T19
U20
U19
SZ4XAVDD
SZ4XAVSS
SZ1XAVDD
SZ1XAVSS
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDA0
PDA1
PDA2
-PDCS1
-PDCS3
PIORDY
PDREQ
IRQ14
CBLIDA
-PDIOR
-PDIOW
-PDDACK
IDEAVDD
IDEAVSS
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDA0PREQ#2
SDA1
SDA2
-SDCS1
-SDCS3
SIORDY
SDREQ
IRQ15
CBLIDB
-SDIOR
-SDIOW
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
3
PDD[15..0]
PDA[2..0]
-PDCS1 17
-PDCS3 17
PIORDY 17
PDREQ 17
IRQ14 17
CBLIDA 17
-PDIOR 17
-PDIOW 17
-PDDACK 17
SDD[15..0]
SDA[2..0]
-SDCS1 17
-SDCS3 17
SIORDY 17
SDREQ 17
IRQ15 17
CBLIDB 17
-SDIOR 17
-SDIOW 17
-SDDACK 17
PDD[15..0] 17
PDA[2..0] 17
SDD[15..0] 17
SDA[2..0] 17
2
Analog Power supplies of Transzip
function for 961A Chip.
SZVREF
IDEAVDD
3.22mA
IDEAVSS
SZ1XAVDD
6.47mA
SZ1XAVSS
SZ4XAVDD
7.92mA
SZ4XAVSS
35.64mA
SVDDZCMP
SZCMP_N-SDDACK
SZCMP_P
SVSSZCMP
R246
R247
56
56
C452
0.1u
1 2
C385
0.1u
1 2
C383
0.1u
1 2
300S/0603
C373
0.1u
1
C382
X_0.1u
C374
0.1u
R306
L50
300S/0603
L49
300S/0603
L48
0
VCC1_8
VCC1_8
VCC3_3
VCC3_3
VCC1_8
R243
150_1%
R235
150_1%
C449
0.1u
C376
0.1u
C353
0.1u
Put near 961A Chip.
VCC1_8
R245 X_0
ZSTB0
R244 X_0
ZSTB1
R234 X_0
ZSTB-0
R233 X_0
ZSTB-1
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
3
2
http://www.msi.com.tw
SIS961 Part 1
MS-6568
Last Revision Date:
Monday, November 26, 2001
Sheet
1
930
Rev
00A
of
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