MSI MS-6546 Schematics

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7

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D D

MS-6546

Title Page

Cover Sheet

C C

B B

Block Diagram

Processor Sockets

Clock Synthesizer

DRCG 9

MCH

SCK/CMD

RIMM 13,14

AGP 15

ICH2

FWH

IDE Connectors

USB Connectors

INTEL (R) 850 CHIPSET
Pentium(R) 4 PROCESSOR in 478-Pin SCHEMATICS

Title Page

1

2,3,4,5

6,7

8

10,11,12

12

16,17

18

19

20

PCI Connectors

VID 24

Audio

LPC/Flopy Connector

Hardware Monitor

Parallel Port/Serial Port

KeyBoard/Mouse Ports

PC-PC

Pull-up Resistors

Front Pannel

VRM 9.0

Voltage Regulator

Diagnostic LED

LAN

21,22,23

25,26

27CNR

28

29

30

31

32

33

34

35

36

37

41

A A

Pentium(R) 4 Mother Board

Title

Size Document Number Rev

Custom

8

7

6

5

4

3

Date: Sheet

2

COVER

MS-6546 1.0

of

139Friday, October 19, 2001

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D D

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1

14.318MHz

3MREF_B

3MREF

14.318MHz

33MHz

PCI_Slot_5

33MHz

PCI_Slot_4

33MHz

PCI_Slot_3

33MHz

PCI_Slot_2

33MHz

PCI_Slot_1

33MHz

33MHz

33MHz

33MHz

33MHz

48MHz Pulled_up

48MHz

66MHz

66MHz

66MHz

66MHz

50/67MHz

50/67MHz

100MHz CPU_CK

100MHz ITP_CK

100MHz MCH_CK

100MHz Pulled_up

32.7kHz

CPU

ITP Port

CK00

3.3 volt

C C

3.3 volt

3.3 volt MEM CLK

14.318MHz

B B

(Half Host CLK)

Host Clock Pairs

SUSCLK

LAN_CLK

EE_CLK

ICH

AUD_BCLK SMBCLK

POC PLD

AGP CON

HCLKOUT0
RCLKOUT0
HCLKOUT1
RCLKOUT1

MCH

24.5MHz

SMBCLK

AUDIO
CODEC

DRCG1

DRCG2

400MHz
Output

DRCG_CTM*
DRCG_CTM1

LAN

AUD_BCLK

CNR CON

AUDIO

SMBCLK

RIMM0

SCL

SMBCLK

RIMM1

SCL

SIO

KBCLK

MCLK

FWH

GLUE

HECETA

Hardware Management

RIMM2

SCL

FNT/LSB

MS/KB

RIMM4

SCL

A A

Title

Clock Distribution

Size Document Number Rev

MS-6546 1.0

Custom

8

7

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5

4

3

Date: Sheet

2

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239Friday, October 19, 2001

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Power
Supply
CONN

AGP 4X
AGP
CONN

VRM
AGP
CONN

C C

Heceta Hardware
Monitor

4X (266MHz) AGP

SM Bus

IDE CONN 1&2

USB Port 1:3

USB Port 4
FRNL Panel

B B

PS2 Mouse &
Keyboard

LPC Bus AC Link

SMC I/O

Parallel (1)
Serial (1)

Floppy Disk
Drive CONN

Socket 478VRM CK_SKS Clock

Scalable Bus

MCH: Memory

Controller HUB

HUB Interface

ICH2: I/O

Controller HUB

FWH: Firmware HUB

Tehama Chipset

Stuffing
Options

LAN

Scalable Bus/2

Sync Clock (2)

400MHz DIFF CLK
400MHz DIFF CLK

Direct RDRAM Channel A
Direct RDRAM Channel B

PCI (33MHz)

AC '97

Digital
Central

AC '97 Audio

Codec

Audio In

Line In

CD-ROM

Telephone In

MIC In

DRCG 1&2

RIMM SKTS 1:2

RIMM SKTS 3:4

PCI Slots 1:4

CNR Riser

(Shared slot)

AMP

Line Out

RJ45

A A

Title

Block Diagram

Size Document Number Rev

MS-6546 0A

Custom

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Date: Sheet

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339Thursday, October 25, 2001

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1

D D

C C

B B

PSU

VCC12

VCC3

5VSB

VCC

VCC12

INTERSIL 3-PHASE
CONVERTER

SC1547

& MOSFET

SC1547

& MOSFET

SC1547

& MOSFET

SC1547

& MOSFET

MOSFET

5VDUAL

VCORE

VCC1.8

VDDQ

2.5VSB_STR

VCC_S4

3VSB

LT1084EZ1084

1.8VSB

A A

Title

Reset/Power on Map

Size Document Number Rev

MS-6546 1.0

Custom

8

7

6

5

4

3

Date: Sheet

2

of

439Friday, October 19, 2001

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