MSI MS-6506 Schematics rev.0B

8

7

6

Last Schematic Update Date:
07/02/2001

5

4

3

2

1

D D

MS-6506

Version 0B

INTEL (R) Brookdale Chipset
Willamette/Northwood 478pin mPGA-B Processor Schematics

Cover Sheet
Block Diagram
GPIO Spec. 3
Clock ICS950208 & ATA100 IDE CONNECTORS
mPGA478-B INTEL CPU Sockets

FormFactor : Flex-ATX (22.4 X 19.2mm) for NEC-CI
CPU:

Willamette/Northwood mPGA-478B Processor

INTEL Brookdale MCH -- North Bridge
INTEL ICH2 -- South Bridge
LPC Super I/O Winbond W83627HF
AC'97 Codec & Audio Amp TL072 & GAME

System Brookdale Chipset:

C C

INTEL MCH (North Bridge) +
INTEL ICH2 (South Bridge)

On Board Chipset:

BIOS -- FWH SST49LF004
LPC Super I/O -- W83627HF
Clock Generation -- ICS950208
AC'97 Codec SigmaTel 9756T

FWH -- BIOS & CNR RISER
SDR DIMM-168PIN DIMM1,2
AGP 4X SLOT (1.5V)
PCI SLOT 1 & 2
Front Panel & Connectors

USB & FAN Connectors

Votlage Regulator
HIP6301V CPU Power ( PWM )-VRM9.0

Expansion Slots:

AGP2.0 SLOT * 1

B B

PCI2.2 SLOT * 2
CNR SLOT * 1

IO Connectors
Layout Screw Hole
Jumper Setting
Layout Guide
Power Delivery

1
2

4
5 - 6
7 - 8
9 - 10

11

12

13

14

15

16

17

18

19

20

21

22

23
24-30

31

History I 32

ERP BOM

601-6506-A10

Function Description

MS-6506 Ver:0A

With AGP,CNR,STR.

A A

Micro Star Restricted Secret

Title

Cover Sheet

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

8

7

6

5

4

3

http://www.msi.com.tw

2

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

1 33

of

Rev

8

D D

AGP
4X(1.5V)
AGP CONN

7

Power
Supply
CONN

Page.15

AGP 4X
(1.5V)

6

Page.20Page.17

VRM

9.2

4X (66MHz) AGP

Page.5,6

(593PINS/FCBGA)

5

(478PINS)

Willamette/Northwood
Socket (mPGA478-B)

Scalable Bus

Page.7,8

MCH: Memory

Controller HUB

4

(100MHz)

3

Page.4

2

1

CK408 Clock

(100MHz)
Scalable Bus/2

(133MHz)

Page.14

DIMM 1:2

( 66MHz X 4 )

Page.18

C C

Heceta Hardware
Monitor

Page.4

IDE CONN 1&2

Page.18

USB Port 0:3

SM Bus

(360PINS/EBGA)

(48MHz)

LPC Bus AC Link

Page.11

Page.9,10

Page.13

FWH: Firmware HUB

SIO

W83627HF

Page.19

B B

PS2 Mouse &
Keyboard

Parallel (1)
Serial (2)

Floppy Disk
Drive CONN

HUB Interface

ICH2: I/O

Controller HUB

(33MHz)

(33MHz)

(14.318MHz)

PCI (33MHz)

Page.12

AC '97 Audio

Codec

Line In

CD-ROM

MIC In

Audio In

Page.16

PCI Slots 1:2

Page.13

CNR Riser

(Shared slot)

AMP

Telephone In

Line Out

A A

Micro Star Restricted Secret

Title

Block Diagram

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

8

7

6

5

4

3

http://www.msi.com.tw

2

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

2 33

Rev

0B

of

1

5

4

3

2

1

General Purpose I/O Spec.

D D

ICH2

FunctionTypeGPIO Pin

GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4

C C

GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14~15

B B

GPIO 16
GPIO 17
GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22
GPIO 23
GPIO 24

A A

GPIO 25
GPIO 26
GPIO 27
GPIO 28
GPIO 29~31

5

I

REQ#A

I

PREQ#5

I

INTE#

I

INTF#

I

INTG#

I

INTH#

I

AC97 Enabled/Disabled

I

None

I

Non Connect

I

AC'97 Serial Data In

I

Non Connect

I

Non Connect

I

External SMI

I

LPC PME

I

Not Implemented

O

Non Connect

O

Non Connect

O

Not Implemented

O

Not Implemented
O Non
O

Not Implemented
O

Not Implemented

OD

BIOS Locked/Unlocked
O

Non
O

Non
O

Non

I/O

Non

I/O

non

I/O

Not Implemented

FWH

GPIO Pin Type Function

GPI 0
GPI 1
GPI 2
GPI 3

DEVICE

PCI Slot 1

PCI Slot 2

4

I

ATA IDE 1 Detect

I

ATA IDE 2 Detect
Auto Recovery

I
I

Reserved

ICH INT Pin

INTA#
INTB#
INTC#
INTD#

INTF#
INTG#
INTH#
INTE#

3

IDSEL

AD16

AD17

Micro Star Restricted Secret

Title

GPIO Spec.

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

2

http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

3 33

Rev

0B

of

8

7

6

5

4

3

2

1

*Trace less 0.5"

for good filtering from 10K~1M

VCC3

D D

VCC3

*Put GND copper under Clock Gen.
connect to every GND pin
* 40 mils Trace on Layer 4
with GND copper around it
* put close to every power pin

C C

Trace Width 7mils.

*

Same Group spacing 15mils

*

Different Group spacing 30mils

*

Different mode spacing 7mils on itself

*

FB12

X_600S/0805
CB145
104P

CB167
104P

Rubycon

for good filtering from 10K~1M

FB13

X_600S/0805

Rubycon

+

ELS10/16-B

+

ELS10/16-B

VCC3

VCCP

CT23

CT24

R148

10K

R157 220

CB81
105P

R127
X_0

VCC3V

CB98
105P

SMBCLK{10,11,13,14}

SMBDATA{10,11,13,14}

B

SMBCLK
SMBDATA

VTT_GD# P_STP

CE

Q19
2N3904S

CB77
104P

CB86
104P

CB76
104P

CB91
104P

CB89
104P

CB93
104P

CB95
104P

CB78
104P

U10

39

CPU_VDD

36

CPU_GND

46

MREF_VDD

43

MREF_GND

29

3V66_GND

9

PCI_VDD

5

PCI_GND

18

PCI_VDD

13

PCI_GND

24

48_VDD

21

48_GND

2

REF_VDD

47

REF_GND

34

CORE_VDD

33

CORE_GND

26

SCLK

25

SDATA

19

VTT_GD#

ICS950208

ICS950208
CY28324

CPU0

CPU0#

CPU1

CPU1#

3VMREF/CPU_STP#

3VMREF#/PCI_STP#

3V66_03V66_VDD
3V66_1
3V66_2
3V66_3

FS2/PCI_F0
FS3/PCI_F1

MODE/PCI_F2

FS4/PCI0

PCI1
PCI2
PCI3
PCI4
PCI5
PCI6

FS0/48MHz

FS1/24_48MHz

MUL0/REF0
MUL1/REF1

IREF
RST#

PWR_DN#

41
40

38
37

45
44

3132
30
28
27

6
7
8

10
11
12
14
15
16
17

22
23

48
1

3

X1

4

X2

35
20

42

R115 33
R116 33

R110 33
R111 33

C_STP
P_STP

R117 33
R118 33
R119 33

3V66_3

FS2

MODE

FS3

RN9

MODE

FS2

8P4R-33

FS4

RN10

8P4R-33

FS0

R153 33

FS1

R137 33

MUL0

R120 33

MUL1

32pF

X1 14.318MHZ/32PF

R104 475RST

CRST#

R134 10K
R114 4.7K

Differential Pair

CPUCLK
CPUCLK#

MCHCLK
MCHCLK#

MCH_66
ICH_66
AGPCLK

SIO_PCLK

1 2

FWH_PCLK

3 4

ICH_PCLK

5 6
7 8

7 8
5 6
3 4
1 2

PCICLK0
PCICLK1

ICH_48
SIO_48

ICH_14

18PC81

18PC78 R101 4.7K

10PC73

VCC3V

CPUCLK {5}
CPUCLK# {5}

MCHCLK {7}
MCHCLK# {7}

MCH_66 {7}
ICH_66 {10}
AGPCLK {15}

SIO_PCLK {11}
FWH_PCLK {13}
ICH_PCLK {9}

PCICLK0 {16}
PCICLK1 {16}

ICH_48 {10}
SIO_48 {11}

ICH_14 {10}

CPUCLK

R108 49.9RST

CPUCLK#

R107 49.9RST

MCHCLK

R102 49.9RST

MCHCLK#

R103 49.9RST

Trace less 0.2"

49.9ohm for 50ohm M/B impedance

CLOCK STRAPPING RESISTORS

FS4

R151 10K

FS3

R141 10K

FS1

R136 X_10K
R147 10K

FS0

R135 10K
R146 X_10K

FS2

R140 10K
R139 X_10K

MODE

R142 10K

MUL0

R106 X_10K
R105 10K

MUL1

R149 X_10K
R150 10K

SMBCLK
SMBDATA

R109 4.7K

C_STP VCC3V

R112 X_1K
R113 X_1K

VCC3V
VCC3V

VCC3V

VCC3V

VCC3V

VCC3V

VCC3V

VCC3

CLOCK GENERATOR BLOCK Shut Source Termination Resistors

Pull-Down Capacitors

CN10
X_10P-8P4C

7
MCH_66
ICH_66
AGPCLK

SIO_PCLK
FWH_PCLK
ICH_PCLK

PCICLK0
PCICLK1

ICH_48
SIO_48

ICH_14

used only for EMI issue

Trace less 0.2"

8
6
4
2

CN15

X_10P-8P4C
8
6

4
2

CN16
X_8P4C-10P

10PC93
10PC89

10PC74

5
3
1

7
5
3
1

87
65
43
21

PRIMARY IDE BLOCK SECONDARY IDE BLOCK

B B

PDD[0..7]{10}

A A

RESET BLOCK

PCIRST#

PCIRST#{9} PCIRST#1 {7,11,13} PCIRST#2 {15,16}

8

HD_RST# HD_RST#

PD_DREQ{10}

PD_IOW#{10}

PD_IOR#{10}
PD_IORDY{10}
PD_DACK#{10}

IRQ14{9}
PD_A1{10}
PD_A0{10}

PD_CS#1{10}

PD_LED{17}

R187 8.2K

1 2

U18A
7407S
(VCC5_SB)

PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

R186 4.7K
R185 33

R327 330

C173

X_10P

7

C75
220P

IDE1
YJ220-CB-1

1

2
3 4
5 6
7 8
91110

12

13 14

1615

17 18
19

22

21

24

23

26

25
27
29
31
33
35
37

R122

8.2K
VCC3 VCC3

VCC3 VCC3

R125 470

28
30
32
34
36
38
4039

PCIRST# HD_RST#

PCIRST#

6

ATA100 IDE CONNECTORS

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

9 8

U18D
7407S
(VCC5_SB)

3 4

U18B
7407S
(VCC5_SB)

PDD[8..15] {10}

PD_DET {13}
PD_A2 {10}
PD_CS#3 {10}

R328 330

R300 1K

5

VCC5

R172 4.7K
R189 33

SD_LED{17}

IRQ15{9}
SD_A1{10}
SD_A0{10}

SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

R100 8.2K

C77
220P

3

SDD[0..7]{10}

SD_DREQ{10}

SD_IOW#{10}

SD_IOR#{10}
SD_IORDY{10}
SD_DACK#{10}

SD_CS#1{10}

VCC5VCC5

4

IDE2

YJ220-CW-1
1
3 4
5 6
7 8

91110

13 14
17 18

19
21
23
25
27
29
31
33
35
37

R121

8.2K

2

12
1615

22
24
26

R128 470

28
30
32
34
36
38
4039

SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

SD_DET {13}
SD_A2 {10}
SD_CS#3 {10}

Micro Star Restricted Secret

Title

Clock CY28323/4 & ATA100 IDE

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

SDD[8..15] {10}

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

4 33

of

1

Rev

0B

8

7

6

5

4

3

2

1

CPU GTL REFERNCE VOLTAGE BLOCKCPU SIGNAL BLOCK

VID1

AE4

VID2#

VID1#

D4#

D3#

A25

HD#3

VID0

AE5

A23

HD#2

VID0#

D2#

B22

HD#1

VCCPS+ {20}
VCCPS- {20}

VID[0..4] {11,20}

GTLREF3
GTLREF2
GTLREF1
GTLREF0

BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#

REQ4#
REQ3#
REQ2#
REQ1#
REQ0#

TESTHI12
TESTHI11
TESTHI10

TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0

BCLK1#
BCLK0#

RS2#
RS1#
RS0#

AP1#
AP0#
BR0#

COMP1
COMP0

DP3#
DP2#
DP1#
DP0#

ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

LINT1/NMI

LINT0/INTR

D1#

D0#

B21

SOCKET478

HD#0

AA21
AA6
F20
F6

AB4
AA5
Y6
AC4
AB5
AC6

H3
J3
J4
K5
J1

AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24

AF23
AF22

F4
G5
F1

V5
AC1
H6

P1
L24

L25
K26
K25
J26

R5
L5
W23
P23
J23
F21
W22
R22
K22
E22

E5
D1

4

GTLREF1
GTLREF2

BPM#5
BPM#4

BPM#1
BPM#0

HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0

R83 4.7K
R46 4.7K

R84 4.7K

R51 4.7K

HRS#2
HRS#1
HRS#0

R56 49.9RST
R81 49.9RST

HREQ#[0..4] {7}

VCCP

CPUCLK# {4}
CPUCLK {4}

HRS#[0..2] {7}

HBR#0 {7}

* Short trace

HADSTB#1 {7}
HADSTB#0 {7}
HDSTBP#3 {7}
HDSTBP#2 {7}
HDSTBP#1 {7}
HDSTBP#0 {7}
HDSTBN#3 {7}
HDSTBN#2 {7}
HDSTBN#1 {7}
HDSTBN#0 {7}

NMI {9}
INTR {9}

Length < 1.5inch.

GTLREF1

Length < 1.5inch.

GTLREF2

C44
220P

C35
220P

2/3*Vccp

C43
220P

2/3*Vccp

C34

Every pin put one 220pF cap near it.
Trace Width 15mils, Space 15mils.
Keep the voltage dividers within 1.5 inches of the
first GTLREF Pin

CPU ITP BLOCK

ITP_TMS
ITP_TDO
ITP_DBR#
ITP_TCK

R53 39
R55 75

R49 27

CPU STRAPPING RESISTORS

ALL COMPONENTS CLOSE TO CPU

PROCHOT#
CPU_GD
HBR#0
CPURST#
THERMTRIP#

BPM#0
BPM#1
BPM#4
BPM#5

ITP_TDI
ITP_TRST#
HINIT#

Title

INTEL mPGA478-B CPU1

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

3

http://www.msi.com.tw

2

R48 X_62
R88 300
R70 49.9RST
R85 49.9RST
R74 62

R61 49.9RST
R62 49.9RST
R63 49.9RST
R57 49.9RST

R72 150
R52 680

R44 300

Micro Star Restricted Secret

HA#[3..31]{7}

D D

U7A

HDBI#[0..3]{7}

STPCLK#{9}

HDRDY#{7}

C C

HDEFER#{7}

Trace : 10
mil width
10mil space

CPU_TMPA{11,18}

VTIN_GND{11}

THERMTRIP#{10}

B B

CPU_GD{10}

CPURST#{7}

HD#[0..63]{7}

A A

8

HDBI#0
HDBI#1
HDBI#2
HDBI#3

FERR#{9}

HINIT#{9,13}

HDBSY#{7}
HTRDY#{7}

HADS#{7}

HLOCK#{7}

HBNR#{7}

HIT#{7}

HITM#{7}

HBPRI#{7}

ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_TCK
CPU_TMPA

THERMTRIP#

IGNNE#{9}

HSMI#{9}
A20M#{9}

PROCHOT#

SLP#{9}

CPU_GD
CPURST#
HD#63

HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54

R82

X_0

E21

G25

P26
V21

AC3

AA3

W5

AB2

G1
G4
G2

AF26

AB26

A22

AD2

AD3
AE21
AF24
AF25

AD6

AD5
AB23
AB25
AA24

AA22
AA25

Y21
Y24
Y23

W25

Y26

W26

V24

V6
B6
Y4

H5
H2
J6

F3
E3
D2
E2

C1
D5
F7
E6
D4
B3
C4
A2

C3
B2
B5
C6

A7

DBI0#
DBI1#
DBI2#
DBI3#

IERR#
MCERR#
FERR#
STPCLK#
BINIT#
INIT#
RSP#

DBSY#
DRDY#
TRDY#

ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#

TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#

RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6

BSEL0
BSEL1

PWRGOOD
RESET#
D63#

D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#

AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2

A35#

D53#

D52#

D51#

D50#

V22

U21

V25

U23

U24

HD#53

HD#51

HD#50

HD#49

HD#52

7

A34#

D49#

U26

HD#48

A33#

D48#

T23

HA#31

A32#

D47#

T22

HD#47

HD#46

A31#

D46#

HA#30

HA#29

A30#

D45#

T25

T26

HD#45

HD#44

HA#28

A29#

D44#

R24

HD#43

HA#27

A28#

D43#

R25

HD#42

A27#

D42#

HA#25

HA#26

A26#

D41#

P24

R21

HD#41

HD#40

A25#

D40#

HA#23

HA#24

A24#

D39#

N25

N26

HD#39

HD#38

A23#

D38#

M26

HA#22

HA#21

A22#

D37#

N23

HD#37

HD#36

A21#

D36#

HA#20

HA#19

A20#

D35#

M24

P21

HD#34

HD#35

6

HA#18

A19#

D34#

N22

HD#33

A18#

D33#

M23

HA#16

HA#17

A17#

D32#

H25

HD#32

HD#31

HA#15

A16#

D31#

K23

HD#30

HA#14

A15#

D30#

J24

HD#29

HA#13

A14#

D29#

L22

HD#28

A13#

D28#

HA#11

HA#12

A12#

D27#

M21

H24

HD#26

HD#27

HA#10

A11#

D26#

G26

HD#25

HA#9

A10#

D25#

L21

HD#24

A9#

D24#

HA#8

HA#7

A8#

D23#

D26

F26

HD#23

HD#22

A7#

D22#

HA#6

A6#

D21#

E25

HD#21

HA#5

HA#4

A5#

D20#

F24

F23

HD#19

HD#20

HA#3

A4#

D19#

G23

HD#18

A3#

D18#

E24

HD#17

ITP_DBR#

AE25A5A4

DBR#

Differential
Host Data
Strobes

D17#

D16#

D15#

D14#

H22

D25

J21

D23

HD#14

HD#16

HD#15

HD#13

5

AD26

AC26

ITP_CLK1

ITP_CLK0

VCC_SENSE

VSS_SENSE

D13#

D12#

D11#

D10#

D9#

C26

H21

G22

B25

HD#9

HD#10

HD#11

HD#12

D8#

C24

HD#8

C23

HD#7

D7#

VID4
AE1

VID4#

D6#

B24

HD#6

VID3
AE2

VID3#

D5#

D22

HD#5

VID2

AE3

C21

HD#4

C53

105P

C20

105P220P

MS-6506

Last Revision Date:

Sheet

VCCP

R86

49.9RST

R87
100RST

VCCP

R66

49.9RST

R64
100RST

VCCP

FP_RST# {17}

VCCP

VCCP

VCCP

VCCP

Tuesday, July 03, 2001

5 33

of

1

Rev

0B

8

VCCP

A10

A12

A14

A16

A18

A20A8AA10

AA12

AA14

VCC

VSS

AD18

VCC

VSS

AD21

VCC

VSS

AD23

AD4

VCC

VSS

AD8

VCC

VSS

VCC

VSS

AE11

AA16

AE13

U7B

VCC

VCC

VCC

VSS

AD10

AD12

VSS

VSS

AD14

VCC

VSS

AD16

D D

D10

VSS

A11

VSS

A13

VSS

A15

VSS

A17

VSS

A19

VSS

A21

VSS

A24

VSS

A26

VSS

A3

VSS

A9

VSS

AA1

VSS

AA11

VSS

AA13

VSS

AA15

VSS

AA17

VSS

AA19

VSS

AA23

VSS

AA26

VSS

AA4

VSS

AA7

VSS

AA9

VSS

AB10

VSS

AB12

VSS

AB14

VSS

AB16

VSS

AB18

VSS

AB20
AB21
AB24

AB3
AB6

AB8
AC11
AC13
AC15
AC17
AC19

AC2
AC22
AC25

AC5

AC7

AC9

AD1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C C

VCC

VSS

AA18

VCC

VSS

AE15

AA8

VCC

VSS

AE17

AB11

AE19

VCC

VSS

AB13

VCC

VSS

AE22

AB15

VCC

VSS

AE24

AB17

VCC

VSS

AE26

7

AB19

VCC

VSS

AE7

AB7

AE9

VCC

VSS

AB9

AF1

VCC

VSS

AC10

VCC

VSS

AF10

AC12

AF12

VCC

VSS

AC14

AF14

VCC

VSS

AC16

VCC

VSS

AF16

AC18

VCC

VSS

AF18

AC8

AF20

VCC

VSS

AD11

VCC

VSS

AF6

6

CPU VOLTAGE BLOCK

AD13

AD15

AD17

AD19

AD7

AD9

AE10

AE12

AE14

AE16

AE18

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AF8

B10

B12

B14

B16

B18

B23

B20

B26B4B8

AE20

VCC

VSS

C11

AE6

C13

VCC

VSS

AE8

C15

VCC

VSS

AF11

VCC

VSS

C17C2C19

AF13

VCC

VSS

AF15

VCC

VSS

AF17

AF19

AF2

VCC

VCC

VCC

VSS

VSS

VSS

C22

C25C5C7C9D12

AF21

VCC

VSS

AF5

VCC

VSS

AF7

AF9

VCC

VSS

D14

VCC

VSS

B11

B13

B15

VCC

VCC

VCC

VSS

VSS

VSS

D16

D18

D20

5

B17

B19B7B9

C10

C12

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

D21D3D24D6D8E1E11

4

C14

C16

C18

C20C8D11

D13

D15

D17

D19D7D9

E10

E12

E14

E16

E18

E20E8F11

F13

F15

F17

F19

AF4

F9

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC-VID

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

F25F5F8

G21G6G24

VSS

VSS

G3H1H23

VSS

VSS

VSS

H26H4J2

VSS

VSS

E13

E15

E17

E19

E23

E7E9F10

F12

F14

F16

E4

E26

F18F2F22

AE23

AF3

VCC-VIDPRG

VSS

VSS

VSS

J22

J25J5K21

3

AD20

VCCA

VSSA

VCC-IOPLL

VSS

VSS

VSS

SOCKET478

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AD22

Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24

VCC_VID {19}

C51
106P/1206

C48
106P/1206

2

C50
226P/1206

L2 4.7UH/1206
L1 4.7UH/1206

C47
226P/1206

1

VCCP

B B

CPU DECOUPLING CAPACITORS

CPU DECOUPLING CAPACITORS

BOTTOM

CB29
106P/1206
CB49
106P/1206
CB55
106P/1206
CB32
106P/1206
CB13
106P/1206
CB30
106P/1206
CB34
106P/1206
CB36
106P/1206

A A

CB41
106P/1206
CB26
106P/1206

CB46
106P/1206
CB24
106P/1206
CB27
106P/1206
CB22
106P/1206
CB50
106P/1206
CB43
106P/1206
CB47
106P/1206
CB51
106P/1206
CB19
106P/1206

CB20
106P/1206
CB18
106P/1206
CB15
106P/1206
CB48
106P/1206
CB39
106P/1206
CB45
106P/1206
CB42
106P/1206
CB23
106P/1206

PLACE CAPS WITHIN CPU CAVITY

VCCPVCCP VCCPVCCP

8

7

6

CB188
106P/1206 5020

5

PLACE CAPS WITHIN CPU CAVITY SOLDER

Micro Star Restricted Secret

Title

INTEL mPGA478-B CPU2

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

4

3

http://www.msi.com.tw

2

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

6 33

Rev

0B

of

1

5

HBR#0{5}

HIT#{5}

HITM#{5}

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HRS#0
HRS#1
HRS#2

HDBI#0
HDBI#1
HDBI#2
HDBI#3

R97 24.9RST
R123 24.9RST

HL0
HL1
HL2
HL3
HL4
HL5

VCCP

HA#[3..31]{5}

D D

HBNR#{5}
HBPRI#{5}

HLOCK#{5}

HADS#{5}

HREQ#[0..4]{5}

C C

HDEFER#{5}

HRS#[0..2]{5}

B B

HL[0..10]{9}

A A

HTRDY#{5}

HDBSY#{5}

HDRDY#{5}

HADSTB#0{5}
HADSTB#1{5}

HDSTBN#0{5}
HDSTBP#0{5}
HDSTBN#1{5}
HDSTBP#1{5}
HDSTBN#2{5}
HDSTBP#2{5}
HDSTBN#3{5}
HDSTBP#3{5}

HDBI#[0..3]{5}

MCHCLK{4}

MCHCLK#{4}

HL[0..10]

HL_STB{9}

HL_STB#{9}

5

AE11
AD11
AC15
AC16

AD15

AC13

AB18
AB20
AC19
AD18
AD20
AE19
AE21
AF18
AF20
AG19
AG21
AG23
AJ19
AJ21
AJ23

AD4
AD3
AE6
AE7

AD5
AG4
AH9

AC2

P25
P24
N27
P23
M26
M25

N25
N24

AA9
AB8

U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
K4
M4
M3

K3
M5

H4
N5

M6

V7
W3
Y7
W5

V3
U6

R7
U5
U2

Y5
Y3
Y4

U7
W2
W7
W6

V5
V4

R5
N6

K8

M8
U8

T4
T5
T3

L3
L5

J2
J3

L2

G2
L7

T7

J8

U11A

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

BR0#
BNR#
BPRI#
HLOCK#

ADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#

HIT#
HITM#
DEFER#

HTRDY#
RS0#
RS1#
RS2#

DBSY#
DRDY#

HAD_STB0#
HAD_STB1#

HD_STBN0#
HD_STBP0#
HD_STBN1#
HD_STBP1#
HD_STBN2#
HD_STBP2#
HD_STBN3#
HD_STBP3#

DBI0#
DBI1#
DBI2#
DBI3#

BCLK
BCLK#

H_RCOMP0
H_RCOMP1

HI0
HI1
HI2
HI3
HI4
HI5

HI_STB
HI_STB#

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

82845-A1

HOST

HUB LINK

POWER

4

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

66IN

RSTIN#

CPURST#
H_VREF0

H_VREF1
H_VREF2
H_VREF3
H_VREF4

H_SWNG0
H_SWNG1

HI10

HI_REF

HL_RCOMP

VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

NC0
NC1

4

3

HD#0

AA2

HD#1

AB5

HD#2

AA5

HD#3

AB3

HD#4

AB4

HD#5

AC5

HD#6

AA3

HD#7

AA6

HD#8

AE3

HD#9

AB7

HD#10

AD7

HD#11

AC7

HD#12

AC6

HD#13

AC3

HD#14

AC8

HD#15

AE2

HD#16

AG5

HD#17

AG2

HD#18

AE8

HD#19

AF6

HD#20

AH2

HD#21

AF3

HD#22

AG3

HD#23

AE5

HD#24

AH7

HD#25

AH3

HD#26

AF4

HD#27

AG8

HD#28

AG7

HD#29

AG6

HD#30

AF8

HD#31

AH5

HD#32

AC11

HD#33

AC12

HD#34

AE9

HD#35

AC9

HD#36

AE10

HD#37

AD9

HD#38

AG9

HD#39

AC10

HD#40

AE12

HD#41

AF10

HD#42

AG11

HD#43

AG10

HD#44

AH11

HD#45

AG12

HD#46

AE13

HD#47

AF12

HD#48

AG13

HD#49

AH13

HD#50

AC14

HD#51

AF14

HD#52

AG14

HD#53

AE14

HD#54

AG15

HD#55

AG16

HD#56

AG17

HD#57

AH15

HD#58

AC17

HD#59

AF16

HD#60

AE15

HD#61

AH17

HD#62

AD17

HD#63

AE16
P22

J27
AE17

HVREF

M7
R8
Y8
AB11
AB17

HSWNG

AA7
AD13

HL6

L28

HI6
HI7
HI8
HI9

L27
M27
N28
M24

P26
P27
L25

L29
M22
N23
N26

B19
C5
C8
C23
C26
D12
F26
H27
K23
K25

AD26
AD27

HL7
HL8
HL9
HL10

HUB_MREF

R171 40.2RST

VCC1_8

HD#[0..63] {5}

MCH_66 {4}
PCIRST#1 {4,11,13}
CPURST# {5}

HL[0..10]

VCC1_8

VCC_AGP

VCC_DIMM

3

VTT1
VTT2

VTT_GND1
VTT_GND2

W22

W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23
AG29
AJ25

U13

U17
AD12
AD14
AD16
AD19
AD22

AE1

AE4
AE18
AE20
AE29

AF5

AF7

AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF25

AG1
AG18
AG20
AG22
AH19
AH21
AH23

AJ3

AJ5

AJ7

AJ9
AJ11
AJ13
AJ15
AJ17
AJ27

R22
R29
U22
U26

N14
N16
P13
P15
P17
R14
R16
T15
U14
U16
T13
T17

A13
A17
A21
A25

C29
D11

D15
D19
D23
D25

F10
F14
F18
F22

G29
H10

H12
H14
H16
H18
H20
H22
H24

K22
K24
K26
L23

A5
A9

C1
D7

H8

K6

F6

G1
G4

J5
J7

U11C

VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

82845-A1

POWER

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

2

A3
A7
A11
A15
A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J26
J29
K5
K7
K27
L1
L4
L6
L8
L22
L24
L26
M23
N1
N4
N8
N13
N15
N17
N22
N29
P6
P8
P14
P16
R1
R4
R13
R15
R17
R26
T6
T8
T14
T16
T22
U1
U4
U15
U29
V6
V8
V22
W1
W4
W8
W26
Y6
Y22
AA1
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AB19
AB22
AC1
AC4
AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10

2

MCH REFERENCE BLOCK

VTT1

VTT_GND1
VTT2

VTT_GND2

Length < 3inch.Width at 12mils.

Place 1 Cap. as Close as possible to
every pin of MCH
Trace width use 15 mils and 15mils space

Length < 3inch.Width at 12mils.

HVREF

C87
103P

Place 1 Cap. as Close as possible to
every pin of MCH

Trace width use 15 mils and 15mils space

Place 0.01uF Cap. as Close as possible to MCH
Trace width use 15 mils and 15mils space

CB92
104P

CB96
104P

HSWNG

C67
103P

HUB_MREF

C86

226P/1206

C92

106P/1206

C65
104P

C66
103P

C98
103P

MCH Trace Decoupling Capacitors

VCCP

CB199

5020
X_104P
CB202
X_104P 5020

BOTTOM

Micro Star Restricted Secret

Title

Brookdale MCH 1

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

1

L4 4.7UH/1206
C85

106P/1206

L6 4.7UH/1206
C91

226P/1206

C82

C80

103P

103P

C84

C68

103P

103P

C100

C99

104P

104P

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

VCCP

R126
301RST

R131
150RST

VCCP

R99

49.9RST

R98

100RST

VCC1_8

R170
150RST

R169
150RST

VCC1_8

CB139
104P
CB121
104P

MCH & ICH2

7 33

of

VCC_AGP

VCC_AGP

C69
104P

Rev

0B

5

AA28
AB25
AB27
AA27
AB26

AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24

AA23

U11B

F27

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63

RD_CLKIN
RD_CLKO

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

G_C/BE0#
G_C/BE1#
G_C/BE2#
G_C/BE3#

82845-A1

SDRAM

AGP

Tri-Stated
during
RSTIN#
assertion

E27
B28
C27
D26
E25
B25
D24
F23
B23
C22
C21
D20
C19
C18
C17
B13
E13
C12
B11
E11
C10

F9
C9
E8
E7
C7
D6
B5
D4
C3

B2
G28
E28
C28
D27
B27
F25
C25
E24
C24
E23
D22
E22
B21
C20
D18
E18
E14
C13
E12
F11
C11
E10
D10

B9

E9

D8

B7

E6

C6

C4

B3

D3

G3

H3
R27

R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27
Y26

Y23

V25
V23
Y25

MD[0..63]{14}

D D

C C

Trace Length:50mils

B B

A A

with TP.

GAD[0..31]{15}

GC_BE#0{15}
GC_BE#1{15}
GC_BE#2{15}
GC_BE#3{15}

5

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GC_BE#0
GC_BE#1
GC_BE#2
GC_BE#3

Data line
SDRAM ECC

Bank
Select

System
memory
clock

4

SMA10
SMA11
SMA12

SCS0#
SCS1#
SCS2#
SCS3#
SCS4#
SCS5#
SCS6#
SCS7#
SCS8#

SCS9#
SCS10#
SCS11#

SCKE0
SCKE1
SCKE2
SCKE3
SCKE4
SCKE5

SCK10

SCK11

SRAS#
SCAS#

SM_RCOMP

SD_REF0
SD_REF1

G_FRAME#

G_IRDY#

G_TRDY#

G_DEVSEL#

G_STOP#

G_PAR

G_REQ#
G_GNT#

SB_STB

SB_STB#

AD_STB0

AD_STB0#

AD_STB1

AD_STB1#

AGPREF

G_RCOMP

TESTIN#

4

SMA0
SMA1
SMA2
SMA3
SMA4
SMA5
SMA6
SMA7
SMA8
SMA9

SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7

SBS0
SBS1

SCK0
SCK1
SCK2
SCK3
SCK4
SCK5
SCK6
SCK7
SCK8
SCK9

SWE#

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

PIPE#

RBF#

WBF#

3

MA0

G22

MA1

E21

MA2

F21

MA3

G21

MA4

E20

MA5

G20

MA6

E19

MA7

F19

MA8

G19

MA9

G18

MA10

E17

MA11

E15

MA12

G12

MCS#0

H23

MCS#1

J23

MCS#2

G7

MCS#3

G8

MCS#4

J24

MCS#5

G24

MCS#6

H7

MCS#7

F7
G25
H25
G6
H6

MDP0

C16

MDP1

E16

MDP2

C15

MDP3

D14

MDP4

B17

MDP5

D16

MDP6

B15

MDP7

C14

MCKE0

G9

MCKE1

F4

MCKE2

G10

MCKE3

F5
G11
E5

F17
G17

MCLK0

F13

MCLK1

G13

MCLK2

E2

MCLK3

C2

MCLK4

G15

MCLK5

G14

MCLK6

F3

MCLK7

E3
G16
F15
H5
G5

G23
J25
G27

R162 20.5RST

J28

SM_REF

J9
J21

Y24
W27
W24
W28
W23
W25

AG24
AH25

SBA0

AH28

SBA1

AH27

SBA2

AG28

SBA3

AG27

SBA4

AE28

SBA5

AE27

SBA6

AE24

SBA7

AE25
AF27

AF26

ST0

AG25

ST0
ST1
ST2

AF24
AG26

R24
R23
AC27
AC28

AF22
AE22
AE23

AA21
AD25
H26

ST1
ST2

CB207 X_104P

5020
R161 40.2RST
R163 X_4.7K

MA[0..12] {14}

MCS#0 {14}
MCS#1 {14}
MCS#2 {14}
MCS#3 {14}
MCS#4 {14}
MCS#5 {14}
MCS#6 {14}
MCS#7 {14}

MDP[0..7] {14}

MCKE0 {14}
MCKE1 {14}
MCKE2 {14}
MCKE3 {14}

MBS0 {14}
MBS1 {14}

MRAS# {14}
MCAS# {14}
MWE# {14}

GFRAME# {15}
GIRDY# {15}
GTRDY# {15}
GDEVSEL# {15}
GSTOP# {15}
GPAR {15}

GREQ# {15}
GGNT# {15}

SB_STB {15}
SB_STB# {15}

ST0 {15}
ST1 {15}
ST2 {15}

GAD_STB0 {15}
GAD_STB#0 {15}
GAD_STB1 {15}
GAD_STB#1 {15}

PIPE# {15}
RBF# {15}
WBF# {15}

AGPREF {15}

VCC1_8

SBA[0..7] {15}

Width 10 mils and less
than 500 mils.

3

VCC_DIMM VCC5

VCC_DIMM VCC1_8

BACK

CB198 X_105P 5020

VCC_AGP

CB206 X_105P 5020
CB200 X_105P 5020
CB208 X_105P 5020
CB204 X_105P 5020
CB205 X_105P 5020

2

MCH REFERENCE VOLTAGE

VCC_DIMM

SM_REF

C88
104P

C90

105P

MCH MEMORY CLOCK RC CIRCUITS

MCLK1{14}
MCLK0{14}
MCLK5{14}
MCLK4{14}
MCLK6{14}
MCLK2{14}
MCLK7{14}
MCLK3{14}

MCLK1
MCLK0
MCLK5
MCLK4
MCLK6
MCLK2
MCLK7
MCLK3

MCH DECOUPLING CAPACITOR

CB97
104P

CB101
106P/1206
CB99
106P/1206

104PC41

104PC101

VCC1_8 VCC_DIMMVCCP VCC_AGP

CB111
105P
CB110
104P

104PC97

C96 105P

VCC_DIMMVCCP

CB203 X_105P 5020
CB201 X_105P 5020

2

AGPREF

Title

Brookdale MCH 2

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

1

R152

49.9RST

R144

49.9RST

CN13

X_33P-8P4C

7

8

5

6

3

4

1

2

7

8

5

6

3

4

1

2

CN9

X_33P-8P4C

CB107
104P
CB109
104P
CB116
104P
CB108
104P
CB135
104P

CB94
104P
CB85
104P
CB102
104P
CB90
104P
CB79
104P
CB87
104P
CB82
104P

Micro Star Restricted Secret

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

8 33

1

of

Rev

0B

ICH2 PCI / HUB LINK / CPU / LAN / INTERRUPT SIGNALS

ICH2 SMI# SIGNAL

VCC1_8

D10D2E5

K19

L19P5V9

VCC1.8

VCC1.8

GND1

GND2

VCC1.8

VCC1.8

GND3

GND4

VCC1.8

GND5

GND6

E14

VCC3

GND7

AD[0..31]{16}

C_BE#0{16}
C_BE#1{16}
C_BE#2{16}
C_BE#3{16}

DEVSEL#{16}

FRAME#{16}

IRDY#{16}
TRDY#{16}
STOP#{16}

PLOCK#{16}

SERR#{16}
PERR#{16}

ICH_PCLK{4}

PCIRST#{4}

CS{13}

DIN{13}

DOUT{13}

SHCLK{13}

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C_BE#0
C_BE#1
C_BE#2
C_BE#3

PAR{16}

PME#{15,16}

REQA#
GNTA#

AA4
AB4

AB3
AA5
AB5

AA6

AA8
AB8

AB9
W10
Y10

AA10

AA3
AB6

AA9
AB7

AA7

Y15

W11

AA15

W5
W4

W6
W3

W9

W8
W1

W2
W7

M3

H3
H4

K4
K3

U15A

Y4

Y5

Y3

Y6
Y2

Y1
V2

V1
U4
U3

Y9
U2

U1
T4
T3

Y8

V3
V4

Y7

L2

F4
G4

J1

J4
J3

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE#0
CBE#1
CBE#2
CBE#3

DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PLOCK#
SERR#
PERR#
PME#

GPIO0/REQA#
GPIO16/GNTA#

PCICLK
PCIRST#
NC12

NC13
NC14
NC15
NC16

EE_CS
EE_DIN
EE_DOUT
EE_SHCLK

VCC1.8

VCC1.8

A1A2A10B1B2B3B9

VCC3

E15

E16

E17

E18

F18

G18

H18

J18

P18

R18R5T5U5V5V6V7V8V14

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

GND8

GND9

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND18

GND19

GND20

B10C2C3C4C9D5D6D7D8D9E6E7E8E9J9

VCC3

VCC3

GND21

GND22

J10

VCC3

VCC3

GND23

GND24

J11

VCC1_8SB

V15

VCCSUS1_8

GND25

GND26

J12

J13

J14K9K10

V16H5J5

VCCSUS1_8

VCCSUS1_8

VCCSUS1_8

VCCSUS1_8

GND27

GND28

GND29

GND30

K11

K12

A22

B21

B22C1D1D3E1E2E3

GND68

GND69

GND31

GND32

GND33

K13

K14J2K1

GND70

GND71

GND58

GND59

AA1

NC5

GND60

AA2

AA21

E4

NC6

NC8

NC9

CPUSLP#

NC10

NC11

NC17

STPCLK#

GPIO1/REQB#/REQ5#

GPIO17/GNTB#/GNT5#

LAN_CLK

LAN_RSTSYNC

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2

GND61

GND62

GND63

GND64

GND65

82I801BA

AA22

AB1

AB2

AB21

A20M#
FERR#

IGNNE#

INIT#

INTR

NMI

SMI#

RCIN#

A20GATE

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8

HL9
HL10
HL11

HL_STB
HL_STB#
HLCOMP

HUBREF

PIRQA#

PIRQB#

PIRQC#

PIRQD#

IRQ14
IRQ15

APICCLK

APICD0

APICD1

SERIRQ

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

GNT0#
GNT1#
GNT2#
GNT3#
GNT4#

GND67
GND66

D11
A12
R22
A11
C12
C11
B11
B12
C10
B13
C13

A4
B5
A5
B6
B7
A8
B8
A9
C8
C6
C7
C5
A6
A7
A3

B4
P1

P2
P3
N4

F21
C16
N20
P22
N19
N21

R2
R3
T1
AB10
P4
L3

M2
M1
R4
T2
R1
L4

G3
H2
G2
G1
H1
F3
F2
F1
A21
AB22

A20M#
FERR#

SMI#
KB_RST#

A20GATE#
HL0

HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

R238 40.2RST
HUB_IREF

APIC_D0
APIC_D1
SERIRQ

PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5

PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4
PGNT#5

RN16
8P4R-22

RN15
8P4R-22

A20M# {5}
SLP# {5}
FERR# {5}
IGNNE# {5}
HINIT# {5,13}
INTR {5}
NMI {5}

STPCLK# {5}
KB_RST# {11}
A20GATE# {11}

HL[0..10] {7}

This resistor less than 0.5"
from ICH use 15 mils trace

HL_STB {7}
HL_STB# {7}

VCC1_8

INTA# {15,16}
INTB# {15,16}
INTC# {16}
INTD# {16}

IRQ14 {4}
IRQ15 {4}

SERIRQ {11}
PREQ#0 {16}

PREQ#1 {16}
PREQ#2 {16}
PREQ#3 {16}
PREQ#4 {16}
PREQ#5 {16}

PGNT#0 {16}
PGNT#1 {16}
PGNT#2 {16}
PGNT#3 {16}
PGNT#4 {16}
PGNT#5 {16}

1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

CNR_CLK {13}
CNR_RST {13}
CNR_RXD0 {13}
CNR_RXD1 {13}
CNR_RXD2 {13}
CNR_TXD2 {13}
CNR_TXD1 {13}
CNR_TXD0 {13}

SMI#

R239 33

100PC124

HSMI# {5}

ICH2 STRAPPING RESISTORS

FERR#
SERIRQ
PME#
KB_RST#

A20GATE#
REQA#

GNTA#
APIC_D0

APIC_D1

R65 62
R255 8.2K
R246 X_10K
R240 10K

R227 10K
R260 2.7K

R266 2.7K
R258 10K

R256 10K

VCCP
VCC3
VCC3_SB

VCC3

VCC5
VCC3

ICH2 REFERENCE VOLTAGE

VCC1_8

R225
150RST

HUB_IREF

C123

C122
104P

Place Cap. as Close as possible to ICH2
Trace width use 15 mils and 15mils space

C121
104P

R226
150RST103P

VCC3

CB173
X_104P

CB148
X_104P

CB163
104P

CB156
X_104P

CB122
X_103P

CB142
103P

CB147
104P

Place one 0.1U/0.01U pair in each corner and
2 on opposite sides close to ICH2 if it fit

ICH2 DECOUPLING CAPACITORS

CB125

CB140

104P

104P

Distribute near the 1.8V
power pin of the ICH2

Distribute near the VCC1_8SB
Power pin of the ICH2

VCC1_8SBVCC1_8

Micro Star Restricted Secret

CB151
104P

CB152
104P

Title

Brookdale ICH2 PCI

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6506

Last Revision Date:

Sheet

Tuesday, July 03, 2001

9 33

Rev

0B

of

ICH2 ASIC / RTC / AC'97 / GPIO / LPC / USB / IDE SIGNALS

VCC5VCC3

AC

D5

P11

GND54

P12

VCC5REF1

VCC5REF2

GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#

GND55

GND56

GND57

82I801BA

P13

P14

1N5817S

PDCS1#
SDCS1#
PDCS3#
SDCS3#

PDA0
PDA1
PDA2
SDA0
SDA1
SDA2

PDDREQ

SDDREQ
PDDACK#
SDDACK#

PDIOR#

SDIOR#
PDIOW#
SDIOW#
PIORDY
SIORDY

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8

PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

SDD0

SDD1

SDD2

SDD3

SDD4

SDD5

SDD6

SDD7

SDD8

SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

GPIO6

GPIO7

GPIO8

GPIO18
GPIO19
GPIO20
GPIO24
GPIO25

TP0

VCC3_SB

RTC_VCC

U21

T18

GND35

L10

L11

VCCRTC

GND36

GND37

L12

GND38

L13

L14M9M10

U18

VCC3SUS1

GND39

GND40

THRM#

THRM#{11}
SLP_S3#{11,19}
SLP_S5#{19}

PWR_GD{17}
CPU_GD{5}
VRM_GD{20}

PWRBTN#{11}
RSMRST#{11}

SUSCLK{11}

SMBDATA{4,11,13,14}

SMBCLK{4,11,13,14}

SM_LNK0{16}
SM_LNK1{16}

AC_RST#{12,13}

AC_SYNC{12,13}

AC_BCLK{12,13}

AC_SDOUT{12,13}

AC_SDIN0{12,13}
AC_SDIN1{13}

EXTSMI#{17}

SIO_PME#{11}

LAD0/FWH0{11,13}
LAD1/FWH1{11,13}
LAD2/FWH2{11,13}
LAD3/FWH3{11,13}

LFRAME#/FWH4{11,13}

NEAR CHIPSET LESS THAN 1 INCH

RN25

8P4R-15

1

USB0+{18}
USB0-{18}
USB1-{18}
USB1+{18}
USB3-{18}
USB3+{18}
USB2-{18}
USB2+{18}

3
5
7
1
3
5
7

RN26

8P4R-15

2
4
6
8
2
4
6
8

R30715
R30615

USBP1­USBP1+

USBP3­USBP3+
USBP2­USBP2+

PWR_GD
VRM_GD
RING#

RSMRST#

SMB_ALERT

INTRUDER#
RTCRST#
VBIAS

RTCX2

ICH_66{4}

ICH_14{4}

ICH_48{4}

R261 33

SPKR{17}

SIO_PME#
GPIO22

GP23

GP23{13}

R331 X_10K

LDRQ#{11}

USBP0+
USBP0­USBP1+
USBP1­USBP2+
USBP2­USBP3+
USBP3-

OC#0{18}
OC#1{18}

CNR_USB1- {13}
CNR_USB1+ {13}

U15B

AA13

THRM#

W16

SLP_S3#

AB18

SLP_S5

R20

PWROK

A13

CPUPWRGD

B15

VRMPWRGD

W21

PWRBTN#

AA17

RI#

R21

RSMRST#

Y16

RSM_PWROK

Y17

SUSSTAT#

AA18

SUSCLK

AA16

SMBDATA

AB16

SMBCLK

AB17

GPIO11/SMBALERT#

U19

SMLINK0

V20

SMLINK1

T19

INTRUDER#

T20

RTCRST#

T21

VBIAS

U22

RTCX1

T22

RTCX2

D4

CLK66

M19

CLK14

P20

CLK48

V22

AC_RST#

P19

AC_SYNC

R19

AC_BITCLK

P21

AC_SDOUT

Y22

AC_SDIN0

W22

AC_SDIN1

N22

SPKR

W14

GPIO12

AB15

GPIO13

L1

GPIO21

B14

GPIO22

A14

GPIO23

AB14

GPIO27

AA14

GPIO28

Y12

LAD0/FWH0

W12

LAD1/FWH1

AB13

LAD2/FWH2

AB12

LAD3/FWH3

AA12

FS0

Y13

LDRQ0#

W13

LDRQ1#

AB11

LFRAME#/FWH4

W17

USBP0+

Y18

USBP0-

AB19

USBP1+

AA19

USBP1-

W18

USBP2+

Y19

USBP2-

AB20

USBP3+

AA20

USBP3-

W19

OC0#

Y20

OC1#

Y21

OC2#

W20

OC3#

GND34

L9

F5G5V17

VCC3SUS2

VCC3SUS4

VCC3SUS5

VCC3SUS6

GND41

GND42

GND43

GND44

M11

M12

M13

VCCP VCC5_SB

V18

VCC3SUS7

GND45

GND46

GND47

M14N9N10

N11

D12

D13

VCPU_IO1

GND48

GND49

N12

N13

V19K2M20

VCPU_IO2

GND50

GND51

GND52

N14P9P10

VCC5REF_SUS

GND53

R259
1K

CB153

CB154

104P

104P

E21
C15
E19
D15

F20
F19
E22
A16
D16
B16

G22
B18
F22
B17
G19
D17
G21
C17
G20
A17

H19
H22
J19
J22
K21
L20
M21
M22
L22
L21
K22
K20
J21
J20
H21
H20

D18
B19
D19
A20
C20
C21
D22
E20
D21
C22
D20
B20
C19
A19
C18
A18

U20
N3
N2
N1
M4
Y11
AA11
Y14
A15
D14
C14
V21
W15

PD_CS#1 {4}
SD_CS#1 {4}
PD_CS#3 {4}
SD_CS#3 {4}

PD_A0 {4}
PD_A1 {4}
PD_A2 {4}
SD_A0 {4}
SD_A1 {4}
SD_A2 {4}

PD_DREQ {4}
SD_DREQ {4}
PD_DACK# {4}
SD_DACK# {4}
PD_IOR# {4}
SD_IOR# {4}
PD_IOW# {4}
SD_IOW# {4}
PD_IORDY {4}
SD_IORDY {4}

PDD0
PDD1RTCX1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

BATLOW#

GP6
GP7
GP8 GP8

INTE# {16}
INTF# {16}
INTG# {16}
INTH# {16}

PDD[0..7] {4}

PDD[8..15] {4}

SDD[0..7] {4}

SDD[8..15] {4}

VCC5_SB

VBAT

R338

1.5K

D10
1N5817S

BAT1
YSKTBT-1

R335

4.7K

AC

ICH2 STRAPPING RESISTORS

PD_IORDY
SD_IORDY

PD_DREQ
SD_DREQ

INTRUDER#
RSMRST#

SPKR
PWR_GD

THRM#
VRM_GD
SIO_PME#
RING#
RSMRST#
PWRBTN#
SM_LNK0

SM_LNK1
BATLOW#

EXTSMI#

SMB_ALERT
SLP_S3#

GP23
GPIO22
GP6
GP7

R130 4.7K
R241 4.7K

R132 5.6K
R229 5.6K

R270 22K
R304 10K

R257 X_10K
R268 8.2K

R316 10K
R231 10K
R332 4.7K
R317 8.2K
R303 1K
R295 10K

1 2
3 4
5 6
7 8

1 2
3 4
5 6
7 8

1 2
3 4
5 6
7 8

123

D8
1N4148S

D9

A C

1N5817S

R336
1K

RTC BLOCK

R319
1K

R329
390K
R11-0394013

473PC167

R334
X_20M

R288 10M R280 10M

R289
X_5.6M

VCC3

VBAT

VCC3
VCC3

VCC3_SB

VCC3_SB

RN23
8P4R-4.7K

VCC3_SB

RN29
8P4R-10K

VCC3

RN24
8P4R-4.7K

C176
473P

C161
15P

RTC_VCC

32.768KHZ +-30PPM

SM_CTRL{17}

THERMTRIP#{5}

YJ102-B

JBAT1 Clear CMOS
1 - 2
2 - 3*Clear CMOS

1
2
3

R311
1K

X3

32pF

R262

4.7K

INTERUDER

JCS1

2
1

Normal

JBAT1
D1x3-BK

JBAT1(1-2)

YJUMPER-MG

RTCRST#
VBIAS

RTCX1

C155
15P

R347
10K

RTCX2

R263
1K

B
Q26
2N3904S

THMTR1

NEC-CI AOL2 Function

+12V

12

CE

B

VCC3

VRM_GDINTRUDER#

CE

DS

G

DS

G

R330

8.2K

THMTR2

Q35
2N3904S

SM_LNK0

SM_LNK1

R228
0

Q27
NDS7002AS

Q28
NDS7002AS

VCC3

B

SM_LNK0 {16}

SMBCLK {4,11,13,14}
SM_LNK1 {16}

SMBDATA {4,11,13,14}

R315

8.2K

THRM# {11}

CE

Q34
2N3904S

SMB_ALERT

VCC3_SB

CB170
104P

VCCP VCC5_SB

CB182
104P

CB141
104P

CB185
104P

RTC_VCC

CB159
103P

Distribute near the VCC3_SB power pin of the ICH

ICH2 DECOUPLING CAPACITOR

VCC5_SBVCC5

CB160
104P

CB168
104P

VCC3

R312
1K

JP3(1-2)
YJUMPER-MG

RECOVERY{13}

AC_SDOUT

1

JP3

2

D1x3-BK

3

Micro Star Restricted Secret

Title

Brookdale ICH2 Other

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6506

Last Revision Date:

Sheet

Tuesday, July 03, 2001

10 33

of

Rev

0B

VBAT

LPC SUPER I/O W83627HF

U13

PCIRST#1{4,7,13}

SIO_PCLK{4}

SERIRQ{9}

LDRQ#{10}

LFRAME#/FWH4{10,13}

LAD0/FWH0{10,13}
LAD1/FWH1{10,13}
LAD2/FWH2{10,13}
LAD3/FWH3{10,13}

JYS_AX2{12}
JYS_AX1{12}
JYS_PB0{12}
JYS_PB1{12}
JYS_AX0{12}
JYS_AX3{12}
JYS_PB3{12}
JYS_PB2{12}
MID_OUT{12}

MID_IN{12}

TMP_VREF
CPU_TMP

THRM#{10}

PSON#{17}
SIO_48{4}

VBAT
VCC3

VCC5

CPU_TMPA
SYS_TMP
VTIN_GND

-5VIN

-12VIN
+12VIN
VTIN_VCC

VCC3
VCCP

VID4
VID3
VID2
VID1
VID0

BEEP

CPU_TMPA{5,18}
VTIN_GND{5}

VID[0..4]{5,20}

CPU_FAN{18}
SYS_FAN{18}

10M
R188

SIO_PME#{10}

SMBDATA{4,10,13,14}

SMBCLK{4,10,13,14}

PWRBTN#{10}

PWRBTIN#{17}

SUS_LED{17}

PWR_LED{17}

SLP_S3#{10,19}

VCC5_SB

30

LRESET#

21

LCLK

23

SERIRQ

22

LDRQ#

29

LFRAME#

27

LAD0

26

LAD1

25

LAD2

24

LAD3

125

GPX2/P15/GP14

123

GPY1/GP15

128

GPSA1/P12/GP10

121

GPSA2/GP17

126

GPX1/P14/GP12

124

GPY2/P16/GP14

127

GPSB1/P13/GP11

122

GPSB2/GP16

120

MSO/IRQIN0

119

MSI/GP20

101

VREF

102

VTIN3

103

VTIN2

104

VTIN1

93

AGND

94

-5VIN

95

-12VIN

96

+12VIN

97

AVCC

98

+3.3VIN

99

VCOREB

100

VCOREA

106

VID4

107

VID3

108

VID2

109

VID1

110

VID0

116

FANPWM1

113

FANIO1

115

FANPWM2

112

FANIO2

111

FANIO3

105

OVT#

118

BEEP

76

CASEOPEN#

19

PME#

89

WDTO/GP24

91

SDA/GP22

92

SCL/GP21

67

PSOUT#

68

PSIN#

64

SUSLED/GP35

90

PLED/GP23

72

PWRCTL#/GP31

73

SUSCIN/GP30

18

CLKIN

61

VSB

74

VBAT

28

VCC3

12

VCC_1

48

VCC_2

77

VCC_3

114

VCC_4

W83627HF

SIO

RSMRST#/GP33

DRVDEN0
DRVDEN1

INDEX#

MOA#

DSB#
DSA#

MOB#

DIR#

STEP#

WRDATA#

WE#

TRACK0#

WP#

RDDATA#

HEAD#

DSKCHG#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

PE

BUSY

ACK#
SLIN#
INIT#

ERR#

AFD#

STB#

IRRX/GP25

CIRRX/GP34

IRTX/GP26

SUSCLKIN

DCDA#
DSRA#

SINA

RTSA#

SOUTA

CTSA#
DTRA#

RIA#

DCDB#
DSRB#

SINB

RTSB#

SOUTB

CTSB#
DTRB#

RIB#

GA20

KBRST

KBDATA

KBCLK

MSDATA

MSCLK

KBLOCK#

PWROK/GP32

VSS1

VSS2

VSS3

VSS4

1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17

RN6
8P4R-33

RN4
8P4R-33

SLCT
PE

BUSY
ACK#
ERR#
AFD#
SLIN#
INIT#

R166 33
IRRX
IRTX

RTSA#
SOUTA

SOUTB

1 2
3 4
5 6
7 8
7 8
5 6
3 4
1 2

8P4R-33
RN11

8P4R-33

RSMRST#

RN12

42
41
40
39
38
37
36
35

SLCT

31

PE

32

BUSY

33

ACK#

34

SLIN#

43

INIT#

44

ERR#

45

AFD#

46
47

88
69
87
75

56
50
53
51
54
49
52
57

84
79
82
80
83
78
81
85

59
60
63
62
66
65
58

70
71

20
55
86
117

LP_D0
LP_D1
LP_D2
LP_D3
LP_D4
LP_D5
LP_D6
LP_D7
7 8
5 6
3 4
1 2
1 2
3 4
5 6
7 8

DRVDEN0 {21}
DRVDEN1 {21}
INDEX# {21}
MOT_A# {21}
DRV_B# {21}
DRV_A# {21}
MOT_B# {21}
DIR# {21}
STEP# {21}
WT_DT# {21}
WT_EN# {21}
TRACK0# {21}
WP# {21}
RDATA# {21}
HEAD# {21}
DSKCHG# {21}

LP_SLCT {21}
LP_PE {21}
LP_BUSY {21}
LP_ACK# {21}
LP_ERR# {21}
LP_AFD# {21}
LP_SLIN# {21}
LP_INIT# {21}

LP_STB# {21}
IRRX {17}
IRTX {17}

SUSCLK {10}
DCDA# {21}

DSRA# {21}
SINA {21}
RTSA# {21}
SOUTA {21}
CTSA# {21}
DTRA# {21}
RIA# {21}

DCDB# {21}
DSRB# {21}
SINB {21}
RTSB# {21}
SOUTB {21}
CTSB# {21}
DTRB# {21}
RIB# {21}

A20GATE# {9}
KB_RST# {9}
KBDATA {21}
KBCLK {21}
MSDATA {21}
MSCLK {21}

RSMRST# {10}

LP_D[0..7] {21}

THERMAL RESISTOR BLOCK

VTIN_VCC

R233
10KST

RT1
X_R-TD-C0603

NOTE: LOCATE INSIDE
SOCKET478

+12V

-12V

-5V

FB18 120S/0805
CB124 104P

TMP_VREF

CPU_TMP

VTIN_GND

TMP_VREF

R199 28KST
R212 232KST
R209 120KST

VTIN_GND

R216
30KST

VTIN_GND

NOTE: LOCATE CLOSE
STATUS PANEL

CPU_TMPA

12

R200
10KST

DECOUPLING CAPACITOR

VCC3 VCC5

CB100
104P
CB119
104P

VCC5

FB17
120S

TMP_VREF

R224
10KST

SYS_TMP

RT2
R-TD-C0603

VTIN_GND

+12VIN

-12VIN

-5VIN

12

R208
56KST

TMP_VREF

CB128
104P
CB143
104P
CB2
104P
CB126
104P

12

R213
56KST

SPEAKER BLOCK

VCC5

R237
10K

BEEP

R242

B

4.7K
Q25

2N3904S

SUPER I/O STRAPPING RESISTOR

R164 4.7K

VCC5

R191 X_4.7K

VCC5

R165 X_4.7K

VCC5

SOUTA

L: Disable KBC H: Enable KBC

SOUTB

L: 24MHZ H: 48MHZ

RTSA#

L: CFAD=2E H: CFAD=4E

DTRA# L: PNP Default H: PNP no Default

VBAT

CB113
104P

VCC5_SB

CB112
104P

CE

SOUTA
SOUTB
RTSA#

ALARM {17}

Title
Document Number

Micro Star Restricted Secret

LPC I/O W83627HF

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jun g-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6506

Last Revision Date:

Sheet

Tuesday, July 03, 2001

11 33

of

Rev

0B

R245 0

VCC3

AC_SDOUT{10,13}

AC_BCLK{10,13}
AC_SDIN0{10,13}
AC_SYNC{10,13}

AC_RST#{10,13}

R251 22
C128
27P

VCC5

21

R234 X_0

AUDIO CODE CD / AUX / MODEM IN HEADERS

JPHN1

MODEM IN

AUX IN

CD IN

JAUX1
YJ104-BY

YJ104-B

JCD1

YJ104-BG

4
3
2
1

AUXL AUXLX

1
2
3
4

R207 10K
R196 10K

CDL

R195 0

1
2

CDGND

R194 0

3
4

CDR

R193 0

12

12

12

12

CDGND1
CDR1

C129 104P

XTALIN
XTALOUT

C146
E_104P

MONO_OUT

C149
105P/0805

C112
105P/0805

C118
105P/0805

C111
105P/0805

R204 10K
R202 10K
R201 10K

+5VR

C109
475P/0805

R274 4.7K

VDD3

1
2
3
4

5
6
7
8

9
10
11

12

MONO_PHONE

AUXRXAUXR

C117
105P/0805
C116
105P/0805
C115
105P/0805

ST9756 AC97 CODEC

JSP1

123

L_D1x3-BK

R190
1K

R265
0

4847464544424140394338

NC

NC

TEST6

TEST5

TEST4

TEST1

AUXL

AUXR

CDLXCDL1
CDGNDX
CDRX

VIDEOL

VIDEOR

AVSS2

CDL

DACOUTR

CDGND

DVDD1
XTL_IN
XTL_OUT
DVSS1

SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET#

PC_BEEP

PHONE

1314151617181920212223

12
12
12

R264
X_0

TEST2

DACOUTL

CDR

MIC1

AVDD2

MIC2

MONO_OUT

37

MONO

LINL

24

VREF_OUT

C126

1 2

105P/0805

LOUTR

LOUTL

NC
NC

VRDA
VRAD

AFILT2
AFILT1

NC

VREF

AVSS1
AVDD1

LINR

STAC9756T

C114

C113

U14

36
35

34
33

32
31

30
29

28
27
26

25

+5VR

CB144
104P

12

C125
X_103P

+5VR

CB155

1 2

104P

LINE_ROUT
LINE_LOUT

VREF_OUT

12

CT31

1 2

ELS10/16-B

LIN_IN_R

105P/0805

LIN_IN_L

105P/0805

R206 33K 1 2
R203 33K

R205 X_01 2

R230

1 2

220

R292
100RST

R287
300RST

+5VR

AUDIO CODE REGULATORS

12

C154

105P

-12V

12

CB186
104P

R291
22/1206

-12VR

1 2

C156

X_105P

+12VR

12

R286
22/1206

CB169
104P

+12V

12

105P

C157

U17
YLT1087S-0.8A

3 2

VIN VOUT

VOUT

ADJ

SOT223

1

4

AUDIO CODE CRYSTAL CIRCUIT

24.576MHZ

12

R252

1 2

10M
X2

1 2

C139

1 2

R198
33K

R192
33K

R236

2.2K

12

C136
820P

C108
102P

R197

12

2.2K

X_224P

C137
105P

LINE_R

LINE_L

12

C143
105P

C106

102P

X_ELS10/16-B

C107
102P

12

12

12

+

12

CT32

C131

+

C130
104P

1 2

104P

ELS10/16-B

+5VR

MIC_IN

C132
820P

1 2

1 2

1 2
C144

104P

12

+

CT34

C105
102P

12

C142
473P

J3C
19
18
17
16
28

YCN15F-001-1

J3B
27
26
25
24
29

YCN15F-001-1

12

C145
X_105P/0805

C133
22P

DECOUPLING CAPACITOR

FB16 X_60S

12

12

VDD3

CB150
104P

XTALINXTALOUT

C138
22P

R124 22K
R232 22K

JYS_PB3
JYS_AX2
MID_OUT
JYS_AX3
JYS_PB2

MID_IN

C79
100P

7
5
3
1

RN7

8P4R-2.2K
1 2
3 4
5 6
7 8

CN17
8P4C-103P

POLY SWITCH

YFUSE1.1AS-P

VCC5

FS3

CB123
104P

JYS_PB0

JYS_PB0{11}

JYS_AX0

JYS_AX0{11}

JYS_AX1

JYS_AX1{11}

JYS_PB1

JYS_PB1{11} MID_IN {11}

GAME/MIDI CONNECTOR

L3 0/0805

CB84
104P

R145

2.2K
R143

2.2K

L5
0

RN8

JYS_AX0
JYS_AX1
JYS_AX2
JYS_AX3

8P4R-1M
1
3
5
7

2
4
6
8

CB83
39P

1
2
3
4
5
6
7
8

J3A

YCN15F-001-1

9
10
11
12
13
14
15

JYS_PB1
JYS_PB2
JYS_PB3
JYS_PB0

CB80
104P

R138 2.2K
R235 2.2K
R133 2.2K

R129 2.2K

CN14

8P4C-103P
7
5
3
1

JYS_PB1
JYS_PB0
JYS_PB2
JYS_PB3

MID_IN
MID_OUT

C127
100P

8
6
4
2

JYS_AX3
JYS_AX2
JYS_AX1
JYS_AX0

8
6
4
2

VCC5

JYS_PB3 {11}
JYS_AX2 {11}
MID_OUT {11}
JYS_AX3 {11}
JYS_PB2 {11}

LINE_ROUT

LINE_LOUT

C148

105P/0805

C147

105P/0805

LOUTR

LOUTL

R275

1 2

33K

R294

1 2

33K

C158

1 2

105P

C160

1 2
105P

2

5
6

+

-

+12VR

-12VR

+

-

8 4

8 4

-12VR

U16A
TL072S3

U16B
TL072S

1

1 2

1 2

7

+12VR

1 2

1 2

SPEAKER OUT JACK

R277

1 2

0/0805

R276
47K
C153
47P

R285

1 2

0/0805

R290
47K
C162
47P

FB15

1 2

30S/0805

FB14

1 2

30S/0805

SPEAKER_R

12

C104
102P

SPEAKER_L

12

C103
102P

Micro Star Restricted Secret

Title

AC97 CODEC AD1885

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

J3D
23
22
21
20
30

YCN15F-001-1

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

12 33

of

Rev

0B

FWH INIT Signal Voltage Translation Block

VCC3

VCC5

R296

Firware Hub (FWH)

Trace
Width

VCC3

C174

PCIRST#1{4,7,11}

RECOVERY{10}

SD_DET{4}
PD_DET{4}

GP23{10}

LAD0/FWH0{10,11}
LAD1/FWH1{10,11}
LAD2/FWH2{10,11}

104P
F_GPI3
RECOVERY
SD_DET
PD_DET

R342
X_4.7K

U19

21

1

VPP

2

RST#

3

FGPI3

4

FGPI2

5

FGPI1

6

FGPI0

7

WP#

8

TBL#

9

ID3

10

ID2

11

ID1

12

ID0

13

FWH0

14

FWH1

15

FWH2

16 17

GND FWH3

YSKT032PLCC

FGPI4
IC(VIL)

GNDA
VCCA

INIT#
FWH4

VCC

CLK

GND
VCC

RFU
RFU
RFU
RFU
RFU

VCC3

32
31

R313 10K

30

R314 10K

29
28
27
26
25
24
23
22
21
20
19
18

FINIT#

FWH_PCLK {4}

LFRAME#/FWH4 {10,11}

LAD3/FWH3 {10,11}

HINIT#{5,9}

R272 4.7K

FWH RESISTORS

F_GPI3
RECOVERY

PD_DET
SD_DET

8.2K

CE

Q32

B

2N3904S

R337 10K
R339 10K

R343 10K
R340 10K

R298
1K

FINIT#

CE

Q33

B

2N3904S

FWH DECOUPLING CAPACITORS

VCC3

CB171

CB172

CB181

104P

104P

104P

CB180
104P

CNR RISER

CNR1

B1

RESV1

B2

RESV2

B3

RESV3

B4

GND1

B5

RESV4

B6

RESV5

B7

CNR_TXD1{9}

CNR_RST{9}

CNR_RXD2{9}
CNR_RXD0{9}

CNR_OC#1{18}

SHCLK{9}

SMBCLK{4,10,11,14}

AC_SYNC{10,12} AC_SDIN1 {10}

AC_SDOUT{10,12}

AC_BCLK{10,12}

CNR_TXD1
CNR_RST

CNR_RXD2
CNR_RXD0

VCC5_SB

CNR_OC#1

-12V

VCC3

DIN

DIN{9}

SHCLK

VCC3

DN#

R254
0

AC_SDOUT
R348 33

X_10PC177

GND2

B8

LAN_TXD1

B9

LAN_RSTSYNC

B10

GND3

B11

LAN_RXD2

B12

LAN_RXD0

B13

GND4

B14

RESV6

B15

+5VDUAL

B16

USB_OC#

B17

GND5

B18

-12V

B19

+3.3VD

B20

GND6

B21

EE_DOUT

B22

EE_SHCLK

B23

GND7

B24

SMB_A0

B25

SMB_SCL

B26

PRIMARY_DN#

B27

GND8

B28

AC97_SYNC

B29

AC97_SDATA_OUT

B30

AC97_BITCLK

CNR-D60

AC97_SDATA_IN1
AC97_SDATA_IN0

RESV7
RESV8

GND9

RESV9

RESV10

GND10
LAN_TXD2
LAN_TXD0

GND11

LAN_CLK

LAN_RXD1

RESV11

USB+

GND12

USB­+12V

GND13

+3.3VDUAL

+5VD

GND14

EE_DIN

EE_CS

SMB_A1
SMB_A2

SMB_SDA

AC97_RESET#

RESV12

GND15

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30

CNR_TXD2
CNR_TXD0

CNR_CLK
CNR_RXD1

+12V

VCC5

DOUT
CS

VCC3

AC_RST#

R321
10K

CNR_TXD2 {9}
CNR_TXD0 {9}

CNR_CLK {9}
CNR_RXD1 {9}

CNR_USB1+ {10}
CNR_USB1- {10}

DOUT {9}
CS {9}

SMBDATA {4,10,11,14}
AC_RST# {10,12}

AC_SDIN0 {10,12}

R320
10K

C166

104P

VCC3_SB

Title
Document Number

Micro Star Restricted Secret

FWH & CNR & AC'97 Control

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jun g-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6506

Last Revision Date:

Sheet

Tuesday, July 03, 2001

13 33

of

Rev

0B

5

4

3

2

1

DIMM1 DIMM2

MD[0..63]{8}

D D

C C

MA[0..12]{8}

B B

A A

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7

MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15

MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23

MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12

MBS0{8}
MBS1{8}

MRAS#

MRAS#{8}

MCAS#

MCAS#{8}

MCS#0{8}
MCS#1{8}
MCS#2{8}
MCS#3{8}

MWE# MWE#

MWE#{8}

MCLK0

MCLK0{8}

MCLK1

MCLK1{8}

MCLK2

MCLK2{8}

MCLK3

MCLK3{8}

5

DIM1

2

D0

3

D1

4

D2

5

D3

7

D4

8

D5

9

D6

10

D7

11

D8

13

D9

14

D10

15

D11

16

D12

17

D13

19

D14

20

D15

55

D16

56

D17

57

D18

58

D19

60

D20

65

D21

66

D22

67

D23

69

D24

70

D25

71

D26

72

D27

74

D28

75

D29

76

D30

77

D31

33

A0

117

A1

34

A2

118

A3

35

A4

119

A5

36

A6

120

A7

37

A8

121

A9

38

A10/AP

123

A11/A13

126

A12/DU

132

A13/DU

122

BA0/A11

39

BA1/A12

115

-RAS

111

-CAS

30

-RAS0/S0

114

-RAS1/S1

45

-RAS2/S2

129

-RAS3/S3

28

DQM0/-CAS0

29

DQM1/-CAS1

46

DQM2/-CAS2

47

DQM3/-CAS3

112

DQM4/-CAS4

113

DQM5/-CAS5

130

DQM6/-CAS6

131

DQM7/-CAS7

27

-WE0

48

-WE2

42

CLK0

125

CLK1

79

CLK2

163

CLK3

DIMM-D168-BK-SN

D32
D33
D34
D35
D36
D37
D38
D39

D40
D41
D42
D43
D44
D45
D46
D47

D48
D49
D50
D51
D52
D53
D54
D55

D56
D57
D58
D59
D60
D61
D62
D63

MDP0
MDP1
MDP2
MDP3
MDP4
MDP5
MDP6
MDP7

REGE

CKE0
CKE1

SDL
SDA

SA0
SA1
SA2

WP

NC
NC
NC

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

86
87
88
89
91
92
93
94

95
97
98
99
100
101
103
104

139
140
141
142
144
149
150
151

153
154
155
156
158
159
160
161

21
22
52
53
105
106
136
137

147
128
63

83
82

165
166
167

81
44
62
146

6
18
26
40
41
49
59
73
84
90
102
110
124
133
143
157
168

MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39

MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47

MD48
MD49
MD50

MD51
MD52
MD54
MD53

MD55

MD56

MD57

MD58

MD59

MD60

MD61

MD62

MD63
MDP0

MDP1
MDP2
MDP3
MDP4
MDP5
MDP6
MDP7

SMBCLK
SMBDATA

DIMM_WP

MDP[0..7] {8}

MCKE0 {8}
MCKE1 {8}

SMBCLK {4,10,11,13}
SMBDATA {4,10,11,13}

VCC_DIMM

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7

MD8
MD9
MD10
MD11

MD12
MD13
MD14
MD15

MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23

MD24

MD25

MD26

MD27

MD28

MD29

MD30

MD31

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

MA10

MA11

MA12

MBS0

MBS1

MRAS#

MCAS#
MCS#4

MCS#4{8}

MCS#5

MCS#5{8}

MCS#6

MCS#6{8}

MCS#7

MCS#7{8}

MCLK4

MCLK4{8}

MCLK5

MCLK5{8}

MCLK6

MCLK6{8}

MCLK7

MCLK7{8}

ADDR.=1010000B ADDR.=1010001B

4

DIM2

2

D0

3

D1

4

D2

5

D3

7

D4

8

D5

9

D6

10

D7

11

D8

13

D9

14

D10

15

D11

16

D12

17

D13

19

D14

20

D15

55

D16

56

D17

57

D18

58

D19

60

D20

65

D21

66

D22

67

D23

69

D24

70

D25

71

D26

72

D27

74

D28

75

D29

76

D30

77

D31

33

A0

117

A1

34

A2

118

A3

35

A4

119

A5

36

A6

120

A7

37

A8

121

A9

38

A10/AP

123

A11/A13

126

A12/DU

132

A13/DU

122

BA0/A11

39

BA1/A12

115

-RAS

111

-CAS

30

-RAS0/S0

114

-RAS1/S1

45

-RAS2/S2

129

-RAS3/S3

28

DQM0/-CAS0

29

DQM1/-CAS1

46

DQM2/-CAS2

47

DQM3/-CAS3

112

DQM4/-CAS4

113

DQM5/-CAS5

130

DQM6/-CAS6

131

DQM7/-CAS7

27

-WE0

48

-WE2

42

CLK0

125

CLK1

79

CLK2

163

CLK3

DIMM-D168-BK-SN

MD32

86

D32

MD33

87

D33

MD34

88

D34

MD35

89

D35

MD36

91

D36

MD37

92

D37

MD38

93

D38

MD39

94

D39

MD40

95

D40

MD41

97

D41

MD42

98

D42

MD43

99

D43

MD44

100

D44

MD45

101

D45

MD46

103

D46

MD47

104

D47

MD48

139

D48

MD49

140

D49

MD50

141

D50

MD51

142

D51

MD52

144

D52

MD54

149

D53

MD53

150

D54

MD55

151

D55

MD56

153

D56

MD57

154

D57

MD58

155

D58

MD59

156

D59

MD60

158

D60

MD61

159

D61

MD62

160

D62

MD63

161

D63

MDP0

21

MDP0
MDP1
MDP2
MDP3
MDP4
MDP5
MDP6
MDP7

REGE

CKE0
CKE1

3

SDL
SDA

SA0
SA1
SA2

WP

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

MDP1

22

MDP2

52

MDP3

53

MDP4

105

MDP5

106

MDP6

136

MDP7

137
147

128
63

83
82

165
166
167

81
44

NC

62

NC

146

NC

6
18
26
40
41
49
59
73
84
90
102
110
124
133
143
157
168

SMBCLK
SMBDATA

DIMM_WP

VCC_DIMMVCC_DIMM

MCKE2 {8}
MCKE3 {8}

VCC_DIMM

VCC_DIMM

VCC_DIMM

2

DIMM CLOCK

MCLK0
MCLK1
MCLK2
MCLK3
MCLK4
MCLK5
MCLK6
MCLK7

R91 49.9RST
R94 49.9RST
R71 49.9RST
R73 49.9RST
R92 49.9RST
R95 49.9RST
R77 49.9RST
R75 49.9RST

270PC55
270PC60
270PC30
270PC23
270PC56
270PC61
270PC38
270PC33

DECOUPLING CAPACITORS

VCC_DIMM VCC_DIMM

+

VCC_DIMM

VCC_DIMM

CT25
EL1000/6.3
CB74
104P
CB88
104P
CB52
100P
CB60
105P
CB69
105P
CB40
100P

CB61 104P
CB71 104P
C83 104P

CB53 104P

+

DIMM SPD WE BLOCK

R67 4.7K

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jun g-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

DIMM_WP

Micro Star Restricted Secret

DIMM 1 & 2

CT15
EL1000/6.3
CB104
104P
CB75
104P
CB28
105P
CB105
105P
CB54
100P
CB68
100P

VCC3

VCC5

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

14 33

1

Rev

0B

of

8

7

6

5

4

3

2

1

AGP SIGNAL REFERENCE CIRCUIT

D D

INTB#{9,16}

AGPCLK{4}

GREQ#{8} GGNT# {8}

ST2{8}

RBF#{8}

SBA0{8}
SBA2{8}

GAD_STB1{8}

GDEVSEL#{8}

GAD_STB0{8}

GC_BE#2{8}

GIRDY#{8}

GC_BE#1{8}

AGPREF{8}

SB_STB{8}

SBA4{8}
SBA6{8}

GAD31{8}
GAD29{8}

GAD27{8}
GAD25{8}

GAD23{8}
GAD21{8}

GAD19{8}
GAD17{8}

GAD14{8}
GAD12{8}

GAD10{8}

GAD8{8}

GAD7{8}
GAD5{8}

GAD3{8}
GAD1{8}

VREF_GC:form
the chipset
to the
graphics
controller

C C

B B

A A

VCC5 = 60mils trace / 15 mils space

GAD[0..31] {8}
SBA[0..7] {8}

AGP1

B1

-OVRCNT

VCC5
VCC3

GREQ#

RBF#

SB_STB

VCC3_SB

GAD_STB1

VCC_AGP

GIRDY#

GDEVSEL#
GPERR#
GSERR#

GAD_STB0

AGPREF

B2

5V

B3

5V

B4

USB+

B5

GND

B6

-INTB

B7

CLK

B8

-REQ

B9

3.3V

B10

ST0

B11

ST2

B12

-RBF

B13

GND

B14

RESERVED

B15

SBA0

B16

3.3V

B17

SBA2

B18

SB_STB

B19

GND

B20

SBA4

B21

SBA6

B22

RSVD/KEY

B23

GND/KEY

B24

AUX3V/KEY

B25

3.3V/KEY

B26

AD31

B27

AD29

B28

3.3V

B29

AD27

B30

AD25

B31

GND

B32

AD_STB1

B33

AD23

B34

VDDQ

B35

AD21

B36

AD19

B37

GND

B38

AD17

B39

C/-BE2

B40

VDDQ

B41

-IRDY

B42

AUX3V/KEY

B43

GND/KEY

B44

RSVD/KEY

B45

3.3V/KEY

B46

-DEVSEL

B47

VDDQ

B48

-PERR

B49

GND

B50

-SERR

B51

C/-BE1

B52

VDDQ

B53

AD14

B54

AD12

B55

GND

B56

AD10

B57

AD8

B58

VDDQ

B59

AD_STB0

B60

AD7

B61

GND

B62

AD5

B63

AD3

B64

VDDQ

B65

AD1

B66

VREF_CG

AGP-D124-BN_1.5V

AGP Slot Imax
VCC_AGP 8.0A

VCC3 6.0A
VCC12 1.0A
VCC5 2.0A

12V

-TYPEDET

RESERVED

USB-

GND

-INTA

-RST

-GNT

3.3V
ST1

RESERVED

-PIPE
GND

-WBF

SBA1

3.3V

SBA3

-SB_STB
GND

SBA5
SBA7

RSVD/KEY

GND/KEY

RSVD/KEY

3.3V/KEY
AD30
AD28

3.3V
AD26
AD24

GND

-AD_STB1
C/-BE3

VDDQ

AD22
AD20

GND
AD18
AD16

VDDQ

-FRAME

RSVD/KEY

GND/KEY

RSVD/KEY

3.3V/KEY

-TRDY

-STOP

-PME

GND

PAR
AD15

VDDQ

AD13
AD11

GND

AD9

C/-BE0

VDDQ

-AD_STB0
AD6

GND

AD4
AD2

VDDQ

AD0

VREF_GC

A1

+12V

A2
A3
A4
A5
A6
A7

GGNT#

A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66

VCC3

PIPE#
WBF#

SB_STB#

GAD_STB#1

VCC_AGP

GFRAME#

GTRDY#
GSTOP#

GPAR

GAD_STB#0

VREF_GC:form
the graphics
controller to
the chipset

INTA# {9,16}
PCIRST#2 {4,16}

ST1 {8}ST0{8}
PIPE# {8}
WBF# {8}

SBA1 {8}
SBA3 {8}

SB_STB# {8}
SBA5 {8}

SBA7 {8}

GAD30 {8}
GAD28 {8}

GAD26 {8}
GAD24 {8}

GAD_STB#1 {8}
GC_BE#3 {8}

GAD22 {8}
GAD20 {8}

GAD18 {8}
GAD16 {8}

GFRAME# {8}

GTRDY# {8}
GSTOP# {8}
PME# {9,16}

GPAR {8}
GAD15 {8}

GAD13 {8}
GAD11 {8}

GAD9 {8}
GC_BE#0 {8}

GAD_STB#0 {8}
GAD6 {8}

GAD4 {8}
GAD2 {8}

GAD0 {8}

Internal Pull-Up
Internal Pull-Up
Internal Pull-Up
Internal Pull-Up

Internal Pull-Up

Internal Pull-Up

VCC_AGP

AGP UNIVERSAL 2X/4X SLOT(AGP VER:2.0 COMPLY)

C120 X_470p

R223
X_82

R220
X_82

C119 X_470p

GIRDY#
GFRAME#
GTRDY#
GDEVSEL# GAD_STB0

GSTOP#
GPERR#
GPAR
GSERR#
GREQ#
GGNT#

ST0
ST1
ST2

+ CT28

EL1000/6.3
CB134
104P
CB120
103P
CB136
104P

8
6
4
2

8
6
4

2
R179 6.8K
R180 6.8K

R174 6.8K
R175 6.8K
R176 6.8K

INTA#
INTB#

8

7

6

5

4

VCC_AGP

R221
1KST

R222
1KST

C102
105P

AGPREF: 10uA

AGPREF

CB138
104P

NEAR AGP SLOT

AGP TERMINATION RESISTORS

VCC_AGP

7

RN13

5

8P4R-6.8K

3
1

7

RN14

5

8P4R-6.8K

3
1

Internal Pull-Up
Internal Pull-Up
Internal Pull-Up
Internal Pull-Up
Internal Pull-Up
Internal Pull-Up

Internal Pull-Down
Internal Pull-Down
Internal Pull-Down

PIPE#
RBF#
WBF#

GAD_STB1
SB_STB

GAD_STB#1
GAD_STB#0
SB_STB#

LESS 10MILS STUB TRACE LENGTH MUST BE FOLLOWING.

Place these resistors between PCI and AGP slot

AGP SLOT DECOUPLING CAPACITORS

CB118
100P
CB115
104P
CB137
104P
CB106
104P
CB133
105P

+12V

CB114
104P

3

CB131
104P

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

VCC_AGP

R181 X_6.8K
R177 X_6.8K
R182 X_6.8K
R178 X_6.8K
R218 X_6.8K
R173 X_6.8K

R219 X_6.8K
R184 X_6.8K
R183 X_6.8K

VCC5VCC3_SB

+ CT35

EL1000/6.3
CB183
104P
CB178
100P

VCC3VCC_AGP

Micro Star Restricted Secret

AGP SLOT

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

2

Sheet

+ CT20

EL1000/6.3
CB129
104P
CB132
104P
CB117
104P
CB130
104P
CB7
100P

+ CT37

EL1000/6.3

15 33

1

Rev

0B

of

8

7

6

5

4

3

2

1

PCI SLOT 1 (PCI VER: 2.2 COMPLY) PCI SLOT 2 (PCI VER: 2.2 COMPLY)

AD[0..31]{9}

D D

INTB#{9,15}

INTD#{9}

PCICLK0{4}

PREQ#0{9}

AD31{9}
AD29{9}

AD27{9}
AD25{9}

C_BE#3{9}

C C

B B

AD23{9}
AD21{9}

AD19{9}
AD17{9}

C_BE#2{9}

IRDY#{9}

DEVSEL#{9}

PLOCK#{9}

PERR#{9}
SERR#{9}

C_BE#1{9}

AD14{9}
AD12{9}

AD10{9}

AD8{9}
AD7{9}

AD5{9}
AD3{9}

AD1{9}

-12V
PCI1

B1

B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

B2
B3
B4
B5
B6
B7
B8
B9

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V

YSLOT120

RESERVED

+5V(I/O)

RESERVED

RESERVED

+5V(I/O)

RESERVED

FRAME#

+5V(I/O)

REQ64#

PTCK

VCC5 VCC5

PRST#11
PRST#12 PRST#22

VCC3

ACK#64

TRST#

+12V

TMS

TDI

+5V
INTA#
INTC#

+5V

GND

GND
RST#
GNT#

GND

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL

+3.3

AD22
AD20

GND

AD18
AD16

+3.3V

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13
AD11

GND

AD9

C/BE#0

+3.3V

AD6
AD4

GND

AD2
AD0

+5V
+5V

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

+12V

PTRST#
PTMS

PTDI

VCC5

VCC3

INTA# {9,15}
INTC# {9}

VCC3_SB

PCIRST#2 {4,15}
PGNT#0 {9}
PME# {9,15}

AD30 {9}
AD28 {9}

AD26 {9}
AD24 {9}

AD22 {9}
AD20 {9}

AD18 {9}
AD16 {9}

FRAME# {9}
TRDY# {9}
STOP# {9}
SM_LNK0 {10}

SM_LNK1 {10}
PAR {9}

AD15 {9}
AD13 {9}

AD11 {9}
AD9 {9}

C_BE#0 {9}
AD6 {9}

AD4 {9}
AD2 {9}

AD0 {9}

REQ#64

R269 100

AD16

PTCK

INTG#
INTE#

PCICLK1{4}

PREQ#1{9}
AD31

AD29
AD27

AD25
C_BE#3

AD23
AD21

AD19
AD17

C_BE#2
IRDY#
DEVSEL#
PLOCK#

PERR#
SERR#
C_BE#1

AD14
AD12

AD10

AD8
AD7

AD5
AD3

AD1
ACK#64

PRST#21

VCC3

-12V

B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

B1
B2
B3
B4
B5
B6
B7
B8
B9

PCI2

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V

YSLOT120

TRST#

+12V
TMS

TDI

+5V
INTA#
INTC#

+5V

RESERVED

+5V(I/O)

RESERVED

GND
GND

RESERVED

RST#

+5V(I/O)

GNT#

GND

RESERVED

AD30

+3.3V

AD28
AD26
GND
AD24

IDSEL

+3.3
AD22
AD20
GND
AD18
AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13
AD11
GND

AD9

C/BE#0

+3.3V

AD6

AD4

GND

AD2

AD0

+5V(I/O)

REQ64#

+5V

+5V

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

+12V

VCC3

VCC5

PTRST#
PTMS

PTDI
INTF#

INTH#

VCC3_SB

PCIRST#2

PGNT#1 {9}
PME#

AD30
AD28

AD26
AD24

R310 100
AD22

AD20
AD18

AD16
FRAME#
TRDY#
STOP#
SM_LNK0

SM_LNK1
PAR

AD15
AD13

AD11
AD9

C_BE#0
AD6

AD4
AD2

AD0
REQ#64

AD17

IDSEL = AD16 IDSEL = AD17

MASTER = PREQ1MASTER = PREQ0

PCI PULL-UP / DOWN RESISTORS

RN18

INTA#
INTD#
INTC#
INTB#

8P4R-2.7K

1 2
3 4
5 6
7 8

RN17
8P4R-2.7K

1 2
3 4
5 6
7 8

RN20

1

1

2

2

3

3

4

4

6

6

7

7

8

8

9

9510

10P8R-2.7K

RN21

1

1

2

2

3

3

4

4

6

6

7

7

8

8

9

9510

X_2.7K-10P8R

R247 4.7K
R281 4.7K

R282 4.7K
R283 4.7K

R267 4.7K
R284 4.7K

RN22

8P4R-8.2K
1 2
3 4
5 6
7 8

RN19

8P4R-8.2K
1 2
3 4
5 6
7 8

2 1
2 1

2 1

VCC5

5

VCC5

10

5

VCC3

10

VCC5

VCC3

VCC3

X_104PC152
X_104PC151
X_104PC1642 1
X_104PC165

FRAME#
IRDY#
TRDY#
DEVSEL#

STOP#
PLOCK#
PERR#
SERR#

PREQ#0
PREQ#2

PREQ#2{9}

PREQ#3

PREQ#3{9}

PREQ#1
PREQ#4

PREQ#4{9}

PREQ#5

PREQ#5{9}

PGNT#2

PGNT#2{9}

PGNT#1
PGNT#3

PGNT#3{9}

PGNT#0
PGNT#4

PGNT#4{9}

PGNT#5

PGNT#5{9}

REQ#64
ACK#64

PTMS
PTDI

PTCK
PTRST#

INTF#

INTF#{10}

INTE#

INTE#{10}

INTG#

INTG#{10}

INTH#

INTH#{10}

PRST#11
PRST#12

PRST#21
PRST#22

INTA# INTE#

A A

VCC5

8

PCI SLOT DECOUPLING CAPACITORS

VCC5

+

CT38
EL1000/6.3
CB176
104P
CB177
104P

7

CB158
104P
CB174
100P
CB161
100P

VCC3

+

VCC3

CT36
EL1000/6.3 CB175
CB187
104P
CB179
104P

6

CB162
104P
CB165
100P
CB166
100P

-12V

104P

5

+12V VCC3_SB

CB164
104P

4

C159

104P

Title
Document Number

3

Micro Star Restricted Secret

PCI Slot 1 & 2 & 3

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jun g-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

16 33

Rev

0B

of

1

5

4

3

2

1

VCC3

-12V

CB66

104P

D D

VCC3_SB

PSON#{11}

C C

R308 4.7K

CB9
33P

VCC5_SB

13 12

U18F
7407S
(VCC5_SB)

CB64

104P

ELS10/16-B

R80 4.7K

C49
X_102P

VCC5

CB56
104P

+

CT18

-PSON

CB63
33P

-5V

C40
E_104P

CT9

ELS47/16-C

11

3.3V

12

-12V

13

GND

14

PSON

15

GND

16

GND

17

GND

18

-5V

19

5V

20

CB35
33P

5V

POWER

+

Brookdale FRONT PANEL-M

PD_LED{4}
SD_LED{4}

VCC5

R323

330

HDD+
IDE_LED

FP_RST#

B B

VCC5

FOR NEC-CI

J12

1

HDD+

2

HDD-

3

GND

4

RESET#

5

+5V

IRRX{11}

IRTX{11}

6
7
8
9

IRRX
GND
IRTX
GND

YJ2090011

D7 1N4148S
D6 1N4148S

C150 470p

PLED1
PLED2

PWRSW+

GND

FP_SLP#

GND

IR_PWR

CHASSIS

IDE_LED

R305
0

BC1
X_104P

PLED1
PLED2
PWRSW

10
11
12
13
14
15

17
18

3.3V

3.3V
GND

5V

GND

5V
GND
POK

5VSB

12V

X_102P

EXTSMI# {10}

C45

1
2
3
4
5
6
7
8
9
10

CB65
33P

CB59
104P

CB44
33P

CB67
105P/0805

CB21
104P

(VCC5_SB)

11 10

CB5 39P

CB31
104P

FP_RST#{5}

VCC3

CB33
33P

U18E
7407S

+

CT6

ELS10/16-B

VCC5

CB25
X_39P

VCC5_SB
+12V

FP_RST#

VCC3

R301

4.7K
R302 33

C163
104P

U20B
74LCX14S

3 4

SM_CTRL

(VCC3_SB)

U20C
74LCX14S
5 6

ATX CONNECTOR

SM_CTRL {10}

R346 22

PWR_GD {10}

PLEDS3SUSLED

R333 330

R309 330

R326 22

VCC5

VCC5_SB

R325

4.7K

C168

105P

S0
S1

1
0
0

S5

R322 0

R318 0

U20E
74LCX14S

11 10

0

VCC5_SB

POWER BUTTON

0
1
1
0

PWR_LED {11}

SUS_LED {11}

PWRBTIN# {11}

SPEAKER

R345 100

G

R351 100

DS

Q36

NDS7002AS

ALARM{11}

SPKR{10}

R341

2.2K

D11 1N4148S
C110 104P

BUZZER-SAT1205-85dB-D

VCC5

SPK

BZ1

A A

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

Micro Star Restricted Secret

Front Panel & Connector

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

17 33

1

Rev

0B

of

E

D

C

B

A

BACK PANEL USB CONNECTOR FOR USB PORT 0,1

C24
33P

5
6
7
8
1
2
3
4

GNDA

USB3

UP

DOWN

YUSB-D1

FB11 60S
C28 104P

9
10

11
12

VCC5_STR

SVCC0

C25
33P

SBD0­SBD0+
GNDA
SVCC0
SBD1­SBD1+
GNDA

USB0-{10}

4 4

USB0+{10}

USB1-{10}
USB1+{10}

USB0­USB0+

USB1­USB1+

246

135

FB9 121S
FB10 121S

FB8 121S
FB7 121S

8

RN28
8P4R-15K

7

NEAR USB CONNECTOR

C26
33P

C27
33P

FRONT PANEL USB CONNECTOR FOR USB PORT 2,3

Ic=200mA

S_FAN1

YJ103-BO-R

3
1

USB3+
USB3-

USB2+

Q8
2N3904S

Ic=200mA

NECFAN

2

B

3 3

NEAR CHIPSET LESS THAN 1 INCH

2 2

USB3+{10}

USB3-{10}

USB2+{10}
USB2-{10}

+12V

SYSTEM FAN

1 1

SYS_FAN{11}

R11
10K

E

R12

4.7K

R10
27K

FB21 121S
FB22 121S

FB20 121S
FB19 121S

246

8

RN27
8P4R-15K

135

7

NEAR USB CONNECTOR

VCC3 +12V

R58

CE

27K

R33

1.3K

R45
160K

+12V

CE

B
Q1
2N3904S

D

OUTOUT

INPUT-

INPUT-

914101112

C172
33P

VCC

INPUT+

INPUT+

INPUT+

VEE

INPUT+

12345678

INPUT-

INPUT-

13

C171
33P

C5
103P

U3

MC33204D

OUT

OUT

R9

8.2K

R35

1.8K

SVCC1
SBD2+

SBD2-USB2-

C169

C170

33P

33P

NEC-CI FAN CONTROL

CPU_TMPA {5,11}

Ic=600mA

R4

B

7.5K

R5
470K

R18 200K

R16 240K
R7
240K

R29

5.6K

R22 33K

R28 90.9KST

+12V

Q2

CE

2N2222S

+12V

USB2
6
7
8
9

YJ2050022

NECCFAN

C

1
2
3
4
510

C_FAN1
YJ103-BO

2

SBD3+
SBD3-

CPU FAN

+12V

R26

4.7K

3

R41 27K

1

CNR_OC#1{13}

CPU_FAN {11}

R34
10K

POWER CIRCUIT FOR USB PORT 0,1

FS2

C18
470P

OC#0{10}

YFUSE1.1AS-P

C29
104P

FB6 60S/0805

R68
470K

R293
560K

NEAR USB CONNECTOR

105P

POWER CIRCUIT FOR USB PORT 2, 3

FS4

OC#1{10}

VCC5_STR

C178
470P

R344
0

B

YFUSE1.1AS-P

C179
104P

FB23 60S/0805

R350
470K

R349
560K

NEAR USB CONNECTOR

Micro Star Restricted Secret

Title

USB & FAN Connectors

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

C17

SVCC0

+

CT3
EL1000/6.3

C175
105P

MS-6506

R59
47K

SVCC1

+

CT39
EL1000/6.3

Last Revision Date:

Tuesday, July 03, 2001

Sheet

A

R324
47K

18 33

Rev

0B

of

8

POWER TRANSLATOR

VCC5_SB

Q6

1

B

234

R50

4.7K
R60

4.7K

SLP_S3#{10,11}
SLP_S5#{10}

VCC5_SB

CEC

NZT651

SPD09N05

IRLR3303
N-MOS

R40 0
R39 X_0

Q7

VCC3

D D

VCC3_SB

C C

Q9

X_FDN337N-S-SOT23

G

N-MOS

S D

C21
104P

G

S D

AGP 4X 1.5V POWER TRANSLATOR

VCC5

R160
1KST

VR3
1050CP
I31-010500B-U04

3 2

+

CT26

470U/10V

8

R159 X_1KST

VIN VOUT

1

R158
100

1

VR2

SC431L

3 2

C95
X_102P

B B

VCC3

A A

+12V

3

+

2

-

4 8

U12A
YLM358S-SOIC8

+12V

5

+

6

-

4 8

U12B
YLM358S-SOIC8

VCC1_8

ADJ

R214

332RST

R215

150RST

7

+12V

C31

3 15

4

9

R47

10K

6 10
7
5
2

13

C94
104P

1

7

VCC5_SB

105P

14

12V

3V3DLSB DRV2

3V3DL

FAULT/SEL

S3 DLA
S5
EN5VDL
EN3VDL
SS

DLA

R154

1KST

R168
1KST

VCC1_8

+ CT30

EL1000/6.3
CB149
100P
CB127
10P

7

1

8

5VSB

GND

R155

1KST

R167

210RST

C19
475P/0805

VSEN2

5VDLSB

5VDL

HIP6501A

G

G

VCC3

S D

DS

U5

16

11

12

Q20
P3055LD

IRLR3303

Q21

IPB15N03L

FDB6696

DIMMCTR

R353 0

R354
X_0

5VCTR

VCC_AGP

G

6

G

G

VCC5

6

VCC3

SD

VCC5_SB

D S

S D

N-MOS

Q13
IRLR3303-S-TO252

Q12
NDS352AP

FDN338P
P-MOS

Q14
SPD09N05

IRLR3303
N-MOS

VCC3_SB Main Standby
VCC5_STR

VCC_DIMM

+ CT5

VCC5_STR

+ CT8

VCC5_SB

R37
220/0805

1

VR1

SC431

1.05KST

3 2

C11
X_102P

1V

EL1000/6.3
CB73
104P
CB14
105P

470U/10V
CB17
104P
CB6
104P
CB16
104P

R27

R21

1KST

1.5KST

R8

1.2KST

5

S0Power S5S3

Main
Main

Standby
Standby

Standby

0V
0VVCC_DIMM

VCC_VID / VID_GOOD

+12V

3

+

1

2

-

4 8

U2A
YLM358S-SOIC8

+12V

CB1
104P

5

+

7

6

-

4 8

U2B
YLM358S-SOIC8

5

4

NOTE1 --- MCH
VCC_AGP

= VCC1_5 (1.5A) VCC_AGP (0.37A)+

NOTE2 --- DIMM
S0 STATE --- 2.0A * 3 = 6.0A ---> VCC3
S1/S3 STATE --- 200mA * 3 = 600mA ---> VCC3_SB
VCC3_SB --> 600mA*3.3V/5V=396mA --> VCC5_SB

NOTE3 --- ICH2

1.8V

1.8V_LAN 36mA
VCC1_8SB
VCC3
VCC3+562ET
VCC3_SB

VCC3_SB
VCC1_8SB
VCC5_SB

D1 X_1N4148S

R3
5K

=
=
= VCC3_SB VCC1_8SB+

R352
1K

C10

105P

4

300mA
45mA

410mA
230mA
25mA

VCC3

VCC5_SB

S0Power S3/S4/S5

S1
100mA
28mA
30mA
5mA
210mA

0.6mA

DS

Q3
NDS7002ASG

CB4
106P/1206

R36
1K

DS

Q4
NDS7002ASG

3

1.8V STANDBY POWER TRANSLATOR
(40mils trace / 20 mils space)

VR4
YLT1087S-0.8A

3 2

VIN VOUT

C135

N/A
N/A
7mA
N/A
N/A
N/A

104P

1

ADJ

C134
104P

VCCP VCC_AGP

CPU

69.0A NOTE40

PMCH

2.4A NOTE1

ICH2

0

CY28324

0

AD1885

0
0

FWH -SST
W83627HF

0
HIP6301
HIP6602A

0

HIP6601A

0
DIMM

0
AGP

0
PCI

0 0 0 0
USB

0

0

USB HUB
FAN

0
TTL

0

0

AMPLIFIER
OTHER

0 0 0 0 0 0

1.8V/3.3V SEQUENCE CIRCUIT

VCC3

R210 200

R217
200

R211
470

VCC_VID {6}

1.2V/0.1A

VID_GD {20}

3

REGULATORS OUTPUT DECOUPLING CAPACITORS

CB103

104P

CB62

105P

2

VCC1_8SBVCC3_SB

C140

C141

R253
432RST

R249
200

100P

104P

POWER CONSUMPTION

VCC1_8

VCC3_DIMM VCC3 VCC5

0

0

0.2A

0

NOTE3 NOTE3 NOTE3
0
0
0
0
000

0
0SC1547
0

0
0

0
0

B

Q23

2N3904S

+ CT1

470U/10V
CB11
104P
CB38
105P

VCC_AGPVCC3

+ CT27

0

2.0A 0 0
0

0

0

0

0

0

0

0

0
0
0

0
0

0

0

0

NOTE2

0
0

0

0

0

0

0

0

0

0

0

00

0

Q22
2N3906S
Ic=200mA

B

Vebo=5V
Vceo=40V

CE

C E

VCC1_8

VCC5

EL1000/6.3

Micro Star Restricted Secret

Title

Voltage Regulator

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

CT33
ELS47/16-C

0
0

0
0

0
0

0
0
0

6.0A 1.0A8.0A 2.0A

0
0
0

CB146
104P
CB184
105P

VCC5_SB

0
0

0
0

NOTE2

0
0
0
0
000

VCC3_SBVCC5_SB

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

0

0
0
0
0
0
0
0

?

0
0

+ CT29

19 33

1

+12V

0
0
0
0

0
0
0
0

0
0
0

0
0
0

EL1000/6.3
CB157
104P
CB10
105P
CB12
104P
CB8
104PR17

-12V

0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0

Rev

0B

of

5

4

3

2

1

CB72
104P

R15
X_0

1
2
3
4
5

19

6

7

R43 0

CHOK4 1.1uH/25A

CB70
33P

U4

VID4
VID3
VID2
VID1
VID0

PGOOD

COMP

FB

HIP6301

VCCP

VCC

GND

PWM1
ISEN1

PWM2
ISEN2FS/DIS

PWM3
ISEN3

PWM4
ISEN4

VSEN

+12VCP

20

9
15

16

14
138

11
12

18
17

10

C62
33P

VCCVID4

R20 3K

R89 3K

R14 3K

VCC

10/0805

VCC5

CT22
1800U/16V

R93

R31
0

C13
105P/0805

+12VCP

+12VCC

CB57

105P/0805

CB58
105P/0805

CB3
105P/0805

CT2
1800U/16V

+12VCC

+12VCC

R13

10/0805

CT7
1800U/16V

U8A

14

VCC

U_G1

BOOT1

PHASE1

3

GND

1

PWM1

HIP6602A

U8B

5 9

6

2

HIP6602A

U1
6
7

4

3

HIP6601A

L_G1

PVCC U_G2

BOOT2

PHASE2

PGND

PWM2

L_G2

VCC

U_G

BOOT

PVCC

PHASE

GND

PWM

L_G

C58
475P/0805

12
11

13

4

10

8

7

1
2

8

5

C32
105P/0805

R90 0/0805

C57
X_103P

R96 0/0805

C64
105P/0805

R76 0/0805

C42
X_103P

R78 0/0805

C15
105P/0805

R69 0/0805

C22
X_103P

R24 0/0805

G

G

G

G

G

C52
104P

C54
104P

C2
104P

C63
475P/0805

ATX12V POWER CONNECTOR

DS

Q18
IPD12N03L

CHOK3 1.1uH/25A

DS

Q17
IPD07N03L

DS

Q15
IPD12N03LG

CHOK2 1.1uH/25A

DS

Q16
IPD07N03L

DS

Q10
IPD12N03L

CHOK1 1.1uH/25A

DS

Q11
IPD07N03L

VCCP

CT17

CT14

CT10

CT4

SP150/2.5

4.67m Ohm

CT12
2200U/6.3V

CT16
2200U/6.3V

CT40

SP150/2.5
5020

SP150/2.5

2200U/6.3V

SP150/2.5
5020

CT19

CT42

SP150/2.5
5020

SP150/2.5

2200U/6.3V
CT47
2200U/6.3V

CT43

SP150/2.5

5020

CT48

SP150/2.5

Beside to CPU Socket Side. Under CPU Socket.

Beside to CPU Socket Solder Side.

CT11

SP150/2.5

SP150/2.5

+

CT41

SP150/2.5
5020

Under CPU Socket Solder.

CT45

CT44

SP150/2.5
5020

SP150/2.5
5020

CT46

CT13

+12VCP

D D

VID[0..4]{5,11}

R30 X_10K

VCC3

VRM_GD{10}

R2 330K

VCC5

R23 X_0

C C

VCCPS-{5}

R42 X_0

VCCPS+{5}

VID4 VID3 VID2 VID1 VID0 VDC(V)

1 1 1 1 0 1.100
1 1 1 0 1 1.125
1 1 1 0 0 1.150
1 1 0 1 1 1.175
1 1 0 1 0 1.200
1 1 0 0 1 1.225
1 1 0 0 0 1.250
1 0 1 1 1 1.275

B B

1 0 1 1 0 1.300
1 0 1 0 1 1.325
1 0 1 0 0 1.350
1 0 0 1 1 1.375
1 0 0 1 0 1.400
1 0 0 0 1 1.425
1 0 0 0 0 1.450
0 1 1 1 1 1.475

DIS

C9

X_15pF

R19
X_15K

C4

X_562P

VID3
VID2
VID1
VID0

R25 0

X_100pC7

R1 154K

R38

8.2K
C3

103P

R6

1.62KST

VID4 VID3 VID2 VID1 VID0 VDC(V)

0 1 1 1 0 1.500
0 1 1 0 1 1.525
0 1 1 0 0 1.550
0 1 0 1 1 1.575
0 1 0 1 0 1.600
0 1 0 0 1 1.625
0 1 0 0 0 1.650
0 0 1 1 1 1.675
0 0 1 1 0 1.700
0 0 1 0 1 1.725
0 0 1 0 0 1.750
0 0 0 1 1 1.775
0 0 0 1 0 1.800
0 0 0 0 1 1.825
0 0 0 0 0 1.850
1 1 1 1 1 OFF

PWM GOOD

+12VCP

VID PULL-UP RESISTORS

HIP6301V DON'T NEED PULL HIGH

A A

VID0
VID1
VID2
VID3
VID4

1
3
5
7

R54 1K

5

HIP6301 NEED PULL HIGH

2
4
6
8

VCC3

RN2
8P4R-1K

4

VID_GD{19}

G

DS

3

DIS

Q5
NDS7002AS

C70
103P

JPW1

3

4

D2x2
C59
33P

1

GND

12V

2

GND

12V

Micro Star Restricted Secret

Title

VRM 9.0

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

2

http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

20 33

Rev

0B

of

8

C39 104P

D D

VCC5
DCDA

DSRA
RXDA
CTSA
RIA

DTRA#{11}
RTSA#{11}

SOUTA{11}

U6

20

VCC

2

RIN1

3

RIN2

4

RIN3

7

RIN4

9

RIN5

16

DIN1

15

DIN2

13

DIN3

11

GND

75232-1

7

SERIAL PORT 1

1

V+

19

ROUT1

18

ROUT2

17

ROUT3

14

ROUT4

12

ROUT5

5

DOUT1

6

DOUT2

8

DOUT3

10

V-

D2
1N4148S

+12VCOM

-12VCOM
D4

1N4148S

C37 104P

DTRA
RTSA
TXDA

C36 104P

AC

A C

+12V

DCDA# {11}
DSRA# {11}
SINA {11}
CTSA# {11}
RIA# {11}

-12V

6

5

4

3

2

1

PS2 KEYBOARD & MOUSE CONNECTOR

DSRA
DCDA
RXDA
RTSA

TXDA
CTSA
DTRA
RIA

DCDA
RXDA RTSA
TXDA
DTRA

2
4
6
8

2
4
6
8

CN5B
26
27
28
29
30

LPT-D25-BK-BI

1

CN3

3

8P4C-220P

5
7

1

CN2

3

8P4C-220P

5
7

DSRA

31
32

CTSA

33

RIA

34

VCC_MS

135

7

RN1
8P4R-4.7K

246

MSDATA{11}

MSCLK{11}

KBDATA{11}

KBCLK{11}

8

135

246

7

CN1
X_22P-8P4C

8

FB3 60S
FB4 60S

FB2 60S
FB5 60S

C14
180P

MS_DT
MS_CK

KB_DT
KB_CK

C12
180P

R32
47K

7

8
11
12

1

2

5

6

C16

180P

KBMS1

YMD12P-1

C8
180P

60S/0805
FB1

C1
104P

10

9

MS

4

3

KB

PSPWR

C6
104P

FS1
YFUSE1.1AS-P
POLY SWITCH

VCC5_STR

SERIAL PORT 2

FLOPPY CONNECTOR

6

INDEX#

20

TRACK0#
WP#
RDATA#

DSKCHG#

4

DRVDEN0 {11}
DRVDEN1 {11}

INDEX# {11}
MOT_A# {11}
DRV_B# {11}
DRV_A# {11}
MOT_B# {11}
DIR# {11}
STEP# {11}
WT_DT# {11}
WT_EN# {11}
TRACK0# {11}
WP# {11}
RDATA# {11}
HEAD# {11}
DSKCHG# {11}

Title
Document Number

3

Micro Star Restricted Secret

IO Connector

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jun g-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

21 33

Rev

0B

of

1

1
2
3
4
6
7
8
9510

1
2
3
4
6
7
8
9510

+12VCOM

C71 104P

1

V+

19
18
17
14
12

-12VCOM

RN3
10P8R-2.2K

RN5
10P8R-2.2K

DTRB
RTSB
TXDB

C76 104P

5
6
8
10

V-

5

10

5

10

7

LP_INIT#
LP_SLIN#
LP_D1
LP_D2

LP_STB#
LP_AFD#
LP_D0
LP_ERR#

LP_D3
LP_D4
LP_D5
LP_D6

LP_D7
LP_ACK#
LP_BUSY
LP_PE

LP_SLCT

DCDB# {11}
DSRB# {11}
SINB {11}
CTSB# {11}
RIB# {11}

1
3
5
7

1
3
5
7

1
3
5
7

1
3
5
7

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

33PC46

6

C C

C72 104P

B B

A A

VCC5

DCDB
DSRB
RXDB
CTSB
RIB

DTRB#{11}
RTSB#{11}

SOUTB{11}

LP_D[0..7]{11}

LP_BUSY{11}

LP_ACK#{11}

LP_ERR#{11}

LP_AFD#{11}

LP_STB#{11}

LP_SLIN#{11}

LP_INIT#{11}

LP_SLCT{11}

8

U9

20

VCC

2

RIN1

3

RIN2

4

RIN3

7

RIN4

9

RIN5

16

DIN1

15

DIN2

13

DIN3

11

GND

75232-1

VCC5

LP_D6
LP_D5
LP_D4
LP_D3
LP_PE

LP_PE{11}

LP_BUSY
LP_ACK#
LP_D7

LP_ERR#
LP_D0
LP_AFD#
LP_STB#
LP_D2
LP_D1
LP_SLIN#
LP_INIT#

LP_SLCT

ROUT1
ROUT2
ROUT3
ROUT4
ROUT5

DOUT1
DOUT2
DOUT3

D3 1N4148S

1
2
3
4
6
7
8
9

1
2
3
4
6
7
8
9

R79 2.2K

DCDB
DSRB
RXDB
DTRB

RTSB
CTSB
TXDB
RIB

DCDB
RXDB RTSB
TXDB
DTRB

PARALLAL PORT

CN7
8P4C-220P

CN8
8P4C-220P

CN6
8P4C-220P

CN4
8P4C-220P

LP_STB#
LP_D0
LP_D1
LP_D2
LP_D3
LP_D4
LP_D5
LP_D6
LP_D7
LP_ACK#
LP_BUSY
LP_PE
LP_SLCT

2
4
6
8

2
4
6
8

CN5C

35
36
37
38
39

LPT-D25-BK-BI

1
2
3
4
5
6
7
8

9
10
11
12
13

1

CN11

3

8P4C-220P

5
7

1

CN12

3

8P4C-220P

5
7

40
41
42
43

CN5A

14
15
16
17
18
19
20
21
22
23
24
25

LPT-D25-BK-BI

5

DSRB
CTSB

RIB

LP_AFD#
LP_ERR#
LP_INIT#
LP_SLIN#

FDD1

1 2
3 4

7 8

9 10
11 12
13 14
15 16
17 18
19
21 22
23 24
25 26
27 28
29 30
31 32
33 34

D2x17-1:31-BK

5

PCB OTHER COMPONENT

4

3

2

1

D D

C C

B B

7

8

9
2

BS1

6
5

3

4

7

8

9
2

BS5

6
5

3

4

7

8

9
2

BS2

6
5

3

4

7

8

9
2

BS3

3

4

BS1_X1 BS2_X1 BS3_X1 BS4_X1 BS5_X1

7

8

9

6

2

5

BS4

6
5

3

4

A A

Micro Star Restricted Secret

Title

Packaging

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

22 33

Rev

0B

of

5

4

3

2

1

Jumper Setting & Connector Setting

D D

Jumper Description Connector

J3 AUDIO REAR PHONE JACK (LINE_IN, LINE_OUT, MIC_IN)

BIOS functionJP3

1-2
2-3
REMOVED

Normal
Configuration Mode
Recovery

(Default)

U3 INTEL mPGA478-B CPU
IDE1

IDE2
DIM1

DIM2
AGP1

JBAT1
1-2

JAUX1 AUDIO AUX HEADER

C C

CLEAR CMOS
NORMAL

CLEAR CMOS2-3

(Default)

PCI1
PCI2 PCI Slot2

COM1

COM2 Serial Port
JCD1 CDROM HEADER (ATAPI)
JPHN1 TELEPHONY HEADER (ATAPI)

JCS1 Chassis Instruction

KBMS1 PS/2 Keyboard and PS/2 mouse

S_FAN System FAN HEADER

USB1

USB2

POWER

B B

SIMULATION TRACE

J8

X_PIN1*2

CPU AGP

PCB1

uATX

P01-650600A
P01-650600A

A A

JCOM1
1
3 4
5 6
7 8

9 10

YCN9M-1

VCC5

2

J10

X_PIN1*2

U19-BIOS

SST49LF004
M31-49002A8-S20
<AVLBak>

JCOM2
1
3 4
5 6
7 8

9 10

YCN9M-1

5

U11-HS

E31-0400070

2

BAT1-BAT

YBA3V

4

F_P1
Pin1 Power of Hard LED

Pin2
Pin3 Hard LED
Pin4
Pin5,8,12,13
Pin6
Pin7 Reset Button
Pin9 VCC

P_FAN1 ATX FAN HEADER

3

Description

Primary
Secondary

SDRAM DIMM1
SDRAM DIMM2

AGP Slot
PCI Slot1

Serial Port

Parallel PortLPT
FloopyFDD1

CPU FAN HEADERC_FAN1

USB REAR CONNECTOR
USB INTERNAL HEADER
ATX Power
Front Panel

Power LED
Suspend LED

GND
Power Button

ATX12V PowerJPW1
SPDIF ConnectorJSP1

2

Micro Star Restricted Secret

Title

JUMPER SETTING

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

24 33

of

Rev

0B

5

4

3

2

1

Pentium 4 Processor /Northwood mPGA 478

Source Synchronous Signal Group and the Associated Strobes

Signals Associated Strobe

REQ[4:0],A[16:3]#

D D

A[31:17]#
D[15:0]#,DBI0#
D[31:16]#,DBI1#
D[47:32]#,DBI2#
D[63:48]#,DBI3#

Signals InaccuracyLength
Data
Address
Strobe
Clock

Delta=(CPU_pkglen.net-CPUpkglen.strobe)+(CS_pkglen.net-CS_pkglen.strobe)

*

2.0" to 10.0"

2.0" to 10.0"

2.0" to 10.0"

2.0" to 10.0"

Trace : 7 mil width 13mil space

Miscellaneous Signals

C C

HL_STB/HL_STB#

Taces 5mils

20mils

15mils

20mils

* Max Length : 8"
* STB and STB# Length must be equal

ADSTB0#
ADSTB1#
DSTBP0#,DSTBN0#
DSTBP1#,DSTBN1#
DSTBP2#,DSTBN2#
DSTBP3#,DSTBN3#

HL[0:10]
HL_STB

HL_STB#

HL[0:10]

+/- 100 mil
+/- 200 mil
+/- 25 mil
Don't need

HL[10..0]

20mils

15mils

20mils

* Max Length : 8"
* Length must be matched within +/- 0."
of the Strobe Signals

Others

HL[0:10]
HL[0:10]

Others

USB

* USB Trace width : 9 mils
* USB Trace Spacing : 25 mils
* Differential USB Signlas Trace

Spacing : 18 mils
* USB Power Trace must be 40mils width

B B

AGP

1X Timing group 2X/4X Timing group

AGPCLK
PIPE#
RBF#
WBF#
ST[2..0]
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GREQ#
GGNT#

A A

GPAR

SET#1
GAD[15..0]
GC_BE#[1..0]
GAD_STB0
GAD_STB0#

SET#2
GAD[31..16]
GC_BE#[3..2]
GAD_STB1
GAD_STB1#

SET#3
SBA[7..0]
SB_STB
SB_STB#

5

SIGNALS

1X Timing group
2X/4X Timing group

SET#1

2X/4X Timing group

SET#2

2X/4X Timing group

SET#3

2X/4X Timing group

SET#1

2X/4X Timing group

SET#2

2X/4X Timing group

SET#3

Maximum
Length Width Space Length

7.5"

5 mil

7.25"

5 mil

7.25"

5 mil

7.25"

5 mil

6"

5 mil

6"

5 mil

6"

5 mil

4

5 mil
20 mil
20 mil
20 mil
15 mil
15 mil
15 mil

Dismatch

X X
+/- 0.125"
+/- 0.125"
+/- 0.125"
+/- 0.25"
+/- 0.25"
+/- 0.25"

Relative to

GAD_STB0
GAD_STB0#

GAD_STB1
GAD_STB1#

SB_STB
SB_STB#

GAD_STB0
GAD_STB0#

GAD_STB1
GAD_STB1#

SB_STB
SB_STB#

Micro Star Restricted Secret

Title

Revision History - 1

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

3

2

http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

25 33

Rev

0B

of

5

CPUCLK
MCHCLK
CPUCLK#
MCHCLK#

D D

0.5" MAX 2"~ 9"

L1 L2 L4
L1 L2 L4

0"~ 0.2"

RS
RS

0"~ 0.2"

L3

4

CPU
MCH
ITP

3

L1+L2DEVICE

X
X
X

* Line Width : 7.0 mil
* Differential pair spacing : 7.0mil
* Spacing to other traces : 28 mil
* BCLK0/BCLK1 LENGTH MATCH +/- 10 mil

2

1

L3

RT

RT

GND

MCH_66
ICH_66
AGP_66

ICH_PCLK
FWH_PCLK

C C

SIO_PCLK
ISAPCLK
PCICLK[4..0]

OSC

ICH_48

B B

SIO_48

0"~ 0.5 " 4"~ 8.5"

L1 L2

0"~ 0.5 " 4"~ 8.5"

L1 L2

L1

RS

RS

RSICH_14

RS

4"~ 8.5"0"~ 0.5 "

L2L1

3"~12"0"~ 0.5 "

L2

DEVICE L1+L2

MCH
ICH

X +/- 100 mils

AGP

DEVICE L1+L2

ICH
FWH
SIO
PCI

DEVICE

X-2.5"

L1+L2

ICH

ISA BRIDGE

DEVICE L1+L2

ICH
SIO

X

X- 4"

X
X
X

Y
Y

* Line Width : 5.0 mil
* Spacing to other traces : 20 mil

* Line Width : 5.0 mil
* Spacing to other traces : 20 mil
* L1/L2 TRACE SAME AS MCH_66 TRACE LENGTH

* Line Width : 5.0 mil
* Spacing to other traces : 10 mil

* Line Width : 5.0 mil
* Spacing to other traces : 20 mil

CK 408

2.5" TO 9"- A

0.5" TO 6.5"

RN

CNR

A

LAN_PCLK

A A

ICH2

RST
RXD[2..0]
TXD[2..0]

AS SHORT AS POSSIBLE

5

Micro Star Restricted Secret

Title

CK-408 and LAN Design Guide

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

4

3

2

http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

26 33

Rev

0B

of

5

Clock Routing Guidelines

1.CPU and MCH differential host bus clock routing rule
Length A

CPUCLK,CPUCLK#
MCHCLK,MCHCLK#

D D

(Note1)

CPU clock trace
length

Max = 0.5" 0.0" - 0.2" 0.0" - 0.2" 2" - 9"

CPU clock length = A + B + D =

Length BSignal

Length C Length D

X"

4

3

2

1

3.ICH,FWH,On board device and PCI slot 33MHz clock routing rule
Width

SpacingLength F
15 mils

5 milsICH_PCLK

Y"

Width

7 mils

Spacing

7 mils
(Note2)

FWH_PCLK
DEV_PCLK
(Note1)
SLOT_PCLK
(Note2)

ICH or DEV PCI clock
trace length

Slot PCI clock
trace length

Length ESignal

4.0" - 8.5" =0.0" - 0.5"

0.0" - 0.5"

Y"

- 2.6"Y"

ICH,FWH or DEV PCI clock length = E + F =

Slot PCI clock length = E + F = Y" - 2.6"

MCH clock trace
length

CK-408

MCH clock length = A + B + D =

Host Clock

(X"+0.4") to (X"+0.6")

CPU or MCH

CK-408

33MHz Clock

E

ICH,FWH,On board
device and PCI slot

Rs

F

Rs

A
A

C C

Note1:

* The clk and clk# length matching +/-10mil of a differential clock pair
* A differential clock pair do not split up,must be keep 7mils spacing and reference to GND

Note2:

* Differential pair spacing = 7 mils
* Spacing to other trace = 28 - 35 mils

2.MCH,ICH and AGP 66MHz clock routing rule

B B

Signal

ICH_66CLK
(Note1)

(Note2)

MCH or ICH clock
trace length

AGP clock trace
length

B
B

D
D

Rs

C C

Rt Rt

Length E

0.0" - 0.5"MCH_66CLK

0.0" - 0.5"AGPCLK

MCH or ICH clock length = E + F = Y"

AGP clock length = E + F = Y" - 4"

Length F Width

4.0" - 8.5" =

- 4"Y"

Note1:33MHz trace length must be match with 66MHz of all the on board device = +/- 100 mils

Note2: Slot PCI clock trace length less than ICH PCI clock trace length = 2.6" +/- 100 mils

4.ICH and SIO 14MHz clock routing rule
Signal
ICH_14CLK 5 mils

SIO_14CLK

Length E

0.0" - 0.5"

0" - 18"

WidthLength F

Spacing
10 mils

5.ICH and SIO 48MHz clock routing rule
Signal Length E Length F Width
ICH_48CLK

SIO_48CLK

Spacing

5 mils 15 mils3" - 12"0.0" - 0.5"

Spacing

5 mils

Y"

20 mils

CK-408 MCH, ICH and AGP

66MHz Clock

Rs

E F

A A

Note1: MCH with ICH clock trace match = +/- 100 mils

Note2: AGP clock trace length less than MCH or ICH clock trace length = 4" +/- 100 mils

5

4

3

2

Micro Star Restricted Secret

Title

CLOCK Layout Guigeline

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

27 33

of

Rev

0B

5

4

3

2

1

0A Revision History

Change

Sheet

Date

GTLREF[0:3] just reference to one Reference Voltage

05/22

05/22

D D

05

GTLREF1.

Remove Processor Hot Block.

10

Add GPIO21 for Flash Vpp Programing Voltage Control.

Desciption

05/22

05/23 05

05/29

06/01

C C

13

Change U10 Vpp Circuit for 12V Programming.

0405/23

Remove ITPCLK/ITPCLK#.

Restore GTLREF[0,2] reference to GTLREF2 and
GTLREF[1,3] to GTLREF1. For Layout Consideration

13

Add Q92 for Vpp Programing Control Logic.

1205/31

Reserved C109 & R190 for SPDIF Noise Considerarion.

X

Rename Schematics file.

0B Revision History ( From 0A )

Change

Sheet Desciption

Date

06/08 10

06/12 18

06/27

06/27 20

06/29 13

B B

Disconnect RN24.5 GP6 Pull-High,It will make the
Onboard AC'97 Codec always Disabled.

USB2+and USB2- Connect error.

Add Resistor to GND on VCC_VID

19

Change R36,R37 from VCC5 to VCC5_SB
Add CT47,CT48 and Change CT12,CT16,CT19 Package

for Reduce ESR.

Simplify AC'97 & CNR Circuit.

A A

Micro Star Restricted Secret

Title

History I

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

MS-6506

1

Last Revision Date:

Tuesday, July 03, 2001

Sheet

28 33

of

Rev

0B

5

MCH Routing Guidelines

1.HVREF,HSWNG and HRCOMP signal layout

Signal Max. Length Width Clearance
HVREF
HSWNG 3" 12 mil 10 mil

D D

HRCOMP 0.5" 10 mil 7 mil

3" 12 mil 10 mil

SDRAM Routing Guidelines

1.SDQ[63:0],SCB[7:0] routing rule

Signal

SCB[7:0]

Breakout CHIP routing rule

Width/spacing
5 mil / 5 mil

C C

5 mil / 8 mil

2.SCS#[7:0],SCKE[3:0] routing rule

SCKE[5:0]

B B

Breakout CHIP routing rule

Width/spacing Max. Length
5 mil / 5 mil 0.5"

Length A

2.0" - 4.0"

Max. Length

3.0" - 4.0"

3.0" - 4.0" 10 mil 12 mil 12 mil

2DIMM Layout Guideline

0.4" - 0.6"SDQ[63:0]

0.5"

1.5"

2DIMM Layout Guideline

WidthLength C Group Spacing

WidthLength B

5 mil

Trace SpacingSignal

12 milSCS#[7:0] 5 mil

Trace Spacing

MCH

12 mil

12 mil

4

3.SMA[12:0],SBS[1:0],SRAS#,SCAS#,SWE# routing rule

Signal Length E

SMA[12:0]
SBS[1:0]
SRAS#
SCAS#
SWE#

2DIMM Breakout CHIP routing rule

Width/spacing
5 mil / 5 mil
5 mil / 8 mil

Group Spacing

12 mil

4.SCK[0:7] routing rule

Signal

SCK[7:0] 15 mil

B

DIMM2

DIMM2DIMM1MCH

2DIMM Total Length Limits

MCH package length G + Length H + Length J = Total length

Breakout CHIP routing rule

Width/spacing
7 mil / 5 mil
7 mil / 10 mil

DIMM1

A

C

3

Max. Length

0.5"

1.5"

2DIMM Layout Guideline

0.4" - 0.6"

Width

5 mil

Trace Spacing

2

Group SpacingLength F

10 mil

DIMM2DIMM1MCH

FE

2DIMM Layout Guideline

Length ILength G

4.0" - 5.0"

See Table-3

Length H

0.0" - 1.0" 0.0" - 0.25"

G + H + J = 5.3"+/- 50mils

Max. Length

0.5"

1.0"

DIMM

12 mil2.0" - 3.0"

Length KLength J Width

SCK Signal Package Trace Length(")

SCK0
SCK1
SCK2
SCK3
SCK4
SCK5
SCK6
SCK7
SCK8
SCK9
SCK10
SCK11

7 mil0.0" - 1.5"

Trace Spacing

15 mil

Table - 3

1

Group Spacing

0.404

0.353

0.865

0.893

0.371

0.349

0.814

0.821

0.483

0.432

0.589

0.689

HG J K

C

MCH

A A

5

4

3

I

Title
Document Number

2

Micro Star Restricted Secret

SDRAM Bus Layout Guigeline

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

28 33

1

Rev

of

5

Norminal 4-layer Board Stackup

1.Board spec.
Description Target Value

Micro-stripline Er
Trace Thickness
Board Thickness

D D

Material
Fab Construction

4.2 - 4.5

1.3 - 1.42 mils
62 mils
FR4
4 layer

notes

Note1: Thickness after plating

2.Board each layer thickness .
Description Target Value

(Layer 1) Top layer

Perpreg

(Layer 2) Power layer

Core

(layer 3) Ground layer

Perpreg

(layer 4) Bottom layer

C C

Note1: Final plating thickness from 1.3 - 1.42 mils

1.4 mil

4.0 mil

1.4 mil
48 mil

1.4 mil

4.0 mil

1.4 mil

Tolerance(+/- mils)
See notes 1

0.3

0.2
5

0.2

0.3
See notes 1

3.Via Stack
Description Target Value

Via Pad
Via Anti-Pad
Via Finiched hole
Signal Pad(BGA)

26 mil
40 mil
14 mil
20 mil

4.CPU GTL+ bus impedance = 50 Ohm(7mil trace width)

5.CPU asynchronous GTL+,AGP,Memory and Hub-link bus impedance = 60 Ohm(5mil trace width)

CPU Routing Guidelines

1.CPU data or address synchronous signal groups and the associate strobe

B B

A A

Signals Associated Strobe

REQ[4:0]#,A[16:3]# ADSTB0#

A[31:17]# ADSTB1#
D[15:0]#,DBI0#
D[31:16]#,DBI1#
D[47:32]#,DBI2#
D[63:48]#,DBI3#

DSTBP0#,DSTBN0#
DSTBP1#,DSTBN1#
DSTBP2#,DSTBN2#
DSTBP3#,DSTBN3#

*All the system bus signals must be referenced to GND

2.CPU connect to MCH address layout guideline

Total length

A[16:3]#
ADSTB0#
(Note1)
A[31:17]# 2" - 10" 5 mils 13 mils +/- 200 mils
ADSTB1#
(Note1) (Note2) (Note4)

(Note2) (Note4)

See Table -1

See Table -1

5 mils2" - 10"

Note1:This group all the signals keep same length
Note2:This trace length is pin to pin length
Note3:Trace edge to edge spacing greater than 3:1 versus trace to reference plane height ratio
Note4:This group other signal trace lengtn match = ADSTB# +/- 200 mils

5

Note1

SpacingWidth
13 milsREQ[4:0]#
(Note3)

(Note3)

4

Length matchSignal PCB length
+/- 200 mils

4

3

2

1

3. CPU connect to MCH data layout guideline

D[15:0]# 5 mils
DBI0#
DSTBP0#
DSTBN0#
(Note1)

DBI1#
DSTBP1#
DSTBN1#
(Note1)

DBI2#
DSTBP2#
DSTBN2#
(Note1)

DBI3#
DSTBP3#
DSTBN3#
(Note1)

2" - 10"

(Note2)
2" - 10"

(Note2)
2" - 10"

(Note2)
2" - 10"

(Note2)

PCB length

Total lengthSignal

See Table -1

See Table -1

See Table -1

See Table -1

Width

5 mils

5 mils

5 mils

13 milsD[31:16]#

(Note3) (Note4)
13 milsD[47:32]#

(Note3) (Note4)
13 milsD[63:48]#

(Note3) (Note4)

Length matchSpacing
+/- 100 mils13 mils
+/- 25 mils

(Note4)(Note3)
+/- 100 mils
+/- 25 mils

+/- 100 mils
+/- 25 mils

+/- 100 mils
+/- 25 mils

Note1:This group all the signals keep same length
Note2:This trace length is pin to pin length
Note3:Trace edge to edge spacing greater than 3:1 versus trace to reference plane height ratio
Note4:

* Each group DSTBPn/p# signals pad to pad length match = +/- 25 mils
* This group other signal trace lengtn match = DSTBn/p# +/- 100 mils

Table - 1

CPU package length + PCB trace length + MCH package length = Total length

L1 + L2 + L3 = Total L4

7.Keep the voltage divider with in 1.5 inches of GTLREF pin.and do not allow the GTLREF routing to
splits or discontinuities power plane.

8.CPU Asynchronous GTL+ bus connect to ICH2 trace length
Signal Name Trace Spacing Trace Length Pull-up Resistor

FERR#
PROCHHOT#
THERMTRIP#
A20M#
IGNNE#
LINT[1:0]
SLP#
SMI#
STPCLK#
INIT#

1"-12"7 MIL 62 Ohm +/- 5%
1"-17"7 MIL 62 Ohm +/- 5%
1"-17"7 MIL 62 Ohm +/- 5%
1"-12"7 MIL None

None7 MIL 1"-12"
None7 MIL 1"-12"
None7 MIL 1"-12"
None7 MIL 1"-12"
None7 MIL 1"-12"
None7 MIL 1"-17"

PWRGOOD 300 Ohm +/- 5%7 MIL 1"-12"

9.CPU BCLK,BCLK# should be routed as a differential pair with 7 mil trace and 7 mil spacing between

them,2.5" to 10" pin to pin common clock lengths, and 25 mil spacing away form all the signal or
clock.

10.DBSY#,DRDY#,TRDY#,ADS#,LOCK#,BNR#,HIT#,HITM#,BPRI#,DEFER#,BR0#,RESET# and RS[2:0]# CPU signal trace

length around 2.5" to 10"

Micro Star Restricted Secret

Title

CPU Bus Layout Guigeline

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

3

2

http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

29 33

of

Rev

5

Norminal 4-layer Board Stackup

1.Board spec.
Description Target Value

Micro-stripline Er
Trace Thickness
Board Thickness

D D

Material
Fab Construction

4.2 - 4.5

1.3 - 1.42 mils
62 mils
FR4
4 layer

Note1: Thickness after plating

2.Board each layer thickness .
Description Target Value

(Layer 1) Top layer

Perpreg

(Layer 2) Power layer

Core

(layer 3) Ground layer

Perpreg

(layer 4) Bottom layer

C C

Note1: Final plating thickness from 1.3 - 1.42 mils

1.4 mil

4.0 mil

1.4 mil
48 mil

1.4 mil

4.0 mil

1.4 mil

3.Via Stack
Description Target Value

Via Pad
Via Anti-Pad
Via Finiched hole
Signal Pad(BGA)

26 mil
40 mil
14 mil
20 mil

4.CPU GTL+ bus impedance = 50 Ohm(7mil trace width)

notes

Tolerance(+/- mils)
See notes 1

0.3

0.2
5

0.2

0.3
See notes 1

Note1

4

3

4.A pair data strobe should be routed to the same length within +/- 25mils, if one strobe switch
layers, and another switch layer in the same manner.Additional CPU,MCH internal trace
length(See Table-1)must be inculded.The calculation trace length follow (Table-2)

5.2" - 10" from pin to pin and each address signal group should be routed to same length within
+/-200 mils of the associated strobes.Additional CPU,MCH internal trcae length(see
Table-1)must be included.The calculation trace length follow (Table-2).

6.Internal adderss strobe trace length(See Table-1) of CPU,MCH must be inculded.The calculation trace
length follow (Table-2)

2

1

Table - 1

CPU package length + PCB trace length + MCH package length = Total length

L1 + L2 + L3 = Total L4

7.Keep the voltage divider with in 1.5 inches of GTLREF pin.and do not allow the GTLREF routing to
splits or discontinuities power plane.

8.CPU Asynchronous GTL+ bus connect to ICH2 trace length
Signal Name Trace Spacing Trace Length Pull-up Resistor

FERR#
PROCHHOT#
THERMTRIP#
A20M#
IGNNE#
LINT[1:0]
SLP#
SMI#
STPCLK#
INIT#

1"-12"7 MIL 62 Ohm +/- 5%
1"-17"7 MIL 62 Ohm +/- 5%
1"-17"7 MIL 62 Ohm +/- 5%
1"-12"7 MIL None

None7 MIL 1"-12"
None7 MIL 1"-12"
None7 MIL 1"-12"
None7 MIL 1"-12"
None7 MIL 1"-12"
None7 MIL 1"-17"

PWRGOOD 300 Ohm +/- 5%7 MIL 1"-12"

5.CPU asynchronous GTL+,AGP,Memory and Hub-link bus impedance = 60 Ohm(5mil trace width)

9.CPU BCLK,BCLK# should be routed as a differential pair with 7 mil trace and 7 mil spacing between

them,2.5" to 10" pin to pin common clock lengths, and 25 mil spacing away form all the signal or

B B

CPU Routing Guidelines

1.CPU data synchronous signal groups and the associate strobe
Signals Associated Strobe

clock.

10.DBSY#,DRDY#,TRDY#,ADS#,LOCK#,BNR#,HIT#,HITM#,BPRI#,DEFER#,BR0#,RESET# and RS[2:0]# CPU signal trace
length around 2.5" to 10"

REQ[4:0]#,A[16:3]# ADSTB0#

A[31:17]# ADSTB1#
D[15:0]#,DBI0#
D[31:16]#,DBI1#
D[47:32]#,DBI2#
D[63:48]#,DBI3#

DSTBP0#,DSTBN0#
DSTBP1#,DSTBN1#
DSTBP2#,DSTBN2#
DSTBP3#,DSTBN3#

*All the system bus signals must be referenced to GND

2.Trace edge to edge spacing greater than 3:1(about 12 mils) versus trace to GND plane height ratio

3.2" - 10" from pin to pin and each data signal group should be routed to same length within

A A

+/-100 mils of the associated strobes.Additional CPU,MCH internal trcae length(see
Table-1)must be included.The calculation trace length follow (Table-2).

5

4

3

2

Micro Star Restricted Secret

Title

CPU Bus Layout Guigeline

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

30 33

of

Rev

5

4

3

2

1

Signal CPU length(")CPU ball MCH length(")MCH ball

Address Group 0

ADSTB#0

A#3
A#4

D D

A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
REQ#0
REQ#1

C C

REQ#2
REQ#3

L5
K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
J1
K5
J4
J3
H3REQ#4

0.210

0.368

0.265

0.155

0.415

0.304

0.144

0.372

0.327

0.246

0.394

0.408

0.349

0.241

0.198

0.427

0.207

0.270

0.337

0.356

R5
T4
T5
T3
U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
U6
T7
R7
U5
U3

0.530

0.518

0.434

0.728

0.577

0.551

0.359

0.643

0.533

0.397

0.463

0.576

0.660

0.407

0.570

0.402

0.350

0.393

0.475

0.599

Address Group 1

ADSTB#1 R5

A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25

B B

A#26
A#27
A#28
A#29
A#30
A#31

T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4

0.214

0.470

0.404

0.303

0.246

0.334

0.388

0.458

0.156

0.379

0.281

0.417

0.166

0.493

0.217

0.285 0.365

N6
K4
M4
M3
L3
L5
K3
J2
M5
J3
L2
H4
N5
G2
M6

0.438

0.550

0.580

0.648

0.604

0.521

0.624

0.685

0.509

0.636

0.648

0.634

0.472

0.792

0.449

L7

Signal CPU length(")CPU ball MCH length(")MCH ball

Data Group 0
DSTBN#0
DSTBP#0

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
DBI#0

E22
F21
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22G22
H21
C26
D23
J21
D25
E21

0.326

0.414

0.475

0.538

0.608

0.386

0.386

0.535

0.464

0.515

0.590

0.274

0.203

0.589

0.462

0.183

0.550

0.309

AD4
AD3
AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AD7
AC7
AC6
AC3
AC8
AE2
AD5

Data Group 1
DSTBN#1
DSTBP#1

D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
DBI#1

K22
J23
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
G25

0.301 0.693

0.306

0.272

0.480

0.358

0.418

0.443

0.508

0.513 0.898

0.597

0.176

0.524

0.412

0.171

0.245

0.401

0.313

0.473

0.458

AE6
AE7
AG5
AG2
AE8
AF6
AH2
AF3
AG3
AE5
AH7
AH3
AF4
AG8
AG7
AG6
AF8
AH5
AG4

0.7590.338

0.801

0.649

0.564

0.531

0.678

0.628

0.635

0.623

0.468

0.802

0.495

0.609

0.548

0.579

0.709

0.590

0.856

0.637

0.638

0.845

0.904

0.663

0.759

0.965

0.798

0.709

0.863

0.904

0.794

0.789

0.785

0.785

0.711

0.892

0.888

DSTBN#2
DSTBP#2

D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
DBI#2

DSTBN#3
DSTBP#3

D#48
D#49
D#40
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
DBI#3

CPU length(") MCH ballCPU ballSignal MCH length(")

Data Group 2
K22
J23
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
P26

0.252

0.266

0.300

0.226

0.178

0.371

0.271

0.454

0.437

0.383

0.165

0.343

0.381

0.329

0.420

0.380

0.221

0.279

0.441

AE11
AD11
AC11
AC12
AE9
AC9
AE10
AD9
AG9
AC10
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AH9

Data Group 3
W22
W23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
V21

0.298 0.443

0.300

0.419

0.324

0.270

0.384

0.167

0.252

0.341

0.447

0.454

0.426

0.336

0.386

0.222

0.426

0.268

0.394

AC15
AC16
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16
AD15 0.4310.202

0.595

0.532

0.514

0.565

0.652

0.566

0.605

0.635

0.724

0.543

0.558

0.666

0.703

0.705

0.754

0.669

0.563

0.596

0.775

0.395

0.668

0.712

0.412

0.548

0.621

0.520

0.612

0.610

0.619

0.703

0.339

0.580

0.534

0.672

0.419

0.503

A A

Micro Star Restricted Secret

Title

CPU/845 Package Length

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

1

31 33

Rev

of

8

Power Delivery Map

7

6

5

4

3

2

1

D D

ATX 12V POWER Supply

3.3V 5V 5VSB1A12V

VRM9.2

Processor Core
Processor Vtt

Power
Translator
ACPI IC

1.5V VREG

MCH Core 1.5V

MCH Vtt
MCH AGP

OP

C C

1.8V VREG

3.3V
DUAL FET

3.3V VREG

MCH HUB Interface 1.8V

MCH Memory sdr 3.3V

PC-133 System Memory 3.3V

ICH2 Core 1.8V
ICH2 I/O 3.3V
ICH2 Resume 1.8V

1.8V VREG
5V TO 3.3V

RESISTOR

ICH2 Resume I/O 1.8V

ICH2 RTC 3.3V
ICH2 5V

FWH 3.3V

B B

LPC Super I/O 3.3V

CLOCK GEN 3.3V

HARDWARE AUDIO 3.3V

PCI LAN 3.3V/2.5V

5VDual For USB and K/B

A A

Micro Star Restricted Secret

Title

Power Delivery Map

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

8

7

6

5

4

3

http://www.msi.com.tw

2

MS-6506

Last Revision Date:

Tuesday, July 03, 2001

Sheet

32 33

Rev

of

1