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MS-6502
Schematics rev.0B
39 pgs1.16 Mb0
Schematics REV0a
39 pgs1.17 Mb0

MSI MS-6502 Schematics REV0a

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1
Cover Sheet
Block Diagram
Clock Synthesizer
AMD 762--------North Bridge
DDR DIMM-184
AGP 4X SLOT
PCI Connectors
ATA66/100 Connectors
Parallel / Serial Port
Keyboard & Mouse
BIOS & FANs
A A
USB Conector
AC'97 Codec
Audio/Game Port
IDE RAID
LAN
Diagnostic LED
DDR Regulator & STR LDO
Vcore/Frequency Ajust
VRM
DDR Terminator
IGD4 PCI Strappings
Bypass Capacitors
ECN / History
1
2
3
4,5,6,7PGA462 Socket A CPU0/CPU1
8,9,10,11,12
13,14
15
16,17,18
19,20VIA VT686B--------South Bridge
21
22
23
24
25
26
27
28
29,30
31
32
33
34
35
36
37
38
MS-6502 ATX
Version 0A
Last Update xx/xx/2000
CPU: Dual AMD Socket-462 Processors
System Chipset: AMD 762(North Bridge) VIA 686B (South Bridge)
Expansion Slots: AGP-Pro SLOT * 1 PCI2.2 PCI/64/33 SLOT * 5
On Board: LAN 82550 AC97 Codec IDE Raid PC 2 PC
Title
Size Document Number Rev
Custom
1
Date: Sheet
MICRO-STAR
Cover Sheet
MS-6502
139Wednesday, March 21, 2001
of
0A
1
K7 462-Pin
VRM Clock
Socket Processor
K7 462-Pin Socket Processor
Block Diagram
AMD SYSTEM BUS
AGP PRO 2X/4X
A A
UltraDMA
IDE Primary
33/66/100
IDE Secondary
USB Port 1
USB
AMD762 North Bridge
VIA 686B South Bridge
USB Port 2
USB Port 3
USB Port 4
Onboard
AC'97 Codec
PC 2 PC
AC'97 Link
AMD SYSTEM BUS
VTT 1.25V Regulator
PCI CNTRL
PCI ADDR/DATA
4 Register DDR DIMM Modules
INTEL 82550 LAN
PCI CNTRL
PCI ADDR/DATA
PCI CNTRL
Promise 20265 IDE RAID
PCI ADDR/DATA
PCI Conn 1
PCI Conn 2
PCI Conn 3
PCI Conn 4
PCI Conn 5
PCI 2.2
10/100Mbps
ISA Bus
Conn.
BIOS
ATA 33/66/100
ATA 33/66/100
Keyboard SerialParallel
Mouse
Game ConnFloopy
Title
Size Document Number Rev
Custom
1
Date: Sheet of
MICRO-STAR
Block Diagram
MS-6502
239Wednesday, March 21, 2001
0A
5
* 25 mils Trace on Layer 6 with GND copper around it
D D
PCISTP-<19>
CPUSTOP-<19>
FP_RST-<25>
C C
B B
A A
100/133-<34,37>
PAPICCLK<34>
OSC<20>
CPUCLK0&CPUCLK0#:
CPUCLK1&CPUCLK1#:
CPUCLK2&GCLK0 X
GCLK1 X-4.5
NBCLK&SBCLK
PCICLK GROUP X-2.5
* X MEANS THE SHORTEST LENGTH FOR MAINTAIN PROPAGATION DELAY
* CPUCLK1'S TERMINATION CKT MUST BE PLACED NEAR TO NB
VCC3
R335 22-REV
R340 22-REV
R318 22 R295 22
C326 10p
WIDTH/SPACE LENGTH
5/20 5 FOR DIFF. PAIR X-1 INCH
5/20 5 FOR DIFF. PAIR X-1 INCH
5/20
5/20
5/20
5/20
* Put close to every power pin
FB16
0_1206
FB15
0_1206
C371
0.01u
1 2
1 2
3 4
5 6
7 8
X
VCC3
3 4
RN68
10K
5 6
7 8
RN77
10K
C354
0.01u
4
+
EC42
10u
Y3
14M-16pf-HC49S-D
R298 1M-REV
C336
C335
22p
22p
FS2 FS1
0
000
0
0
1
0
11
0
1
0
1
11
1
C358 330p
3422189154845
VDD
VDDSD
4
VDDREF
X1
5
X2
32
PCI_STOP_L
31
CPU_STOP_L
30
PD_L
29
SPREAD_L
28
FS2
2
FS1
1
FS0
24
24MHZ/48MHZ#
35
RSVD2
44
RSVD1
GND
GND
GND
GND
212536333841
12
*Put GND copper under Clock Gen. connect to every GND pin
CPU
FS0
SDRAM
133.3 33.3 66.7
95.0
1
100.99
0
115.0
100.7
0
103.0
1
105.0 35.0011 0 60.0
110.0
C339330p
C337330p
VDD48
VDDAGP
CPUCLKT2
VDDPCI1
VDDPCI2
CPUCLKC2 CPUCLKT1 CPUCLKC1 CPUCLKT0 CPUCLKC0
SDRAM_OUT
PCICLK_F0
GND
GND
GND
GND
GND
47
PCI AGP
31.67
33.66
38.33
33.57
34.33
36.67
C5380.01u
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
AGP1 AGP0
USB0
SCLK
SDATA
W174B
63.33
67.33
76.67
67.13
66.6
66.6
C5330.01u
3
2
1
Clock Synthesizer
10u
EC44
C5290.01u
U24
+
C5370.01u
C3730.01u
C3720.01u
R302 0
42
CPUCLKC2
43
CPUCLKT1
39
CPUCLKC1
40
CPUCLKT0
36
CPUCLKC0
37
46
PCICLK6
17
PCICLK5
16
PCICLK4
14
PCICLK3
13
PCICLK2
11
PCICLK1
10
PCICLK0
8
PCICLK_FB
7
AGP1
20
AGP0
19
USB0
23
26 27
CPUCLKC2
CPUCLKC1 CPUCLKT1 CPUCLKC0 CPUCLKT0
PCICLK6
PCICLK5 PCICLK4 PCICLK3
PCICLK2 PCICLK1 PCICLK0 PCICLK_FB
AGP1
AGP0
USB0
C346 10p
NOPOP
CN15 10p
7 8 5 6 3 4 1 2
C365 10p
NOPOP
CN16 10p
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
CN14 10p
C369 10p
NOPOP
C367 10p
NOPOP
C374 10p
NOPOP
NOPOP
NOPOP
NOPOP
1 2 3 4 5 6 7 8
RN72 33
RN75 22
1 2 3 4 5 6 7 8 1 2 3 4 5 6
7 8
RN71 22 R333 22 R332 22
R336 22
PCICLK6
Close to clock generator
CPUCLK2 <8>
CPUCLK-1 <6> CPUCLK1 <6> CPUCLK-0 <4> CPUCLK0 <4>
PCLK5 <18> PCLK4 <17> PCLK3 <17> PCLK2 <16> PCLK1 <16> NBCLK <11> SBCLK <19>
GCLK1 <15> GCLK0 <11>
USBCLK <20>
SMBCLK <13,14,19,20,34> SMBDATA <13,14,19,20,34>
R317 22
R327 22
VCC3
C5170.01u
C5060.01u
NOPOP
Length = X"
Length = X" - 1"
Length = X" - 2.5"
Length = X"
Length = X" Length = X" - 4.5"
LANCLK <31>
IDECLK <29>
C5140.01u
C3760.01u
NOPOP
NOPOP
NOPOP
(5 mil trace / 20 mil clearance)
(20/5/5/5/20)
(5 mil trace / 20 mil clearance)
(5 mil trace / 20 mil clearance)
(5 mil trace / 20 mil clearance)
(5 mil trace / 20 mil clearance) (5 mil trace / 20 mil clearance)
LAN: Length = X"(SHARE)
IDE: Length = X"(SHARE)
EMI
C900.01u
C5050.01u
NOPOP
NOPOP
Title
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet of
MICRO-STAR
Clock Synthesizer
MS-6502
1
339Wednesday, March 21, 2001
0A
A
P0_SDATA-[0..63]<8>
4 4
3 3
P0_DICLK-[0..3]<8>
2 2
P0_DOCLK-[0..3]<8>
P0_SDATA-0 P0_SDATA-1 P0_SDATA-2 P0_SDATA-3 P0_SDATA-4 P0_SDATA-5 P0_SDATA-6 P0_SDATA-7 P0_SDATA-8 P0_SDATA-9 P0_SDATA-10 P0_SDATA-11 P0_SDATA-12 P0_SDATA-13 P0_SDATA-14 P0_SDATA-15 P0_SDATA-16 P0_SDATA-17 P0_SDATA-18 P0_SDATA-19 P0_SDATA-20 P0_SDATA-21 P0_SDATA-22 P0_SDATA-23 P0_SDATA-24 P0_SDATA-25 P0_SDATA-26 P0_SDATA-27 P0_SDATA-28 P0_SDATA-29 P0_SDATA-30 P0_SDATA-31 P0_SDATA-32 P0_SDATA-33 P0_SDATA-34 P0_SDATA-35 P0_SDATA-36 P0_SDATA-37 P0_SDATA-38 P0_SDATA-39 P0_SDATA-40 P0_SDATA-41 P0_SDATA-42 P0_SDATA-43 P0_SDATA-44 P0_SDATA-45 P0_SDATA-46 P0_SDATA-47 P0_SDATA-48 P0_SDATA-49 P0_SDATA-50 P0_SDATA-51 P0_SDATA-52 P0_SDATA-53 P0_SDATA-54 P0_SDATA-55 P0_SDATA-56 P0_SDATA-57 P0_SDATA-58 P0_SDATA-59 P0_SDATA-60 P0_SDATA-61 P0_SDATA-62 P0_SDATA-63
P0_DICLK-0 P0_DICLK-1 P0_DICLK-2 P0_DICLK-3
P0_DIVAL-
P0_DIVAL-<8>
P0_DOCLK-0 P0_DOCLK-1 P0_DOCLK-2 P0_DOCLK-3
P0_AIN-[2..14]<8>
1 1
P0_AINCLK-<8>
P0_CFWDRST<8> P0_CONNECT<8> P0_PROCRDY<8> P0_SFILLVAL-<8>
A
P0_DOVAL-
P0_AIN-0 P0_AIN-1 P0_AIN-2 P0_AIN-3 P0_AIN-4 P0_AIN-5 P0_AIN-6 P0_AIN-7 P0_AIN-8 P0_AIN-9 P0_AIN-10 P0_AIN-11 P0_AIN-12 P0_AIN-13 P0_AIN-14
P0_CFWDRST P0_CONNECT P0_PROCRDY
P0_SFILLVAL-
R266
10K
AA35
AA33 AE37 AC33 AC37
AA37 AC35
AN33
AE35
AL31
AL29 AG33
AL35 AE33
AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31
AL23 AN23
W37 W35
Y35 U35 U33 S37 S33
Y37
S35 Q37 Q35 N37
J33 G33 G37 E37 G35 Q33 N33
L33 N35
L37
J37 A37 E35 E31 E29 A27 A25 E21 C23 C27 A23 A35 C35 C33 C31 A29 C29 E23 C25 E17 E13 E11 C15
E9
A13
C9
A9 C21 A21 E19 C19 C17 A11 A17 A15
W33
J35 E27 E15
C37 A33 C11
AJ29
AJ37
AJ35
AJ33
AJ21
AJ31
SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 SDATA16 SDATA17 SDATA18 SDATA19 SDATA20 SDATA21 SDATA22 SDATA23 SDATA24 SDATA25 SDATA26 SDATA27 SDATA28 SDATA29 SDATA30 SDATA31 SDATA32 SDATA33 SDATA34 SDATA35 SDATA36 SDATA37 SDATA38 SDATA39 SDATA40 SDATA41 SDATA42 SDATA43 SDATA44 SDATA45 SDATA46 SDATA47 SDATA48 SDATA49 SDATA50 SDATA51 SDATA52 SDATA53 SDATA54 SDATA55 SDATA56 SDATA57 SDATA58 SDATA59 SDATA60 SDATA61 SDATA62 SDATA63
SDATAINCLK0 SDATAINCLK1 SDATAINCLK2 SDATAINCLK3
SDATAINVAL
SDATAOUTCLK0 SDATAOUTCLK1 SDATAOUTCLK2 SDATAOUTCLK3
SDTATOUTVAL
SADDIN0 SADDIN1 SADDIN2 SADDIN3 SADDIN4 SADDIN5 SADDIN6 SADDIN7 SADDIN8 SADDIN9 SADDIN10 SADDIN11 SADDIN12 SADDIN13 SADDIN14
SADDINCLK
CLKFWDRST CONNECT PROCRDY SFILLVAL
B
A20M
FERR
IGNNE
RESET
STPCLK
PWROK
PICCLK PICD0/BYPASSCLK PICD1/BYPASSCLK
COREFB-
COREFB+
CLKIN CLKIN
RSTCLK RSTCLK
K7CLKOUT K7CLKOUT
ANALOG
SYSVREFMODE
VREF_SYS
PLLBYPASS PLLBYPASSCLK PLLBYPASSCLK
PLLMON1 PLLMON2
PLLTEST
SCANCLK1 SCANCLK2
SCANINTEVAL
SCANSHIFTEN
DBRDY DBREQ FLUSH
TRST
SCHECK0 SCHECK1 SCHECK2 SCHECK3 SCHECK4 SCHECK5 SCHECK6 SCHECK7
SADDOUT0 SADDOUT1 SADDOUT2 SADDOUT3 SADDOUT4 SADDOUT5 SADDOUT6 SADDOUT7 SADDOUT8
SADDOUT9 SADDOUT10 SADDOUT11 SADDOUT12 SADDOUT13 SADDOUT14
SADDOUTCLK
B
C
CPU1A
A20M-
AE1 AG1 AJ3
INIT
AL1
INTR
AJ1 AN3
NMI
AG3 AN5
SMI
AC1
AE3
R315 100
N1 N3 N5
AG13 AG11
AN17 AL17
AN19 AL19
AL21 AN21
AJ13
AA5 W5
AC5
ZN
AE5
ZP
AJ25 AN15 AL15
AN13 AL13 AC3
S1 S5 S3 Q5
P0_CPU_DBRDY
AA1
P0_DBREQ-
AA3
P0_FLUSH-
AL3
Q1
TCK
U1
TDI
U5
TDO
Q3
TMS
U3
L1
VID0
L3
VID1
L5
VID2
L7
VID3
J7
VID4
W1
FID0
W3
FID1
Y1
FID2
Y3
FID3
P0_SCHECK-0
U37
P0_SCHECK-1
Y33
P0_SCHECK-2
L35
P0_SCHECK-3
E33
P0_SCHECK-4
E25
P0_SCHECK-5
A31
P0_SCHECK-6
C13
P0_SCHECK-7
A19
J1 J3
P0_AOUT-2
C7
P0_AOUT-3
A7
P0_AOUT-4
E5
P0_AOUT-5
A5
P0_AOUT-6
E7
P0_AOUT-7
C1
P0_AOUT-8
C5
P0_AOUT-9
C3
P0_AOUT-10
G1
P0_AOUT-11
E1
P0_AOUT-12
A3
P0_AOUT-13
G5
P0_AOUT-14
G3
E3
PGA-D462
FERR CPUINIT­INTR IGNNE­NMI CPURST­SMI­STPCLK-
APICD0­APICD1-
P0_COREFB­P0_COREFB
CPUCLK0_R CPUCLK-0_R
P0_CLKOUT P0_CLKOUT-
P0_VREFMODE P0_VREF_SYS
P0_ZN P0_ZP
P0_PLLBP-
P0_PLLMON1 P0_PLLMON2 P0_PLLTEST-
P0_SCANCLK1 P0_SCANCLK2 P0_SINTVAL P0_SSHIFTEN
P0_CPU_TCK P0_CPU_TDI P0_CPU_TDO P0_CPU_TMS P0_CPU_TRST-
P0_VID0 P0_VID1 P0_VID2 P0_VID3 P0_VID4
P0_FID0 P0_FID1 P0_FID2 P0_FID3
A20M- <6,19> FERR <6> CPUINIT- <6,19> INTR <6,19> IGNNE- <6,19> NMI <6,19>
SMI- <6,19> STPCLK- <6,19>
P0_DC_OK <23>
APICCLK
APICD0- <6,34> APICD1- <6,34>
The farest VCORE and GND
P0_VID0 <34> P0_VID1 <34> P0_VID2 <34> P0_VID3 <34> P0_VID4 <34>
P0_FID0 <34> P0_FID1 <34> P0_FID2 <34> P0_FID3 <34>
P0_AOUTCLK- <8>
**All CPU interface are 2.5V tolerant**
CPURST- <6,19>
C351 4700p
APICCLK <6,34>
P0_COREFB- <35> P0_COREFB <35>
R293
R285
100
100
AMD use 100ohm
VCORE
VCORE
RN63
78 56 34 12
100
CPUCLK0<3>
RN76
7 8 5 6 3 4 1 2
680
RN66
1 2 3 4 5 6 7 8
680
R286 56 R284 56 R314 680 R267 680
R247 270
R253 270
R241 270
R236 270
680pC311
680pC307
21
21
P0_SCHECK-[0..7] <8>
P0_AOUT-[2..14] <8>
INTR CPUINIT­NMI SMI-
IGNNE­CPURST­A20M­STPCLK-
P0_PLLMON1 P0_PLLMON2 P0_FLUSH­P0_PLLBP-
P0_AIN-0
P0_AIN-1
P0_DOVAL-
P0_SFILLVAL-
CPUCLK0_R
CPUCLK-0_R
VCORE
R274 301
P0_SSHIFTEN P0_SINTVAL P0_SCANCLK2
P0_DBREQ­CPURST-
R276 60.4
R272 60.4
CPUCLK-0<3>
C
D
VCORE
HDT2
1
1
2
3
3
4
5
5
6
7
7
8
9
9
10
11
11
12
13
13
14
15 16
15 16
D2x8-BK
NOPOP
VCORE
FERR
P0_VREFMODE
VREFMODE=Low=No voltage scaling
VCORE
Near socket-A
D
P0_DBREQ-
P0_PLLTEST-
P0_CPU_TCK
2
P0_CPU_TMS
4
P0_SCANCLK1
6
P0_CPU_TDI
8
P0_CPU_TRST-
10
P0_CPU_TDO
12
P0_CPU_DBRDY
14
P0_PLLTEST-
P0_CPU_TCK P0_CPU_TMS P0_CPU_TRST­P0_CPU_TDI
VCC3
R328 1K
5
2 4
3
7S14-SSOP5
U28
VCORE
for internal VREFSYS
R280 1K-REV
R282 270
P0_SCANCLK1 P0_SSHIFTEN P0_SINTVAL P0_SCANCLK2
1 2 3 4 5 6 7 8
Title
Size Document Number Rev
Custom
Date: Sheet
0.5 * VCORE
P0_VREF_SYS
RN79
P0_ZN
P0_ZP
10K
P0_CLKOUT P0_CLKOUT-
* Trace lengths of CLKOUT and -CLKOUT are between 2" and 3"
SocketA (Part 1)
C321
39p
match the transmission line
Push-Pull compensation circuit
MICRO-STAR
MS-6502
E
R313 510
R305 510
FERR-
C320
1000p
R279 40.2
R278 40.2
E
C319
0.047u
100
RN80
510
VCORE
RN59
439Thursday, March 22, 2001
VCORE
12 34 56 78
FERR- <19>
R283 100
R281 100
VCORE
VCORE
78 56 34 12
of
0A
A
B
C
D
E
* 25 mils Trace/ 12 mils Space
RN55
100
VCC P0_VCCA_PLL1P0_VCCA_PLL
7 8 5 6 3 4 1 2
C253
4 4
39p
2 1
Max 150mA, Design for 100mA
C271 39p
2
2 1
3 1
VR6
CSK-2-SOT23-150mA
R250 0
R264 0-REV
C281
0.01u
Used when spec. change
2.5V
R257 10R259 0
C289
C266
C291
39p
2 1
39p
2 1
NOPOP
NOPOP
VCCA_PLL trace length from the VR1 to the PGA must be 0.75". Place al filters close to the PGA. Keep all power and signal trce away from the VR1. Place a cut in the GND plane around the VCCA_PLL regulator circuit.
39p
2 1
Place inside CPU socket
C272 39p
2 1
Power Up Strappings :
AD[3:0] => CPU Clock Multiplier
0000 3 0001 3.5 0010 4 0011 4.5 0100 5 0101 5.5 0110 6 0111 6.5
1000 7 1001 7.5 1010 8 1011 8.5 1100 9 1101 9.5 1110 10 1111 Reserved
B20
B16
B12B8B4
VCC_CORE96
VCC_CORE97
VCC_CORE98
VCC_CORE99
VSS98
VSS99
VSS100
VSS101
B14
B10B6B2
AJ5
VCC_CORE100
VCC_CORE101
BP0_CUT BP1_CUT BP2_CUT BP3_CUT
VSS102
VSS103
VSS104
AM4
AK6
AM6
D
P0_VCCA_PLL
0~100 mA,
2.25~2.75V
CPU1B
AC7
AJ23
PGA-D462
VCC_Z
VCC_A
AA31
NC1
AC31
NC2
AE31
NC3
AG23
NC6
AG25
NC7
AG31
NC8
AG5
NC9
AJ11
NC10
AJ15
NC11
AJ17
NC12
AJ19
NC13
AJ27
NC15
AL11
NC16
AN11
NC17
AN9
NC18
G11
NC19
G13
NC20
G27
NC21
G29
NC22
G31
NC23
J31
NC24
J5
NC25
L31
NC27
N31
NC28
Q31
NC29
S31
NC30
S7
NC31
U31
NC32
U7
NC33
W31
NC34
W7
NC35
Y31
NC36
Y5
NC37
AG19
NC42
G21
NC43
AG21
NC44
G19
NC45
AE7
VSS_Z
AN27 AL27 AN25 AL25
VCC
P0BP0 <34> P0BP1 <34> P0BP2 <34> P0BP3 <34>
R294
The presence pin is only connected to GND
10K
through the processor
P0_PRESENCE-
Title
Size Document Number Rev
Custom
Date: Sheet
MICRO-STAR
SocketA (Part 2)
MS-6502
539Wednesday, March 21, 2001
E
0A
of
VCORE
3 3
2 2
1 1
AD30
AF10 AF28 AF30 AF32
AH30
AG15 AG29
AD8
AF6 AF8
AH8
AJ9 AK8 AL9
AM8
F30
H10 H28 H30 H32
K30
AJ7 AL7 AN7
G25 G17
G9
AG7
F8
H6 H8
K8
N7 Y7
VCC_SRAM1 VCC_SRAM2 VCC_SRAM3 VCC_SRAM4 VCC_SRAM5 VCC_SRAM6 VCC_SRAM7 VCC_SRAM8 VCC_SRAM9 VCC_SRAM11 VCC_SRAM13 VCC_SRAM14 VCC_SRAM16 VCC_SRAM17 VCC_SRAM19 VCC_SRAM20 VCC_SRAM21 VCC_SRAM22 VCC_SRAM23 VCC_SRAM24 VCC_SRAM25 VCC_SRAM26 VCC_SRAM27 VCC_SRAM28 VCC_SRAM29 VCC_SRAM30 VCC_SRAM31
KEY4 KEY6 KEY8 KEY10 KEY12 KEY14 KEY16 KEY18
H12
H16
H20
H24M8P30R8T30V8X30Z8AB30
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VSS1
VSS2
VSS3
VSS4
VSS5
H14
H18
H22
H26
M30P8R30T8V30X8Z30
A
VCC_CORE6
VCC_CORE7
VCC_CORE8
VCC_CORE9
VSS6
VSS7
VSS8
VSS9
AF14
AF18
VCC_CORE10
VCC_CORE11
VCC_CORE12
VCC_CORE13
VCC_CORE14
VSS10
VSS11
VSS12
VSS13
VSS14
AB8
AF12
AF16
AF22
AF26
AM34
AK36
VCC_CORE15
VCC_CORE16
VCC_CORE17
VCC_CORE18
VSS15
VSS16
VSS17
VSS18
AF20
AF24
AM36
AK32
AK34
AK30
AK26
AK22
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VSS19
VSS20
VSS21
VSS22
AK28
AK24
AK20
AK16
AK18
AK14
AK10
AL5
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
VSS23
VSS25
VSS26
VSS27
AK12
AK4
AK2
AH36
AH26
AM30
AH22
AH18
VCC_CORE27
VCC_CORE28
VCC_CORE29
VSS28
VSS29
VSS30
AM32
AH34
AH32
AH28
AH14
AH10
AH4
AH2
VCC_CORE30
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VSS31
VSS32
VSS33
VSS34
VSS35
AH24
AH20
AH16
AH12
AF36
AF34
AD6
AM26
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
VSS37
VSS38
VSS39
VSS40
AF4
AF2
AD36
AD34
B
AD4
AD2
AB36
AB34
VCC_CORE39
VCC_CORE40
VCC_CORE41
VSS41
VSS42
VSS43
AD32
AB6
AB4
AB2
AB32Z6Z4Z2X36
VCC_CORE42
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VSS44
VSS45
VSS46
VSS47
VSS48
Z36
Z34
Z32X6AM28X4X2
X34
AM22
X32V6V4V2T36
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
VSS49
VSS50
VSS51
VSS52
VSS53
V36
V34
T34
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VSS54
VSS55
VSS56
VSS57
V32T6T4T2R36
T32R6R4R2AM18
VCC_CORE56
VCC_CORE57
VCC_CORE58
VCC_CORE59
VSS58
VSS59
VSS60
VSS61
R34
AM24
R32P6P4P2M36
P36
P34
P32M4M6M2K36
VCC_CORE60
VCC_CORE61
VCC_CORE62
VCC_CORE63
VSS62
VSS63
VSS64
VSS65
M34
K34
VCC_CORE64
VCC_CORE65
VCC_CORE66
VCC_CORE67
VCC_CORE68
VSS66
VSS67
VSS68
VSS69
VSS70
M32K6K4K2AM20
C
K32H4H2
AM14
VCC_CORE69
VCC_CORE70
VCC_CORE71
VCC_CORE72
VSS71
VSS72
VSS73
VSS74
H36
H34
F26
F36
F34
F32
F28
VCC_CORE73
VCC_CORE74
VCC_CORE75
VCC_CORE76
VSS75
VSS76
VSS77
VSS78
F22
F18
F14
F10F6F4F2AM16
F24
F20
F16
F12
VCC_CORE77
VCC_CORE78
VCC_CORE79
VCC_CORE80
VSS79
VSS80
VSS81
VSS82
D32
D28
AM10
D24
VCC_CORE81
VCC_CORE82
VCC_CORE83
VCC_CORE84
VSS83
VSS84
VSS85
VSS86
D36
D34
D30
D26
D20
D16
D12D8D4D2B36
VCC_CORE85
VCC_CORE86
VCC_CORE87
VCC_CORE88
VSS87
VSS88
VSS89
VSS90
D22
D18
D14
D10D6B34
B32
AM2
VCC_CORE89
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VSS91
VSS92
VSS93
VSS94
VSS95
AM12
B30
B26
B28
B24
VCC_CORE94
VCC_CORE95
VSS96
VSS97
B22
B18
A
P1_SDATA-[0..63]<9>
4 4
3 3
P1_DICLK-[0..3]<9>
2 2
P1_DOCLK-[0..3]<9>
P1_SDATA-0 P1_SDATA-1 P1_SDATA-2 P1_SDATA-3 P1_SDATA-4 P1_SDATA-5 P1_SDATA-6 P1_SDATA-7 P1_SDATA-8 P1_SDATA-9 P1_SDATA-10 P1_SDATA-11 P1_SDATA-12 P1_SDATA-13 P1_SDATA-14 P1_SDATA-15 P1_SDATA-16 P1_SDATA-17 P1_SDATA-18 P1_SDATA-19 P1_SDATA-20 P1_SDATA-21 P1_SDATA-22 P1_SDATA-23 P1_SDATA-24 P1_SDATA-25 P1_SDATA-26 P1_SDATA-27 P1_SDATA-28 P1_SDATA-29 P1_SDATA-30 P1_SDATA-31 P1_SDATA-32 P1_SDATA-33 P1_SDATA-34 P1_SDATA-35 P1_SDATA-36 P1_SDATA-37 P1_SDATA-38 P1_SDATA-39 P1_SDATA-40 P1_SDATA-41 P1_SDATA-42 P1_SDATA-43 P1_SDATA-44 P1_SDATA-45 P1_SDATA-46 P1_SDATA-47 P1_SDATA-48 P1_SDATA-49 P1_SDATA-50 P1_SDATA-51 P1_SDATA-52 P1_SDATA-53 P1_SDATA-54 P1_SDATA-55 P1_SDATA-56 P1_SDATA-57 P1_SDATA-58 P1_SDATA-59 P1_SDATA-60 P1_SDATA-61 P1_SDATA-62 P1_SDATA-63
P1_DICLK-0 P1_DICLK-1 P1_DICLK-2 P1_DICLK-3
P1_DIVAL-
P1_DIVAL-<9>
P1_DOCLK-0 P1_DOCLK-1 P1_DOCLK-2 P1_DOCLK-3
P1_AIN-[2..14]<9>
1 1
P1_AINCLK-<9>
P1_CFWDRST<9> P1_CONNECT<9> P1_PROCRDY<9> P1_SFILLVAL-<9>
A
P1_DOVAL-
P1_AIN-0 P1_AIN-1 P1_AIN-2 P1_AIN-3 P1_AIN-4 P1_AIN-5 P1_AIN-6 P1_AIN-7 P1_AIN-8 P1_AIN-9 P1_AIN-10 P1_AIN-11 P1_AIN-12 P1_AIN-13 P1_AIN-14
P1_CFWDRST P1_CONNECT P1_PROCRDY P1_SFILLVAL-
R156
10K
AA35
AA33 AE37 AC33 AC37
AA37 AC35
AN33
AE35
AL31
AL29 AG33
AL35 AE33
AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31
AL23 AN23
W37 W35
Y35 U35 U33 S37 S33
Y37
S35 Q37 Q35 N37
J33 G33 G37 E37 G35 Q33 N33
L33 N35
L37
J37 A37 E35 E31 E29 A27 A25 E21 C23 C27 A23 A35 C35 C33 C31 A29 C29 E23 C25 E17 E13 E11 C15
E9
A13
C9
A9 C21 A21 E19 C19 C17 A11 A17 A15
W33
J35 E27 E15
C37 A33 C11
AJ29
AJ37
AJ35
AJ33
AJ21
AJ31
SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 SDATA16 SDATA17 SDATA18 SDATA19 SDATA20 SDATA21 SDATA22 SDATA23 SDATA24 SDATA25 SDATA26 SDATA27 SDATA28 SDATA29 SDATA30 SDATA31 SDATA32 SDATA33 SDATA34 SDATA35 SDATA36 SDATA37 SDATA38 SDATA39 SDATA40 SDATA41 SDATA42 SDATA43 SDATA44 SDATA45 SDATA46 SDATA47 SDATA48 SDATA49 SDATA50 SDATA51 SDATA52 SDATA53 SDATA54 SDATA55 SDATA56 SDATA57 SDATA58 SDATA59 SDATA60 SDATA61 SDATA62 SDATA63
SDATAINCLK0 SDATAINCLK1 SDATAINCLK2 SDATAINCLK3
SDATAINVAL
SDATAOUTCLK0 SDATAOUTCLK1 SDATAOUTCLK2 SDATAOUTCLK3
SDTATOUTVAL
SADDIN0 SADDIN1 SADDIN2 SADDIN3 SADDIN4 SADDIN5 SADDIN6 SADDIN7 SADDIN8 SADDIN9 SADDIN10 SADDIN11 SADDIN12 SADDIN13 SADDIN14
SADDINCLK
CLKFWDRST CONNECT PROCRDY SFILLVAL
B
A20M
FERR
IGNNE
RESET
STPCLK
PWROK
PICCLK PICD0/BYPASSCLK PICD1/BYPASSCLK
COREFB-
COREFB+
CLKIN CLKIN
RSTCLK RSTCLK
K7CLKOUT K7CLKOUT
ANALOG
SYSVREFMODE
VREF_SYS
PLLBYPASS PLLBYPASSCLK PLLBYPASSCLK
PLLMON1 PLLMON2
PLLTEST
SCANCLK1
SCANCLK2 SCANINTEVAL SCANSHIFTEN
DBRDY DBREQ FLUSH
TRST
SCHECK0 SCHECK1 SCHECK2 SCHECK3 SCHECK4 SCHECK5 SCHECK6 SCHECK7
SADDOUT0
SADDOUT1
SADDOUT2
SADDOUT3
SADDOUT4
SADDOUT5
SADDOUT6
SADDOUT7
SADDOUT8
SADDOUT9
SADDOUT10 SADDOUT11 SADDOUT12 SADDOUT13 SADDOUT14
SADDOUTCLK
B
C
CPU2A
A20M-
AE1 AG1 AJ3
INIT
AL1
INTR
AJ1 AN3
NMI
AG3 AN5
SMI
AC1
AE3
R62 100
N1 N3 N5
AG13 AG11
AN17 AL17
AN19 AL19
AL21 AN21
AJ13
AA5 W5
AC5
ZN
AE5
ZP
AJ25 AN15 AL15
AN13 AL13 AC3
S1 S5 S3 Q5
P1_CPU_DBRDY
AA1
P1_DBREQ-
AA3
P1_FLUSH-
AL3
Q1
TCK
U1
TDI
P1_CPU_TDO
U5
TDO
Q3
TMS
U3
L1
VID0
L3
VID1
L5
VID2
L7
VID3
J7
VID4
W1
FID0
W3
FID1
Y1
FID2
Y3
FID3
P1_SCHECK-0
U37
P1_SCHECK-1
Y33
P1_SCHECK-2
L35
P1_SCHECK-3
E33
P1_SCHECK-4
E25
P1_SCHECK-5
A31
P1_SCHECK-6
C13
P1_SCHECK-7
A19
J1 J3
P1_AOUT-2
C7
P1_AOUT-3
A7
P1_AOUT-4
E5
P1_AOUT-5
A5
P1_AOUT-6
E7
P1_AOUT-7
C1
P1_AOUT-8
C5
P1_AOUT-9
C3
P1_AOUT-10
G1
P1_AOUT-11
E1
P1_AOUT-12
A3
P1_AOUT-13
G5
P1_AOUT-14
G3
E3
PGA-D462
FERR CPUINIT­INTR IGNNE­NMI CPURST­SMI­STPCLK-
APICD0­APICD1-
P1_COREFB­P1_COREFB
CPUCLK1_R CPUCLK-1_R
P1_CLKOUT P1_CLKOUT-
P1_VREFMODE P1_VREF_SYS
P1_ZN P1_ZP
P1_PLLBP-
P1_PLLMON1 P1_PLLMON2 P1_PLLTEST-
P1_SCANCLK1 P1_SCANCLK2 P1_SINTVAL P1_SSHIFTEN
P1_CPU_TCK P1_CPU_TDI
P1_CPU_TMS P1_CPU_TRST-
P1_VID0 P1_VID1 P1_VID2 P1_VID3 P1_VID4
P1_FID0 P1_FID1 P1_FID2 P1_FID3
A20M- <4,19> FERR <4> CPUINIT- <4,19> INTR <4,19> IGNNE- <4,19> NMI <4,19>
SMI- <4,19> STPCLK- <4,19>
P1_DC_OK <23>
APICCLK
APICD0- <4,34> APICD1- <4,34>
NOPOP
The farest VCORE and GND Already stuff on CPU0
P1_VID0 <34> P1_VID1 <34> P1_VID2 <34> P1_VID3 <34> P1_VID4 <34>
P1_FID0 <34> P1_FID1 <34> P1_FID2 <34> P1_FID3 <34>
**All CPU interface are 2.5V tolerant**
APICCLK <4,34>
P1_COREFB- <35> P1_COREFB <35>
R97
R103
100
100
NOPOP
VCORE
VCORE
RN33
78 56 34 12
100
P1_SCHECK-[0..7] <9>
P1_AOUT-[2..14] <9>
P1_AOUTCLK- <9>
CPURST- <4,19>
P1_PLLMON1 P1_PLLMON2 P1_FLUSH­P1_PLLBP-
P1_AIN-0
P1_AIN-1
P1_DOVAL-
P1_SFILLVAL-
CPUCLK1_R
CPUCLK-1_R
CPUCLK1<3>
VCORE
P1_SSHIFTEN P1_SINTVAL P1_SCANCLK2 P1_CPU_TDI
P1_DBREQ- P1_CPU_DBRDY CPURST-
VCORE
R101 56 R95 56 R89 680 R157 680
R172 270
R173 270
R180 270
R406 270
Reserved
R136 60.4
21
680pC154
R140 301
R143 60.4
21
680pC158
CPUCLK-1<3>
C
D
HDT1
P1_CPU_TCK
1
2
1
2
P1_CPU_TMS
3
4
3
4
P1_SCANCLK1
5
6
5
6
7
8
7
8
P1_CPU_TRST-
9
10
9
10 11 13 15 16
D2x8-BK
NOPOP
P1_CPU_TDO
12
12
14
14
P1_PLLTEST-
11 13 15 16
P1_VREFMODE
VREFMODE=Low=No voltage scaling
VCORE
Near socket-A
D
P1_DBREQ-
P1_PLLTEST-
P1_CPU_TCK P1_CPU_TMS P1_CPU_TRST­P1_CPU_TDI
VCORE
for internal VREFSYS
R118 1K
R113 270
P1_SCANCLK1 P1_SSHIFTEN P1_SINTVAL P1_SCANCLK2
7 8 5 6 3 4 1 2
Title
Size Document Number Rev
Custom
Date: Sheet
0.5 * VCORE
P1_VREF_SYS
C143
39p
RN30
10K
P1_CLKOUT P1_CLKOUT-
* Trace lengths of CLKOUT and -CLKOUT are between 2" and 3"
SocketA (Part 1)
C142
1000p
P1_ZN
P1_ZP
match the transmission line
Push-Pull compensation circuit
MICRO-STAR
MS-6502
E
R75 510
R81 510
RN31
510
VCORE
C141
0.047u
R119 40.2
R120 40.2
RN36
100
639Thursday, March 22, 2001
E
12 34 56 78
VCORE
VCORE
78 56 34 12
VCORE
R112 100
R117 100
of
0A
A
B
C
D
E
* 25 mils Trace/ 12 mils Space
RN32
100
VCC P1_VCCA_PLL1P1_VCCA_PLL
7 8 5 6 3 4 1 2
4 4
3 3
2 2
1 1
C122 39p
2 1
Max 150mA, Design for 100mA
AD30
AD8 AF10 AF28 AF30 AF32
AF6
AF8 AH30
AH8
AJ9 AK8 AL9
AM8
F30
F8 H10 H28 H30 H32
H6
H8 K30
K8
AJ7 AL7 AN7
G25 G17
G9
N7 Y7
AG7 AG15 AG29
C133 39p
H12
VCC_CORE1
VCC_SRAM1 VCC_SRAM2 VCC_SRAM3 VCC_SRAM4 VCC_SRAM5 VCC_SRAM6 VCC_SRAM7 VCC_SRAM8 VCC_SRAM9 VCC_SRAM11 VCC_SRAM13 VCC_SRAM14 VCC_SRAM16 VCC_SRAM17 VCC_SRAM19 VCC_SRAM20 VCC_SRAM21 VCC_SRAM22 VCC_SRAM23 VCC_SRAM24 VCC_SRAM25 VCC_SRAM26 VCC_SRAM27 VCC_SRAM28 VCC_SRAM29 VCC_SRAM30 VCC_SRAM31
KEY4 KEY6 KEY8 KEY10 KEY12 KEY14 KEY16 KEY18
VSS1
H14
2 1
3 1
VR5
CSK-2-SOT23-150mA
H16
H20
H24M8P30R8T30V8X30Z8AB30
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VCC_CORE6
VCC_CORE7
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
H18
H22
H26
M30P8R30T8V30X8Z30
A
R102 0
2
R122 0-REV
VCC_CORE8
VCC_CORE9
VCC_CORE10
VCC_CORE11
VSS8
VSS9
VSS10
VSS11
C134
0.01u
Used when spec. change
AF14
AF18
AF22
VCC_CORE12
VCC_CORE13
VCC_CORE14
VCC_CORE15
VSS12
VSS13
VSS14
VSS15
AB8
AF12
AF16
AF20
AF26
AM34
VCC_CORE16
VCC_CORE17
VSS16
VSS17
AF24
AM36
2.5V
R167 10R114 0
C175 39p
2 1
NOPOP
C173 39p
2 1
Place inside CPU socket
C144 39p
2 1
NOPOP
VCCA_PLL trace length from the VR1 to the PGA must be 0.75".
Place al filters close to the PGA.
Keep all power and signal trce away from the VR1.
Place a cut in the GND plane around the VCCA_PLL regulator circuit.
AK36
AK34
AK30
AK26
AK22
AK18
AK14
AK10
AL5
AH26
AM30
AH22
AH18
AH14
AH10
AH4
AH2
AF36
AF34
AD6
AM26
VCC_CORE18
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
VCC_CORE27
VCC_CORE28
VCC_CORE29
VCC_CORE30
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS37
VSS38
AK32
AK28
AK24
AK20
AK16
AK12
AK4
AK2
AH36
AM32
AH34
AH32
AH28
AH24
AH20
AH16
AH12
VSS39
AF4
AF2
AD36
AD34
B
C189 39p
2 1
AD4
AD2
AB36
AB34
VCC_CORE38
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VSS40
VSS41
VSS42
VSS43
VSS44
AD32
AB6
AB4
AB2
AB32Z6Z4Z2X36
VCC_CORE43
VCC_CORE44
VCC_CORE45
VSS45
VSS46
VSS47
Z36
Z34
Z32X6AM28X4X2
VCORE
X34
AM22
X32V6V4V2T36
VCC_CORE46
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VSS48
VSS49
VSS50
VSS51
VSS52
V36
Power Up Strappings :
AD[3:0] => CPU Clock Multiplier
0000 3 0001 3.5 0010 4 0011 4.5 0100 5 0101 5.5 0110 6 0111 6.5
T34
T32R6R4R2AM18
VCC_CORE51
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VCC_CORE56
VCC_CORE57
VCC_CORE58
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
V34
V32T6T4T2R36
R34
AM24
R32P6P4P2M36
P36
P34
P32M4M6M2K36
VCC_CORE59
VCC_CORE60
VCC_CORE61
VCC_CORE62
VSS61
VSS62
VSS63
VSS64
VCC_CORE63
VCC_CORE64
VCC_CORE65
VCC_CORE66
VSS65
VSS66
VSS67
VSS68
M34
M32K6K4K2AM20
C
1000 7 1001 7.5 1010 8 1011 8.5 1100 9 1101 9.5 1110 10 1111 Reserved
K34
K32H4H2
AM14
VCC_CORE67
VCC_CORE68
VCC_CORE69
VCC_CORE70
VCC_CORE71
VSS69
VSS70
VSS71
VSS72
VSS73
H36
H34
F26
F36
F34
F32
F28
VCC_CORE72
VCC_CORE73
VCC_CORE74
VCC_CORE75
VCC_CORE76
VSS74
VSS75
VSS76
VSS77
VSS78
F22
F18
F14
F10F6F4F2AM16
F24
F20
F16
F12
VCC_CORE77
VCC_CORE78
VCC_CORE79
VCC_CORE80
VSS79
VSS80
VSS81
VSS82
D32
D28
AM10
D24
VCC_CORE81
VCC_CORE82
VCC_CORE83
VCC_CORE84
VSS83
VSS84
VSS85
VSS86
D36
D34
D30
D26
D20
D16
D12D8D4D2B36
VCC_CORE85
VCC_CORE86
VCC_CORE87
VCC_CORE88
VSS87
VSS88
VSS89
VSS90
D22
D18
D14
D10D6B34
B32
AM2
VCC_CORE89
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VSS91
VSS92
VSS93
VSS94
VSS95
AM12
B30
B26
B28
B24
B20
B16
VCC_CORE94
VCC_CORE95
VCC_CORE96
VSS96
VSS97
VSS98
B22
B18
B14
B10B6B2
B12B8B4
AJ5
VCC_CORE97
VCC_CORE98
VCC_CORE99
VCC_CORE100
VCC_CORE101
VSS99
VSS100
VSS101
VSS102
VSS103
AM4
AK6
D
P1_VCCA_PLL
0~100 mA,
2.25~2.75V
CPU2B
AC7
AJ23
PGA-D462
VCC_Z
VCC_A
AA31
NC1
AC31
NC2
AE31
NC3
AG23
NC6
AG25
NC7
AG31
NC8
AG5
NC9
AJ11
NC10
AJ15
NC11
AJ17
NC12
AJ19
NC13
AJ27
NC15
AL11
NC16
AN11
NC17
AN9
NC18
G11
NC19
G13
NC20
G27
NC21
G29
NC22
G31
NC23
J31
NC24
J5
NC25
L31
NC27
N31
NC28
Q31
NC29
S31
NC30
S7
NC31
U31
NC32
U7
NC33
W31
NC34
W7
NC35
Y31
NC36
Y5
NC37
AG19
NC42
G21
NC43
AG21
NC44
G19
NC45
AN27
BP0_CUT
AL27
BP1_CUT
AN25
BP2_CUT
AL25
BP3_CUT
VSS104
VSS_Z
AM6
AE7
Title
Size Document Number Rev
Custom
Date: Sheet
P1BP0 <34> P1BP1 <34> P1BP2 <34> P1BP3 <34>
MICRO-STAR
SocketA (Part 2)
MS-6502
739Wednesday, March 21, 2001
of
E
0A
5
D D
BELONG TO CLKFWD GROUP[SADDIN] MATCH W/IN +/-50MILS OF GROUP 5/10, CLK:5/20
BELONG TO CLKFWD GROUP[SADDOUT] MATCH
C C
W/IN +/-50MILS OF GROUP 5/10, CLK:5/20
BELONG TO CLKFWD GROUP;MATCHED TO INDIVIDUAL CLKFWD GROUP
RESPECTIVELY.[SDATA0], [SDATA1], [SDATA2],[SDATA3] W/IN+/-50MILS OF GROUP
B B
P0_AIN-[2..14]<4>
--------------------------------
P0_AOUT-[2..14]<4>
--------------------------------
P0_SCHECK-[0..7]<4>
----------------------
P0_DICLK-[0..3]<4>
P0_DOCLK-[0..3]<4>
4
AH20
AC5
AC4
AC6
AA2 AA6
AA4 AA3 AA5 AB3 AB5
AD1 AC3 AC1
AA7
AB1
Y4
Y5
Y6
G1 H2 G3 F4 H4 E1 F3 F2 F5 G5 F1 E2 D1
E3
V7 V8 P8 T1 N7 N1
J3
K3
U5 R1 M1 H3
W5
R8 N5 H1
J8
AMD-AMD762
U23A
P0_CLKFWDRST
P0_CONNECT
P0_PROCRDY
SYSCLK
P0_SADDIN2# P0_SADDIN3# P0_SADDIN4# P0_SADDIN5# P0_SADDIN6# P0_SADDIN7# P0_SADDIN8# P0_SADDIN9# P0_SADDIN10# P0_SADDIN11# P0_SADDIN12# P0_SADDIN13# P0_SADDIN14#
P0_SADDINCLK#
P0_SADDOUT2# P0_SADDOUT3# P0_SADDOUT4# P0_SADDOUT5# P0_SADDOUT6# P0_SADDOUT7# P0_SADDOUT8# P0_SADDOUT9# P0_SADDOUT10# P0_SADDOUT11# P0_SADDOUT12# P0_SADDOUT13# P0_SADDOUT14#
P0_SADDOUTCLK#
P0_SCHECK0# P0_SCHECK1# P0_SCHECK2# P0_SCHECK3# P0_SCHECK4# P0_SCHECK5# P0_SCHECK6# P0_SCHECK7#
P0_SDATAINCLK0# P0_SDATAINCLK1# P0_SDATAINCLK2# P0_SDATAINCLK3#
P0_SDATAINVALID#
P0_SDATAOUTCLK0# P0_SDATAOUTCLK1# P0_SDATAOUTCLK2# P0_SDATAOUTCLK3#
P0_SYSFILLVALID#
P0_CFWDRST<4>
P0_CONNECT<4>
P0_PROCRDY<4>
CPUCLK2<3>
P0_AINCLK-<4>
P0_AOUTCLK-<4>
P0_SFILLVAL-<4>
P0_CFWDRST
P0_CONNECT
P0_PROCRDY
CPUCLK2
P0_AIN-2 P0_AIN-3 P0_AIN-4 P0_AIN-5 P0_AIN-6 P0_AIN-7 P0_AIN-8 P0_AIN-9 P0_AIN-10 P0_AIN-11 P0_AIN-12 P0_AIN-13 P0_AIN-14
P0_AINCLK-
P0_AOUT-2 P0_AOUT-3 P0_AOUT-4 P0_AOUT-5 P0_AOUT-6 P0_AOUT-7 P0_AOUT-8 P0_AOUT-9 P0_AOUT-10 P0_AOUT-11 P0_AOUT-12 P0_AOUT-13 P0_AOUT-14
P0_AOUTCLK-
P0_SCHECK-0 P0_SCHECK-1 P0_SCHECK-2 P0_SCHECK-3 P0_SCHECK-4 P0_SCHECK-5 P0_SCHECK-6 P0_SCHECK-7
P0_DICLK-0 P0_DICLK-1 P0_DICLK-2 P0_DICLK-3
P0_DIVAL-<4>
P0_DIVAL-
P0_DOCLK-0 P0_DOCLK-1 P0_DOCLK-2 P0_DOCLK-3
3
AMD-762
System Bus 0
P0_SDATA0# P0_SDATA1# P0_SDATA2# P0_SDATA3# P0_SDATA4# P0_SDATA5# P0_SDATA6# P0_SDATA7# P0_SDATA8#
P0_SDATA9# P0_SDATA10# P0_SDATA11# P0_SDATA12# P0_SDATA13# P0_SDATA14# P0_SDATA15# P0_SDATA16# P0_SDATA17# P0_SDATA18# P0_SDATA19# P0_SDATA20# P0_SDATA21# P0_SDATA22# P0_SDATA23# P0_SDATA24# P0_SDATA25# P0_SDATA26# P0_SDATA27# P0_SDATA28# P0_SDATA29# P0_SDATA30# P0_SDATA31# P0_SDATA32# P0_SDATA33# P0_SDATA34# P0_SDATA35# P0_SDATA36# P0_SDATA37# P0_SDATA38# P0_SDATA39# P0_SDATA40# P0_SDATA41# P0_SDATA42# P0_SDATA43# P0_SDATA44# P0_SDATA45# P0_SDATA46# P0_SDATA47# P0_SDATA48# P0_SDATA49# P0_SDATA50# P0_SDATA51# P0_SDATA52# P0_SDATA53# P0_SDATA54# P0_SDATA55# P0_SDATA56# P0_SDATA57# P0_SDATA58# P0_SDATA59# P0_SDATA60# P0_SDATA61# P0_SDATA62# P0_SDATA63#
P0_VREF
W3 V4 V3 V5 V6 U4 U3 U8 Y1 Y3 AA1 Y7 W1 W7 Y2 U6 U7 R7 R6 R5 R3 R4 R2 U2 T7 V1 T5 V2 T3 U1 P6 P1 P2 P4 M8 M6 L3 L7 M4 L6 P7 P5 N3 P3 M5 M7 L5 M3 K7 J6 J7 K5 J4 J2 H6 H5 M2 L4 L2 L1 K1 H7 J5 J1
AC2
P0_SDATA-0 P0_SDATA-1 P0_SDATA-2 P0_SDATA-3 P0_SDATA-4 P0_SDATA-5 P0_SDATA-6 P0_SDATA-7 P0_SDATA-8 P0_SDATA-9 P0_SDATA-10 P0_SDATA-11 P0_SDATA-12 P0_SDATA-13 P0_SDATA-14 P0_SDATA-15 P0_SDATA-16 P0_SDATA-17 P0_SDATA-18 P0_SDATA-19 P0_SDATA-20 P0_SDATA-21 P0_SDATA-22 P0_SDATA-23 P0_SDATA-24 P0_SDATA-25 P0_SDATA-26 P0_SDATA-27 P0_SDATA-28 P0_SDATA-29 P0_SDATA-30 P0_SDATA-31 P0_SDATA-32 P0_SDATA-33 P0_SDATA-34 P0_SDATA-35 P0_SDATA-36 P0_SDATA-37 P0_SDATA-38 P0_SDATA-39 P0_SDATA-40 P0_SDATA-41 P0_SDATA-42 P0_SDATA-43 P0_SDATA-44 P0_SDATA-45 P0_SDATA-46 P0_SDATA-47 P0_SDATA-48 P0_SDATA-49 P0_SDATA-50 P0_SDATA-51 P0_SDATA-52 P0_SDATA-53 P0_SDATA-54 P0_SDATA-55 P0_SDATA-56 P0_SDATA-57 P0_SDATA-58 P0_SDATA-59 P0_SDATA-60 P0_SDATA-61 P0_SDATA-62 P0_SDATA-63
P0_S2K_VREF
2
P0_SDATA-[0..63] <4>
+12V
JFAN1
2 1
D1x2-WH
1
VCC2_5
R408 100
CPUCLK2
R410 150
Put these two res. very close to N.B.
U3_X
_
Set S2K_VREF to 50% of VCORE
P0_S2K_VREF
C265
C270
0.047u
0.039u
VCORE
R248 100
R251 100
A A
Title
{Title}
Size Document Number Rev
MS-6502 0A
B
5
4
3
2
Date: Sheet
839Wednesday, March 21, 2001
of
1
5
D D
BELONG TO CLKFWD GROUP[SADDIN] MATCH W/IN +/-50MILS OF GROUP 5/10, CLK:5/20
BELONG TO CLKFWD GROUP[SADDOUT] MATCH
C C
W/IN +/-50MILS OF GROUP 5/10, CLK:5/20
BELONG TO CLKFWD GROUP;MATCHED TO INDIVIDUAL CLKFWD GROUP
RESPECTIVELY.[SDATA0], [SDATA1], [SDATA2],[SDATA3] W/IN+/-50MILS OF GROUP
B B
P1_AIN-[2..14]<6>
--------------------------------
P1_AOUT-[2..14]<6>
--------------------------------
P1_SCHECK-[0..7]<6>
----------------------
P1_DICLK-[0..3]<6>
P1_DOCLK-[0..3]<6>
4
AE19
AG17 AH18
AF17 AG16 AG18 AD17 AK18 AK17 AG19 AE18 AF18
AG14
AH12
AE15 AD12
AE17
AH15 AH11
AL19
AJ19
AL18 AL17
AJ18
AK3 AE3
AG3
AF3 AD7
AF2 AD5 AD6 AF1 AH1
AG2
AG1
AL15
AJ10
AL9
AG8
AF6 AL7
AK5
AG9
AL20
AJ2
AJ3
AJ8
AJ4
AMD-AMD762
U23B
P1_CLKFWDRST
P1_CONNECT
P1_PROCRDY
P1_SADDIN2# P1_SADDIN3# P1_SADDIN4# P1_SADDIN5# P1_SADDIN6# P1_SADDIN7# P1_SADDIN8# P1_SADDIN9# P1_SADDIN10# P1_SADDIN11# P1_SADDIN12# P1_SADDIN13# P1_SADDIN14#
P1_SADDINCLK#
P1_SADDOUT2# P1_SADDOUT3# P1_SADDOUT4# P1_SADDOUT5# P1_SADDOUT6# P1_SADDOUT7# P1_SADDOUT8# P1_SADDOUT9# P1_SADDOUT10# P1_SADDOUT11# P1_SADDOUT12# P1_SADDOUT13# P1_SADDOUT14#
P1_SADDOUTCLK#
P1_SCHECK0# P1_SCHECK1# P1_SCHECK2# P1_SCHECK3# P1_SCHECK4# P1_SCHECK5# P1_SCHECK6# P1_SCHECK7#
P1_SDATAINCLK0# P1_SDATAINCLK1# P1_SDATAINCLK2# P1_SDATAINCLK3#
P1_SDATAINVALID#
P1_SDATAOUTCLK0# P1_SDATAOUTCLK1# P1_SDATAOUTCLK2# P1_SDATAOUTCLK3#
P1_SYSFILLVALID#
P1_CFWDRST<6>
P1_CONNECT<6>
P1_PROCRDY<6>
P1_AINCLK-<6>
P1_AOUTCLK-<6>
P1_SFILLVAL-<6>
P1_CFWDRST
P1_CONNECT
P1_PROCRDY
P1_AIN-2 P1_AIN-3 P1_AIN-4 P1_AIN-5 P1_AIN-6 P1_AIN-7 P1_AIN-8 P1_AIN-9 P1_AIN-10 P1_AIN-11 P1_AIN-12 P1_AIN-13 P1_AIN-14
P1_AINCLK-
P1_AOUT-2 P1_AOUT-3 P1_AOUT-4 P1_AOUT-5 P1_AOUT-6 P1_AOUT-7 P1_AOUT-8 P1_AOUT-9 P1_AOUT-10 P1_AOUT-11 P1_AOUT-12 P1_AOUT-13 P1_AOUT-14
P1_AOUTCLK-
P1_SCHECK-0 P1_SCHECK-1 P1_SCHECK-2 P1_SCHECK-3 P1_SCHECK-4 P1_SCHECK-5 P1_SCHECK-6 P1_SCHECK-7
P1_DICLK-0 P1_DICLK-1 P1_DICLK-2 P1_DICLK-3
P1_DIVAL-<6>
P1_DIVAL-
P1_DOCLK-0 P1_DOCLK-1 P1_DOCLK-2 P1_DOCLK-3
P1_SFILLVAL-
3
AMD-762
System Bus 1
P1_SDATA0#
P1_SDATA1#
P1_SDATA2#
P1_SDATA3#
P1_SDATA4#
P1_SDATA5#
P1_SDATA6#
P1_SDATA7#
P1_SDATA8#
P1_SDATA9# P1_SDATA10# P1_SDATA11# P1_SDATA12# P1_SDATA13# P1_SDATA14# P1_SDATA15# P1_SDATA16# P1_SDATA17# P1_SDATA18# P1_SDATA19# P1_SDATA20# P1_SDATA21# P1_SDATA22# P1_SDATA23# P1_SDATA24# P1_SDATA25# P1_SDATA26# P1_SDATA27# P1_SDATA28# P1_SDATA29# P1_SDATA30# P1_SDATA31# P1_SDATA32# P1_SDATA33# P1_SDATA34# P1_SDATA35# P1_SDATA36# P1_SDATA37# P1_SDATA38# P1_SDATA39# P1_SDATA40# P1_SDATA41# P1_SDATA42# P1_SDATA43# P1_SDATA44# P1_SDATA45# P1_SDATA46# P1_SDATA47# P1_SDATA48# P1_SDATA49# P1_SDATA50# P1_SDATA51# P1_SDATA52# P1_SDATA53# P1_SDATA54# P1_SDATA55# P1_SDATA56# P1_SDATA57# P1_SDATA58# P1_SDATA59# P1_SDATA60# P1_SDATA61# P1_SDATA62# P1_SDATA63#
P1_VREF
AE14 AJ14 AE16 AD14 AJ15 AL14 AK15 AE13 AL16 AD15 AG15 AF15 AJ16 AH17 AJ17 AH14 AF14 AF12 AE12 AK12 AJ11 AE11 AG11 AF11 AK14 AL13 AL12 AG13 AJ13 AG12 AJ12 AL11 AG7 AF9 AK11 AL10 AK8 AL8 AH8 AK9 AE10 AE9 AD11 AG10 AJ9 AH9 AF8 AJ7 AF4 AG5 AF5 AK6 AH4 AJ5 AL4 AH3 AE8 AE7 AG6 AL6 AJ6 AE5 AH6 AL5
AB7
P1_SDATA-0 P1_SDATA-1 P1_SDATA-2 P1_SDATA-3 P1_SDATA-4 P1_SDATA-5 P1_SDATA-6 P1_SDATA-7 P1_SDATA-8 P1_SDATA-9 P1_SDATA-10 P1_SDATA-11 P1_SDATA-12 P1_SDATA-13 P1_SDATA-14 P1_SDATA-15 P1_SDATA-16 P1_SDATA-17 P1_SDATA-18 P1_SDATA-19 P1_SDATA-20 P1_SDATA-21 P1_SDATA-22 P1_SDATA-23 P1_SDATA-24 P1_SDATA-25 P1_SDATA-26 P1_SDATA-27 P1_SDATA-28 P1_SDATA-29 P1_SDATA-30 P1_SDATA-31 P1_SDATA-32 P1_SDATA-33 P1_SDATA-34 P1_SDATA-35 P1_SDATA-36 P1_SDATA-37 P1_SDATA-38 P1_SDATA-39 P1_SDATA-40 P1_SDATA-41 P1_SDATA-42 P1_SDATA-43 P1_SDATA-44 P1_SDATA-45 P1_SDATA-46 P1_SDATA-47 P1_SDATA-48 P1_SDATA-49 P1_SDATA-50 P1_SDATA-51 P1_SDATA-52 P1_SDATA-53 P1_SDATA-54 P1_SDATA-55 P1_SDATA-56 P1_SDATA-57 P1_SDATA-58 P1_SDATA-59 P1_SDATA-60 P1_SDATA-61 P1_SDATA-62 P1_SDATA-63
P1_S2K_VREF
2
P1_SDATA-[0..63] <6>
1
Set S2K_VREF to 50% of VCORE
P1_S2K_VREF
C261
0.047u
C250
0.039u
VCORE
R242 100
R244 100
A A
Title
{Title}
Size Document Number Rev
MS-6502 0A
B
5
4
3
2
Date: Sheet
939Wednesday, March 21, 2001
of
1
5
D D
C C
B B
CLKOUT[0..5]<36>
CLKOUT-[0..5]<36>
A A
DDR_REF
5
C530
0.1u
C532
0.1u
(near the chip)
DDR_VREF
VCC2_5
CLKOUT0 CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5
CLKOUT-0 CLKOUT-1 CLKOUT-2 CLKOUT-3 CLKOUT-4 CLKOUT-5
4
U23E
MAA0
F17
MAA0
MAA1
G15
MAA1
MAA2
E15
MAA2
MAA3
G14
MAA3
MAA4
F14
MAA4
MAA5
E11
MAA5
MAA6
G12
MAA6
MAA7
G9
MAA7
MAA8
G11
MAA8
MAA9
G10
MAA9
MAA10
F18
MAA10
MAA11
H11
MAA11
MAA12
F9
MAA12
MAA13
G19
MAA13
MAA14
MAA[0..14]<36>
MAB[0..14]<36>
DM[0..8]<36>
CS-[0..7]<36>
RASA-<36> RASB-<36>
CASA-<36> CASB-<36>
WEA-<36> WEB-<36>
CKEA<36> CKEB<36>
4
G18
MAA14
MAB0
H17
MAB0
MAB1
H15
MAB1
MAB2
F15
MAB2
MAB3
H14
MAB3
MAB4
E14
MAB4
MAB5
E12
MAB5
MAB6
G13
MAB6
MAB7
H12
MAB7
MAB8
F12
MAB8
MAB9
F11
MAB9
MAB10
H18
MAB10
MAB11
H9
MAB11
MAB12
E9
MAB12
MAB13
E20
MAB13
MAB14
E18
MAB14
DM0
B5
DM0
DM1
D8
DM1
DM2
A11
DM2
DM3
D14
DM3
DM4
E19
DM4
DM5
A22
DM5
DM6
D24
DM6
DM7
A28
DM7
DM8
C17
DM8
CS-0
H21
CS0#
CS-1
E23
CS1#
CS-2
F21
CS2#
CS-3
F23
CS3#
CS-4
H23
CS4#
CS-5
G23
CS5#
CS-6
G24
CS6#
CS-7
F24
CS7#
RASA-
G20
RASA#
RASB-
F20
RASB#
CASA-
G22
CASA#
CASB-
G21
CASB#
WEA- MDAT57
E21
WEA#
WEB-
H20
WEB#
CKEA
G8
CKEA
CKEB
F8
CLKOUT0 CLKOUT-0 CLKOUT1 CLKOUT-1 CLKOUT2 CLKOUT-2 CLKOUT3 CLKOUT-3 CLKOUT4 CLKOUT-4 CLKOUT5 CLKOUT-5
DDR_REF
CKEB
G16
CLKOUT0
G17
CLKOUT#0
E6
CLKOUT1
F6
CLKOUT#1
E24
CLKOUT2
E25
CLKOUT#2
E16
CLKOUT3
E17
CLKOUT#3
E7
CLKOUT4
E8
CLKOUT#4
E26
CLKOUT5
F26
CLKOUT#5
D4
DDR_REF
MECC[0..7]<36>
3
AMD-762
DDR Interface
PDL_OUTPUT_TEST
MECC0
MECC1
MECC2
MECC3
MECC4
C15
A16
A17
D17
C14
MECC0
MECC1
MECC4
MECC2
MECC3
3
MECC5
D15
B17
MECC6
MECC5
MECC6
MECC7
A18
MECC7
MDAT0 MDAT1 MDAT2 MDAT3 MDAT4 MDAT5 MDAT6 MDAT7 MDAT8
MDAT9 MDAT10 MDAT11 MDAT12 MDAT13 MDAT14 MDAT15 MDAT16 MDAT17 MDAT18 MDAT19 MDAT20 MDAT21 MDAT22 MDAT23 MDAT24 MDAT25 MDAT26 MDAT27 MDAT28 MDAT29 MDAT30 MDAT31 MDAT32 MDAT33 MDAT34 MDAT35 MDAT36 MDAT37 MDAT38 MDAT39 MDAT40 MDAT41 MDAT42 MDAT43 MDAT44 MDAT45 MDAT46 MDAT47 MDAT48 MDAT49 MDAT50 MDAT51 MDAT52 MDAT53 MDAT54 MDAT55 MDAT56 MDAT57 MDAT58 MDAT59 MDAT60 MDAT61 MDAT62 MDAT63
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
AMD-AMD762
2
VCC2_5
C542 0.1u
MDAT0
C4
MDAT1
A4
MDAT2
B6
MDAT3
D6
MDAT4
C3
MDAT5
B3
MDAT6
C5
MDAT7
A6
MDAT8
C6
MDAT9
C7
MDAT10
A9
MDAT11
D9
MDAT12
A7
MDAT13
B8
MDAT14
C8
MDAT15
B9
MDAT16
E10
MDAT17
A10
MDAT18
D11
MDAT19
B12
MDAT20
C9
MDAT21
B11
MDAT22
C11
MDAT23
D12
MDAT24
A12
MDAT25
E13
MDAT26
A14
MDAT27
B15
MDAT28
C12
MDAT29
A13
MDAT30
B14
MDAT31
A15
MDAT32
B18
MDAT33
A19
MDAT34
A20
MDAT35
D20
MDAT36
C18
MDAT37
D18
MDAT38
B20
MDAT39
C20
MDAT40
B21
MDAT41
D21
MDAT42
E22
MDAT43
B23
MDAT44
A21
MDAT45
C21
MDAT46
A23
MDAT47
C23
MDAT48
D23
MDAT49
B24
MDAT50
B26
MDAT51
C26
MDAT52
A24
MDAT53
C24
MDAT54
A25
MDAT55
A26
MDAT56
C27 B27
MDAT58
C29
MDAT59
C30
MDAT60
A27
MDAT61
D26
MDAT62
D28
MDAT63
B29
DQS0
A5
DQS1
A8
DQS2
C10
DQS3
C13
DQS4
C19
DQS5
C22
DQS6
C25
DQS7
C28
DQS8
C16
TP3
D3
Place near IGD4 for VCC2_5 decoupling
MDAT[0..63] <36>
DQS[0..8] <36>
2
C541 0.1u
C540 0.1u
C361 0.1u
C357 0.1u
C539 0.1u
C360 0.1u
VCC2_5
C528 100p
C513 100p
C519 0.1u
C524 0.1u
C511 100p
C518 1000p
C525 1000p
C527 0.1u
Place under IGD4 (NOPOP)
Title
Size Document Number Rev Custom
Date: Sheet of
North Bridge AMD762-DDR
1
MICRO-STAR
MS-6502
1
10 39Wednesday, March 21, 2001
0F
5
4
3
2
1
AMD-762 PCI Bus
AA28 AA31
AA30
AA27
AF21
W29
W31
W27
W25
P27 R29 P30 T25 P31 U24 R26 U25 T29 R31 V24 T27 R30 T31 U26 U27 V27
V26 Y28
Y29
Y25 Y31
Y30
Y27 Y26
R27 V25
Y24
V28 V31 H28 V29 U31 U29 U30 V30
J24 J25
E30 F30 H25 H27 F29 G27 E29
D31 E31 G29 H26 F28 F27 D29
U23C
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
CBE0# CBE1# CBE2# CBE3#
DEVSEL# FRAME# WSC# IRDY# PAR SERR# STOP# TRDY#
SBREQ# SBGNT#
REQ0# REQ1# REQ2# REQ3# REQ4# REQ5# REQ6#
GNT0# GNT1# GNT2# GNT3# GNT4# GNT5# GNT6#
RESET#
AMD-AMD762
AD32 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD40 AD41 AD42 AD43 AD44 AD45 AD46 AD47 AD48 AD49 AD50 AD51 AD52 AD53 AD54 AD55 AD56 AD57 AD58 AD59 AD60 AD61 AD62 AD63
CBE4 CBE5 CBE6 CBE7
PAR64
ACK64#
REQ64#
M66
VDD_PCI0 VDD_PCI1 VDD_PCI2 VDD_PCI3 VDD_PCI4 VDD_PCI5 VDD_PCI6 VDD_PCI7 VDD_PCI8
VDD_PCI9 VDD_PCI10 VDD_PCI20 VDD_PCI21 VDD_PCI22 VDD_PCI23 VDD_PCI24
PCI66_CLK0 PCI66_CLK1 PCI66_CLK2
PCICLK
4
K25 G31 L24 H30 J26 H31 J28 J30 J29 J31 L25 J27 M24 K27 K29 L26 L28 L27 L29 K31 M28 L30 M25 L31 P24 M26 M29 M27 N25 N27 R24
R25 M31 N29 N31
M30 R28 P26 U28
D30 G30 K26 K30 N26 N30 T26 T30 W26 W30 G26 L23 N23 R23 U23 W23
P25 P28 P29
AH21
C_BE-4 C_BE-5 C_BE-6 C_BE-7
PAR64 ACK64­REQ64-
VCC3
AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD40 AD41 AD42 AD43 AD44 AD45 AD46 AD47 AD48 AD49 AD50 AD51 AD52 AD53 AD54 AD55 AD56 AD57 AD58 AD59 AD60 AD61 AD62 AD63
M66EN-
PAR64 <16> ACK64- <16> REQ64- <16>WSC-<19>
R273 4.7K
R275
4.7K
NBCLK <3>
NOPOP
AD32
F31
AD[32..63] <16>
C_BE-[4..7] <16>
VCC3
AMD DOC SCH AGP_CAL- 34.8 56.2 AGP_CAL 39.2 56.2
R252 R0603MS
AGP_CAL-
R268 38.4
AGP_CAL
AGP_VREF2X
C259
0.01u
(near the chip)
3
D D
C C
B B
A A
AD[0..31]8,19,29,31,34,37>
VCC3
R287
4.7K
C_BE-[0..3]
C_BE-[0..3]<16,17,18,19,29,31,37>
5
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C_BE-0 C_BE-1 C_BE-2 C_BE-3
DEVSEL-<16,17,18,19,29,31>
FRAME-<16,17,18,19,29,31>
PCIRST-2<13,21,29,31,34>
WSC-
IRDY-<16,17,18,19,29,31>
PAR<16,17,18,19,29,31,37> SERR-<16,17,18,19,31> STOP-<16,17,18,19,29,31> TRDY-<16,17,18,19,29,31>
SBREQ-<19,20> SBGNT-<19,20>
REQ0-<18,31> REQ1-<16,18> REQ2-<16,18> REQ3-<17,18> REQ4-<17,18> REQ5-<18> REQ6-<18,29>
GNT0-<31> GNT1-<16> GNT2-<16> GNT3-<17> GNT4-<17> GNT5-<18> GNT6-<29>
GAD[0..31]<15>
GCLK0<3>
VDDQ
R249 150
R245
100
GAD[0..31]
VDDQ
R237 100
Reserved
C239 100p
Reserved
GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31
VDDQ
AB31 AA26 AC31 AA25 AC30 AB29 AD31 AC26 AC27
AG31
AC29 AH31 AB25 AD29 AC28 AE29 AD26 AH28 AJ30
AG29
AK29 AF27 AH29
AG27
AL28 AJ26 AD25
AF24 AG26 AG24
AF23
AE25
AJ21
AA23
AB26
AB30
AC23
AF22
AE26
AE30
AH30
AK22
AK25
AK28
AF25
Y22 AB22 AC21
AB20
2
AMD-762 AGP Bus
U23D
GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31
AGPCLK
VDD_AGP0 VDD_AGP1 VDD_AGP2 VDD_AGP3 VDD_AGP4 VDD_AGP5 VDD_AGP6 VDD_AGP7 VDD_AGP8 VDD_AGP9 VDD_AGP10 VDD_AGP11 VDD_AGP12 VDD_AGP13 VDD_AGP14
VDD_AGP15
AMD-AMD762
Title
{Title}
Size Document Number Rev
MS-6502 0A
B
Date: Sheet
GCBE0# GCBE1# GCBE2# GCBE3#
GDEVSEL#
GFRAME#
GSERR#
GSTOP# GTRDY#
GIRDY#
GPAR WBF# PIPE#
RBF#
GGNT# GREQ#
ADSTB0
ADSTB0#
ADSTB1
ADSTB1#
SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7
SBSTB
SBSTB#
AGP_VREF4X
AGP_VREF
AGP_CAL
AGP_CAL#VDD_AGP15
AGP_VREF4X_IN
C262
0.01u
ST0 ST1 ST2
C257
1u
AB27 AD28 AJ29 AF26
AC24 AF29 AE27 AK27 AF30 AF28 AD27 AK26 AL25 AL26
AL23 AK23
AK24 AL24 AJ23
AE31 AD30 AJ27 AJ28
AG23 AE23 AJ25 AD23 AE24 AG25 AL27 AH26
AJ24 AH24
AC25 AG30
AA24 AF31AA21
SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7
SBSTB SBSTB-
AGP_VREF4X_IN AGP_VREF2X
AGP_CAL AGP_CAL-
AGP_VREF4X_IN <15>
C254
0.1u
1
GCBE0- <15> GCBE1- <15> GCBE2- <15> GCBE3- <15>
GDEVSEL- <15> GFRAME- <15> GSERR- <15> GSTOP- <15> GTRDY- <15> GIRDY- <15> GPAR <15> WBF- <15> PIPE- <15> RBF- <15>
GGNT- <15> GREQ- <15>
ST0 <15> ST1 <15> ST2 <15>
ADSTB0 <15> ADSTB0- <15> ADSTB1 <15> ADSTB1- <15>
SBA[0..7]
SBSTB <15> SBSTB- <15>
11 39Wednesday, March 21, 2001
of
SBA[0..7] <15>
5
D D
C C
B B
VCC2_5
A A
Power for clock PLL. MUST close to AMD-762
0_1206
FB21
100p
C492
4.7u-0805
C495
5
C491
4.7u-0805
4
AMD-762
U23F
AA11 D2
VDD_CORE P0_K7_VCORE0
AA13
VDD_CORE
AA15
VDD_CORE
AA17
VDD_CORE
AA19
VDD_CORE
B10
VDD_CORE
B13
VDD_CORE
B16
VDD_CORE
B19
VDD_CORE
B22
VDD_CORE
B25
VDD_CORE
B28
VDD_CORE
B4
VDD_CORE
B7
VDD_CORE
F10
VDD_CORE
F13
VDD_CORE
F16
VDD_CORE
F19
VDD_CORE
F22
VDD_CORE
F25
VDD_CORE
J11
VDD_CORE
J13
VDD_CORE
J15
VDD_CORE
J17
VDD_CORE
J19
VDD_CORE
J21
VDD_CORE
J23
VDD_CORE
J9
VDD_CORE
K10
VDD_CORE
K12
VDD_CORE
K14
VDD_CORE
K16
VDD_CORE
K18
VDD_CORE
K20
VDD_CORE
K22
VDD_CORE
L11
VDD_CORE
L13
VDD_CORE
L15
VDD_CORE
L17
VDD_CORE
L19
VDD_CORE
L21
VDD_CORE
M12
VDD_CORE
M14
VDD_CORE
M16
VDD_CORE
M18
VDD_CORE
M20
VDD_CORE
M22
VDD_CORE
N11
VDD_CORE
N13
VDD_CORE
N15
VDD_CORE
N17
VDD_CORE
N19
VDD_CORE
N21
VDD_CORE
P12
VDD_CORE
P14
VDD_CORE
P16
VDD_CORE
P18
VDD_CORE
P20
VDD_CORE
P22
VDD_CORE
R11
VDD_CORE
R13
VDD_CORE
R15
VDD_CORE
R17
VDD_CORE
R19
VDD_CORE
R21
VDD_CORE
T12
VDD_CORE
T14
VDD_CORE
T16
VDD_CORE
T18
VDD_CORE
T20
VDD_CORE
T22
VDD_CORE
U11
VDD_CORE
U13
VDD_CORE
U15
VDD_CORE
U17
VDD_CORE
U19
VDD_CORE
U21
VDD_CORE
V12
VDD_CORE
V14
VDD_CORE
V16
VDD_CORE
V18
VDD_CORE
V20
VDD_CORE
V22
VDD_CORE
W11
VDD_CORE
W13
VDD_CORE
W15
VDD_CORE
W17
VDD_CORE
W19
VDD_CORE
W21
VDD_CORE
Y12
VDD_CORE
Y14
VDD_CORE
Y16
VDD_CORE
Y18
VDD_CORE
Y20
VDD_CORE
F7
VDD_CORE
AG22
AVDD
TP2
AE1
SI_VDD
TP1
AD2
SI_VSS
4
POWER
P0_K7_VCORE10 P0_K7_VCORE11 P0_K7_VCORE12 P0_K7_VCORE13 P0_K7_VCORE14 P0_K7_VCORE15 P0_K7_VCORE16 P0_K7_VCORE17 P0_K7_VCORE18 P0_K7_VCORE19 P0_K7_VCORE20 P0_K7_VCORE21 P0_K7_VCORE22 P0_K7_VCORE23
P1_K7_VCORE10 P1_K7_VCORE11 P1_K7_VCORE12 P1_K7_VCORE13 P1_K7_VCORE14 P1_K7_VCORE15 P1_K7_VCORE16 P1_K7_VCORE17 P1_K7_VCORE18 P1_K7_VCORE19 P1_K7_VCORE20 P1_K7_VCORE21 P1_K7_VCORE22 P1_K7_VCORE23 P1_K7_VCORE24
P0_K7_VCORE1 P0_K7_VCORE2 P0_K7_VCORE3 P0_K7_VCORE4 P0_K7_VCORE5 P0_K7_VCORE6 P0_K7_VCORE7 P0_K7_VCORE8 P0_K7_VCORE9
P1_K7_VCORE0 P1_K7_VCORE1 P1_K7_VCORE2 P1_K7_VCORE3 P1_K7_VCORE4 P1_K7_VCORE5 P1_K7_VCORE6 P1_K7_VCORE7 P1_K7_VCORE8 P1_K7_VCORE9
NC10 NC11 NC12 NC13 NC14 NC15 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC31 NC32
REF_5V
ROM_SDA ROM_SCK
DEBUG0 DEBUG1 DEBUG2
PX_CAL
PX_CAL#
SYSCLKREF
TEST#
DCSTOP#
AMD-AMD762
3
VCOREVCC2_5
G2 K2 N2 T2 W2 AB2 G6 K6 N6 T6 W6 AB6 L9 N9 R9 U9 W9 AA9 Y10 V10 T10 P10 M10
AE2 AH2 AK4 AK7 AK10 AK13 AK16 AK19 AF7 AF10 AF13 AF16 AF19 AC9 AC11 AC13 AC15 AC17 AC19 AE6 AB10 AB12 AB14 AB16 AB18
A29
NC0
A3
NC1
AH23
NC2
AA29
NC3
AA8
NC4
AC8
NC5
AD18
NC6
AD21
NC7
AC7
NC8
AD9
NC9
AE20 AE22 AJ1 AJ31 AK2 AK30 AL22 AL29 AL3 B2 B30 C1 C2 C31 E27 E5 G25 G7 L8 Y8
REF_5V
H29
SIPROM_DATA
AL21
SIPROM_CLK
AK21
TP4
AK20
TP6
AJ22
TP5
AF20
PX_CAL
AD3
PX_CAL-
AD4
NBCLK_VREF
AG20
TEST-
AE21 AD20
SUSST- <19>
3
D10 D13 D16 D19 D22 D25 D27
E28
G28
H10 H13 H16 H19 H22 H24
J10 J12 J14 J16 J18 J20 J22
K11 K13 K15 K17 K19 K21 K23 K24 K28 L10 L12 L14 L16 L18 L20 L22
M9 M11 M13 M15 M17 M19 M21 M23
N10 N12 N14 N16 N18 N20 N22 N24 N28
P11 P13 P15 P17 P19 P21 P23 R10 R12 R14 R16 R18 R20 R22
T11 T13 T15 T17 T19 T21 T23 T24 T28
D5 D7
E4
G4
H8
K4 K8 K9
N4 N8
P9
T4 T8 T9
U23G
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AMD-AMD762
AMD-762
GND
2
U10
VSS
U12
VSS
U14
VSS
U16
VSS
U18
VSS
U20
VSS
U22
VSS
V9
VSS
V11
VSS
V13
VSS
V15
VSS
V17
VSS
V19
VSS
V21
VSS
V23
VSS
W4
VSS
W8
VSS
W10
VSS
W12
VSS
W14
VSS
W16
VSS
W18
VSS
W20
VSS
W22
VSS
W24
VSS
W28
VSS
Y9
VSS
Y11
VSS
Y13
VSS
Y15
VSS
Y17
VSS
Y19
VSS
Y21
VSS
Y23
VSS
AA10
VSS
AA12
VSS
AA14
VSS
AA16
VSS
AA18
VSS
AA20
VSS
AA22
VSS
AB4
VSS
AB8
VSS
AB9
VSS
AB11
VSS
AB13
VSS
AB15
VSS
AB17
VSS
AB19
VSS
AB21
VSS
AB23
VSS
AB24
VSS
AB28
VSS
AC10
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC20
VSS
AC22
VSS
AD8
VSS
AD10
VSS
AD13
VSS
AD16
VSS
AD19
VSS
AD22
VSS
AD24
VSS
AE4
VSS
AE28
VSS
AG4
VSS
AG21
VSS
AG28
VSS
AH5
VSS
AH7
VSS
AH10
VSS
AH13
VSS
AH16
VSS
AH19
VSS
AH22
VSS
AH25
VSS
AH27
VSS
AJ20
VSS
2
AMD DOC SCH PX_CAL- 32 62 PX_CAL 23 47
R246 33
PX_CAL
R243 33
PX_CAL-
REF_5V
Set CLK_VREF to 1.15V
NBCLK_VREF
R235 470
SIPROM_DATA
R234 470
SIPROM_CLK
Title
{Title}
Size Document Number Rev
MS-6502 0A
Custom
Date: Sheet
R296
22
C496
1
VCORE
4.7u-0805
TEST-
1
C328
0.1u
5VSB
C497
4.7u-0805
VCC3
VCC2_5
12 39Wednesday, March 21, 2001
R409 10K
R407
5.1K
Reserved
of
R231 10K
R230 10K
5
VCC2_5 VCC2_5
DDR1
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
MDAT_SR0
D D
C C
B B
WEA-_SR<14,36>
VCC2_5
C394
C390
1000p
2 1
DDR_VREF
0.1u
C391
C396
1000p
2 1
0.1u
MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
WEA-_SR
C397
39p
C395
39p
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
DIMM-D184-BK
VDDQ2
DDR DIMM-184
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
3111826344250586674818993
Place 104p Cap. near the DIMM Place 104p Cap. near the DIMM
A A
5
VDDQ3
VDDQ4
VSS9
VSS10
104
VDDQ5
VDDQ6
VSS11
VSS12
112
100
128
VDDQ7
VDDQ8
VSS13
VSS14
116
136
VDDQ9
VSS15
124
4
143
156
VDDQ10
VSS16
132
139
4
164
VDDQ11
VDDQ12
VSS17
VSS18
145
172
VDDQ13
VSS19
152
1801582
VDDQ14
VDDQ15
CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2#(DU)
NC(RESET#)
VSS20
VSS21
160
176
VDDID
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
CK0(DU)
CK2(DU)
CKE0 CKE1 CAS# RAS#
184
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A11 A12 A13
BA0 BA1 BA2 SCL
SDA
SA0 SA1 SA2
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
NC5
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
VDDSPD
PCIRST-2<11,21,29,31,34>
157 158 71 163
5 14 25 36 56 67 78 86 47
167
48 43 41 130 37 32 125 29 122 27 141 118 115 103
59 52 113 92 91 181 182 183
44 45 49 51 134 135 142 144
16 17 137 138 76 75
173 10
21 111 65 154
97 107 119 129 149 159 169 177 140
CS-_SR0 CS-_SR1
DQS_SR0 DQS_SR1 DQS_SR2 DQS_SR3 DQS_SR4 DQS_SR5 DQS_SR6 DQS_SR7 DQS_SR8
MAA_SR0 MAA_SR1 MAA_SR2 MAA_SR3 MAA_SR4 MAA_SR5 MAA_SR6 MAA_SR7 MAA_SR8 MAA_SR9 MAA_SR10 MAA_SR11 MAA_SR12
MAA_SR13 MAA_SR14
SMBCLK SMBDATA
MECC_SR0 MECC_SR1 MECC_SR2 MECC_SR3 MECC_SR4 MECC_SR5 MECC_SR6 MECC_SR7
CLKOUT_SR1 CLKOUT-_SR1 CLKOUT_SR0 CLKOUT-_SR0 CLKOUT_SR2 CLKOUT-_SR2
CKEA_SR
CASA-_SR RASA-_SR
DM_SR0 DM_SR1 DM_SR2 DM_SR3 DM_SR4 DM_SR5 DM_SR6 DM_SR7 DM_SR8
R434 62
DDR_VREF
DDR_RESET-
R433
2.2K
CKEA_SR <14,36>
CASA-_SR <14,36> RASA-_SR <14,36>
WEB-_SR<14,36>
VCC2_5
C409
0.1u
2 1
C410
0.1u
2 1
C401
1000p
C404
1000p
3
DDR_RESET- <14>
MDAT_SR0 MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
WEB-_SR
C407
39p
C406
39p
3
DDR2
2 4 6
8 94 95 98 99 12 13 19 20
105 106 109 110
23 24 28 31
114 117 121 123
33 35 39 40
126 127 131 133
53 55 57 60
146 147 150 151
61 64 68 69
153 155 161 162
72 73 79 80
165 166 170 171
83 84 87 88
174 175 178 179
90 63
1
9
101 102
DIMM-D184-BK
738467085
VDD0
VDD1
VDD2
VDD3
VDD4
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
WP(NC) WE#
VREF
NC2 NC3 NC4
VSS0
VSS1
3111826344250586674818993
108
120
148
168223054627796
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
DDR DIMM-184
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
MAA_SR[0..14]<14,36>
MAB_SR[0..14]<14,36>
MECC_SR[0..7]<14,36>
DM_SR[0..8]<14,36>
104
112
VDDQ6
VDDQ7
VSS12
VSS13
100
128
116
136
VDDQ8
VDDQ9
VSS14
VSS15
124
2
143
156
VDDQ10
VSS16
132
139
2
164
172
VDDQ11
VDDQ12
VSS17
VSS18
145
152
1801582
VDDQ13
VDDQ14
VDDQ15
CK1#(CK0#)
NC(RESET#)
VSS19
VSS20
VSS21
160
176
VCC2_5VCC2_5
184
VDDID
VDDSPD
CS-_SR2
157
CS0#
CS-_SR3
158
CS1#
71
CS2#
163
CS3#
DQS_SR0
5
DQS0
DQS_SR1
14
DQS1
DQS_SR2
25
DQS2
DQS_SR3
36
DQS3
DQS_SR4
56
DQS4
DQS_SR5
67
DQS5
DQS_SR6
78
DQS6
DQS_SR7
86
DQS7
DQS_SR8
47
DQS8
167
FETEN
MAB_SR0
48
A0
MAB_SR1
43
A1
MAB_SR2
41
A2
MAB_SR3
130
A3
MAB_SR4
37
A4
MAB_SR5
32
A5
MAB_SR6
125
A6
MAB_SR7
29
A7
MAB_SR8
122
A8
MAB_SR9
27
A9
MAB_SR10
141
A10_AP
MAB_SR11
118
A11
MAB_SR12
115
A12
103
A13
MAB_SR13
59
BA0
MAB_SR14
52
BA1
113
BA2
SMBCLK
92
SCL
SMBDATA
91
SDA
181
SA0
182
SA1
183
SA2
MECC_SR0
44
CB0
MECC_SR1
45
CB1
MECC_SR2
49
CB2
MECC_SR3
51
CB3
MECC_SR4
134
CB4
MECC_SR5
135
CB5
MECC_SR6
142
CB6
MECC_SR7
144
CB7
CLKOUT_SR4
16
CK0(DU)
CLKOUT-_SR4
17
CK0#(DU) CK1(CK0)
CK2#(DU)
CLKOUT_SR3
137
CLKOUT-_SR3
138
CLKOUT_SR5
76
CK2(DU)
CLKOUT-_SR5
75
173
NC5
DDR_RESET-DDR_RESET-
10
CKEB_SR
21
CKE0
111
CKE1
CASB-_SR
65
CAS#
RASB-_SR
154
RAS#
DM_SR0
97
DM0
DM_SR1
107
DM1
DM_SR2
119
DM2
DM_SR3
129
DM3
DM_SR4
149
DM4
DM_SR5
159
DM5
DM_SR6
169
DM6
DM_SR7
177
DM7
DM_SR8
140
DM8
CLKOUT_SR[0..5]<36>
CLKOUT-_SR[0..5]<36>
CS-_SR[0..7]<14,36>
MDAT_SR[0..63]<14,36>
DQS_SR[0..8]<14,36>
Title
Size Document Number Rev
Custom
Date: Sheet of
VCC2_5
R366 270
SMBCLK <3,14,19,20,34> SMBDATA <3,14,19,20,34>
VCC2_5
CKEB_SR <14,36>
CASB-_SR <14,36> RASB-_SR <14,36>
MICRO-STAR
Rigster DDR DIMMs (1,2)
MS-6502
1
D15
1 2
GNx2-S-GN
1
13 39Wednesday, March 21, 2001
0A
5
VCC2_5 VCC2_5
DDR3
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
D D
C C
B B
VCC2_5
C416
0.1u
2 1
DDR_VREF
C412
0.1u
2 1
MDAT_SR0
2
MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
WEA-_SR
WEA-_SR<13,36>
C414
C420
1000p
39p
C419
C424
1000p
39p
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
DIMM-D184-BK
VSS0
VSS1
VSS2
3111826344250586674818993
VDDQ5
DDR DIMM-184
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
104
VDDQ6
VSS12
112
VDDQ7
VSS13
100
128
VDDQ8
VSS14
116
136
VDDQ9
VSS15
124
143
156
VDDQ10
VSS16
132
139
164
VDDQ11
VDDQ12
VSS17
VSS18
145
4
172
1801582
VDDQ13
VSS19
152
160
VDDQ14
VSS20
VDDID
VDDQ15
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
NC(RESET#)
CKE0 CKE1 CAS# RAS#
VSS21
176
3
DDR4
738467085
108
120
148
184
VDDSPD
CS-_SR4
157
CS-_SR5
158 71 163
DQS_SR0
5
DQS_SR1
14
DQS_SR2
25
DQS_SR3
36
DQS_SR4
56
DQS_SR5
67
DQS_SR6
78
DQS_SR7
86
DQS_SR8
47
167
MAA_SR0
48
A0
MAA_SR1
43
A1
MAA_SR2
41
A2
MAA_SR3
130
A3
MAA_SR4
37
A4
MAA_SR5
32
A5
MAA_SR6
125
A6
MAA_SR7
29
A7
MAA_SR8
122
A8
MAA_SR9
27
A9
MAA_SR10
141
MAA_SR11
118
A11
MAA_SR12
115
A12
103
A13
MAA_SR13
59
BA0
MAA_SR14
52
BA1
113
BA2
SMBCLK
92
SCL
SMBDATA
91
SDA
181
SA0
182
SA1
183
SA2
44
CB0
45
CB1
49
CB2
51
CB3
134
CB4
135
CB5
142
CB6
144
CB7
16 17 137 138 76 75
173
NC5
10
21 111 65 154
97
DM0
107
DM1
119
DM2
129
DM3
149
DM4
159
DM5
169
DM6
177
DM7
140
DM8
VCC2_5
MECC_SR0 MECC_SR1 MECC_SR2 MECC_SR3 MECC_SR4 MECC_SR5 MECC_SR6 MECC_SR7
CLKOUT_SRB2 CLKOUT-_SRB2
DDR_RESET- DDR_RESET-
CKEA_SR
CASA-_SR RASA-_SR
DM_SR0 DM_SR1 DM_SR2 DM_SR3 DM_SR4 DM_SR5 DM_SR6 DM_SR7 DM_SR8
DDR_VREF
CKEA_SR <13,36>
CASA-_SR <13,36> RASA-_SR <13,36>
VCC2_5
C544
0.1u
2 1
C426
0.1u
2 1
MDAT_SR0
2 4 6
8 94 95 98 99 12 13 19 20
105 106 109 110
23 24 28 31
114 117 121 123
33 35 39 40
126 127 131 133
53 55 57 60
146 147 150 151
61 64 68 69
153 155 161 162
72 73 79 80
165 166 170 171
83 84 87 88
174 175 178 179
90 63
1
9
101 102
DIMM-D184-BK
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
WP(NC) WE#
VREF
NC2 NC3 NC4
MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
WEB-_SR
WEB-_SR<13,36>
C543
C429
1000p
39p
C425
C428
1000p
39p
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
DDR DIMM-184
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
3111826344250586674818993
VDDQ0
VDDQ1
VSS6
VSS7
VDDQ2
VDDQ3
VSS8
VSS9
VDDQ4
VDDQ5
VSS10
VSS11
104
112
VDDQ6
VSS12
100
128
VDDQ7
VDDQ8
VSS13
VSS14
116
136
124
143
VDDQ9
VDDQ10
VSS15
VSS16
132
156
VDDQ11
VSS17
139
164
172
VDDQ12
VSS18
145
152
2
1801582
VDDQ13
VDDQ14
CK1#(CK0#)
NC(RESET#)
VSS19
VSS20
160
176
VDDQ15
VSS21
VCC2_5VCC2_5
VDDID
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
CK0(DU) CK0#(DU) CK1(CK0)
CK2(DU) CK2#(DU)
CKE0 CKE1 CAS# RAS#
184
A11 A12 A13
BA0 BA1 BA2 SCL
SDA
SA0 SA1 SA2
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
NC5
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
VDDSPD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
157 158 71 163
5 14 25 36 56 67 78 86 47
167
48 43 41 130 37 32 125 29 122 27 141 118 115 103
59 52 113 92 91 181 182 183
44 45 49 51 134 135 142 144
16 17 137 138 76 75
173 10
21 111 65 154
97 107 119 129 149 159 169 177 140
CS-_SR6 CS-_SR7
DQS_SR0 DQS_SR1 DQS_SR2 DQS_SR3 DQS_SR4 DQS_SR5 DQS_SR6 DQS_SR7 DQS_SR8
MAB_SR0 MAB_SR1 MAB_SR2 MAB_SR3 MAB_SR4 MAB_SR5 MAB_SR6 MAB_SR7 MAB_SR8 MAB_SR9 MAB_SR10 MAB_SR11 MAB_SR12
MAB_SR13 MAB_SR14
SMBCLK SMBDATA
MECC_SR0 MECC_SR1 MECC_SR2 MECC_SR3 MECC_SR4 MECC_SR5 MECC_SR6 MECC_SR7
CLKOUT_SRB5 CLKOUT-_SRB5
CKEB_SR
CASB-_SR RASB-_SR
DM_SR0 DM_SR1 DM_SR2 DM_SR3 DM_SR4 DM_SR5 DM_SR6 DM_SR7 DM_SR8
CLKOUT_SR[0..5]<13,36>
CLKOUT-_SR[0..5]<13,36>
CS-_SR[0..7]<13,36>
MDAT_SR[0..63]<13,36>
DQS_SR[0..8]<13,36>
MAA_SR[0..14]<13,36>
MAB_SR[0..14]<13,36>
MECC_SR[0..7]<13,36>
DM_SR[0..8]<13,36>
SMBCLK <3,13,19,20,34> SMBDATA <3,13,19,20,34>
VCC2_5
CLKOUT_SRB2<36>
CLKOUT-_SRB2<36>
CLKOUT_SRB5<36>
CLKOUT-_SRB5<36>
DDR_RESET- <13>
CKEB_SR <13,36>
CASB-_SR <13,36> RASB-_SR <13,36>
1
CLKOUT_SRB2
CLKOUT-_SRB2
CLKOUT_SRB5
CLKOUT-_SRB5
Place 104p Cap. near the DIMM Place 104p Cap. near the DIMM
A A
Title
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet of
MICRO-STAR
Rigster DDR DIMMs (3,4)
MS-6502
14 39Wednesday, March 21, 2001
1
0A
5
GAD[0..31]
GAD[0..31]<11>
SBA[0..7]
SBA[0..7]<11>
D D
C C
B B
VREF2.5<34>
VDDQ
TYPEDET-
VCC
R90
1K
R96
4.7K
A A
EC34 1000u/6.3V
B
5
SBA2 SBA0 SBA3 SBA1
SBA6 SBA4 SBA7 SBA5
PU_ADSTB0 PU_ADSTB1 PU_SBSTB
PD_ADSTB0-
PD_ADSTB1-
PD_SBSTB-
R165 1K
EC29
1000u/6.3V
C
E
WBF­RBF­PIPE­GREQ-
GDEVSEL­GTRDY­GIRDY­GFRAME-
GSERR­GPAR GPERR­GSTOP-
R229 8.2K R208 8.2K R170 8.2K
R239 8.2K
R196 8.2K
R159 8.2K
R164
1K
C178
0.1u
Q19
NPN-3904LT1-S-SOT23
RN35
8.2K
RN42
8.2K
RN44
8.2K
RN37
8.2K
RN41
8.2K
R163
348
R166
523
3
2
VDDQ
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
2
+
1
-
U16A NS-LM358MX-SOIC8
8 4
+12V
3VDUAL
R108 100
VR4
CSK-2-SOT23-150mA
3 1
R219 100
4
PIRQC-<16,17,18,19,29> GCLK1<3> GREQ-<11>
ST0<11> ST2<11> RBF-<11>
SBSTB<11>
R168
ADSTB1<11>
R204
GCBE2-<11>
GIRDY-<11>
GDEVSEL-<11>
GSERR-<11>
GCBE1-<11>
ADSTB0<11>
R232
Q40
DS
G
N-IPD20N03L-S-TO252
C223
0.1u
2 1
4
3VDUAL
VCC3
C224
0.1u
0
0
0
GREQ-
ST0 ST2 RBF-
SBA0
SBA2 PU_SBSTB
SBA4 SBA6
GAD31 GAD29
GAD27 GAD25
PU_ADSTB1 GAD23
GAD21 GAD19
GAD17 GCBE2-
GIRDY-
GDEVSEL-
GPERR-
GSERR­GCBE1-
GAD14 GAD12
GAD10 GAD8
PU_ADSTB0
GAD7
GAD5 GAD3
GAD1 VREF4X_OUT
+
EC25
1000u/6.3V
VCC3
3
VDDQ
AGP1
D1
VCC3_3_J
D2
VCC3_3_K
D3
VCC3_3_L
D4
VCC3_3_M
D5
VCC3_3_N
D6
VCC3_3_O
D7
VCC3_3_P
D8
VCC3_3_Q
D9
PRSNT#2
D10
PRSNT#1
AGP_OVRCNT# 5V_A 5V_B AGP_USB+ GND_Q INTB# AGPCLK_CONN REQ# VCC3_3_R ST0 ST2 RBF# GND_R RESV_L SBA0 VCC3_3_S SBA2 SB_STB GND_S SBA4 SBA6 RESV_M GND_T 3_3AUX_1 VCC3_3_T GAD31 GAD29 VCC3_3_U GAD27 GAD25 GND_U AD_STB1 GAD23 VDDQ_F GAD21 GAD19 GND_V GAD17 C/BE#2 VDDQ_G IRDY# 3_3AUX_2 GND_W RESV_N VCC3_3_V DEVSEL# VDDQ_H PERR# GND_X SERR# C/BE#1 VDDQ_I GAD14 GAD12 GND_Y GAD10 GAD8 VDDQ_J AD_STB0 GAD7 GND_Z GAD5 GAD3 VDDQ_K GAD1 VREFCG
RESV_O RESV_P GND_AA GND_BB GND_CC GND_DD GND_EE GND_FF GND_GG GND_HH GND_II GND_JJ GND_KK GND_LL
CARD-D180
3
KEY
VCC
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66
F1 F2 F3 F4 F5 F6 F7 F8
F9 F10 F11 F12 F13 F14
VCC3_3_A
VCC3_3_B
VCC_12V_A
TYPEDET#
AGP_USB-
VCC3_3_E
VCC3_3_F
VCC3_3_G
VCC3_3_H
AD_STB1#
AD_STB0#
KEY
VCC_12V_B VCC_12V_C VCC_12V_D VCC_12V_E VCC_12V_F VCC_12V_G VCC_12V_H
VCC_12V_I VCC_12V_J VCC_12V_K VCC_12V_L
VCC_12V_M
GND_A
GND_B GND_C GND_D GND_E
GND_F RESV_A RESV_B
RESV_C
GND_G
INTA#
RST#
GNT#
RESV_D
PIPE#
GND_H
WBF#
SBA1
SBA3
SB_STB#
GND_I
SBA5 SBA7
RESV_E
GND_J RESV_F
GAD30
GAD28
GAD26
GAD24
GND_K
C/BE#3
VDDQ_A
GAD22
GAD20
GND_L
GAD18
GAD16 VDDQ_B FRAME# RESV_G
GND_M
RESV_H
VCC3_3_I
TRDY#
STOP#
PME#
GND_N
GAD15
VDDQ_C
GAD13
GAD11
GND_O
GAD9
C/BE#0
VDDQ_D
GAD6
GND_P
GAD4 GAD2
VDDQ_E
GAD0
VREFGC
RESV_I
RESV_J
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
ST1
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50
PAR
A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66
+12V E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14
+12V
TYPEDET-
GGNT-
ST1
PIPE-
WBF­SBA1
SBA3 PD_SBSTB-
SBA5 SBA7
GAD30 GAD28
GAD26 GAD24
PD_ADSTB1­GCBE3-
GAD22 GAD20
GAD18 GAD16
GFRAME-
GTRDY­GSTOP-
GPAR GAD15
GAD13 GAD11
GAD9 GCBE0-
PD_ADSTB0­GAD6
GAD4 GAD2
GAD0 AGP_VREF4X_IN
C299
0.1u
+12V
+
2
EC37 470u
2
R161
R200 0
R233
TYPEDET- <37>
PIRQB- <16,17,18,19,31> PCIRST-1 <16,17,18,21> GGNT- <11>
ST1 <11>
PIPE- <11>
WBF- <11>
0
GCBE3- <11>
GFRAME- <11>
GTRDY- <11> GSTOP- <11> PME- <16,17,18,19,31>
GPAR <11>
GCBE0- <11>
0
Near the AGP connector
AGP_VREF4X_IN <11>
1
AGP Pro Connector
AGP Pro Imax
VCC3 7.6A VCC12 9.2A
VCC3
+
EC18 1000u/6.3V
SBSTB- <11>
+12V
J4
1
3
GND
12V
2
VREF4X_OUT
TYPEDET#
Low
High
MICRO-STAR
MS-6502
4
GND
12V
D2x2
VDDQ
C280 560p
R255
R258
75
1K
R263
R260
1K
75
C292 560p
Place close to N/B
VDDQ
1.5V
3.3V
15 39Thursday, March 22, 2001
1
ADSTB1- <11>
ADSTB0- <11>
Title
Size Document Number Rev
Custom
Date: Sheet of
AGP PRO CONNECTOR
0A
5
VCC3
D D
PIRQB-<15,17,18,19,31> PIRQD-<17,18,19>
PCLK1<3>
REQ1-<11,18>
C C
IRDY-<11,17,18,19,29,31>
DEVSEL-1,17,18,19,29,31>
PLOCK-<17,18>
PERR-<17,18,31>
SERR-<11,17,18,19,31>
ACK64-<11>
B B
A A
-12V
TCK
TCK<17,18>
PIRQB­PIRQD­PRSNT-11
PRSNT-12
AD31 AD29
AD27 AD25 AD28
C_BE-3 AD23
AD21 AD19
AD17 C_BE-2
IRDY-
DEVSEL-
PLOCK­PERR-
SERR-
C_BE-1 AD14
AD12 AD10
AD8 AD7
AD5 AD3
AD1
ACK64-
C_BE-6 C_BE-4
AD63 AD61
AD59 AD57
AD55 AD53
AD51 AD49
AD47 AD45
AD43 AD41
AD39 AD37
AD35 AD33
5
PCI4
B1
-12V
B2
TCK
B3
GND
B4
TDO
B5
+5V
B6
+5V
B7
INTB#
B8
INTD#
B9
PRSNT#1
B10
RESV_E
B11
PRSNT#2
B12
GND
B13
GND
B14
RESV_F
B15
GND
B16
CLK
B17
GND_U
B18
REQ#
B19
+5V_I/O
B20
AD31
B21
AD29
B22
GND
B23
AD27
B24
AD25
B25
+3.3V
B26
C/BE#3
B27
AD23
B28
GND
B29
AD21
B30
AD19
B31
+3.3V
B32
AD17
B33
C/BE#2
B34
GND
B35
IRDY#
B36
+3.3V
B37
DEVSEL#
B38
GND
B39
LOCK#
B40
PERR#
B41
+3.3V
B42
SERR#
B43
+3.3V
B44
C/BE#1
B45
AD14
B46
GND
B47
AD12
B48
AD10
B49
M66EN
B52
AD8
B53
AD7
B54
+3.3V
B55
AD5
B56
AD3
B57
GND_CC
B58
AD1
B59
+5V_I/O
B60
ACK64#
B61
+5V
B62
+5V
B63
RESV_G
B64
GND
B65
C/BE#6
B66
C/BE#4
B67
GND
B68
AD63
B69
AD61
B70
+5V_I/O
B71
AD59
B72
AD57
B73
GND
B74
AD55
B75
AD53
B76
GND
B77
AD51
B78
AD49
B79
+5V_I/O
B80
AD47
B81
AD45
B82
GND
B83
AD43
B84
AD41
B85
GND
B86
AD39
B87
AD37
B88
+5V_I/O
B89
AD35
B90
AD33
B91
GND
B92
RESV_H
B93
RESV_I
B94
GND
KEY
KEY
CARD-D184-S3
TRST#
INTA# INTC#
RESV_A
+5V_I/O
RESV_B
3_3VAUX
+5V_I/O
PME#
IDSEL
FRAME#
TRDY# GND_E STOP#
SDONE
C/BE#0
GND_J
+5V_I/O
REQ64#
C/BE#7 C/BE#5
+5V_I/O
PAR64
+5V_I/O
+5V_I/O
RESV_C
RESV_D
+12V
RST#
GNT#
AD30 +3.3V AD28 AD26
AD24
+3.3V AD22 AD20
AD18 AD16 +3.3V
+3.3V
SBO#
AD15 +3.3V AD13 AD11
+3.3V
AD62
AD60 AD58
AD56 AD54
AD52 AD50
AD48 AD46
AD44 AD42
AD40 AD38
AD36 AD34
AD32
TMS
TDI +5V
+5V
GND GND
GND
GND
GND
GND
GND PAR
GND
AD9
AD6 AD4
AD2 AD0
+5V +5V
GND
GND
GND
GND
GND
GND
GND
GND
4
VCC3
+12VVCC
VCC VCC3
PIRQA­PIRQC-
PCIRST-1
GNT1-
PME­AD30
AD28 AD26
AD24
R130 100
AD22 AD20
AD18 AD16
FRAME-
TRDY-
STOP-
SDONE1 SBO1
PAR AD15
AD13 AD11
AD9
C_BE-0
AD6
AD2 AD0
REQ64-
C_BE-7 C_BE-5
PAR64 AD62
AD60 AD58
AD56 AD54
AD52 AD50
AD48 AD46
AD44 AD42
AD40 AD38
AD36 AD34
AD32
4
TRST-
TMS TDI
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94
PCI Connector 1,2
TRST- <17,18>
TMS <17,18> TDI <17,18>
PIRQA- <17,18,19> PIRQC- <15,17,18,19,29>
3VDUAL
PCIRST-1 <15,17,18,21>
GNT1- <11>
PME- <15,17,18,19,31>
AD20
IDSEL
FRAME- <11,17,18,19,29,31>
TRDY- <11,17,18,19,29,31>
STOP- <11,17,18,19,29,31>
PAR <11,17,18,19,29,31,37>
REQ64- <11>
SBO1 SDONE1 SBO2 SDONE2
PAR64 <11>
PRSNT-11
PRSNT-12
PRSNT-21
PRSNT-22
C96
0.1u
C103
0.1u
C97
0.1u
C104
0.1u
1 2 3 4 5 6 7 8
3
VCC3
-12V
TCK
TCK<17,18>
PIRQC­PIRQA­PRSNT-21
PRSNT-22
PCLK2<3>
REQ2-<11,18>
AD31 AD29
AD27 AD25
C_BE-3 AD23
AD21 AD19
AD17 C_BE-2
IRDY-
DEVSEL-
PLOCK­PERR-
SERR-
C_BE-1 AD14
AD12 AD10
AD8 AD7AD4
AD5 AD3
VCC3
RN40
8.2K
AD1
ACK64-
C_BE-6 C_BE-4
AD63 AD61
AD59 AD57
AD55 AD53
AD51 AD49
AD47 AD45
AD43 AD41
AD39 AD37
AD35 AD33
3
PCI5
B1
-12V
B2
TCK
B3
GND
B4
TDO
B5
+5V
B6
+5V
B7
INTB#
B8
INTD#
B9
PRSNT#1
B10
RESV_E
B11
PRSNT#2
B12
GND
B13
GND
B14
RESV_F
B15
GND
B16
CLK
B17
GND_U
B18
REQ#
B19
+5V_I/O
B20
AD31
B21
AD29
B22
GND
B23
AD27
B24
AD25
B25
+3.3V
B26
C/BE#3
B27
AD23
B28
GND
B29
AD21
B30
AD19
B31
+3.3V
B32
AD17
B33
C/BE#2
B34
GND
B35
IRDY#
B36
+3.3V
B37
DEVSEL#
B38
GND
B39
LOCK#
B40
PERR#
B41
+3.3V
B42
SERR#
B43
+3.3V
B44
C/BE#1
B45
AD14
B46
GND
B47
AD12
B48
AD10
B49
M66EN
B52
AD8
B53
AD7
B54
+3.3V
B55
AD5
B56
AD3
B57
GND_CC
B58
AD1
B59
+5V_I/O
B60
ACK64#
B61
+5V
B62
+5V
B63
RESV_G
B64
GND
B65
C/BE#6
B66
C/BE#4
B67
GND
B68
AD63
B69
AD61
B70
+5V_I/O
B71
AD59
B72
AD57
B73
GND
B74
AD55
B75
AD53
B76
GND
B77
AD51
B78
AD49
B79
+5V_I/O
B80
AD47
B81
AD45
B82
GND
B83
AD43
B84
AD41
B85
GND
B86
AD39
B87
AD37
B88
+5V_I/O
B89
AD35
B90
AD33
B91
GND
B92
RESV_H
B93
RESV_I
B94
GND
KEY
KEY
CARD-D184-S3
TRST#
INTA# INTC#
RESV_A
+5V_I/O
RESV_B
3_3VAUX
+5V_I/O
PME#
IDSEL
FRAME#
TRDY#
GND_E
STOP#
SDONE
C/BE#0
GND_J
+5V_I/O
REQ64#
C/BE#7 C/BE#5
+5V_I/O
PAR64
+5V_I/O
+5V_I/O
RESV_C
RESV_D
+12V
RST#
GNT#
AD30 +3.3V AD28 AD26
AD24
+3.3V AD22 AD20
AD18 AD16 +3.3V
+3.3V
SBO#
AD15 +3.3V AD13 AD11
+3.3V
AD62
AD60 AD58
AD56 AD54
AD52 AD50
AD48 AD46
AD44 AD42
AD40 AD38
AD36 AD34
AD32
TMS
TDI +5V
+5V
GND GND
GND
GND
GND
GND
GND PAR
GND AD9
AD6 AD4
AD2 AD0
+5V +5V
GND
GND
GND
GND
GND
GND
GND
GND
2
+12VVCC
VCC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94
TRST-
TMS TDI
PIRQB­PIRQD-
3VDUAL
PCIRST-1
GNT2-
GNT2- <11>
PME­AD30
AD26
AD24
R137 100
AD21
AD22 AD20
AD18 AD16
FRAME-
TRDY-
STOP-
SDONE2 SBO2
PAR AD15
AD13 AD11
AD9
C_BE-0
AD6 AD4
AD2 AD0
REQ64-
C_BE-7 C_BE-5
PAR64 AD62
AD60 AD58
AD56 AD54
AD52 AD50
AD48 AD46
AD44 AD42
AD40 AD38
AD36 AD34
AD32
2
IDSEL
PAR64 <11>
Title
Size Document Number Rev
Custom
Date: Sheet
1
AD[0..63]<11,17,18,19,29,31,34,37>
C_BE-[0..7]
C_BE-[0..7]<11,17,18,19,29,31,37>
REQ64­ACK64­PAR64
C_BE-4 C_BE-5 C_BE-6 C_BE-7
1 2 3 4 6 7 8 9510
AD32
1
AD33
2
AD34
3
AD35
4
AD36
6
AD37
7
AD38
8
AD39
9510
AD40
1
AD41
2
AD42
3
AD43
4
AD44
6
AD45
7
AD46
8
AD47
9510
AD48
1
AD49
2
AD50
3
AD51
4
AD52
6
AD53
7
AD54
8
AD55
9510
AD56
1
AD57
2
AD58
3
AD59
4
AD60
6
AD61
7
AD62
8
AD63
9510
MICRO-STAR
PCI CONNECTOR 1,2
MS-6502
1
AD[0..63]
RN47
1 2 3 4 6 7 8 9510
8.2K
RN62
1 2 3 4 6 7 8 9510
8.2K
RN60
1 2 3 4 6 7 8 9510
8.2K
RN57
1 2 3 4 6 7 8 9510
8.2K
RN54
1 2 3 4 6 7 8 9510
8.2K
16 39Wednesday, March 21, 2001
VCC3
VCC3
VCC3
VCC3
VCC3
0A
of
5
AD[0..31]
AD[0..31]<11,16,18,19,29,31,34,37>
C_BE-[0..3]<11,16,18,19,29,31,37>
C_BE-[0..3]
4
3
2
1
PCI Connector 3,4
TCK
PIRQB­PRSNT-31
PRSNT-32
AD31 AD29
AD27 AD25
C_BE-3 AD23
AD21 AD19
AD17 C_BE-2
IRDY-
DEVSEL-
PLOCK­PERR-
SERR-
C_BE-1 AD14
AD12 AD10
AD8 AD7
AD5 AD3
AD1
ACK64-3
VCC3
VCC3
VCC
-12V
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
PCI1
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSVD2 PRSNT2# GND GND RSVD5 GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND
AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V
PCI-D120-WH-SN
RSVD1
RSVD3
RSVD4
RSVD6
IDSEL#
FRAME#
TRDY#
STOP#
SDONE
C/BE0#
REQ64#
4
TRST#
+12V
INTA# INTC#
GND GND
RST#
GNT#
GND
AD30
+3.3V
AD28 AD26 GND AD24
+3.3V
AD22 AD20 GND AD18 AD16
+3.3V
GND
GND
+3.3V
SBO#
GND
AD15
+3.3V
AD13 AD11 GND
+3.3V
GND
VCC3
+12V
VCC
A1 A2 A3
TMS
A4
TDI
A5
+5V
A6 A7 A8
+5V
A9 A10
+5V
A11 A12 A13 A14 A15 A16
+5V
A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43
PAR
A44 A45 A46 A47 A48 A49
AD9
A52 A53 A54
AD6
A55
AD4
A56 A57
AD2
A58
AD0
A59
+5V
A60 A61
+5V
A62
+5V
TRST-
TMS TDI
PIRQC­PIRQA-PIRQD-
PCIRST-1
GNT3-
PME­AD30
AD28 AD26
AD24
R134 100
AD22 AD20
AD18 AD16
FRAME-
TRDY-
STOP-
SDONE3 SBO3
PAR AD15
AD13 AD11
AD9
C_BE-0
AD6 AD4
AD2 AD0
REQ64-3
TRST- <16,18>
TMS <16,18> TDI <16,18>
PIRQC- <15,16,18,19,29> PIRQA- <16,18,19>
3VDUAL
PCIRST-1 <15,16,18,21>
GNT3- <11>
PME- <15,16,18,19,31>
AD22
IDSEL
FRAME- <11,16,18,19,29,31>
TRDY- <11,16,18,19,29,31>
STOP- <11,16,18,19,29,31>
PAR <11,16,18,19,29,31,37>
PRSNT-31
PRSNT-32
PRSNT-41
PRSNT-42
3
C98
0.1u
C105
0.1u
C99
0.1u
C108
0.1u
PCLK4<3>
REQ4-<11,18>
SBO3 SDONE3 SBO4 SDONE4
TCK<16,18>
TCK
PIRQA­PIRQC­PRSNT-41
PRSNT-42
AD31 AD29
AD27 AD25
C_BE-3 AD23
AD21 AD19
AD17 C_BE-2
IRDY-
DEVSEL-
PLOCK­PERR-
SERR-
C_BE-1 AD14
AD12 AD10
AD8 AD7
AD5 AD3
AD1
ACK64-4
-12V
VCC3
VCC
RN39
1 2 3 4 5 6 7 8
8.2K
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
2
PCI2
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSVD2 PRSNT2# GND GND RSVD5 GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND
AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V
PCI-D120-WH-SN
VCC3
VCC3
+12V
VCC
A1
TRST#
A2
+12V
A3
TMS
A4
TDI
A5
+5V
A6
INTA#
A7
INTC#
A8
+5V
A9
RSVD1
A10
+5V
A11
RSVD3
A12
GND
A13
GND
A14
RSVD4
A15
RST#
A16
+5V
A17
GNT#
A18
GND
A19
RSVD6
A20
AD30
A21
+3.3V
A22
AD28
A23
AD26
A24
GND
A25
AD24
A26
IDSEL#
A27
+3.3V
A28
AD22
A29
AD20
A30
GND
A31
AD18
A32
AD16
A33
+3.3V
A34
FRAME#
A35
GND
A36
TRDY#
A37
GND
A38
STOP#
A39
+3.3V
A40
SDONE
A41
SBO#
A42
GND
A43
PAR
A44
AD15
A45
+3.3V
A46
AD13
A47
AD11
A48
GND
A49
AD9
A52
C/BE0#
A53
+3.3V
A54
AD6
A55
AD4
A56
GND
A57
AD2
A58
AD0
A59
+5V
A60
REQ64#
A61
+5V
A62
+5V
Title
Size Document Number Rev
Custom
Date: Sheet of
TRST-
TMS TDI
PIRQD­PIRQB-
3VDUAL
PCIRST-1
GNT4-
GNT4- <11>
PME­AD30
AD28 AD26
AD24
AD23
R135 100
AD22 AD20
AD18 AD16
FRAME-
TRDY-
STOP-
SDONE4 SBO4
PAR AD15
AD13 AD11
AD9
C_BE-0
AD6 AD4
AD2 AD0
REQ64-4
IDSEL
MICRO-STAR
PCI CONNECTOR 3,4
MS-6502
1
17 39Wednesday, March 21, 2001
0A
D D
TCK<16,18>
PIRQD-<16,18,19> PIRQB-<15,16,18,19,31>
PCLK3<3>
REQ3-<11,18>
C C
IRDY-<11,16,18,19,29,31>
DEVSEL-<11,16,18,19,29,31>
PLOCK-<16,18>
PERR-<16,18,31>
SERR-<11,16,18,19,31>
B B
ACK64-3 ACK64-4 REQ64-3 REQ64-4
A A
1 2 3 4 5 6 7 8
5
RN43
8.2K
5
AD[0..31]
AD[0..31]<11,16,17,19,29,31,34,37>
C_BE-[0..3]
C_BE-[0..3]<11,16,17,19,29,31,37>
D D
VCC3
VCC
-12V
TCK
TCK<16,17>
PIRQB-
PIRQB-<15,16,17,19,31>
PIRQD-
PIRQD-<16,17,19>
PRSNT-51
C C
B B
PRSNT-52
PCLK5
PCLK5<3>
REQ5-
REQ5-<11>
AD31 AD29
AD27 AD25
C_BE-3 AD23
AD21 AD19
AD17 C_BE-2
IRDY-
IRDY-<11,16,17,19,29,31>
DEVSEL-
DEVSEL-<11,16,17,19,29,31>
PLOCK-
PLOCK-<16,17>
PERR-
PERR-<16,17,31>
SERR-
SERR-<11,16,17,19,31>
C_BE-1 AD14
AD12 AD10
AD8 AD7
AD5 AD3
AD1
ACK64-5
PCI3
B1
-12V
B2
TCK
B3
GND
B4
TDO
B5
+5V
B6
+5V
B7
INTB#
B8
INTD#
B9
PRSNT1#
B10
RSVD2
B11
PRSNT2#
B12
GND
B13
GND
B14
RSVD5
B15
GND
B16
CLK
B17
GND
B18
REQ#
B19
+5V
B20
AD31
B21
AD29
B22
GND
B23
AD27
B24
AD25
B25
+3.3V
B26
C/BE3#
B27
AD23
B28
GND
B29
AD21
B30
AD19
B31
+3.3V
B32
AD17
B33
C/BE2#
B34
GND
B35
IRDY#
B36
+3.3V
B37
DEVSEL#
B38
GND
B39
LOCK#
B40
PERR#
B41
+3.3V
B42
SERR#
B43
+3.3V
B44
C/BE1#
B45
AD14
B46
GND
B47
AD12
B48
AD10
B49
GND
B52
AD8
B53
AD7
B54
+3.3V
B55
AD5
B56
AD3
B57
GND
B58
AD1
B59
+5V
B60
ACK64#
B61
+5V
B62
+5V
TRST#
+12V
INTA# INTC#
RSVD1
RSVD3
RSVD4
RST#
GNT#
RSVD6
AD30
+3.3V
AD28 AD26
AD24
IDSEL#
+3.3V
AD22 AD20
AD18 AD16
+3.3V
FRAME#
TRDY#
STOP#
+3.3V
SDONE
SBO#
AD15
+3.3V
AD13 AD11
C/BE0#
+3.3V
REQ64#
4
PCI Connector 5
VCC3
+12V
VCC
A1 A2 A3
TMS
A4
TDI
A5
+5V
A6 A7 A8
+5V
A9 A10
+5V
A11 A12
GND
A13
GND
A14 A15 A16
+5V
A17 A18
GND
A19 A20 A21 A22 A23 A24
GND
A25 A26 A27 A28 A29 A30
GND
A31 A32 A33 A34 A35
GND
A36 A37
GND
A38 A39 A40 A41 A42
GND
A43
PAR
A44 A45 A46 A47 A48
GND
A49
AD9
A52 A53 A54
AD6
A55
AD4
A56
GND
A57
AD2
A58
AD0
A59
+5V
A60 A61
+5V
A62
+5V
TRST-
TMS TDI
PIRQA­PIRQC-
PCIRST-1
GNT5-
PME­AD30
AD28 AD26
AD24
R123 100
AD22 AD20
AD18 AD16
FRAME-
TRDY-
STOP-
SDONE5 SBO5
PAR AD15
AD13 AD11
AD9
C_BE-0
AD6 AD4
AD2 AD0
REQ64-5
TRST- <16,17>
TMS <16,17> TDI <16,17>
PIRQA- <16,17,19> PIRQC- <15,16,17,19,29>
3VDUAL
PCIRST-1 <15,16,17,21>
GNT5- <11>
PME- <15,16,17,19,31>
AD24
IDSEL
-
FRAME- <11,16,17,19,29,31>
TRDY- <11,16,17,19,29,31>
STOP- <11,16,17,19,29,31>
PAR <11,16,17,19,29,31,37>
1000u/6.3V
EC32
3
-12V+12V
10u
+
EC15
3VDUAL
C115
0.1u
-
VCC
+
C228
0.1u
C231
0.1u
C85
0.1u
C116
0.1u
-
C229
0.1u
C117
0.1u
-
C227
0.1u
C80
0.1u
2
TDI TMS TCK TRST-
SDONE5 SBO5 ACK64-5
REQ64-5 PIRQA­PIRQD­PIRQC­PIRQB-
FRAME­IRDY­TRDY­DEVSEL­STOP­PLOCK­SERR­PERR-
REQ0-
REQ0-<11,31>
REQ1-
REQ1-<11,16>
REQ2-
REQ2-<11,16>
REQ3-
REQ3-<11,17>
REQ4-
REQ4-<11,17>
REQ5-
REQ5-<11>
REQ6-
REQ6-<11,29>
VCC3
10u
+
+
EC21
C222
0.1u
C193
0.1u
C92
0.1u 1000u/6.3V
EC23
RN28
1 2 3 4 5 6 7 8
8.2K
1 2 3 4 6 7 8 9510
1 2 3 4 6 7 8 9510
1 2 3 4 6 7 8 9510
C190
0.1u
RN29
1 2 3 4 6 7 8 9510
8.2K
RN38
1 2 3 4 6 7 8 9510
8.2K
RN45
1 2 3 4 6 7 8 9510
8.2K
1
VCC3
VCC3
VCC3
VCC3
PCI-D120-WH-SN
A A
5
4
3
PRSNT-51
PRSNT-52
C102
0.1u
C109
0.1u
Title
Size Document Number Rev
Custom
2
Date: Sheet of
MICRO-STAR
PCI CONNECTOR 5,6
MS-6502
1
18 39Thursday, March 22, 2001
0A
8
7
6
5
4
3
2
1
PD_D[0..15]
PD_D[0..15]<21>
D D
-DDACK_A<21> DDREQ_A<21>
HDRDY_A<21>
AD[0..31]<11,16,17,18,29,31,34,37>
C C
C_BE-[0..3]<11,16,17,18,29,31,37>
B B
Y4 32K-12.5pf-CSA-309-D
1 2
C343 10p
A A
Trece width of RTCX1 and RTCX2 are 12 mils As short as possible
8
PD_D0 BITCLK PD_D1 PD_D2 SDIN1 PD_D3 PD_D4 PD_D5 PD_D6 PD_D7 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15
PD_A0 SD_A0
PD_A0<21>
PD_A1 SD_A1
PD_A1<21>
PD_A2 SD_A2
PD_A2<21>
-PDCS_1 -SDCS_1
-PDCS_1<21>
-PDCS_3 -SDCS_3
-PDCS_3<21>
-DDACK_A -DDACK_B DDREQ_A DDREQ_B
-DIOR_A -DIOR_B
-DIOR_A<21>
-DIOW_A -DIOW_B
-DIOW_A<21> HDRDY_A HDRDY_B
AD[0..31]
AD0 A 20M­AD1 AD2 FERR­AD3 IGNNE­AD4 CPUINIT­AD5 INTR AD6 NMI AD7 SLP­AD8 SMI­AD9 STPCLK­AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 PWROK AD22 SMBCLK AD23 SMBDATA AD24 AD25 AD26 SUSST­AD27 AD28 AD29 EXTSMI­AD30 RI­AD31 PME-_SB
C_BE-0 PWRBT­C_BE-1 RSMRST­C_BE-2 PD_80P C_BE-3 WSC-
FRAME-
FRAME-<11,16,17,18,29,31>
IRDY-
IRDY-<11,16,17,18,29,31>
TRDY- SUSB-
TRDY-<11,16,17,18,29,31>
STOP- SUSC-
STOP-<11,16,17,18,29,31>
DEVSEL-
DEVSEL-<11,16,17,18,29,31>
SERR-
SERR-<11,16,17,18,31>
PAR
PAR<11,16,17,18,29,31,37>
AD18 SBREQ-
SBREQ-<11,20>
SBGNT-
SBGNT-<11,20>
PCIRST-
PCIRST-<21>
PIRQA-
PIRQA-<16,17,18>
PIRQB-
PIRQB-<15,16,17,18,31>
PIRQC-
PIRQC-<15,16,17,18,29>
PIRQD-
PIRQD-<16,17,18>
SBCLK
SBCLK<3>
3VDUAL
C344
VBAT
10p
VCC3
U22A
P16
PDD0
P18
PDD1
P20
PDD2
R17
PDD3
R19
PDD4
T16
PDD5
T18
PDD6
T20
PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
PDA0 PDA1 PDA2 PDCS1 PDCS3 PDDACK PDDREQ PDIOR PDIOW PDRDY
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C_BE0 C_BE1 C_BE2 C_BE3
FRAME IRDY TRDY STOP DEVSEL SERR PAR IDSEL REQ GNT PCIRST
PINTA PINTB PINTC PINTD
PCICLK
RTCX1
RTCX2
VCCSUS VCCSUS
VBAT
VCC VCC VCC VCC VCC VCC VCC VCC VCC
VIA-VT82C686B-VB
*:VSUS
*PME/GPI5/THRM
*LID/APICREQ/GP
*SUSA/APICACK/G *SUSB/APICCS/GP
CHAS/GPIOC/GPIO
FAN2/GPIOB/GPIO
6
T19
T17 R20 R18 R16
P19
P17 N20
M17 M19 M18
L20 M16 M20 N19 N17 N18 N16
L17
L16
K20
K19
K18
K17
K16
J20
J18
J17
J16 H20 H19 H18 H17 H16
F16
E20
E19
E18
E17 D20 D19 D18
B20
A20
A19
B19
A18
B18 C18
A17
J19 G20
F17 C19
F18
F19
F20 G17 G16 G18 G19 C20
L18
L19
B16
A16 D17 C17
B17
E16
Y5
W5
R9
R10
Y6
H15
J15
K15 M15 N15
R7
R8 R11 R14
7
SDD0/BITCLK
*SDD1/SDIN
*SDD2/SDIN2
SDD3/SYNC
SDD4/SDOUT
SDD5/-ACRST
SDD6/JBY SDD7/JBX SDD8/JAY
SDD9/JAX SDD10/JAB2 SDD11/JAB1 SDD12/JBB2 SDD13/JBB1
SDD14/MSO
SDD15/MSI
SDA0 SDA1
SDA2 SDCS1 SDCS3
SDDACK
SDDREQ
SDIOR SDIOW SDRDY
A20M
CPURST
FERR
IGNNE
INTR
SLP/GPO7
STPCLK
CPUSTP/GPO4
PCISTP/GPO5
CLKRUN
SPKR
GPIOA/GPIO8
GPIOD
*PWRGD
*SMBCLK
*SMBDATA
*GPO0
*SUSST1/GPO6
*SUSCLK
*EXTSMI
*RING/GPI7
*BATLOW/GPI2
*PWRBTN
*RSMRST
*GPI1/IRQ8
*SMBALT/GPI6
*SUSC
GND GND GND GND GND
IN12
IN2A
IN2B
TSEN1
VREF
TSEN2
FAN1
VCCHWM
GNDHWM
W18
SDIN0
V17 Y17 V16 Y16 U15
JBY
W15
JBX
U14
JAY
Y15
JAX
V15
JAB2
T15
JAB1
W16
JBB2
U16
JBB1
W17
TXD
Y18
RXD
Y19
U19 V18 U20 U17 U18 V19 Y20 W19 W20 V20
Y7
CPURST-
V8 V7 Y8 T6
INIT
W8 U7
NMI
T7 U6
SMI
W7
CPUSTOP-
Y12
PCISTP-
V12
PCKRUN-
W12
SPKR
V5
FAN_ON PCISTP-
T14 U8
W6 U9 T9
SUSLED
T8 V10
PAPICD1-
T10
Y10 V11 T11
SD_80P
U11 Y11 V6 W11 U10
SMBALT-
W10
PAPICD0-
V9 W9 Y9
F15 G15 L15 P15 R15
Y14
W14
IN5
U13
V13
V14
W13
T13
Y13
CPUFAN1
T12
CPUFAN2
U12
R12
R13
C352
0.1u
R311
5
BITCLK <27> SDIN0 <27>
SD_A0 <21> SD_A1 <21> SD_A2 <21>
-SDCS_1 <21>
-SDCS_3 <21>
-DDACK_B <21> DDREQ_B <21>
-DIOR_B <21>
-DIOW_B <21> HDRDY_B <21>
A20M- <4,6> CPURST- <4,6> FERR- <4> IGNNE- <4,6> CPUINIT- <4,6> INTR <4,6> NMI <4,6> SLP- <20> SMI- <4,6> STPCLK- <4,6>
CPUSTOP- <3> PCISTP- <3>
SPKR <25> FAN_ON <24>
ROMLOCK <24>
PWROK <25> SMBCLK <3,13,14,20,34> SMBDATA <3,13,14,20,34>
SUSLED <25> SUSST- <12>
PAPICD1- <34>
EXTSMI- <25> RI- <22>
SD_80P <21> PWRBT- <25>
PD_80P <21> WSC- <11>
PAPICD0- <34> SUSB- <25> SUSC- <25,33>
10K
CPUFAN1 <24>
CPUFAN2 <24>
EC41 10u
HM_GND
FB14
FB13
RN74 22
VCC3
R303 10K-REV
t
0_0805
0_0805
12 56 34 78
SYNC <27> SDOUT <27> ACRST- <27>
SDIN0 SDIN1
CPUSTOP-
VCC2_5 VCORE
R304 0-REV
RT1 10K
VCC3
4
RN70
1 2 3 4 5 6 7 8
10K
RN78
1 2 3 4 5 6 7 8
10K
R312
53.6K
R309 10K
C348
1u
C349
1u
R310 10K
Place RT2 under CPU2
VT686B
INTA#
PCI1 PCI2 PCI3 PCI4 PCI5
NA
INTB#
NA
INTC#
NA
INTD#
NA
IDSEL AD18 AD20 AD21 AD22 AD23 AD24 AD26
VCC3
VCC+12V
R321
C363
16.2K
0.1u
HM_GND
t
Place RT1 under CPU1
HM_GND
3
R316
B
CDAA
C
DAB
D
ABB
C
A
D
JBY
JBY<28>
JAX
JAX<28>
JBX
JBX<28>
JAY
JAY<28>
JAB1
JAB1<28>
JBB1
JBB1<28>
JBB2
JBB2<28>
JAB2
JAB2<28>
TXD
TXD<28>
RXD
RXD<28>
C364
0.1u
R319 10K
RT2 10K
JCASE1
1 2
D1x2
3VDUAL
2M
Title
Size Document Number Rev
Date: Sheet
1394 RAID
A
B
C
C
D
R265 1K
SPKR
PME-_SB SUSST­SMBALT-
PD_80P RI­EXTSMI­SD_80P
SUSLED
PME-_SB
PCKRUN-
7 8 5 6 3 4 1 2
1 2 3 4 5 6 7 8
R300 1K
R270 0
R326 100
RN69
10K
RN73
10K
MICRO-STAR
VT686A (Part1)
2
3VDUAL
R308 10K
RSMRST-
C342 1u
MS-6502
VCC3
3VDUAL
PME- <15,16,17,18,31>
of
19 39Wednesday, March 21, 2001
1
0A
8
SD_D[0..15]
SD_D[0..15]<21,24>
D D
SA16<24> SA17<24> SA18<24>
SD[0..7]
SD[0..7]<24>
C C
B B
GPO16<32> GPO17<32> GPO18<32>
GPO19<32> FAN_ON2<24> PWRLED<25>
MEMR-<24> MEMW-<24>
OSC<3>
IRRX<25>
R261 1K
IRQ14<21>
IRQ15<21>
FDD_WP-
Q61
C
E
NPN-3904LT1-S-SOT23
8
IRTX<25>
R411 1K
B
VCC
A A
7
SD_D0 SD_D1 SD_D2 SD_D3 SD_D4 SD_D5 SD_D6 SD_D7 SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
GPO16 GPO17 GPO18 GPO19 FAN_ON2
DREQ0 USBOC-1 DREQ1 DREQ3 DREQ5 DREQ6 DREQ7
SBHE- MCLK REFRESH­IOR­IOW­MEMR­MEMW-
IOCS16­MEMCS16­IOCHRDY GPI0
OSC
IRRX IRTX
IRQ3 IRQ4 IRQ5
IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15
VCC3
U22B
W1
SA0
V2
SA1
V1
SA2
U3
SA3
U2
SA4
U1
SA5
T4
SA6
T3
SA7
T2
SA8
T1
SA9
R5
SA10
R4
SA11
R3
SA12
R2
SA13
R1
SA14
P5
SA15
P4
SA16
P3
SA17
K2
SA18
K1
SA19
J5
LA20
J4
LA21
J3
LA22
J2
LA23
Y1
SD0
Y2
SD1
W2
SD2
Y3
SD3
W3
SD4
V3
SD5
Y4
SD6
W4
SD7
L5
SD8
M2
SD9
M4
SD10
N1
SD11
N3
SD12
N5
SD13
P1
SD14
P2
SD15
L2
DACK0
E1
DACK1
D2
DACK3
L4
DACK5
M3
DACK6
N2
DACK7
L3
DRQ0
E2
DRQ1
D3
DRQ3
M1
DRQ5
M5
DRQ6
N4
DRQ7
B2
AEN
H2
BALE
F2
SBHE
E3
REFRESH
D1
IOR
C2
IOW
U4
MEMR
V4
MEMW
A1
SMEMR
B1
SMEMW
F3
IOCS16
F1
MEMCS16
A2
IOCHRDY
F4
IOCHK/GPI0
H1
TC
J1
RSTDRV
E4
OSC
H5
BCLK
D12
IRRX/GPO15
E12
IRTX/GPO14
G4
IRQ3
G3
IRQ4
G2
IRQ5
G1
IRQ6/SLPBTN
F5
IRQ7
H4
IRQ9
K3
IRQ10
K4
IRQ11
L1
IRQ14
K5
IRQ15
T5
XDIR/PCS0/GPO12
U5
XOE/GPO13
F7
VCC
F10
VCC
F12
VCC
F13
VCC
F14
VCC
H6
VCC
J6
VCC
K6
VCC
M6
VCC
N6
VCC
VIA-VT82C686B-VB
7
PRD0 PRD1 PRD2 PRD3 PRD4 PRD5 PRD6 PRD7
BUSY
SLCT
ERROR
PINIT
AUTOFD
SLCTIN
STROBE
TXD1 DTR1 RTS1 CTS1 DSR1 DCD1
RXD1
TXD2 DTR2 RTS2 CTS2 DSR2 DCD2
RXD2
VCCUSB
GNDUSB
USBCLK
USBP0+
USBP0-
USBP1+
USBP1-
DRQ2/OC1/SERIRQ
DACK2/OC0/GPIOF
USBP2+
USBP2-
USBP3+
USBP3-
KBCK
KBDT/KBRC
MSCK/IRQ1
MSDT/IRQ12
ROMCS
DRVDEN0 DRVDEN1
INDEX
MTR0
MTR1
STEP
WDATA WGATE TRAK00
WRTPRT
RDATA
HDSEL
DSKCHG
6
PD0
B15
PD1
D15
PD2
A14
PD3
B14
PD4
C14
PD5
D14
PD6
E14
PD7
A13
B13
ACK
C13 D13
PE
E13 A15 C15 C16 E15 D16
SOUTA
A11
DTRA-
D11
RTSA-
B11
CTSA-
C11
DSRA-
C12
DCDA-
A12
RIA-
E11
RI1
SINA
B12
SOUTB
D10
DTRB-
B9
RTSB-
E10
CTSB-
A9
DSRB-
C10
DCDB-
A10
RIB-
C9
RI2
SINB
B10
USB_VCC
F9
USB_GND
F8
USBCLK
C3
SR_USBP0
A3
SR_USBN0
B3
SR_USBP1
C4
SR_USBN1
D4
USBOC-0
H3 G5
SR_USBP2
A4
SR_USBN2
B4
SR_USBP3
B5
SR_USBN3
E6
KCLK
E5
KDAT
A5 D5
MDAT
C5
BIOSCS-
C1
DRVEN0
D9
DRVEN1
D6
INDEX-
D7
MOA-
E9
DSB-
A8
DS1
DSA-
B8
DS0
MOB-
C8
DIR-
D8
DIR
STEP-
E8
WD-
A7
PWE-
B7
TRAK0-
E7
FDD_WP-
A6
RDATA-
B6
HEAD-
C7
DSKCHG-
C6
F6
GND
F11
GND
G6
GND
J9
GND
J10
GND
J11
GND
J12
GND
K9
GND
K10
GND
K11
GND
K12
GND
L6
GND
L9
GND
L10
GND
L11
GND
L12
GND
M9
GND
M10
GND
M11
GND
M12
GND
P6
GND
R6
GND
6
PD[0..7]
ACK- <22> BUSY <22> PE <22> SLCT <22> ERR- <22> INIT- <22> AFD- <22> SLIN- <22> STB- <22>
SOUTA <22> DTRA- <22> RTSA- <22> CTSA- <22> DSRA- <22> DCDA- <22> RIA- <22> SINA <22>
SOUTB <22> DTRB- <22> RTSB- <22> CTSB- <22> DSRB- <22> DCDB- <22> RIB- <22> SINB <22>
C252
0.1u
5
PD[0..7] <22>
EC35 10u
FB12
0_0805
4
3VDUAL
USBCLK <3>
USBOC-0 <26> USBOC-1 <26>
KCLK <23> KDAT <23> MCLK <23> MDAT <23>
BIOSCS- <24>
DRVEN0 DRVEN1
INDEX­MOA­DSB­DSA­MOB­DIR­STEP­WD­PWE­TRAK0-
RDATA­HEAD-
FDD. Trace length must be less than 12 inches.
FDD_WP-
DSKCHG-
D16
A C
1N4148-S-LL34
SR_USBP0
SR_USBP1 USBP1 SR_USBN1
5
FDD1
1342
56 78 91110
12
1314
16 15
1718 1920
22
21
24
23
26
25
28
27
30
29
32
31
34
33
D2x17-3:29.30.31-BK
0
VCC
RN117 150
1
2
3
4
5
6
7
8
R385 150
RN48
78 56 34 12
27
123456
78
CN12
47p
4
USBP0 USBN0SR_USBN0
USBN1
3
MEMCS16­SBHE­IOCS16­IOR­IRQ9 IRQ3 IRQ5 IRQ4
BIOSCS­IOW­IOCHRDY SA20 GPI0 IRQ7 REFRESH­IRQ11
SD3 SD4 SD5 SD1 SD7 SD6 SD_D6 SD_D10
SD_D7 SD_D14 SD_D13 SD_D12 SD_D8 SD_D9 SD_D11 SD15
SD10 SD8 SA19 SA18 SA21 IRQ10 SA23 SA22
SR_USBP2 SR_USBN2 SR_USBP3 SR_USBN3 USBN3
RN49
78 56 34 12
RN53
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9510
9510
4.7K
RN50
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9510
9510
4.7K
RN67
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9510
9510
4.7K
RN64
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9510
9510
4.7K
RN56
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9510
9510
4.7K
VCC
VCC
VCC
VCC
VCC
RN51
27
123456
78
CN13
47p
15K
Title
Size Document Number Rev
3
Date: Sheet
2
SMBCLK
SMBCLK<3,13,14,19,34>
SMBDATA
SMBDATA<3,13,14,19,34>
SBREQ-
SBREQ-<11,19>
SBGNT-
SBGNT-<11,19>
SLP-
SLP-<19>
USBP0
USBP[0..3] USBP1 USBP2 USBP3
USBN[0..3]
USBN0 USBN1 USBN2 USBN3
SA17
1
SD12
2
SD11
3
SD9
4
SD_D15
6
SD13
7
SA16
8
SD14
9
SD0
1
SD_D0
2
SD2
3
SD_D1
4
SD_D2
6
SD_D3
7
SD_D4
8
SD_D5
9
1
DREQ7
2
DREQ5
3
DREQ0
4
DREQ6
6
DREQ3
7
DREQ1
8 9
USBP2
78
USBN2
56
USBP3
34 12
RN61
4.7K
RN65
4.7K
RN58
4.7K
RN52
1 2 3 4 6 7 8 9510
1 2 3 4 6 7 8 9510
1 2 3 4 6 7 8 9510
1
R307 1K
R306 1K
R288 4.7K
R297 4.7K
R301 4.7K
USBP[0..3] <26>
USBN[0..3] <26>
VCC
5
10
VCC
5
10
5
10
78 56 34 12
VCC3
NOPOP
15K
MICRO-STAR
VT686A (Part2)
MS-6502
2
20 39Wednesday, March 21, 2001
0A
of
1
5
4
3
2
1
D D
PD_D[0..15]<19>
SD_D[0..15]<20,24>
C C
B B
A A
5
PD_D[0..15]
SD_D[0..15]
RN84
PDA2PD_A2
7
PD_A2<19>
PD_A0
PD_A0<19>
-PDCS_1
-PDCS_1<19>
-PDCS_3
-PDCS_3<19>
PD_D8 PDD8 PD_D7 PDD7 PD_D9 PDD9 PD_D6 PDD6
PD_D12 PD_D3 PD_D13 PDD13 PD_D2 PDD2
PD_D10 PDD10 PD_D5 PDD5 PD_D11 PDD11 PD_D4 PDD4
PD_D0 PD_D15 PD_D1 PD_D14 -DIORB
PCIRST-<19>
8
PDA0
5
6
-PDCS1
3
4
-PDCS3
1
2
33
RN129
7
8
5
6
3
4
1
2
33
RN121
PDD12
7
8
PDD3
5
6
3
4
1
2
33
RN125
7
8
5
6
3
4
1
2
33
RN115
33
PDD0
1
2
PDD15
3
4
PDD1
5
6
PDD14
7
8
147
U17B
1 2
147
5 6
147
9 8
4
3VDUAL
PCIRST- PCIRST-1
147
3 4
SN74LVC14A-SOIC14
PD_A1<19>
-DDACK_A<19>
-DIOR_A<19>
HDRDY_A<19>
-SDCS_1<19>
-SDCS_3<19> SD_A0<19> SD_A2<19>
DDREQ_A<19>
-DIOW_A<19>
-DIOW_B<19>
DDREQ_B<19>
SD_A1<19>
-DDACK_B<19>
-DIOR_B<19>
HDRDY_B<19>
U17A
IDERST
SN74LVC14A-SOIC14
U17C
SN74LVC14A-SOIC14
U17D
PCIRST-2
SN74LVC14A-SOIC14
RN118
SD_D14 SD_D1 SD_D15 SD_D0
SD_D10 SD_D5 SD_D11 SD_D4
SD_D8 SD_D7 SD_D9 SD_D6
SD_D12 SD_D3 SDD3 SD_D13 SD_D2
PD_A1
-DDACK_A
-DIOR_A HDRDY_A
-SDCS_1
-SDCS_3 SD_A0 SD_A2
DDREQ_A
-DIOW_A
-DIOW_B DDREQ_B
SD_A1
-DDACK_B -DDACKB
-DIOR_B HDRDY_B
1
2
3
4
5
6
7
8
33
RN127
1
2
3
4
5
6
7
8
33
RN131
1
2
3
4
5
6
7
8
33
RN122
1
2
3
4
5
6
7
8
33
RN110
1
2
3
4
5
6
7
8
33
RN83
1
2
3
4
5
6
7
8
33
RN113
1
2
3
4
5
6
7
8
33
RN111
1
2
3
4
5
6
7
8
33
PCIRST-1 <15,16,17,18>
C204 4700p
PCIRST-2 <11,13,29,31,34>
C203 4700p
SDD14 SDD1SDD1 SDD15 SDD0
SDD10 SDD5 SDD11 SDD4
SDD8 SDD7 SDD9 SDD6
SDD12
SDD13 SDD2
PDA1
-DDACKA
-DIORA HDRDYA
-SDCS1
-SDCS3 SDA0 SDA2
DDREQA
-DIOWA
-DIOWB DDREQB
SDA1
HDRDYB
3
All series Res. should be very close SB
VCC
R367 1K
HDRDYA
IRQ14<20>
VCC
R256
VCC
R369
1K
HDRDYB
IRQ15<20>
VCC
R362
PD_D7
R401
10K
R277 10K
VCC
DDREQA
R404
4.7K
DDREQB
ATA33/66/100
IDERST
PDD7 PDD6 PDD5 PDD4 PDD3
R383
PDD2 PDD13
5.6K
PDD1 PDD14 PDD0 PDD15
-DIOWA
-DIORA
-DDACKA
PDA1 PDA0
-PDCS1
10K
VCC
R402
4.7K
-DASP0
-DASP1
IDERST SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1
R384
SDD0
5.6K
-DIOWB
-DIORB
-DDACKB
SDA1 SDA0
-SDCS1
10K
-DASP1
SD_D7
2
1 3 4 5 6 7 8 91110
13 14
17 18 19 20 21 23 25 27 29 31 33 35 37
D2x20-1:21-BL
1N4148-S-LL34
D18
D19
1N4148-S-LL34
1 3 4 5 6 7 8 91110
13 14
17 18 19 20 21 23 25 27 29 31 33 35 37
D2x20-1:21-WH
VCC
C232
0.1u
Title
Size Document Number Rev
Custom
Date: Sheet of
IDE1
2
12
1615
22 24 26 28 30 32 34 36 38 4039
IDE2
2
12
1615
22 24 26 28 30 32 34 36 38 4039
C226 104P-REV
PDD8 PDD9 PDD10 PDD11 PDD12
R371
470
PD_80P <19>
PDA2
-PDCS3
HD_LED1 <25,30>
SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
R373
470
SD_80P <19>
SDA2
-SDCS3
C230
C368
0.1u
0.1u
MICRO-STAR
ATA33/66 Connectors
MS-6502
1
21 39Wednesday, March 21, 2001
0A
8
PD[0..7]
PD[0..7]<20>
ACK-
ACK-<20>
BUSY
BUSY<20>
PE
PE<20>
SLCT
D D
SLCT<20>
PD3 ERR-
ERR-<20>
INIT-
INIT-<20> SLIN-<20>
PD0 PD1 PD2 AFD-
AFD-<20>
PD4 PD5 PD6 PD7
STB-<20>
C C
C66
0.1u
+12V
B B
A A
-12V
RTSB-<20> DTRB-<20>
SOUTB<20>
CTSB-<20>
DSRB-<20>
DCDB-<20>
RTSA-<20> DTRA-<20> SOUTA<20>
RIA-<20>
CTSA-<20> DSRA-<20>
SINA<20>
DCDA-<20>
C69
0.1u
RIB-<20>
SINB<20>
1N4148-S-LL34
D5
1N4148-S-LL34
7
RN18 33
1 2 3 4 5 6 7 8
RN20 33
1 2 3 4 5 6 7 8
RN21 33
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
RN19 33
R23 33
D3
RTSA- NRTSA DTRA- NDTRA SOUTA NSOUTA
RIA- NRIA­CTSA- NCTSA­DSRA- NDSRA­SINA NSINA DCDA- NDCDA-
RTSB­DTRB­SOUTB
RIB­CTSB­DSRB­SINB DCDB-
U9
1
VDD(12V)
16
DA1
15
DA2
13
DA3
19
RA1
18
RA2
17
RA3
14
RA4
12
RA5
10
VSS(-12V)
Multiple RS232 Drivers and Receivers
U8
1
VDD(12V)
16
DA1
15
DA2
13
DA3
19
RA1
18
RA2
17
RA3
14
RA4
12
RA5
10
VSS(-12V)
TI-GD75232-SSOP20
Multiple RS232 Drivers and Receivers
RACK­RBUSY RPE RSLCT
PRND3
RERR­RINIT­RSLIN-
PRND0 PRND1 PRND2
RAFD-
PRND4 PRND5 PRND6 PRND7
RSTB-
TI-GD75232-SSOP20
CN6 180p
1 2 3 4 5 6 7 8
CN8 180p
1 2 3 4 5 6 7 8
CN9 180p
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
CN7 180p
C43 180p
VCC(5V)
GND
VCC(5V)
GND
6
20
5
DY1
6
DY2
8
DY3
2
RY1
3
RY2
4
RY3
7
RY4
9
RY5
11
20
5
DY1
6
DY2
8
DY3
2
RY1
3
RY2
4
RY3
7
RY4
9
RY5
11
NRTSB NDTRB NSOUTB
NRIB­NCTSB­NDSRB­NSINB NDCDB-
RSLCT RPE RBUSY
RACK­PRND7 PRND6 PRND5 PRND4
RAFD­PRND2 PRND1 PRND0
RSLIN-
RINIT-
RERR­PRND3
RSTB-
VCC
VCC
INTERNAL MODEM WAKEUP HEADER
1N4148-S-LL34
RN26
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9
9510
2.2K
RN27
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9
9510
2.2K
R35 2.2K
CGNDCGND
5
NRIA-
NRIB-
VCC
D6
5
10
5
10
JMDM1
D1x5-BK
C67
0.1u
D4 1N4148-S-LL34
D7 1N4148-S-LL34
5 4 3 2 1
NDTRB NSINB NSOUTB NDCDB-
NRIB­NCTSB­NDSRB­NRTSB
CGND
CGNDSTB-
CN10
1 2 3 4 5 6 7 8
180p
CN11
1 2 3 4 5 6 7 8
180p
CN4
7 8 5 6 3 4 1 2
180p
CN5
7 8 5 6 3 4 1 2
180p
R49 10K
5VSB
R25 10K
4
R50
1 2
4.7K
NRIA­NCTSA­NDSRA­NRTSA
NDTRA NSINA NSOUTA NDCDA-
B
CGND
CGND
C
E
U10A
7407-SOIC14
Q14
NPN-3904LT1-S-SOT23
3
2
1
LPT1
47
NDCDA­NDSRA­NSINA NRTSA NSOUTA NCTSA­NDTRA NRIA-
NDCDB­NDSRB­NSINB NRTSB NSOUTB NCTSB­NDTRB
RI-
NRIB-
26 31 27 32 28 33 29 34 30
49
48
50
35 40 36 41 37 42 38 43 39
51
RSLCT
13 25
RPE
12 24
RBUSY
11 23
RACK-
10 22
PRND7
9 21
PRND6
8 20
PRND5
7 19
PRND4
6 18
PRND3
5
RSLIN-
17
PRND2
4
RINIT-
16
PRND1
3
RERR-
15
PRND0
2
RAFD-
14
RSTB-
1
52
46
LPT-D25-BR-BI
LAN WAKEUP HEADER
JWOL1
3 2 1
D1x3-WH-HSNO
5VSB
R59 1K
C73
0.1u
CGND
B
R63 10K
CGND <23,26>
RI-
RI- <19>
C
Q16 NPN-3904LT1-S-SOT23
E
Title
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet of
2
MICRO-STAR
LPT & COM Ports
MS-6502
22 39Wednesday, March 21, 2001
0A
1
8
7
6
5
4
3
2
1
VCC
1 2
3 4
5 6
5VSB
FUSE USE POLY SWITCH FUSE
7 8
R24 1K
D1
1N4148-S-LL34
A C
D2
1N5817-S-DO-241AC
5
F2
1.1A-MF-MSMD110-S
FB8
1 2
0
FB9
1 2
0
VBAT
123
JBAT1
D1x3-BK
D D
+
EC9
VCORE
R169
G
270
P0_DC_OK
DS
Q28 NDS7002A-S-SOT23
VCC
R171
75K
VCC3
R177 30K
R174
R201 30K
15K
R191
10K
C C
P1_VCCA_PLL1
R187 15K
VCORE
R205 15K
C209 1u
C198 1u
C202 1u
B
B
B
C
Q33
E
NPN-3904LT1-S-SOT23
C
Q34
E
NPN-3904LT1-S-SOT23
C
Q39
E
NPN-3904LT1-S-SOT23
10u
P0_DC_OK <4>
RN23
4.7K
KDAT<20>
KCLK<20>
MCLK<20>
MDAT<20>
VCORE
R121
VCC
270
G
P1_DC_OK
DS
Q21 NDS7002A-S-SOT23
P1_DC_OK <6>
R19 3K
BAT1
3
R29 1K
12
BH-D2
7
6
R141
15K
R153
10K
C167 1u
C152 1u
C162 1u
VCC
B
B
B
R129
75K
C
Q23
E
NPN-3904LT1-S-SOT23
C
Q26
E
NPN-3904LT1-S-SOT23
C
Q27
E
NPN-3904LT1-S-SOT23
B B
VCC3
R146 30K
P1_VCCA_PLL1
R151 15K
VCORE
R162 15K
R160 30K
A A
8
C31
0.1u
CGND
C306 0.1u
R18 1K
0805 SIZE
FB7
1 2
0_0805
FB11
1 2
0
FB10
1 2
0
4
JBAT(1-2) JC-D2-GN
KBMSVCC
C45
0.1u
CGND
5 6
7 8
Support Keyboard wake-up
JKBMS1
14
6 4 2 1 3 5
15 17
MINIDINx2-D12-ML
CGND
CN2
220p
1 2
3 4
CGND
CGND <22,26>
16
10 12 8 7 11 9
13
PCB1
1650200B
Title
Size Document Number Rev
Custom
3
Date: Sheet of
MICRO-STAR
Keyboard & Mouse
MS-6502 0A
2
23 39Thursday, May 03, 2001
1
8
7
6
+12V
5
4
3
2
1
C217 0.1u
R212 1K
D D
VCC3
R390 10K
R393
4.7K
C C
C430 0.1u
R400 4.7K SYSFAN1
R399 1K
C
B
Q58
E
NPN-3904LT1-S-SOT23
B
B
E
PNP-A-31-S-SOT23
C
C216
0.1u
+12V
E
PNP-A-31-S-SOT23
C
C469
0.1u
Q41
Q60
PSFAN1
3 2 1
D1x3-WH-SN
3 2 1
D1x3-WH-SN
SD_D[0..15]<20,21>
SD_D[0..15]
SD_D0 SD_D1 SD_D2 SD_D3 SD_D4 SD_D5 SD_D6 SD_D7 SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 SA16
SA16<20>
SA17
SA17<20>
VCC
R291
R292 0
Reserved
4.7K
SA18<20>FAN_ON2<20>
BIOS
U26
12
A0
11
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 CE#
PGM#
PLCC32-SMT
VCC
D0 D1 D2 D3 D4 D5 D6 D7
VCC
OE#
GND
10
9 8 7 6
5 27 26 23 25
4 28 29
3
2 30
1 22
SD[0..7]
SD[0..7] <20>
SD0
13
SD1
14
SD2
15
SD3
17
SD4
18
SD5
19
SD6
20
SD7
21
32
24 31 16
R299
4.7K
BIOSCS­MEMR-
C313
0.1u
VCC
R289
0-REV
EC
Q48 NPN-3904LT1 -S-SOT23
B
R290 1K
JP2
1 2
D1x2
BIOSCS- <20> MEMR- <20> MEMW- <20>
ROMLOCK <19>
Bios Protection
+12V
C377 0.1u
R341 4.7K
R342 1K
B B
C114 0.1u
R67 4.7K
R60 1K
C
FAN_ON<19>
A A
B
Q18
E
R61
4.7K
NPN-3904LT1-S-SOT23
B
B
E
C
+12V
E
C
Q50
PNP-A-31-S-SOT23
C385
0.1u
Q17
PNP-A-31-S-SOT23
C113
0.1u
CPUFAN2
3 2 1
D1x3-WH-SN
CPUFAN1
3 2 1
D1x3-WH-SN
VCC3
VCC3
12
12
R339
4.7K
R66
4.7K
CPUFAN2
CPUFAN1FAN_ON
CPUFAN2 <19>
CPUFAN1 <19>
Fan Driver
12 11 10
9 8 7 6
5 27 26 23 25
4 28 29
3
2
22 24
1 31
U26-1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
CE# OE# VPP PGM#
W49F002UP12N
JP2(1-2) JC-D2-GN
NOPOP
D0 D1 D2 D3 D4 D5 D6 D7
VAA
VCC
GND
13 14 15 17 18 19 20 21
30
32
16
2
MICRO-SATR
BIOS & Fans
MS-6502
24 39Wednesday, March 21, 2001
0A
1
Title
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet of
5
R331
3VDUAL
JRMS1
D D
C C
AC97_SPKR<27>
B B
PWRON-
VCC
A A
D1x2-WH
JP1(2-3) JC-D2-GN
SPKR<19>
R109
2.2K
R124
2.2K-REV
-12V
-5V
VCC3
4.7K
R334 68
1 2
EXTSMI-<19>
VCC
1 2 3 4 5
JIR1 D1x5-BK
VCC
LED3 LED2 LED1 PWRSW+
JP1
1 2 3
D1x3-BK
B
C83
0.1u
JWR1
11
3.3V
12
-12V
13
GND
14
PS_ON
15
GND
16
GND
17
GND
18
-5V
19
5V
20
5V
ATX-D2x10
D10
1N4148-S-LL34
5
EXTSMI-
IR
C471
0.1u
C470
0.1u
C
E
Q20 NPN-3904LT1-S-SOT23
3.3V
3.3V GND
5V
GND
5V
GND
PW_OK
5V_SB
12V
PWRBT-PWRSW+
C375 1u
IRRX
IRTX
R387
270
C422
0.1u
RN34
1 2 3 4 5 6 7 8
150
1 2 3 4 5 6 7 8 9 10
IRRX <20>
IRTX <20>
A3
C413
0.1u
D9
1N4148-S-LL34
C112
0.1u
VCC
5VSB +12V
JGS1
1 2
D1x2
PWRBT- <19>
VCC
MSI
JFP1
1 2 3 4 5 6 7
D2x7-1:7-BK
C157
0.1u
R155
2.2K
R154
4.7K
VCC
8
9 10 11 12 13 14
A1
D12
1N4148-S-LL34
SN74LVC14A-SOIC14
R158 10K
4
4
C411 470p
HD_LED1
A2
AC
C172
0.1u
3VDUAL
13 12
5VDUAL
R58 330
Reserved for LEGEND
R73 0
PLED1 LED2
Reserved for LEGEND
R78 0
Reserved for LEGEND
HD_LED1 <21,30>
RAIDLED <21,30>
R389 0-REV
R392
100
FP_RST-
FP_RST- <3>
BZ1 BUZZER-SAT1205-85dB-D
VCC
5VSB
U17F
147
14
LED3PLED2
JFP1(10-11 JC-D2-GN
5VSB
R223 1K
U18C
5 6
SN74ALS05ADR-SOIC14
PWRGD <33>
VCC3
R391 1K
1110
147
U17E
SN74LVC14A-SOIC14
5VSB
34
14
U18B SN74ALS05ADR-SOIC14
5VSB
3
PWRLED<20>
C417
0.1u
3VDUAL
U18D
14
9 8
SN74ALS05ADR-SOIC14
3
R227 1K
SUSB-<19>
SUSC-<19,33>
PWRLED
5VSB
VCC
R51 1K
PWRLED
SUSLED<19>
STR Power-On
R197 0
SUSB-
R193 0-REV
Normal Power-On
5VSB
U18F
14
13 12
SN74ALS05ADR-SOIC14
5VSB
3 4
SUSLED
C210 0.1u
3VDUAL
R222 270
U10B
7407-SOIC14
5VSB
5 6
5VSB
U18E
14
11 10
SN74ALS05ADR-SOIC14
5VSB
U18A
14
SUSLED
1 2
7
SN74ALS05ADR-SOIC14
R192
4.7K
4.7K
R56
VCC3
PWROK
2
B
C225 4700p
2
VCC
R53 270
U10C
7407-SOIC14
5VSB
C
Q15
E
NPN-3904LT1-S-SOT23
PWROK <19>
1
R64 0
R188 10K
C206 1000p
PWRON-
5VSB
JGL1
1 2 3
D1x3-BK
R77 270
PLED1
PLED2
C76
0.01u
C75
0.01u
C78
0.1u
R84 0
R85 0
VCCVCC VCCVCC
C77
0.1u
VCC3VCC3
-12V
C91
0.1u
5VSB+12V -5V
-12V
C74
0.1u
LED1
LED2LED1
LED3
C111
0.01u
+12V
C88
0.1u
C81
0.1u
Put near ATX Power Connector
For EMI issue
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR
Front Panel
MS-6502
1
25 39Wednesday, March 21, 2001
C106
0.1u
10u
+
EC13
C110
0.1u
0A
E
D
C
B
A
EC11
5VDUAL
F3
+
1.1A-MF-MSMD110-S
C54 1000p
C48 47K
J2A
21
1 2 3 4
24 23
4 4
USBP[0..3] <20>
USBN[0..3] <20>
1000u/6.3V
RJ45+USB+LEDx2-D20-BK
3 3
C47 0
R378
F4
+
EC51
1000u/6.3V
2 2
EC52
470u
1.1A-MF-MSMD110-S
C403
+
1000p
USBN2_FB USBP2_FB USBP3_FB
470K
USB2_5V
USB1
12
4
3
6
5
8
7
109
D2x5-BK
VCC3
R347
C388 47p
1.5K
USBPP4P
1 1
R34922
R34822
C386 47p
E
USBPC4NUSBPP4N USBPC4P XTAL2
VCC3
EC40
10u
USBP1 USBN1
U25
1
GPIO1
2
GPIO2
3
LVM
4
LVP
5
VCP
6
RVP
EXTRST_
7
RVM
8 9
GND GND
GL620USB
D
GPIO4 GPIO3 XTAL2 XTAL1
OSCSEL
XTAL2A
C378
33p
C
VCC
EC38
10u
16
VCC
15 14
R338 33
13
XTAL1
12 11 10
Y5 12M-32pf-HC49S-D
R337 1M
C379
33p
R26
470K
USB1_5V
R34
+
10K
EC10
470u
22
5 6 7 8
CGND
C408
0.01u
USBN1_FBUSBN0_FB USBP1_FBUSBP0_FB
CGND <22,23>
R386 10K
USBN3_FB
USBN0 USBP0
USBPP4N USBPP4P USBP3_FB
B
C56
0.01u
USBOC-0 <20>
USBOC-1 <20>
USBN2
FB4 0
USBP2
FB3 0
FB6 0
USBP3
FB5 0
123456
78
CN1 10p
FB20 0 FB19 0
FB18 0 FB17 0
123456
Title
Size Document Number Rev
Custom
Date: Sheet of
78
CN17 10p
MICRO-STAR
USB Connector
USBN2_FB USBP2_FB
USBN3_FB
MS-6502
CGND
USBN0_FB USBP0_FB
USBN1_FBUSBN3 USBP1_FB
A
26 39Thursday, March 22, 2001
0A
8
7
6
5
+5VR
4
3
VR1
+12V +5VR
L78L00-TO92-100mA
GND
VIN
VOUT
2
1
231
1 2
D D
VCC3
C61
C53
12
22p
Y1
24M-16pf-HC49S-D
C60
C64
22p
1 2
12
R33 22
R32 22
C58
22p
C C
SDOUT<19> BITCLK<19>
SDIN0<19>
SYNC<19>
ACRST-<19>
AC97_SPKR<25>
R31 1K-REV
1u
R28
4.7K-REV C57 102P-REV
B B
A A
0.1u
1
DVDD1
2
XTL_IN
3
XTL_OUT
4
DVSS1
5
SDATA_OUT
6
BIT_CLK
7
DVSS2
8
SDATA_IN
9
DVDD2
10
SYNC
11
RESET#
12
PC_BEEP
C59
0.1u
R17 0
4847464544424140394338
NC
NC
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
AVSS2
PHONE
AUXL
AUXR
VIDEOL
VIDEOR
CDLNCCDR
MIC1
1314151617181920212223
C46 1u
C51 1u
C52 1u
C18 1u
RN6
1 2 3 4 5 6 7 8
8P4R_0-REV
U5
37
NC
MONO
AVDD2
LOUTR LOUTL
NC
NC VRDA VRAD
AFILT2 AFILT1
NC
VREF AVSS1 AVDD1
MIC2
LINL
LINR
24
CODEC-VIA-VT1611A-VA8
C22 1u
C25 1u
C26 1u
C27 1u C33 1u C44 1u
36 35 34 33 32 31 30 29 28 27 26 25
C21
470p
R11 1K
C8
0.1u
C23
0.1u
R7
2.2K-REV
R5 20K
R8 20K
C19
470p
RN7
7 8 5 6 3 4 1 2
4.7K
AGND
MIC_IN
C7
102P-REV
LINE_OUT_R LINE_OUT_L
+
EC1
MIC_IN
C20 1000p
10u
C9
0.1u
C5 102P-REV
RN13
4.7K
C10
0.1u
LINE_R <28>
LINE_L <28>
MIC_IN <28>
78 56 34 12
LINE_OUT_R <28> LINE_OUT_L <28>
AGND
8
7
6
5
4
+
10u
EC2
C49
0.1u
-12V
C63
0.1u
C11
C12
270p
270p
JCD1
4 3 2 1
CD-D1x4-BK-SBTJ
JAUX1
4 3
AUX IN
2 1
AUX-D1x4-YL
JPHN1
1 2
MODEM IN
3 4
MON-D1x4-GN
AGND
VR2
LM79L05-TO92-100mA
2 3
IN OUT
GND
1
AGND
10u
C14
C13
1u
1u
C15
+
EC3
473P-REV
+5VR
R13 1K
R10
4.7K-REV
MIC_IN AGND
CD IN
3
-5VR
C16
0.1u
Title
Size Document Number Rev
Date: Sheet
10u
C50
+
EC4
0.1u
C62
EC5
+
0.1u 10u
0805 SIZE
C17
1u
R16
EC6
+
10u
1K
C28
0.1u
R12
2.2K
MIC_PWR <28>
MICRO-STAR
AC'97 CODEC
MS-6502
2
27 39Wednesday, March 21, 2001
0A
of
1
8
7
6
+5VR
5
4
3
2
1
AGND
C6
1u
D D
LINE_OUT_R<27>
LINE_OUT_R
R4
C3
47K
1u
3
+
2
-
8 4
U4A
1
TI-TL072CDR-SOIC8
R3 47K
R1 33
FB1
1 2
0_0805
SPEAKER_R
C4 1000p
C2 33p
U4B
5
+
LINE_OUT_L<27>
C C
AGND
LINE_OUT_L
GAME AND CODEDEC BRIDGE
R15
C30
47K
1u
-5VR
6
C24
1u
-
TI-TL072CDR-SOIC8
8 4
AGND
7
R14 47K
C29 33p
R9 33
FB2
1 2
0_0805
0805 SIZE
SPEAKER_L
C1 1000p
AGND
VCC
F1
1.1A-MF-MSMD110-S
C42
0.1u
B B
SPEAKER_R
SPEAKER_L
LINE_R<27>
LINE_L<27>
MIC_PWR<27>
A A
MIC_IN<27>
R
23
22
G
30
21
L
20
R
19
18
G
28
17
L
16
R
27
26
G
29
25
L
24
AUDIO1
32
8 15 7 14 6 13 5 12 4 11 3 10 2 9 1
31
GAME-PHONE-D15-ML-B
RN16
4.7K
1 2
3 4
5 6
7 8
RN11
JBB1 JAB1
C32
0.1u
CN3
1 2
3 4
5 6
7 8
100p
2.2K
AGND
8
7
6
5
VCCVCC
VCC
R21
R22 22K
4.7K
TXD
TXD <19>
RXD <19> JAB2 <19> JBB2 <19>
C38
0.01u
JAY
JAY <19>
JBY
JBY <19>
JBX
JBX <19>
JAX
JAX <19> JBB1 <19> JAB1 <19>
2
MICRO-STAR
Audio/Game Port
MS-6502
28 39Wednesday, March 21, 2001
0A
1
Title
Size Document Number Rev
Custom
3
Date: Sheet of
78 56 34 12
C37
C36
C41
C40
0.01u
C39
0.01u
0.01u
4
100p
100p
5
IDE RAID Control
D D
AD[31..0]<11,16,17,18,19,31,34,37>
C C
C_BE-[3..0]<11,16,17,18,19,31,37>
1N4148-S-LL34
D11
AD26
DIS_IDE<34>
VCC
B B
C301 1000p
IF INSTALL OSC1 THEN REMOVE R473
AC
4
3
OUT
VDD
66M-5V-DH
OE
GND
1
2
OSC1
R262
AD[31..0]
C_BE-[3..0]
FRAME-<11,16,17,18,19,31>
IRDY-<11,16,17,18,19,31>
TRDY-<11,16,17,18,19,31>
DEVSEL-<11,16,17,18,19,31>
STOP-<11,16,17,18,19,31>
PAR<11,16,17,18,19,31,37>
PIRQC-<15,16,17,18,19> REQ6-<11,18> GNT6-<11>
PCIRST-2<11,13,21,31,34>
IDECLK<3>
1K
PPDIAGN<30> SPDIAGN<30>
AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C_BE-0 C_BE-1 C_BE-2 C_BE-3
FRAME­IRDY­TRDY­DEVSEL­STOP­PAR
PIRQC-
IDECLK
PPDIAGN SPDIAGN
4
C2671uC279
0.1u
PCI
GND
181527344047647799110
GND
GND
1030436892
VCC
GND
GND
128 127 126 125
121 124 123
122
120
109
115 113 114
49 48 46 45 44 42 41 39 37 36 35 33 32 31 29 28 18 17 16 14 13 12 11
38 26 19
20 21 22 23 24 25
9 5 4 3 2
6
7
BAD0 BAD1 BAD2 BAD3 BAD4 BAD5 BAD6 BAD7 BAD8 BAD9 BAD10 BAD11 BAD12 BAD13 BAD14 BAD15 BAD16 BAD17 BAD18 BAD19 BAD20 BAD21 BAD22 BAD23 BAD24 BAD25 BAD26 BAD27 BAD28 BAD29 BAD30 BAD31
BCBE0# BCBE1# BCBE2# BCBE3#
IDSEL BFRAME# BIRDY# BTRDY# BDEVSEL# BSTOP# PAR
INTA# PCIREQ# PCIGNT#
RESET#
CLK
ECLK66
BFLHCS# PCBLID SCBLID
3
VCC3VCC3
TRACETRACE
C297
C302
VCC
VCC
VCC
VCC
GND
GND
GND
1u
0.1u
117
108
116
VCC
VCC
AVCC
VCCIK
PIDE1
PIDE2
GND
GND
AGND
GND
GNDIK
118
119
RAID_GND
U20
60
PBDSD0
62
PBDSD1
65
PBDSD2
70
PBDSD3
72
PBDSD4
74
PBDSD5
78
PBDSD6
80
PBDSD7
79
PBDSD8
75
PBDSD9
73
PBDSD10
71
PBDSD11
66
PBDSD12
63
PBDSD13
61
PBDSD14
59
PBDSD15
54
PBDSA0
55
PBDSA1
52
PBDSA2
53
PBCS0#
51
PBCS1#
57
DMACK0#
58
DMARQ0
56
DINT0
76
PIORD#
67
PIOWR#
69
PCHRDY#
89
SBDSD0
94
SBDSD1
96
SBDSD2
100
SBDSD3
102
SBDSD4
104
SBDSD5
106
SBDSD6
111
SBDSD7
112
SBDSD8
107
SBDSD9
105
SBDSD10
103
SBDSD11
101
SBDSD12
97
SBDSD13
95
SBDSD14
90
SBDSD15
84
SBDSA0
85
SBDSA1
82
SBDSA2
83
SBCS0#
81
SBCS1#
87
DMACK1#
88
DMARQ1
86
DINT1
93
SIORD#
98
SIOWR#
91
SCHRDY
50
DRVRSTN
PDC20265R
L6 0 _0805
PHD0 PHD1 PHD2 PHD3 PHD4 PHD5 PHD6 PHD7 PHD8 PHD9 PHD10 PHD11 PHD12 PHD13 PHD14 PHD15
PHDA0 PHDA1 PHDA2
PHCS0J PHCS1J PDMACKJ PDMARQ PINTRJ PHIORJ PHIOWJ PHIORDY
SHD0 SHD1 SHD2 SHD3 SHD4 SHD5 SHD6 SHD7 SHD8 SHD9 SHD10 SHD11 SHD12 SHD13 SHD14 SHD15
SHDA0 SHDA1 SHDA2
SHCS0J SHCS1J SDMACKJ SDMARQ SINTRJ SHIORJ SHIOWJ SHIORDY
DRVRSTJ
2
PHD[15..0]
PHDA[2..0]
PHCS0J <30> PHCS1J <30> PDMACKJ <30> PDMARQ <30> PINTRJ <30> PHIORJ <30> PHIOWJ <30> PHIORDY <30>
SHD[15..0]
SHDA[2..0]
SHCS0J <30> SHCS1J <30> SDMACKJ <30> SDMARQ <30> SINTRJ <30> SHIORJ <30> SHIOWJ <30> SHIORDY <30>
DRVRSTJ <30>
C248
10u
C258
0.1u
PHD[15..0] <30>
PHDA[2..0] <30>
SHD[15..0] <30>
SHDA[2..0] <30>
L7
0_0805
1
VCC
C242
RAID_GNDAD0
1u
A A
5
4
VCC
C300
C263
C238
C236
0.1u
0.1u
0.1u
3
C240
0.1u
0.1u
2
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR
IDE RAID
MS-6502
of
29 39Wednesday, March 21, 2001
1
0A
5
R403
R374
4.7K
R370
22
R405
33
R375
4.7K
R372
22
Class Code
1 : IDE 0 : RAID
VCC3
VCC3
33
IDE4
R_PHD7 R_PHD6 R_PHD5
R_PHD3 R_PHD2 R_PHD1 R_PHD0
RPDMARQ RPHIOWJ RPHIORJ
RPDMACKJ PIDEINT RPHDA1 RPHDA0 RPHCS0J
A C
AC
R_SHD7 R_SHD6 R_SHD5 R_SHD4 R_SHD3 R_SHD2 R_SHD1 R_SHD0
RSDMARQ RSHIOWJ RSHIORJ
RSDMACKJ SIDEINT RSHDA1 RSHDA0 RSHCS0J
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
D2x20-1:21-BL-ZBT
D21
1N4148-S-LL34
D20
1N4148-S-LL34
IDE3
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
D2x20-1:21-WH-SBT
R354 1K
SHDA2 SHDA1
DRVRSTJ
DRVRSTJ<29>
D D
PHIORDY
PHIORDY<29>
C C
B B
SHIORDY<29>
EXTERNAL BIOS ROM SIZE
PHDA2: PULL UP 1K TO VCC ULTRA66 MODE
SHDA2:PULL DOWN 1K
A A
DRVRSTJ
:SHDA1
PHDA2
1K PULL DOWNSHDA0
SHIORDY
R271 1K
RAIDLED<21,25>
VCC3=VCC6=VCC4FOR INTERNAL PCI CLOCK
R269 1K
5
4
R_PHD8 R_PHD9 R_PHD10 R_PHD11R_PHD4 R_PHD12 R_PHD13 R_PHD14 R_PHD15
PPDIAGN RPHDA2 RPHCS1J
R_SHD8 R_SHD9 R_SHD10 R_SHD11 R_SHD12 R_SHD13 R_SHD14 R_SHD15
SPDIAGN RSHDA2 RSHCS1J
R353
1K
1:Enable external 66M Clock 0:Disable
4
PPDIAGN <29>
SPDIAGN <29>
R358 1K
R361
Bios Size
1K
1 : 128KB 0 : 64KB
3
PHD14
7 8
PHD1
5 6
PHD15
3 4
PHD0
1 2
10
PHD10
7 8
PHD5
5 6
PHD11
3 4
PHD4
1 2
10
PHD8
7 8
PHD7
5 6
PHD9
3 4
PHD6
1 2
10
PHD2
1 2
PHD13
3 4
PHD3
5 6
PHD12
7 8
10
PHDA2 PHDA0 PHDA1
SHD0 SHD15 SHD1 SHD14
SHD4 SHD11 SHD5 SHD10
SHD6 SHD9 SHD7 SHD8
SHD2 SHD13 SHD3
SHDA0 SHDA2 SHDA1
PDMACKJ
SDMACKJ
PHD[15..0]<29>
SHD[15..0]<29>
RN85
1 2 3 4 5 6 7 8
10
RN82
1 2 3 4 5 6 7 8
10
RN112
1 2 3 4 5 6 7 8
22
RN116
1 2 3 4 5 6 7 8
10
RN128
1 2 3 4 5 6 7 8
10
RN132
1 2 3 4 5 6 7 8
10
RN120
1 2 3 4 5 6 7 8
10
RN86
1 2 3 4 5 6 7 8
10
R365
51 R368
51
PHD[15..0]
SHD[15..0]
PHDA[2..0]
SHDA[2..0]
PHCS1J
PHCS1J<29>
SHCS0J
SHCS0J<29>
RPHCS0J
SHIORJ
SHIORJ<29>
SHIOWJ
SHIOWJ<29>
PHIOWJ
PHIOWJ<29>
PHIORJ
PHIORJ<29>
SHCS1J
SHCS1J<29>
PDMACKJ<29>
SDMACKJ<29>
VCC3VCC3VCC3
PHDA[2..0]<29>
SHDA[2..0]<29>
3
RN114
RN126
RN130
RN119
R_PHD14 R_PHD1 R_PHD15 R_PHD0
R_PHD10 R_PHD5 R_PHD11 R_PHD4
R_PHD8 R_PHD7 R_PHD9 R_PHD6
R_PHD2 R_PHD13 R_PHD3 R_PHD12
RPHCS1J RPHDA2 RPHDA0 RPHDA1
RSHCS0J
RSHIORJ RSHIOWJ RPHIOWJ RPHIORJ
R_SHD0 R_SHD15 R_SHD1 R_SHD14
R_SHD4 R_SHD11 R_SHD5 R_SHD10
R_SHD6 R_SHD9 R_SHD7 R_SHD8
R_SHD2 R_SHD13 R_SHD3 R_SHD12SHD12
RSHCS1J RSHDA0 RSHDA2 RSHDA1
RPDMACKJ
RSDMACKJ
2
PHCS0J
2
1
PHDA0 PHDA1 PHCS0J PHCS1J
SHDA0
PINTRJ
PINTRJ<29>
SINTRJ<29>
PHCS0J <29>
PDMARQ
PDMARQ<29>
SDMARQ RSDMARQ
SDMARQ<29>
Title
Size Document Number Rev
Custom
Date: Sheet
IDE RAID CONNECTORS
RN81
1 2 3 4 5 6 7 8
1K
R363
82
C389 22p
R364
82
C393 22p
R377
22
C405 22p
R381
22
C402 22p
R_SHD3
1
R_SHD2
2
R_SHD1
3
R_SHD0
4
R_SHD7
6
R_SHD6
7
R_SHD5
8
R_SHD4
9
R_PHD3
1
R_PHD2
2
R_PHD1
3
R_PHD0
4
R_PHD7
6
R_PHD6
7
R_PHD5
8
R_PHD4
9
MICRO-STAR
MS-6502
1
RN124
1 2 3 4 6 7 8 9510
10K
RN123
1 2 3 4 6 7 8 9510
10K
R3511K
30 39Wednesday, March 21, 2001
VCC3
PIDEINT
R359 10K
SIDEINTSINTRJ
R360 10K
RPDMARQ
R376
5.6K
R382
5.6K
5
10
5
10
of
0A
8
7
6
5
4
3
2
1
3VDUAL
VCC
R57 62K
C95 0.1u
AD[31..0]
C70
0.1u
+
EC7 10u
1N4148-S-LL34
AD[31..0]<11,16,17,18,19,29,34,37>
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8
IRDY-<11,16,17,18,19,29>
TRDY-<11,16,17,18,19,29>
STOP-<11,16,17,18,19,29>
PIRQB-<15,16,17,18,19>
PERR-<16,17,18> SERR-<11,16,17,18,19>
PAR<11,16,17,18,19,29,37>
3VDUAL
AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C_BE-0 C_BE-1 C_BE-2 C_BE-3
FRAME­IRDY­TRDY­DEVSEL­STOP­PAR PIRQB­PERR­SERR-
REQ0­GNT0-
R47 62K
PCIRST-2 1AOLAUX PME-
R46 5.6K
R41 4.7K R40 4.7K R42 4.7K
C84
C55
0.1u
0.1u
C_BE-[3..0]
C_BE-[3..0]<11,16,17,18,19,29,37>
FRAME-<11,16,17,18,19,29>
DEVSEL-<11,16,17,18,19,29>
REQ0-<11,18> GNT0-<11>
3VDUAL
LANCLK<3>
PCIRST-2<11,13,21,29,34>
PME-<15,16,17,18,19>
D D
3VDUAL
C119
C82
0.1u
C87
0.1u
0.1u
3VDUAL
C93
C65
0.1u
0.1u
C C
D8
AD25
DIS_LAN<34>
3VDUAL
B B
R43 8.2K
A3A7E1K3N6P2G5G6H5H6H7H8J5J6J7J8J9
U11
G2
VIO
VCCPP1
VCCPP2
VCCPP3
N7
AD0
M7
AD1
P6
AD2
P5
AD3
N5
AD4
M5
AD5
P4
AD6
N4
AD7
P3
AD8
N3
AD9
N2
AD10
M1
AD11
M2
AD12
M3
AD13
L1
AD14
L2
AD15
K1
AD16
E3
AD17
D1
AD18
D2
AD19
D3
AD20
C1
AD21
B1
AD22
B2
AD23
B4
AD24
A5
AD25
B5
AD26
B6
AD27
C6
AD28
C7
AD29
A8
AD30
B8
AD31
M4
C/BE#0
L3
C/BE#1
F3
C/BE#2
C4
C/BE#3
F2
FRAME#
F1
IRDY#
G3
TRDY#
H3
DEVSEL#
H1
STOP#
J1
PAR
H2
INTA#
J2
PERR#
A2
SERR#
A4
IDSEL
C3
REQ#
J3
GNT#
C2
RST#
G1
CLK
B9
ISOLATE#
A9
ALRST#
A6
PME#
C5
CSTSCHG/WOL
C8
CLKRUN#
B10
SMBALRT#
A10
SMBCLK
C9
SMBDATA
VCCPP4
VSSPP1
B3E2M6
VCCPP5
VCCPP6
VSSPP2
VSSPP3
N1
VCC1
VCC2
VSSPP4
VSSPP5
VSSPP6
B7K2G14
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VSSPL1
VSSPL2
VSSPL3
VSSPL4
K12
N12
P8L8D4D5D6D7D8
VCC9
VCC10
J10
J11K4K5K6K7K8K9
VCC11
VCC12
VCC13
VCC14
VSS1
VSS2
VCC15
VSS3
VCC16
VSS4
VCC17
VSS5
K10
K11L4L5L9L10
VCC18
VCC19
VCC20
VCC21
VCC22
VSS6
VSS7
VSS8
VSS9
VSS10
D11E4E5E6E7E8E9
VCC23
VSS11
VCC24
VSS12
E10
VCC25
VSS13
A11
K13N8P12
E12
VCC26
VCCPT
VSS14
VSS15
VSS16
E11F4F5F6F7F8F9
VCCPL1
VCCPL2
VSS17
VSS18
G13
VCCPL3
VCCPL4
VSS19
VSS20
VSS21
VSS22
VSS23
F10
F11G7G8G9G10
P14
VSS24
NC9
VSS25
NC7
NC8
VSS26
VSS27
G11H9H10
NC3
NC4
NC5
NC6
FLA16/CLK25
FLA12/MCNTSM#
FLA10/MRING#
FLA8/IOCHRDY
FLA1/AUXPWR
FLA0/PCIMODE#
MDMCS/CFCS
VSS28
VSS29
VSS30
VSS31
H11L6L11
A1
A14D9D10G4H4J4P1
NC1
NC2
LINKLED
ACTLED
SPEEDLED
FLA15/EESK
FLA14/EEDO
FLA13/EEDI
FLA11/MINT
FLA9/MRST
FLA7/CLKEN
EECS
FLCS#/AEN
FLOE#
FLWE#
TEST
TEXEC
VREF
NC/CFCLK
RBIAS10
RBIAS100
VSS32
TDP
TDN
RDP
RDN
FLA6 FLA5 FLA4 FLA3 FLA2
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
TCK
TI
TO
X1 X2
INT-82550EL
A12 C11 B11
C13
C14
E13
E14
P9 M10 N10 P10 M11 M12 N13 P13 N14 M13 M14 L12 L13 L14 K14 J12 J13 J14 H12 H13 H14 G12 F12 F13 F14
P7 N9
M8 M9
A13 D13 D14 D12 B12
C12
L7
B14
B13
N11 P11
LINKLED ACTLED SPEEDLED
TDP
TDN
RDP
RDN
R55 3.3K
R54 3.3K
R39 150
R37 549
R38 619
LAN1_X1 LAN1_X2
3VDUAL
3VDUAL
U13
4 5
DO GND
3
DI
ORG
2
SK
CS
VCC
ATL-512x8-1us-SOIC8
LAN1_X1 LAN1_X2
NC
1
25M-18pf-HC49S-D
Y2
C101 22p
3VDUAL
R76
4.7K
6
7
8
3VDUAL
12
C100 22p
RDN
R36
121
RDP
A A
PLACE THESE RESISTORS AS CLOCE TO 82559 AS POSSIBLE
TDN RDP2
R20 100
TDP
8
7
C34
22p
T1
1 2 3
6 8 7
C68
22p
6
1:1-TX
16
TD+
TX+
15
TDC
CMT
14
TD-
TX-
11
RD+
RX+
9
RD-
RX-
10
RDC
RXC
123456
78
RN24
5
RDN2
TDN2
TDP2
75
4
J2B
27
9
G
10 11 12 13 14
Y
15 16 28
RJ45+USB+LEDx2-D20-BK
25 18
17
20
19 26
3
SPEEDLED
R27
270
R30
270
3VDUAL
LINKLED
ACTLED
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR
LAN 82550
MS-6502
2
31 39Wednesday, March 21, 2001
0A
of
1
5
D D
4
3
2
1
VCC VCC
C C
VCC3
123456
78
Q8
NPN-3904LT1-S-SOT23
RN22
NPN-3904LT1-S-SOT23
78 56 34 12
B
RN46
4.7K
1 2
3 4
5 6
7 8
GPO16
GPO16<20>
B B
GPO17
GPO17<20>
GPO18
GPO18<20>
GPO19
GPO19<20>
C
C
B
E
E
NPN-3904LT1-S-SOT23
C
B
E
NPN-3904LT1-S-SOT23
C
B
E
Q9
Q6
Q5
RN12
4.7K
Q3
NPN-3904LT1-S-SOT23
C
B
E
RN25 330
1 2
3 4
5 6
7 8
DDLED1
DDLED2
DDLED3
DDLED4
Q1
NPN-3904LT1-S-SOT23
C
B
E
J1
2 1
4 3
GN_RD-D-5V-CR-A
Q2
NPN-3904LT1-S-SOT23
C
B
E
DLED1
DLED2
DLED3
56
DLED4
78
Q4
NPN-3904LT1 -S-SOT23
C
B
E
RN15 330
1 2
3 4
5 6
7 8
4.7K
DDLED1 DDLED2 DDLED3 DDLED4
J3
2
2
4
4
6
6
8
8
10
10
DLED1
1
1
DLED2
3
3
DLED3
5
5
DLED4
7
7
D2x5-1:2
A A
Title
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet of
MICRO-STAR
Diagnostic LED
MS-6502
1
32 39Wednesday, March 21, 2001
0A
5
3VDUAL
D17
AC
1N5817-S-DO-241AC
VCC3
Q57
D D
EC55
+
1000u/6.3V
C C
B B
A A
N-IPD20N03L-S-TO252
R388 4.7
C415
0.1u
R380
4.7K
D S
G
C418
0.1u
MOS_SW
B
Q56
NPN-3904LT1-S-SOT23
PWRGD <25>
5
MOS_SW
C421
0.1u
+12V
C
E
R379
4.7K
VCC2_5
R397
15K
R396
10K
VCC
G
D S
DS
G
Q49
SI2303DS-S-SOT23
5VSB
1
VCC1
16
VCC2
2
PVDD1
15
PVDD2
4
PGND1
13
PGND2
5
AGND1
8
AGND2
9
AGND3
12
AGND4
C427
0.1u
Q54
IPD12N03L-S-TO252
D13 1N5817-S-DO-241AC
A C
5VDUAL
B
+
EC50
U30
VL1
VL2
VIN/2
VCCQ
SD
FB
CM8500
R394
1K
C
E
VCC2_5
Q59
NPN-3904LT1-S-SOT23
5VDUAL
+
C382
1000u/6.3V
0.1u
4
REG_OUT
3
14
VCC2_5
7
10
6
11
R352
1K
C392
R350
0.1u
1K
VR3
US1050CD-TO252-5A
1 3
VIN VOUT
10u
ADJ
2
EC16
4
3
DDR Regulator & STR LDO
VTT_DDR
CHOCK1
3.3u
C359
0.1u
C423
1000p
DDR_VREF
C398
0.1u
place near DIMM1
5A
50 MILS TRACE
R52 200
R48 332
C79
0.1u
1000u/6.3V
R395
100K
SUSC-<19,25>
3VDUAL
+
EC56
EC14 1000u/6.3V
+
+
EC58 1000u/6.3V
R398
1K
+
EC57 1000u/6.3V
R357
10K
C94 105P-REV
3
C467
0.1u
5VDUAL
B
NPN-3904LT1-S-SOT23
C86 105P-REV
R355
1K
C
B
E
C
E
Q53
C71 1u
R346 15K
R345
82K Q52 NPN-3904LT1-S-SOT23
C72 1u
4700p
C383
EN
C384
2
SUSB# SUSC#
STD
0
STR
0
Normal
1
5VDUAL 5VDUAL5VDUAL
AC
L10
C380
4.7u-1206
U29
5
7
COMP
12p
2
BOOT
VCC
UGATE PHASE
LGATEFB
GND
3
INTS-ISL6520-SOIC8
1
Q55
2
G 8
IPD12N03L-S-TO252
46
IPD12N03L-S-TO252
Title
Size Document Number Rev
Date: Sheet
1.2u
Q51
Custom
D14 1N4148-S-LL34
C400
DS
1u
C387
0.1u
L9 3.3u
EC48
1000u/6.3V
DDR Regulator & STR LDO
1
0
1
1
EC53
EC54
+
+
1000u/6.3V
1000u/6.3V
EC49
EC46
+
+
+
1000u/6.3V
1000u/6.3V
MICRO-STAR
MS-6502
1
VCC2_5
33 39Thursday, March 22, 2001
2.5V/11A
R343
2.2K
R344
1K
of
0A
5
BIOS TUNE CPU RATO CIRCUIT
VCC
U2
20
VDD
Reserved
3 4
5 6
P1_VID2 P1_VID3 P1_VID1 P1_VID0
P1_VID4
RN2
10K
7 8
1
SCL
2
SDA
19
RST#
3
A0/GP20
4
A1/GP21
5
A2/GP22
GPIO-WB-W83601R-SSOP20
P0_VID[0..4]
P1_VID[0..4]
RN5
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9
9510
10K
SMBCLK<3,13,14,19,20>
D D
PCIRST-2<11,13,21,29,31>
BIOS TUNE CPU VCORE CIRCUIT
P0_VID2 P0_VID3 P0_VID1
C C
P0_VID0 P0_VID4
SMBDATA<3,13,14,19,20>
PCIRST-2
R2 0
VID_SET
1 2
P0_VID[0..4]<4>
P1_VID[0..4]<6>
VCC2_5P VCC2_5P VCC3
RN10
1
5
1
2
2
3
3
4
4
6
6
7
7
8
8
9
10
9510
10K
BIOS TUNE CPU RATO CIRCUIT
VCC
4
7
9
12
PCIRST-2
FP_RST­P0_FID_SET
P1_FID_SET
VCC
P0BP0
P0BP1
P0BP2
P0BP3
SMBCLK<3,13,14,19,20>
SMBDATA<3,13,14,19,20>
Reserved
R6 0
1 2
3 4
5 6
7 8
RN17
1 2 3 4 5 6 7 8
10K
RN8
10K
B B
PCIRST-2<11,13,21,29,31>
FP_RST
VCC2_5P VCC2_5P
P0_FID0
P0_FREQ0
P0_FID1
P0_FREQ1
P0_FID2
P0_FREQ2
P0_FID3
P0_FREQ3
A A
P0_FID_SET
U6
2
1A
3
1B
5
2A
6
2B
11
3A
10
3B
14
4A
13
4B
1
A/B
15
G
74LCX157-SOIC16
5
1Y
2Y
3Y
4Y
4
6
GP10
7
GP11
13
GP12
14
GP13
15
GP14
16
GP15
17
GP16
18
GP17
8
GP23
9
GP24
11
GP25
12
GP26
5
10
U3
20
VDD
GP10 GP11
1
SCL
GP12
2
SDA
GP13 GP14 GP15
19
RST#
GP16 GP17
3
A0/GP20
GP23
4
A1/GP21
GP24
5
A2/GP22
GP25 GP26
GPIO-WB-W83601R-SSOP20
AD0 AD1 AD2 AD3
4
VID_SEL LOW: P0_FID HIGH: FREQ
UVID0 UVID1 UVID2 UVID3 UVID4 DIS_IDE
DIS_IDE <29>
100/133-
100/133- <3,37>
DIS_LAN
DIS_LAN <31>
VID_SET
VID_SEL LOW: P0_FID HIGH: FREQ
P0_FREQ0
6
P0_FREQ1
7
P0_FREQ2
13
P0_FREQ3
14
P1_FREQ0
15
P1_FREQ1
16
P1_FREQ2
17
P1_FREQ3
18 8 9 11 12
P1_FID0
P1_FREQ0
P1_FID1 P1BP2
P1_FREQ1
P1_FID2
P1_FREQ2
P1_FID3
P1_FREQ3
P1_FID_SET
U1
2
1A
3
1B
5
2A
6
2B
11
3A
10
3B
14
4A
13
4B
1
A/B
15
G
74LCX157-SOIC16
4
1Y
7
2Y
9
3Y
12
4Y
1 2 3 4 5 6 7 8
P1BP0 P1BP1
P1BP3
3
P0_VID0
UVID0
P0_VID1
UVID1
P0_VID2
UVID2
P0_VID3
UVID3
VID_SET
RN14
10K
1 2 3 4 5 6 7 8
3
APICD0-<4,6> APICD1-<4,6> APICCLK<4,6>
RN1
10K
P0_FID[0..3] P1_FID[0..3]
P0_FID[0..3] <4> P1_FID[0..3] <6>
P0BP[0..3]
P0BP[0..3] <5>
AD[0..3] AD[16..19]
VCC3
U7
2
1A
1Y
3
1B
5
2A
2Y
6
2B
11
3A
3Y
10
3B
14
4A
4Y
13
4B
1
A/B
15
G
74LCX157-SOIC16
Q7
NPN-3904LT1-S-SOT23
C
B
E
Q12
NPN-3904LT1-S-SOT23
C
B
E
AD16 AD17 AD18 AD19
AD[0..3] <11,16,17,18,19,29,31> AD[16..19] <11,16,17,18,19,29,31>
R_VID0
4
R_VID1
7
R_VID2
9
R_VID3
12
VCC3
R65 10K
R_VID4
UVID4
NPN-3904LT1-S-SOT23
R_VID4 <35>
Q13
C
B
E
P0_VID4
U27
1
GND
GATE
2
A1
B1
3
A2
B2
4
A3
B3
5
A4
B4
6
A5
B5
7
A6
B6
8
A7
B7
9
A8
B8
10
A9
B9
11
A10
B10
12 13
A11 B11
JACK+RCA-D9-RWY
R_VID0 <35>
R_VID1 <35>
R_VID2 <35>
R_VID3 <35>
24 23 22 21 20 19 18 17 16 15 14
VREF2.5<15>
2
C370 0.1u
R320 200K
2
1
P1BP[0..3]
P1BP[0..3] <7>
P0_FID2 P0_FID3 P0_FID0 P0_FID1 P1_FID2 P1_FID3 P1_FID0 P1_FID1
P0_FREQ0 P0_FREQ1 P0_FREQ2 P0_FREQ3 P1_FREQ0 P1_FREQ1 P1_FREQ2 P1_FREQ3
UVID0 UVID1 UVID2
VCCVCC2_5P
PAPICD0- <19> PAPICD1- <19> PAPICCLK <3>
UVID3 UVID4 DIS_LAN DIS_IDE
* 25 mils Trace/ 12 mils Space
VCC3
D
Q22
5
+
7
6
-
U16B NS-LM358MX-SOIC8
8 4
+12V
Max 150mA, Design for 100mA
Title
Size Document Number Rev Custom
Date: Sheet of
2N7002-S-SOT23
G
S
R131
1K
MICRO-STAR
MS-6502
VCORE AJUST
C146
0.1u
1
2 1
RN3
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9510
9510
10K
RN9
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9510
9510
10K
RN4
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9510
9510
10K
C35
0.1u
2 1
34 39Wednesday, March 21, 2001
VCC2_5P
VCC2_5P
EC12
+
10u
VCC3
VCC3
0A
5
4
3
2
1
Voltage Regular Module
All N-Channel MOSFET use TO-252
VCC
+12V
D D
C107
1u
U12 INTS-HIP6301-SOIC20
1
R_VID4<34> R_VID3<34> R_VID2<34> R_VID1<34> R_VID0<34>
R87
L1
VCC
C C
+12V 12V_VIN
B B
EC17
+
EC36
+
EC20
1.2u
+
3900u
100u
L8
EC26
1.2u
+
1500u
100u
EC24
+
3900u
EC33
+
1500u
5V_VIN
154K
5.6K
R70
C121
47p
NOPOP
0.01u
C118
R71 100K
VID4
2
VID3
3
VID2
4
VID1
5
VID0
8
FS/DIS
6
COMP
7
FB
10
VSEN
2K
R74
NOPOP
20
VCC
19
PGOOD
15
PWM1
14
PWM2
11
PWM3
18
PWM4
16
ISEN1
13
ISEN2
12
ISEN3
17
ISEN4
GND
9
R79
C123
NOPOP
R238 10
C241
1u
+12V
R80 10
C130
1u
+12V 12V_VIN
R254 10
C269
1u
+12V
R142 10
C163
1u
C237
1u
U19
2
BOOT
UGATE
7
PVCC
PHASE
6
VCC
3
PWM
LGATEGND
MOSDVR-INTS-HIP6601A-SOIC8
3K
R72
C120
1u
U14
2
BOOT
UGATE
7
PVCC
PHASE
6
VCC
3
PWM
LGATEGND
MOSDVR-INTS-HIP6601A-SOIC8
R86 3K
C268
1u
U21
2
BOOT
UGATE
7
PVCC
PHASE
6
VCC
3
PWM
LGATEGND
MOSDVR-INTS-HIP6601A-SOIC8
R93 3K
C156
1u
U15
2
BOOT
UGATE
7
PVCC
PHASE
6
VCC
3
PWM
LGATEGND
MOSDVR-INTS-HIP6601A-SOIC8
R69 3K
1 8
R228 0
54
R152 0
1 8
R186 0
54
R226 0
1 8
R240 0
54
R179 0
1 8
R178 0
54
R211 0
5V_VIN
DS
DS
UG1
G
IPD12N03L-S-TO252
LG1
G
Q45
IPD12N03L-S-TO252
UG2
G
IPD12N03L-S-TO252
LG2 LG2
G
Q31
IPD12N03L-S-TO252
UG3
G
N-IPD20N03L-S-TO252
LG3
G
Q47
N-IPD07N03L-S-TO252
UG4 UG4
G
N-IPD20N03L-S-TO252
LG4
G
Q35
N-IPD07N03L-S-TO252
Q38
5V_VIN
Q24
Q43
12V_VIN
Q36
DS
DS
DS
DS
DS
DS
DS
Q37
DS
IPD12N03L-S-TO252
Q44 IPD12N03L-S-TO252
DS
Q25
DS
IPD12N03L-S-TO252
Q32 IPD12N03L-S-TO252
DS
Q42
DS
N-IPD20N03L-S-TO252
Q46 N-IPD07N03L-S-TO252
DS
Q30
DS
N-IPD20N03L-S-TO252
Q29 N-IPD07N03L-S-TO252
C200
C199
1u
1u
UG1
G
LG1
G
C139
1u
UG2
G
G
C214
1u
UG3
G
LG3
G
C208
1u
G
LG4
G
C212
1u
C138
1u
C196
1u
L4
0.5u
DUAL K7
1.1V~1.85V/80A
L3
0.5u
EC27
EC30
+
+
4700u
4700u
L5
0.5u
EC19
EC47
+
+
4700u
4700u
L2
0.5u
R94
1K
EC28
+
4700u
EC22
+
4700u
EC31
+
4700u
EC8
+
4700u
VCORE
VCORE
VID4 VID3 VID2 VID1 VID0 VDC(V)
1 0 1 1 0 1.30
1 0 0 0 1 1.425
1 0 0 0 0 1.45
0 1 1 1 1 1.475
0 1 1 1 0 1.500
0 1 1 0 1 1.525
0 1 1 0 0 1.550
A A
0 1 0 1 1 1.575
0 1 0 1 0 1.600
0 1 0 0 1 1.625
0 1 0 0 0 1.650
0 0 1 1 1 1.675
0 0 1 1 0 1.700
5
VID4 VID3 VID2 VID1 VID0 VDC(V)
0 0 1 1 0 1.70
0 0 1 0 1 1.725
0 0 1 0 0 1.75
0 0 0 1 1 1.775
0 0 0 1 0 1.80
0 0 0 0 1 1.825
0 0 0 0 0 1.85
1 1 1 1 1 NO CPU
Design for 45A @+/- 100 mV
4
R88 0
R68 0
P0_COREFB <4>
P1_COREFB <6>
P1_COREFB- <6>
P0_COREFB- <4>
VCORE
VCORE
3
C166
106P
C287
106P
C177
C317
106P
106P
Place under CPU0
C149
C176
C135
106P
106P
106P
Place under CPU1
C323
C324
C286
106P
106P
106P
C136
106P
C298
106P
C150
106P
C315
106P
C171
106P
C296
106P
R98
5.1K
Title
Size Document Number Rev
Custom
2
Date: Sheet of
MICRO-STAR
MS-6341
VRM
1
35 39Thursday, March 22, 2001
0F
5
RN8822
7 8 5 6 3 4 1 2
RN8922
7 8 5 6 3 4 1 2
RN9022
7 8 5 6 3 4 1 2
RN9122
7 8 5 6 3 4 1 2
RN9222
7 8 5 6 3 4 1 2
RN9322
7 8 5 6 3 4 1 2
RN9522
7 8 5 6 3 4 1 2
RN9622
7 8 5 6 3 4 1 2
RN9722
7 8 5 6 3 4 1 2
RN9822
7 8 5 6 3 4 1 2
RN9922
7 8 5 6 3 4 1 2
RN10022
7 8 5 6 3 4 1 2
RN10122
7 8 5 6 3 4 1 2
RN10222
7 8 5 6 3 4 1 2
RN10322
7 8 5 6 3 4 1 2
RN10422
7 8 5 6 3 4 1 2
R35622
R43022
R43122
R43222
R429220 R330220
MDAT_SR1 MDAT_SR5 MDAT_SR0 MDAT_SR4
MDAT_SR6 MDAT_SR2 DQS_SR0 DM_SR0
MDAT_SR12 MDAT_SR8 MDAT_SR3 MDAT_SR7
DM_SR1 DQS_SR1 MDAT_SR13 MDAT_SR9
MDAT_SR11 MDAT_SR10 MDAT_SR15 MDAT_SR14
MDAT_SR21 MDAT_SR17 MDAT_SR16 MDAT_SR20
MDAT_SR22 MDAT_SR18 DM_SR2 DQS_SR2
MDAT_SR28 MDAT_SR24 MDAT_SR23 MDAT_SR19
DM_SR3 DQS_SR3 MDAT_SR29 MDAT_SR25
MDAT_SR31 MDAT_SR27 MDAT_SR26 MDAT_SR30
MECC_SR1 MECC_SR0 MECC_SR5 MECC_SR4
MECC_SR2 MECC_SR6 DM_SR8 DQS_SR8
MDAT_SR33 MDAT_SR37 MDAT_SR36 MDAT_SR32
MDAT_SR34 MDAT_SR38 DM_SR4 DQS_SR4
MDAT_SR44 MDAT_SR40 MDAT_SR35 MDAT_SR39
DQS_SR5 DM_SR5 MDAT_SR41 MDAT_SR45
MECC_SR3
MECC_SR7
CS-_SR7CS-7
CLKOUT-_SRB2CLKOUT_SRB2
5
MDAT1 MDAT5 MDAT0 MDAT4
MDAT6 MDAT2 DQS0 DM0
D D
MDAT12 MDAT8 MDAT3 MDAT7
DM1 DQS1 MDAT13 MDAT9
MDAT11 MDAT10 MDAT15 MDAT14
MDAT21 MDAT17 MDAT16 MDAT20
MDAT22 MDAT18 DM2 DQS2
C C
MDAT28 MDAT24 MDAT23 MDAT19
DM3 DQS3 MDAT29 MDAT25
MDAT31 MDAT27 MDAT26 MDAT30
MECC1 MECC0 MECC5 MECC4
MECC2 MECC6 DM8 DQS8
B B
MDAT33 MDAT37 MDAT36 MDAT32
MDAT34 MDAT38 DM4 DQS4
MDAT44 MDAT40 MDAT35 MDAT39
DQS5 DM5 MDAT41 MDAT45
MECC3
MECC7
CS-6 CS-_SR6
A A
RN15010
CKEA CKEB MAB12 MAA12
MAA9 MAB9 MAA11 MAB11
MAB7 MAA7 MAA8 MAB8
MAB5 MAA5 MAA6 MAB6
MDAT47 MDAT46 MDAT43 MDAT42
MDAT49 MDAT52 MDAT53 MDAT48
MAB3 MAA4 MAB4 MAA3
MAB2 MAA2 MAB1 MAA1
MAA0 MAA10 MAB0 MAB10
MAB14 MAB_SR14 MAA14 MAB13 MAA13
MDAT50 DQS6 MDAT54 DM6
MDAT56 MDAT61 MDAT51 MDAT55
DQS7 DM7 MDAT57 MDAT60
MDAT59 MDAT63 MDAT58 MDAT62
RASB­RASA­WEB­WEA-
CS-4 CS-1CS-_SR4
CASA­CS-0
CLKOUT0 CLKOUT_SR0 CLKOUT1
CLKOUT4
CLKOUT-1 CLKOUT-4 CLKOUT-3
CLKOUT_SR0 CLKOUT_SR1 CLKOUT_SR2 CLKOUT-_SR2 CLKOUT_SR3 CLKOUT_SR4 CLKOUT_SR5 CLKOUT-_SR5
CKEA_SR
7 8
CKEB_SR
5 6
MAB_SR12
3 4
MAA_SR12
1 2
RN9410
MAA_SR9
7 8
MAB_SR9
5 6
MAA_SR11
3 4
MAB_SR11
1 2
RN15110
MAB_SR7
7 8
MAA_SR7
5 6
MAA_SR8
3 4
MAB_SR8
1 2
RN15210
MAB_SR5
7 8
MAA_SR5
5 6
MAA_SR6
3 4
MAB_SR6
1 2
RN10522
MDAT_SR47
7 8
MDAT_SR46
5 6
MDAT_SR43
3 4
MDAT_SR42
1 2
RN8722
MDAT_SR49
7 8
MDAT_SR52
5 6
MDAT_SR53
3 4
MDAT_SR48
1 2
RN15310
MAB_SR3
7 8
MAA_SR4
5 6
MAB_SR4
3 4
MAA_SR3
1 2
RN15410
MAB_SR2
7 8
MAA_SR2
5 6
MAB_SR1
3 4
MAA_SR1
1 2
RN15510
MAA_SR0
7 8
MAA_SR10
5 6
MAB_SR0
3 4
MAB_SR10
1 2
RN15610
7 8
MAA_SR14
5 6
MAB_SR13
3 4
MAA_SR13
1 2
RN10622
MDAT_SR50
7 8
DQS_SR6
5 6
MDAT_SR54
3 4
DM_SR6
1 2
RN10722
MDAT_SR56
7 8
MDAT_SR61
5 6
MDAT_SR51
3 4
MDAT_SR55
1 2
RN10822
DQS_SR7
7 8
DM_SR7
5 6
MDAT_SR57
3 4
MDAT_SR60
1 2
RN10922
MDAT_SR59
7 8
MDAT_SR63
5 6
MDAT_SR58
3 4
MDAT_SR62
1 2
RN15710
RASB-_SR
7 8
RASA-_SR
5 6
WEB-_SR
3 4
WEA-_SR
1 2
RN15822
7 8 5 6
CASA-_SR
3 4
CS-_SR0
1 2
R41833 R41533 R32233 R42033
CLKOUT_SR3CLKOUT3
R41733
CLKOUT_SR4
R41933
CLKOUT-_SR0CLKOUT-0
R41633
CLKOUT-_SR1
R41233
CLKOUT-_SR4
R42133
CLKOUT-_SR3
R427120 R424120 R329220 R428120 R425120 R426220
MDAT_SR1 MDAT_SR5 MDAT_SR0 MDAT_SR4
DQS_SR0 DM_SR0 MDAT_SR2 MDAT_SR6
MDAT_SR12 MDAT_SR8 MDAT_SR3 MDAT_SR7
MDAT_SR9 DQS_SR1 MDAT_SR13 DM_SR1
CKEB_SR MDAT_SR10 MDAT_SR15 MDAT_SR14
CKEA_SR MDAT_SR11 MDAT_SR20 MAB_SR12
MDAT_SR21 MDAT_SR17 MAA_SR12 MDAT_SR16
DQS_SR2 MAA_SR11 MAB_SR11 MAA_SR9
MAB_SR7 MDAT_SR18 DM_SR2 MAB_SR9
MAA_SR7 MDAT_SR22 MAB_SR8 MAA_SR8
MDAT_SR24 MAB_SR5 MDAT_SR23 MDAT_SR19
MAA_SR5 MAB_SR6 MAA_SR6 MDAT_SR28
MAB_SR3 MAB_SR4 DQS_SR3 MDAT_SR25
MDAT_SR29 DM_SR3 MAA_SR4 MAA_SR3
MDAT_SR31 MDAT_SR27 MDAT_SR26 MDAT_SR30
CLKOUT-_SR0 CLKOUT-_SR1
CLKOUT-_SR3 CLKOUT-_SR4
4
RN133 27
RN160 27
RN134 27
RN161 27
RN135 27
RN162 27
RN136 27
RN163 27
RN137 27
RN164 27
RN138 27
RN165 27
RN139 27
RN166 27
RN140 27
CS-_SR1
CS-_SR2CASB-_SR
CS-_SR3 CS-_SR5
R42233
R32333 R42333
R41433 R32533
R41333 R32433
MAB_SR2 MAA_SR2 MECC_SR4 MECC_SR5
MECC_SR1 MECC_SR0 MAA_SR1 MAB_SR1
DQS_SR8 DM_SR8 MAB_SR0 MAB_SR10
MAB_SR14 MAA_SR14 MAA_SR10 MAA_SR0
MECC_SR2 MECC_SR6 MECC_SR3 MECC_SR7
MDAT_SR33 MDAT_SR37 MDAT_SR36 MDAT_SR32
DQS_SR4 MDAT_SR34 DM_SR4 MDAT_SR38
RASB-_SR MDAT_SR44 MDAT_SR40 MAB_SR13
MDAT_SR39 MAA_SR13 MDAT_SR35 RASA-_SR
CS-_SR0 MDAT_SR41 WEB-_SR MDAT_SR45
CASA-_SR CS-_SR6 CS-_SR7 CS-_SR3
MDAT_SR46 MDAT_SR43 CS-_SR1 CS-_SR2
DM_SR5 DQS_SR5 MDAT_SR47 MDAT_SR42
MDAT_SR53 MDAT_SR49 MDAT_SR52 MDAT_SR48
MDAT_SR61 MDAT_SR60 DQS_SR6 DM_SR6
MDAT_SR54 MDAT_SR55 MDAT_SR50 MDAT_SR51
MDAT_SR63 MDAT_SR58 MDAT_SR62 MDAT_SR57
MDAT_SR56 DM_SR7 DQS_SR7 MDAT_SR59
WEA-_SR CS-_SR4 CS-_SR5 CASB-_SR
CLKOUT_SR2CLKOUT_SR1 CLKOUT_SRB2
CLKOUT-_SR2 CLKOUT-_SRB2
CLKOUT_SR5 CLKOUT_SRB5
CLKOUT-_SR5 CLKOUT-_SRB5CLKOUT-_SRB5CLKOUT_SRB5
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
RN15922
7 8
CS-2CASB-
5 6
CS-3
3 4
CS-5
1 2
CLKOUT2
CLKOUT-2
CLKOUT5
CLKOUT-5
4
RN167 27
RN141 27
RN168 27
RN142 27
RN169 27
RN143 27
RN170 27
RN144 27
RN171 27
RN145 27
RN173 27
RN146 27
RN174 27
RN147 27
RN148 27
RN175 27
RN149 27
RN176 27
RN172 27
CLKOUT0 CLKOUT-0 CLKOUT1 CLKOUT-1
CLKOUT2 CLKOUT-2 CLKOUT3 CLKOUT-3
CLKOUT4 CLKOUT-4 CLKOUT5 CLKOUT-5
3
3
VCC2_5VTT_DDRVTT_DDR
0.1u
0.1u C558
0.1u C562
0.1u C466
0.1u C464
0.1u C462
0.1u C459
0.1u C457
0.1u C455
0.1u C453
0.1u C554
0.1u C461
0.1u C550
0.1u C451
0.1u C449
0.1u C447
0.1u C444
0.1u C442
0.1u C439
0.1u C441
0.1u C437
0.1u C435
0.1u C433
0.1u C546
0.1u C548
0.1u C556
0.1u C560
VCC2_5
0.01u C512
0.01u C531
0.01u C362
0.01u C356
0.01u C509
RJ7S_160-REV RJ8S_160-REV RJ3S_160-REV RJ4S_160-REV
RJ11S_160-REV RJ12S_160-REV RJ9S_160-REV RJ10S_160-REV
RJ5S_160-REV RJ6S_160-REV RJ2S_160-REV RJ1S_160-REV
VCC2_5
C552
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
VTT_DDR
RASA-_SR CASA-_SR WEA-_SR CKEA_SR
RASB-_SR CASB-_SR WEB-_SR CKEB_SR
RASA­CASA­WEA­CKEA
CLKOUT[0..5]<10>
CLKOUT-[0..5]<10>
C468
C431
MECC[0..7]<10>
MAA[0..14]<10>
MAB[0..14]<10>
CS-[0..7]<10>
MDAT[0..63]<10>
DQS[0..8]<10>
VTT_DDR
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
RASA-_SR <13,14> CASA-_SR <13,14> WEA-_SR <13,14> CKEA_SR <13,14>
RASB-_SR <13,14> CASB-_SR <13,14> WEB-_SR <13,14> CKEB_SR <13,14>
RASA- <10> CASA- <10> WEA- <10> CKEA <10>
DM[0..8]<10>
RASB-<10> CASB-<10>
WEB-<10> CKEB<10>
0.1u C553
0.1u C465
0.1u C463
0.1u C460
0.1u C458
0.1u C456
0.1u C563
0.1u C454
0.1u C445
0.1u C555
0.1u C452
0.1u C549
0.1u C557
0.1u C446
0.1u C559
0.1u C448
0.1u C443
0.1u C440
0.1u C438
0.1u C547
0.1u C436
0.1u C434
0.1u C561
0.1u C551
0.1u C450
0.1u C545
0.1u C432
4.7u-1206
4.7u-1206
Place 475P MLCC cap.on the either end of VTT plane
RASB-
CASB-
WEB­CKEB
2
MAA_SR0 MAA_SR1 MAA_SR2 MAA_SR3 MAA_SR4 MAA_SR5 MAA_SR6 MAA_SR7 MAA_SR8 MAA_SR9 MAA_SR10 MAA_SR11 MAA_SR12 MAA_SR13 MAA_SR14
MAB_SR0 MAB_SR1 MAB_SR2 MAB_SR3 MAB_SR4 MAB_SR5 MAB_SR6 MAB_SR7 MAB_SR8 MAB_SR9 MAB_SR10 MAB_SR11 MAB_SR12 MAB_SR13 MAB_SR14
MECC_SR0 MECC_SR1 MECC_SR2 MECC_SR3 MECC_SR4 MECC_SR5 MECC_SR6 MECC_SR7
DM_SR0 DM_SR1 DM_SR2 DM_SR3 DM_SR4 DM_SR5 DM_SR6 DM_SR7 DM_SR8
DQS_SR0 DQS_SR1 DQS_SR2 DQS_SR3 DQS_SR4 DQS_SR5 DQS_SR6 DQS_SR7 DQS_SR8
MAA_SR[0..14] <13,14>
MAB_SR[0..14] <13,14>
MECC_SR[0..7] <13,14>
DM_SR[0..8] <13,14>
DQS_SR[0..8] <13,14>
CS-_SR0 CS-_SR1 CS-_SR2 CS-_SR3 CS-_SR4 CS-_SR5 CS-_SR6 CS-_SR7
CLKOUT_SR0 CLKOUT_SR1 CLKOUT_SR2 CLKOUT_SR3 CLKOUT_SR4 CLKOUT_SR5
CLKOUT-_SR0 CLKOUT-_SR1 CLKOUT-_SR2 CLKOUT-_SR3 CLKOUT-_SR4 CLKOUT-_SR5
CLKOUT_SRB2<14>
CLKOUT-_SRB2<14>
CLKOUT_SRB5<14>
CLKOUT-_SRB5<14>
Title
Size Document Number Rev
Custom
2
Date: Sheet of
1
MDAT_SR[0..63]<13,14>
CS-_SR[0..7] <13,14>
CLKOUT_SR[0..5] <13>
CLKOUT-_SR[0..5] <13>
CLKOUT_SRB2
CLKOUT-_SRB2
CLKOUT_SRB5
CLKOUT-_SRB5
MICRO-STAR
DDR Termination
MS-6502
1
MDAT_SR0 MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
36 39Wednesday, March 21, 2001
0A
5
AD[0..31]
AD[0..31]<11,16,17,18,19,29,31,34>
C_BE-[0..3]<11,16,17,18,19,29,31>
D D
10K-REV
C_BE-0 C_BE-1 AD11 C_BE-2 C_BE-3
C C
AD31
B B
AD30
R99 10K-REV
AD29
A A
AD28
R100
10K
VCC3
R210
R182
R149 10K
10K
R150
R181
R209
10K
10K
10K
VCC3
R91
1K
R92
8.2K
C
B
E
Q10 NPN-3904LT1-S-SOT23
VCC3
R82
R83
1K
C
8.2K
B
E
Q11 NPN-3904LT1-S-SOT23
VCC3
AD[29] Disable Divider
R106
LOW - disable large skew accomodation mode HIGH - enable large skew accomodation mode
10K
AD[28] SysClk Threshold
LOW - Senses input thresholds between 0.6V and 1.0V. HIGH - Senses input thresholds between 1.0V and 1.4V.
R107
10K
5
C_BE-[0..3]
C_BE3# - K7_PP_Enable
R127
Enables/Disables K7 push-pull drivers
10K
C_BE2# - IG_PP_Enable
Enables/Disables IGD4 push-pull drivers
C_BE1# - PLL BYPASS ENABLE
LOW - Disable
R128
C_BE0# - M66ADV
LOW - Diable HIGH - Enable
10K
AD[31:30] CLK SPEED
L L ---> 100 Mhz (DEFAULT)
L H ---> 66 Mhz
H L ---> RESERVED
H H ---> 133 MHz
R45
10K
R44
10K
100/133- <3,34>
4
AD[11:10] CPU0 Physical S2K Bus Length
00 - Short non-slotA 01 - Single Slot A or "close" 10 - Far dual Slot A 11 - Farthest possible Slot A
AD[27:26] CPU1 Physical S2K Bus Length AD[27:26]
00 - Short non-slotA 01 - Single Slot A or "close" 10 - Far dual Slot A 11 - Farthest possible Slot A
VCC3
R199
R203
R115
10K-REV
10K-REV
10K
AD10 AD27 AD26
R198
VCC3
R126
R111
R133
10K
10K
10K
NOPOP
R138 10K
NOPOP
R125
R132
10K
10K
VCC3
R144
10K
R145
R139
10K
10K
NOPOP
PAR<11,16,17,18,19,29,31>
AD25 AD24 AD23
R110
10K
AD22 AD21
4
R116
10K
10K
R202 10K
AD[25] TRISTATE_ENABLE
Enables board test mode when TEST# is asserted
AD[24] INCLK_DELAY_ENABLE
Enables IGD4 INCLK delay
AD[23] NAND_TREE_ENABLE
Enables NAND tree test mode when TEST# is asserted
AD[22:21] IGD4 INPUT HYSTERISIS OF OUTCLKS
0b00 - No Hysteresis
0b01 - Low hysteresis
0b10 - Medium Hysteresis
0b11 - Max. Hysteresis
VCC3
R176
10K
PAR
R175
10K
3
R105 10K
NOPOP
R104
10K
AD14 AD13 AD12
R183
10K
A pullup on PAR will put IGD4 into clock test mode when TEST# is low
3
R184
10K
AD15
R185
10K
VCC3
10K-REV
AD20
R190
10K
R189
R195
10K
R194
10K-REV
2
AD[15] 66MHz PCI
LOW -> Disable 66MHz PCI Mode HIGH -> Enable 66MHz PCI Mode
AD[14:12] AGP CLock Mux[2:0]
Selects input APLL clock mux for PLL test mode. Refer to Ch. 11 of IGD4 Differences Document
VCC3
5VSB
R147
4.7K
R148
4.7K
U10D
7407-SOIC14
2
1
VCC3 VCC3
R216
R214 R207 10K-REV
AD9 AD8 AD7
R206
10K
98
TYPEDET- <15>
Title
Size Document Number Rev
Custom
Date: Sheet of
10K-REV
10K
R213
R215
10K-REV
10K
AD[9] Bypass_PLLs
Enables PLL bypass mode when TEST# is asserted.
AD[8] Outclk_Delay_Enable
Enables K7 OUTCLK delay. Default is disabled.
AD[7:5] SysClock_Mux[2:0]
Selects input SPLL clock mux for PLL test mode. Refer to Ch. 11 of IGD4 Differences Document
AD[4] IGD4 Threshhold Range Select for S2k Cells is
Low - Threshold sense set to between 0.6V and 1.0V. High - S2k Threshold sense set to between 1.0V and 1.4V.
AD[20] AGP TYPEDET
LOW - AGP Card with VDD_AGP = 1.5V installed HIGH - AGP Card with VDD_AGP = 3.3V installed
IGD4 PCI Strappings
R218 10K-REV
AD6 AD5 AD4
MICRO-STAR
MS-6502
R217
R221
R225 10K-REV
10K-REV
R220
R224
10K
10K
10K
37 39Wednesday, March 21, 2001
1
0A
8
Place at solder side of CPU0 Place at solder side of CPU1
VCORE VCORE VCORE VCORE
C474 0.1u
C484 0.1u
C473 0.1u
D D
C490 0.1u
C523 0.1u
C535 0.1u
C475 0.1u
C534 0.1u
C515 0.1u
C479 0.1u
C522 0.1u
C489 0.1u
C C
B B
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
5VSB
EC45 1000u/6.3V
C488 0.1u
C516 0.1u
C483 0.1u
C480 0.1u
+
C381 0.1u
NOPOP
NOPOP
NOPOP
NOPOP
VCORE decoupling for IGD4
VCORE
C245
0.1u
C243
0.1u
C353
0.1u
C350
0.1u
Around IGD4
A A
8
VCORE
C499
C526
C355
C247
C244
C503
C498
Under IGD4
7
C502 0.1u
C536 0.1u
C472 0.1u
C508 0.1u
C507 0.1u
C486 0.1u
C476 0.1u
C500 0.1u
C477 0.1u
C482 0.1u
C521 0.1u
C487 0.1u
0.1u
100p
1000p
0.1u
1000p
100p
100p
7
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
VCC3
C485 0.1u
NOPOP
C501 0.1u
NOPOP
C478 0.1u
NOPOP
C481 0.1u
NOPOP
C294 0.1u
C347 0.1u
C345 0.1u
C341 0.1u
Place around the SB
6
S.B.
6
AGP Decoupling
5
(Near the VDDQ Power Pin of AMD762)
VDDQ
C504
C494
C493
C264
VDDQ
C288
100p
100p
0.1u
0.1u
C251
C290
C255
1000p
1000p
100p
0.1u
Place under IGD4
AGP Slot Decoupling
VDDQ VCC3
C213
0.1u
C233
0.1u
VCC3
VCC2_5
C246
C249
0.1u
0.1u
10u
+
EC39
10u
+
EC43
N.B.
C197
C151
0.1u
0.1u
Place an additional four spread from A14 - A33
VCC3
near IGD4
VCC3
C211
0.1u
C510 0.1u
C174 0.1u
C520 0.1u
C338 0.1u
C308 0.1u
C340 0.1u
C304 0.1u
C145 1u
C194 1u
C195 1u
C192 1u
5
C207
0.1u
Place 1 at each pair of VDDQ pins
4
VDDQ
Place near AGP slot
C89
0.1u
Place 1 at each pair of VCC3 pins
VCC3 VCC2_5
C366 0.1u
C399 0.1u
Place at 2.5v/3.3v plane split near DCSTOP# and PLL signals going into IGD4
VCC3
4
C234 0.1u
C256 0.1u
C235 0.1u
C260
C205
C215
C219
C148
C201
1000p
C221 0.1u
C218 0.1u
C220 0.1u
C191
0.1u
3
VCORE
C131
0.22u
C180
0.22u
C126
VCORE
C127
C159
C155
C181
C165
C137
C187
C185
C182
C282
C334
C325
C305
C322
C331
C329
C277
C275
C273
C327
C309
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.1u
0.1u
0.1u
0.1u
0.1u
C169
C160
0.1u
0.1u
3
2
CPU0 VCORE DECOUPLING CAPACITOR
C124
C132
C129
C140
C164
C168
C161
C147
C188
C186
C184
C170
CPU1 VCORE DECOUPLING CAPACITOR
C293
C333
C318
C295
C316
C330
C278
C276
C274
C284
C283
C310
Title
Size Document Number Rev
Custom
Date: Sheet of
2
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
MICRO-STAR
C125
C179
C128
C183
C153
C303
C332
C314
C285
C312
Bypass Capacitors
MS-6502
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
1
38 39Thursday, March 22, 2001
1
0A
5
4
3
2
1
FIDUCIALSMOUNTING HOLES
MH2
X_150 Drill / 300 Pad
9 2 3
D D
4
5 6 7
(NPTH)
8
1
MH4
X_150 Drill / 300 Pad
9 2 3 4
5 6 7
(NPTH)
8
1
MH3
X_150 Drill / 300 Pad
9 2 3
C C
4
5 6 7
(NPTH)
8
1
MH1
X_150 Drill / 300 Pad
9 2 3
(NPTH)
4
KBGND
5 6 7 8
1
MH7
X_150 Drill / 300 Pad
9
B B
2 3 4
5 6 7
(NPTH)
8
1
MH6
X_150 Drill / 300 Pad
9 2 3
(NPTH)
4
1
MH5
X_150 Drill / 300 Pad
9 2 3
(NPTH)
4
1
MH8
X_150 Drill / 300 Pad
9 2 3
(NPTH)
4
1
MH9
X_150 Drill / 300 Pad
9 2 3
(NPTH)
4
1
T5
1
1 2 3
D1x3-BK
T2
1 2 3
D1x3-BK
5 mil Coupon
5 mil Coupon
Layer 4: 5 mil trace 10 mil spacing
2
2
4
4
Layer 6: 5 mil trace 8 mil spacing
6
6
8
8
Layer 1: 5 mil trace 10 mil spacing
2
2
4
4
Layer 3: 5 mil trace 20 mil spacing
6
6
8
8
2 3
1 2 3
T3
1
1
3
3
5
5
7
7
D2x4-BK
T4
1
1
3
3
5
5
7
7
D2x4-BK
L4_USB+ L4_USB­L6_USB+ L6_USB-
L1_LAN+ L1_LAN­L3_LAN+ L6_LAN-
L1_60ohm
L3_60ohm
L4_60ohm
L6_60ohm
5 6 7 8
5 6 7 8
5 6 7 8
5 6 7 8
FM4
X_FIDUCIAL
FM2
X_FIDUCIAL
FM3
X_FIDUCIAL
FM1
X_FIDUCIAL
FM8
X_FIDUCIAL
FM6
X_FIDUCIAL
FM7
X_FIDUCIAL
FM5
X_FIDUCIAL
5VSB
U10E
1110
7407-SOIC14
U10F
1312
7407-SOIC14
A A
Title
Size Document Number Rev
B
5
4
3
2
Date: Sheet
MICRO-STAR
Mounting Hole
MS-6502
1
39 39Wednesday, March 21, 2001
0A
of
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