MOTOROLA MC68HC908GR8, MC68HC908GR4 Technical data
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MC68HC908GR8
MC68HC908GR4
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Technical Data
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M68HC08
Microcontrollers
WWW.MOTOROLA.COM/SEMICONDUCTORS
MC68HC908GR8/D
Rev. 4, 6/2002
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MC68HC908GR8
MC68HC908GR4
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Technical Data — Rev 4.0
Motorola reserves the righ t to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of i ts products for any partic ular purpose, nor does Moto rola assume any
liability arising out of the application or use of any prod uct or circuit, and s pecifically
disclaims any an d all liability, including withou t limitation consequential or inc idental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can an d do vary in different applications and actua l performance may
vary over time. A ll operating parameters, i ncluding "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under i ts patent rights nor the rig hts of others. Motorola prod ucts are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other applicat ion in wh ich the failure of the Mo torola pr oduct could cr eate a
situation where personal injury or death may oc cur. Should Buyer purchase o r use
Motorola products for any such unintended or una uthorized application, Buye r shall
indemnify and hold Motorola and its officers, employees, subsid iaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent reg arding the design o r manufacture of the p art.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2002
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA 3
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Technical Data MC68HC908GR8 — Rev 4.0
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Technical Data — MC68HC908GR8
List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
List of Paragraphs
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List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Section 1. General Description . . . . . . . . . . . . . . . . . . . .25
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .35
Section 3. Low Power Modes. . . . . . . . . . . . . . . . . . . . . .49
Section 4. Resets and Interrupts. . . . . . . . . . . . . . . . . . .61
Section 5. Analog-to-Digital Converter (ADC) . . . . . . . .79
Section 6. Break Module (BRK) . . . . . . . . . . . . . . . . . . . .91
Section 7. Clock Generator Module (CGMC) . . . . . . . . .99
Section 8. Configuration Register (CONFIG) . . . . . . . .129
Section 9. Computer Operating Properly (COP) . . . . .133
Section 10. Central Processing Unit (CPU) . . . . . . . . .139
Section 11. Flash Memory . . . . . . . . . . . . . . . . . . . . . . .157
Section 12. External Interrupt (IRQ) . . . . . . . . . . . . . . .167
Section 13. Keyboard Interr upt (KBI) . . . . . . . . . . . . . .175
Section 14. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . .183
Section 15. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .189
Section 16. Input/Output Ports (I/O) . . . . . . . . . . . . . . .205
MC68HC908GR8 — Rev 4.0 Technical Data
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Section 17. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Section 18. Serial Communications Interface (SCI). . .231
Section 19. System Integration Module (SIM) . . . . . . .271
Section 20. Serial Peripheral Interface (SPI). . . . . . . . .297
Section 21. Timebase Module (TBM). . . . . . . . . . . . . . .329
Section 22. Timer Interface Module (TIM). . . . . . . . . . .335
Section 23. Electrical Specificatio ns. . . . . . . . . . . . . . .361
Section 24. Mechanical Specifications . . . . . . . . . . . . .387
Section 25. Ordering Information . . . . . . . . . . . . . . . . .391
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Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Technical Data MC68HC908GR8 — Rev 4.0
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Technical Data — MC68HC908GR8
Table of Contents
List of Paragraphs
Table of Contents
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List of Tables
List of Figures
Section 1. General Description
1.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Section 2. Memory Map
2.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . .35
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
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Section 3. Low Power Modes
3.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . .50
3.4 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.5 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .51
3.6 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . . 52
3.7 Computer Operating Properly Module (COP). . . . . . . . . . . . . .52
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3.8 External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .53
3.9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . .53
3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .54
3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . .54
3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . .55
3.13 Timer Interface Module (TIM1 and TIM2). . . . . . . . . . . . . . . . .55
3.14 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.16 Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Section 4. Resets and Interrupts
4.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Section 5. Analog-to-Digital Converter (ADC)
5.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
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5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table of Contents
Section 6. Break Module (BRK)
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6.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.6 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Section 7. Clock Generator Module (CGMC)
7.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
7.6 CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
7.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
7.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
7.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .125
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Section 8. Configuration Register (CONFIG)
8.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Section 9. Computer Operating Properly (COP)
9.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
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9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 37
9.9 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . .137
Section 10. Central Processing Unit (CPU)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 39
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.4 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10.5 Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .145
10.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
10.7 CPU during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . .146
10.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
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Table of Contents
Section 11. Flash Memory
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 57
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .160
11.6 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . .161
11.7 FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . . .162
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11.8 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
11.9 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
11.10 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Section 12. External Interrupt (IRQ)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 67
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
12.5 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
12.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .1 71
12.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .172
Section 13. Keyboard Interrupt (KBI)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 75
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
13.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
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13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 80
13.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 1 80
13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Section 14. Low-Voltage Inhibit (LVI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 83
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
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14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
14.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 88
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 89
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
15.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Section 15. Monitor ROM (MON)
Section 16. Input/Output Ports (I/O)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 05
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
16.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
16.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
16.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
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16.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Table of Contents
Section 17. RAM
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 29
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Section 18. Serial Communications Interface (SCI)
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 31
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18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
18.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 50
18.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .251
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
Section 19. System Integration Module (SIM)
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 71
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
19.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .275
19.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .276
19.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
19.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 90
19.8 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
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MOTOROLA Table of Contents 13
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Section 20. Serial Peripheral Interface (SPI)
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 97
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
20.4 Pin Name Conventions and I/O Register Addresses . . . . . . .298
20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
20.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
20.7 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . .309
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20.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
20.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 17
20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 3 18
20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
Section 21. Timebase Module (TBM)
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 29
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
21.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .331
21.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 33
Section 22. Timer Interface Module (TIM)
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 35
Technical Data MC68HC908GR8 — Rev 4.0
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22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
22.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
22.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
22.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 47
22.8 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . .348
22.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
Table of Contents
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22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
Section 23. Electrical Specifications
23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 61
23.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .363
23.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
23.5 5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .364
23.6 3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .366
23.7 5.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
23.8 3.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
23.9 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . .370
23.10 Output Low-Voltage Characteristics. . . . . . . . . . . . . . . . . . . .373
23.11 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
23.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
23.13 5.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 79
23.14 3.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 80
23.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .383
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Table of Contents 15
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23.16 Clock Generation Module Characteristics . . . . . . . . . . . . . . .383
23.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
Section 24. Mechanical Specifications
24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 87
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
24.3 32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . .388
24.4 28-Pin PDIP (Case #710). . . . . . . . . . . . . . . . . . . . . . . . . . . .389
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24.5 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .390
Section 25. Ordering Information
25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 91
25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
25.4 Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
Glossary
Revision History
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 05
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Changes from Rev 3.0 published in February 2002 to Rev 4.0
published in June 2002. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Changes from Rev 2.0 published in Janu ary 2002 to Rev 3.0 pub-
lished in February 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
Changes from Rev 1.0 published in April 2001 to Rev 2.0 pub-
lished in December 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
Technical Data MC68HC908GR8 — Rev 4.0
16 Table of Contents MOTOROLA
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Technical Data — MC68HC908GR8
Table Title Page
2-1 Vector Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4-1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4-2 Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
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5-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
5-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7-1 Numeric Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7-2 PRE 1 and PRE0 Programming. . . . . . . . . . . . . . . . . . . . . . .117
7-3 VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .117
10-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10-2 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11-1 Examples of protect start address:. . . . . . . . . . . . . . . . . . . . .166
14-1 LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15-1 Monitor Mode Signal Requirements and Options. . . . . . . . . .193
15-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
15-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .197
15-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .199
15-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .199
15-6 IREAD (Indexed Read) Command. . . . . . . . . . . . . . . . . . . . .200
15-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .200
15-8 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .201
15-9 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .201
16-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .208
16-2 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16-3 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
16-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
16-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
16-6 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
18-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
18-2 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
List of Tables
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA List of Tables 17
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18-3 Data Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
18-4 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
18-5 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .255
18-6 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .266
18-7 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
18-8 SCI Baud Rate Selection Examples. . . . . . . . . . . . . . . . . . . .268
19-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .273
19-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
19-3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
19-4 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 93
20-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
20-2 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
20-3 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
20-4 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .327
21-1 Timebase Rate Selection for OSC1 = 32.768 kHz. . . . . . . . .331
22-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
22-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
22-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .358
23-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362
23-2 Functional Operation Range. . . . . . . . . . . . . . . . . . . . . . . . . .363
23-3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
23-4 5.0V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .364
23-5 3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .366
23-6 5.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
23-7 3.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
23-8 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .383
23-9 CGM Component Specifications. . . . . . . . . . . . . . . . . . . . . . .383
25-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
25-2 Development Tool Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
25-3 Development Tool Components. . . . . . . . . . . . . . . . . . . . . . .393
Technical Data MC68HC908GR8 — Rev 4.0
18 List of Tables MOTOROLA
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Technical Data — MC68HC908GR8
Figure Title Page
1-1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1-2 QFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1-3 DIP And SOIC Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . .31
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1-4 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2-2 Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . . . .39
4-1 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4-2 Power-On Reset Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4-3 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . .65
4-4 Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4-5 Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . . . . .68
4-6 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4-7 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .76
4-8 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .76
4-9 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .77
5-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5-2 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . . .85
5-3 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
5-4 ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . .88
6-1 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . .92
6-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
6-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . . .95
6-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . .96
6-5 Break Address Register Low (BRKL). . . . . . . . . . . . . . . . . . . .96
6-6 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . .96
6-7 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . .98
7-1 CGMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 01
7-2 CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . . . .111
7-3 CGMC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .114
List of Figures
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA List of Figures 19
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List of Figures
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7-4 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .115
7-5 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . .118
7-6 PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . .119
7-7 PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . .120
7-8 PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . .121
7-9 PLL Reference Divider Select Register (PMDS) . . . . . . . . . .122
7-10 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
8-1 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .130
8-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .130
9-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9-2 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .136
10-1 CPU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10-3 Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10-4 Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
10-5 Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
10-6 Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 143
11-1 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . .159
11-2 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . .164
11-3 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . .165
11-4 FLASH Block Protect Start Address. . . . . . . . . . . . . . . . . . . .165
12-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .169
12-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .169
12-3 IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . .172
13-1 Keyboard Module Block Diagram. . . . . . . . . . . . . . . . . . . . . .177
13-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
13-3 Keyboard Status and Cont rol Register (INTKBSCR) . . . . . . .181
13-4 Keyboard Interrupt Enable Register (INTKBIER) . . . . . . . . . .182
14-1 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .185
14-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .186
14-3 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .187
15-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .195
15-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
15-4 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
15-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15-6 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15-7 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .202
Technical Data MC68HC908GR8 — Rev 4.0
20 List of Figures MOTOROLA
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15-8 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .2 03
16-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .206
16-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .209
16-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .210
16-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16-5 Port A Input Pullup Enable Register (PTAPUE) . . . . . . . . . . .212
16-6 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .213
16-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .214
16-8 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
16-9 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .216
16-10 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . . .217
16-11 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
16-12 Port C Input Pullup Enable Register (PTCPUE). . . . . . . . . . .219
16-13 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .220
16-14 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . .222
16-15 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
16-16 Port D Input Pullup Enable Register (PTDPUE). . . . . . . . . . .224
16-17 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .225
16-18 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .2 26
16-19 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
18-1 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .234
18-2 SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .235
18-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
18-4 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
18-5 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .242
18-6 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
18-7 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
18-8 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
18-9 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .253
18-10 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .256
18-11 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .258
18-12 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .260
18-13 Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
18-14 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .264
18-15 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . .265
18-16 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .265
19-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
19-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .274
List of Figures
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA List of Figures 21
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19-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
19-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
19-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
19-6 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .278
19-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
19-8 Interrupt Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
19-9 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .283
19-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
19-11 Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . . . .285
19-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .288
19-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .288
19-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .289
19-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
19-16 Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . . .291
19-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .292
19-18 Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
19-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .293
19-20 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .294
19-21 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .295
19-22 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .296
20-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .299
20-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .300
20-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . .301
20-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .305
20-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
20-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .306
20-7 Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . . . .308
20-8 .SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . .309
20-9 Missed Read of Overflow Condition. . . . . . . . . . . . . . . . . . . .311
20-10 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . .312
20-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .315
20-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
20-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .322
20-14 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .325
20-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .328
21-1 Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
21-2 Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . . .331
22-1 TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 38
Technical Data MC68HC908GR8 — Rev 4.0
22 List of Figures MOTOROLA
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22-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 339
22-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .343
22-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .349
22-5 TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . .352
22-6 TIM Counter Registers Low (TCNTL). . . . . . . . . . . . . . . . . . .352
22-7 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .353
22-8 TIM Counter Modulo Register Low (TMODL). . . . . . . . . . . . .353
22-9 TIM Counter Register High (TCNTH) . . . . . . . . . . . . . . . . . . .354
22-10 TIM Counter Register Low (TCNTL). . . . . . . . . . . . . . . . . . . .354
22-11 TIM Channel 0 Status and Control Register (TSC0) . . . . . . .355
22-12 TIM Channel 1 Status and Control Register (TSC1) . . . . . . .355
22-13 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
22-14 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . .360
22-15 TIM Channel 0 Register Low (TCH0L). . . . . . . . . . . . . . . . . .360
22-16 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . .360
22-17 TIM Channel 1 Register Low (TCH1L). . . . . . . . . . . . . . . . . .360
23-1 Typical High-Side Driver Characteristics –
23-2 Typical High-Side Driver Characteristics –
23-3 Typical High-Side Driver Characteristics –
23-4 Typical High-Side Driver Characteristics –
23-5 Typical High-Side Driver Characteristics – Ports PTB5–PTB0,
23-6 Typical High-Side Driver Characteristics – Ports PTB5–PTB0,
23-7 Typical Low-Side Driver Characteristics –
23-8 Typical Low-Side Driver Characteristics –
23-9 Typical Low-Side Driver Characteristics –
23-10 Typical Low-Side Driver Characteristics –
23-11 Typical Low-Side Driver Characteristics – Port s PTB5–PTB0,
List of Figures
Port PTA3–PTA0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . .370
Port PTA3–PTA0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . .370
Port PTC1–PTC0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . .371
Port PTC1–PTC0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . .371
PTD6–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) . . . . . . . . . .372
PTD6–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc) . . . . . . . . . .372
Port PTA3–PTA0 (VDD = 5.5 Vdc) . . . . . . . . . . . . . . . . . . . . .373
Port PTA3–PTA0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . .373
Port PTC1–PTC0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . .374
Port PTC1–PTC0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . .374
PTD6–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) . . . . . . . . . .375
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA List of Figures 23
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23-12 Typical Low-Side Driver Characteristics – Port s PTB5–PTB0,
23-13 Typical Operating IDD, with All Modules Turned On
23-14 Typical Wait Mode IDD, with all Modules Disabled
23-15 Typical Stop Mode IDD, with all Modules Disabled
23-16 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
23-17 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
PTD6–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc) . . . . . . . . . .375
(–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
(–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
(–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
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Technical Data MC68HC908GR8 — Rev 4.0
24 List of Figures MOTOROLA
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Technical Data — MC68HC908GR8
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Section 1. General Description
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1.2 Introduction
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1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
The MC68HC908GR8 is a member of the low-cost, high-performance
M68HC08 Family of 8- bit micro cont rol ler uni t s (MCU s). All M CUs in th e
family use the enhanced M68HC08 central processor unit (CPU08) and
are available with a variety of modules, memory sizes and types, and
package types.
This document also describes the MC68HC908GR4. The
MC68HC908GR4 is a device identical to the MC68HC908GR8 except
that it has less Flash memory. Only wh en there are differ ences from the
MC68HC908GR8 is the MC68HC908GR4 specifically mentioned in the
text.
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA General Description 25
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General Description
1.3 Features
For convenie nce, features have been organized to reflect:
• Standard features of the MC68HC908GR8
• Features of the CPU08
1.3.1 Standard Features of the MC68HC908GR8
• High-performance M68HC08 architecture optimized for Ccompilers
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• Fully upward-com pa tibl e obj ect cod e wi th M 680 5, M 14 68 05, and
M68HC05 Families
• 8-MHz internal bus frequency
• FLASH program memory security
• On-chip programming firmware for use with host personal
computer which does not require high voltage for entry
• In-system programming
• System protection features:
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset and selectable trip
points for 3.0 V an d 5.0 V operation
– Illegal opcode detection with reset
– Illegal address detection with reset
• Low-power design; fully static with stop and wait modes
• Standard low-power modes of operation:
(1)
– Wait mode
– Stop mode
• Master reset pin and power-o n reset (POR)
1. No security feature is absolute ly se cure . Howe ve r, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Technical Data MC68HC908GR8 — Rev 4.0
26 General Description MOTOROLA
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• 7680 bytes of on-chip FLASH memory on the MC68HC908GR8
• 384 bytes of on-chip random-access memory (RAM)
• Serial peripheral interface module (SPI)
• Serial communications inte rface module (SCI)
• One 16-bit, 2-channel timer (TIM1) and one 16-bit, 1-channel
General Description
Features
and 4096 bytes of on-chip FLASH memory on the
MC68HC908GR4 with in-circuit programming capabilities of
FLASH program memory
timer (TIM2) interface modules with sel ectab le input capture,
output compare, and PWM cap ability on each channel
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• 6-channel, 8-bit successive approximation analog-to-digital
converter (ADC)
• BREAK module (BRK) to allow single breakpoint setting during incircuit debugging
• Internal pullups on IRQ and RST to reduce customer system cost
• Clock generator module with on-chip 32-kHz crystal compatible
PLL (phase-lock loop)
• Up to 21 general-purpose input/output (I/O) pins, including:
– 19 shared-function I/O pins
– Up to two dedicated I/O pins, depending on package choice
• Selectable pullups on inputs only on ports A, C, and D. Selection
is on an individual port bit basis. During output mode, pullups are
disengaged.
• High current 10-mA sink/10-mA source capab ility on all port pins
• Higher current 15-mA sink/source capability on PTC0–PTC1
• Timebase module with clock prescaler circuitry for eight user
selectable periodic re al- ti me int er rupts with optional active clock
source during stop mode for periodic wakeup from stop using an
external 32-kHz crystal
• Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG
register to allow user s electio n of havin g the oscill ator enabled or
disabled during stop mode
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA General Description 27
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General Description
• 4-bit keyboard wakeup port
• 32-pin quad flat pack (QFP) or 2 8-p in pla stic dual- in-line package
• Specific features of the MC68HC908GR8 in 28-pin DIP and 28-p in
1.3.2 Features of the CPU08
(DIP) or 28-pin small outline integrated circuit (SOIC)
SOIC are:
– Port B is only 4 bits: PTB 0–PTB3; 4-channel ADC module
– No Port C bits
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1.4 MCU Block Diagram
Features of the CPU08 include:
• Enhanced HC05 programming model
• Extensive lo op control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
Figure 1-1 shows the struc ture of the MC68HC908GR8.
Technical Data MC68HC908GR8 — Rev 4.0
28 General Description MOTOROLA
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General Description
MCU Block Diagram
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–PTA0/KBD0 †
PTD6/T2CH0 †
PTD5/T1CH1 †
PTD4/T1CH0 †
PTA3/KBD3
PORTA
DDRA
INTERNAL BUS
MODULE
PROGR. TIMEBASE
UNIT (ALU)
ARITHMETIC/LOGIC
M68HC08 CPU
PTB5/AD5–PTB0/AD0
PORTB
DDRB
MODULE
SINGLE BRKPT BREAK
DUAL V. LOW-VOLTAGE INH IBI T
PTC1–PTC0 † ‡
PORTC
DDRC
MODULE
4-BIT KEYBOARD
INTERRUPT MODULE
2-CHANNEL TIMER INTERFACE
PTD3/SPSCK †
MODULE 1
MODULE 2
1-CHANNEL TIMER INTERFACE
†
PTE1/RxD
COMPUTER OPERATING
PROPERLY MODULE
PHASE-LOCKED LOOP
PTE0/TxD
PORTE
DDRE
MODULE
POWER-ON RESET
MODULE
DATA BUS SWITCH
INTERFACE MODULE
24 INTR SYSTEM INTEGRATION
MONITOR MODULE
MODULE
MODULE
SINGLE EXTERNAL IRQ
CONVERTER MODULE
8-BIT ANALOG-TO-DIG ITA L
SERIAL PERIPHERAL
MODULE
SECURITY
MODULE
MEMORY MAP
POWER
MODULE
MONITOR MODE ENTRY
MODULE
MASK OPTION REGISTER1
MODULE
MASK OPTION REGISTER2
PTD2/MOSI †
PTD1/MISO †
PTD0/SS
PORTD
DDRD
INTERFACE MODULE
SERIAL COMMUNICATIONS
32-kHz OSCILLATOR
CLOCK GENERATOR MODULE
USER RAM — 384 BYTES
CPU
REGISTERS
MC68HC908GR4 US ER FLA SH — 4096BYTES
MC68HC908GR8 USER FLASH — 7680 BYTES
CONTROL AND STATUS REGISTERS — 64 BYTES
MONITOR ROM — 310 BYTES
OSC1
USER FLASH VECTOR SPACE — 36 BYTES
FLASH PROGRAMMING (BURN-IN) ROM — 544 BYTES
OSC2
CGMXFC
* RST
* IRQ
DD
DDA
SSA
VSSV
REFL
REFH
V
/ V
SSAD
DDAD /
V
V
V
V
† Ports are software configurable with pullup device if input port.
‡ Higher current drive port pins
* Pin contains integrated pullup device
Figure 1-1. MCU Block Diagram
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA General Description 29
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General Description
1.5 Pin Assignments
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OSC1
OSC2
32
RST
1
PTE0/TxD
PTE1/RxD
IRQ
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PTD0/SS
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP.
31
2
3
4
5
6
7
8
9
10
SS
DD
V
V
SSAVDDA
CGMXFC
V
29
30
11
12
PTD4/T1CH0
PTD5/T1CH1
28
13
PTD6/T2CH0
PTC1
27
14
PTB0/AD0
Figure 1-2. QFP Pin Assignments
cale Semiconductor,
PTC0
PTB1/AD1
26
15
PTA3/KBD3
25
24
23
22
21
20
19
18
17
16
PTB2/AD2
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
V
SSAD/VREFL
V
DDAD/VREFH
PTB5/AD5
PTB4/AD4
PTB3/AD3
Frees
Technical Data MC68HC908GR8 — Rev 4.0
30 General Description MOTOROLA
For More Information On This Product,
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