Motorola MC14536BCL, MC14536BCP, MC14536BDW Datasheet

MOTOROLA CMOS LOGIC DATA

MC14536B

 

The MC14536B programmable timer is a 24–stage binary ripple counter with 16 stages selectable by a binary code. Provisions for an on–chip RC oscillator or an external clock are provided. An on–chip monostable circuit incorporating a pulse–type output has been included. By selecting the appropriate counter stage in conjunction with the appropriate input clock frequency, a variety of timing can be achieved.

• 24 Flip–Flop Stages — Will Count From 20 to 2

• Last 16 Stages Selectable By Four–Bit Select Code

• 8–Bypass Input Allows Bypassing of First Eight Stages

• Set and Reset Inputs

• Clock Inhibit and Oscillator Inhibit Inputs

• On–Chip RC Oscillator Provisions

• On–Chip Monostable Output Provisions

• Clock Conditioning Circuit Permits Operation With Very Long Rise and

Fall Times

• Test Mode Allows Fast Test Sequence

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter Value Unit

DC Supply Voltage – 0.5 to + 18.0 V

Vin, V

out

Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current (DC or Transient), per Pin

± 10 mA

Power Dissipation, per Package† 500 mW

stg

Storage Temperature – 65 to + 150

Lead Temperature (8–Second Soldering) 260

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

BLOCK DIAGRAM

STAGES 9 THRU 24

Q22Q

Q20Q

Q18Q

Q16Q

Q14Q

Q12Q

Q10Q

DECODER

MONOSTABLE

MULTIVIBRATOR

DECODE

OUT

13MONO–IN 15

D 12

C 11

B 10

A 9

VDD = PIN 16

VSS = PIN 8

STAGES

1 THRU 8

8 BYPASSSETRESETCLOCK INH.

7 2 1 6

OUT

OSC. INHIBIT 14



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94



L SUFFIX

CERAMIC CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBDW SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

MOTOROLA CMOS LOGIC DATAMC14536B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

– 55_C 25_C 125_C

Characteristic

Symbol

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage “0” Level

Vin = VDD or 0

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

0.05

Vdc

“1” Level

Vin = 0 or V

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

— — —

Vdc

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

1.5

3.0

4.0

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

— — —

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) Pins 4 & 5 (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

5.0

5.0 10 15

– 1.2 – 0.25 – 0.62

– 1.8

— — — —

– 1.0

– 0.25

– 0.5 – 1.5

– 1.7

– 0.36

– 0.9 – 3.5

— — — —

– 0.7 – 0.14 – 0.35

– 1.1

— — — —

mAdc

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) Pin 13 (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2 – 0.88 – 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

— — — —

mAdc

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)

5.0 10 15

0.64

1.6

4.2

— — —

0.51

1.3

3.4

0.88

2.25

8.8

— — —

0.36

0.9

2.4

— — —

mAdc

Input Current I

15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc

Input Capacitance

(Vin = 0)

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

5.0 10 15

— — —

5.0 10 20

— — —

0.010

0.020

0.030

5.0 10 20

— — —

150 300 600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)

5.0 10 15

IT = (1.50 µA/kHz) f + I

IT = (2.30 µA/kHz) f + I

IT = (3.55 µA/kHz) f + I

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

MOTOROLA CMOS LOGIC DATA

MC14536B

SWITCHING CHARACTERISTICS* (C

= 50 pF, TA = 25_C)

Characteristic

Symbol V

Min Typ # Max Unit

Output Rise and Fall Time (Pin 13)

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

TLH

THL

5.0 10 15

— — —

100

50 40

200 100

Propagation Delay Time

Clock to Q1, 8–Bypass (Pin 6) High

PLH

, t

PHL

= (1.7 ns/pF) CL + 1715 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 617 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 425 ns

PLH

PHL

5.0 10 15

— — —

1800

650 450

3600 1300 1000

Clock to Q1, 8–Bypass (Pin 6) Low

PLH

, t

PHL

= (1.7 ns/pF) CL + 3715 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 1467 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 1075 ns

PLH

PHL

5.0 10 15

— — —

3.8

1.5

1.1

7.6

3.0

2.3

µs

Clock to Q16

PHL

, t

PLH

= (1.7 ns/pF) CL + 6915 ns

PHL

, t

PLH

= (0.66 ns/pF) CL + 2967 ns

PHL

, t

PLH

= (0.5 ns/pF) CL + 2175 ns

PLH

PHL

5.0 10 15

— — —

7.0

3.0

2.2

6.0

4.5

µs

Reset to Q

PHL

= (1.7 ns/pF) CL + 1415 ns

PHL

= (0.66 ns/pF) CL + 567 ns

PHL

= (0.5 ns/pF) CL + 425 ns

PHL

5.0 10 15

— — —

1500

600 450

3000 1200

900

Clock Pulse Width t

5.0 10 15

600 200 170

300 100

— — —

Clock Pulse Frequency

(50% Duty Cycle)

5.0 10 15

— — —

1.2

3.0

5.0

0.4

1.5

2.0

MHz

Clock Rise and Fall Time t

TLH

THL

5.0 10 15

No Limit

—

Reset Pulse Width t

5.0 10 15

1000

400 300

500 200 150

— — —

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

PIN ASSIGNMENT

125

DECODE

OSC INH

MONO IN

OUT 1

IN 1

RESET

SET

CLOCK INH

8–BYPASS

OUT 2

MOTOROLA CMOS LOGIC DATAMC14536B

PIN DESCRIPTIONS

INPUTS

SET (Pin 1) — A h igh on S et asynchronously forces

Decode Out to a high level. This is accomplished by setting an output conditioning latch to a high level while at the same time resetting the 24 flip–flop stages. After Set goes low (inactive), the occurrence of the first negative clock transition on IN1 causes Decode Out to go low. The counter’s flip–flop stages begin counting on the second negative clock transition of IN1. When Set is high, the on–chip RC oscillator is disabled. This allows for very low–power standby operation.

RESET (Pin 2) — A high on Reset asynchronously forces Decode Out to a low level; all 24 flip–flop stages are also reset to a low level. Like the Set input, Reset disables the on–chip RC oscillator for standby operation.

IN1 (Pin 3) — The device’s internal counters advance on the negative–going edge of this input. IN1 may be used as an external clock input or used in conjunction with OUT1 and OUT2 to form an RC oscillator. When an external clock is used, both OUT1 and OUT2 may be left unconnected or used to drive 1 LSTTL or several CMOS loads.

8–BYPASS (Pin 6) — A high on this input causes the first 8 flip–flop stages to be bypassed. This device essentially becomes a 16–stage counter with all 16 stages selectable. Selection is accomplished by the A, B, C, and D inputs. (See the truth tables.)

CLOCK INHIBIT (Pin 7) — A high on this input disconnects the first counter stage from the clocking source. This holds the present count and inhibits further counting. However, the clocking source may continue to run. Therefore, when Clock Inhibit is brought low, no oscillator start–up time is required. When Clock Inhibit is low, the counter will start counting on the occurrence of the first negative edge of the clocking source at IN1.

OSC INHIBIT (Pin 14) — A high level on this pin stops the RC oscillator which allows for very low–power standby operation. May also be used, in conjunction with an external clock, with essentially the same results as the Clock Inhibit input.

MONO–IN (Pin 15) — Used as the timing pin for the on– chip monostable multivibrator. If the Mono–In input is connected to VSS, the m onostable circuit is d isabled, a nd Decode Out is directly connected to the selected Q output. The monostable circuit is enabled if a resistor is connected between Mono–In and VDD. This resistor and the device’s internal capacitance will determine the minimum output pulse widths. With the addition of an external capacitor to VSS, the pulse width range may be extended. For reliable operation the resistor value should be limited to the range of 5 kΩ to 100 kΩ and the capacitor value should be limited to a maximum of 1000 pf. (See figures 3, 4, 5, and 10).

A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the flip–flop stage to be connected to Decode Out. (See the truth tables.)

OUTPUTS

OUT1, OUT2 (Pin 4, 5) — Outputs used in conjunction with

IN1 to form an RC oscillator. These outputs are buffered and may be used for 20 frequency division of an external clock.

DECODE OUT (Pin 13) — Output function depends on configuration. When the monostable circuit is disabled, this output is a 50% duty cycle square wave during free run.

TEST MODE

The test mode configuration divides the 24 flip–flop stages into three 8–stage sections to facilitate a fast test sequence. The test mode is enabled when 8–Bypass, Set and Reset are at a high level. (See Figure 8.)

+ 9 hidden pages