DDR SDRAM |
MITSUBISHI LSIs |
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M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
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(Rev.1.44) |
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
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Mar. '02 |
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256M Double Data Rate Synchronous DRAM |
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Contents are subject to change without notice. |
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DESCRIPTION
M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit,
M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit,
M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK.Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieve very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
-VDD=VDDQ=2.5V+0.2V
-Double data rate architecture; two data transfers per clock cycle
-Bidirectional, data strobe (DQS) is transmitted/received with data
-Differential clock inputs (CLK and /CLK)
-DLL aligns DQ and DQS transitions
-Commands are entered on each positive CLK edge
-Data and data mask are referenced to both edges of DQS
-4-bank operations are controlled by BA0, BA1 (Bank Address)
-/CAS latency- 2.0/2.5 (programmable)
-Burst length- 2/4/8 (programmable)
-Burst typesequential / interleave (programmable)
-Auto precharge / All bank precharge is controlled by A10
-8192 refresh cycles /64ms (4 banks concurrent refresh)
-Auto refresh and Self refresh
-Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
-SSTL_2 Interface
-Both 66-pin TSOP Package and 64-pin Small TSOP Package M2S56D*0ATP: 0.8mm lead pitch 66-pin TSOP Package M2S56D*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package
-JEDEC standard
- Low Power for the Self Refresh Current ICC6 : 2mA (-75AL , -75L , -10L)
Operating Frequencies
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Max. Frequency |
Max. Frequency |
Standard |
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@CL=2.0 * |
@CL=2.5 * |
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M2S56D20/30/40ATP/AKT-75AL/-75A |
133MHz |
133MHz |
DDR266A |
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M2S56D20/30/40ATP/AKT-75L/-75 |
100MHz |
133MHz |
DDR266B |
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M2S56D20/30/40ATP/AKT-10L/-10 |
100MHz |
125MHz |
DDR200 |
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* CL = CAS(Read) Latency
MITSUBISHI ELECTRIC |
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DDR SDRAM |
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MITSUBISHI LSIs |
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M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
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(Rev.1.44) |
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M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
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Mar. '02 |
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256M Double Data Rate Synchronous DRAM |
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PIN CONFIGURATION(TOP VIEW) |
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x4 |
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x16 |
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VDD |
VDD |
VDD |
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1 |
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66 |
VSS |
VSS |
VSS |
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NC |
DQ0 |
DQ0 |
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2 |
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65 |
DQ15 |
DQ7 |
NC |
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VDDQ |
VDDQ |
VDDQ |
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3 |
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64 |
VSSQ |
VSSQ |
VSSQ |
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NC |
NC |
DQ1 |
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4 |
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63 |
DQ14 |
NC |
NC |
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DQ0 |
DQ1 |
DQ2 |
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5 |
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62 |
DQ13 |
DQ6 |
DQ3 |
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VSSQ |
VSSQ |
VSSQ |
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6 |
66pin TSOP(II) |
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VDDQ |
VDDQ |
VDDQ |
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NC |
NC |
DQ3 |
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7 |
60 |
DQ12 |
NC |
NC |
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NC |
DQ2 |
DQ4 |
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8 |
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DQ11 |
DQ5 |
NC |
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VDDQ |
VDDQ |
VDDQ |
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9 |
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58 |
VSSQ |
VSSQ |
VSSQ |
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NC |
NC |
DQ5 |
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10 |
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57 |
DQ10 |
NC |
NC |
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DQ1 |
DQ3 |
DQ6 |
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11 |
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56 |
DQ9 |
DQ4 |
DQ2 |
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VSSQ |
VSSQ |
VSSQ |
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12 |
400mil width |
55 |
VDDQ |
VDDQ |
VDDQ |
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NC |
NC |
DQ7 |
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13 |
54 |
DQ8 |
NC |
NC |
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NC |
NC |
NC |
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14 |
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x |
53 |
NC |
NC |
NC |
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VDDQ |
VDDQ |
VDDQ |
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15 |
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52 |
VSSQ |
VSSQ |
VSSQ |
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875mil length |
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NC |
NC |
LDQS |
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16 |
51 |
UDQS |
DQS |
DQS |
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NC |
NC |
NC |
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50 |
NC |
NC |
NC |
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VDD |
VDD |
VDD |
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VREF |
VREF |
VREF |
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NC |
NC |
NC |
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19 |
0.65mm |
48 |
VSS |
VSS |
VSS |
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NC |
NC |
LDM |
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20 |
47 |
UDM |
DM |
DM |
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Lead Pitch |
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/WE |
/WE |
/WE |
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46 |
/CLK |
/CLK |
/CLK |
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/CAS |
/CAS |
/CAS |
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CLK |
CLK |
CLK |
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/RAS |
/RAS |
/RAS |
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CKE |
CKE |
CKE |
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/CS |
/CS |
/CS |
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ROW |
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NC |
NC |
NC |
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NC |
NC |
NC |
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25 |
42 |
A12 |
A12 |
A12 |
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BA0 |
BA0 |
BA0 |
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A0-12 |
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A11 |
A11 |
A11 |
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BA1 |
BA1 |
BA1 |
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40 |
A9 |
A9 |
A9 |
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Column |
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A10/AP |
A10/AP |
A10/AP |
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28 |
39 |
A8 |
A8 |
A8 |
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A0 |
A0 |
A0 |
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29 |
A0-9,11(x4) |
38 |
A7 |
A7 |
A7 |
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A1 |
A1 |
A1 |
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30 |
37 |
A6 |
A6 |
A6 |
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A0-9 (x8) |
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A2 |
A2 |
A2 |
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31 |
36 |
A5 |
A5 |
A5 |
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A3 |
A3 |
A3 |
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A0-8 (x16) |
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A4 |
A4 |
A4 |
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VDD |
VDD |
VDD |
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33 |
34 |
VSS |
VSS |
VSS |
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CLK,/CLK |
: Master Clock |
DM |
: Write Mask |
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CKE |
: Clock Enable |
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LDM,UDM |
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/CS |
: Chip Select |
VREF |
: Reference Voltage |
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/RAS |
: Row Address Strobe |
A0-12 |
: Address Input |
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/CAS |
: Column Address Strobe |
BA0,1 |
: Bank Address Input |
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/WE |
: Write Enable |
VDD |
: Power Supply |
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DQ0-15 |
: Data I/O |
VDDQ |
: Power Supply for Output |
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DQS |
: Data Strobe |
VSS |
: Ground |
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LDQS,UDQS |
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VSSQ |
: Ground for Output |
MITSUBISHI ELECTRIC |
2 |
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DDR SDRAM |
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MITSUBISHI LSIs |
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M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
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(Rev.1.44) |
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
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Mar. '02 |
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256M Double Data Rate Synchronous DRAM |
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PIN CONFIGURATION(TOP VIEW) |
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X 4 |
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X 8 |
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X 16 |
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VDD |
VDD |
VDD |
NC |
DQ0 |
DQ0 |
VDDQ |
VDDQ |
VDDQ |
NC |
NC |
DQ1 |
DQ0 |
DQ1 |
DQ2 |
VSSQ |
VSSQ |
VSSQ |
NC |
NC |
DQ3 |
NC |
DQ2 |
DQ4 |
VDDQ |
VDDQ |
VDDQ |
NC |
NC |
DQ5 |
DQ1 |
DQ3 |
DQ6 |
VSSQ |
VSSQ |
VSSQ |
NC |
NC |
DQ7 |
VDDQ |
VDDQ |
VDDQ |
NC |
NC |
LDQS |
NC |
NC |
NC |
VDD |
VDD |
VDD |
NC |
NC |
NC |
NC |
NC |
LDM |
/WE |
/WE |
/WE |
/CAS |
/CAS |
/CAS |
/RAS |
/RAS |
/RAS |
/CS |
/CS |
/CS |
NC |
NC |
NC |
BA0 |
BA0 |
BA0 |
BA1 |
BA1 |
BA1 |
A10/AP |
A10/AP |
A10/AP |
A0 |
A0 |
A0 |
A1 |
A1 |
A1 |
A2 |
A2 |
A2 |
A3 |
A3 |
A3 |
VDD |
VDD |
VDD |
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1 |
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64 |
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2 |
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3 |
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62 |
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58 |
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8 |
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57 |
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9 |
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56 |
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10 |
64pin sTSOP |
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55 |
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11 |
PIN PITCH 0.4 mm |
54 |
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12 |
53 |
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13 |
52 |
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14 |
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16 |
49 |
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17 |
48 |
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18 |
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19 |
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21 |
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22 |
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24 |
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41 |
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40 |
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26 |
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39 |
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27 |
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38 |
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28 |
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37 |
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29 |
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36 |
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35 |
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31 |
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34 |
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32 |
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33 |
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VSS |
VSS |
VSS |
DQ15 |
DQ7 |
NC |
VSSQ |
VSSQ |
VSSQ |
DQ14 |
NC |
NC |
DQ13 |
DQ6 |
DQ3 |
VDDQ |
VDDQ |
VDDQ |
DQ12 |
NC |
NC |
DQ11 |
DQ5 |
NC |
VSSQ |
VSSQ |
VSSQ |
DQ10 |
NC |
NC |
DQ9 |
DQ4 |
DQ2 |
VDDQ |
VDDQ |
VDDQ |
DQ8 |
NC |
NC |
VSSQ |
VSSQ |
VSSQ |
UDQS |
DQS |
DQS |
NC |
NC |
NC |
VREF |
VREF |
VREF |
VSS |
VSS |
VSS |
UDM |
DM |
DM |
/CLK |
/CLK |
/CLK |
CLK |
CLK |
CLK |
CKE |
CKE |
CKE |
NC |
NC |
NC |
A12 |
A12 |
A12 |
A11 |
A11 |
A11 |
A9 |
A9 |
A9 |
A8 |
A8 |
A8 |
A7 |
A7 |
A7 |
A6 |
A6 |
A6 |
A5 |
A5 |
A5 |
A4 |
A4 |
A4 |
VSS |
VSS |
VSS |
CLK,/CLK |
: Master Clock |
DM |
: Write Mask |
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CKE |
: Clock Enable |
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LDM,UDM |
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/CS |
: Chip Select |
VREF |
: Reference Voltage |
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/RAS |
: Row Address Strobe |
A0-12 |
: Address Input |
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/CAS |
: Column Address Strobe |
BA0,1 |
: Bank Address Input |
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/WE |
: Write Enable |
VDD |
: Power Supply |
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DQ0-15 |
: Data I/O |
VDDQ |
: Power Supply for Output |
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DQS |
: Data Strobe |
VSS |
: Ground |
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LDQS,UDQS |
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VSSQ |
: Ground for Output |
MITSUBISHI ELECTRIC |
3 |
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DDR SDRAM |
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MITSUBISHI LSIs |
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M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
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M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
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Mar. '02 |
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256M Double Data Rate Synchronous DRAM |
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Package Outline of sTSOP |
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+ |
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0.05 |
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0.125- |
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0.02 |
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64 |
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A
10.65+0.2 |
9.05+0.1 |
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*2 |
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1 |
32 |
*1 |
1.2 MAX |
13.1+0.1 |
B |
0.4 NOM |
*3 |
+0.1 |
0.08 |
M |
|
0.1 |
0.16-0.05 |
0 - 10 |
|
0.25 |
|
0.8 |
0.6+0.15 |
0.5+0.1 |
|
(1) |
0.35 |
0.125+0.075 |
0.55 MAX |
Note)
1.DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2.DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
Detail A (NTS) |
Detail B (NTS) |
MITSUBISHI ELECTRIC |
4 |
|
|
DDR SDRAM |
|
MITSUBISHI LSIs |
|
|
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
|||
|
(Rev.1.44) |
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
||
|
Mar. '02 |
|||
|
|
256M Double Data Rate Synchronous DRAM |
||
|
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||
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PIN FUNCTION |
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||
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SYMBOL |
TYPE |
DESCRIPTION |
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Clock: CLK and /CLK are differential clock inputs. All address and control |
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CLK, /CLK |
Input |
input signals are sampled on the crossing of the positive edge of CLK and |
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negative edge of /CLK. Output (read) data is referenced to the crossings of |
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CLK and /CLK (both directions of crossing). |
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Clock Enable: CKE controls internal clock. When CKE is low, internal clock |
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CKE |
Input |
for the following cycle is ceased. CKE is also used to select auto / self |
|
|
refresh.After self refresh mode is started, CKE becomes asynchronous |
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input. Self refresh is maintained as long as CKE is low. |
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/CS |
Input |
Chip Select: When /CS is high, any command means No Operation. |
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/RAS, /CAS, /WE |
Input |
Combination of /RAS, /CAS, /WE defines basic commands. |
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A0-12 specify the Row / Column Address in conjunction with BA0,1. The |
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Row Address is specified by A0-12. The Column Address is specified by |
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A0-12 |
Input |
A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge |
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|
option. When A10 is high at a read / write command, an auto precharge is |
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performed. When A10 is high at a precharge command, all banks are |
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precharged. |
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BA0,1 |
Input |
Bank Address: BA0,1 specifies one of four banks to which a command is |
|
|
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. |
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DQ0-15(x16), |
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DQ0-7(x8), |
Input / Output |
Data Input/Output: Data bus |
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DQ0-3(x4), |
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Data Strobe: Output pin during Read operation, input pin during Write |
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|
DQS |
Input / Output |
operation. Edge-aligned with read data, placed at the centered of write data |
|
|
to capture the write data. For the x16, LDQS corresponds to the data on |
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DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15. |
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Input Data Mask: DM is an input mask signal for write data. Input data |
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|
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is masked when DM is sampled HIGH along with the input data |
|
|
DM |
Input |
during a WRITE operations. DM is sampled on both edges of DQS. |
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Although DM pins are input only, the DM loading matches the DQ |
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|
|
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; |
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|
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UDM corresponds to the data on DQ8-DQ15. |
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VDD, VSS |
Power Supply |
Power Supply for the memory array and peripheral circuitry. |
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VDDQ, VSSQ |
Power Supply |
VDDQ and VSSQ are supplied to the Output Buffers only. |
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VREF |
Input |
SSTL_2 reference voltage. |
|
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|
MITSUBISHI ELECTRIC |
5 |
|
DDR SDRAM |
MITSUBISHI LSIs |
|
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
||
(Rev.1.44) |
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
|
Mar. '02 |
||
256M Double Data Rate Synchronous DRAM |
||
|
||
|
|
BLOCK DIAGRAM |
DQ0 - 15 |
UDQS,LDQS |
|
||
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|
||
DLL |
|
I/O Buffer |
QS Buffer |
|
|
Memory |
Memory |
Memory |
Memory |
|
|
Array |
|
Array |
Array |
Array |
|
Bank #0 |
Bank #1 |
Bank #2 |
Bank #3 |
|
|
Mode Register |
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Control Circuitry |
|
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Address Buffer |
|
Control Signal Buffer |
|||
|
|
Clock Buffer |
|
|
|
A0-12 |
BA0,1 |
|
/CS |
/RAS /CAS /WE |
UDM, |
|
|
CLK |
/CLK CKE |
|
LDM |
Type Designation Code |
This rule is applied to only Synchronous DRAM family. |
|
||||||||
M 2 S 56 D 3 0 A KT –75A L |
|
|||||||||
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Power Grade L: Low power, Blank: standard |
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Speed Grade10: 125MHz@CL=2.5,100MHz@CL=2.0 |
(DDR200) |
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75: 133MHz@CL=2.5,100MHz@CL=2.0 |
(DDR266B) |
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75A: 133MHz@CL=2.5,133MHz@CL=2.0 |
(DDR266A) |
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Package Type TP: TSOP(II), KT: sTSOP(Small TSOP) |
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Process Generation |
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Function Reserved for Future Use |
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||
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Organization 2 n 2: x4, 3: x8, 4: x16 |
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||
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DDR Synchronous DRAM |
|
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|
Density 56: 256M bits
Interface V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
Mitsubishi Main Designation
MITSUBISHI ELECTRIC |
6 |
|
DDR SDRAM |
MITSUBISHI LSIs |
|
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
||
(Rev.1.44) |
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
|
Mar. '02 |
||
256M Double Data Rate Synchronous DRAM |
||
|
||
|
|
BASIC FUNCTIONS
The M2S56D20/30/40A* provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. Refer to the command truth table for the detailed definition of commands.
/CLK CLK
/CS |
|
|
|
Chip Select : L=select, H=deselect |
|
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|
Command |
|
/RAS |
|
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|
Command |
|
/CAS |
|
|
|
define basic commands |
|
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/WE |
|
|
|
Command |
|
|
|
|
|
Refresh Option @refresh command |
|
CKE |
|
|
|
||
|
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|
|
Precharge Option @precharge or read/write command |
|
A10 |
|
|
|
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates one row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H in this command, the bank is deactivated after the burst read (auto - precharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is defined by burst length. When A10 =H in this command, the bank is deactivated after the burst write (auto-precharge, WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H in this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh addresses including bank address are generated internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC |
7 |
|
|
DDR SDRAM |
|
|
|
|
|
|
|
|
|
MITSUBISHI LSIs |
|||
|
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
|||||||||||||
|
(Rev.1.44) |
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
||||||||||||
|
Mar. '02 |
|||||||||||||
|
|
|
|
|
256M Double Data Rate Synchronous DRAM |
|||||||||
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|||||||||
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|
COMMAND TRUTH TABLE |
|
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COMMAND |
MNEMONIC |
|
CKE |
CKE |
/CS |
/RAS |
/CAS |
/WE |
BA0,1 |
A10 |
A0-9, |
note |
|
|
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|
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n-1 |
n |
|
|
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|
|
/AP |
11-12 |
|
|
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Deselect |
DESEL |
|
H |
X |
H |
X |
X |
X |
X |
X |
X |
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No Operation |
NOP |
|
H |
X |
L |
H |
H |
H |
X |
X |
X |
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|
Row Address Entry & |
ACT |
|
H |
H |
L |
L |
H |
H |
V |
V |
V |
|
|
|
Bank Activate |
|
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||||||||||
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Single Bank Precharge |
PRE |
|
H |
H |
L |
L |
H |
L |
V |
L |
X |
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Precharge All Banks |
PREA |
|
H |
H |
L |
L |
H |
L |
X |
H |
X |
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|
Column Address Entry |
WRITE |
|
H |
H |
L |
H |
L |
L |
V |
L |
V |
|
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& Write |
|
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||||||||||
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Column Address Entry |
WRITEA |
|
H |
H |
L |
H |
L |
L |
V |
H |
V |
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& Write with |
|
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||||||||||
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Auto-Precharge |
|
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Column Address Entry |
READ |
|
H |
H |
L |
H |
L |
H |
V |
L |
V |
|
|
|
& Read |
|
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Column Address Entry |
|
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|
& Read with |
READA |
|
H |
H |
L |
H |
L |
H |
V |
H |
V |
|
|
|
Auto-Precharge |
|
|
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|
Auto-Refresh |
REFA |
|
H |
H |
L |
L |
L |
H |
X |
X |
X |
|
|
|
Self-Refresh Entry |
REFS |
|
H |
L |
L |
L |
L |
H |
X |
X |
X |
|
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|
Self-Refresh Exit |
REFSX |
|
L |
H |
H |
X |
X |
X |
X |
X |
X |
|
|
|
|
L |
H |
L |
H |
H |
H |
X |
X |
X |
|
|
||
|
|
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|
|||||||||
|
Burst Terminate |
TERM |
|
H |
H |
L |
H |
H |
L |
X |
X |
X |
1 |
|
|
Mode Register Set |
MRS |
|
H |
H |
L |
L |
L |
L |
L |
L |
V |
2 |
|
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1.Applies only to read bursts while autoprecharge is disabled; this command is undefined (and should not be used) during read bursts while autoprecharge is enabled, as well as during write bursts.
2.BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 ,BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-codes to be written to the selected Mode Register.
MITSUBISHI ELECTRIC |
8 |
|
|
DDR SDRAM |
|
|
|
|
|
MITSUBISHI LSIs |
|||
|
|
|
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
|||||||
|
(Rev.1.44) |
|
|
|
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
|||||
|
Mar. '02 |
|
|
|
||||||
|
|
|
|
|
|
256M Double Data Rate Synchronous DRAM |
||||
|
|
|
|
|
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||||
|
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|
FUNCTION TRUTH TABLE |
|
|
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|
||||||
|
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|
Current State |
/CS |
/RAS |
/CAS |
/WE |
Address |
Command |
Action |
Notes |
|
|
IDLE |
H |
X |
X |
X |
X |
DESEL |
NOP |
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP |
|
|
|
|
L |
H |
H |
L |
BA |
TERM |
ILLEGAL |
2 |
|
|
|
L |
H |
L |
X |
BA, CA, A10 |
READ / WRITE |
ILLEGAL |
2 |
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active, Latch RA |
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
NOP |
4 |
|
|
|
L |
L |
L |
H |
X |
REFA |
Auto-Refresh |
5 |
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
Mode Register Set |
5 |
|
|
|
Mode-Add |
|
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|
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|
|
|
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|
|
|
|
|
|
ROW ACTIVE |
H |
X |
X |
X |
X |
DESEL |
NOP |
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP |
|
|
|
|
L |
H |
H |
L |
BA |
TERM |
NOP |
|
|
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ / READA |
Begin Read, Latch CA, |
|
|
|
|
Determine Auto-Precharge |
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / WRITEA |
Begin Write, Latch CA, |
|
|
|
|
Determine Auto-Precharge |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL |
2 |
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
Precharge / Precharge All |
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
READ(Auto- |
H |
X |
X |
X |
X |
DESEL |
NOP (Continue Burst to END) |
|
|
|
Precharge |
L |
H |
H |
H |
X |
NOP |
NOP (Continue Burst to END) |
|
|
|
Disabled) |
L |
H |
H |
L |
BA |
TERM |
Terminate Burst |
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
Terminate Burst, Latch CA, Begin |
|
|
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ / READA |
New Read, Determine Auto- |
3 |
|
|
|
|
|
|
|
|
|
Precharge |
|
|
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / WRITEA |
ILLEGAL |
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL |
2 |
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
Terminate Burst, Precharge |
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
MITSUBISHI ELECTRIC |
9 |
|
|
DDR SDRAM |
|
|
|
|
|
MITSUBISHI LSIs |
|||
|
|
|
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
|||||||
|
(Rev.1.44) |
|
|
|
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
|||||
|
Mar. '02 |
|
|
|
||||||
|
|
|
|
|
|
256M Double Data Rate Synchronous DRAM |
||||
|
|
|
|
|
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|
||||
|
|
|
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|
|
|
|
|
|
FUNCTION TRUTH TABLE (continued) |
|
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|||||||
|
|
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|
|
|
|
|
|
|
|
|
Current State |
/CS |
/RAS |
/CAS |
/WE |
Address |
Command |
Action |
Notes |
|
|
WRITE(Auto- |
H |
X |
X |
X |
X |
DESEL |
NOP (Continue Burst to END) |
|
|
|
Precharge |
L |
H |
H |
H |
X |
NOP |
NOP (Continue Burst to END) |
|
|
|
Disabled) |
L |
H |
H |
L |
BA |
TERM |
ILLEGAL |
|
|
|
|
|
|
|||||||
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ / READA |
Terminate Burst, Latch CA, Begin |
3 |
|
|
|
Read, Determine Auto-Precharge |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / WRITEA |
Terminate Burst, Latch CA, Begin |
3 |
|
|
|
Write, Determine Auto-Precharge |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL |
2 |
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
Terminate Burst, Precharge |
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
READ with |
H |
X |
X |
X |
X |
DESEL |
NOP (Continue Burst to END) |
|
|
|
Auto- |
L |
H |
H |
H |
X |
NOP |
NOP (Continue Burst to END) |
|
|
|
Precharge |
L |
H |
H |
L |
BA |
TERM |
ILLEGAL |
|
|
|
|
|
|
|||||||
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ / READA |
ILLEGAL for Same Bank |
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / WRITEA |
ILLEGAL for Same Bank |
6 |
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL |
2 |
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
Precharge / ILLEGAL |
2 |
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
WRITE with |
H |
X |
X |
X |
X |
DESEL |
NOP (Continue Burst to END) |
|
|
|
Auto- |
L |
H |
H |
H |
X |
NOP |
NOP (Continue Burst to END) |
|
|
|
Precharge |
L |
H |
H |
L |
BA |
TERM |
ILLEGAL |
|
|
|
|
|
|
|||||||
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ / READA |
ILLEGAL for Same Bank |
7 |
|
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / WRITEA |
ILLEGAL for Same Bank |
7 |
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL |
2 |
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
Precharge / ILLEGAL |
2 |
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
MITSUBISHI ELECTRIC |
10 |
|
DDR SDRAM |
|
|
|
|
|
MITSUBISHI LSIs |
|||
|
|
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
|||||||
(Rev.1.44) |
|
|
|
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
|||||
Mar. '02 |
|
|
|
||||||
|
|
|
|
|
256M Double Data Rate Synchronous DRAM |
||||
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
FUNCTION TRUTH TABLE (continued) |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
Current State |
/CS |
/RAS |
/CAS |
/WE |
Address |
Command |
Action |
Notes |
|
PRE- |
H |
X |
X |
X |
X |
DESEL |
NOP (Idle after tRP) |
|
|
CHARGING |
L |
H |
H |
H |
X |
NOP |
NOP (Idle after tRP) |
|
|
|
L |
H |
H |
L |
BA |
TERM |
ILLEGAL |
2 |
|
|
L |
H |
L |
X |
BA, CA, A10 |
READ / WRITE |
ILLEGAL |
2 |
|
|
L |
L |
H |
H |
BA, RA |
ACT |
ILLEGAL |
2 |
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
NOP (Idle after tRP) |
4 |
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
ROW |
H |
X |
X |
X |
X |
DESEL |
NOP (Row Active after tRCD) |
|
|
L |
H |
H |
H |
X |
NOP |
NOP (Row Active after tRCD) |
|
|
|
ACTIVATING |
|
|
|||||||
L |
H |
H |
L |
BA |
TERM |
ILLEGAL |
2 |
|
|
|
|
||||||||
|
L |
H |
L |
X |
BA, CA, A10 |
READ / WRITE |
ILLEGAL |
2 |
|
|
L |
L |
H |
H |
BA, RA |
ACT |
ILLEGAL |
2 |
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
ILLEGAL |
2 |
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
WRITE RE- |
H |
X |
X |
X |
X |
DESEL |
NOP |
|
|
L |
H |
H |
H |
X |
NOP |
NOP |
|
|
|
COVERING |
|
|
|||||||
L |
H |
H |
L |
BA |
TERM |
ILLEGAL |
2 |
|
|
|
|
||||||||
|
L |
H |
L |
X |
BA, CA, A10 |
READ / WRITE |
ILLEGAL |
2 |
|
|
L |
L |
H |
H |
BA, RA |
ACT |
ILLEGAL |
2 |
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
ILLEGAL |
2 |
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
MITSUBISHI ELECTRIC |
11 |
|
|
DDR SDRAM |
|
|
|
|
|
MITSUBISHI LSIs |
|||
|
|
|
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 |
|||||||
|
(Rev.1.44) |
|
|
|
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10 |
|||||
|
Mar. '02 |
|
|
|
||||||
|
|
|
|
|
|
256M Double Data Rate Synchronous DRAM |
||||
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
FUNCTION TRUTH TABLE (continued) |
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
Current State |
/CS |
/RAS |
/CAS |
/WE |
Address |
Command |
Action |
Notes |
|
|
REFRESHING |
H |
X |
X |
X |
X |
DESEL |
NOP (Idle after tRFC) |
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP (Idle after tRFC) |
|
|
|
|
L |
H |
H |
L |
BA |
TERM |
ILLEGAL |
|
|
|
|
L |
H |
L |
X |
BA, CA, A10 |
READ / WRITE |
ILLEGAL |
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
ILLEGAL |
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
ILLEGAL |
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
MODE |
H |
X |
X |
X |
X |
DESEL |
NOP (Idle after tMRD) |
|
|
|
REGISTER |
L |
H |
H |
H |
X |
NOP |
NOP (Idle after tMRD) |
|
|
|
SETTING |
L |
H |
H |
L |
BA |
TERM |
ILLEGAL |
|
|
|
|
|
|
|||||||
|
|
L |
H |
L |
X |
BA, CA, A10 |
READ / WRITE |
ILLEGAL |
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
ILLEGAL |
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / PREA |
ILLEGAL |
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
Mode-Add |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1.All entries are valid only when CKE was High during the preceding clock cycle and the current clock cycle.
2.ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of specific bank.
3.Must satisfy bus contention, bus turn around, write recovery requirements.
4.NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5.ILLEGAL if any bank is not idle.
6.Refer to Read with Auto-Precharge in page 27.
7.Refer to Write with Auto-Precharge in page 29.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC |
12 |
|