The LC370EUN is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED
backlight system . The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 37 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7M(true) colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
LVDS
2Port
LVDS
Select
CN1
(51pin)
+12.0V
ExtVBR-B
+24.0V, GND, On/Off
LVDS 1,2
Option
I2C
EEPROM
SCL
Timing Controller
LVDS Rx + DGA
Power Circuit
SDA
Block
Power Signals
Mini-LVDS(RGB)
Signals
General Features
Active Screen Size37 inches(940.091mm) diagonal
Outline Dimension
856.4(H) × 501.0(V) X 10.8(B)/23.6 mm(D) (Typ.)
Source Driver Circuit
S1S1920
G1
-
(1920 × RGB × 1080 pixels)
[Gate In Panel]
G1080
Backlight AssemblyLED Driver
Pixel Format1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60
minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (ExtV
BR-B : 100%), it is total power consumption.
2. The life time (MTTF) is determined as the time which luminance of the LED is 50% compared to that of initial
value at the typical LED current (ExtV
BR-B :100%) on condition of continuous operating inLCM state at
25±2°C.
V_
Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected.
4. The duration of rush current is about 200ms. This duration is applied to LED on time.
5. Even though inrush current is over the specified value, there is no problem if I2T spec of fuse is satisfied.
6. ExtVBR-B signal have to input available duty range and sequence.
After Driver ON signal is applied, ExtVBR-B should be sustained from 5% to 100% more than 500ms.
After that, ExtVBR-B 1% and 100% is possible
For more information, please see 3-6-2. Sequence for LED Driver.
Ver. 1.0
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LC370EUN
This LCD module employs two kinds of interface connection
pin connector is used for the module
Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION
15
R1BP
FIRST LVDS R
(B+)
41NCNo C
24
NC
No C
50
VLCD
Power Supply +12.0V
(
(g)gyg
Product Specification
3-2. Interface Connections
, 51-
electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-RE51S-HF(manufactured by JAE) or IS050-C51B-C39(manufactured by UJU)
Refer to below and next Page table.
- Mating Connector : FI-R51HL(JAE) or compatible
NoSymbolDescriptionNoSymbolDescription
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
20
21
22
23
25
26
NC
NC
NC
NC
NC
NC
LVDS Select
NC
NC
NC
GND
R1AN
R1AP
R1BN
R1CN
R1CP
GND
R1CLKN
R1CLKP
GND
R1DN
R1DP
NC
NC or GND
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
‘H’ =JEIDA , ‘L’ or NC = VESA
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
eceiver Signal
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)
Ground
FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)
Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
Horizontal
Vertical
Frequency
Display
Period
BlanktHB5070120tCLK1
TotaltHP530550600tCLK
Display
Period
BlanktVB
TotaltVP
ITEMSymbolMinTypMaxUnitNote
DCLKfCLK63.0074.2578.00MHz
VerticalfV
HV480480480tCLK1920 / 4
t
tVV108010801080Lines
20
(228)
1100
(1308)
57
(47)
45
(270)
1125
(1350)
60
(50)
69
(300)
1149
(1380)
63
(63)
Lines1
Lines
Hz
NTSC : 57~63Hz
(PAL : 47~53Hz)
2
Note 1. The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
If you use spread spectrum for EMI, add some additional clock to minimum value for clock margin.
-
refresh rate and the horizontal frequency.
3. Timing should be set based on clock frequency.
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3-4. LVDS Signal Specification
t
VB
t
VFP
tWVt
VBP
3-4-1. LVDS Input Signal Timing Diagram
LC370EUN
Product Specification
DE, Data
DCLK
First data
Second data
0.7VDD
0.3VDD
tCLK
0.5 VDD
Invalid data
Invalid data
DE(Data Enable)
Pixel 0,0
Pixel 1,0
Valid data
Pixel 2,0
Valid data
Pixel 3,0
Invalid data
Invalid data
tHV
DE(Data Enable)
Ver. 1.0
tHP
11080
tVV
tVP
* tHB = tHFP + tWH +tHBP
*
=
+
+
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