Lenovo LA-5752P Schematics

A

1 1

B

C

D

E

Compal Confidential

NIWE2

2 2

Schematics Document

Arrandale

with Intel IBEX PEAK-M core logic

3 3

REV:0.3

4 4

http://hobi-elektronika.net

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F COMPAL ELECTRONICS, INC. AND CONTAI NS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETE NT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE IN FORMATI ON IT C ONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECT RONICS, INC.

2008/03/25 2008/04/

C

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Cover Sheet

Size Document Number Re v

Custom

LA-5752P

D

Date : Sheet

E

of

151Thursday, October 29, 2009

0.3

A

Compal confidential

File Name :

ZZZ

15.6W_PCB_LA5752P

1 1

HDMI
CONN

page24

VRAM 64*16

DDR3*4

page20

NVidia N11M-GE1

page19~23

level shift IC

ASM1442

page25

PCI-E X16

B

intel
Arrandale
(UMA/DIS)

C

POWER BD: LS-5754P
POWER BT
NOVO BT
POWER MANAGE BT

D

CAP SENSOR BD:LS-5752P
VOLUME UP
VOLUME DOWN
MUTE
AUDIO ENHANCE

E

CARD READER BD:
LS-5753P
RTS5138
HP JACK
MIC JACK

BUTTON & LED

Clock Generator

ICS9LRS3199AKLFT

page12

Socket-rPGA989

37.5mm*37.5mm

page5~9

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

page 10,11

Dual Channel

100MHz

2.7GT/s

FDI *8

DMI *4

DDR3-800(1.5V)
DDR3-1067(1.5V)

UP TO 8G

2Channel Speaker

page33

CRT Connector

page26

2 2

LVDS
Connector

page27

PCI Express
Mini card Slot 1

page28

6*PCI-E BUS

PCI Express
Mini card Slot 2

SIM Card

3 3

page28

page28

USB(WWAN)

SPI ROM
BIOS

page13

RTL8111DL-VB-GR

10/100/1G LAN

RJ45 CONN

page29

page30

Intel Ibex Peak M

FCBGA 951

25mm*25mm

LPC BUS

EC

ENE KB926D

Touch Pad

page35

page 13~18

page34

Int.KBD

SPI ROM

AZALIA

14*USB2.0

6*SATA serial

page35

page36

Audio Codec

Conexant
CX20671

page33

CMOS Camera

BlueTooth CONN

USB CONN X1(Right)

USB PORT X1(Left)

New Card X1

WWAN

SATA HDD CONN

page32

page27

page37

page28

page28

Analog MIC_Int

page37

page37

Card Reader/Audio Jack SB
CONN

Realtek 5138
MS/MS
pro/SD/SD
pro/mmc/XD

page33

HP X 1+
MIC_Ext X1

ESATA HDD AND USB CONN

page38

page37

4 4

http://hobi-elektronika.net

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFID ENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CON TAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, IN C.

C

2008/03/24 2008/04/

SATA ODD CONN

Compal Secret Data

Deciphered Date

page32

Title

Size Docu ment Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

MB Block Diagram

LA-5752P

251Thurs day, October 29, 2009

E

0.3

of

A

B

C

D

E

DDR3 Voltage Rails

SMBUS Control Table

N10x
Thermal
Sensor

X

X

X

XX

X

XX

X

X

V

+3VS

X

X

+3VS

X

WLAN
WWAN

+5VS

power
plane

1 1

+B

State

+5VALW

+3VALW

+1.5V

+3VS

+1.5VS

+VCCP

+CPU_CORE

+VGA_CORE

+1.8VS

+0.75VS

+1.05VS

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

SOURCE

KB926

+3VALW

KB926

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

RAM
M2

X V

X

V

+3VALW

X

BATT KE926 SOD IMM CL K CHIP

+3VALW

X

X

X

X

X

X

V

+3VALW

X

X

VV

+3VS

X

N10x

X

X

X

Cap sensor
board

+3VS

NEW

PCH

CARD

X

XX

X

X

V

XX

X

V

+3VALW

V

+3VS

X

X

XXXX XXX X

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O

O

O

X

O

O

O

X

O

XX

X

OO

X

X

XX X

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

DDR SO-DIMM 1

CLOCK GENERATOR ( EXT. )

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

@ FUNCTION

EVT NON-USE

45@
100@ 10/100 LAN
GIGA@

UMA_HDMI@

HDMI@

3 3

3G@
X76@
ESATA@
CMOS@
BT@ Blue Tooth
10M@
11M@
UMA@
DIS@
VGA@ FOR NVIDIA PART

HYBRID@ FOR SWITCHABLE

HU@
HD@

SKU

Arrandale(dGPU)

4 4

http://hobi-elektronika.net

DIS only

Arrandale(iGPU)

UMA only

Arrandale(iGPU+dGPU)

SWITCHABLE

A

(45 BOM)

GIGA LAN

FOR UMA HDMI components

FOR HDMI components
3G(WWAN) function
(X76 BOM)
ESATA function
Camera function

FOR 10M CHIP
FOR 11M CHIP
UMA only (Arranddale)
DIS only (Arranddale)

SWITCHABLE or UMA only
SWITCHABLE or DIS only

DIS@ / 100@ for EVT

UMA@ / 100@ for EVT

VGA@+HD@+HU@+HYBRID@

PCIE PORT LIST

DEVICEPORT

1
2

LAN

3

3G

4

NEW CARD

5
6
7
8

USB PORT LIST

DEVICEPORT

RIGHT SIDE0
LEFT SIDE

1WLAN

CMOS

2

LEFT SIDE

3
4

RIGHT SIDE

CARD READER

5
6
7

WIRELESS8
9
10

NEW CARD

BT

11
12
13

3G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFID ENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CON TAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, IN C.

C

2008/03/24 2008/04/

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

B

D

Date: Sheet

Compal Electronics, Inc.

MB Notes List

LA-5752P

351Th ursday, October 29, 2009

E

0.3

of

A

B

C

D

E

Performance Mode P0 TDP at Tj = 102 C* (DDR3)VGA and DDR3 Voltage Rails (N10x GPIO)

GPIO I/O ACTIVE Function Description

GPIO0

GPIO1

GPIO2

1 1

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

2 2

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

3 3

N/A

N/A

-

IN

H

OUT

H

OUT

H

OUT

OUT

-

OUT

-

OUT

-

L

I/O

L

OUT

OUT

I/O

L

IN

-

OUT

-

OUT

- Power supply control

-

IN

-

OUT

-

IN

-

IN

-

IN

-

IN

-

IN

-

IN

I/O

Hot plug detect for IFP link C

Panel Back-Light brightness(PW M capable)

Panel Power Enable

Panel Back-Light On/Off (PWM)

GPU VID0

GPU VID1

GPU VID2

Thermal Catastrophic Overtemp

Thermal Alert

Memory VREF switch

SLI raster sync

AC power detect pin

MEM_VID orPower supply control

Hot plug detect for IFP Link E

Programmable Fan Control

Hot plug detect for IFP Link D

Hot plug detect for IFP link F

SLI swap ready signal

Products

N10P-GS
128bit
1024MB
DDR3

N10P-GE
128bit
1024MB
DDR3

N10P-LP
128bit
1024MB
DDR3

Performance Mode P0 TDP at Tj = 102 C* (DDR3)

Products

N10M-GE
64bit
512MB
DDR3

N10M-GS
64bit
512MB
DDR3

N10M-LP
64bit
512MB
DDR3

Power Sequence

(+3VS)

(1.05VS)

(+VGA_CORE)

GPIO6

GPU_VID1 GPU_VID0 VGA_CORE

GPIO5 N10M-GS N10P-GS

P-State

0.8V

(1.8VS)IFPAB_IOVDD

GPU M em NVC L K
(4) (1,5) (6)

(W) (W)

21.07

20.97

15.48

GPU M e m NV CL K
(4) (1,5) (6)

(W) (W)

13.36

14.29

8.28

/MCLK NVVDD

(MHz)

6.67

TBD

6.73

TBD

6.44

TBD

/MCLK NVVDD

(MHz)

2.93

TBD

3.10

TBD

2.91

TBD

(V) (A) (W ) (A) (W) (A) (W ) (W )(mA) (W) (W) (W)(mA) (mA) (mA)

18.25

TBD

19.17

TBD

13.95

TBD

(V) (A) (W ) (A) ( W)

11.89

TBD

11.53

TBD

6.60

TBD

The ramp time for any rail must be more than 40us

VDD33

PEX_VDD

NVVDD

17.34

17.25

11.86

10.70

11.53

5.61

tNVVDD

FBVDD

2.06

2.03

1.90

FBVDD

0.66

0.70

0.62

01120.85V 12

10000.9V

11

1.0V (N10M-GS)

0.925V (N10P-GS)

0,10

(1.5VS)

FBVDDQ

FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.5V)(1.5V)

4.09

3.09

4.09 6.14

3.05

2.85

3.99

FBVDDQ PCI Expres s I/O and
(GPU+Mem)
(1.5V)(1.5V)

(A) ( W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

2.16

0.99

2.28 3.42

1.05

0.93

2.20

(1.05V)

6.14

850 75 0.14

5.99

810

(1.05V)

3.24

792 75 0.14

3.3

782

0.89

0.88840

0.85

0.83

0.86817

0.82

PLLVDD

75 0.14

75 0.14

PLLVDD

75 0.14

75 0.14

PEX_VDD can ramp up any time

tNV-IFPAB_IOVDD

tNV-FBVDDQ

I/O and
PLLVDD

63 0.07

63 0.07

63 0.07

I/O and
PLLVDD

63 0.07

63 0.07

63 0.07

Other

(3.3V)(1.05V)(1.8V)

55 0.18

55 0.18

55 0.18

Other

(3.3V)(1.05V)(1.8V)

100 0.33

100 0.33

100 0.33

4 4

http://hobi-elektronika.net

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFID ENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CON TAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, IN C.

C

2009/03/16 2010/03/15

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

B

D

Date: Sheet

Compal Electronics, Inc.

VGA Notes List

LA-5752P

451Th ursday, October 29, 2009

E

0.3

of

5

D D

C C

VCCP_POK<46>

FROM POWER VTT
POWER GOOD SIGNAL

B B

R184

1K_04 02_1%

12

Layout rule 10mil width Κtrace
length < 0.5", spacing 20mil

+VCCP

H_PROCHOT#<34,48>

H_THERMTRIP#<16>

+VCCP

H_PM_SYNC<15>

H_CPUPWRGD<16>

PM_DRAM_PWRGD<15>

R183
560_0402_5%

1 2

BUF_PLT_RST#<16,19,28,29>

R564 0_0402_5%

H_PECI<16>

+VCCP

1.5K_ 0402_5%

4

R56020_0402_1%

1 2

R55820_0402_1%

1 2

R54849.9_0402_1%

1 2

R55749.9_0402_1%

1 2

TP_SKTOCC#

12

R16349.9_0402_1%

H_PECI_ISO

1 2

R569 68_0402_5%

12

H_PROCHOT#

H_THERMTRIP#

H_CPURST #_R

12

R13568_0402_5%

H_P M_SYNC_R

R187

1 2

0_0402_5%

VCCPWRGOOD_1

R190

1 2

0_0402_5%

VCCPWRGOOD_0

R139

1 2

0_0402_5%

VDDPW RGOOD_R

R191

1 2

0_0402_5%

R185

PLT_ RST#_R

1 2

12

COMP3

COMP2

COMP1

COMP0

H_CATERR#

VTT_POK

R186
750_0402_1%

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R1P0

ME@

MISC THERMAL

PWR MANAGEMENT

CLOCKS

DDR3

MISC

JTAG & BPM

3

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#
PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

A16
B16

AR30
AT30

E16
D16

A18
A17

F6

AL1
AM1
AN1

AN15
AP15

AT28
AP27

AN28

TCK

AP28

TMS

AT27

AT29

TDI

AR27

TDO

AR29
AP29

AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_EXP
CLK_EXP#

SM_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PM_EXTTS#0
PM_EXTTS#1

XDP_PRDY#
XDP_PREQ#

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI
XDP_TDO

R555 0_0402_5%

XDP_DBRESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

T17 P AD
T18 P AD

3

1 2

R563 0_0402_5%

T19 PA D

12

CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>

CLK_EXP <14>

pins unused by
Clarksfield on the
rPGA989 Package

CLK_EXP# <14>

PM_E XTTS#1_R < 10,11 >

2

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

PM_EXTTS#0

PM_EXTTS#1

XDP_PREQ#

XDP_TMS

XDP_TDI

XDP_TDO

XDP_TCK

XDP_TRST#

XDP_DBRESET#

1 2

R567 100_0402_1%

1 2

R566 24.9_0402_1%

1 2

R565 130_0402_1%

Layout Note:Please these
resistors near Processor

1 2

R56 1 10K_0 402_5%

1 2

R56 2 10K_0 402_5%

R136 51_0402_1%@

1 2

R138 51_0402_1%@

1 2

R556 51_0402_1%@

1 2

R134 51_0402_5%

1 2

R57 51_0402_1%@

1 2

R133 51_0402_5%

1 2

R137

1K_04 02_5%@

1 2

1

+VCCP

+3VS

CHECK INTEL DOCUMENT #385422

Debug Port Design Guide Rev1.3

+1.5V

For Intel S3 Power Reduction.

5

+3VALW

5

U8

2

P

B

DRAM_PWRGD

VCCP_POK<46>

A A

VCCP_POK

2N7002_SOT23

5

4

Y

1

A

G

MC74VHC1G08DFT2G SC70 5P

3

+5VALW

12

R610
10K_0 402_5%

S3_0.75V_EN

13

D

2

G

Q42

S

4

R195

1 2

1.5K_ 0402_1%

750_0402_1%

S3_0.75V_EN <44>

R194

12

+1.5V

12

R193

1.1K_ 0402_1%

@

VDDPW RGOOD_R

12

R192
3K_04 02_1%

@

R301

DDR3 CONNECTER

DRAMRST#<10,11>

PCH GPIO CONTROL

DRAMRST_CNTRL_PCH<16>

DRAMRST_CNTRL_EC<34>

EC GPIO CONTROL

1K_04 02_1%

1 2

1 2

R281 0_0402_5%

1 2

R282 0_0402_5%@

1 2

DRAMRST# SM_DRAMRST#

2N7002_SOT23

DRAMRST_CNTRL_R

C338

6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

For Intel S3 Power Reduction.

@

R3000_0402_5%

D

S

1 3

Q27

G

2

1

0.01U_0402_16V7K

2

2

12

R283 100K_0402_5%

Title

Size D ocument Number Re v

Custom

Date: Sheet

3

Compal Electronics, Inc.

Arrandale(1/5)-Thermal/XDP

LA-5752P

1

551Thursday, October 29, 2009

0.3

of

http://hobi-elektronika.net

5

JCPU1A

DMI_CRX_PT X_N0<15>
DMI_CRX_PT X_N1<15>
DMI_CRX_PT X_N2<15>
DMI_CRX_PT X_N3<15>

DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>

D D

DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>
FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>

C C

FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15>
FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15>
FDI_LSYNC1<15>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

A24
C23
B22
A21

B24
D23
B23
A22

D24
G24
F23
H23

D25
F24
E23
G23

E22
D21
D19
D18
G21
E19
F21
G18

D22
C21
D20
C18
G22
E20
F20
G19

F17
E17

C17

F18
D17

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

FDI_FSYNC[0]
FDI_FSYNC[1]

FDI_INT

FDI_LSYNC[0]
FDI_LSYNC[1]

PEG_RCOMPO

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

B B

FDI_FSYNC0

FDI_FSYNC1

FDI_INT

FDI_LSYNC0

FDI_LSYNC1

A A

IC,AUB_CFD_rPGA,R1P0

ME@

R53 2 1K_0402_5%DIS@

1 2

R53 6 1K_0402_5%DIS@

1 2

R53 4 1K_0402_5%DIS@

1 2

R53 3 1K_0402_5%DIS@

1 2

R53 5 1K_0402_5%DIS@

1 2

PEG_ICOMPI

PEG_ICOMPO

PEG_RBIAS

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

4

EXP_ICOMPI

EXP_RBIAS

PCIE _CRX_GTX_N15
PCIE _CRX_GTX_N14
PCIE _CRX_GTX_N13
PCIE _CRX_GTX_N12
PCIE _CRX_GTX_N11
PCIE _CRX_GTX_N10

PCIE _CRX_GTX_N9
PCIE _CRX_GTX_N8
PCIE _CRX_GTX_N7
PCIE _CRX_GTX_N6
PCIE _CRX_GTX_N5
PCIE _CRX_GTX_N4
PCIE _CRX_GTX_N3
PCIE _CRX_GTX_N2
PCIE _CRX_GTX_N1
PCIE _CRX_GTX_N0

PCIE _CRX_GTX_P15
PCIE _CRX_GTX_P14
PCIE _CRX_GTX_P13
PCIE _CRX_GTX_P12
PCIE _CRX_GTX_P11
PCIE _CRX_GTX_P10
PCIE_CRX_G TX_P9
PCIE_CRX_G TX_P8
PCIE_CRX_G TX_P7
PCIE_CRX_G TX_P6
PCIE_CRX_G TX_P5
PCIE_CRX_G TX_P4
PCIE_CRX_G TX_P3
PCIE_CRX_G TX_P2
PCIE_CRX_G TX_P1
PCIE_CRX_G TX_P0

PCIE _CTX_GRX_C_N15
PCIE _CTX_GRX_C_N14
PCIE _CTX_GRX_C_N13
PCIE _CTX_GRX_C_N12
PCIE _CTX_GRX_C_N11
PCIE _CTX_GRX_C_N10
PCIE _CTX_GRX_C_N9
PCIE _CTX_GRX_C_N8
PCIE _CTX_GRX_C_N7
PCIE _CTX_GRX_C_N6
PCIE _CTX_GRX_C_N5
PCIE _CTX_GRX_C_N4
PCIE _CTX_GRX_C_N3
PCIE _CTX_GRX_C_N2
PCIE _CTX_GRX_C_N1
PCIE _CTX_GRX_C_N0

PCIE _CTX_GRX_C_P15
PCIE _CTX_GRX_C_P14
PCIE _CTX_GRX_C_P13
PCIE _CTX_GRX_C_P12
PCIE _CTX_GRX_C_P11
PCIE _CTX_GRX_C_P10
PCIE _CTX_GRX_C_P9
PCIE _CTX_GRX_C_P8
PCIE _CTX_GRX_C_P7
PCIE _CTX_GRX_C_P6
PCIE _CTX_GRX_C_P5
PCIE _CTX_GRX_C_P4
PCIE _CTX_GRX_C_P3
PCIE _CTX_GRX_C_P2
PCIE _CTX_GRX_C_P1
PCIE _CTX_GRX_C_P0

R544 49.9_0402_1%

1 2

R545 750_0402_1%

1 2

Layout rule trΚace
length < 0.5"

PCIE _CRX_GT X_N[0..15] <19>

PCIE _CRX_GTX_P[ 0..15] <19>

3

PCIE Lane Numbers Reversed
CFG3-PCI Express Static Lane Reversal

VGA@

C527 0.1U_0402_10V 6K

1 2

C540 0.1U_0402_10V 6K

1 2

C529 0.1U_0402_10V 6K

1 2

C542 0.1U_0402_10V 6K

1 2

C531 0.1U_0402_10V 6K

1 2

C544 0.1U_0402_10V 6K

1 2

C533 0.1U_0402_10V 6K

1 2

C546 0.1U_0402_10V 6K

1 2

C535 0.1U_0402_10V 6K

1 2

C562 0.1U_0402_10V 6K

1 2

C564 0.1U_0402_10V 6K

1 2

C555 0.1U_0402_10V 6K

1 2

C557 0.1U_0402_10V 6K

1 2

C561 0.1U_0402_10V 6K

1 2

C548 0.1U_0402_10V 6K

1 2

C559 0.1U_0402_10V 6K

1 2

C528 0.1U_0402_10V 6K

1 2

C541 0.1U_0402_10V 6K

1 2

C530 0.1U_0402_10V 6K

1 2

C543 0.1U_0402_10V 6K

1 2

C532 0.1U_0402_10V 6K

1 2

C545 0.1U_0402_10V 6K

1 2

C534 0.1U_0402_10V 6K

1 2

C547 0.1U_0402_10V 6K

1 2

C536 0.1U_0402_10V 6K

1 2

C563 0.1U_0402_10V 6K

1 2

C565 0.1U_0402_10V 6K

1 2

C556 0.1U_0402_10V 6K

1 2

C558 0.1U_0402_10V 6K

1 2

C560 0.1U_0402_10V 6K

1 2

C549 0.1U_0402_10V 6K

1 2

C550 0.1U_0402_10V 6K

1 2

PCIE _CTX_GRX_N15
PCIE _CTX_GRX_N14
PCIE _CTX_GRX_N13
PCIE _CTX_GRX_N12
PCIE _CTX_GRX_N11
PCIE _CTX_GRX_N10
PCIE _CTX_GRX_N9
PCIE _CTX_GRX_N8
PCIE _CTX_GRX_N7
PCIE _CTX_GRX_N6
PCIE _CTX_GRX_N5
PCIE _CTX_GRX_N4
PCIE _CTX_GRX_N3
PCIE _CTX_GRX_N2
PCIE _CTX_GRX_N1
PCIE _CTX_GRX_N0

PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0

PCIE _CTX_GR X_N[0..15] <19>

PCIE _CTX_GRX_P[0..15] <19>

CFG Straps for PROCESSOR

CFG0

CFG3

CFG4

R59

@

FOR ES1 SAMPLE ONLY

@

1 2

R58 3.0 1K_0402_1%

PCI-Express Configuration Select

1: Single PEG

CFG0

Not applicable for Clarksfield Processor

CFG[1:0] 11=1*16 PEG

0: Bifurcation enabled

10=2*8 PEG

1 2

R61 3.0 1K_0402_1%

CFG3-PCI Express Static Lane Reversal

1: Normal Operation

CFG3

0: Lane Numbers Reversed

15 -> 0, 14 ->1, .....

@

1 2

R60 3.0 1K_0402_1%

CFG4-Display Port Presence

1: Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

0: Enabled; An external Display Port
device is connected to the Embedded
Display Port

1 2

3.01K _0402_1%

R547
0_0402_5%

@

1 2

@

1 2

R546
0_0402_5%

CFG0

CFG3
CFG4

CFG7

H_RS VD17_R
H_RS VD18_R

2

JCPU1E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_rPGA ,R1P0

ME@

RSVD_NCTF_37

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RESERVED

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD38
RSVD39

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53

RSVD58

RSVD_TP_59
RSVD_TP_60

RSVD62
RSVD63
RSVD64
RSVD65

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

1

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2

KEY

D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

VSS

RSV D64_R
RSV D65_R

R189
0_0402_5%

R188
0_0402_5%

@

12

@

12

5

http://hobi-elektronika.net

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Title

Size D ocument Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Arrandale(2/5)-DMI/PEG/FDI

LA-5752P

1

651Thursday, October 29, 2009

of

0.3

5

4

3

2

1

AR10
AT10

JCPU1D

W8

SB_CK[0]

W9

SB_CK#[0]

B5

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

AC5

SB_CAS#

Y7

SB_RAS#

AC6

SB_WE#

DDR SYSTEM MEMORY - B

SB_CKE[0]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_DM 0
DDR_B_DM 1
DDR_B_DM 2
DDR_B_DM 3
DDR_B_DM 4
DDR_B_DM 5
DDR_B_DM 6
DDR_B_DM 7

DDR_B_DQS #0
DDR_B_DQS #1
DDR_B_DQS #2
DDR_B_DQS #3
DDR_B_DQS #4
DDR_B_DQS #5
DDR_B_DQS #6
DDR_B_DQS #7

DDR_B _DQS0
DDR_B _DQS1
DDR_B _DQS2
DDR_B _DQS3
DDR_B _DQS4
DDR_B _DQS5
DDR_B _DQS6
DDR_B _DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 <11>
M_CLK_DDR#2 <11>
DDR_CKE2_DIMMB <11>

M_CLK_DDR3 <11>
M_CLK_DDR#3 <11>
DDR_CKE3_DIMMB <11>

DDR_CS2_DIMMB# <11>
DDR_CS3_DIMMB# <11>

M_ODT2 <11>
M_ODT3 <11>

DDR_B_DM [0..7] <11>

DDR_B_DQ S#[0..7] < 11>

DDR_B_DQS[0..7] <11>

DDR_B_MA[0..15] <11>

JCPU1C

D D

DDR_A_D[0..63]<10>

C C

B B

DDR_A_BS0<10>
DDR_A_BS1<10>
DDR_A_BS2<10>

DDR_A_CAS#<10>
DDR_A_RAS#<10>
DDR_A_WE#<10>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AJ10

AL10

AK12

AK11

AM10
AR11
AL11

AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14

A10

SA_DQ[0]

C10

SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]

G10

SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39]
SA_DQ[40]

AJ9

SA_DQ[41]
SA_DQ[42]
SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45]
SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

U7

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]

SA_DM[1]

SA_DM[2]

SA_DM[3]

SA_DM[4]

SA_DM[5]

SA_DM[6]

SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_DM 0
DDR_A_DM 1
DDR_A_DM 2
DDR_A_DM 3
DDR_A_DM 4
DDR_A_DM 5
DDR_A_DM 6
DDR_A_DM 7

DDR_A_DQS #0
DDR_A_DQS #1
DDR_A_DQS #2
DDR_A_DQS #3
DDR_A_DQS #4
DDR_A_DQS #5
DDR_A_DQS #6
DDR_A_DQS #7

DDR_A _DQS0
DDR_A _DQS1
DDR_A _DQS2
DDR_A _DQS3
DDR_A _DQS4
DDR_A _DQS5
DDR_A _DQS6
DDR_A _DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
DDR_CKE0_DIMMA <10>

M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
DDR_CKE1_DIMMA <10>

DDR_CS0_DIMMA# <10>
DDR_CS1_DIMMA# <10>

M_ODT0 <10>
M_ODT1 <10>

DDR_A_DM [0..7] <10>

DDR_A_DQ S#[0..7] <10>

DDR_A_DQS[0..7] <10>

DDR_A_MA[0..15] <10>

DDR_B_D[0..63]<11>

DDR_B_BS0<11>
DDR_B_BS1<11>
DDR_B_BS2<11>

DDR_B_CAS#<11>
DDR_B_RAS#<11>
DDR_B_W E#<11>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

IC,AUB_CFD_rPGA,R1P0

ME@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

IC,AUB_CFD_rPGA ,R1P0

ME@

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

Arrandale(3/5)-DDR III

LA-5752P

1

0.3

of

751Thursday, October 29, 2009

http://hobi-elektronika.net

5

+CPU_CORE

JCPU1F

D D

C C

B B

A A

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,AUB_CFD_rPGA ,R1P0

ME@

CPU CORE SUPPLY

5

1.1V RAIL POWER

POWER

PROC_DPRSLPVR

CPU VIDS

VSS_SENSE_VTT

SENSE LINES

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT

ISENSE

VCC_SENSE
VSS_SENSE

VTT_SENSE

PSI#

AH14

10U_0805_10V4K

AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

VTT_SELECT

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PM_DPRSLPVR_R

10U_0805_10V4K

C201

1

2

1

2

C199

1

2

10U_0805_10V4K

10U_0805_10V4K

C270

C271

1

@

2

10U_0805_10V4K

C208

1

1

2

2

R608 1K _0402_5%

1 2

R56 0_0402_5%

1

2

1

@

2

+VCCP

10U_0805_10V4K

C209

1 2

PSI# <48>

H_VI D[0..6] <48>

H_VTTVID1 = Low, 1.1V FOR Clarksfiel

H_VTTVID1 = High, 1.05V FOR Auburndale

AN35

AJ34
AJ35

B15
A15

VCC_SENSE
VSS_SENSE

IMVP _IMON <48>

0_0402_5%

R554

1 2
1 2

R553 0_0402_5%

VTT_SENSE <46>

@

T15PAD

Close to CPU

VCCSENSE

VSSSENSE

1 2

R552 100_0402_1%

1 2

R551 100_0402_1%

10U_0805_10V4K

C198

10U_0805_10V4K

C216

10U_0805_10V4K

1

2

10U_0805_10V4K

1

2

1

2

VCCSENSE
VSSSENSE

4

C181

1

+

2

C182

1

2

10U_0805_10V4K

C219

+CPU_CORE

4

+VCCP

330U_D2_2.5VY_R9M

C554

10U_0805_10V4K

C200

+VCCP

10U_0805_10V4K

10U_0805_10V4K

C274

C217

1

1

2

2

PROC_DPRSLPVR <48>

VTT_SELECT <46>

VCCSENSE <48>
VSSSENSE <48>

3

+GFX_CORE

22U_0805_6.3V6M

1

C160

C161

@

2

22U_0805_6.3V6M

12

R559
0_0402_5%

DIS@

10U_0805_10V4K

C207

1

2

CPU

1

C191

@

2

22U_0805_6.3V6M

1

SUSP<39,44,45>

22U_0805_6.3V6M

1

C190

@

2

22U_0805_6.3V6M

1

1

C189

@

UMA@

2

2

22U_0805_6.3V6M

+VCCP

1

2

+1.5V +1.5V_DDR3

+5VALW

R268
20K_0 402_5%

1.5V_DDR3_GATE

13

D

2

G

S

3

1

1

C591

C159

UMA@

UMA@

2

2

10U_0805_6.3V6M

10U_0805_10V4K

10U_0805_10V4K

C215

C214

1

2

J3

2

JUMP_43X118

@

J2

2

JUMP_43X118

@

U11

8

D

7

D

6

D

5

D

SI4800BDY-T1-E3_SO8

Q23
2N7002_SOT23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

10U_0805_6.3V6M

1

C592

UMA@

2

+VCCP

10U_0805_10V4K

C210

1

2

10U_0805_10V4K

C272

1

2

112

112

1

S

2

S

3

S

4

G

R267
0_0402_5%

@

1 2

1

2

1

2

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

10U_0805_10V4K

C211

10U_0805_10V4K

C240

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R1P0

ME@

GRAPHICS

FDI PEG & DMI

For Intel S3 Power Reduction.

0.1U_0402_10V6K

0.1U_0402_10V6K

C289

1

1

2

+1.5V_DDR3

1

C325

0.1U_0603_25V7K

2

2008/10/31 2009/10/31

2

Compal Secret Data

POWER

+1.5V

0.1U_0402_10V6K

C288

C287

1

2

Deciphered Date

2

SENSE

GRAPHICS VIDs

3A

0.6A

0.1U_0402_10V6K

1

2

2

LINES

VAXG_SENSE

VSSAXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

DDR3 - 1.5V RAILS

1.1V1.8V

VCCPLL1
VCCPLL2
VCCPLL3

C286

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

AN24

GFX_VR_EN

AR25
AT25

GFX_IMON

AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

2

SUSP

UMA@

1 2

1U_0603_10V4Z

1U_0603_10V4Z

C254

1

1

2

2

22U_0805_6.3V6M

220U_B2_2.5VM_R35

C268

1

1

+

@

2

2

1U_0603_10V4Z

1U_0603_10V4Z

C167

C149

1

2

1

1

2

2

+1.5V_DDR3

0.1U_0402_10V6K
C269

1

@

2

2

G

For Intel S3 Power Reduction.

1

GFX_IMON

R132

DIS@

1K_04 02_5%

12

AS NO CONNECT

BUT A SMALL AMOUNT OF POWER

VCC_AXG_SENSE <47>
VSS_AXG_SENSE <47>

GFXV R_VID_0 <47>
GFXV R_VID_1 <47>
GFXV R_VID_2 <47>
GFXV R_VID_3 <47>
GFXV R_VID_4 <47>
GFXV R_VID_5 <47>
GFXV R_VID_6 <47>

R141 0_0402_5%

1U_0603_10V4Z

1U_0603_10V4Z

C253

C256

1

1

2

2

22U_0805_6.3V6M

Modify for cost revew.

C258

C252

1

09/16/2009

2

+VCCP

10U_0805_10V4K

10U_0805_10V4K

C273

1

1

2

2

10U_0805_10V4K

10U_0805_10V4K

C218

1

1

2

2

2.2U_0603_6.3V4Z

10U_0805_10V4K

C168

C169

1

2

12

R233
220_0402_5%

13

D

Q19
BSS1 38_NL_SOT23-3

S

Title

Size D ocument Number Re v

Custom

Date: Sheet

(~15MW) MAYBE WASTED

DESIGN GUIDE REV1.1

R140

1 2

UMA@

1

+1.5V_DDR3

1U_0603_10V4Z

C255

1

2

C212

+VCCP

C213

+1.8VS

4.7U_0603_6.3V6K
C170

1

2

GFX_VR_EN

GFXV R_EN <47>
GFXVR_DPRSLPVR <47>

GFXV R_IMON < 47>

C257

Compal Electronics, Inc.

Arrandale(4/5)-PWR

LA-5752P

1

851Thursday, October 29, 2009

4.7K_ 0402_5%

of

0.3

http://hobi-elektronika.net

5

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17
AR15
AR12

AP20
AP17
AP13
AP10

AN34
AN31
AN23
AN20

AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AL34

AL31

AL23

AL20

AL17

AL12

AK29
AK27
AK25
AK20
AK17

AJ31

AJ23

AJ20

AJ17

AJ14

AJ11

AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13

AG10

AE35

VSS8
VSS9
VSS10
VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14
VSS15
VSS16
VSS17
VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75
VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

4

JCPU1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

VSS_NCTF1_R
VSS_NCTF2_R
VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R
VSS_NCTF6_R
VSS_NCTF7_R

3

+CPU_CORE

2

1

CPU CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

C585

C568

1

1

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C163

C147

1

1

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C192

C195

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C580

1

2

10U_0805_6.3V6M

C162

1

2

10U_0805_6.3V6M

C88

1

2

22U_0805_6.3V6M

C579

1

2

1

2

1

2

C574

1

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C193

C179

1

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C196

C180

1

2

Under cavity

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C584

C573

1

1

2

2

10U_0805_6.3V6M

C166

1

1

2

2

10U_0805_6.3V6M

C89

1

1

2

2

C578

1

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C148

C165

1

2

10U_0805_6.3V6M

C197

22U_0805_6.3V6M

C583

1

2

1

2

1

2 3

C577

1

2

10U_0805_6.3V6M

C194

between Inductor and socket

470U_D2T_2VM

470U_D2T_2VM

C76

C75

1

+

+

2 3

22U_0805_6.3V6M

22U_0805_6.3V6M

C571

C572

1

1

2

470U_D2T_2VM

1

+

2 3

2

C92

1

+

2 3

Inside cavity

470U_D2T_2VM

C164

22U_0805_6.3V6M

22U_0805_6.3V6M

C91

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C90

C129

C87

1

1

2

2

470uF 4.5mohm

IC,AUB_CFD_rPGA,R1P0

ME@

A A

5

IC,AUB_CFD_rPGA,R1P0

ME@

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Title

Size D ocument Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Arrandale(5/5)-GND/Bypass

LA-5752P

1

of

951Thursday, October 29, 2009

0.3

http://hobi-elektronika.net

5

+VREF_DQ_DIMMA

+VREF_DQ_DIMMA

2.2U_0603_6.3V4Z

0.1U_0402_10V6K
C303

1

1

2

D D

C C

B B

A A

2

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_W E#<7>
DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

+3VS

1

2

5

DDR_A_D0

C347

DDR_A_D1

DDR_A_DM 0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS #1
DDR_A _DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS #2
DDR_A _DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM 3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR _A_WE#
DDR_A_CA S# M_ODT0

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS #4
DDR_A _DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM 5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS #6
DDR_A _DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM 7

DDR_A_D58
DDR_A_D59

1 2

10K_0 402_5%

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

C608

C617

1

2

+1.5V +1.5V

4BA

4BA 2/6W

2/6W

4BA4BA

2/6W2/6W

DDR3 SO-DIMM A

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R570

10K_0 402_5%

12

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

R571

VTT1

205

G1

DQ4
DQ5

VSS3

DQS#0

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

A15
A14

VDD4

A11

A7

VDD6

A6
A4

VDD8

A2
A0

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

FOX_ AS0A626-U4SN-7F
ME@

G2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

4

DDR_A_D4
DDR_A_D5

DDR_A_DQS #0
DDR_A _DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM 1
DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM 2

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS #3
DDR_A _DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_DM 4

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS #5
DDR_A _DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_DM 6

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS #7
DDR_A _DQS7

DDR_A_D62
DDR_A_D63

PM_E XTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

+0.75VS

1/

1/ 76BA1/86W

76BA1/86W

1/1/

76BA1/86W76BA1/86W

4

DRAMRST# <5,11>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_10V6K
C346

1

1

2

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

VREF =

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

PM_E XTTS#1_R < 5,11>

SMB_DATA_S3 <1 1,12,14,28>
SMB_CLK_S3 <11,12,14,28>

DDR_A_D[0..63]<7>

DDR_A_DM [0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_DQ S#[0..7]<7>

DDR_A_MA[0..15]<7>

+VREF_DQ_DIMMA

2.2U_0603_6.3V4Z
C355

4*0402 1uf

1*0402 2.2uf

3

Layout Note:
Place near DIMM

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C588

C589

1

1

@

@

2

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

2008/10/31 2009/10/31

C581

C586

1

2

+0.75VS

C607

C605

1U_0603_10V4Z

1

1

2

2

Compal Secret Data

1

2

1U_0603_10V4Z

10U_0603_6.3V6M

10U_0603_6.3V6M

C310

1

2

C606

C300

1U_0603_10V4Z

1

2

Deciphered Date

2

10U_0603_6.3V6M

C570

C309

1

1

2

2

C301

1U_0603_10V4Z

1U_0603_10V4Z

1

1

2

2

2

1

+1.5V

12

R297

1K_04 02_1%

1K_04 02_1%

For Arranale only +VREF_DQ_DIMMA
supply from a exter nal 1.5V voltage divide
circ uit.
07/17/2009

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

C308

1

2

C314

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K
C317

C315

1

1

2

Title

Size D ocument Number Re v

Custom

Date: Sheet

1

2

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

R305

0.1U_0402_10V6K
C316

+VREF_DQ_DIMMA

12

1

+

C569
220U_B2_2.5VM_R35

2

LA-5752P

1

0.3

of

10 51Thursday, October 29, 2009

http://hobi-elektronika.net

5

+VREF_DQ_DIMMB

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

1

C382

+3VS

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

2.2U_0603_6.3V4Z

1

2

D D

C C

B B

A A

+VREF_DQ_DIMMB

DDR_B_D0
DDR_B_D1

1

C384

DDR_B_DM 0

2

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS #1
DDR_B _DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS #2
DDR_B _DQS2

DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM 3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR _B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS #4
DDR_B _DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM 5

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS #6
DDR_B _DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM 7

DDR_B_D58
DDR_B_D59

1 2

10K_0 402_5%

0.1U_0402_10V6K

C618

C616

1

2

5

+1.5V +1.5V

4BA

4BA 2/6W

2/6W

4BA4BA

2/6W2/6W

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

R572

1 2

R57 3 10K _0402_5%

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

TYCO _2-2013297-2~D

ME@

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND1

2

VSS

4

DQ4

6

DQ5

8

VSS

10
12
14

VSS

16

DQ6

18

DQ7

20

VSS

22
24
26

VSS

28

DM1

30
32

VSS

34
36
38

VSS

40
42
44

VSS

46

DM2

48

VSS

50
52
54

VSS

56
58
60

VSS

62
64
66

VSS

68
70
72

VSS

74
76

VDD

78

A15

80

A14

82

VDD

84

A11

86

A7

88

VDD

90

A6

92

A4

94

VDD

96

A2

98

A0

100

VDD

102

CK1

104
106

VDD

108

BA1

110
112

VDD

114

S0#

116
118

VDD

120
122

NC

124

VDD

126
128

VSS

130
132
134

VSS

136

DM4

138

VSS

140
142
144

VSS

146
148
150

VSS

152
154
156

VSS

158
160
162

VSS

164
166
168

VSS

170

DM6

172

VSS

174
176
178

VSS

180
182
184

VSS

186
188
190

VSS

192
194
196

VSS

198
200

SDA

202

SCL

204

VTT

206

4

DDR_B_D4
DDR_B_D5

DDR_B_DQS #0
DDR_B _DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM 1
DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM 2

DDR_B_D22
DDR_B_D23DDR_B_D18

DDR_B_D28
DDR_B_D29

DDR_B_DQS #3
DDR_B _DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB#
M_ODT2

M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_DM 4

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS #5
DDR_B _DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_DM 6

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS #7
DDR_B _DQS7

DDR_B_D62
DDR_B_D63

PM_E XTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

1/

1/ 76BA1/86W

76BA1/86W

1/1/

76BA1/86W76BA1/86W

4

DDR_B_DQ S#[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_DM [0..7]<7>

DDR_B_DQS[0..7]<7>

DDR_B_MA[0..15]<7>

DRAMRST# <5,10>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RA S# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

1

2

0.1U_0402_10V6K

C385

+VREF_DQ_DIMMB

2.2U_0603_6.3V4Z

C383

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

4*0402 1uf

1*0402 2.2uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

PM_E XTTS#1_R < 5,10>

SMB_DATA_S 3 <10, 12,14,28>
SMB_CLK_S3 <10,12,14,28>

+0.75VS

3

Layout Note:
Place near DIMM

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

C582

1

@

@

2

Layout Note:
Place near DIMM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

10U_0603_6.3V6M

C587

C576

1

1

2

2

+0.75VS

1U_0603_10V4Z

10U_0603_6.3V6M

C595

C596

1

1

2

2

2008/10/31 2009/10/31

10U_0603_6.3V6M

C311

1

2

1U_0603_10V4Z

C299

1

2

10U_0603_6.3V6M

C313

1

2

1U_0603_10V4Z

C598

1

2

Compal Secret Data

10U_0603_6.3V6M

C575

C590

1

2

Deciphered Date

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C312

1

1

2

2

2

1

+1.5V

12

R341

1K_04 02_1%

1K_04 02_1%

For Arranale only +VREF_DQ_DIMMB
supply from a exter nal 1.5V voltage divide
circ uit.
07/17/2009

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C304

C307

1

1

2

2

0.1U_0402_10V6K

C305

1

2

C306

1

2

Title

Size D ocument Number Re v

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

R340

+VREF_DQ_DIMMB

12

LA-5752P

1

0.3

of

11 5 1T hursday, October 29, 2009

http://hobi-elektronika.net

5

4

3

2

1

Reserve for Low Power CLK GEN.
RTM890N-632
SLG8LV597VTR

VDD_3V3_1V5+3VS_CK505

1 2

R2780_0603_5%

@

D D

+1.5VS

1 2

R2690_0603_5%

1 PCS CAP(0.1u) BY 1 INPUT PIN

VDD_3V3_1V5

0.1U_0402_10V6K

10U_0805_10V4K

C336

1

1

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

C366

C330

C334

1

1

2

2

CLK GEN TO PCH

1. CLK_DMI

2. CLK_BUF_BCLK

3. CLK_BUF_CKSSCD

4. CLK_BUF_DOT96

5. CLK_14M_PCH

C C

CLK GEN TO VGA

1. 27M_CLK

1. 27M_CLK_SS

+1.05VS_CK505+1.05VS

1 2

R2770_0603_5%

CLK_BUF_DOT96<14>

CLK_BUF_DOT96#<14>

CLK_BUF_CKSSCD<14>

CLK_BUF_CKSSCD#<14>

CLK_DMI<14>

CLK_DMI#<14>

CLK_BUF_DOT96
CLK_BUF_DOT96#

CLK_BUF_CKSSCD
CLK_BUF_CKSSCD#

CLK_DMI
CLK_DMI#

+3VS_CK505

R324 0_0402_5%
R308

R307 0_0402_5%
R306

R299

1 PCS CAP(0.1u) BY 1 INPUT PIN

10U_0805_10V4K

10U_0805_10V4K

C333

1

1

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

C331

C343

C332

1

1

2

2

0.1U_0402_10V6K
C335

1

2

R318 0_0402_5%

1 2
1 2

R319 0_0402_5%

CLOSE U27

1 2
1 2

1 2
1 2

1 2

CLK_48M_CR

0_0402_5%

0_0402_5%

10K_0 402_5%

L_CLK_BUF_DOT96
L_CLK_BUF_DOT96#

L_CLK_DMI
L_CLK_DMI#

CPU_STOP#

unstuff 09.09.08

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_SRC

+3VS_CK505 +1.05VS_CK505+3VS_CK505 +1.05VS_CK505

32

SCL

31

SDA

30
29
28
27
26
25

24
23
22
21
20
19
18
17

VDD_3V3_1V5

CLK_48M_CR_R

CLK_BUF_CKSSCD_R
CLK_BUF_CKSSCD#_R

U14

1

VDD_USB_48

2

VSS_48M

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

USB_48

9

VSS_27M

10

SATA

11

SATA#

12

VSS_SRC

13

SRC_1

14

SRC_1#

15

VDD_SRC_IO

16

CPU_STOP#

33

TGND

SLG8S P587VTR_QFN32_5X5

REF_0/CPU_SEL

CKPWRGD/P D#

VDD_CPU_IO

RTM890N-631-GRT QFN 32P CLK GEN (SA00003HQ00)
ICS9LVS3199AKLFT MLF 32P CLK GEN (SA00003HR00)

1 2

@

CLK_48M_CR_R

R32233_0402_1%

12

R3230_0402_5%

@

PIN8 IS GND FOR ICS3197

SMB_CLK_S3
SMB_DATA_S3
REF_0/CPU_SE L

CLK_XTAL_IN
CLK_XTAL_OUT

CK_PWRGD

VDD_3V3_1V5
R_CLK_BUF_BCLK CLK_BUF_BCLK
R_CLK_BUF_BCLK# CLK_BUF_BCLK#

VDD_3V3_1V5

R275 0_0402_5%

1 2
1 2

R276 0_0402_5%

R315

12

33_0402_1%

CK_PWRGD

CLK_14M_PCH

2N7002_S OT23-3

SMB_CLK_S3 <10,11,14,28>
SMB_DATA_S3 <10,11,14,28>

CLK_14M_PCH <14>

CLK_BUF_BCLK <14>
CLK_BUF_BCLK# <14>

R298

1 2

10K_0 402_5%

13

D

2

G

Q25

S

+3VS_CK505

CLK_EN# <48>

PIN8 IS 48MHz FOR ICS3199

B B

A A

+3VS

1 2

R2790_0603_5%

+3VS_CK505

1 PCS CAP(0.1u) BY 1 INPUT PIN

0.1U_0402_10V6K

C342

C350

1

1

2

2

100MHz 100MHz

0.1U_0402_10V6K
C367

CPU_1PIN 30 CPU_0

133MHz

0.1U_0402_10V6K

10U_0805_10V4K

C344

1

1

2

2

(Default)

0 133MHz

1

+1.05VS

1 2

R317 10K_0 402_5%@

1 2

R316 10K_0 402_5%

C365

CLK_14M_PCH

12

22P_0 402_50V8J

C364

EMI Capacitor

REF_0/CPU_SE L

REF_0/CPU_SE L

12

10P_0402_50V8J@

C348

22P_0402_50V8J

CLK_XTAL_OUT

CLK_XTAL_IN

Y1

12

2

2

14.31818MHZ_16PF_DSX840GA

1

C349

22P_0402_50V8J

1

5

http://hobi-elektronika.net

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Title

Size D ocument Number Re v

Date: Sheet

Compal Electronics, Inc.

CLOCK GENERATOR

LA-5752P

1

of

12 51Thursday, October 29, 2009

0.3

5

PCH_RTCX1

1 2

R15 4 10 M_0402_5%

1

D D

+RTCVCC

R144

1 2

100_0603_1%

2

C441

0.1U_0402_16V4Z

1

C C

+RTCBATT

12

SHORT PADS

+RTCVCC

R421

R420

CLRP1

H IntegrΚated VRM enable

*

Κ

L Integra

+3VS

1 2

1 2

R45 2 1K_0402_5%@

1

2

15P_0402_50V8J

1M_0402_5%

330K_0402_5%

ted VRM disable

1 2

C171

2

SM_INTRUDER#

PCH_INTVRMEN

PCH_SPKR

OSC4OSC

NC3NC

PCH_RTCX2

X1

32.768KHZ_12.5PF_9H03200413

1

C183
15P_0402_50V8J

2

@

HDA_BITCLK_CODEC<33>

HDA_SYNC_CODEC<33>

@

GPIO33 = GPO , internal pull-up,should not be pulled low

flash ME core of strap pin pull down

(2009,07,07)

+3VALW+3VALW +3VALW +3VALW +3VS

12

@

R74
200_0402_5%

12

B B

@

R117
100_0402_1%

A A

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_JTAG_RST#

RefDesPCH Pin

R591

R590

R584

R583

R586

R580

R595

R594

12

@

R72
200_0402_5%

PCH_JTAG_TMS PCH_JTAG_RST#PCH_JTAG_TDO PCH_JTAG_TDI

12

@

R115
100_0402_1%

PCH JTAG
Pre-Production

ES1 MPES2

No Install

No Install

200ohm

100ohm 100ohm

200ohm

100ohm 100ohm

51ohm

20Kohm 20Kohm

10Kohm 10Kohm

5

12

@

R73

200_0402_5%

12

@

R116
100_0402_1%

PCH JTAG
Production

*

200ohm

No Install

100ohm

No InstallPCH_JTAG_TDO

200ohm

No Install

No InstallPCH_JTAG_TMS

No InstallR587

200ohm

No Install

51ohm 51ohm

No Install

No Install

@

R75
20K_0 402_5%

1 2

12

@

R118
10K_0 402_5%

PCH_JTAG_TCK

FOR INTEL DPDG REV1.6 (MAY 2009)

4

+RTCVCC

1U_0603_10V4Z

1 2

R419 20 K_0402_1%

1 2

R422 20 K_0402_1%

C64712P_0402_50V8J

1 2

1 2

C64812P_0402_50V8J

R114 51_0402_5%

1U_0603_10V4Z

PCH_SPKR<33>

HDA_RST_CODEC#<33>

HDA_ SDIN1<33>

HDA_S DOUT_CODEC<33>

ME_FLASH<34>

1 2

4

C184

C202

+3VALW

SPI_CLK_PCH

1

12

CLRP3

SHORT PADS

2

1

12

CLRP2

SHORT PADS

2

R168 33_0402_5%

1 2

R167 33_0402_5%

1 2

R169 33_0402_5%

1 2

R166 33_0402_5%

1 2

R40 9 1 K_0402_5%@

1 2

R425 0_0402_5%

1 2

R424 10 K_0402_5%

1 2

@

GPIO13 = GPI,3.3V,SUS

R99

1 2

0_0402_5%

(2009,05,04)

PCH_RTCX1
PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

BITCLK

HDA_SYNC

PCH_SPKR

HDA_RST#

HDA_ SDIN0

HDA_ SDIN1

HDA_SDOUT

GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_P CH_R

SPI_SB_CS0#

SPI_SI

SPI_SO_R

3

U7A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_FCBGA1071

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

RTCIHDA

SPI JTAG

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

SATA

SATA0GP / GPIO21

SATA1GP / GPIO19

D33

FWH0 / LAD0

B33

FWH1 / LAD1

C32

FWH2 / LAD2

A32

FWH3 / LAD3

C34

A34

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

2008/10/31 2009/10/31

GPIO23

F34

SERIRQ

AB9

AK7
AK6

SAT A_ITX_C_DRX_N0

AK11

SATA_ITX_C_DRX _P0

AK9

AH6
AH5

SAT A_ITX_C_DRX_N1

AH9

SATA_ITX_C_DRX _P1

AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

SATA_DTX_C_IRX_N4

AD9

SATA_DTX_C_IRX _P4

AD8

SAT A_ITX_C_DRX_N4

AD6

SATA_ITX_C_DRX _P4

AD5

AD3
AD1
AB3
AB1

AF16

SATAICOMPPCH_JTAG_RST#

AF15

T3

Y9

V1

R453 10K _0402_5%

GPIO21

GPIO19

SPI_SB_CS0#
SPI_SO_R SPI_SO_L

Compal Secret Data

2

LPC_AD0 <28,34>
LPC_AD1 <28,34>
LPC_AD2 <28,34>
LPC_AD3 <28,34>

LPC_FRAME# <28,34>

T7 PAD

GPIO23 = NATIVE,3.3V,CORE

1 2

37.4_0402_1%

1 2

SERIRQ <34>

R500

HDD_LED# <36>

GPIO21 = GPI,3.3V,CORE

GPIO19 = GPI,3.3V,CORE

+3VS

R62

1 2

R102

1 2

R103
15_0402_5%

1 2

15_0402_5%

Deciphered Date

2

+1.05VS

+3VS

R101

12

R4791 0K_0402_5%

12
12

12
12

12
12

SPI_WP#

3.3K_ 0402_5%

SPI_HOLD#

3.3K_ 0402_5%

12

SPI_WP#

+3VS

C1400.01U_0402_16V7K
C1410.01U_0402_16V7K

C4270.01U_0402_16V7K
C4280.01U_0402_16V7K

SAT A_DTX_C_IRX_N0
SATA_DTX_C_IRX _P0

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0

SAT A_DTX_C_IRX_N1
SATA_DTX_C_IRX _P1

SATA_ITX_DRX_N1

SATA_ITX_DRX_P1

SATA_ITX_DRX_N4_CONN

C1420.01U_0402_16V7K ESATA@

SATA_ITX_DRX_P4_CONN

C1430.01U_0402_16V7K ESATA@

R447

10K_0 402_5%

GPIO21

GPIO19

1 2

1 2

SATA _DTX_C_IRX_N0 <32>

SATA_DTX_C_IRX_P 0 <32>
SATA_ITX_DRX_N0 < 32>
SATA_ITX_DRX_P0 <32>

SATA _DTX_C_IRX_N1 <32>

SATA_DTX_C_IRX_P 1 <32>
SATA_ITX_DRX_N1 < 32>

SATA_ITX_DRX_P1 <32>

R482
10K_0 402_5%

4M SPI ROM FOR HM55
(ME code & BIOS code)
SA00003K800

+3VS

U3

1

CS#

VCC

2

SO

HOLD#

3

WP#

SCLK

4

GND

SI

S IC FL 16M EN25F16-100HIP SOP 8P

Title

Size D ocument Number Re v

Custom

Date: Sheet

1 2

8

SPI_HOLD#

7

SPI_CLK_PCH

6

SPI_SI

5

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

1

SATA_DTX_C_IRX_N4 <37>

SATA_DTX_C_IRX_P 4 <37>
SATA _ITX_DRX_N4_CONN <37>
SATA _ITX_DRX_P4_CONN <37>

C460

0.1U_0402_16V4Z

LA-5752P

1

HDD

ODD

E-SATA

SPI_CLK_PCH

R100

33_0402_5%

@

22P_0402_50V8J

@

of

13 51Thursday, October 29, 2009

12

C138

0.3

http://hobi-elektronika.net

5

PCIE PORT LIST

DEVICEPORT

X

1

WLAN

2
3

LAN

4

CLK_PCIE _CARD_PCH#<28>
CLK_PCIE_CARD_PCH<28>

5
6
7
8

CLK_PCIE_EXP_PCH#<28>
CLK_PCIE_E XP_PCH<28>

PCIE _PRX_DTX_N2<28>
PCIE_PRX_DTX _P2<28>
PCIE _PTX_C_DRX_N2<28>
PCIE _PTX_C_DRX_P2<28>

PCIE _PRX_DTX_N3<29>
PCIE_PRX_DTX _P3<29>
PCIE _PTX_C_DRX_N3<29>
PCIE _PTX_C_DRX_P3<29>

PCIE _PRX_DTX_N4<28>
PCIE_PRX_DTX _P4<28>
PCIE _PTX_C_DRX_N4<28>
PCIE _PTX_C_DRX_P4<28>

PCIE _PRX_DTX_N5<28>
PCIE_PRX_DTX _P5<28>
PCIE _PTX_C_DRX_N5<28>
PCIE _PTX_C_DRX_P5<28>

CLK_PCIE_WLAN1#<28>
CLK_PCIE_WLAN1<28>

WLAN_CLKREQ1#<28>

CLK_PCIE_LAN#<29>
CLK_PCIE_LAN<29>

CLKREQ_LAN#<29>

PCIECLKREQ3#<28>

CLKREQ_EXP#< 28>

3G
NEW CARD
X
X
X

C230 0.1U_0402_10V 6K
C229 0.1U_0402_10V 6K

C223 0.1U_0402_10V 6K
C222 0.1U_0402_10V 6K

C231 0.1U_0402_10V 6K3G@
C232 0.1U_0402_10V 6K3G@

C220 0.1U_0402_10V 6K
C221 0.1U_0402_10V 6K

R431 10 K_0402_5%

+3VALW

R196 0_0402_5%
R197 0_0402_5%

R454 10 K_0402_5%

+3VS

R220 0_0402_5%
R221 0_0402_5%

R113 10 K_0402_5%

+3VS

R223 0_0402_5%3G@
R222 0_0402_5%3G@

R120 10 K_0402_5%

+3VALW

R224 0_0402_5%
R225 0_0402_5%

R435 10 K_0402_5%

+3VALW

R434 10 K_0402_5%

+3VALW

R457 10 K_0402_5%

+3VALW

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

1 2

1 2
1 2

1 2

1 2
1 2

1 2

1 2
1 2

1 2

1 2

1 2

PCIE _PRX_DTX_N2
PCIE_PRX _DTX_P2
PCIE _PTX_DRX_N2
PCIE_PTX _DRX_P2

PCIE _PRX_DTX_N3
PCIE_PRX _DTX_P3
PCIE _PTX_DRX_N3
PCIE_PTX _DRX_P3

PCIE _PRX_DTX_N4
PCIE_PRX _DTX_P4
PCIE _PTX_DRX_N4
PCIE_PTX _DRX_P4

PCIE _PRX_DTX_N5
PCIE_PRX _DTX_P5
PCIE _PTX_DRX_N5
PCIE_PTX _DRX_P5

GPIO73 = NATIVE,3.3V,SUS

CLK_PCIE _WLAN1#_R
CLK_PCIE _WLAN1_R

GPIO18 = NATIVE,3.3V,CORE

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

GPIO20 = NATIVE,3.3V,CORE

CLK_ PCIE_CARD_PCH#_R
CLK_P CIE_CARD_PCH_R

GPIO25 = NATIVE,3.3V,SUS

CLK_PCIE_EXP_PCH#_R

CLKREQ_EXP#

GPIO26 = NATIVE,3.3V,SUS

GPIO44 = NATIVE,3.3V,SUS

GPIO56 = NATIVE,3.3V,SUS

D D

WLAN

LAN

3G

C C

EXP

WLAN

B B

LAN

3G

EXP

A A

4

U7B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071

WLAN

LAN

MINI1

NEW CARD

SMBus

PCI-E*

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

3

R407
0_0402_5%

LID_OUT#

B9

H14

C8

J14

C6

G8

M14

E10

G12

T13

T11

T9

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

AH51
AH53

AF38

T45

P43

T42

N50

GPIO11 = NATIVE,3.3V,SUS

SMBCLK

SMBDATA

GPIO60 = NATIVE,3.3V,SUS

GPIO60

SML 0CLK

SML0DATA

GPIO74 = NATIVE,3.3V,SUS

GPIO74

SML 1CLK

R79

SML1DATA

R80

PEG_CLKREQ#

PEG_CLKREQ#

GPIO47 = 10Kohm PULL DOWN

CLKOUT_DP_N
CLKOUT_DP_P

CLK_14M_PCH

CLK_PCI_FB

XTAL25_IN
XTAL25_OUTCLK_PCIE_EXP_PCH_R

CLK_PCI_DB_R

1 2

CLK_PCIE_VGA#_R
CLK_PCIE_VGA_R

CLK_EXP#_R
CLK_EXP_R

R491 90.9_0402_1%

R524 0_0402_5%
R525 0_0402_5%

R105 0_0402_5%
R106 0_0402_5%

1 2

R198

1 2

EC_LID_OUT# <34>

0_0402_5%

0_0402_5%

DTS , read from EC

PEG_CLKREQ# <19>

R41210K_0402_5%

1 2
1 2

1 2
1 2

CLK_DMI# <12>
CLK _DMI < 12>

CLK_BUF_BCLK# <12>
CLK_BUF_BCLK <12>

CLK_B UF_DOT96# < 12>
CLK_BUF_DOT96 <12>

CLK_BUF_CKSSCD# <12>
CLK_BUF_CKSSCD <12>

CLK_14M_PCH <12>

CLK_PCI_FB <16>

+1.05VS

22_0402_5%

@

EC_SMB_CK2

EC_SMB_DA2

CLK_PCI_DB <28>

SMBCLK

SMBDATA

CLK_PCIE_VGA#
CLK_PCIE_VGA

SMB_CLK_S3

SMB_DATA_S3

EC_S MB_CK2 < 34>

EC_S MB_DA2 < 34>

CLK_EXP# <5>
CLK_EXP <5>

2

1 2

R12 1 1 0K_0402_5%

1 2

R40 6 1 0K_0402_5%

Q8A

2N7002DW-T/R7_SOT363-6

6 1

2N7002DW-T/R7_SOT363-6

3

SMB_CLK_S3

2

+3VS

Q8B

SMB_DATA_S3

4

5

EC_THERMAL

CLK_PCIE_VGA# <19>

CLK_P CIE_VGA <19>

+3VS

Q7A

6 1

5

2N7002DW-T/R7_SOT363-6

Q7B

3

2N7002DW-T/R7_SOT363-6

4

EC_SMB_DA2

EC_SMB_CK2

EMI REQUEST 0303

CLK_14M_PCHCLK_PCI_FB

R209
33_0402_5%

@

1 2

C263
22P_0402_50V8J

@

1 2

SMBCLK

+3VS +3VALW

SMBDATA

SML 0CLK

SML0DATA

SML 1CLK

SML1DATA

GPIO74

LID_OUT#

GPIO60

SMB_CLK _S3 <10 ,11,12,28>

1 2

R12 3 2 .2K_0402_5%

1 2

R7 8 2. 2K_0402_5%

1 2

R14 8 2 .2K_0402_5%

1 2

R14 7 2 .2K_0402_5%

1 2

R40 4 2 .2K_0402_5%

1 2

R40 3 2 .2K_0402_5%

1 2

R39 9 1 0K_0402_5%

1 2

R14 5 1 0K_0402_5%

1 2

R40 0 1 0K_0402_5%

DDR3*2 AND CLK GEN

SMB_DATA_S 3 <10, 11,12,28>

+3VS

2

R81 0_0402_5%

1 2

R83 0_0402_5%

1 2

R413
33_0402_5%

@

C439
22P_0 402_50V8J

@

+3VS

R124

2.2K_ 0402_5%

@

SMB_EC_DA2_R

@

SMB_EC_CK2_R

25MHz crystal not used, XTAL25_IN
need to GND.
(checklist Rev1.6)

XTAL25_IN

XTAL25_OUT

1

R122

SMBCLK

SMBDATA SMB_DATA_S3

R82

2.2K_ 0402_5%

SMB_EC_DA2_REC_SMB_DA2

SMB_EC_CK2_REC_SMB_CK2

0_0402_5%

@

1 2

@

1 2

0_0402_5%
R119

Nvidia
thermal
sensor

1 2

R59 8 1 M_0402_5%@

Y4

@

1 2

25MHZ_20P_1BG25000CK1A

18P_0 402_50V8J

C630

1

@

2

SMB_EC_DA2_R <19,31>

SMB_EC_CK2_R <19,31>

SMB_CLK_S3

0_0402_5%

1

2

C631

5

http://hobi-elektronika.net

C631 Resistor Pull down

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

LA-5752P

1

of

14 51Thursday, October 29, 2009

0.3

5

4

3

2

1

D D

DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>

DMI_CRX_PT X_N0<6>
DMI_CRX_PT X_N1<6>
DMI_CRX_PT X_N2<6>
DMI_CRX_PT X_N3<6>

DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>

+1.05VS

1 2

R520 49.9_0402_1%

4mil width and place
within 500mil of the PCH

C C

Checklist0.8 MEPWROK
can be connect to
PWROK if iAMT disable

(2009,05,04)

SUS_PWR_DN_ACK<34>

+3VALW

R45 0 10K_0 402_5%

VGATE

ICH_POK

Reserved
(2009,09,08)

1

2

+3VALW

A

B

+3VS

B B

A A

Κ

R396 100K_0402_1%

VGATE<48>

ICH_POK<34>

+3VALW

1 2

AC_PRESENT<34>

MC74VHC1G08DFT2G SC70 5P

3

@

G

Y

P

U28

5

12

R398 0_0402_5%@

R397 0_0402_5%

PM_DRAM_PWRGD<5>

R401

R43 7 10K_0402_5%

1 2

1 2

R599 0_0402_5%@

PBTN_OUT#< 34>

GPIO31 = GPI,3.3V,SUS

R77 8 .2K_0402_1%

1 2

GPIO30 = GPI,3.3V,SUS

R165 10K_0 402_5%

1 2

SYS_PWROK

4

1 2

1 2

10K_0 402_5%

R451 0_0402_5%

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX _PTX_N0
DMI_CRX _PTX_N1
DMI_CRX _PTX_N2
DMI_CRX _PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP

+3VS

R448
10K_0 402_5%

SYS_RST#

1 2

SYS_PWROK

R455

0_0402_5%

1 2

R146 10 K_0402_5%

1 2

PM_DRAM_PWRGD

PM_RSMRST#

12

SUS_PWR_DN_ACK_R

PBTN_OUT#

AC_PRESENT_R

1 2

GPIO72

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA1071

EC_RSMRST#<34>

U7C

System Power Management

RSMRST circuit

BAV9 9DW-7_SOT363

5

D8B

R175

1 2

2.2K_ 0402_5%

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_LAN# / GPIO29

@

0_0402_5%

1 2

E

B

4

2

3

6

BA18

FDI_RXN0

BH17

FDI_RXN1

BD16

FDI_RXN2

BJ16

FDI_RXN3

BA16

FDI_RXN4

BE14

FDI_RXN5

BA14

FDI_RXN6

BC12

FDI_RXN7

BB18

FDI_RXP0

BF17

FDI_RXP1

BC16

FDI_RXP2

BG16

FDI_RXP3

AW16

FDI_RXP4

BD14

FDI_RXP5

BB14

FDI_RXP6

BD12

FDI_RXP7

BJ14

FDI_INT

BF13

FDI_FSYNC0

BH13

FDI_FSYNC1

BJ12

FDI_LSYNC0

BG14

FDI_LSYNC1

J12

WAKE#

Y1

P8

F3

E4

H7

SLP_S4#

P12

SLP_S3#

K8

SLP_M#

N2

TP23

BJ10

PMSYNCH

GPIO29 = GPO,3.3V,SUS

F6

R402

C

PM_RSMRST#

123

Q14
MMBT3906_SOT23-3

1 2

R17 6 4.7K_04 02_5%

1

D8A
BAV9 9DW-7_SOT363

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

10K_0 402_5%

1 2

PCIE_WA KE#

GPIO32 = GPO,3.3V,CORE

GPIO61

GPIO62

R436

PCIE_WAKE# <28>

1 2

R10 8 10 K_0402_5%

GPIO61 = NATIVE,3.3V,SUS

GPIO62 = NATIVE,3.3V,SUS

SLP_S5# <34>

SLP_S4# <34>

SLP_S3# <34>

Can be left NC when IAMT is
not support on the platfrom

H_PM_SYNC <5>

If not using integrated
LAN,signal may be left as NC.

+3VALW

FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>

FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>

FDI_INT <6>

FDI_FSYNC0 <6>

FDI_FSYNC1 <6>

FDI_LSYNC0 <6>

FDI_LSYNC1 <6>

+3VALW

+3VS

SLP_S3#

SLP_S4#

SLP_S5#

+3VS

1 2

R41 8 10K _0402_5%@

1 2

R41 7 10K _0402_5%@

1 2

R41 6 10K _0402_5%@

PCH_ENBKL<27>

PCH_ENVDD< 27>

EDID_CLK<27>
EDID_DATA<27>

PCH_PWM<27>

12

R502

2.37K _0402_1%

CRT_D DC_CLK<26>
CRT_DDC_DATA<26>

CRT_HSYNC<26>
CRT_VSYNC<26>

LVDS_ACLK#<27>
LVDS_ACLK<27>

LVDS_A0#<27>
LVDS_A1#<27>
LVDS_A2#<27>

LVDS_A0<27>
LVDS_A1<27>
LVDS_A2<27>

DAC_BLU<26>
DAC_GRN<26>
DAC_RED<26>

PCH_ENBKL

PCH_ENVDD

EDI D_CLK
EDID_DATA

R497

1 2

10K_0 402_5%

1 2

R49 6 1 0K_0402_5%

T10 P AD

DAC_BLU
DAC_GRN
DAC_RED

CRT_IREF

1K_04 02_5%

R492

12

U7D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M_FCBGA1071

update R492 tolerance for
DAC_CRT from 0.5% to 5%
(checklist 2.0)

DAC_BLU

DAC_GRN

DAC_RED

EDI D_CLK

EDID_DATA

CRT OUT

R493 150_0402_1%UMA@

1 2

R495 150_0402_1%UMA@

1 2

R494 150_0402_1%UMA@

1 2

R45 8 2.2K_0402_5%UMA@

R49 8 2.2K_0402_5%UMA@

LVDS

CRT

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

+3VS

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40

2.2K_ 0402_5%

AW38
BA38

HDMICLK _NB

Y49

HDMIDAT_NB

AB49

BE44
BD44
AV40

TMDS _B_DATA2#_PCH

BE40

TMDS_B_ DATA2_PCH

BD40

TMDS _B_DATA1#_PCH

BF41

TMDS_B_ DATA1_PCH

BH41

TMDS _B_DATA0#_PCH

BD38

TMDS_B_ DATA0_PCH

BC38

TMDS_B_CLK#_PCH

BB36

TMDS_B_CLK_PCH

BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

R51 0 10K _0402_5%

12

+3VS

12

12

UMA@

UMA@

R504

R503

2.2K_ 0402_5%

C638 0.1U_0402_10V6KUMA_HDMI@
C639 0.1U_0402_10V6KUMA_HDMI@
C640 0.1U_0402_10V6KUMA_HDMI@
C641 0.1U_0402_10V6KUMA_HDMI@
C642 0.1U_0402_10V6KUMA_HDMI@
C643 0.1U_0402_10V6KUMA_HDMI@
C644 0.1U_0402_10V6KUMA_HDMI@
C645 0.1U_0402_10V6KUMA_HDMI@

HDMICLK_NB <25>
HDMIDAT_NB <25>

TMDS _B_HPD# < 25>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

TMDS_B_DAT A2# <25>
TMDS_B_DAT A2 <25>
TMDS_B_DAT A1# <25>
TMDS_B_DAT A1 <25>
TMDS_B_DAT A0# <25>
TMDS_B_DAT A0 <25>
TMDS _B_CLK# <25>
TMDS _B_CLK <25>

HDMI

http://hobi-elektronika.net

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

LA-5752P

1

15 51Thursday, October 29, 2009

0.3

of

5

D D

PCI_PIRQA#
PCI_PIRQB#

GPIO18 = NATIVE,5V,CORE
GPIO52 = NATIVE,5V,CORE
GPIO54 = NATIVE,5V,CORE

C C

GPIO2 = GPI,5V,CORE
GPIO3 = GPI,5V,CORE
GPIO4 = GPI,5V,CORE
GPIO5 = GPI,5V,CORE

PCI_RST#<28,34>

R408 100K_0402_1%

12

GNT2

Default-Internal pull up

Low=Configures DMI for ESI
compatible operation(for
servers only.Not for
mobile/desktops)

PCI_PME#<34>

B B

CLK_PCI_LPC<34>
CLK_PCI_FB<14>

PCI_REQ0#

PCI_PIRQF#
PCI_REQ3#

PCI_REQ1#
PCI_FRAME#
PCI_ TRDY#
PCI _PIRQH#

PCI_STOP#
PCI_IRDY#
PCI _PIRQD#
PCI_REQ2#

A A

PCI_GNT3#

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

R199 22_0402_5%

1 2
1 2

R211 22_0402_5%

RP5

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP7

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP4

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

R20 0 1K_0402_5%@

1 2

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default

PCI _PIRQC#
PCI _PIRQD#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI _PIRQH#

PCI_SE RR#
PCI_PE RR#

PCI_IRDY#

*

PCI_DEVSEL#
PCI_FRAME#

PCI_LOCK#

PCI_STOP#
PCI_ TRDY#

PLT_RST#

CLK_PCI_LPC_R
CLK_PCI_FB_R

+3VS +3VS

*

5

H40
N34
C44
A38
C36

J34
A40
D45
E36
H48
E40
C40
M48
M45

F53
M40
M43

J36
K48

F40
C42
K46
M51

J52

K51

L34

F42

J40
G46

F44
M47
H36

J50
G42
H47
G34

G38
H51
B37
A44

F51
A46
B45
M53

F48
K45

F36
H53

B41
K53
A36
A48

K6

E44
E50

A42
H44

F46
C46

D49

D41
C48

M7

D5

N52
P53
P46
P51
P48

PCI_PIRQG#
PCI _PIRQC#PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQE#

PCI_DEVSEL#
PCI_LOCK#
PCI_SE RR#
PCI_PE RR#

U7E

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE0#
C/BE1#
C/BE2#
C/BE3#

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PCIRST#

SERR#
PERR#

IRDY#
PAR
DEVSEL#
FRAME#

PLOCK#

STOP#
TRDY#

PME#

PLTRST#

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

IBEXPEAK-M_FCBGA1071

RP3

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP6

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

BUF_PLT_RST#<5,19,28,29>

NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

PCI

USB

0.1U_0402_16V4Z
C646

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

4

AY9

NV_CE#0

BD1

NV_CE#1

AP15

NV_CE#2

BD8

NV_CE#3

AV9

NV_DQS0

BG8

NV_DQS1

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

NV_ALE

BD3

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

AY6

AU2

AV7

AY8
AY5

AV11
BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25

D25

N16
J16
F16
L16
E14
G16
F12
T15

PCI_GNT0#

PCI_GNT1#

NV_CLE

NV_RCOMP

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

USB20_N5
USB20_P5

USB20_N8
USB20_P8

USB20_N10
USB20_P10
USB20_N11
USB20_P11

USB20_N13
USB20_P13

USBRBIAS

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

R212 1K _0402_5%@

R210 1K _0402_5%@

Boot BIOS Strap

0

0

1

R149 0_0402_5%

MC74VHC1G08DFT2G SC70 5P

12

1

R155
100K_0402_5%

2

4

GPIO8

Weak internal PU, don't PD

Check list Rev0.8 section1.23.2
If not implemented, the
Braidwood
interface signals can be
left as No Connect (NC).

GPIO15

*

L Intel ME

Κ

Layer Security(TLS) chiper suite
with no confidentiality

Crypto Transport

H Intel MEΚ Crypto Transport
Layer Security(TLS) chiper suite
with confidentiality

it have weak internal PU 20K

within 500mil

R104

1 2

32.4_0402_1%

@

USB20_N0 <37>
USB2 0_P0 <37>
USB20_N1 <37>
USB2 0_P1 <37>
USB20_N2 <27>
USB2 0_P2 <27>
USB20_N3 <37>
USB2 0_P3 <37>

USB20_N5 <38>
USB2 0_P5 <38>

USB20_N8 <28>
USB2 0_P8 <28>

USB20_N10 <28>
USB20_P10 <28>
USB20_N11 <37>
USB20_P11 <37>

USB20_N13 <28>
USB20_P13 <28>

1 2

R164 22.6_0402_1%

Within 500 mils minimum spacing to other
signal is 15mil

1 2

1 2

PCI_GNT1#PCI_GNT0#

1 2

@

4

U5

0

1

0

11

Y

+3VS

Boot BIOS
Location

LPC

Reserved(NAND)

PCI

SPI

3

1

G

A

2

B

P

5

GPIO27

Κ

Default Do

High EnableΚs the internal VccVRM
to have a clean supply for analog
rails. no need to use on board
filter circuit.

GPIO1 = GPI,3.3V,CORE
GPIO6 = GPI,3.3V,CORE
GPIO7 = GPI,3.3V,CORE
GPIO8 = GPO,3.3V,SUS
GPIO12 = GPI,3.3V,SUS

LEFT USB

LEFT USB (COMBO)

USB Camera

RIGHT USB

checklist 2.0 update 2009.0916

CARD READER

WLAN

EXPRESS

Bluetooth

3G CARD

USB_OC#0 <37>
USB_OC#1 <37>

*

PLT_RST#

3

+3VS

EC_SCI#<34>

EC_SMI#<34>

CPUSB#<28>

+3VALW

GPIO27 if pull down to turn off 1.8V VR

+3VALW

not connect(floating)

6

DRAMRST_CNTRL_PCH<5>

PCH_TE MP_ALERT#<34>

SUSP#<28,34,39,42,44,46> VGA_EN <45>

+3VALW

+3VALW

DIS@

R506 0_0402_5%

1 2

DRAMRST_CNTRL_PCH GPIO 46

Intel Anti-Theft Techonlogy

High=Enabled

NV_ALE

Low=Disable(floating)

NV_ALE

R515 1K _0402_5%@

1 2

*

+1.8VS

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

NV_CLE

R98 1K_0402_5%@

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS SHEET NO R THE INFORMA TION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRI OR WRITTEN CON SENT OF COM PAL ELECTRON ICS, INC.

3

+3VS

Issued Date

GPIO0 = GPI,3.3V,CORE

GPIO0

1 2

R48310K _0402_5%

GPIO1

1 2

R42810K _0402_5%

GPIO6

1 2

R42710K _0402_5%

EC_SCI#

EC_SMI#

CPUSB#

GPIO15

1 2

R4331K _0402_5%

GPIO16

GPIO17

GPIO22

1 2

R44910K _0402_5%

@

12

R50710K _0402_5%

GPIO28

1 2

R44610K _0402_5%

GPIO34

12

R43210K _0402_5%

GPIO35

12

R45610K _0402_5%

GPIO36

GPIO37

1 2

R48110K _0402_5%

GPIO38

1 2

R10910K _0402_5%

GPIO39

1 2

R11210K _0402_5%

GPIO45

1 2

R7610K_0 402_5%

GPIO48

1 2

R48010K _0402_5%

PCH_ TEMP_ALERT#

GPIO57

1 2

R415 10K _0402_5%

1 2

R609 10K _0402_5%

@

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3

USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

NV_ALE

Enable Intel Anti-Theft
Technology 8.2K PU to +3VS

Disable Intel Anti-Theft
Technology

NV_CLE

DMI termination voltage.
weak internal PU, don't PD

2008/08/12 2009/08/12

U7F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CT RL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M_FCBGA1071

RP1

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP2

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

Κ

Κ

floating(internal PD)

Compal Secret Data

Deciphered Date

2

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE 8N

CLKOUT_BCLK0_P / CLKOUT_PCI E8P

GPIO

CPU

NCTF

RSVD

+3VALW

+3VS

+3VS

+3VALW

2

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

A20GATE

PROCPWRGD

THRMTRIP#

INIT3_3V#

1 2

R42 9 10K _0402_5%

1 2

R48 5 10K _0402_5%

1 2

R48 4 10K _0402_5%

R10 7 10K _0402_5%

1 2

R42 6 10K _0402_5%

1 2

R41 4 10K _0402_5%

PCH_ TEMP_ALERT#

12

@

@

1

AH45
AH46

+3VS

PECI

RCIN#

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

TP24

AF48
AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

R110
10K_0 402_5%

1 2

H_PECI

KB_RST#

H_THE RMTRIP#_L

56_0402_5%

56 5%-->checklist 1.6

54.9 1%-->CRB 1.0

+3VALW

INT3_3V#

TP24

GATEA20 <34>

CLK_CPU_BCLK# <5>

CLK_CPU_BCLK <5>

H_PECI <5>

KB_RST# <34>

H_CPUPWRGD <5>

R518

1 2

R519

56_0402_5%

KB_RST#

H_THERMTRIP# <5>

12

+VCCP

DRAMRST_CNTRL_PCH

12

R40 5 10K_0402_5%

USB PORT LIST

DEVICEPORT

RIGHT SIDE0

1

LEFT SIDE
CMOS

GPIO17

GPIO36

2

LEFT SIDE

3
4

CARD READER

5
6

GPIO16

EC_SCI#

EC_SMI#

7

9
10
11

WIRELESS8

NEW CARD
BT

12

3G

13

Title

Size D ocument Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

LA-5752P

1

+3VS

12

R111
10K_0 402_5%

0.3

of

16 51Thursday, October 29, 2009

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