intersil FN7415.2, EL7640, EL7641, EL7642 DATA SHEET

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EL7640, EL7641, EL7642

Data Sheet February 22, 2006

TFT-LCD DC/DC with Integrated Amplifiers

The EL7640, EL7641, and EL7642 integrate a high performance boost regulator with 2 LDO controllers for V and V

, a VON-slice circuit with adjustable delay and

OFF

either one (EL7640), three (EL7641), or five amplifiers (EL7642) for V

COM

and V

GAMMA

applications.

The boost converter in the EL7640, EL7641, and EL7642 is a current mode PWM type integrating an 18V N-channel MOSFET. Operating at 1.2MHz, this boost can operate in either P-mode for superior transient response, or in PI-mode for tighter output regulation.

Using external low-cost transistors, the LDO controllers provide tight regulation for V

, V

, as well as providing

OFF

start-up sequence control and fault protection.

The amplifiers are ideal for V

COM

and V

GAMMA

applications, with 150mA peak output current drive, 12MHz bandwidth, and 12V/µs slew rate. All inputs and outputs are rail-to-rail.

Available in the 32 Ld thin QFN (5mm x 5mm) Pb-free packages, the EL7640, EL7641, and EL7642 are specified for operation over the -40°C to +85°C temperature range.

Ordering Information

PART NUMBER

(Note)

EL7640ILTZ 7640ILTZ - 32 Ld 5x5

EL7640ILTZ-T7 7640ILTZ 7” 32 Ld 5x5

EL7640ILTZ-T13 7640ILTZ 13” 32 Ld 5x5

EL7641ILTZ 7641ILTZ - 32 Ld 5x5

EL7641ILTZ-T7 7641ILTZ 7” 32 Ld 5x5

EL7641ILTZ-T13 7641ILTZ 13” 32 Ld 5x5

EL7642ILTZ 7642ILTZ - 32 Ld 5x5

EL7642ILTZ-T7 7642ILTZ 7” 32 Ld 5x5

EL7642ILTZ-T13 7642ILTZ 13” 32 Ld 5x5

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PAR T

MARKING

TAPE &

REEL

PACKAGE

(Pb-Free)

Thin QFN

PKG.

DWG. #

MDP0051

FN7415.2

Features

• Current mode boost regulator

- Fast transient response

- 1% accurate output voltage

- 18V/3A integrated FET

- >90% efficiency

• 2.6V to 5.5V V

• 2 LDO controllers for V

supply

and V

OFF

- 2% output regulation

-slice circuit

-V

• High speed amplifiers

- 150mA short-circuit output current

-12V/µs slew rate

- 12MHz -3dB bandwidth

- Rail-to-rail inputs and outputs

• Built-in power sequencing

• Internal soft-start

• Multiple overload protection

• Thermal shutdown

• 32 Ld 5x5 thin QFN package

• Pb-Free plus anneal available (RoHS compliant)

Applications

• TFT-LCD panels

• LCD monitors

• Notebooks

•LCD-TVs

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinouts

EL7640

(32 LD QFN)

TOP VIEW

EL7640, EL7641, EL7642

EL7641

(32 LD QFN)

TOP VIEW

COM

DRN

CTL

DEL

DRVN

SRC

REF

AGND

PGND

OUT1

NEG1

POS1

8 17

NC = NOT INTERNALLY CONNECTED IC = INTERNALLY CONNECTED

10 IC

THERMAL

PAD

BGND

EL7642

(32 LD QFN)

TOP VIEW

DRVP

26925

152716

FBP

COMP

COM

DRN

CTL

DEL

DRVN

SRC

REF

AGND

PGND

OUT1

NEG1

POS1

OUT2

8 17

NEG2

NC = NOT INTERNALLY CONNECTED IC = INTERNALLY CONNECTED

POS2

THERMAL

PAD

BGND

DRVP

26925

152716

POS3

FBP

NEG3

COMP

OUT3

FBN

SUP

FBN

SUP

COM

DRN

CTL

DEL

DRVN

SRC

REF

AGND

PGND

OUT1

NEG1

POS1

OUT2

8 17

NEG2

POS2

THERMAL

PAD

POS3

BGND

OUT3

DRVP

26925

152716

POS4

FBP

NEG4

COMP

OUT5

NEG5

POS5

OUT4

FBN

SUP

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

Absolute Maximum Ratings (T

IN, CTL to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

COMP, FB, FBP, FBN, DEL, REF to AGND. . . . . -0.3V to V

PGND, BGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V

LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V

SUP to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18V

DRVP, SRC to AGND . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +36V

POS1, NEG1, OUT1, POS2, NEG2, OUT2, POS3, OUT3, POS4, NEG4, OUT4, POS5, OUT5 to AGND . .-0.3V to V

DRVN to AGND . . . . . . . . . . . . . . . . . . . . . . . V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = T

Electrical Specifications V

= 25°C)

= 3V, V

= V

SUP

-20V to VIN +0.3V

BOOST

+0.3V

= 12V, V

COM, DRN to AGND . . . . . . . . . . . . . . . . . . . . -0.3V to V

LX Maximum Continuous RMS Output Current. . . . . . . . . . . . . 1.6A

OUT1, OUT2, OUT3, OUT4, OUT5

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . ±75mA

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Maximum Continuous Junction Temperature . . . . . . . . . . . . +125°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Operating Ambient Temperature . . . . . . . . . . . . . . . . -40°C to +85°C

= 20V, Over temperature from -40°C to 85°C.

SRC

+0.3V

Unless Otherwise Specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SUPPLY

LOR

LOF

REF

Input Supply Range 2.6 5.5 V

Undervoltage Lockout Threshold VIN rising 2.4 2.5 2.6 V

Undervoltage Lockout Threshold VIN falling 2.2 2.3 2.4 V

Quiescent Current LX not switching 2.5 mA

Quiescent Current - Switching LX switching 5 10 mA

Fault Delay Time C

= 220nF 52 ms

DEL

Reference Voltage TA= 25°C 1.19 1.215 1.235 V

1.187 1.215 1.238 V

SHUTDN Thermal Shutdown Temperature 140 °C

MAIN BOOST REGULATOR

BOOST

Output Voltage Range (Note 1) VIN+

18 V

15%

OSC

FBB

Oscillator Frequency 1050 1200 1350 kHz

Maximum Duty Cycle 82 85 %

Boost Feedback Voltage TA= 25°C 1.192 1.205 1.218 V

1.188 1.205 1.222 V

FTB

∆V ∆I

BOOST

∆V ∆V

BOOST

BOOST IN

FB Fault Trip Level Falling edge 0.85 0.925 1.020 V

Load Regulation 50mA < I

Line Regulation VIN = 2.6V to 5.5V 0.08 %/V

< 250mA 0.1 %

LOAD

Input Bias Current VFB = 1.35V 500 nA

gmV FB Transconductance dI = ±2.5µA at COMP, FB = COMP 160 µA/V

LX LX On Resistance 160 mΩ

LX LX Leakage Current VFB = 1.35V, V

LEAK

LX LX Current Limit Duty cycle = 65% (Note 1) 3.0 A

LIM

B Soft-Start Period C

= 220nF 2 ms

DEL

= 13V 0.02 40 µA

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

Electrical Specifications V

= 3V, V

BOOST

= V

SUP

= 12V, V

= 20V, Over temperature from -40°C to 85°C.

SRC

Unless Otherwise Specified. (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

OPERATIONAL AMPLIFIERS

SUP

CMIR Common Mode Input Range 0 V

Supply Operating Range 4.5 18 V

Supply Current per Amplifier 600 800 µA

Offset Voltage 312mV

Input Bias Current -50 +50 nA

SUP

CMRR Common Mode Rejection Ratio 60 90 dB

CONT

Open Loop Gain 110 dB

Output Voltage High I

Output Voltage Low I

= 100µA V

OUT

= 5mA V

OUT

-15

-250

= -100µA 2 30 mV

OUT

= -5mA 100 150 mV

OUT

SUP

-150

SUP

-2

SUP

Short-Circuit Current 100 150 mA

Continuous Output Current ±50 mA

PSRR Power Supply Rejection Ratio 60 100 dB

-3dB

-3dB Bandwidth 12 MHz

GBWP Gain Bandwidth Product 8MHz

SR Slew Rate 12 V/µs

POSITIVE LDO

FBP

FTP

∆V

POS

∆I

POS

DRVP

P DRVP Off Leakage Current V

LEAK

P Soft-Start Period C

Positive Feedback Voltage I

Fault Trip Level V

FBP

Positive LDO Input Bias Current V

FBP Load Regulation V

Sink Current V

= 100µA, TA = 25°C 1.176 1.2 1.224 V

DRVP

= 100µA 1.176 1.2 1.229 V

DRVP

falling 0.82 0.9 0.98 V

FBP

= 1.4V -50 50 nA

FBP

= 25V, I

DRVP

= 1.1V, V

FBP

= 1.4V, V

FBP

= 220nF 2 ms

DEL

= 0 to 20µA 0.5 %

DRVP

= 10V 2 4 mA

DRVP

= 30V 0.1 10 µA

DRVP

NEGATIVE LDO

FBN

FTN

DRVN

N DRVN Off Leakage Current V

LEAK

N Soft-start Period C

FBN Regulation Voltage I

Fault Trip Level V

FBN

Negative LDO Input Bias Current V

FBN Load Regulation V

Source Current V

= 0.2mA, TA = 25°C 0.173 0.203 0.233 V

DRVN

= 0.2mA 0.171 0.203 0.235 V

DRVN

rising 380 430 480 mV

FBN

= 250mV -50 50 nA

FBN

= -6V, I

DRVN

= 500mV, V

FBN

= 1.35V, V

FBP

= 220nF 2 ms

DEL

= 2µA to 20µA 0.5 %

DRVN

= -6V 2 4 mA

DRVN

= 30V 0.1 10 µA

DRVP

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

Electrical Specifications V

= 3V, V

BOOST

= V

SUP

= 12V, V

= 20V, Over temperature from -40°C to 85°C.

SRC

Unless Otherwise Specified. (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

VON-SLICE CIRCUIT

CTL CTL Input Leakage Current CTL = AGND or IN -1 1 µA

LEAK

rise CTL to OUT Rising Prop Delay 1kΩ from DRN to 8V, V

fall CTL to OUT Falling Prop Delay 1kΩ from DRN to 8V, V

SRC

CTL Input Low Voltage VIN = 2.6V to 5.5V 0.4V

CTL Input High Voltage VIN = 2.6V to 5.5V 0.6V

= 0V to 3V step, no load on OUT, measured from V to OUT = 20%

no load on OUT, measured from V to OUT = 80%

CTL

= 3V to 0V step,

CTL

= 1.5V

100 ns

SRC Input Voltage Range 30 V

ISRC SRC Input Current Start-up sequence not completed 150 250 µA

Start-up sequence completed 150 250 µA

SRC SRC On Resistance Start-up sequence completed 5 10 Ω

DRN DRN On Resistance Start-up sequence completed 30 60 Ω

RONCOM COM to GND On Resistance Start-up sequence not completed 350 1000 1800 Ω

SEQUENCING

DEL1

DEL2

DEL3

DEL

Turn On Delay C

Delay Between V

Delay Between VON and V

BOOST

and V

OFF

Delay From VON to VON-slice Enabled C

= 0.22µF (See Figure 23) 30 ms

DLY

= 0.22µF (See Figure 23) 10 ms

DLY

= 0.22µF (See Figure 23) 17 ms

DLY

= 0.22µF (See Figure 23) 10 ms

DLY

Delay Capacitor 50 220 nF

NOTE:

1. Guaranteed by design.

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

Pin Descriptions

PIN NAME EL7642 EL7641 EL7640 PIN FUNCTION

SRC 1 1 1 Upper reference voltage for switch output

REF 2 2 2 Internal reference bypass terminal

AGND 3 3 3 Analog ground for boost converter and control circuitry

PGND 4 4 4 Power ground for boost switch

OUT1 5 5 5 Operational amplifier 1 output

NEG1 6 6 6 Operational amplifier 1 inverting input

POS1 7 7 7 Operational amplifier 1 non-inverting input

OUT2 8 8 - Operational amplifier 2 output

NEG2 9 9 - Operational amplifier 2 inverting input

POS2 10 10 - Operational amplifier 2 non-inverting input

BGND 11 11 11 Operational amplifier ground

POS3 12 15 - Operational amplifier 3 non-inverting input

NEG3 - 16 - Operational amplifier 3 inverting input

OUT3 13 17 - Operational amplifier 3 output

SUP 14 14 14 Amplifier positive supply rail. Bypass to BGND with 0.1µF capacitor

POS4 15 - - Operational amplifier 4 non-inverting input

NEG4 16 - - Operational amplifier 4 inverting input

OUT4 17 - - Operational amplifier 4 output

POS5 18 - - Operational amplifier 5 non-inverting input

NEG5 19 - - Operational amplifier 5 inverting input

OUT5 20 - - Operational amplifier 5 output

LX 21 21 21 Main boost regulator switch connection

IN 22 22 22 Main supply input; bypass to AGND with 1µF capacitor

FB 23 23 23 Main boost feedback voltage connection

COMP 24 24 24 Error amplifier compensation pin

FBP 25 25 25 Positive LDO feedback connection

DRVP 26 26 26 Positive LDO transistor drive

FBN 27 27 27 Negative LDO feedback connection

DRVN 28 28 28 Negative LDO transistor driver

DEL 29 29 29 Connection for switch delay timing capacitor

CTL 30 30 30 Input control for switch output

DRN 31 31 31 Lower reference voltage for switch output

COM 32 32 32 Switch output; when CTL = 1, COM is connected to SRC through a 15Ω

resistor; when CTL = 0, COM is connected to DRN through a 30Ω resistor

FN7415.2

February 22, 2006

Typical Performance Curves

EL7640, EL7641, EL7642

100

90 80 70 60 50 40 30

EFFICIENCY (%)

20 10

0 200 400 600 800 1000 1200

=3V

LOAD CURRENT (mA)

FIGURE 1. BOOST EFFICIENCY AT V

-0.1

-0.2

-0.3

-0.4

VIN=5V

-0.5

LOAD REGULATION (%)

-0.6 0 200 400 600 800 1000 1200

LOAD CURRENT (mA)

VIN=5V

=3V

= 12V (PI MODE) FIGURE 2. BOOST EFFICIENCY AT V

OUT

FIGURE 3. BOOST LOAD REGULATION vs LOAD CURRENT

(PI MODE)

94 92 90 88 86

=3V

EFFICIENCY (%)

-10

LOAD REGULATION (%)

-12

-14

84 82 80 78

-2

-4

-6

-8

0 200 400 600 800 1000 1200

LOAD CURRENT (mA)

VIN=3.3V

0 200 400 600 800 1000 1200

LOAD CURRENT (mA)

VIN=5V

VIN=5.0V

= 12V (P MODE)

OUT

FIGURE 4. BOOST LOAD REGULATION vs LOAD CURRENT

(P MODE)

0.12

0.1

0.08

0.06

0.04

LINE REGULATION (%)

0.02

3 3.5 4 4.5 5 5.5 6

INPUT VOLTAGE (V)

FIGURE 5. BOOST LINE REGULATION vs INPUT VOLTAGE

(PI MODE)

3.5 3

2.5 2

1.5 1

LINE REGULATION (%)

0.5 0

33.544.555.56 INPUT VOLTAGE (V)

FIGURE 6. BOOST LINE REGULATION vs INPUT VOLTAGE

(P MODE)

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

Typical Performance Curves (Continued)

BOOST OUTPUT

VOLTAGE

(AC COUPLING)

BOOST OUTPUT

CURRENT

BOOST

OUT

=12V

=30µF

-0.05

-0.1

-0.15

-0.2

LOAD REGULATION (%)

-0.25 5 1015202530

LOAD CURRENT (mA)

VON=20V

FIGURE 7. BOOST PULSE LOAD TRANSIENT RESPONSE FIGURE 8. VON LOAD REGULATION

-0.02

-0.04

-0.06

-0.08

-0.1

LINE REGULATION (%)

-0.12 20 21 22 23 24 25 26

INPUT VOLTAGE (V)

VON=20V I

LOAD

=20mA

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

LOAD REGULATION (%)

-0.8

-0.9 5 1015202530

LOAD CURRENT (mA)

OFF

=-8V

FIGURE 9. V

-0.1

-0.2

-0.3

-0.4 V

=-8V

OFF

-0.5

LINE REGULATION (%)

LOAD

-0.6

-15-14-13-12-11-10

FIGURE 11. V

LINE REGULATION FIGURE 10. V

=50mA

INPUT VOLTAGE (V)

LINE REGULATION FIGURE 12. START-UP SEQUENCE

OFF

CDLY

BOOST

OFF

LOAD REGULATION

OFF

DEL

TIME (20ms/DIV)

=220nF

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

Typical Performance Curves (Continued)

INPUT

VOLTAGE

BOOST

INPUT

OFF

TIME (20ms/DIV)

=220nF

DEL

FIGURE 13. START-UP SEQUENCE FIGURE 14. OP AMP RAIL-TO-RAIL INPUT/OUTPUT

JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD

0.8

0.7 758mW

0.6

0.5

0.4

0.3

0.2

0.1

POWER DISSIPATION (W)

0 255075100 150

AMBIENT TEMPERATURE (°C)

QFN32

θJA=125°C/W

12585

FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

OUTPUT

TIME (50µs/DIV)

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5

2.857W

2.5

1.5

0.5

POWER DISSIPATION (W)

0 255075100 150

AMBIENT TEMPERATURE (°C)

QFN32

θJA=35°C/W

12585

FIGURE 16. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

Applications Information

The EL7640, EL7641, EL7642 provide a highly integrated multiple output power solution for TFT-LCD applications. The system consists of one high efficiency boost converter and two low cost linear-regulator controllers (V V

) with multiple protection functions. The block diagram

OFF

of the whole part is shown in Figure 17. Table 1 lists the recommended components.

The EL7640, EL7641, EL7642 integrate an N-channel MOSFET in boost converter to minimize the external component counts and cost. The V

, V

OFF

regulators are independently regulated by using external resistors. To achieve higher voltage than V multiple stage charge pumps may be used.

linear-

BOOST

and

, one or

TABLE 1. RECOMMENDED COMPONENTS

DESIGNATION DESCRIPTION

, C2, C310µF, 16V X5R ceramic capacitor (1210)

TDK C3216X5R0J106K

1A 20V low leakage schottky rectifier (CASE 457-04) ON SEMI MBRM120ET3

, D12, D21200mA 30V schottky barrier diode (SOT-23)

Fairchild BAT54S

6.8µH 1.3A Inductor TDK SLF6025T-6R8M1R3-PF

200mA 40V PNP amplifier (SOT-23) Fairchild MMBT3906

200mA 40V NPN amplifier (SOT-23) Fairchild MMBT3904

FN7415.2

February 22, 2006

REF

REFERENCE

GENERATOR

EL7640, EL7641, EL7642

OSCILLATOR

FBB

INT

DRVN

THERMAL

SHUTDOWN

BUFFER

AMPLIFIER

UVLO

COMPARATOR

COMPENSATION

VOLTAGE

AMPLIFIER

SHUTDOWN

& START-UP

CONTROL

0.2V

SLOPE

COMP

LIMIT COMPARATOR

OSC

PWM

LOGIC

CONTROLLER

CURRENT

AMPLIFIER

CURRENT

UVLO

COMPARATOR

CURRENT REF

REF

BUFFER

PGND

DRVP

BUFFER

FBP

FBN

0.4V UVLO

COMPARATOR

FIGURE 17. BLOCK DIAGRAM

Boost Converter

The main boost converter is a current mode PWM converter operating at a fixed frequency. The 1.2MHz switching frequency enables the use of low profile inductor and multilayer ceramic capacitors, which results in a compact, low cost power system for LCD panel design.

The boost converter can operate in continuous or discontinuous inductor current mode. The EL7640, EL7641, EL7642 are designed for continuous current mode, but they can also operate in discontinuous current mode at light load. In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by:

BOOST

----------------------- -

Where D is the duty cycle of switching MOSFET.

-------------=

1D–

Figure 18 shows the block diagram of the boost controller. It uses a summing amplifier architecture consisting of GM stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached.

An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60kΩ is recommended. The boost converter output voltage is determined by the following equation:

R1R

BOOST

---------------------

×=

REF

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

The current through MOSFET is limited to 3A peak. This restricts the maximum output current based on the following equation:

∆I

OMAXILMT

 

---------

--------–

×=

SLOPE

COMPENSATION

REF

CURRENT

AMPLIFIER

Where ∆IL is peak to peak inductor ripple current, and is set by:

---- -

---------

∆I

where f

CLOCK

LOGIC

PWM

×=

is the switching frequency.

SHUTDOWN

& START-UP

CONTROL

BUFFER

FBB

AMPLIFIER

VOLTAGE

AMPLIFIER

REFERENCE GENERATOR

COMP

REF

FIGURE 18. THE BLOCK DIAGRAM OF THE BOOST CONTROLLER

PGND

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

The following table gives typical values (margins are considered 10%, 3%, 20%, 10% and 15% on V and I

LMT

TABLE 2.

(V) VO (V) L (µH) fS (MHz) I

3.3 9 6.8 1.2 898

3.3 12 6.8 1.2 622

3.3 15 6.8 1.2 458

5 9 6.8 1.2 1360

5126.81.2 944

5156.81.2 694

, VO, L, fS

OMAX

(mA)

Input Capacitor

The input capacitor is used to supply the current to the converter. It is recommended that C The reflected ripple voltage will be smaller with larger C

be larger than 10µF.

. The voltage rating of input capacitor should be larger than maximum input voltage.

Boost Inductor

The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Value of 3.3µH to 10µH inductor is recommended in applications to fit the internal slope compensation. The inductor must be able to handle the following average and peak current:

LAVG

LPKILAVG

-------------=

1D–

∆I

--------+=

Rectifier Diode

A high-speed diode is desired due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The rectifier diode must meet the output current and peak inductor current requirements.

For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage.

NOTE: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. C

in the equation above assumes the effective value of the

OUT

capacitor at a particular voltage and not the manufacturer’s stated value, measured at zero volts.

Compensation

The EL7640, EL7641, EL7642 can operate in either P mode or PI mode. Connecting COMP pin directly to V

will enable

P mode; For better load regulation, use PI mode with a

2.2nF capacitor and a 180Ω resistor in series between COMP pin and ground. To improve the transient response, either the resistor value can be increased or the capacitor value can be reduced, but too high resistor value or too low capacitor value will reduce loop stability.

Boost Feedback Resistors

As the boost output voltage, V the effective voltage feedback in the IC increases the ratio of voltage to current feedback at the summing comparator because R2 decreases relative to R1. To maintain stable operation over the complete current range of the IC, the voltage feedback to the FBB pin should be reduced proportionally, as V

is reduced, by means of a series

BOOST

resistor-capacitor network (R7 and C7) in parallel with R1, with a pole frequency (fp) set to approximately 10kHz. for C2 effective = 10µF and 4kHz for C2 (effective) = 30µF.

R7 = ((1/0.1 x R2) – 1/R1)^-1

C7 = 1/(2 x 3.142 x fp x R7)

Linear-Regulator Controllers (VON and V

The EL7640, EL7641, EL7642 include 2 independent linear-regulator controllers, in which there is one positive output voltage (V V

and V

OFF

application circuit and waveforms are shown in Figure 19 and Figure 20 respectively.

), and one negative voltage (V

linear-regulator controller function diagram,

, is reduced below 12V

BOOST

OFF

)

). The

Output Capacitor

The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor.

RIPPLEILPK

ESR

–

OVIN

----------------------- -

----------------

OUT

---- -

××+×=

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

0.9V

PG_LDOP

GMP

LDO_ON

1: Np

36V

ESD

CLAMP

700Ω

DRVP

FBP

20kΩ

FIGURE 19. VON FUNCTIONAL BLOCK DIAGRAM

PG_LDON

0.4V

GMN

CLAMP

36V ESD

1: Nn

LDO_OFF

FBN

DRVN

700Ω

20kΩ

REF

BOOST

0.1µF

CP (TO 36V)

0.1µF

VON (TO 35V)

CP (TO -26V)

0.1µF

(TO -20V)

OFF

The V

power supply is used to power the negative

OFF

supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_OFF). The LDO_OFF regulator uses an external NPN transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 5mA output current, which is sufficient for up to 50mA or more output current under the low dropout condition (forced beta of 10). Typical V

voltage supported by EL7640, EL7641

OFF

and EL7642 ranges from -5V to -25V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 200mV above the 0.2V reference level.

Set-up Output Voltage

Refer to Typical Application Diagram, the output voltages of V

, V

OFF

and V

are determined by the following

LOGIC

equations:



ONVREF

OFFVREFN

Where V

REF

--------- -+

×=





--------- -

= 1.2V, V

REFN

–()×+=

REFNVREF

= 0.2V.

High Charge Pump Output Voltage (>36V) Applications

In the applications where the charge pump output voltage is over 36V, an external NPN transistor needs to be inserted in between the DRVP pin and the base of pass transistor Q3 as shown in Figure 21, or the linear regulator can control only one stage charge pump and regulate the final charge pump output as shown in Figure 22.

VIN

OR V

BOOST

CHARGE PUMP OUTPUT

FIGURE 20. V

FUNCTIONAL BLOCK DIAGRAM

OFF

The VON power supply is used to power the positive supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_ON). The LDO_ON regulator uses an external PNP transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 5mA output current, which is sufficient for up to 50mA or more output current under the low dropout condition (forced beta of 10). Typical V

voltage supported by EL7640, EL7641 and EL7642

ranges from +15V to +36V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 25% below the 1.2V reference.

700Ω

Q11

EL764X

DRVP

FBP

NPN

CASCODE

TRANSISTOR

FIGURE 21. CASCODE NPN TRANSISTOR CONFIGURATION

FOR HIGH CHARGE PUMP OUTPUT VOLTAGE (>36V)

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

0.1µF

700Ω

DRVP

EL7642

FBP

FIGURE 22. THE LINEAR REGULATOR CONTROLS ONE STAGE OF CHARGE PUMP

0.47µF

Calculation of the Linear Regulator Base-emitter Resistors (RBP and RBN)

For the pass transistor of the linear regulator, low frequency gain (Hfe) and unity gain frequency (f in the datasheet. The pass transistor adds a pole to the loop transfer function at fp = f

T/Hfe. Therefore, in order to

maintain phase margin at low frequency, the best choice for a pass device is often a high frequency low gain switching transistor. Further improvement can be obtained by adding a base-emitter resistor R

(RBP, RBL, RBN in the Functional

Block Diagram), which increases the pole frequency to: fp = fT*(1+ Hfe *re/R the lowest value R enough base current (I current (I

)/Hfe, where re = KT/qIc. So choose

in the design as long as there is still

) to support the maximum output

We will take as an example the VON linear regulator. If a Fairchild MMBT3906 PNP transistor is used as the external pass transistor, Q11 in the application diagram, then for a maximum V

operating requirement of 50mA the data

sheet indicates Hfe_min = 60. The base-emitter saturation voltage is: Vbe_max = 0.7V.

For the EL7640, EL7641 and EL7642, the minimum drive current is: I_DRVP_min = 2mA

The minimum base-emitter resistor, RBP, can now be calculated as: RBP_min = VBE_max/(I_DRVP_min - Ic/Hfe_min) =

0.7V/(2mA - 50mA/60) = 600Ω

This is the minimum value that can be used – so, we now choose a convenient value greater than this minimum value; say 700Ω. Larger values may be used to reduce quiescent current, however, regulation may be adversely affected by supply noise if R

is made too high in value.

T) are usually specified

BOOST

0.22µF

(>36V)

Q11

0.1µF

Charge Pump

To generate an output voltage higher than V multiple stages of charge pumps are needed. The number of stage is determined by the input and output voltage. For positive charge pump stages:

POSITIVE

where V

OUTVCEVINPUT

--------------------------------------------------------------

≥

INPUT

is the dropout voltage of the pass component of

–+

2VF×–

the linear regulator. It ranges from 0.3V to 1V depending on the transistor selected. V

is the forward-voltage of the

charge-pump rectifier diode.

The number of negative charge-pump stages is given by:

NEGATIVE

OUTPUTVCE

-------------------------------------------------

≥

INPUT

2VF×–

To achieve high efficiency and low material cost, the lowest number of charge-pump stages, which can meet the above requirements, is always preferred.

Charge Pump Output Capacitors

Ceramic capacitor with low ESR is recommended. With ceramic capacitors, the output ripple voltage is dominated by the capacitance value. The capacitance value can be chosen by the following equation:

OUT

where f

------------------------------------------------------

≥

OUT

OSC

××

RIPPLEfOSC

is the switching frequency.

Discontinuous/Continuous Boost Operation and its Effect on the Charge Pumps

The EL7640, EL7641 and EL7642 VON and V architecture uses LX switching edges to drive diode charge pumps from which LDO regulators generate the V

BOOST

OFF

, single or

and

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

supplies. It can be appreciated that should a regular

OFF

supply of LX switching edges be interrupted, for example during discontinuous operation at light boost load currents, then this may affect the performance of V regulation – depending on their exact loading conditions at the time.

To optimize V

ON/VOFF

regulation, the boundary of discontinuous/continuous operation of the boost converter can be adjusted, by suitable choice of inductor given V V

, switching frequency and the V

OUT

BOOST

to be in continuous operation.

The following equation gives the boundary between discontinuous and continuous boost operation. For continuous operation (LX switching every clock cycle) we require that:

I(V

where the duty cycle, D = (V

For example, with VIN = 5V, F

_load) > D*(1-D)*VIN/(2*L*F

BOOST

– VIN)/V

BOOST

= 1.2MHz and V

OSC

12V we find continuous operation of the boost converter can be guaranteed for: L = 10µH and I(V L = 6.8µH and I(V L = 3.3µH and I(V

BOOST

) > 51mA

) > 74mA ) > 153mA

and V

current loading,

)

OSC

BOOST

OFF

BOOST

Start-up Sequence

Figure 23 shows a detailed start-up sequence waveform. For a successful power-up, there should be 6 peaks at V When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled.

When the input voltage is higher than 2.4V, an internal current source starts to charge C

. During the initial slow

CDLY

ramp, the device checks whether there is a fault condition. If no fault is found during the initial ramp, C after the first peak. V

turns on at the peak of the first

REF

is discharged

CDLY

ramp.

Initially the boost is not enabled so V V V

through the output diode. Hence, there is a step at

DIODE

during this part of the start-up sequence.

BOOST

soft-starts at the beginning of the third ramp, and is

BOOST

rises to VIN-

checked at the end of this ramp. The soft-start ramp depends on the value of the C

capacitor. For C

DLY

220nF, the soft-start time is ~2ms.

turns on at the start of the fourth peak.

OFF

is enabled at the beginning of the sixth ramp. V

are checked at end of this ramp.

DLY

OFF

CDLY

and

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

BOOST

CDLY

REF

DEL1

BOOST

OFF

SOFT-START

FAULT DETECTEDCHIP DISABLED

OFF

ON SLICE

CIRCUIT

START-UP SEQUENCE

TIMED BY C

FIGURE 23. START-UP SEQUENCE

Component Selection for Start-up Sequencing and Fault Protection

The C to stabilize the V 22nF to 1µF and should not be more than five times the capacitor on C

The C range from 47nF minimum to several microfarads – only limited by the leakage in the capacitor reaching µA levels.

capacitor is typically set at 220nF and is required

REF

capacitor is typically 220nF and has a usable

DEL

output. The range of C

REF

to ensure correct start-up operation.

DEL

REF

is from

DEL2

DEL3

DLY

should be at least 1/5 of the value of C

DEL

OPERATION

above). Note with 220nF on C

NORMAL

FAULT

PRESENT

(see

the fault time-out will be

DEL

REF

typically 50ms and the use of a larger/smaller value will vary this time proportionally (e.g. 1µF will give a fault time-out period of typically 230ms).

Fault Sequencing

The EL7640, EL7641 and EL7642 have an advanced fault detection system which protects the IC from both adjacent pin shorts during operation and shorts on the output

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

supplies. A high quality layout/design of the PCB, in respect of grounding quality and decoupling is necessary to avoid falsely triggering the fault detection scheme – especially during start-up. The user is directed to the layout guidelines and component selection sections to avoid problems during initial evaluation and prototype PCB generation.

VON-Slice Circuit

The VON-slice Circuit functions as a three way multiplexer, switching the voltage on COM between ground, DRN and SRC, under control of the start-up sequence and the CTL pin.

During the start-up sequence, COM is held at ground via an NDMOS FET, with ~1k impedance. Once the start-up sequence has completed, CTL is enabled and acts as a multiplexer control such that if CTL is low, COM connects to DRN through a 5Ω internal MOSFET, and if CTL is high, COM connects to SRC via a 30Ω MOSFET.

The slew rate of start-up of the switch control circuit is mainly restricted by the load capacitance at COM pin as in the following equation:

∆V

------- -

∆t

Where V circuit, R including the internal MOSFET r and the resistor inserted, R switch control circuit, and C

------------------------------------=

()C

RiR

•

is the supply voltage applied to the switch control

is the resistance between COM and DRN or SRC

DS(ON)

is the load resistance of the

is the load capacitance of the

, the trace resistance

switch control circuit.

In the Typical Application Circuit, R

, R9 and C8 give the

bias to DRN based on the following equation:

DRN

and R

VONR9A

-------------------------------------------------------------=

8R9

can be adjusted to adjust the slew rate.

VDDR8

•+•

Op Amps

The EL7640, EL7641 and EL7642 have 1, 3 and 5 amplifiers respectively. The op amps are typically used to drive the TFT-LCD backplane (V divider string. They feature rail-to-rail input and output capability, they are unity gain stable, and have low power consumption (typical 600µA per amplifier). The EL7640, EL7641 and EL7642 have a –3dB bandwidth of 12MHz while maintaining a 10V/µs slew rate.

Short Circuit Current Limit

The EL7640, EL7641 and EL7642 will limit the short circuit current to ±180mA if the output is directly shorted to the positive or the negative supply. If an output is shorted for a long time, the junction temperature will trigger the Over Temperature Protection limit and hence the part will shut down.

) or the gamma-correction

COM

Driving Capacitive Loads

EL7640, EL7641 and EL7642 can drive a wide range of capacitive loads. As load capacitance increases, however, the –3dB bandwidth of the device will decrease and the peaking will increase. The amplifiers drive 10pF loads in parallel with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain. Another method of reducing peaking is to add a “snubber” circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current and reduce the gain.

Over-Temperature Protection

An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point, the device will be latched off until either the input supply voltage or enable is cycled.

Layout Recommendation

The device’s performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency.

There are some general guidelines for layout:

1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance.

2. Place V

3. Reduce the loop with large AC amplitudes and fast slew rate.

4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible.

5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point.

6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC.

7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air.

and VDD bypass capacitors close to the pins.

REF

FN7415.2

February 22, 2006

EL7640, EL7641, EL7642

8. A signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for feedback resistor networks (R1, R11, R41) and the V

capacitor, C22, the C

REF

DELAY

capacitor

C7 and the integrator capacitor C23.

Typical Application Circuit

(2.6V-5.5V)

INPUT

220nF

MAIN

COM4

470nF

180Ω

2.2nF

10Ω

COMP

DRVN

FBN

REF

CTL

DEL

VDD

NEG4

OUT4

POS4

NEG REG

REF

OP4

(-8V)

0.1µF

NEG

470nF

R22

R21

Q21

700Ω

82kΩ

10kΩ

0.1µF

10µF

CONTROL

COM FB4

COM SET4

9. Minimize feedback input track lengths to avoid switching noise pick-up.

A demo board is available to illustrate the proper layout implementation.

D11

D21

6.8µH

BOOST

POS REG

CTL

0.1µF

D12

0.1µF

10.2kΩ

PGND

GND

DRVP

FBP

SRC

COM

DRIVER IC

DRN

OP3

OP5

OUT3

POS3

NEG5

OUT5

POS5

0.1µF

64.9kΩ

700Ω

R12

R11

TO GATE

100kΩ

1kΩ

GAMMA

GAMMA SET

COM FB3

COM3

COM SET3

10µFx2

R7 OPEN

OPEN

Q11

182kΩ

9.76kΩ

68kΩ

0.1µF

VDD

(9V)

1kΩ

0.1µF

470nF

(24.5V)

VDD

COM FB2

COM2

COM SET2

NEG2

OUT2

POS2

OP2

AGND

NEG1

OP1

OUT1

POS1

COM FB1

COM1

COM SET1

FN7415.2

February 22, 2006

QFN Package Outline Drawing

EL7640, EL7641, EL7642

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7415.2

February 22, 2006

intersil FN7415.2, EL7640, EL7641, EL7642 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual