Datasheet FOD2200 Datasheet (Fairchild)

FOD2200 — Low Input Current Logic Gate Optocouplers

August 2010

FOD2200 Low Input Current Logic Gate Optocouplers

Features

■

1kV/µs minimum common mode rejection Compatible with LSTTL, TTL, and CMOS logic

■

Wide V

2.5Mbd guaranteed over temperature

■

Low input current (1.6mA) Three state output (no pullup resistor required)

■

Guaranteed performance from 0°C to 85°C

■

Hysteresis Safety and regulatory approved

■

– UL1577, 5000 V

range (4.5V to 20V)

CC

for 1 min.

RMS

– IEC60747-5-2

■

>8.0mm clearance and creepage distance (option ‘T’ or ‘TS’)

■

1,414V Peak Working Insulation Voltage (V

Applications

■

Isolation of high speed logic systems Computer peripheral interfaces

■

Microprocessor system interfaces Ground loop elimination

■

Pulse transformer replacement Isolated bus driver

■

High speed line receiver

IORM

Description

The FOD2200 is an optically coupled logic gate that combine an AlGaAs LED and an integrated high gain photo detector. The detector has a three state output stage and has a detector threshold with hysteresis. The three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. The hysteresis provides differential mode noise immunity and eliminates the potential for output signal chatter.

The Electrical and Switching Characteristics of the FOD2200 are guaranteed over the temperature range of 0°C to 85°C and a V wide V

range allow compatibility with TTL, LSTTL, and

CC

CMOS logic and result in lower power consumption compared to other high speed opto-couplers. Logic

)

signals are transmitted with a maximum propagation delay of 300ns. The FOD2200 is useful for isolating high speed logic interfaces, buffering of input and output lines, and implementing isolated line receivers in high noise environments.

Truth Table

LED Enable Output

On H Z Off H Z On L H Off L L

range of 4.5V to 20V. Low I

CC

(Positive Logic)

and

F

Functional Block Diagram and Schematic Package Outlines

I

CC

NC

1

NC

2

3

4

SHIELD

ANODE

CATHODE

8

V

CC

I

V

7

O

6

V

E

5

GND

F

+

2

V

F

–

3

SHIELD

V

CC

8

I

O

V

O

7

I

E

V

E

6

GND

5

8

1

8

1

8

1

8

1

Safety and Insulation Ratings

As per IEC 60747-5-2. This optocoupler is suitable for “safe electrical insulation” only within the safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits.

Symbol Parameter Min. Typ. Max. Unit

Climatic Classiﬁcation 40/85/21 Pollution Degree (DIN VDE 0110/1.89) 2

CTI Comparative Tracking Index 175

V

PR

V

IORM

V

IOTM

External Creepage 8 mm External Clearance 7.4 mm

Insulation Thickness 0.5 mm

T

Case

I

S,INPUT

P

S,OUTPUT

R

IO

Installation Classiﬁcations per DIN VDE 0110/1.89 Table 1 For Rated Mains Voltage < 150Vrms I–IV For Rated Mains Voltage < 300Vrms I–IV For Rated Mains Voltage < 450Vrms I–III For Rated Mains Voltage < 600Vrms I–III For Rated Mains Voltage < 1000Vrms (Option T, TS) I–III

Input to Output Test Voltage, Method b, V

x 1.875 = V

IORM

, 100% Production Test with

PR

2651

tm = 1 sec., Partial Discharge < 5pC Input to Output Test Voltage, Method a,

V

IORM

x 1.5 = V

, Type and Sample Test with

PR

2121

tm = 60 sec.,Partial Discharge < 5 pC Max Working Insulation Voltage 1,414 V Highest Allowable Over Voltage 6000 V

External Clearance (for Option T or TS - 0.4” Lead Spacing) 10.16 mm

Safety Limit Values – Maximum Values Allowed in the Event of a Failure

Case Temperature 150 °C Input Current 10 mA Output Power (Duty Factor ≤ 2.7%) 150 mW Insulation Resistance at T

, V

= 500V 10

S

IO

9

Ω

FOD2200 — Low Input Current Logic Gate Optocouplers

peak

FOD2200 — Low Input Current Logic Gate Optocouplers

Absolute Maximum Ratings

(T

= 25°C unless otherwise speciﬁed)

A

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Value Units

T

STG

T

OPR

T

SOL

EMITTER

I

F (PK)

I

F

V P

DETECTOR

V

CC

I

O

V V P

Storage Temperature -40 to +125 °C Operating Temperature -40 to +85 °C Lead Solder Temperature (1.6mm below seating plane) 260 for 10 sec °C

Peak Transient Input Current ( ≤ 1µs PW, 300pps) 1.0 A Average Forward Input Current 10 mA Reverse Input Voltage 5.0 V

R

Output Power Dissipation (No derating required up to 85°C) 45 mW

D

Supply Voltage 0 to 20 V Average Output Current 25 mA Three State Enable Voltage -0.5 to 20 V

E

Output Voltage -0.5 to 20 V

O

Output Power Dissipation (No derating required up to 85°C) 150 mW

D

Recommended Operating Conditions

The Recommended Operating Conditions table deﬁnes the conditions for actual device operation. Recommended operating conditions are speciﬁed to ensure optimal performance to the datasheet speciﬁcations. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Min. Max. Units

I

F(ON)

I

F(OFF)

V

CC

V

EL

V

EH

T

A

NFan Out (TTL Load) 4

*The initial switching threshold is 1.6mA or less. It is recommended that 2.2mA be used to permit at least a 20% CTR degradation guardband.

Forward Input Current 1.6* 5 mA Forward Input Current 0.1 mA Supply Voltage, Output 4.5 20 V Enable Voltage, LOW Level 0 0.8 V Enable Voltage, HIGH Level 2.0 20 V Operating Temperature 0 +85 °C

∆

FOD2200 — Low Input Current Logic Gate Optocouplers

Electrical Characteristics

= 2V to 20V, V

V

EH

= 0V to 0.8V, I

EL

(T

= 0°C to +85°C, V

A

= 0 mA to 0.1mA unless otherwise speciﬁed.)

F(OFF)

= 4.5V to 20V, I

CC

= 1.6mA to 5mA,

F(ON)

(1)

Individual Component Characteristics

Symbol Parameter Test Conditions Min. Typ.* Max. Unit

EMITTER

V

B

C

VF/ ∆ TA Input Diode Temperature

DETECTOR

I

CCH

I

CCL

I I

V V

Input Forward Voltage I

F

Input Reverse Breakdown

VR

= 5mA 1.75 V

F

T

= 25°C 1.40 1.7

A

I

= 10µA 5.0 V

R

Voltage Input Capacitance Pins 2 & 3, V

IN

I

= 5mA -1.4 mV/°C

F

= 0, f = 1MHz 60 pF

F

Coefﬁcient

High Level Supply Current

Low Level Supply Current I

Low Level Enable Current V

EL

High Level Enable Current V

EH

High Level Enable Voltage 2.0 V

EH

Low Level Enable Voltage 0.8 V

EL

I

= 5mA, I

F

V

= Don’t Care

E

= 0, I

F

V

= Don’t care

E

= 0.4V -0.1 -0.32 mA

E

= 2.7V 20 µA

E

V

= 5.5V 100

E

= 20V 0.005 250

V

E

= Open,

O

= Open,

O

= 5.5V 3.5 4.5 mA

V

CC

V

= 20V 4.0 6.0

CC

= 5.5V 4.4 6.0 mA

V

CC

V

= 20V 5.2 7.5

CC

Switching Characteristics

(T

= 0°C to +85°C, I

A

= 1.6mA to 5mA, I

F(ON)

= 0 to 0.1mA, V

F(OFF)

= 4.5V to 20V

CC

unless otherwise speciﬁed.)

Symbol AC Characteristics Test Conditions Min. Typ.* Max. Unit

T

Propagation Delay Time

PLH

With Peaking Capacitor

to Output High Level

T

Propagation Delay Time

PHL

With Peaking Capacitor

to Output Low Level

(5)

(Fig. 1) 80 ns

(6)

(Fig. 1) 25 ns

(Fig. 2) 40 ns

t

r

t

PZH

Output Rise Time (10% to 90%) Output Fall Time (90% to 10%)

f

Enable Propagation Delay Time to Output High Level

t

PZL

Enable Propagation Delay Time

(Fig. 2) 50 ns

to Output Low Level

T

PHZ

Disable Propagation Delay Time from

(Fig. 2) 95 ns

Output High Level

T

Disable Propagation Delay Time from

PLZ

(Fig. 2) 80 ns

Output Low Level

| Common Mode Transient Immunity

|CM

H

(at Output High Level)

| Common Mode

|CM

L

Tr ansient Immunity (at Output Low Level)

*Typical values at T

= 25°C, V

A

= 5V, I

CC

F(ON)

TA =25°C,

(Min.) = 2.0V,

V

OH

V

CC

= 5V

(7)

(Fig. 3)

TA =25°C, IF = 0mA

(Max.) = 0.8 V,

V

OL

V

CC

= 5V

(8)

(Fig. 3)

= 3mA unless otherwise specified.

(2)(4)

(Fig. 1) 120 300 ns

(3)(4)

(Fig. 1) 180 300 ns

I

= 1.6mA,

F

| = 50V

|V

CM

= 5mA,

I

F

| = 1,000V

|V

CM

|V

| = 50V 1,000 V/µs

CM

| = 1,000V 10,000

|V

CM

1,000 V/µs

10,000

Electrical Characteristics (Continued)

FOD2200 — Low Input Current Logic Gate Optocouplers

Transfer Characteristics (T

V

= 0V to 0.8V, I

EL

= 0mA to 0.1mA unless otherwise speciﬁed.)

F(OFF)

= 0°C to +85°C, VCC = 4.5V to 20V, I

A

= 1.6mA to 5mA, VEH = 2V to 20V,

F(ON) (1)

Symbol DC Characteristics Test Conditions Min. Typ.* Max. Unit

I

OHH

V

I

V I

OZL

I

OZH

I

OSL

I

OSH

I

HYS

FT

OH

Output Leakage Current (V

> VCC)

OUT

Low Level Output Voltage VCC = 4.5 V, IF = 0mA, VE = 0.4 V,

OL

= 4.5V, IF = 5mA VO = 5.5V 2.0 100 µA

V

CC

V

= 20V 2.5 500

O

0.33 0.5 V

I

= 6.4mA

OL

(2)

Input Threshold Current VCC = 4.5V, VO = 0.5V, VE = 0.4V,

I

= 6.4mA

OL

Logic High Output Voltage IOH = -2.6mA 2.4 VCC – 1.8 V High Impedance State

VO = 0.4V, VEN = 2V, IF = 5mA -20 µA

Output Current High Impedance State

Output Current

Logic Low Short Circuit Output Current

Logic High Short Circuit Output Current

(10)

VO = 2.4 V, VEN = 2 V, IF = 5mA 20 µA V

= 5.5 V, VEN = 2 V, IF = 5mA 100

O

V

= 20 V, VEN = 2 V, IF = 5mA 500

O

VO = VCC = 5.5V, IF = 0mA 25 mA V

= VCC = 20V, IF = 0mA 40

O

VCC = 5.5V, IF = 5mA, VO = GND -10 mA V

= 20V, IF = 5mA, VO = GND -25

CC

Input Current Hysteresis VCC = 4.5V 0.03 mA

1.6 mA

Isolation Characteristics (T

= 0°C to +85°C unless otherwise speciﬁed)

A

Symbol Characteristics Test Conditions Min. Typ.* Max. Unit

V

R C

*Typical values at T

Withstand Insulation Test Voltage RH < 50%, TA = 25°C, t = 1 min.

ISO

Resistance (Input to Output) V

I-O

Capacitance (Input to Output) V

I-O

= 25°C, VCC = 5V, I

A

= 500 VDC

I-O

= 0V, f = 1MHz

I-O

= 3mA unless otherwise stated.

F(ON)

(9)

Notes:

1. The V

supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic

CC

or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V

2. t

– Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse

PLH

and GND pins of each device.

CC

to the 1.3V level on the LOW to HIGH transition of the output voltage pulse.

3. t

– Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse

PHL

to the 1.3V level on the HIGH to LOW transition of the output voltage pulse.

4. When the peaking capacitor is omitted, propagation delay times may increase by 100ns. – Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse.

5. t

r

– Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse.

6. t

f

7. CM

8. CM

– The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high

H

state (i.e., V

– The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low

L

state (i.e., V

OUT

> 2.0V).

< 0.8V).

9. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted together.

10. Duration of output short circuit time should not exceed 10ms.

(9)

5000 V

12

10

0.6 pF

RMS

Ω

Test Circuits

PULSE GEN.

t

=

= t

r

f

f = 100 kHz 10 % DUTY

CYCLE

= 5 V

V

O

INPUT MONITORING NODE

R

1

5 ns

I

F

C1 = 120 pF

1

2

3

4

FOD2200

V

GND

FOD2200 — Low Input Current Logic Gate Optocouplers

V

CC

OUTPUT V

O

MONITORING NODE

8

CC

7

6

5

C2 = 15 pF

D

5 kΩ

5 V

619 Ω

1

D

2

D

3

D

4

INPUT I

OUTPUT V

O

THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C

2.15 kΩ

R

I

1.6 mA

IF (ON)

ALL DIODES ARE 1N916 OR 1N3064.

F

t

PLHtPHL

1

1.10 kΩ

3 mA

AND

C

681 Ω

5 mA

Fig. 1. Test Circuit and Waveforms for t

CL= 15 pF INCLUDING PROBE AND JIG CAPACITANCES

=

5 ns

f

FOD2200

1

2

3

4

D

ARE 1N916 OR 1N3064.

1-4

V

GND

V

CC

8

CC

7

6

5

GENERATOR

Z

t

r

I

F

INPUT V

C

MONITORING NODE

PULSE

= 50 Ω

O

= t

.

2

I

F

50 % IF (ON)

0 mA

V

1.3 V

, t

PLH

.

V

O

C

L

(ON)

OH

V

OL

PHL, tr

D

5 kΩ

and t

f

+5 V

S1

619 Ω

1

D

2

D

3

D

4

S2

INPUT V

E

OUTPUT V

O

OUTPUT V

O

Fig. 2. Test Circuit and Waveforms for t

t

PZL

S1 CLOSED S2 OPEN

t

PZH

S1 OPEN S2 CLOSED

1.3 V

1.3 V 0 V

t

PLZ

0.5 V

t

PHZ

3.0 V

1.3 V

0 V S1 AND S2 CLOSED

V

S1 AND S2 CLOSED

, t

PHZ

OL

OH

PZH

≈1.5 V

, t

PLZ

, and t

PZL

Test Circuits (Continued)

R

IN

V

FF

PULSE GENERATOR

FOD2200 — Low Input Current Logic Gate Optocouplers

V

FOD2200

1

A

2

B

3

4

V

GND

V

CM

–+

CC

0.1 µF BYPASS

OUTPUT V

O

MONITORING NODE

8

CC

7

6

5

V

CM

OUTPUT V

O

Fig. 3. Test Circuit and Typical Waveforms for Common Mode Transient Immunity

V

(+5V)

DATA

INPUT

TOTEM

OUTPUT

CC1

POLE

GATE

1.1

kΩ

TTL OR LSTTL

1

120pF

FOD2200

1

2

3

4

V

GND

8

CC

7

6

5

2

Figure 4. Recommended LSTTL to LSTTL Circuit

0 V

SWITCH AT A: IF = 1.6mA

V

OH

SWITCH AT B: I

V

OL

* SEE NOTE 6.

50 V

VO (MIN.)*

VO (MAX.)*

V

CC2

(+5V)

DATA OUTPUT

UP TO 16 LSTTL LOADS OR 4 TTL LOADS

= 0mA

F

V

CC1

DATA

INPUT

OUTPUT

(+5V)

TOTEM

POLE

GATE

1

1.1

kΩ

TTL OR LSTTL

120pF (OPTIONAL*)

FOD2200

1

2

3

4

R

V

CC2

5V 10V 15V 20V

L

1.1kΩ

2.37kΩ

3.83kΩ

5.11kΩ

GND

Figure 5. LSTTL to CMOS Interface Circuit

V

CC2

(4.5V TO 20V)

V

CC

R

L

8

DATA

CMOS

7

6

5

2

OUTPUT

V

(+5 V)

V

CC1

DATA

INPUT

TTL OR

(+5 V)

LSTTL

1.1kΩ

D1

D1 (1N4150) REQUIRED FOR ACTIVE PULL-UP DRIVER.

FOD2200

V

1

2

3

4

CC

GND

Figure 6. Recommended LED Drive Circuit

CC

8

7

6

5

DATA

INPUT

OPEN

COLLECTOR

GATE

Figure 7. Series LED Drive with Open Collector Gate

(4.7kΩ Resistor Shunts IOH from the LED)

1.1 kΩ

4.7kΩ

TTL OR LSTTL

120pF (OPTIONAL*)

FOD2200

1

2

3

4

V

CC

GND

8

7

6

5

*The 120pF capacitor may be omitted in applications where 500ns propagation delay is sufficient.

Typical Performance Curves

FOD2200 — Low Input Current Logic Gate Optocouplers

Figure 8. Input Forward Current vs Forward Voltage

100

10

TA = 85°C

1

TA = 70°C

TA = 25°C

0.1

– FORWARD CURRENT (mA)

0.01

F

I

TA = -40°C

TA = 0°C

0.001

0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 VF – FORWARD VOLTAGE (V)

Figure 10. Input Threshold Current vs. Ambient Temperature

1.2 VCC = 5V, 20V

1.0

0.8

(ON)

I

0.6

F

0.4

0.2

INPUT CURRENT THRESHOLD (mA)

0.0

-40 -20 0 20 40 60 80 100 TA – Ambient Temperature (°C)

I

F

(OFF)

Figure 9. Output Voltage vs. Input Forward Current

5

V

= 4.5V

CC

T

= 25°C

A

4

3

IO = -2.6mA

2

– Output Voltage (V)

O

1

V

0

0.0 0.2 0.4 0.6 0.8 1.0 1.2

I

= 6.4mA

O

I

F(OFF)

I

F(ON)

IF – INPUT FORWARD CURRENT (mA)

Figure 11. Logic Low Output Voltage vs. Ambient Temperature

0.8 V

= 4.5V

CC

= 0 mA

I

F

0.7

= 6.4 mA

I

O

0.6

0.5

0.4

0.3

0.2

0.1

– LOGIC LOW OUTPUT VOLTAGE (V)

OL

0.0

V

-40 -20 0 20 40 60 80 100 T

– AMBIENT TEMPERATURE (°C)

A

Figure 12. Logic High Output Voltage vs. Supply Voltage

20

= -2.6 mA

I

O

= 25°C

T

A

I

≥ IF (ON)

F

16

12

8

4

– LOGIC HIGH OUTPUT VOLTAGE (V)

OH

V

0

048121620

VCC – SUPPLY VOLTAGE (V)

Figure 14. Propagation Delay vs Ambient Temperature

260

V

= 5V

CC

C1 (120pF) Peaking Capacitor Is Used. See Figure 1.

220

t

, IF = 5mA

180

t

140

– PROPAGATION DELAY (µs)

100

P

t

PHL

60

-40 -20 0 20 40 60 80 100

PHL

, I

= 3mA

F

t

, I

= 1.6mA

PHL

F

t

, IF = 1.6mA–5mA

PLH

TA – AMBIENT TEMPERATURE (°C)

Figure 13. Logic High Output Current vs. Ambient Temperature

0

-1

-2

-3

V

= 2.7V

O

-4 V

= 2.4V

-5

O

-6

– LOGIC HIGH OUTPUT CURRENT (mA)

-7

OH

I

-40 -20 0 20 40 60 80 100 TA – AMBIENT TEMPERATURE (°C)

VCC = 4.5V

= 5 mA

I

F

Figure 15. Rise, Fall Time vs Ambient Temperature

200

V

= 5V

CC

= 1.6mA

I

F

160

120

t

80

, tr – RISE, FALL TIME (µs)

f

40

t

0

-40 -20 0 20 40 60 80 100

r

t

f

T

– AMBIENT TEMPERATURE (°C)

A

Package Dimensions

FOD2200 — Low Input Current Logic Gate Optocouplers

Through Hole

PIN 1 ID.

241

0.270 (6.86)

0.250 (6.35)

8

0.070 (1.78)

0.045 (1.14)

0.020 (0.51)

0.154 (3.90)

0.120 (3.05)

MIN

0.016 (0.40)

0.008 (0.20)

0.156 (3.94)

0.144 (3.68)

15° MAX

0.300 (7.62) TYP

SEATING PLANE

0.022 (0.56)

0.016 (0.41)

0.200 (5.08) MAX

3

56 7

0.390 (9.91)

0.370 (9.40)

0.100 (2.54) TYP

Surface Mount – 0.3" Lead Spacing (Option S)

0.390 (9.91)

0.370 (9.40)

3214

PIN 1 ID.

0.270 (6.86)

0.250 (6.35)

0.4" Lead Spacing (Option T)

PIN 1

0.270 (6.86)

0.250 (6.35)

8

0.070 (1.78)

0.045 (1.14)

0.154 (3.90)

0.120 (3.05)

ID.

0.020 (0.51) MIN

0.016 (0.40)

0.008 (0.20)

0.156 (3.94)

0.144 (3.68)

0.400 (10.16)

0.200 (5.08) MAX

SEATING PLANE

0.022 (0.56)

0.016 (0.41)

0.031 (0.78)

3

241

56 7

0.390 (9.91)

0.370 (9.40)

0.100 (2.54) TYP

8-Pin Surface Mount DIP – Land Pattern (Option S)

0.070 (1.78)

0.060 (1.52)

0° to 15°

TYP

0.100 (2.54) TYP

8

0.070 (1.78)

0.045 (1.14)

0.022 (0.56)

0.016 (0.41)

0.020 (0.51) MIN

0.300 (7.62) TYP

0.015 (0.40) MIN Both Sides

0.315 (8.00) MIN

0.405 (10.30) MAX.

0.016 (0.40)

0.008 (0.20)

0.415 (10.54)

0.295 (7.49)

0.100 (2.54)

0.030 (0.76)

0.156 (3.94)

0.144 (3.68)

0.200 (5.08) MAX

567

Note:

All dimensions are in inches (millimeters)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

Package Dimensions (Continued)

FOD2200 — Low Input Current Logic Gate Optocouplers

Surface Mount – 0.4" Lead Spacing (Option TS)

0.390 (9.91)

0.156 (3.94)

0.144 (3.68)

0.200 (5.08) MAX

0.370 (9.40)

3214

567

0.100 (2.54) TYP

0.270 (6.86)

0.250 (6.35)

8

0.070 (1.78)

0.045 (1.14)

0.031 (0.775)

0.022 (0.56)

0.016 (0.41)

PIN 1 ID.

0.020 (0.51) MIN

0.300 (7.62) TYP

0.015 (0.40) MIN Both Sides

0.400 (10.16)

0.497 (12.6) MAX.

8-Pin Surface Mount DIP – Land Pattern (Option TS)

0.070 (1.78)

0.100 (2.54)

0.016 (0.40)

0.008 (0.20)

0.392 (9.96)

0.511 (13.0)

0.060 (1.52)

0.030 (0.76)

Note:

All dimensions are in inches (millimeters)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

Ordering Information

Part Number Package Packing Method

FOD2200 DIP 8-Pin Tube (50 units per tube) FOD2200S SMT 8-Pin (Lead Bend) Tube (50 units per tube) FOD2200SD SMT 8-Pin (Lead Bend) Tape and Reel (1,000 units per reel) FOD2200V DIP 8-Pin, IEC60747-5-2 option Tube (50 units per tube) FOD2200SV SMT 8-Pin (Lead Bend), IEC60747-5-2 option Tube (50 units per tube) FOD2200SDV SMT 8-Pin (Lead Bend), IEC60747-5-2 option Tape and Reel (1,000 units per reel) FOD2200TV DIP 8-Pin, 0.4” Lead Spacing, IEC60747-5-2 option Tube (50 units per tube) FOD2200TSV SMT 8-Pin, 0.4” Lead Spacing, IEC60747-5-2 option Tube (50 units per tube) FOD2200TSR2V SMT 8-Pin, 0.4” Lead Spacing, IEC60747-5-2 option Tape and Reel (700 units per reel)

Marking Information

1

FOD2200 — Low Input Current Logic Gate Optocouplers

2

6

XX

43

2200

BYYV

5

Deﬁnitions

1Fairchild logo 2Device number 3 IEC60747-5-2 Option (only appears on component ordered

with this option) (Pending approval) 4Two digit year code, e.g., ‘08’ 5Two digit work week ranging from ‘01’ to ‘53’ 6 Assembly package code

Carrier Tape Specifications (Option SD)

K

0

t

FOD2200 — Low Input Current Logic Gate Optocouplers

D

0

P

0

P

2

E

F

D

1

W

1

User Direction of Feed

d

A

0

B

0

P

Symbol Description Dimension in mm

WTape Width 16.0 ± 0.3

tTape Thickness 0.30 ± 0.05

P

0

D

0

E Sprocket Hole Location 1.75 ± 0.10

FPocket Location 7.5 ± 0.1

P

2

PPocket Pitch 12.0 ± 0.1

A

0

B

0

K

0

W

1

dCover Tape Thickness 0.1 max

R Min. Bending Radius 30

Sprocket Hole Pitch 4.0 ± 0.1 Sprocket Hole Diameter 1.55 ± 0.05

2.0 ± 0.1

Pocket Dimensions 10.30 ±0.20

10.30 ±0.20

4.90 ±0.20

Cover Tape Width 13.2 ± 0.2

Max. Component Rotation or Tilt 10°

W

Carrier Tape Specifications (Option TSR2V)

K

0

t

FOD2200 — Low Input Current Logic Gate Optocouplers

D

0

P

0

P

2

E

F

D

1

W

1

User Direction of Feed

d

A

0

B

0

P

Symbol Description Dimension in mm

WTape Width 24.0 ± 0.3

tTape Thickness 0.40 ± 0.1

P

0

D

0

E Sprocket Hole Location 1.75 ± 0.10

FPocket Location 11.5 ± 0.1

P

2

PPocket Pitch 16.0 ± 0.1

A

0

B

0

K

0

W

1

dCover Tape Thickness 0.1 max

R Min. Bending Radius 30

Sprocket Hole Pitch 4.0 ± 0.1 Sprocket Hole Diameter 1.55 ± 0.05

2.0 ± 0.1

Pocket Dimensions 12.80 ± 0.1

10.35 ± 0.1

5.7 ±0.1

Cover Tape Width 21.0 ± 0.1

Max. Component Rotation or Tilt 10°

W

Reﬂow Proﬁle

FOD2200 — Low Input Current Logic Gate Optocouplers

Max. Ramp-up Rate = 3°C/S

Max. Ramp-down Rate = 6°C/S

Ts ma x

Preheat Area

Ts mi n

t

L

t

s

260 240 220 200 180 160 140 120

T

P

T

L

100

80 60

Temperature (°C)

40 20

0

120

240 360

Time 25°C to Peak

Time (seconds)

Proﬁle Freature Pb-Free Assembly Proﬁle

Temperature Min. (Tsmin) 150°C Temperature Max. (Tsmax) 200°C Time (t Ramp-up Rate (t Liquidous Temperature (T Time (t Peak Body Package Temperature 260°C +0°C / –5°C Time (t Ramp-down Rate (T Time 25°C to Peak Temperature 8 minutes max.

) from (Tsmin to Tsmax) 60–120 seconds

S

to tP) 3°C/second max.

L

) 217°C

L

) Maintained Above (TL) 60–150 seconds

L

) within 5°C of 260°C 30 seconds

P

to TL) 6°C/second max.

P

t

P

TRADEMARKS

®

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries,andisnot intended to be an exhaustive list of all such trademarks.

AccuPower™ Auto-SPM™ Build it Now™ CorePLUS™ CorePOWER™

CROSSVOLT™

CTL™ Current Transfer Logic™ DEUXPEED Dual Cool™ EcoSPARK EfficientMax™

®

n

ESBC™

®

Fairchild Fairchild Semiconductor FACT Quiet Series™

®

FACT

®

FAST FastvCore™ FETBench™ FlashWriter

®

*

FPS™

F-PFS™

®

FRFET Global Power Resource

SM

Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™

®

MotionMax™ Motion-SPM™ OptoHiT™ OPTOLOGIC OPTOPLANAR

®

PDP SPM™

Power-SPM™ PowerTrench PowerXS™ Programmable Active Droop™ QFET

®

QS™ Quiet Series™ RapidConfigure™

™

Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™

®

SPM STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS SyncFET™ Sync-Lock™

®

* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

The Power Franchise

TinyBoost™ TinyBuck™ TinyCalc™ TinyLogic TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TriFault Detect™ TRUECURRENT™* " SerDes™

UHC Ultra FRFET™ UniFET™ VCX™ VisualMax™ XS™

®

*

®

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

ANTI-C OUNTERFEITING POLICY

Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on ourexternal website, www.fairchildsemi.com, under Sales Support.

Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance,failed applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customersfromthe proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized FairchildDistributors are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Product Status Definition

Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

Rev. I49

FOD2200 — Low Input Current Logic Gate Optocouplers