C-UL, UL and VDE approved
High input-output isolation voltage of 5000Vrms
■
Minimum BV
■
■
Higher operating temperatures (versus H11AXXX
of 70V guaranteed
CEO
counterparts)
Applications
FOD814 Series
■
AC line monitor
Unknown polarity DC sensor
■
Telephone line interface
■
FOD817 Series
Power supply regulators
■
■
Digital logic inputs
Microprocessor inputs
■
Description
The FOD814 consists of two gallium arsenide infrared
emitting diodes, connected in inverse parallel, driving a
silicon phototransistor output in a 4-pin dual in-line
package. The FOD817 Series consists of a gallium
arsenide infrared emitting diode driving a silicon
phototransistor in a 4-pin dual in-line package.
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
ValueUnits
SymbolParameter
TOTAL DEVICE
T
STG
T
OPR
T
SOL
T
J
θ
JC
P
TOT
EMITTER
I
F
V
R
P
D
DETECTOR
V
CEO
V
ECO
I
C
P
C
Storage Temperature-55 to +150°C
Operating Temperature-55 to +105-55 to +110°C
Lead Solder Temperature260 for 10 sec°C
Junction Temperature125 Max.°C
Junction-to-Case Thermal Resistance210°C/W
Total Power Dissipation200mW
Continuous Forward Current±5050mA
Reverse Voltage6
Power Dissipation
Derate above 100°C
Collector-Emitter Voltage70V
Emitter-Collector Voltage6V
Continuous Collector Current50mA
Collector Power Dissipation
Derate above 90°C
FOD814FOD817
70
1.7
150
2.9
mW
mW/°C
mW
mW/°C
FOD814 Series, FOD817 Series — 4-Pin High Operating Temperature Phototransistor Optocouplers
FOD814 Series, FOD817 Series — 4-Pin High Operating Temperature Phototransistor Optocouplers
Package Dimensions
Through Hole
E
N
LA
P
G
IN
T
A
E
S
0.130 (3.30)
0.091 (2.30)
0.150 (3.80)
0.110 (2.80)
0.110 (2.79)
0.090 (2.29)
0.4" Lead Spacing
0.200 (5.10)
0.161 (4.10)
LANE
P
NG
I
T
EA
S
0.200 (5.10)
0.161 (4.10)
0.130 (3.30)
0.091 (2.30)
0.157 (4.00)
0.118 (3.00)
0.020 (0.51)
TYP
0.024 (0.60)
0.016 (0.40)
0.157 (4.00)
0.118 (3.00)
Surface Mount
0.312 (7.92)
0.288 (7.32)
0.276 (7.00)
0.236 (6.00)
0.010 (0.26)
0.393 (9.98)
0.300 (7.62)
0.200 (5.10)
E
0.161 (4.10)
N
G PLA
ATIN
SE
0.051 (1.30)
0.043 (1.10)
0.110 (2.79)
0.090 (2.29)
Lead Coplanarity 0.004 (0.10) MAX
0.157 (4.00)
0.118 (3.00)
0.024 (0.60)
0.004 (0.10)
0.312 (7.92)
0.288 (7.32)
0.276 (7.00)
0.236 (6.00)
0.049 (1.25)
0.030 (0.76)
0.412 (10.46)
0.388 (9.86)
0.010 (0.26)
Surface Mount (Footprint Dimensions)
1.5
1.3
0.312 (7.92)
0.288 (7.32)
0.276 (7.00)
0.236 (6.00)
9
0.291 (7.40)
0.252 (6.40)
0.150 (3.80)
0.110 (2.80)
0.024 (0.60)
0.016 (0.40)
0.110 (2.79)
0.090 (2.29)
0.110 (2.80)
0.011 (1.80)
0.42 (10.66)
0.38 (9.66)
0.010 (0.26)
2.54
Note:
All dimensions are in inches (millimeters)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: