Datasheet FOD8012 Datasheet (Fairchild)

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

November 2010

FOD8012 High CMR, Bi-Directional, Logic Gate Optocoupler

Features

■

Full Duplex, Bi-Directional

20kV/µs Minimum Common Mode Rejection

■

High Speed:

– 15Mbit/sec Data Rate (NRZ) – 60ns max. Propagation Delay , and opti– 15ns max. Pulse Width Distortion – 30ns max. Propagation Delay Skew

3.3V and 5V CMOS Compatibility

■

Extended industrial temperate range, -40 to +110˚C temperature range

■

Safety and regulatory approvals

– UL1577, 3750 VAC – DIN EN/IEC60747-5-2 (approval pending)

RMS

for 1 min.

Applications

■

Industrial ﬁeldbus communications

– DeviceNet, CAN, RS485, RS232

■

Microprocessor System Interface

2

– SPI, I

■

Programmable Logic Control

Isolated Data Acquisition System

■

Voltage Level Translator

C

Description

The FOD8012 is a full duplex, bi-directional, high-speed logic gate Optocoupler, which supports isolated communications allowing digital signals to communicate between systems without conducting ground loops or hazardous voltages. It utilizes Fairchild’s proprietary co-

planar packaging technology, Optoplanar

IC design to achieve minimum 20kV/µs Common Mode Noise Rejection (CMR) rating.

This high-speed logic gate optocoupler is highly integrated with 2 optically coupled channels arranged in bi-directional configuration, and housed in a compact 8-pin small outline package. Each optocoupler channel consists of a high-speed AlGaAs LED driven by a CMOS buffer IC coupled to a CMOS detector IC. The detector IC comprises of an integrated photodiode, a high-speed trans-impedance amplifier and a voltage comparator with an output driver. The CMOS technology coupled to the high efficiency of the LED achieves low power consumption as well as very high speed (60ns propagation delay, 15ns pulse width distortion).

®

Related Resources

■

FOD8001, High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Datasheet

■

www.fairchildsemi.com/products/opto/

Functional Schematic

1

V

DD1

V

2

OA

V

3

INB

GND

45

1

0.1µF bypass capacitor required from V

8

7

6

V

DD2

V

INA

V

OB

GND

to GND

DD

Truth Table

VIN LED VO

High OFF

Low ON

2

High

Low

Pin Definitions

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

Number

1V 2V 3V 4 GND 5 GND 6V 7V 8V

Absolute Maximum Ratings

Name Description

DD1

OA

INB

OB INA

DD2

Supply V oltage to Channel-A detector IC and Channel-B buffer IC Output V oltage from Channel-A detector IC Input V oltage to Channel-B buffer IC Ground for Channel-A detector IC and Channel-B buffer IC

1

Ground for Channel-A buffer IC and Channel-B detector IC

2

Output V oltage from Channel-B detector IC Input V oltage to Channel-A buffer IC Supply V oltage to Channel-A buffer IC and Channel-B detector IC

(T

=25ºC unless otherwise specified)

A

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Value Units

V

DD1

V

I

T

I

OA

OPR

T

IA

PD

STG

J

SOL

, V

, I

, V

, I

DD2

IB

OB

I

O

Storage Temperature -40 to +125 ºC

Operating Temperature -40 to +110 ºC

Junction Temperature -40 to +130 ºC

Lead Solder Temperature

260 for 10sec ºC

(Refer to Reﬂow Temperature Proﬁle)

Supply Voltage 0 to 6.0 V

Input Voltage -0.5 to VDD+0.5 V

Input DC Current -10 to +10 µA

Output Voltage -0.5 to VDD+0.5 V

Average Output Current 10 mA

Input Power Dissipation

Output Power Dissipation

(1)

60 mW

Recommended Operating Conditions

The Recommended Operating Conditions table deﬁnes the conditions for actual device operation. Recommended operating conditions are speciﬁed to ensure optimal performance to the datasheet speciﬁcations. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

T

A

V

, V

DD1

V

IH

V

IL

t

, t

r

f

Ambient Operating Temperature Supply Voltages (3.3V Operation)

DD2

Supply Voltages (5.0V Operation) Logic High Input Voltage

Logic Low Input Voltage Input Signal Rise and Fall Time

(2) (2)

-40 +110 ºC

3.0 3.6 V

4.5 5.5 V

2.0

V

DD

0 0.8 V

1.0 ms

V

Isolation Characteristics

Apply over all recommended conditions, typical value is measured at T

Symbol Parameter Conditions Min. Typ. Max. Units

= 25ºC

A

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

V

ISO

R

ISO

C

ISO

Input-Output Isolation Voltage freq = 60Hz, t = 1.0min,

I

I-O

Isolation Resistance V

Isolation Capacitance V

I-O

(3)(4)

≤

10µA

= 500V

(3)

= 0V, freq = 1.0MHz

3750 Vac

11

10

(3)

0.2 pF

Electrical Characteristics

T

= -40ºC to +110ºC, 3.0V

A

Apply over all recommended conditions, typical value is measured at V

Symbol Parameter Conditions Min. Typ. Max. Units

I

DD1L

I

DD1H

, I

DD2L

, I

DD2H

I

, I

IA

IB

V

OH

V

OL

Logic Low Supply Current V Logic High Supply Current V Input Current Logic High Output Voltage I

Logic Low Output Voltage I

≤

V

≤

5.5V, unless otherwise specified.

DD

, V

= 0V

IA

IB

, V

= V

IA

IB

DD

DD1

= V

= +3.3V, T

DD2

= 25ºC

A

5.8 8.0 mA

2.5 4.0 mA

-10 +10 µA

= –20µA, V

O

I

= –4mA, V

O

I

= –20µA, V

O

I

= –4mA, V

O

= 20µA, V

O

V

= V

I

= 4mA, VDD = 3.3V or 5V,

I

O

V

= V

I

DD

= 3.3V, V

DD

= 3.3V, V

DD

= 5V, V

DD

= 3.3V or 5V,

DD

IL

= V

I

= V

I

= V

I

= V

I

3.2 3.3 V

IH

3.0 3.1 V

IH

4.9 5.0 V

4.7 4.8 V

0 0.1 V

0.26 0.6 V

IL

RMS

Ω

Switching Characteristics

T

= -40ºC to +110ºC, 3.0V ≤ VDD ≤ 5.5V, unless otherwise specified.

A

Apply over all recommended conditions, typical value is measured at V

Symbol Parameter Conditions Min. Typ. Max. Units

Data Rate 15 Mbit/s

DD1

= V

= +3.3V, TA=25ºC

DD2

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

t

PHL

Propagation Delay Time

PW = 66.7ns, CL = 15pF 37 60 ns

to Logic Low Output

t

PLH

Propagation Delay Time

PW = 66.7ns, CL = 15pF 40 60 ns

to Logic High Output

PWD Pulse Width Distortion,

| t

– t

PLH

|

t

PSK(CC)

t

PSK(PP)

t

R

PHL

Channel-Channel Skew PW = 66.7ns, CL = 15pF

Part-Part Skew PW = 66.7ns, CL = 15pF

Output Rise Time

PW = 66.7ns, C

= 15pF

L

PW = 66.7ns, CL = 15pF 6.5 ns

(5)

(6)

(7)

315ns

12 25 ns

30 ns

(10% to 90%)

t

F

Output Fall Time

PW = 66.7ns, CL = 15pF 6.5 ns

(90% to 10%)

| Common Mode Transient

|CM

H

Immunity at Output High

| Common Mode Transient

|CM

L

Immunity at Output Low

VI = V V

CM

VI = 0V, VO < 0.8V, V

CM

, VO > 0.8V

DD1

= 1000V

(8)

DD1

,

20 40 kV/µs

Notes:

1. No derating required.

2. 0.1µF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. The capacitors should be kept close to the supply pins.

3. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.

4. 3,750 VAC

for 1 minute duration is equivalent to 4,500 VAC

RMS

5. PWD is equal to the magnitude of the worst case difference in t

for 1 second duration.

RMS

PHL

and/or t

that will be seen for one channel

PLH

switching, while holding the other channel output at a low or high state, or while both channels are in synchronous data transmission mode.

6. t

is equal to the magnitude of the worst case difference in t

PSK(CC)

PHL

and/or t

that will be seen between the two

PLH

channels within a single device.

7. t

is equal to the magnitude of the worst case difference in t

PSK(PP)

PHL

and/or t

that will be seen between any two

PLH

units from the same manufacturing date code that are operated at same case temperature, at same operating conditions, with equal loads.

8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to assure that the output will remain low.

Typical Performance Curves

Fig. 1 Typical Output Voltage vs. Input Voltage

4.0

V

= V

DD1

= 3.3V

(Channel A & B)

Fig. 2 Typical Input Voltage Switching Threshold

vs. Input Supply Voltage (Channel A & B)

2.0

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

3.0

2.0

OUTPUT VOLTAGE (V)

–

1.0

O

V

0

0123 45

VI –

INPUT VOLTAGE (V)

Fig. 3 Typical Propagation Delay vs.

Ambient Temperature (Channel A & B)

54

Frequency = 7.5MHz Duty Cycle = 50% V

= V

DD2

= 3.3V

t

PLH

t

PHL

DD1

50

46

42

38

– PROPAGATION DELAY (ns)

P

t

34

1.8

1.6

1.4

THRESHOLD (V)

INPUT VOLTAGE SWITCHING

–

1.2

ITH

V

1.0

3.0 3.5 4.0 4.5 5.0 5.5

VDD –

SUPPLY VOLTAGE (V)

Fig. 4 Typical t

PHL

– t

vs. Ambient Temperature

PLH

(Channel A & B)

2

Frequency = 7.5MHz Duty Cycle = 50%

1

V

= V

DD2

= 3.3V

(ns)

PLH

– t

PHL

t

DD1

0

-1

-2

-3

-4

-5

30

-40 -20 0 20 40 60 80 100 110

TA –

AMBIENT TEMPERATURE (°C)

Fig. 5 Typical Rise Time vs. Ambient Temperature

7.0

Frequency = 7.5MHz Duty Cycle = 50% V

= V

DD1

6.5

6.0

5.5

– RISE TIME (ns)

5.0

R

t

4.5

4.0

-40 -20 0 20 40 60 80 100 110

(Channel A & B)

= 3.3V

DD2

t

R

TA –

AMBIENT TEMPERATURE (°C)

-6

-40 -20 0 20 40 60 80 100 110

TA –

AMBIENT TEMPERATURE (°C)

Fig. 6 Typical Fall Time vs. Ambient Temperature

9.0

Frequency = 7.5MHz Duty Cycle = 50%

8.5

V

= V

DD1

8.0

7.5

7.0

6.5

– FALL TIME (ns)

F

t

6.0

5.5

5.0

-40 -20 0 20 40 60 80 100 110

(Channel A & B)

= 3.3V

DD2

t

F

TA –

AMBIENT TEMPERATURE (°C)

Typical Performance Curves (Continued)

Fig. 7 Typical Propagation Delay vs. Output Load

45

43

41

39

– PROPAGATION DELAY (ns)

37

P

t

Capacitance (Channel A & B)

Frequency = 7.5MHz Duty Cycle = 50% V

= V

DD2

= 3.3V

t

PLH

DD1

t

PHL

Fig. 8 Typical t

0

Frequency = 7.5MHz Duty Cycle = 50% V

= V

DD1

-1

-2

(ns)

PLH

– t

-3

PHL

t

-4

DD2

PHL

= 3.3V

– t

vs. Output Load Capacitance

PLH

(Channel A & B)

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

35

15 20 25 30 35 40 45 50 55

CL – OUTPUT LOAD CAPACITANCE (pF)

Fig. 9 Typical Rise Time vs. Output Load Capacitance

DD2

= 3.3V

(Channel A & B)

t

R

12

Frequency = 7.5MHz Duty Cycle = 50% V

= V

DD1

10

8

6

– RISE TIME (ns)

R

t

4

2

15 20 25 30 35 40 45 50 55

CL – OUTPUT LOAD CAPACITANCE (pF)

-5 15 20 25 30 35 40 45 50 55

CL – OUTPUT LOAD CAPACITANCE (pF)

Fig. 10 Typical Fall Time vs. Output Load Capacitance

DD2

= 3.3V

(Channel A & B)

t

F

16

Frequency = 7.5MHz Duty Cycle = 50% V

= V

DD1

14

12

10

– FALL TIME (ns)

F

8

t

6

4

15 20 25 30 35 40 45 50 55

CL – OUTPUT LOAD CAPACITANCE (pF)

Typical Performance Curves (Continued)

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

Fig. 11a Typical I

7.5

V

DD1

V

INA

Pin 2 and 6 Floating

7.0

6.5

6.0

5.5

5.0

– INPUT SUPPLY CURRENT (mA)

DD2

/ I

4.5

DD1

I

4.0 0 2,000 4,000 6,000 8,000 10,000 12,000 14,000

= V

and V

DD2

INB

TA = 25°C

DD1/IDD2

= 5.5V, TA = 25°C

Switching

Supply Current vs. Frequency

TA = 110°C

F –

FREQUENCY (kHz)

TA = -40°C

Fig. 11c Typical I

7.5

V

= V

DD1

V

= 0V @ I

INA

V

= 0V @ I

7.0

INB

Pin 2 and 6 Floating

6.5

DD1/IDD2

= 5.5V, TA = 25°C

DD2

, V

DD1

INB

, V

DD2

INA

Fig. 11b Typical I

7.5

V

= V

DD1

DD2

V

= 0V @ I

INB

V

= 0V @ I

7.0

INA

Pin 2 and 6 Floating

6.5

6.0

5.5

TA = -40°C

5.0

– INPUT SUPPLY CURRENT (mA)

DD2

/ I

4.5

DD1

I

4.0 0 2,000 4,000 6,000 8,000 10,000 12,000 14,000

Supply Current vs. Frequency

Switching Switching

DD1/IDD2

= 5.5V, TA = 25°C

DD1

DD2

Supply Current vs. Frequency

, V

Switching

INA

, V

Switching

INB

TA = 110°C

F –

FREQUENCY (kHz)

TA = 25°C

6.0

TA = -40°C

5.5

5.0

– INPUT SUPPLY CURRENT (mA)

DD2

/ I

4.5

DD1

I

4.0 0 2,000 4,000 6,000 8,000 10,000 12,000 14,000

F –

TA = 25°C

TA = 110°C

FREQUENCY (kHz)

Test Circuits

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

1

V

OA

0.1µF

V

DD1

2

C

L

3

4 5

t

PLH

t

PHL

Input

V

IN

V

OUT

90% 10%

t

R

Output

8

7

6

t

F

0.1µF

V

3.3V 50%

V

OH

50%

V

OB

OL

0V~3.3V

V

DD2

Figure 11. Test Circuit for Propogation Delay Time and Rise Time, Fall Time

V

DD1

0.1µF

1

V

OA

2

C

L

3

4 5

+–

Vcm Pulse Gen

8

7

0.1µF

6

A

B

V

CM

GND

V

OH

Switching Pos. (A), V

0.8 x V

DD

IN

= 3.3V

CM

H

0.8V

V

OL

Switching Pos. (B), V

IN

= 0V

CM

L

Figure 12. Test Circuit for Instantaneous Common Mode Rejection Voltage

V

DD2

Small Outline Package Dimensions

0.202 (5.13)

0.182 (4.63)

SEATING PLANE

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

0.164 (4.16)

0.144 (3.66)

0.143 (3.63)

0.123 (3.13)

0.021 (0.53)

0.011 (0.28)

0.275 (6.99)

0.008 (0.20)

0.003 (0.08)

0.050 (1.27) TYP

Lead Coplanarity : 0.004 (0.10) MAX

0.024 (0.61)

0.060 (1.52)

0.155 (3.94)

0.050 (1.27)

0.010 (0.25)

0.006 (0.16)

0.244 (6.19)

0.224 (5.69)

Note:

All dimensions are in millimeters.

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

Carrier Tape Specification

3.50 ± 0.20

0.30 MAX

8.3 ± 0.10

4.0 ± 0.10

8.0 ± 0.10

2.0 ± 0.05

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

Ø1.5 MIN

1.75 ± 0.10

5.5 ± 0.05

12.0 ± 0.3

5.20 ± 0.20

0.1 MAX User Direction of Feed

6.40 ± 0.20

Ø1.5 ± 0.1/-0

Note: All dimensions are in millimeters.

Ordering Information

Option Order Entry Identiﬁer Description

No Sufﬁx FOD8012 Small outline 8-pin, shipped in tubes (50 units per tube)

R2 FOD8012R2 Small outline 8-pin, tape and reel (2,500 units per reel)

All packages are lead free per JEDEC: J-STD-020B standard.

Marking Information

1

8012

S1YYX

2

5

3

4

Deﬁnitions

1

Fairchild logo

2

Device number

3

One digit year code, e.g., ‘8’

4

Two digit work week ranging from ‘01’ to ‘53’

5

Assembly package code

Reﬂow Proﬁle

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler

260 245

240

220

200

Max. Ramp-up Rate = 3°C/S

Max. Ramp-down Rate = 6°C/S

T

P

T

L

Ts ma x

180

160

Ts mi n

140

120

100

80

Temperature (°C)

60

40

20

0

120

Time 25°C to Peak

t

s

240 360

Time (seconds)

t

P

t

L

Proﬁle Freature Pb-Free Assembly Proﬁle

Temperature Min. (Tsmin) 150°C Temperature Max. (Tsmax) 200°C Time (t Ramp-up Rate (t Liquidous T emper ature (T Time (t Peak Body Package Temperature 245°C +0°C / –5°C Time (t Ramp-down Rate (T Time 25°C to Peak Temperature 8 minutes max.

) from (Tsmin to Tsmax) 60–120 seconds

S

to tP) 3°C/second max.

L

) 217°C

L

) Maintained Above (TL) 60–150 seconds

L

) within 5°C of 245°C 30 seconds

P

to TL) 6°C/second max.

P

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®

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FACT

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FAST FastvCore™ FETBench™ FlashWriter

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SM

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Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ SPM STEALTH™ SuperFET™

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* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

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PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Product Status Definition

Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

Rev. I49

FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler