Intel MAX 10 JTAG User Manual
Intel® MAX® 10 JTAG Boundary-Scan
Testing User Guide
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Contents
Contents
1. Intel® MAX® 10 JTAG BST Overview................................................................................3
2. JTAG BST Architecture.................................................................................................... 4
2.1. JTAG Pins............................................................................................................. 4
2.2. JTAG Circuitry Functional Model...............................................................................4
2.3. JTAG Boundary-Scan Register..................................................................................5
2.3.1. Boundary-Scan Cells in Intel MAX 10 I/O Pin................................................. 5
3. BST Operation Control.................................................................................................... 7
3.1. JTAG IDCODE .......................................................................................................7
3.2. JTAG Secure Mode................................................................................................. 8
3.3. JTAG Private Instruction......................................................................................... 8
3.4. JTAG Instructions.................................................................................................. 9
4. I/O Voltage Support in the JTAG Chain......................................................................... 10
5. Enabling and Disabling JTAG BST Circuitry....................................................................11
6. Guidelines for JTAG BST................................................................................................ 12
7. Boundary-Scan Description Language Support............................................................. 13
A. Document Revision History for the Intel MAX 10 JTAG Boundary-Scan Testing
User Guide............................................................................................................... 14
Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide
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1. Intel® MAX® 10 JTAG BST Overview
Intel® MAX® 10 devices support the IEEE Std.1149.1 (JTAG) boundary-scan testing
(BST).
When you perform BST, you can test pin connections without using physical test
probes and capture functional data during normal operation. The boundary-scan cells
(BSCs) in a device can force signals onto pins, or capture data from pins or core logic
signals. Forced test data is serially shifted in from the TDI pin to the BSCs. Captured
data is serially shifted out to the TDO pin for external comparison with expected
results.
Note: You can perform BST on Intel MAX 10 devices before, after, and during configuration.
Related Information
• Intel MAX 10 FPGA Configuration User Guide
Provides more information about JTAG in-system programming.
• IEEE 1149.1 JTAG Boundary-Scan Testing in Altera Devices
Provides more information on IEEE 1149.1 JTAG boundary-scan testing.
• JTAG BST Architecture on page 4
• JTAG Boundary-Scan Register on page 5
• BST Operation Control on page 7
• I/O Voltage Support in the JTAG Chain on page 10
• Enabling and Disabling JTAG BST Circuitry on page 11
• Guidelines for JTAG BST on page 12
• Boundary-Scan Description Language Support on page 13
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
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2. JTAG BST Architecture
Intel MAX 10 JTAG interface uses four pins, TDI, TDO, TMS, and TCK.
2.1. JTAG Pins
Table 1. JTAG Pin Descriptions
Pin Function Description
TDI
TDO
TMS
TCK
Serial input pin for:
• Instructions
• Test data
• Programming data
Serial output pin for:
• Instructions
• Test data
• Programming data
Input pin that provides the control signal to
determine the transitions of the TAP
controller state machine.
The clock input to the BST circuitry. —
•
TDI is sampled on the rising edge of TCK
•
TDI pins have internal weak pull-up resistors.
•
TDO is sampled on the falling edge of TCK
• The pin is tri-stated if data is not being shifted out of the
device.
•
TMS is sampled on the rising edge of TCK
•
TMS pins have internal weak pull-up resistors.
All the JTAG pins are powered by the V
of I/O bank 1B. In JTAG mode, the I/O pins
CCIO
support the LVTTL/LVCMOS 3.3-1.5V standards.
2.2. JTAG Circuitry Functional Model
The JTAG BST circuitry requires the following registers:
• Instruction register—determines which action to perform and which data register
to access.
• Bypass register (1-bit long data register)—provides a minimum-length serial path
between the TDI and TDO pins.
• Boundary-scan register—shift register composed of all the BSCs of the device.
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
a
UPDATEIR
CLOCKIR
SHIFTIR
UPDATEDR
CLOCKDR
SHIFTDR
TDI
Instruction Register
Bypass Register
Boundary-Scan Register
Instruction Decode
TMS
TCK
TAP
Controller
ISP Registers
TDO
Data Registers
Device ID Register
2. JTAG BST Architecture
UG-M10JTAG | 2019.05.10
Figure 1. JTAG Circuitry Functional Model
• Test access port (TAP) controller—controls the JTAG BST.
•
TMS and TCK pins—operate the TAP controller.
•
TDI and TDO pins—provide the serial path for the data registers.
•
The TDI pin also provides data to the instruction register to generate the control logic for the data
registers.
2.3. JTAG Boundary-Scan Register
You can use the boundary-scan register to test external pin connections or to capture
internal data. The boundary-scan register is a large serial shift register that uses the
TDI pin as an input and the TDO pin as an output. The boundary-scan register consists
2.3.1. Boundary-Scan Cells in Intel MAX 10 I/O Pin
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of 3-bit peripheral elements that are associated with Intel MAX 10 I/O pins.
The Intel MAX 10 3-bit BSC contains the following registers:
•
Capture registers—connect to internal device data through OUTJ, OEJ, and
PIN_IN signals.
•
Update registers—connect to external data through PIN_OUT and PIN_OE signals.
Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide
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