Intel MAX 10 FPGA User Manual

Intel® MAX® 10 FPGA Configuration
User Guide

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Contents

Contents

1. Intel® MAX® 10 FPGA Configuration Overview................................................................ 4

2. Intel MAX 10 FPGA Configuration Schemes and Features...............................................5

2.1. Configuration Schemes..........................................................................................5

2.1.1. JTAG Configuration.................................................................................... 5

2.1.2. Internal Configuration................................................................................ 6

2.2. Configuration Features.........................................................................................13

2.2.1. Remote System Upgrade...........................................................................13

2.2.2. Configuration Design Security....................................................................20

2.2.3. SEU Mitigation and Configuration Error Detection........................................ 24

2.2.4. Configuration Data Compression................................................................ 27

2.3. Configuration Details............................................................................................ 28

2.3.1. Configuration Sequence............................................................................ 28

2.3.2. Intel MAX 10 Configuration Pins................................................................. 31

3. Intel MAX 10 FPGA Configuration Design Guidelines.....................................................32

3.1. Dual-Purpose Configuration Pins............................................................................ 32

3.1.1. Guidelines: Dual-Purpose Configuration Pin................................................. 32

3.1.2. Enabling Dual-Purpose Pin.........................................................................33

3.2. Configuring Intel MAX 10 Devices using JTAG Configuration....................................... 33

3.2.1. Auto-Generating Configuration Files for Third-Party Programming Tools...........34

3.2.2. Generating Third-Party Programming Files using Intel Quartus Prime

Programmer............................................................................................34

3.2.3. JTAG Configuration Setup..........................................................................35

3.2.4. ICB Settings in JTAG Configuration............................................................. 37

3.3. Configuring Intel MAX 10 Devices using Internal Configuration...................................37

3.3.1. Selecting Internal Configuration Modes....................................................... 38

3.3.2. .pof and ICB Settings............................................................................... 38

3.3.3. Programming .pof into Internal Flash..........................................................41

3.4. Implementing ISP Clamp in Intel Quartus Prime Software......................................... 42

3.4.1. Creating IPS File...................................................................................... 43

3.4.2. Executing IPS File.................................................................................... 43

3.5. Accessing Remote System Upgrade through User Logic.............................................43

3.6. Error Detection....................................................................................................44

3.6.1. Verifying Error Detection Functionality........................................................ 44

3.6.2. Enabling Error Detection........................................................................... 46

3.6.3. Accessing Error Detection Block Through User Logic..................................... 46

3.7. Enabling Data Compression...................................................................................48

3.7.1. Enabling Compression Before Design Compilation.........................................48

3.7.2. Enabling Compression After Design Compilation........................................... 49

3.8. AES Encryption....................................................................................................49

3.8.1. Generating .ekp File and Encrypt Configuration File...................................... 49

3.8.2. Generating .jam/.jbc/.svf file from .ekp file................................................. 51

3.8.3. Programming .ekp File and Encrypted POF File.............................................51

3.8.4. Encryption in Internal Configuration........................................................... 52

3.9. Intel MAX 10 JTAG Secure Design Example..............................................................54

3.9.1. Internal and External JTAG Interfaces.........................................................55

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3.9.2. JTAG WYSIWYG Atom for JTAG Control Block Access Using Internal JTAG

Interface.................................................................................................55

3.9.3. Executing LOCK and UNLOCK JTAG Instructions........................................... 57

3.9.4. Verifying the JTAG Secure Mode.................................................................58

4. Intel MAX 10 FPGA Configuration IP Core Implementation Guides............................... 60

4.1. Unique Chip ID Intel FPGA IP Core......................................................................... 60

4.1.1. Instantiating the Unique Chip ID Intel FPGA IP Core..................................... 60

4.1.2. Resetting the Unique Chip ID Intel FPGA IP Core.......................................... 61

4.2. Dual Configuration Intel FPGA IP Core.................................................................... 61

4.2.1. Instantiating the Dual Configuration Intel FPGA IP Core.................................61

5. Dual Configuration Intel FPGA IP Core References....................................................... 62

5.1. Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map................62

5.2. Dual Configuration Intel FPGA IP Core Parameters....................................................64

6. Unique Chip ID Intel FPGA IP Core References............................................................. 65

6.1. Unique Chip ID Intel FPGA IP Core Ports................................................................. 65

7. Document Revision History for the Intel MAX 10 FPGA Configuration User Guide......... 66

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1. Intel® MAX® 10 FPGA Configuration Overview

You can configure Intel® MAX® 10 configuration RAM (CRAM) using the following
configuration schemes:

• JTAG configuration—using JTAG interface.

• Internal configuration—using internal flash.

Supported Configuration Features

Table 1. Configuration Schemes and Features Supported by Intel MAX 10 Devices

Configuration Scheme

JTAG configuration — — — Yes

Internal configuration Yes Yes Yes Yes

Remote System

Upgrade

Compression Design Security SEU Mitigation

Related IP Cores

• Dual Configuration Intel FPGA IP—used in the remote system upgrade feature.

• Unique Chip ID Intel FPGA IP—retrieves the chip ID of Intel MAX 10 devices.

Related Information

• Intel MAX 10 FPGA Configuration Schemes and Features on page 5
Provides information about the configuration schemes and features.

• Intel MAX 10 FPGA Configuration Design Guidelines on page 32
Provides information about using the configuration schemes and features.

• Unique Chip ID Intel FPGA IP Core on page 21

• Dual Configuration Intel FPGA IP Core on page 19

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.

ISO
9001:2015
Registered

CRAM

Intel MAX 10 Device

JTAG In-System Programming

Configuration
Flash Memory

Configuration Data

Internal

Configuration

JTAG Configuration

.sof

.pof

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2. Intel MAX 10 FPGA Configuration Schemes and Features

2.1. Configuration Schemes

Figure 1. High-Level Overview of JTAG Configuration and Internal Configuration for

Intel MAX 10 Devices

2.1.1. JTAG Configuration

In Intel MAX 10 devices, JTAG instructions take precedence over the internal
configuration scheme.

Using the JTAG configuration scheme, you can directly configure the device CRAM
through the JTAG interface—TDI, TDO, TMS, and TCK pins. The Intel Quartus
software automatically generates an SRAM Object File (.sof). You can program
the .sof using a download cable with the Intel Quartus Prime software programmer.

Related Information

Configuring Intel MAX 10 Devices using JTAG Configuration on page 33

Provides more information about JTAG configuration using download cable with
Intel Quartus Prime software programmer.

2.1.1.1. JTAG Pins

Table 2. JTAG Pin

Pin Function Description

TDI

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.

Serial input pin for: •

TDI is sampled on the rising edge of TCK

•

TDI pins have internal weak pull-up resistors.

®

Prime

continued...

ISO
9001:2015
Registered

2. Intel MAX 10 FPGA Configuration Schemes and Features

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Pin Function Description

• instructions

• boundary-scan test (BST) data

• programming data

TDO

TMS

TCK

Serial output pin for:

• instructions

• boundary-scan test data

• programming data

Input pin that provides the control signal to
determine the transitions of the TAP
controller state machine.

Clock input to the BST circuitry. —

•

TDO is sampled on the falling edge of TCK

• The pin is tri-stated if data is not shifted out of the
device.

•

TMS is sampled on the rising edge of TCK

•

TMS pins have internal weak pull-up resistors.

All the JTAG pins are powered by the V

1B. In JTAG mode, the I/O pins support the

CCIO

LVTTL/LVCMOS 3.3-1.5V standards.

Related Information

• Intel MAX 10 Device Datasheet
Provides more information about supported I/O standards in Intel MAX 10
devices.

• Guidelines: Dual-Purpose Configuration Pin on page 32

• Enabling Dual-Purpose Pin on page 33

2.1.2. Internal Configuration

You need to program the configuration data into the configuration flash memory (CFM)
before internal configuration can take place. The configuration data to be written to
CFM will be part of the programmer object file (.pof). Using JTAG In-System

Programming (ISP), you can program the .pof into the internal flash.

During internal configuration, Intel MAX 10 devices load the CRAM with configuration
data from the CFM.

2.1.2.1. Internal Configuration Modes

Table 3. Supported Internal Configuration Modes Based on Intel MAX 10 Feature

Options

Intel MAX 10 Feature Options Supported Internal Configuration Mode

Compact

Flash and Analog

• Single Compressed Image

• Single Uncompressed Image

• Dual Compressed Images

• Single Compressed Image

• Single Compressed Image with Memory Initialization

• Single Uncompressed Image

• Single Uncompressed Image with Memory Initialization

Note:

In dual compressed images mode, you can use the CONFIG_SEL pin to select the
configuration image.

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Configuration Flash Memory SectorsUser Flash Memory Sectors

CFM0UFM0UFM1 CFM1CFM2

Dual Compressed Image

Single Uncompressed Image

Single Uncompressed Image
with Memory Initialization

Single Compressed Image
with Memory Initialization

Single Compressed Image

Compressed

Image 0

Compressed

Image 0

Uncompressed Image 0 with Memory Initialization

Compressed Image 0 with Memory Initialization

Uncompressed Image 0

Compressed Image 1

Additional UFM

UFM

UFM

UFM

UFM

UFM Additional UFM

Internal Configuration

Mode

2. Intel MAX 10 FPGA Configuration Schemes and Features

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Related Information

• Configuring Intel MAX 10 Devices using Internal Configuration on page 37

• Remote System Upgrade on page 13

2.1.2.2. Configuration Flash Memory

The CFM is a non-volatile internal flash that is used to store configuration images. The
CFM may store up to two compressed configuration images, depending on the
compression and the Intel MAX 10 devices. The compression ratio for the configuration
image should be at least 30% for the device to be able store two configuration
images.

Related Information

Configuration Flash Memory Permissions on page 23

2.1.2.2.1. Configuration Flash Memory Sectors

All CFM in Intel MAX 10 devices consist of three sectors, CFM0, CFM1, and CFM2
except for the 10M02. The sectors are programmed differently depending on the
internal configuration mode you select.

The 10M02 device consists of only CFM0. The CFM0 sector in 10M02 devices is
programmed similarly when you select single compressed image or single
uncompressed image.

Figure 2. Configuration Flash Memory Sectors Utilization for all Intel MAX 10 with

Analog and Flash Feature Options

Unutilized CFM1 and CFM2 sectors can be used for additional user flash memory (UFM).

Related Information

CFM and UFM Array Size

Provides more information about UFM and CFM sector sizes.

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2.1.2.2.2. Configuration Flash Memory Programming Time

Table 4. Configuration Flash Memory Programming Time for Sectors in Intel MAX 10

Devices

Note: The programming time reflects JTAG interface programming time only without any system

Device

(1)

10M02

10M04 and 10M08 6.5 4.6 11.1

10M16 12.0 8.9 20.8

10M25 16.4 12.6 29.0

10M40 and 10M50 30.2 22.7 52.9

overhead. It does not reflect the actual programming time that you face. To compensate the
system overhead, Intel Quartus Prime Programmer is enhanced to utilize flash parallel mode
during device programming for Intel MAX 10 10M04/08/16/25/40/50 devices. The 10M02
device does not support flash parallel mode, you may experience a relatively slow
programming time if compare to other device.

In-System Programming Time (s)

CFM2 CFM1 CFM0

— — 5.4

2.1.2.3. In-System Programming

You can program the internal flash including the CFM of Intel MAX 10 devices with ISP
through industry standard IEEE 1149.1 JTAG interface. ISP offers the capability to
program, erase, and verify the CFM. The JTAG circuitry and ISP instructions for Intel
MAX 10 devices are compliant to the IEEE-1532-2002 programming specification.

During ISP, the Intel MAX 10 receives the IEEE Std. 1532 instructions, addresses, and
data through the TDI input pin. Data is shifted out through the TDO output pin and
compared with the expected data.

The following are the generic flow of an ISP operation:

1. Check ID—the JTAG ID is checked before any program or verify process. The time

required to read this JTAG ID is relatively small compared to the overall
programming time.

2. Enter ISP—ensures the I/O pins transition smoothly from user mode to the ISP

mode.

3. Sector Erase—shifting in the address and instruction to erase the device and

applying erase pulses.

4. Program—shifting in the address, data, and program instructions and generating

the program pulse to program the flash cells. This process is repeated for each
address in the internal flash sector.

5. Verify—shifting in addresses, applying the verify instruction to generate the read

pulse, and shifting out the data for comparison. This process is repeated for each
internal flash address.

6. Exit ISP—ensures that the I/O pins transition smoothly from the ISP mode to the

user mode.

(1)

The CFM0 programming time for the 10M02SCU324 device is 11.1 s.

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You can also use the Intel Quartus Prime Programmer to program the CFM.

Related Information

Programming .pof into Internal Flash on page 41

Provides the steps to program the .pof using Intel Quartus Prime Programmer.

2.1.2.3.1. ISP Clamp

When a normal ISP operation begins, all I/O pins are tri-stated. For situations when
the I/O pins of the device should not be tri-stated when the device is in ISP operation,
you can use the ISP clamp feature.

When the ISP clamp feature is used, you can set the I/O pins to tri-state, high, low, or
sample and sustain. The Intel Quartus Prime software determines the values to be
scanned into the boundary-scan registers of each I/O pin, based on your settings. This
will determine the state of the pins to be clamped to when the device programming is
in progress.

Before clamping the I/O pins, the SAMPLE/PRELOAD JTAG instruction is first executed
to load the appropriate values to the boundary-scan registers. After loading the
boundary-scan registers with the appropriate values, the EXTEST instruction is
executed to clamp the I/O pins to the specific values loaded into the boundary-scan
registers during SAMPLE/PRELOAD.

If you choose to sample the existing state of a pin and hold the pin to that state when
the device enters ISP clamp mode, you must ensure that the signal is in steady state.
A steady state signal is needed because you cannot control the sample set-up time as
it depends on the TCK frequency as well as the download cable and software. You
might not capture the correct value when sampling a signal that toggles or is not
static for long periods of time.

Related Information

Implementing ISP Clamp in Intel Quartus Prime Software on page 42

2.1.2.3.2. Real-Time ISP

In a normal ISP operation, to update the internal flash with a new design image, the
device exits from user mode and all I/O pins remain tri-stated. After the device
completes programing the new design image, it resets and enters user mode.

The real-time ISP feature updates the internal flash with a new design image while
operating in user mode. During the internal flash programming, the device continues
to operate using the existing design. After the new design image programming
process completes, the device will not reset. The new design image update only takes
effect in the next reconfiguration cycle.

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2.1.2.3.3. ISP and Real-Time ISP Instructions

Table 5. ISP and Real-Time ISP Instructions for Intel MAX 10 Devices

Instruction Instruction Code Description

CONFIG_IO 00 0000 1101

PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration

ISC_ENABLE_HIZ

ISC_ENABLE_CLAMP

(2)

(2)

10 1100 1100

10 0011 0011

ISC_DISABLE 10 0000 0001

(3)

(3)

(3)

(3)

10 1111 0100

10 0001 0000

10 0000 0011

10 1111 0010

ISC_PROGRAM

ISC_NOOP

ISC_ADDRESS_SHIFT

ISC_ERASE

• Allows I/O reconfiguration through JTAG ports using the
IOCSR for JTAG testing. This is executed after or during
configurations.

•

nSTATUS pin must go high before you can issue the
CONFIG_IO instruction.

even though the physical pin is unaffected.

• Puts the device in ISP mode, tri-states all I/O pins, and drives
all core drivers, logic, and registers.

•

Device remains in the ISP mode until the ISC_DISABLE
instruction is loaded and updated.

•

The ISC_ENABLE instruction is a mandatory instruction. This
requirement is met by the ISC_ENABLE_CLAMP or

ISC_ENABLE_HIZ instruction.

• Puts the device in ISP mode and forces all I/O pins to follow
the contents of the JTAG boundary-scan register.

• When this instruction is activated, all core drivers, logics, and
registers are frozen. The I/O pins remain clamped until the
device exits ISP mode successfully.

• Brings the device out of ISP mode.

•

Successful completion of the ISC_DISABLE instruction
happens immediately after waiting 200 µs in the Run-Test/Idle
state.

Sets the device up for in-system programming. Programming
occurs in the run-test or idle state.

• Sets the device to a no-operation mode without leaving the
ISP mode and targets the ISC_Default register.

• Use when:
— two or more ISP-compliant devices are being accessed in

ISP mode and;

— a subset of the devices perform some instructions while

other more complex devices are completing extra steps in
a given process.

Sets the device up to load the flash address. It targets the

ISC_Address register, which is the flash address register.

• Sets the device up to erase the internal flash.

•

Issue after ISC_ADDRESS_SHIFT instruction.

continued...

(2)

Do not issue the ISC_ENABLE_HIZ and ISC_ENABLE_CLAMP instructions from the core logic.

(3)

All ISP and real-time ISP instructions are disabled when the device is not in the ISP or real­time ISP mode, except for the enabling and disabling instructions.

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Instruction Instruction Code Description

ISC_READ

(3)

10 0000 0101

BGP_ENABLE 01 1001 1001

BGP_DISABLE 01 0110 0110

• Sets the device up for verifying the internal flash under
normal user bias conditions.

•

The ISC_READ instruction supports explicit addressing and
auto-increment, also known as the Burst mode.

• Sets the device to the real-time ISP mode.

• Allows access to the internal flash configuration sector while
the device is still in user mode.

• Brings the device out of the real-time ISP mode.

• The device has to exit the real-time ISP mode using the

BGP_DISABLE instruction after it is interrupted by

reconfiguration.

Caution: Do not use unsupported JTAG instructions. It will put the device into an unknown state

and requires a power cycle to recover the operation.

2.1.2.4. Initialization Configuration Bits

Initialization Configuration Bits (ICB) stores the configuration feature settings of the
Intel MAX 10 device. You can set the ICB settings in the Convert Programming File
tool.

Table 6. ICB Values and Descriptions for Intel MAX 10 Devices

Configuration Settings Description Default State/

Set I/O to weak pull-up prior usermode • Enable: Sets I/O to weak pull-up during device

Configure device from CFM0 only. Enable:

Use secondary image ISP data as
default setting when available.

Verify Protect To disable or enable the Verify Protect feature. Disable

Allow encrypted POF only If enabled, configuration error will occur if

configuration.

• Disable: Tri-states I/O

•

CONFIG_SEL pin setting is disabled.

• Device automatically loads image 0.

• Device does not load image 1 if image 0 fails.
Disable:

• Device automatically loads secondary image if initial
image fails.

Select ISP data from initial or secondary image to include in
the POF.

• Disable: Use ISP data from initial image

• Enable: Use ISP data from secondary image

ISP data contains the information about state of the pin
during ISP. This can be either tri-state with weak pull-up or
clamp the I/O state. You can set the ISP clamp through
Device and Pin Option, or Pin Assignment tool.

unencrypted .pof is used.

Value

Enable

Disable

Disable

Disable

continued...

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Configuration Settings Description Default State/

JTAG Secure

Enable Watchdog To disable or enable the watchdog timer for remote system

Watchdog value To set the watchdog timer value for remote system

(4)

To disable or enable the JTAG Secure feature. Disable

upgrade.

upgrade.

Related Information

• .pof and ICB Settings on page 38

• Verify Protect on page 22

• JTAG Secure Mode on page 22

• ISP and Real-Time ISP Instructions on page 10

• User Watchdog Timer on page 18

• Generating .pof using Convert Programming Files on page 39
Provides more information about setting the ICB during .pof generation using
Convert Programming File.

2.1.2.5. Internal Configuration Time

The internal configuration time measurement is from the rising edge of nSTATUS
signal to the rising edge of CONF_DONE signal.

Value

Enable

0xFFF

(5)

Table 7. Internal Configuration Time for Intel MAX 10 Devices (Uncompressed .rbf)

Device Internal Configuration Time (ms)

Unencrypted Encrypted

Without Memory

Initialization

Min Max Min Max Min Max Min Max

10M02/

10M02SCU324

10M04 0.6 2.7 1.0 3.4 5.0 15.0 6.8 19.6

10M08 0.6 2.7 1.0 3.4 5.0 15.0 6.8 19.6

10M16 1.1 3.7 1.4 4.5 9.3 25.3 11.7 31.5

10M25 1.0 3.7 1.3 4.4 14.0 38.1 16.9 45.7

10M40 2.6 6.9 3.2 9.8 41.5 112.1 51.7 139.6

10M50 2.6 6.9 3.2 9.8 41.5 112.1 51.7 139.6

(4)

The JTAG Secure feature will be disabled by default in Intel Quartus Prime software. To make

0.3/0.6 1.7/2.7 — — 1.7/5.0 5.4/15.0 — —

With Memory
Initialization

Without Memory

Initialization

With Memory

Initialization

this option visible, refer to Generating .pof using Convert Programming Files on page 39 for
more information.

(5)

The watchdog timer value depends on the Intel MAX 10 you are using. Refer to the Watchdog
Timer section for more information.

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Table 8. Internal Configuration Time for Intel MAX 10 Devices (Compressed .rbf)

Compression ratio depends on design complexity. The minimum value is based on the best case (25% of
original .rbf sizes) and the maximum value is based on the typical case (70% of original .rbf sizes).

Device Internal Configuration Time (ms)

Unencrypted/Encrypted

Without Memory Initialization With Memory Initialization

Min Max Min Max

10M02/10M02SCU324 0.3/0.6 5.2/10.7 — —

10M04 0.6 10.7 1.0 13.9

10M08 0.6 10.7 1.0 13.9

10M16 1.1 17.9 1.4 22.3

10M25 1.1 26.9 1.4 32.2

10M40 2.6 66.1 3.2 82.2

10M50 2.6 66.1 3.2 82.2

2.2. Configuration Features

2.2.1. Remote System Upgrade

Intel MAX 10 devices support the remote system upgrade feature. By default, the
remote system upgrade feature is enabled when you select the dual compressed
image internal configuration mode.

The remote system upgrade feature in Intel MAX 10 devices offers the following
capabilities:

• Manages remote configuration

• Provides error detection, recovery, and information

• Supports direct-to-application configuration image

•

Supports compressed and encrypted .pof

There are two methods to access remote system upgrade in Intel MAX 10 devices:

• Dual Configuration Intel FPGA IP core

• User interface

Related Information

• Dual Configuration Intel FPGA IP Core on page 19

• Accessing Remote System Upgrade through User Logic on page 43

• AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the

Nios II Processor

Provides reference design for remote system upgrade in Intel MAX 10 FPGA
devices.

• I2C Remote System Update Example

This example demonstrates a remote system upgrade using the I2C protocol.

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Intel® MAX® 10 FPGA Configuration User Guide

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Sample CONFIG_SEL pin

Image 0 Image 1

CONFIG_SEL=0

CONFIG_SEL=1

Wait for Reconfiguration

Power-up

Reconfiguration

Reconfiguration

First Error Occurs

First Error Occurs

Second Error Occurs

Flow when

Configure device
from CFM0 only

is enabled.

Second Error Occurs

Error Occurs

Reconfiguration

Reconfiguration

Power-up

2. Intel MAX 10 FPGA Configuration Schemes and Features

2.2.1.1. Remote System Upgrade Flow

Both the application configuration images, image 0 and image 1, are stored in the
CFM. The Intel MAX 10 device loads either one of the application configuration image
from the CFM.

Figure 3. Remote System Upgrade Flow for Intel MAX 10 Devices

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The remote system upgrade feature detects errors in the following sequence:

1.

After power-up, the device samples the CONFIG_SEL pin to determine which
application configuration image to load. The CONFIG_SEL pin setting can be
overwritten by the input register of the remote system upgrade circuitry for the

subsequent reconfiguration.

2. If an error occurs, the remote system upgrade feature reverts by loading the other
application configuration image. These errors cause the remote system upgrade
feature to load another application configuration image:

• Internal CRC error

• User watchdog timer time-out

3. Once the revert configuration completes and the device is in user mode, you can
use the remote system upgrade circuitry to query the cause of error and which
application image failed.

4. If a second error occurs, the device waits for a reconfiguration source. If the
Auto-restart configuration after error is enabled, the device will reconfigure
without waiting for any reconfiguration source.

5. Reconfiguration is triggered by the following actions:

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Status Register (SR)

Previous
State
Register 2
Bit[31..0]

State
Register 1
Bit[31..0]

Current
State
Logic
Bit[33..0]

Internal Oscillator

Control Register
Bit [38..0]

Logic

Input Register
Bit [38..0]

update

Logic

Bit [40..39]

doutdin

Bit [38..0]

dout

din

capture

Shift Register

clkout

capture

update

Logic

clkin

RU_DIN

RU_SHIFTnLD

RU_CAPTnUPDT

RU_CLK

RU_nRSTIMER

Logic Array

RU
Reconfiguration
State
Machine

User
Watchdog
Timer

RU
Master
State
Machine

timeout

RU_nCONFIGRU_DOUT

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•

Driving the nSTATUS low externally.

•

Driving the nCONFIG low externally.

•

Driving RU_nCONFIG low.

2.2.1.2. Remote System Upgrade Circuitry

Figure 4. Remote System Upgrade Circuitry

Send Feedback

The remote system upgrade circuitry does the following functions:

• Tracks the current state of configuration

• Monitors all reconfiguration sources

• Provides access to set up the application configuration image

• Returns the device to fallback configuration if an error occurs

• Provides access to the information on the failed application configuration image

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2.2.1.2.1. Remote System Upgrade Circuitry Signals

Table 9. Remote System Upgrade Circuitry Signals for Intel MAX 10 Devices

Core Signal Name Logical

Signal

Name

RU_DIN regin

RU_DOUT regout

RU_nRSTIMER rsttimer

RU_nCONFIG rconfig

RU_CLK clk

RU_SHIFTnLD shiftnld

RU_CAPTnUPDT captnupdt

Input/

Output

Input

Output

Input

Input

Input

Input

Input

Description

Use this signal to write data to the shift register on the rising edge of

RU_CLK. To load data to the shift register, assert RU_SHIFTnLD.

Use this signal to get output data from the shift register. Data is
clocked out on each rising edge of RU_CLK if RU_SHIFTnLD is
asserted.

• Use this signal to reset the user watchdog timer. A falling edge of
this signal triggers a reset of the user watchdog timer.

•

To reset the timer, pulse the RU_nRSTIMER signal for a minimum of
250 ns.

Use this signal to reconfigure the device. Driving this signal low
triggers the device to reconfigure if you enable the remote system
upgrade feature.

The clock to the remote system upgrade circuitry. All registers in this
clock domain are enabled in user mode if you enable the remote
system upgrade. Shift register and input register are positive edge flip­flops.

Control signals that determine the mode of remote system upgrade
circuitry.

•

When RU_SHIFTnLD is driven low and RU_CAPTnUPDT is driven
low, the input register is loaded with the contents of the shift
register on the rising edge of RU_CLK.

•

When RU_SHIFTnLD is driven low and RU_CAPTnUPDT is driven
high, the shift register captures values from the input_cs_ps
module on the rising edge of RU_CLK.

•

When RU_SHIFTnLD is driven high, the RU_CAPTnUPDT will be
ignored and the shift register shifts data on each rising edge of

RU_CLK.

Related Information

Intel MAX 10 FPGA Device Datasheet

Provides more information about Remote System Upgrade timing specifications.

2.2.1.2.2. Remote System Upgrade Circuitry Input Control

The remote system upgrade circuitry has three modes of operation.

• Update—loads the values in the shift register into the input register.

• Capture—loads the shift register with data to be shifted out.

• Shift—shifts out data to the user logic.

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Table 10. Control Inputs to the Remote System Upgrade Circuitry

Remote System Upgrade Circuitry Control Inputs Operation

RU_SHIFTnLD RU_CAPTnUPDT

0 0 Don't Care Don't Care Update

0 1 0 0 Capture Current State

0 1 0 1 Capture

0 1 1 0 Capture

0 1 1 1 Capture

1 Don't Care Don't Care Don't Care Shift

Shift register

[40]

Shift register

[39]

Mode

The following shows examples of driving the control inputs in the remote system
upgrade circuitry:

•

When you drive RU_SHIFTnLD high to 1’b1, the shift register shifts data on each
rising edge of RU_CLK and RU_CAPTnUPDT has no function.

•

When you drive both RU_SHIFTnLD and RU_CAPTnUPDT low to 1’b0, the input
register is loaded with the contents of the shift register on the rising edge of

RU_CLK.

•

When you drive RU_SHIFTnLD low to 1’b0 and RU_CAPTnUPDT high to 1’b1, the
shift register captures values on the rising edge of RU_DCLK.

Input Settings for Registers

Shift

Register[38:0]

Shift Register

[38:0]

{8’b0, Previous

State

Application1}

{8’b0, Previous

State

Application2}

Input

Register[38:0]

{ru_din, Shift

Register

[38:1]}

Input

Register[38:0]

Shift Register

[38:0]

Input

Register[38:0]

Input

Register[38:0]

Input

Register[38:0]

Input

Register[38:0]

Input

Register[38:0]

2.2.1.2.3. Remote System Upgrade Input Register

Table 11. Remote System Upgrade Input Register for Intel MAX 10 Devices

Bits Name Description

38:14 Reserved

13

12

11:0 Reserved

Send Feedback

ru_config_sel

ru_config_sel_overwrit

e

Reserved—set to 0.

• 0: Load configuration image 0

• 1: Load configuration image 1
This bit will only work if the ru_config_sel_overwrite bit is set to 1.

•

0: Disable overwrite CONFIG_SEL pin

•

1: Enable overwrite CONFIG_SEL pin

Reserved—set to 0.

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2.2.1.2.4. Remote System Upgrade Status Registers

Table 12. Remote System Upgrade Status Register—Current State Logic Bit for Intel

MAX 10 Devices

Bits Name Description

33:30

29

28:0

msm_cs

ru_wd_en

wd_timeout_value

The current state of the master state machine (MSM).

The current state of the enabled user watchdog timer. The default state is active
high.

The current, entire 29-bit watchdog time-out value.

Table 13. Remote System Upgrade Status Register—Previous State Bit for Intel MAX 10

Devices

Bits Name Description

31

30

29

28

27:26

25:22

21:0

nconfig

crcerror

nstatus

wdtimer

An active high field that describes the reconfiguration sources which caused the
Intel MAX 10 device to leave the previous application configuration. In the event
of a tie, the higher bit order takes precedence. For example, if the nconfig and
the ru_nconfig triggered at the same time, the nconfig takes precedence
over the ru_nconfig.

Reserved Reserved—set to 0.

msm_cs

The state of the MSM when a reconfiguration event occurred. The reconfiguration
will cause the device to leave the previous application configuration.

Reserved Reserved—set to 0.

Related Information

Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map on page

62

2.2.1.2.5. Master State Machine

The master state machine (MSM) tracks current configuration mode and enables the
user watchdog timer.

Table 14. Remote System Upgrade Master State Machine Current State Descriptions for

Intel MAX 10 Devices

msm_cs Values

0010

0011

0100

0101

Image 0 is being loaded.

Image 1 is being loaded after a revert in application image happens.

Image 1 is being loaded.

Image 0 is being loaded after a revert in application image happens.

State Description

2.2.1.3. User Watchdog Timer

The user watchdog timer prevents a faulty application configuration from stalling the
device indefinitely. You can use the timer to detect functional errors when an
application configuration is successfully loaded into the device.

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Dual

Configuration

clk

nreset

avmm_rcv_address[2..0]

avmm_rcv_read

avmm_rcv_writedata[31..0]

avmm_rcv_write

avmm_rcv_readdata[31..0]

2. Intel MAX 10 FPGA Configuration Schemes and Features

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The counter is 29 bits wide and has a maximum count value of 229. When specifying
the user watchdog timer value, specify only the most significant 12 bits. The
granularity of the timer setting is 217 cycles. The cycle time is based on the frequency
of the user watchdog timer internal oscillator. Depending on the counter and the
internal oscillator of the device, you can set the cycle time from 9 ms to 244 s.

Figure 5. Watchdog Timer Formula for Intel MAX 10 Devices

The timer begins counting as soon as the application configuration enters user mode.
When the timer expires, the remote system upgrade circuitry generates a time-out
signal, updates the status register, and triggers the loading of the revert configuration
image. To reset the timer and ensure that the application configuration is valid, pulse
the RU_NRSTIMER continuously for a minimum of 250 ns per reset pulse.

When you enable the watchdog timer, the setting will apply to all images, all images
should contain the soft logic configuration to reset the timer. Application configuration
will reset the control block registers.

Related Information

• User Watchdog Internal Circuitry Timing Specifications
Provides more information about the user watchdog frequency.

• Initialization Configuration Bits on page 11

2.2.1.4. Dual Configuration Intel FPGA IP Core

The Dual Configuration Intel FPGA IP core offers the following capabilities through
Avalon® memory-mapped interface:

•

Asserts RU_nCONFIG to trigger reconfiguration.

•

Asserts RU_nRSTIMER to reset watchdog timer if the watchdog timer is enabled.

• Writes configuration setting to the input register of the remote system upgrade

circuitry.

• Reads information from the remote system upgrade circuitry.

Figure 6. Dual Configuration Intel FPGA IP Core Block Diagram

Related Information

• Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map on

page 62

Send Feedback

Intel® MAX® 10 FPGA Configuration User Guide

19

• Avalon Interface Specifications
Provides more information about the Avalon memory-mapped interface
specifications applied in Dual Configuration Intel FPGA IP core.

• Instantiating the Dual Configuration Intel FPGA IP Core on page 61

• Dual Configuration Intel FPGA IP Core References on page 62

• Remote System Upgrade on page 13

• AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the

Nios II Processor

Provides reference design for remote system upgrade in Intel MAX 10 FPGA
devices.

• I2C Remote System Update Example
This example demonstrates a remote system upgrade using the I2C protocol.

2.2.2. Configuration Design Security

The Intel MAX 10 design security feature supports the following capabilities:

• Encryption—Built-in encryption standard (AES) to support 128-bit key industry-

standard design security algorithm

• Chip ID—Unique device identification

• JTAG secure mode—limits access to JTAG instructions

• Verify Protect—allows optional disabling of CFM content read-back

2. Intel MAX 10 FPGA Configuration Schemes and Features

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2.2.2.1. AES Encryption Protection

The Intel MAX 10 design security feature provides the following security protection for
your designs:

• Security against copying—the non-volatile key is securely stored in the Intel MAX

10 devices and cannot be read through any interface. Without this key, attacker
will not be able to decrypt the encrypted configuration image.

• Security against reverse engineering—reverse engineering from an encrypted

configuration file is very difficult and time consuming because the file requires
decryption.

• Security against tampering—after you enable the JTAG Secure and Encrypted POF

(EPOF) only, the Intel MAX 10 device can only accept configuration files encrypted
with the same key. Additionally, configuration through the JTAG interface is
blocked.

Related Information

Generating .pof using Convert Programming Files on page 39

2.2.2.1.1. Encryption and Decryption

Intel MAX 10 supports AES encryption. Programming bitstream is encrypted based on
the encryption key that is specified by you. In Intel MAX 10 devices, the key is part of
the ICB settings stored in the internal flash. Hence, the key will be non-volatile but
you can clear/delete the key by a full chip erase the device.

Intel® MAX® 10 FPGA Configuration User Guide

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clkin data_valid

chip_id[63..0]reset

Unique Chip ID

2. Intel MAX 10 FPGA Configuration Schemes and Features

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When you use compression with encryption, the configuration file is first compressed,
and then encrypted using the Intel Quartus Prime software. During configuration, the
device first decrypts, and then decompresses the configuration file.

The header and I/O configuration shift register (IOCSR) data will not be encrypted.
The decryption block is activated after the IOCSR chain is programmed. The
decryption block only decrypts core data and postamble.

Related Information

JTAG Instruction Availability on page 23

2.2.2.2. Unique Chip ID

Unique chip ID provides the following features:

• Identifies your device in your design as part of a security feature to protect your
design from an unauthorized device.

• Provides non-volatile 64-bits unique ID for each Intel MAX 10 device with write
protection.

You can use the Unique Chip ID Intel FPGA IP core to acquire the chip ID of your Intel
MAX 10 device.

Related Information

• Unique Chip ID Intel FPGA IP Core on page 60

• Unique Chip ID Intel FPGA IP Core Ports on page 65

2.2.2.2.1. Unique Chip ID Intel FPGA IP Core

Figure 7. Unique Chip ID Intel FPGA IP Core Block Diagram

At the initial state, the data_valid signal is low because no data is read from the
unique chip ID block. After feeding a clock signal to the clkin input port, the Unique
Chip ID Intel FPGA IP core begins to acquire the chip ID of your device through the

unique chip ID block. After acquiring the chip ID of your device, the Unique Chip ID
Intel FPGA IP core asserts the data_valid signal to indicate that the chip ID value at
the output port is ready for retrieval.

The operation repeats only when you provide another clock signal when the

data_valid signal is low. If the data_valid signal is high when you provide

another clock signal, the operation stops because the chip_id[63..0] output holds
the chip ID of your device.

Send Feedback

A minimum of 67 clock cycles are required for the data_valid signal to go high.

Intel® MAX® 10 FPGA Configuration User Guide

21

The chip_id[63:0]output port holds the value of chip ID of your device until you
reconfigure the device or reset the Unique Chip ID Intel FPGA IP core.

2.2.2.3. JTAG Secure Mode

In JTAG Secure mode, the device only allows mandatory IEEE 1149.1 JTAG
instructions to be exercised.

You can enable the JTAG secure when generating the .pof in the Convert

Programming Files. To exit JTAG secure mode, issue the UNLOCK JTAG instruction.

The LOCK JTAG instruction puts the device in the JTAG secure mode again. The LOCK
and UNLOCK JTAG instructions can only be issued through the JTAG core access. Refer
to Table 16 on page 23 for list of available instructions.

Related Information

• JTAG Instruction Availability on page 23

• Configuration Flash Memory Permissions on page 23

• JTAG Secure Design Example

• Generating .pof using Convert Programming Files on page 39

2.2.2.3.1. JTAG Secure Mode Instructions

2. Intel MAX 10 FPGA Configuration Schemes and Features

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Table 15. JTAG Secure Mode Instructions for Intel MAX 10 Devices

JTAG

Instruction

LOCK 10 0000 0010

UNLOCK 10 0000 1000

Instruction Code Description

• Activates the JTAG secure mode.

• Blocks access from both external pins and core to JTAG.

Deactivates the JTAG secure mode.

2.2.2.4. Verify Protect

Verify Protect is a security feature to enhance CFM security. When you enable the
Verify Protect, only program and erase operation are allowed on the CFM. This
capability protects the CFM contents from being copied.

You can turn on the Verify Protect feature when converting the .sof file to .pof file
in the Intel Quartus Prime Convert Programming File tool.

Related Information

• Configuration Flash Memory Permissions on page 23

• Generating .pof using Convert Programming Files on page 39

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2. Intel MAX 10 FPGA Configuration Schemes and Features

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2.2.2.5. JTAG Instruction Availability

Table 16. JTAG Instruction Availability Based on JTAG Secure Mode and Encryption

Settings

JTAG Secure Mode Encryption Description

Disabled All JTAG Instructions enabled

Disabled

Enabled

Enabled

Disabled All non-mandatory IEEE 1149.1 JTAG instructions are disabled except:

Enabled

Related Information

• JTAG Secure Mode on page 22

• Intel MAX 10 JTAG Secure Design Example on page 54

• JTAG Secure Design Example

• Encryption and Decryption on page 20

All JTAG Instructions are enabled except:

•

CONFIGURE

•

SAMPLE/PRELOAD

•

BYPASS

•

EXTEST

•

IDCODE

•

UNLOCK

•

LOCK

2.2.2.6. Configuration Flash Memory Permissions

The JTAG secure mode and verify protect features determines the CFM operation
permission. The table list the operations permitted based on the security settings.

Table 17. CFM Permissions for Intel MAX 10 Devices

JTAG Secure Mode Disabled JTAG Secure Mode Enabled

Operation

ISP through core Illegal operation Illegal operation Illegal operation Illegal operation

ISP through JTAG pins Full access

Real-time ISP through
core

Real-time ISP through
JTAG pins

UFM interface through

(6)

core

Related Information

• JTAG Secure Mode on page 22

• Intel MAX 10 JTAG Secure Design Example on page 54

• JTAG Secure Design Example

Verify Protect

Disabled

Full access

Full access

Full access Full access Full access Full access

Verify Protect

Enabled

Program and erase
only

Program and erase
only

Program and erase
only

Verify Protect

Disabled

No access No access

No access No access

No access No access

Verify Protect

Enabled

(6)

The UFM interface through core is available if you select the dual compressed image mode.

Send Feedback

Intel® MAX® 10 FPGA Configuration User Guide

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2. Intel MAX 10 FPGA Configuration Schemes and Features

• Verify Protect on page 22

• Generating .pof using Convert Programming Files on page 39

2.2.3. SEU Mitigation and Configuration Error Detection

The dedicated circuitry built in Intel MAX 10 devices consists of an error detection
cyclic redundancy check (EDCRC) feature. You can use this feature to mitigate single­event upset (SEU) or soft errors.

The hardened on-chip EDCRC circuitry allows you to perform the following operations
without any impact on the fitting of the device:

• Auto-detection of cyclic redundancy check (CRC) errors during configuration.

• Identification of SEU in user mode with the optional CRC error detection.

• Testing of error detection by error detection verification through the JTAG
interface.

Related Information

• Verifying Error Detection Functionality on page 44

• Enabling Error Detection on page 46

• Accessing Error Detection Block Through User Logic on page 46

UG-M10CONFIG | 2020.11.05

2.2.3.1. Configuration Error Detection

In configuration mode, a frame-based CRC is stored in the configuration data and
contains the CRC value for each data frame.

During configuration, the Intel MAX 10 device calculates the CRC value based on the
frame of data that is received and compares it against the frame CRC value in the data
stream. Configuration continues until the device detects an error or when all the
values are calculated.

For Intel MAX 10 devices, the CRC is computed by the Intel Quartus Prime software
and downloaded into the device as part of the configuration bit stream. These devices
store the CRC in the 32-bit storage register at the end of the configuration mode.

2.2.3.2. User Mode Error Detection

SEUs are changes in a CRAM bit state due to an ionizing particle. Intel MAX 10 devices
have built-in error detection circuitry to detect data corruption in the CRAM cells.

This error detection capability continuously computes the CRC of the configured CRAM
bits. The CRC of the contents of the device are compared with the pre-calculated CRC
value obtained at the end of the configuration. If the CRC values match, there is no
error in the current configuration CRAM bits. The process of error detection continues
until the device is reset—by setting nCONFIG to low.

The error detection circuitry in Intel MAX 10 device uses a 32-bit CRC IEEE Std. 802
and a 32-bit polynomial as the CRC generator. Therefore, the device performs a single
32-bit CRC calculation. If an SEU does not occur, the resulting 32-bit signature value is

0x000000, which results in a 0 on the output signal CRC_ERROR. If an SEU occurs in

the device, the resulting signature value is non-zero and the CRC_ERROR output signal
is 1. You must decide whether to reconfigure the FPGA by strobing the nCONFIG pin
low or ignore the error.

Intel® MAX® 10 FPGA Configuration User Guide

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Send Feedback

Control Signals

Error Detection

State Machine

32-bit Storage

Register

Compute & Compare

CRC

32-bit Signature

Register

32

32

32

CRC_ERROR

2. Intel MAX 10 FPGA Configuration Schemes and Features

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2.2.3.2.1. Error Detection Block

Figure 8. Error Detection Block Diagram

Error detection block diagram including the two related 32-bit registers—the signature register and the storage
register.

There are two sets of 32-bit registers in the error detection circuitry that store the
computed CRC signature and pre-calculated CRC value. A non-zero value on the
signature register causes the CRC_ERROR pin to go high.

Table 18. Error Detection Registers for Intel MAX 10 Devices

Register Description

This register contains the CRC signature. The signature register contains the result of the user
32-bit signature
register

32-bit storage register

mode calculated CRC value compared against the pre-calculated CRC value. If no errors are

detected, the signature register is all zeros. A non-zero signature register indicates an error in the

configuration CRAM contents. The CRC_ERROR signal is derived from the contents of this register.

This register is loaded with the 32-bit pre-computed CRC signature at the end of the configuration

stage. The signature is then loaded into the 32-bit Compute and Compare CRC block during user

mode to calculate the CRC error. This register forms a 32-bit scan chain during execution of the

CHANGE_EDREG JTAG instruction. The CHANGE_EDREG JTAG instruction can change the content of

the storage register. Therefore, the functionality of the error detection CRC circuitry is checked in-

system by executing the instruction to inject an error during the operation. The operation of the

device is not halted when issuing the CHANGE_EDREG JTAG instruction.

2.2.3.2.2. CHANGE_EDREG JTAG Instruction

Table 19.

JTAG Instruction Instruction Code Description

CHANGE_EDREG 00 0001 0101 This instruction connects the 32-bit CRC storage register between TDI

2.2.3.3. Error Detection Timing

CHANGE_EDREG JTAG Instruction Description

and TDO. Any precomputed CRC is loaded into the CRC storage register
to test the operation of the error detection CRC circuitry at the

CRC_ERROR pin.

When the error detection CRC feature is enabled through the Intel Quartus Prime
software, the device automatically activates the CRC process upon entering user
mode, after configuration and initialization is complete.

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The CRC_ERROR pin will remain low until the error detection circuitry has detected a
corrupted bit in the previous CRC calculation. After the pin goes high, it remains high
during the next CRC calculation. This pin does not log the previous CRC calculation. If
the new CRC calculation does not contain any corrupted bits, the CRC_ERROR pin is
driven low. The error detection runs until the device is reset.

The error detection circuitry is clocked by an internal configuration oscillator with a
divisor that sets the maximum frequency. The CRC calculation time depends on the
device and the error detection clock frequency.

Related Information

Enabling Error Detection on page 46

2.2.3.3.1. Error Detection Frequency

You can set a lower clock frequency by specifying a division factor in the Intel Quartus
Prime software.

Table 20. Minimum and Maximum Error Detection Frequencies for Intel MAX 10 Devices

Device Error Detection Frequency Maximum Error

Frequency (MHz)

10M02 55 MHz/2n to 116 MHz/2

10M04

10M08

10M16

10M25

10M40 35 MHz/2n to 77 MHz/2

10M50

n

n

Detection

58 214.8 1, 2, 3, 4, 5, 6, 7, 8

38.5 136.7

Minimum Error

Detection

Frequency (kHz)

Valid Values for n

2.2.3.3.2. Cyclic Redundancy Check Calculation Timing

Table 21. Cyclic Redundancy Check Calculation Time for Intel MAX 10 Devices

Device Divisor Value (n = 2)

Minimum Time (ms) Maximum Time (ms)

10M02/10M02SCU324 2/6 6.6/15.7

10M04 6 15.7

10M08 6 15.7

10M16 10 25.5

10M25 14 34.7

10M40 43 106.7

10M50 43 106.7

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Figure 9. CRC Calculation Formula

You can use this formula to calculate the CRC calculation time for divisor other than 2.

Example 1. CRC Calculation Example

For 10M16 device with divisor value of 256:

Minimum CRC calculation time for divisor 256 = 10 x (256/2) = 1280 ms

2.2.3.4. Recovering from CRC Errors

The system that Intel MAX 10 resides in must control device reconfiguration. After
detecting an error on the CRC_ERROR pin, strobing the nCONFIG pin low directs the
system to perform reconfiguration at a time when it is safe for the system to
reconfigure the Intel MAX 10 device.

When the data bit is rewritten with the correct value by reconfiguring the device, the
device functions correctly.

While SEUs are uncommon in Intel FPGA devices, certain high-reliability applications
might require a design to account for these errors.

2.2.4. Configuration Data Compression

Intel MAX 10 devices can receive compressed configuration bitstream and decompress
the data in real-time during configuration. This feature helps to reduce the
configuration image size stored in the CFM. Data indicates that compression typically
reduces the configuration file size by at least 30% depending on the design.

Related Information

• Enabling Compression Before Design Compilation on page 48

• Enabling Compression After Design Compilation on page 49

Send Feedback

Intel® MAX® 10 FPGA Configuration User Guide

27

Power supplies including V

CCIO

, V

CCA

and V

CC

reach recommended operating voltage

nSTATUS and nCONFIG released high
CONF_DONE pulled low

CONF_DONE released high

Power Up

•
nSTATUS and CONF_DONE driven low

• All I/Os pins are tri-stated with no

pull up

• Clears configuration RAM bits

Reset

•

nSTATUS and CONF_DONE remain low

Initialization

• Initializes internal logic and registers

• Enables I/O buffers

Configuration Error Handling

• nSTATUS pulled low

• CONF_DONE remains low

• Restarts configuration if option
enabled

User Mode

Executes your design

Configuration

Writes configuration data to FPGA

• All I/Os pins are tri-stated with no pull up

• Samples CONFIG_SEL pin

Read ICB Settings

I/Os remain tri-stated or I/Os
become tri-stated with weak pull up
enabled (default)

POR Delay

Note:

1. Before an Intel MAX 10 device has been configured or CFM programmed for
the first time (such as a new device or a device that has been erased), the
weak pull up resistors will remain off during configuration.

(1)

2. Intel MAX 10 FPGA Configuration Schemes and Features

2.3. Configuration Details

2.3.1. Configuration Sequence

Figure 10. Configuration Sequence for Intel MAX 10 Devices

UG-M10CONFIG | 2020.11.05

You can initiate reconfiguration by pulling the nCONFIG pin low to at least the
minimum t

CONF_DONE pins are pulled low and all I/O pins are either tied to an internal weak

pull-up or tri-stated based on the ICB settings.

RU_nCONFIG

low-pulse width. When this pin is pulled low, the nSTATUS and

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Related Information

Generating .pof using Convert Programming Files on page 39

Provides more information about how to set the weak pull-up during configuration.

2.3.1.1. Power-up

If you power-up a device from the power-down state, you need to power the V

CCIO

for
bank 1B (bank 1 for 10M02 devices), bank 8 and the core to the appropriate level for
the device to exit POR. The Intel MAX 10 device enters the configuration stage after
exiting the power-up stage with a small POR delay.

Related Information

• Intel MAX 10 Power Management User Guide

Provides more information about power supply modes in Intel MAX 10 devices

• Intel MAX 10 Device Datasheet

Provides more information about the ramp-up time specifications.

• Intel MAX 10 FPGA Device Family Pin Connection Guideline

Provides more information about configuration pin connections.

2.3.1.1.1. POR Monitored Voltage Rails for Single-supply and Dual-supply Intel MAX 10 Devices

To begin configuration, the required voltages must be powered up to the appropriate
voltage levels as shown in the following table. The V

for bank 1B (bank 1 for

CCIO

10M02 devices) and bank 8 must be powered up to a voltage between 1.5V – 3.3V
during configuration.

Table 22. POR Monitored Voltage Rails for Single-supply and Dual-supply Intel MAX 10

Devices

There is no power-up sequence required when powering-up the voltages.

Power Supply Device Options

Single-supply Regulated V

Dual-supply V

Power Supply Monitored by POR

CC_ONE

V

CCA

V

V

CCIO

CCIO

bank 1B

bank 1B

(7)

and bank 8

CC

V

CCA

(7)

and bank 8

(7)

Bank 1 for 10M02 devices

Send Feedback

Intel® MAX® 10 FPGA Configuration User Guide

29

Time

POR trip level

Volts

POR Delay

Configuration
time

Device

Initialization

User Mode

t

RAMP

first power
supply

last
power
supply

nSTATUS

goes high

CONF_DONE

goes high

2. Intel MAX 10 FPGA Configuration Schemes and Features

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2.3.1.1.2. Monitored Power Supplies Ramp Time Requirement for Intel MAX 10 Devices

Figure 11. Monitored Power Supplies Ramp Time Requirement Diagram for Intel MAX 10

Devices

Table 23. Monitored Power Supplies Ramp Time Requirement for Intel MAX 10 Devices

Symbol Parameter Minimum Maximum Unit

t

RAMP

Power Supply Ramp Time

(8)

(9)

—

10 ms

2.3.1.2. Configuration

During configuration, configuration data is read from the internal flash and written to
the CRAM.

2.3.1.3. Configuration Error Handling

To restart configuration automatically, turn on the Auto-restart configuration after
error option in the General page of the Device and Pin Options dialog box in the

Intel Quartus Prime software.
If you do not turn on this option, you can monitor the nSTATUS pin to detect errors.

To restart configuration, pull the nCONFIG pin low for at least the duration of
t

RU_nCONFIG

.

2.3.1.4. Initialization

The initialization sequence begins after the CONF_DONE pin goes high. The
initialization clock source is from the internal oscillator and the Intel MAX 10 device
will receive enough clock cycles for proper initialization.

(8)

Ensure that all V

power supply reaches full rail before configuration completes. See

CCIO

Internal Configuration Time on page 12.

(9)

There is no absolute minimum value for the ramp rate requirement. Intel characterized the
minimum t

Intel® MAX® 10 FPGA Configuration User Guide

30

RAMP

of 200µs.

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2.3.1.5. User Mode

After the initialization completes, your design starts executing. The user I/O pins will
then function as specified by your design.

2.3.2. Intel MAX 10 Configuration Pins

All configuration pins and JTAG pins in Intel MAX 10 devices are dual-purpose pins.
The configuration pins function as configuration pins prior to user mode. When the
device is in user mode, they function as user I/O pins or remain as configuration pins.

Table 24. Configuration Pin Summary for Intel MAX 10 Devices

All pins are powered by V

Configuration Pin Input/Output Configuration Scheme

CRC_ERROR

CONFIG_SEL

DEV_CLRn

DEV_OE

CONF_DONE

nCONFIG

nSTATUS

JTAGEN

TCK

TDO

TMS

TDI

Bank 1B (bank 1 for 10M02 devices) and 8.

CCIO

Output only, open-drain Optional, JTAG and internal configurations

Input only Internal configuration

Input only Optional, JTAG and internal configurations

Input only Optional, JTAG and internal configurations

Bidirectional, open-drain JTAG and internal configurations

Input only JTAG and internal configurations

Bidirectional, open-drain JTAG and internal configurations

Input only Optional, JTAG configuration

Input only JTAG configuration

Output only JTAG configuration

Input only JTAG configuration

Input only JTAG configuration

Related Information

• Guidelines: Dual-Purpose Configuration Pin on page 32

• Enabling Dual-Purpose Pin on page 33

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3. Intel MAX 10 FPGA Configuration Design Guidelines

3.1. Dual-Purpose Configuration Pins

3.1.1. Guidelines: Dual-Purpose Configuration Pin

To use configuration pins as user I/O pins in user mode, you have to adhere to the
following guidelines.

Table 25. Dual-Purpose Configuration Pin Guidelines for Intel MAX 10 Devices

Guidelines Pins

Configuration pins during initialization:

• Tri-state the external I/O driver and drive an external pull-up resistor

• Use the external I/O driver to drive the pins to the state same as the external weak pull-up
resistor

JTAG pins:

• If you intend to switch back and forth between user I/O pins and JTAG pin functions using the

(10)

or

JTAGEN pin, all JTAG pins must be assigned as single-ended I/O pins or voltage-referenced I/O

pins. Schmitt trigger input is the recommended input buffer.

• JTAG pins cannot perform as JTAG pins in user mode if you assign any of the JTAG pin as a
differential I/O pin.

• You must use the JTAG pins as dedicated pins and not as user I/O pins during JTAG programming.

• Do not toggle JTAG pin during the initialization stage.

•

Put the test access port (TAP) controller in reset state by driving the TDI and TMS pins high and
toggle the TCK pin for at least 5 clock cycles before the initialization.

• The Signal Tap logic analyzer IP, JTAG-to-Avalon master bridge IP, and other JTAG-related IPs
cannot be used if you enable the JTAG pin sharing feature in your design.

•

nCONFIG

•

nSTATUS

•

CONF_DONE

•

TDO

•

TMS

•

TCK

•

TDI

Attention: Assign all JTAG pins as single-ended I/O pins or voltage-referenced I/O pins if you

enable JTAG pin sharing feature.

Related Information

• Intel MAX 10 FPGA Device Family Pin Connection Guidelines
Provides more information about recommended resistor values.

• Intel MAX 10 General Purpose I/O User Guide
Provides more information about Schmitt trigger input.

• Intel MAX 10 Configuration Pins on page 31

• JTAG Pins on page 5

(10)

If you intend to remove the external weak pull-up resistor, Intel recommends that you remove
it after the device enters user mode.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.

ISO
9001:2015
Registered

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3.1.1.1. JTAG Pin Sharing Behavior

Table 26. JTAG Pin Sharing Behavior for Intel MAX 10 Devices

Configuration Stage JTAG Pin Sharing

Disabled User I/O pin Dedicated JTAG pins.

User mode

Configuration Don’t Care Not used Dedicated JTAG pins.

Enabled

JTAGEN Pin JTAG Pins (TDO, TDI, TCK, TMS)

Driven low User I/O pins.

Driven high Dedicated JTAG pins.

Note: You have to set the pins according to Table 25 on page 32 and with correct pin

direction (input, output or bidirectional) for the JTAG pins work correctly.

3.1.2. Enabling Dual-Purpose Pin

To use the configuration and JTAG pins as user I/O in user mode, you must do the
following in the Intel Quartus Prime software:

1. On the Assignments menu, click Device. The Device dialog box appears.

2. In the Device dialog box, click Device and Pin Options. The Device and Pin
Options dialog box appears.

3. In the Device and Pin Option dialog box, select General from the category
pane.

4. In the Options list, do the following:

• Check the Enable JTAG pin sharing.

• Uncheck the Enable nCONFIG, nSTATUS, and CONF_DONE pins.

Note:

Unchecking this option allows the nCONFIG, nSTATUS, and CONF_DONE
pins to turn into user I/Os in user mode.

5. Click OK.

Related Information

• Intel MAX 10 Configuration Pins on page 31

• JTAG Pins on page 5

3.2. Configuring Intel MAX 10 Devices using JTAG Configuration

The Intel Quartus Prime software generates a .sof that you can use for JTAG
configuration. You can directly configure the Intel MAX 10 device by using a download
cable with the Intel Quartus Prime software programmer.

Alternatively, you can use the JAM Standard Test and Programming Language (STAPL)
Format File (.jam), JAM Byte Code File (.jbc), or Serial Vector Format (.svf) with
other third-party programming tools. You can either:

• Auto-generate these files

• Manually convert them using Intel Quartus Prime Programmer

Related Information

AN 425: Using the Command-Line Jam STAPL Solution for Device Programming

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3.2.1. Auto-Generating Configuration Files for Third-Party Programming Tools

To generate the third-party programming tool files, perform the following steps:

1. On the Assignments menu, click Settings. The Settings dialog box appears.

2. In the Category list, select Device. The Device page appears.

3. Click Device and Pin Options.

4. In the Device and Pin Options dialog box, select the Configuration Files from
the category pane.

5. Select the programming file you want to generate.

Note: The Intel Quartus Prime software generates two files for each optional

programming file you selected. For example:

•

<project_name>.jbc—This is the .sof equivalent file. Use this file to

perform JTAG configuration.

•

<project_name>_pof.jbc—This is the .pof equivalent file. Use this

file to perform Internal configuration.

6. Click OK once setting is completed.

3.2.2. Generating Third-Party Programming Files using Intel Quartus Prime Programmer

To convert a .sof or .pof file to .jam, .jbc, or .svf file, perform the following
steps:

1. On the Tools menu, click Programmer.

2. Click Add File and select the programming file and click Open.

3.

On the Intel Quartus Prime Programmer menu, select File ➤ Create/Update ➤

Create Jam, SVF, or ISC File.

4. In the File Format list, select the format you want to generate.

Note: The generated file name does not indicate whether it was converted from

a .sof or a .pof file. You can rename the generated file to avoid future
confusion.

Generating Third-Party Programming Files using Command Line

Alternatively, you can generate third-party programming files through command line.
Perform the following steps:

1.

Run the following command to generate .svf file with JTAG voltage of 3.3 V and
JTAG frequency of 10 MHz from .pof file without real-time ISP mode turned on.

quartus_cpf -c -q 10MHz -g 3.3 -n p <input_pof_file> <output_svf_file>

Similarly, JAM and JBC can be generated through the following command line.

quartus_cpf -c <input_pof_file> <output_jam/jbc_file>

Intel® MAX® 10 FPGA Configuration User Guide

34

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nSTATUS
CONF_DONE
nCONFIG

JTAGEN

TCK

TDO

TMS

TDI

10 kΩ 10 kΩ 10 kΩ

V

CCIO Bank 8

MAX 10

2
4
6
8

10

3
5
7
9

1

1 kΩ

V

CCIO Bank 1 or 1B

Download Cable

(JTAG Mode)

10-Pin Male Header

To use JTAGEN pin, you must enable the JTAG pin sharing.
In user mode, to use JTAG pins as:

- Regular I/O pins: Tie the JTAGEN pin to a weak 1-kΩ pull-down.

- Dedicated JTAG pins: Tie the JTAGEN pin to V

CCIO Bank 1B or 1B

through a 10-kΩ pull-up.

10 kΩ 10 kΩ

V

CCIO Bank 1 or 1B

The diodes and capacitors must be placed as close as possible to the Intel MAX 10 device. For effective voltage clamping, Intel recommends using the
Schottky diode, which has a relatively lower forward diode voltage than the switching and Zener diodes. See Preventing Voltage Overshoot.

10pF 10pF 10pF10pF

3. Intel MAX 10 FPGA Configuration Design Guidelines

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2.

Run the following command to generate .svf file with voltage of 3.3 V and JTAG
frequency of 10 MHz from .pof file with real-time ISP mode turned on.

quartus_cpf -c -q 10MHz -g 3.3 -n p <input_pof_file> <output_svf_file> -o
background_programming=on

Similarly, JAM and JBC can be generated through the following command line.

quartus_cpf -c <input_pof_file> <output_jam/jbc_file> -o
background_programming=on

For more information, run the following command to understand the details of
each option.

quartus_cpf --help=<option>

at which <option> can be jam, jbc, or svf.

3.2.3. JTAG Configuration Setup

Figure 12. Connection Setup for JTAG Single-Device Configuration using Download Cable

Connect to V

Bank 1 for 10M02 devices or V

CCIO

Bank 1B for all other Intel MAX 10 devices.

CCIO

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Intel® MAX® 10 FPGA Configuration User Guide

35

nSTATUS
CONF_DONE
nCONFIG

TCK

TDO

TMS

TDI

10 kΩ 10 kΩ 10 kΩ

V

CCIO Bank 8

MAX 10

nSTATUS
CONF_DONE
nCONFIG

TMS

TDI

MAX 10

nSTATUS
CONF_DONE
nCONFIG

TMS

TDI

MAX 10

TCK

TDO

TCK

TDO

2
4
6
8

10

3
5
7
9

1

Download Cable

(JTAG Mode)

10-Pin Male Header

1kΩ

Resistor value can vary from
1kΩ to 10kΩ. Perfrom signal
integrity analysis to select
resistor value for your setup.

V

CCIO Bank 1 or 1B

10 kΩ 10 kΩ 10 kΩ

V

CCIO Bank 8

10 kΩ 10 kΩ 10 kΩ

V

CCIO Bank 8

V

CCIO Bank 1 or 1B

The diodes and capacitors must be placed as close as possible to the Intel MAX 10 device. For effective voltage clamping, Intel recommends using the
Schottky diode, which has a relatively lower forward diode voltage than the switching and Zener diodes. See Preventing Voltage Overshoot.

10pF 10pF 10pF10pF

3. Intel MAX 10 FPGA Configuration Design Guidelines

UG-M10CONFIG | 2020.11.05

Figure 13. Connection Setup for JTAG Multi-Device Configuration using Download Cable

Connect to V

Bank 1 for 10M02 devices or V

CCIO

Bank 1B for all other Intel MAX 10 devices.

CCIO

To configure a device in a JTAG chain, the programming software sets the other
devices to bypass mode. A device in bypass mode transfers the programming data
from the TDI pin to the TDO pin through a single bypass register. The configuration

data is available on the TDO pin one clock cycle later.

The Intel Quartus Prime software uses the CONF_DONE pin to verify the completion of
the configuration process through the JTAG port:

•

CONF_DONE pin is low—indicates that the configuration has failed.

•

CONF_DONE pin is high—indicates that the configuration was successful.

After the configuration data is transmitted serially using the JTAG TDI port, the TCK
port is clocked to perform device initialization.

Preventing Voltage Overshoot

To prevent voltage overshoot, you must use external diodes and capacitors if
maximum AC voltage for both VCCIO and JTAG header exceed 3.9 V. However, Intel
recommends that you use the external diodes and capacitors if the supplies exceed

2.5 V.

JTAGEN

If you use the JTAGEN pin, Intel recommends the following settings:

• Once you entered user mode and JTAG pins are regular I/O pins—connect the

JTAGEN pin to a weak pull-down (1 kΩ).

Note:

Intel® MAX® 10 FPGA Configuration User Guide

36

• Once you entered user mode and JTAG pins are dedicated pins—connect the

JTAGEN pin to a weak pull-up (10 kΩ).

Intel recommends that you use three-pin header with a jumper or other switching
mechanism to change the JTAG pins behavior.

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3.2.4. ICB Settings in JTAG Configuration

The ICB settings are loaded into the device during .pof programming of the internal
configuration scheme. The .sof used during JTAG configuration programs the CRAM
only and does not contain ICB settings. The Intel Quartus Prime Programmer will

make the necessary setting based on the following:

• Device without ICB settings—ICB settings cleared from the internal flash or new
device

•

Device with ICB settings—prior ICB settings programmed using .pof

Devices without ICB Settings

For devices without ICB settings, the default value will be used. However, Intel
Quartus Prime Programmer disables the user watchdog timer by setting the Watchdog
Timer Enable bit to 0. This step is to avoid any unwanted reconfiguration from
occurring due to user watchdog timeout.

If the default ICB setting is undesired, you can program the desirable ICB setting first
by using .pof programming before doing the JTAG configuration.

Devices with ICB Settings

For device with ICB settings, the settings will be preserved until the internal flash is
erased. You can refer to the .map file to view the preserved ICB settings. JTAG
configuration will follow the preserved ICB setting and behave accordingly.

If the prior ICB setting is undesired, you can program the desirable ICB setting first by
using .pof programming before doing the JTAG configuration.

Related Information

• .pof and ICB Settings on page 38

• Verify Protect on page 22

• JTAG Secure Mode on page 22

• ISP and Real-Time ISP Instructions on page 10

• User Watchdog Timer on page 18

• Generating .pof using Convert Programming Files on page 39

Provides more information about setting the ICB during .pof generation using
Convert Programming File.

3.3. Configuring Intel MAX 10 Devices using Internal Configuration

There are three main steps for using internal configuration scheme for Intel MAX 10
devices:

1. Selecting the internal configuration scheme.

2.

Generating the .pof with ICB settings

3.

Programming the .pof into the internal flash

Related Information

• Internal Configuration Modes on page 6

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Intel® MAX® 10 FPGA Configuration User Guide

37

3. Intel MAX 10 FPGA Configuration Design Guidelines

• Remote System Upgrade on page 13

3.3.1. Selecting Internal Configuration Modes

To select the configuration mode, follow these steps:

1. Open the Intel Quartus Prime software and load a project using a Intel MAX 10
device.

2. On the Assignments menu, click Device. The Device dialog box appears.

3. In the Device dialog box, click Device and Pin Options. The Device and Pin
Options dialog box appears.

4. In the Device and Pin Option dialog box, click the Configuration tab.

5. In the Configuration Scheme list, select Internal Configuration.

6. In the Configuration Mode list, select 1 out of 5 configuration modes available.
The 10M02 devices has only 2 modes available.

7. Turn on Generate compressed bitstreams if needed.

8. Click OK.

3.3.2. .pof and ICB Settings

UG-M10CONFIG | 2020.11.05

There are two methods which the .pof will be generated and setting-up the ICB. The
internal configuration mode you selected will determine the corresponding method.

Table 27. .pof Generation and ICB Setting Method for Internal Configuration Modes

Internal Configuration Mode ICB Setting Description .pof Generation

Single Compressed Image ICB can be set in

Single Uncompressed Image

Single Compressed Image with Memory
Initialization.

Single Uncompressed Image with Memory
Initialization

Dual Compressed Images

Device and Pin
Options

ICB can be set
during Convert

Programming Files

task.

Intel Quartus Prime software
automatically generates
the .pof during project
compilation.

You need to generate the .pof
using Convert Programming

Files.

Method to Use

Auto­generated .pof

(11)

Generating .po

f using

Convert
Programming
Files

3.3.2.1. Auto-Generated .pof

To set the ICB for the auto-generated .pof, follow these steps:

1. On the Assignments menu, click Device. The Device dialog box appears.

2. In the Device dialog box, click Device and Pin Options. The Device and Pin
Options dialog box appears.

3. In the Device and Pin Option dialog box, select Configuration from the
category pane.

4. Click the Device Options … button.

(11)

Auto-generated .pof does not allow encryption. To enable the encryption feature in Single
Compressed and Single Uncompressed mode, use the Convert Programming Files method.

Intel® MAX® 10 FPGA Configuration User Guide

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5. The Max 10 Device Options dialog box allows you to set the following:

a. User I/Os weak pull up during configuration.

b. Verify Protect.

6. To automatically generate configuration files for third-party programming tools,
select the Programming Files from the category pane and select the format that
you want to generate.

Note: The Intel Quartus Prime software generates two files for each optional

programming file you selected. For example:

•

<project_name>.jbc—This is the .sof equivalent file. Use this file to

perform JTAG configuration.

•

<project_name>_pof.jbc—This is the .pof equivalent file. Use this

file to perform Internal configuration.

7. Click OK once setting is completed.

3.3.2.2. Generating .pof using Convert Programming Files

To convert .sof files to .pof files and to set the ICB, follow these steps:

1. On the File menu, click Convert Programming Files.

2.

Under Output programming file, select Programmer Object File (.pof) in the
Programming file type list.

3. In the Mode list, select Internal Configuration.

4. To set the ICB settings, click Option/Boot Info and the Max 10 Device Options
dialog box will appear. The Max 10 Device Options dialog box allows you to set
the following:

a. User I/Os weak pull up during configuration.

b. Configure device from CFM0 only.

Note: When you enable this feature, the device will always load the

configuration image 0 without sampling the physical CONFIG_SEL pin.
After successfully loading the configuration image 0, you can switch
between configuration image using the config_sel_overwrite bit of
the input register. Refer to related information for details about Dual
Configuration Intel FPGA IP input register.

c. Use secondary image ISP data as default setting when available.

d. JTAG Secure.

Note: The JTAG Secure feature will be disabled by default in Intel Quartus

Prime software. To make this option visible in the GUI, you must create
a quartus.ini file using the text editor, with the key-value pair:

PGM_ENABLE_MAX10_JTAG_SECURITY=ON and save the file in one of

the following folders:

• Project folder.

•

Windows operating system: <Quartus installation folder>

\bin64 folder.

•

Linux operating system: <Quartus installation folder>/

linux64 folder.

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Caution: Intel MAX 10 FPGA device would become permanently locked if you

enabled JTAG secure mode in the POF file and POF is encrypted with
the wrong key. You must instantiate the internal JTAG interface for
you unlock the external JTAG when the device is in JTAG Secure
mode.

e. Verify Protect.

f. Allow encrypted POF only.

g. Watchdog timer for dual configuration and watchdog timer value (Enabled

after adding 2 .sof page with two designs that compiled with Dual
Compressed Internal Images).

h. User Flash Memory settings.

i. RPD File Endianness

5. In the File name box, specify the file name for the programming file you want to
create.

6.

To generate a Memory Map File (.map), turn on Create Memory Map File (Auto
generate output_file.map). The .map contains the address of the CFM and UFM
with the ICB setting that you set through the Option/Boot Info option.

7.

To generate a Raw Programming Data (.rpd), turn on Create config data RPD
(Generate output_file_auto.rpd).

Separate Raw Programming Data (.rpd) for each configuration flash memory and
user flash memory (CFM0, CFM1, UFM) section will be generated together for
remote system upgrade purpose.

8.

The .sof can be added through Input files to convert list and you can add up
to two .sof files.

For remote system upgrade purpose, you can retain the original page 0 data in
the .pof, and replaces page 1 data with new .sof file. To perform this, you must
to add the .pof file in page 0, then add .sof page, then add the new .sof file to
page 1.

9. After all settings are set, click Generate to generate related programming file.

Related Information

• Intel MAX 10 User Flash Memory User Guide

Provides more information about On-Chip Flash Intel FPGA IP core.

• Encryption in Internal Configuration on page 52

Provides more information about internal configuration image loaded based on
various settings.

Intel® MAX® 10 FPGA Configuration User Guide

40

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3.3.2.3. Generating Third-Party Programming Files using Intel Quartus Prime Programmer

To convert a .sof or .pof file to .jam, .jbc, or .svf file, perform the following
steps:

1. On the Tools menu, click Programmer.

2. Click Add File and select the programming file and click Open.

3.

On the Intel Quartus Prime Programmer menu, select File ➤ Create/Update ➤

Create Jam, SVF, or ISC File.

4. In the File Format list, select the format you want to generate.

Note: The generated file name does not indicate whether it was converted from

a .sof or a .pof file. You can rename the generated file to avoid future
confusion.

Generating Third-Party Programming Files using Command Line

Alternatively, you can generate third-party programming files through command line.
Perform the following steps:

1.

Run the following command to generate .svf file with JTAG voltage of 3.3 V and
JTAG frequency of 10 MHz from .pof file without real-time ISP mode turned on.

quartus_cpf -c -q 10MHz -g 3.3 -n p <input_pof_file> <output_svf_file>

Similarly, JAM and JBC can be generated through the following command line.

quartus_cpf -c <input_pof_file> <output_jam/jbc_file>

2.

Run the following command to generate .svf file with voltage of 3.3 V and JTAG
frequency of 10 MHz from .pof file with real-time ISP mode turned on.

quartus_cpf -c -q 10MHz -g 3.3 -n p <input_pof_file> <output_svf_file> -o
background_programming=on

Similarly, JAM and JBC can be generated through the following command line.

quartus_cpf -c <input_pof_file> <output_jam/jbc_file> -o
background_programming=on

For more information, run the following command to understand the details of
each option.

quartus_cpf --help=<option>

at which <option> can be jam, jbc, or svf.

3.3.3. Programming .pof into Internal Flash

You can use the Intel Quartus Prime Programmer to program the .pof into the CFM
through JTAG interface. The Intel Quartus Prime Programmer also allows you to
program the UFM part of the internal flash.

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To program the .pof into the flash, follow these steps:

1. On the Tools menu, click Programmer.

2. In the Programmer window, click Hardware Setup and select USB Blaster in
the currently selected hardware drop down list.

3. In the Mode list, select JTAG.

4. Click Auto Detect button on the left pane.

5. Select the device to be programmed, and click Add File.

6.

Select the .pof to be programmed to the selected device.

7. There are several options in programming the internal flash:

— To program any of the CFM0/CFM1/CFM2 only, select the corresponding CFM in

the Program/Configure column.

— To program the UFM only, select the UFM in the Program/Configure column.

— To program the CFM and UFM only, select the CFM and UFM in the Program/

Configure column.

Note: ICB setting is preserved in this option. However, before the

programming starts, Intel Quartus Prime Programmer will make sure
the ICB setting in the device and the ICB setting in the selected .pof
are the same. If the ICB settings are different, Intel Quartus Prime
Programmer will overwrite the ICB setting.

— To program the whole internal flash including the ICB settings, select the

<yourpoffile.pof> in the Program/Configure column.

8. To enable the real-time ISP mode, turn-on the Enable real-time ISP to allow
background programming.

9. After all settings are set, click Start to start programming.

3.4. Implementing ISP Clamp in Intel Quartus Prime Software

To implement ISP clamp, you have to:

1.

Create a pin state information (.ips) file. The .ips file defines the state for all
the pins of the device when the device is in ISP clamp operation. You can use an
existing .ips file.

2.

Execute the .ips file.

Note:

Intel® MAX® 10 FPGA Configuration User Guide

42

You can use the .ips file created to program the device with any designs, provided
that it targets the same device and package. You must use the .ips file together with
a POF file.

Related Information

ISP Clamp on page 9

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3.4.1. Creating IPS File

To create an .ips file, perform the following steps:

1. Click Programmer on the toolbar, or on the Tools menu, click Programmer to
open the Programmer.

2. Click Add File in the programmer to add the programming file (POF, Jam, or JBC).

3. Click on the programming file (the entire row will be highlighted) and on the Edit
menu, click ISP CLAMP State Editor.

4. Specify the states of the pins in your design in the ISP Clamp State Editor. By
default, all pins are set to tri-state.

5. Click Save to save IPS file after making the modifications.

3.4.2. Executing IPS File

To execute ISP Clamp, perform the following steps:

1.

In the Quartus Prime Programmer, select the .pof you want to program to the
device.

2.

Select the .pof, right click and select Add IPS File and turn-on ISP CLAMP.

Note: You can change the start-up delay of the I/O Clamp after configuration. To

do this, select Tools ➤ Options, turn-on the Overwrite MAX10

configuration start up delay when using IO Clamp in Programmer

option, and change the delay value accordingly.

3.

Select the .pof in the Program/Configure column.

Note:

For third party programming, you can generate the .jam or .jbc file from
the .pof file with .ips file.

4. After all settings are set, click Start to start programming.

3.5. Accessing Remote System Upgrade through User Logic

The following example shows how the input and output ports of a WYSIWYG atom are
defined in the Intel MAX 10 device.

Note: WYSIWYG is a technique that performs optimization on the Verilog Quartus Mapping

netlist within the Intel Quartus Prime software.

fiftyfivenm_rublock <rublock_name>
(
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.captnupdt(<captnupdt source>),
.regin(<regin input source from the core>),
.rsttimer(<input signal to reset the watchdog timer>),
.rconfig(<input signal to initiate configuration>),
.regout(<data output destination to core>)
);
defparam <rublock_name>.sim_init_config = <initial configuration for simulation
only>;
defparam <rublock_name>.sim_init_watchdog_value = <initial watchdog value for
simulation only>;
defparam <rublock_name>.sim_init_config = <initial status register value for
simulation only>;

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43

Table 28. Port Definitions

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Port Input/

<rublock_name>

.clk(<clock source>)

.shiftnld(<shiftnld source>)

.captnupdt(<captnupdt source>)

.regin(<regin input source from
the core>)

.rsttimer(<input signal to reset
the watchdog timer>)

.rconfig(<input signal to
initiate configuration>)

.regout(<data output destination
to core>)

Output

Definition

- Unique identifier for the RSU Block. This is any identifier name
which is legal for the given description language (e.g. Verilog,
VHDL, AHDL, etc.). This field is required.

Input This signal designates the clock input of this cell. All operation of

this cell are with respect to the rising edge of this clock. Whether
it is the loading of the data into the cell or data out of the cell, it
always occurs on the rising edge. This field is required.

Input This signal is an input into the remote system upgrade block. If

shiftnld = 1, then data gets shifted from the internal shift

registers to the regout at each rising edge of clk and it gets
shifted into the internal shift registers from regin. This field is
required.

Input This signal is an input into the remote system upgrade block. This

controls the protocol of when to read the configuration mode or
when to write into the registers that control the configuration.
This field is required.

Input This signal is an input into the remote system upgrade block for

all data being loaded into the core. The data is shifted into the
internal registers at the rising edge of clk. This field is required

Input This signal is an input into the watchdog timer of the remote

update block. When this is high, it resets the watchdog timer. This
field is required.

Input This signal is an input into the configuration section of the remote

update block. When this signal goes high, it initiates a
reconfiguration. This field is required.

Output This is a 1 bit output which is the output of the internal shift

register updated every rising edge of .clk. The data coming out
depends on the control signals. This field is required.

Related Information

• Dual Configuration Intel FPGA IP Core References on page 62

• Remote System Upgrade on page 13

• AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the

Nios II Processor

Provides reference design for remote system upgrade in Intel MAX 10 FPGA
devices.

• I2C Remote System Update Example

This example demonstrates a remote system upgrade using the I2C protocol.

3.6. Error Detection

3.6.1. Verifying Error Detection Functionality

You can inject a soft error by changing the 32-bit CRC storage register in the CRC
circuitry. After verifying the failure induced, you can restore the 32-bit CRC value to
the correct CRC value using the same instruction and inserting the correct value. Be
sure to read out the correct value before updating it with a known bad value.

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In user mode, Intel MAX 10 devices support the CHANGE_EDREG JTAG instruction,
which allows you to write to the 32-bit storage register. You can use .jam to automate
the testing and verification process. You can only execute this instruction when the
device is in user mode. This instruction enables you to dynamically verify the CRC
functionality in-system without having to reconfigure the device. You can then switch
to use the CRC circuit to check for real errors induced by an SEU.

After the test completes, you can clear the CRC error and restore the original CRC
value using one of the following methods:

•

Bring the TAP controller to the RESET state by holding TMS high for five TCK clocks

• Power cycle the device

• Perform these steps:

1.

After the configuration completes, use CHANGE_EDREG JTAG instruction to
shift out the correct precomputed CRC value and load the wrong CRC value to
the CRC storage register. When an error is detected, the CRC_ERROR pin will
be asserted.

2.

Use CHANGE_EDREG JTAG instruction to shift in the correct precomputed CRC
value. The CRC_ERROR pin is de-asserted to show that the error detection CRC
circuitry is working.

Example 2. JAM File

'EDCRC_ERROR_INJECT

ACTION ERROR_INJECT = EXECUTE;
DATA DEVICE_DATA;
BOOLEAN out[32];
BOOLEAN in[32] = $02040608; 'shift in any wrong CRC value
ENDDATA;
PROCEDURE EXECUTE USES DEVICE_DATA;
BOOLEAN X = 0;
DRSTOP IDLE;
IRSTOP IDLE;
STATE IDLE;
IRSCAN 10, $015; 'shift in CHANGE_EDREG instruction
WAIT IDLE, 10 CYCLES, 1 USEC, IDLE;
DRSCAN 32, in[31..0], CAPTURE out[31..0];
WAIT IDLE, 10 CYCLES, 50 USEC, IDLE;
PRINT " ";
PRINT "Data read out from the Storage Register: "out[31], out[30], out[29],
out[28], out[27],
out[26], out[25], out[24], out[23], out[22], out[21], out[20], out[19],
out[18], out[17], out[16], out[15], out[14], out[13], out[12], out[11],
out[10], out[9], out[8], out[7], out[6], out[5], out[4], out[3],
out[2], out[1], out[0]; 'Read out correct precomputed CRC value
PRINT " ";
STATE IDLE;
EXIT 0;
ENDPROC;

You can run the .jam file using quartus_jli executable with the following command
line:

quartus_jli -c<cable index> -a<action name> <filename>.jam

Related Information

• SEU Mitigation and Configuration Error Detection on page 24

• AN 425: Using the Command-Line Jam STAPL Solution for Device Programming

Send Feedback

Provides more information about quartus_jli command line executable.

Intel® MAX® 10 FPGA Configuration User Guide

45

3.6.2. Enabling Error Detection

The CRC error detection feature in the Intel Quartus Prime software generates the

CRC_ERROR output to the optional dual-purpose CRC_ERROR pin.

To enable the error detection feature using CRC, follow these steps:

1. Open the Intel Quartus Prime software and load a project using Intel MAX 10
device family.

2. On the Assignments menu, click Device. The Device dialog box appears.

3. In the Device dialog box, click Device and Pin Options. The Device and Pin
Options dialog box appears.

4. Click Device and Pin Option. The Device and Pin Option dialog box appears.

5. In the Device and Pin Option dialog box, select Error Detection CRC from the
category pane.

6. Turn on Enable Error Detection CRC_ERROR pin.

7. In the Divide error check frequency by field, enter a valid divisor.

The divisor value divides down the frequency of the configuration oscillator output
clock. This output clock is used as the clock source for the error detection process.

8. Click OK.

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Related Information

SEU Mitigation and Configuration Error Detection on page 24

3.6.3. Accessing Error Detection Block Through User Logic

The error detection circuit stores the computed 32-bit CRC signature in a 32-bit
register. The user logic from the core reads out this signature. The

fiftyfivenm_crcblock primitive is a WYSIWYG component used to establish the

interface from the user logic to the error detection circuit. The

fiftyfivenm_crcblock primitive atom contains the input and output ports that

must be included in the atom. To access the logic array,you must insert the

fiftyfivenm_crcblock WYSIWYG atom into your design. The recommended clock

frequency of .clk port is to follow the clock frequency of EDCRC block.

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Clock Divider

(1 to 256 Factor)

Pre-Computed CRC

(Saved in the Option Register)

CRC

Computation

Error Detection

Logic

SRAM

Bits

CRC_ERROR

(Shown in BIDIR Mode)

VCC

Logic Array

CLK

SHIFTNLD

LDSRC

REGOUT

CRC_ERROR

Internal Chip Oscillator

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Figure 14. Error Detection Block Diagram with Interfaces for Intel MAX 10 Devices

The following example shows how the input and output ports of a WYSIWYG atom are
defined in the Intel MAX 10 device.

fiftyfivenm_crcblock <name>
(
.clk(<ED_CLK clock source>),
.shiftnld(<ED_SHIFTNLD source>),
.ldsrc (<LDSRC source>),
.crcerror(<CRCERROR_CORE out destination>),
.regout(<output destination>)
);
defparam <crcblock_name>.oscillator_divider = <internal oscillator division (1
to 256)>;

Table 29. Port Definitions

Port Input/

<crcblock_name>

.clk(<clock source>

.shiftnld (<shiftnld
source>)

.ldsrc (<ldsrc
source>)

Output

Input This signal designates the clock input of this cell. All operations of this cell are

Input

Input

Definition

— Unique identifier for the CRC block and represents any identifier name that is

legal for the given description language such as Verilog HDL, VHDL, AHDL. This
field is required.

with respect to the rising edge of the clock. Whether it is the loading of the data
into the cell or data out of the cell, it always occurs on the rising edge. This port
is required.

This signal is an input into the error detection block. If shiftnld=1, the data is
shifted from the internal shift register to the regout at each rising edge of clk. If

shiftnld=0, the shift register parallel loads either the pre-calculated CRC value

or the update register contents depending on the ldsrc port input. This port is
required.

This signal is an input into the error detection block. If ldsrc=0, the pre­computed CRC register is selected for loading into the 32-bit shift register at the
rising edge of clk when shiftnld=0. Ifldsrc=1, the signature register (result

continued...

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Port Input/

.crcerror (<crcerror
out destination>)

.regout (<output
destination>)

Output

of the CRC calculation) is selected for loading into the shift register at the rising
edge of clk when shiftnld=0. This port is ignored when shiftnld=1. This
port is required.

Output This signal is the output of the cell that is synchronized to the internal oscillator

of the device (100-MHz or 80-MHz internal oscillator) and not to the clk port. It
asserts automatically high if the error block detects that a SRAM bit has flipped
and the internal CRC computation has shown a difference with respect to the
pre-computed value. This signal must be connected either to an output pin or a
bidirectional pin. If it is connected to an output pin, you can only monitor the

CRC_ERROR pin (the core cannot access this output). If the CRC_ERROR signal is

used by core logic to read error detection logic, this signal must be connected to
a BIDIR pin. The signal is fed to the core indirectly by feeding a BIDIR pin that
has its oe port connected to VCC.

Output This signal is the output of the error detection shift register synchronized to the

clk port, to be read by core logic. It shifts one bit at each cycle. User should

clock the clk signal 31 cycles to read out the 32 bits of the shift register. The
values at the .regout port are an inversion of the actual values.

Related Information

• SEU Mitigation and Configuration Error Detection on page 24

• Error Detection Timing on page 25

3.7. Enabling Data Compression

When you enable compression, the Intel Quartus Prime software generates
configuration files with compressed configuration data.

Definition

A compressed configuration file is needed to use the dual configuration mode in the
internal configuration scheme. This compressed file reduces the storage requirements
in internal flash memory, and decreases the time needed to send the bitstream to the
Intel MAX 10 device family. There are two methods to enable compression for the Intel
MAX 10 device family bitstreams in the Intel Quartus Prime software:

• Before design compilation—using the Compiler Settings menu.

• After design compilation—using the Convert Programming Files option.

3.7.1. Enabling Compression Before Design Compilation

To enable compression before design compilation, follow these steps:

1. On the Assignments menu, click Device. The Device dialog box appears.

2. Click Device and Pin Options. The Device and Pin Options dialog box appears.

3. In the Device and Pin Option dialog box, select Configuration from the
category pane.

4. Turn on Generate compressed bitstreams.

5. Click OK.

6. In the Settings dialog box, click OK.

Related Information

Configuration Data Compression on page 27

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3.7.2. Enabling Compression After Design Compilation

To enable compression after design compilation, follow these steps:

1. On the File menu, click Convert Programming Files.

2. Under Output programming file, from the Programming file type pull-down
menu, select your desired file type.

3. If you select the Programmer Object File (.pof), you must specify a configuration
device, directly under the file type.

4. In the Input files to convert box, select SOF Data.

5. Click Add File to browse to the Intel MAX 10 device family .sof.

6. In the Convert Programming Files dialog box, select the .pof you added to SOF
Data and click Properties.

7. In the SOF Properties dialog box, turn on the Compression option.

Related Information

Configuration Data Compression on page 27

3.8. AES Encryption

This section covers detailed guidelines on applying AES Encryption for design security.
There are two main steps in applying design security in Intel MAX 10 devices. First is
to generate the encryption key programming (.ekp) file and second is to program

the .ekp file into the device.

The .ekp file has other different formats, depending on the hardware and system
used for programming. There are three file formats supported by the Intel Quartus
Prime software:

•

JAM Byte Code (.jbc) file

•

•

™

JAM

Standard Test and Programming Language (STAPL) Format (.jam) file

Serial Vector Format (.svf) file

Only the .ekp file type generated automatically from the Intel Quartus Prime
software. You must create the .jbc, .jam and .svf files using the Intel Quartus
Prime software if these files are required in the key programming.

Note:

Intel recommends that you keep the .ekp file confidential.

3.8.1. Generating .ekp File and Encrypt Configuration File

To generate the .ekp file and encrypt your configuration file, follow these steps:

1. On the File menu, click Convert Programming Files.

2.

Under Output programming file, select Programmer Object File (.pof) in the
Programming file type list.

3. In the Mode list, select Internal Configuration.

4. Click Option/Boot Info and the ICB setting dialog box will appear.

5. You can enable the Allow encrypted POF only option. Click OK once ICB setting
is set.

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The device will only accept encrypted bitstream during internal configuration if this
option is enabled. If you encrypt one of CFM0, CFM1 or CFM2 only, the
Programmer will post a warning.

6. Type the file name in the File name field, or browse to and select the file.

7. Under the Input files to convert section, click SOF Data.

8. Click Add File to open the Select Input File dialog box.

9.

Browse to the unencrypted .sof and click Open.

10.

Under the Input files to convert section, click on the added .sof.

11. Click Properties and the SOF Files Properties: Bitstream Encryption dialog
box will appear.

12. Turn on Generate encrypted bitstream.

13.

Turn on Generate key programming file and type the .ekp file path and file
name in the text area, or browse to and select <filename>.ekp.

14.

You can the key with either a .key file or entering the key manually.

Note: Intel MAX 10 devices require the entry of 128-bit keys.

—

Adding key with a .key file.
The .key file is a plain text file in which each line represents a key unless the

line starts with "#". The "#" symbol is used to denote comments. Each valid
key line has the following format:

<key identity><white space><128-bit hexadecimal key>
# This is an example key file
key1 0123456789ABCDEF0123456789ABCDEF

a. Enable the Use key file checkbox.

b.

Click Open and add the desired .key file and click Open again.

c.

Under Key entry part, the key contained in the .key file will be selected
in the drop-down list.

d. Click OK.

— Entering your key manually.

a. Under Key entry part, click the Add button.

b. Select the Key Entry Method to enter the encryption key either with the

On-screen Keypad or Keyboard.

c. Enter a key name in the Key Name (alphanumeric) field.

d. Key in the desired key in the Key (128-bit hexadecimal) field and

repeat in the Confirm Key field below it.

e. Click OK.

15. Read the design security feature disclaimer. If you agree, turn on the
acknowledgment box and click OK.

16.

In the Convert Programming Files dialog box, click OK. The <filename>.ekp
and encrypted configuration file will be generated in the same project directory.

Note:

For dual configuration .pof file, both .sof file need to be encrypted with
the same key.The generation of key file and encrypted configuration file will
not be successful if different keys are used.

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3.8.2. Generating .jam/.jbc/.svf file from .ekp file

To generate .jam/.jbc/.svf file from .ekp file, follow these steps:

1. On the Tools menu, click Programmer and the Programmer dialog box will
appear.

2. In the Mode list, select JTAG as the programming mode.

3. Click Hardware Setup. The Hardware Setup dialog box will appear.

4. Select USBBlaster as the programming hardware in the currently selected
hardware list and click Done.

5. Click Add File and the Select Programmer File dialog box will appear.

6.

Type <filename>.ekp in the File name field and click Open.

7. Select the .ekp file you added and click Program/Configure.

8. On the File menu, point to Create/Update and click Create JAM, SVF, or ISC
File. The Create JAM, SVF, or ISC File dialog box will appear.

9.

Select the file format required for the .ekp file in the File format field.

—

JEDEC STAPL Format (.jam)

—

Jam STAPL Byte Code (.jbc)

—

Serial Vector Format (.svf)

10. Type the file name in the File name field, or browse to and select the file.

11.

Click OK to generate the .jam, .jbc or .svf file.

3.8.3. Programming .ekp File and Encrypted POF File

There are two methods to program the encrypted .pof and .ekp files:

•

Program the .ekp and .pof separately.

Note:

You only can program the .ekp and .pof separately when Allow
encrypted POF only option is disabled.

•

Integrate the .ekp into .pof and program both altogether.

3.8.3.1. Programming .ekp File and Encrypted .pof Separately

To program the .ekp and encrypted .pof separately using the Intel Quartus Prime
software, follow these steps:

1. In the Intel Quartus Prime Programmer, under the Mode list, select JTAG as the
programming mode.

2. Click Hardware Setup and the Hardware Setup dialog box will appear.

3. Select USBBlaster as the programming hardware in the Currently selected
hardware list and click Done.

4. Click Add File and the Select Programmer File dialog box will appear.

5.

Type <filename>.ekp in the File name field and click Open.

6.

Select the .ekp file you added and click Program/Configure.

7. Click Start to program the key.

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Note: The Intel Quartus Prime software message window provides information

about the success or failure of the key programming operation. Once
the .ekp is programmed, .pof can be programmed separately. To retain
the security key in the internal flash that had been programmed through
the .ekp, continue with the following steps.

8.

Select the .pof to be programmed to the selected device.

9. Check only the functional block that need to be updated at child level for CFM and
UFM. Do not check operation at the parent level when using Programmer GUI.

10. After all settings are set, click Start to start programming.

3.8.3.2. Integrate the .ekp into .pof Programming

To integrate the .ekp into .pof and program both altogether using the Intel Quartus
Prime software, follow these steps:

1. In the Intel Quartus Prime Programmer, under the Mode list, select JTAG as the
programming mode.

2. Click Hardware Setup and the Hardware Setup dialog box will appear.

3. Select USBBlaster as the programming hardware in the Currently selected
hardware list and click Done.

4. Click the Auto Detect button on the left pane.

5.

Select the .pof you want to program to the device.

6.

Select the <yourpoffile.pof>, right click and select Add EKP File to
integrate .ekp file with the .pof file.

Once the .ekp is integrated into the .pof, you can to save the integrated .pof
into a new .pof. This newly saved file will have original .pof integrated
with .ekp information.

7.

Select the <yourpoffile.pof> in the Program/Configure column.

8. After all settings are set, click Start to start programming

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3.8.4. Encryption in Internal Configuration

During internal configuration, the FPGA decrypts the .pof with the stored key and
uses the decrypted data to configure itself. The configuration image loaded during
configuration is also affected by the encryption settings and the Configure device

from CFM0 only setting.

Table 30. Configuration Image Outcome Based on Encryption Settings, Encryption Key

and CONFIG_SEL Pin Settings

Table shows the scenario when you disable the Configure device from CFM0 only. Key X and Key Y are
security keys included in your device and configuration image.

Configuratio

n Image

Mode

Single Not Encrypted Not Available No key Disabled 0 image 0

Single Not Encrypted Not Available No key Disabled 1 image 0

Single Not Encrypted Not Available Key X Disabled 0 image 0

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CFM0 (image 0)

Encryption Key

CFM1 (image 1)

Encryption Key

Key Stored

in the Device

Allow

Encrypted

POF Only

CONFIG_SEL

pin

Design Loaded

After Power-up

continued...

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Configuratio

n Image

Mode

CFM0 (image 0)

Encryption Key

CFM1 (image 1)

Encryption Key

Key Stored

in the Device

Allow

Encrypted

POF Only

CONFIG_SEL

pin

Design Loaded

After Power-up

Single Not Encrypted Not Available Key X Disabled 1 image 0

Single Not Encrypted Not Available Key X Enabled 0 Configuration Fail

Single Not Encrypted Not Available Key X Enabled 1 Configuration Fail

Single Key X Not Available No key Enabled 0 Configuration Fail

Single Key X Not Available No key Enabled 1 Configuration Fail

Single Key X Not Available Key X Enabled 0 image 0

Single Key X Not Available Key X Enabled 1 image 0

Single Key X Not Available Key Y Enabled 0 Configuration Fail

Single Key X Not Available Key Y Enabled 1 Configuration Fail

Dual Not Encrypted Not Encrypted No key Disabled 0 image 0

Dual Not Encrypted Not Encrypted No key Disabled 1 image 1

Dual Key X Not Encrypted No key Disabled 0 image 1

Dual Key X Not Encrypted No key Disabled 1 image 1

Dual Key X Not Encrypted Key X Disabled 0 image 0

Dual Key X Not Encrypted Key X Disabled 1 image 1

Dual Key X Not Encrypted Key X Enabled 0 image 0

Dual Key X Not Encrypted Key X Enabled 1 image 0

Dual Key X Not Encrypted Key Y Enabled 0 Configuration Fail

Dual Key X Not Encrypted Key Y Enabled 1 Configuration Fail

Dual Key X Key X No key Enabled 0 Configuration Fail

Dual Key X Key X No key Enabled 1 Configuration Fail

Dual Key X Key X Key X Enabled 0 image 0

Dual Key X Key X Key X Enabled 1 image 1

Dual Key X Key Y Key X Enabled 0 image 0

Dual Key X Key Y Key X Enabled 1 image 0

Dual Key Y Key Y Key Y Enabled 0 image 0

Dual Key Y Key Y Key Y Enabled 1 image 1

Dual Key X Key Y Key Y Enabled 0 image 1

Dual Key X Key Y Key Y Enabled 1 image 1

(12)

(13)

(12)

(12)

After image 0 configuration failed, device will automatically load image 1.

(13)

After image 1 configuration failed, device will automatically load image 0.

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Table 31. Configuration Image Outcome Based on Encryption Settings and Encryption

Key

Table shows the scenario when you enable the Configure device from CFM0 only.

CFM0 (image 0) Encryption

Key

Not Encrypted No key Disabled image 0

Not Encrypted Key X Disabled image 0

Not Encrypted Key Y Disabled image 0

Not Encrypted No key Enabled Configuration Fail

Not Encrypted Key X Enabled Configuration Fail

Not Encrypted Key Y Enabled Configuration Fail

Key X No key Disabled Configuration Fail

Key X Key X Disabled image 0

Key X Key Y Disabled Configuration Fail

Key X No key Enabled Configuration Fail

Key X Key X Enabled image 0

Key X Key Y Enabled Configuration Fail

Key Y No key Disabled Configuration Fail

Key Y Key X Disabled Configuration Fail

Key Y Key Y Disabled image 0

Key Y No key Enabled Configuration Fail

Key Y Key X Enabled Configuration Fail

Key Y Key Y Enabled image 0

Key Stored in the

Device

Allow Encrypted POF Only Design Loaded After Power-

up

Related Information

Generating .pof using Convert Programming Files on page 39

3.9. Intel MAX 10 JTAG Secure Design Example

This design example demonstrates the instantiation of the JTAG WYSIWYG atom and
the example of user logic implementation in the Intel Quartus Prime software to
execute the LOCK and UNLOCK JTAG instructions. This design example is targeted for
Intel MAX 10 devices with the JTAG Secure Mode enabled.

Related Information

• JTAG Instruction Availability on page 23

• Configuration Flash Memory Permissions on page 23

• JTAG Secure Design Example

Intel® MAX® 10 FPGA Configuration User Guide

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JTAG

Control Block

TDI

TMS

TCK

TDO

Core Interface

Internal JTAG

TDICORE

TMSCORE

TCKCORE

TDOCORE

CORECTL

I/O Interface

External JTAG

TDI
TMS
TCK

TDO

External

JTAG Pins

JTAG WYSIWYG Interface

JTAG WYSIWYG Atom

TDI
TMS
TCK

TDO

3. Intel MAX 10 FPGA Configuration Design Guidelines

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3.9.1. Internal and External JTAG Interfaces

There are two interfaces to access the JTAG control block in Intel MAX 10 devices:

• External JTAG interface—connection of the JTAG control block from the physical

JTAG pins; TCK, TDI, TDO, and TMS.

• Internal JTAG interface—connection of the JTAG control block from the internal
FPGA core fabric.

You can only access the JTAG control block using either external or internal JTAG
interface one at a time. External JTAG interfaces are commonly used for JTAG
configuration using programming cable. To access the internal JTAG interface, you
must include the JTAG WYSIWYG atom in your Intel Quartus Prime software design.

Figure 15. Internal and External JTAG Interface Connections

Note: To ensure the internal JTAG interfaces of Intel MAX 10 devices function correctly, all

four JTAG signals (TCK, TDI, TMS and TDO) in the JTAG WYSIWYG atom need to be
routed out. The Intel Quartus Prime software will automatically assign the ports to
their corresponding dedicated JTAG pins.

3.9.2. JTAG WYSIWYG Atom for JTAG Control Block Access Using Internal JTAG Interface

The following example shows how the input and output ports of a JTAG WYSIWYG
atom are defined in the Intel MAX 10 device.

fiftyfivenm_jtag <name>
(
.tms(),

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Intel® MAX® 10 FPGA Configuration User Guide

55

.tck(),
.tdi(),
.tdoutap(),
.tdouser(),
.tdicore(),
.tmscore(),
.tckcore(),
.corectl(),
.tdo(),
.tmsutap(),
.tckutap(),
.tdiutap(),
.shiftuser(),
.clkdruser(),
.updateuser(),
.runidleuser(),
.usr1user(),
.tdocore(),
.ntdopinena()
);

Table 32. Port Description

Ports Input/Output Functions

<name>

.corectl()

.tckcore()

.tdicore()

.tmscore()

.tdocore()

.tck()

.tdi()

.tms()

.tdo()

.clkdruser()

.runidleuser()

.shiftuser()

.tckutap()

.tdiutap()

.tdouser()

.tdoutap()

.tmsutap()

Input Active high input to the JTAG control block to enable the internal JTAG

Input

Input

Input

Output

Input

Input

Input

Output

Input/Output

3. Intel MAX 10 FPGA Configuration Design Guidelines

UG-M10CONFIG | 2020.11.05

— Identifier for the Intel MAX 10 JTAG WYSIWYG atom and represents any

identifier name that is legal for the given description language, such as
Verilog HDL, VHDL, and AHDL.

access from core interface. When the FPGA enters user mode after
configuration, this port is low by default. Pulling this port to logic high
will enable the internal JTAG interface (with external JTAG interface
disabled at the same time) and pulling this port to logic low will disable
the internal JTAG interface (with external JTAG interface enabled at the
same time).

Core tck signal

Core tdi signal

Core tms signal

Core tdo signal

Pin tck signal

Pin tdi signal

Pin tms signal

Pin tdo signal

These ports are not used for enabling the JTAG Secure mode using the
internal JTAG interface, you can leave them unconnected.

continued...

Intel® MAX® 10 FPGA Configuration User Guide

56

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Start

Enable the Internal JTAG
Interface, corectl = 1

Shift the JTAG Instruction
to the TDI Core.

start_unlock or

start_lock

= 1?

no

yes

End of Instruction

Length?

no

yes

Move the TAP Controller
State Machine from the
RESET State to the
SHIFT_IR State by
Controlling the TMS Core.

Move the TAP Controller
State Machine from the
SHIFT_IR State to the
IDLE State.

End

3. Intel MAX 10 FPGA Configuration Design Guidelines

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Ports Input/Output Functions

.updateuser()

.usr1user()

.ntdopinena()

3.9.3. Executing LOCK and UNLOCK JTAG Instructions

When you configure this reference design into a Intel MAX 10 device with the JTAG
Secure mode enabled, the device is in JTAG Secure mode after power-up and
configuration.

To disable the JTAG Secure mode, trigger the start_unlock port of the user logic to
issue the UNLOCK JTAG instruction. After the UNLOCK JTAG instruction is issued, the
device exits from JTAG secure mode. When the JTAG Secure mode is disabled, you can

choose to full-chip erase the internal flash of Intel MAX 10 device to disable the JTAG
Secure mode permanently.

The start_lock port in the user logic triggers the execution of the LOCK JTAG
instruction. Executing this instruction enables the JTAG Secure mode of the Intel MAX
10 device.

Figure 16. LOCK or UNLOCK JTAG Instruction Execution

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Intel® MAX® 10 FPGA Configuration User Guide

57

3. Intel MAX 10 FPGA Configuration Design Guidelines

Table 33. Input and Output Port of the User Logic

UG-M10CONFIG | 2020.11.05

Port Input/

clk_in

start_lock

start_unlock

jtag_core_en_out

tck_out

tdi_out

tms_out

indicator

Output

Input Clock source for the user logic. The f

Input

Input

Output

Output Output to the JTAG WYSIWYG atom. This port is connected to the

Output Output to the JTAG WYSIWYG atom. This port is connected to the

Output Output to the JTAG WYSIWYG atom. This port is connected to the

Output

timing closure analysis. You need to apply timing constraint and perform
timing analysis on the path to determine the f

Triggers the execution of the LOCK JTAG instruction to the internal JTAG
interface. Pulse signal high for at least 1 clock cycle to trigger.

Triggers the execution of the UNLOCK JTAG instruction to the internal JTAG
interface. Pulse signal high for at least 1 clock cycle to trigger.

Output to the JTAG WYSIWYG atom. This port is connected to the corectl
port of the JTAG WYSIWYG atom to enable the internal JTAG interface.

tck_core port of the JTAG WYSIWYG atom.

tdi_core port of the JTAG WYSIWYG atom.

tms_core port of the JTAG WYSIWYG atom.

Logic high of this output pin indicates the completion of the LOCK or

UNLOCK JTAG instruction execution.

3.9.4. Verifying the JTAG Secure Mode

You can verify whether your device has successfully entered or exited JTAG secure
mode by executing a non-mandatory JTAG instruction.

Function

of the user logic depends on the

MAX

.

MAX

Note: You must instantiate the internal JTAG interface for you unlock the external JTAG when

the device is in JTAG Secure mode.

When you enable the JTAG Secure option, the Intel MAX 10 device will be in the JTAG
Secure mode after power-up. To validate the JTAG Secure feature in your design
example, perform these steps:

1.

Configure the reference design .pof file into the device with JTAG Secure mode
enabled. After power cycle, the device should be in JTAG Secure mode.

2. You can ensure that the device enters user mode successfully by observing one of
the following:

—

CONFDONE pin goes high

—

counter_output pin starts toggling

3.

Issue the PULSE_NCONFIG JTAG instruction using the external JTAG pins to
reconfigure the device. You can use the pulse_ncfg.jam file attached in the
design example. To execute the pulse_ncfg.jam file, you can use the
quartus_jli or the JAM player. You can ensure that the device does not reconfigure

by observing one of the following:

—

CONFDONE pin stays high

—

counter_output pin continues toggling

Intel® MAX® 10 FPGA Configuration User Guide

58

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3. Intel MAX 10 FPGA Configuration Design Guidelines

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Unsuccessful reconfiguration verifies that the device is currently in JTAG Secure
mode.

4.

Pull the start_unlock port of the user logic to logic high to execute the UNLOCK
JTAG instruction.

The indicator port goes high after the UNLOCK JTAG instruction is complete.

5.

Issue the PULSE_NCONFIG JTAG instruction using the external JTAG pins to
reconfigure the device. You can ensure that the device reconfigures successfully
by observing one of the following:

—

CONFDONE pin is low

—

counter_output pin stops toggling

Successful reconfiguration verifies that the device is currently not in JTAG Secure
mode.

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59

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4. Intel MAX 10 FPGA Configuration IP Core Implementation Guides

Related Information

• Introduction to Intel FPGA IP Cores

Provides general information about all Intel FPGA IP cores, including
parameterizing, generating, upgrading, and simulating IP cores.

• Creating Version-Independent IP and Qsys Simulation Scripts

Create simulation scripts that do not require manual updates for software or IP
version upgrades.

• Project Management Best Practices

Guidelines for efficient management and portability of your project and IP files.

4.1. Unique Chip ID Intel FPGA IP Core

This section provides the guideline to implement the Unique Chip ID Intel FPGA IP
core.

Related Information

• Unique Chip ID on page 21

• Unique Chip ID Intel FPGA IP Core Ports on page 65

4.1.1. Instantiating the Unique Chip ID Intel FPGA IP Core

To instantiate the Unique Chip ID Intel FPGA IP core, follow these steps:

1. On the Tools menu of the Intel Quartus Prime software, click IP Catalog.

2. Under the Library category, expand the Basic Functions and Configuration
Programming.

3. Select Unique Chip Intel FPGA IP and click Add, and enter your desired output
file name

4. In the Save IP Variation dialog box:

— Set your IP variation filename and directory.

— Select IP variation file type.

5. Click Finish.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.

ISO
9001:2015
Registered

4. Intel MAX 10 FPGA Configuration IP Core Implementation Guides

UG-M10CONFIG | 2020.11.05

4.1.2. Resetting the Unique Chip ID Intel FPGA IP Core

To reset the Unique Chip ID Intel FPGA IP core, you must assert high to the reset
signal for at least one clock cycle. After you de-assert the reset signal, the Unique
Chip ID Intel FPGA IP core re-reads the unique chip ID of your device from the fuse ID
block. The Unique Chip ID Intel FPGA IP core asserts the data_valid signal after
completing the operation.

4.2. Dual Configuration Intel FPGA IP Core

This section provides the guideline to implement the Dual Configuration Intel FPGA IP
core.

4.2.1. Instantiating the Dual Configuration Intel FPGA IP Core

To instantiate the Dual Configuration Intel FPGA IP Core, follow these steps:

1. On the Tools menu of the Intel Quartus Prime software, click IP Catalog.

2. Under the Library category, expand the Basic Functions and Configuration
Programming.

3. Select Dual Configuration Intel FPGA IP and after clicking Add, the IP
Parameter Editor appears.

4. In the New IP Instance dialog box:

— Set the top-level name of your IP.

— Select the Device family.

— Select the Device

5. Click OK.

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5. Dual Configuration Intel FPGA IP Core References

Related Information

• Dual Configuration Intel FPGA IP Core on page 19

• Accessing Remote System Upgrade through User Logic on page 43

• AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the

Nios II Processor

Provides reference design for remote system upgrade in Intel MAX 10 FPGA
devices.

• I2C Remote System Update Example

This example demonstrates a remote system upgrade using the I2C protocol.

5.1. Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map

Table 34. Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map

for Intel MAX 10 Devices

•

Intel recommends you to set the reserve bits to 0 for write operations. For read operations, the IP core
will always generate 0 as the output.

•

Write 1 to trigger any operation stated in the description.

• You need to trigger the desired operation from offset 2 before any read operation of offset 4, 5, 6 and 7.

Offset

0 W 32 • Bit 0—trigger reconfiguration.

1 W 32 •

2 W 32 • Bit 0—trigger read operation from the user watchdog.

R/W Width

(Bits)

• Bit 1—reset the watchdog timer.

• Bit 31:2—reserved.
Signals are triggered at the same write cycle on Avalon.

Bit 0—trigger config_sel_overwrite to the input register.

•

Bit 1—writes config_sel to the input register. Set 0 or 1 to load from
configuration image 0 or 1 respectively.

• Bit 31:2—reserved.
The busy signal is generated right after the write cycle, while the configuration

image information is registered. Once busy signal is high, writing to this address
is ignored until the process is completed and the busy signal is de-asserted.

• Bit 1—trigger read operation from the previous state application 1 register.

• Bit 2—trigger read operation from the previous state application 2 register.

• Bit 3—trigger read operation from the input register.

• Bit 31:4—reserved.
The busy signal is generated right after the write cycle. These bits are not one-

hot. Multiple bits can be set to 1 at the same time to trigger the read operation
from multiple registers.

Description

continued...

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.

ISO
9001:2015
Registered

5. Dual Configuration Intel FPGA IP Core References

UG-M10CONFIG | 2020.11.05

Offset R/W Width

3 R 32 •

4

5 R 32 • Bit 3:0—previous state application 1 reconfiguration source value from the

6 R 32 • Bit 3:0—previous state application 2 reconfiguration source value from the

7 R 32 •

R 32 • Bit 11:0—user watchdog value.

(Bits)

Bit 0—IP busy signal.

• Bit 31:1—reserved.
The busy signal indicates that the Dual Configuration Intel FPGA IP core is in the

writing or reading process. In this state, all write operation requests to the
remote system upgrade block registers are ignored except for triggering the
reset timer. Intel recommends you to poll this busy signal once you trigger any
read or write process. The busy signal will not stay high for more than 531 clock
cycles in each single operation triggered.

• Bit 12—current state of the user watchdog.

•

Bit 16:13—msm_cs value of the current state.

• Bit 31:17—reserved.

Remote System Upgrade Status Register—Previous State Bit for Intel MAX 10
Devices table.

•

Bit 7:4—msm_cs value of the previous state application 1.

• Bit 31:8—reserved.

Remote System Upgrade Status Register—Previous State Bit for Intel MAX 10
Devices table.

•

Bit 7:4—msm_cs value of the previous state application 2.

• Bit 31:8—reserved.

Bit 0—config_sel_overwrite value from the input register.

•

Bit 1—config_sel value of the input register.

• Bit 31:2—reserved.

Description

(14)

(15)

Related Information

• Dual Configuration Intel FPGA IP Core on page 19

• Avalon Interface Specifications
Provides more information about the Avalon memory-mapped interface
specifications applied in Dual Configuration Intel FPGA IP core.

• Instantiating the Dual Configuration Intel FPGA IP Core on page 61

• Remote System Upgrade Status Registers on page 18
The Remote System Upgrade Status Register—Previous state bit for Intel MAX
10 Devices table provides more information about previous state applications
reconfiguration sources.

(14)

You can only read the 12 most significant bit of the 29 bit user watchdog value using Dual
Configuration IP Core.

(15)

Reads the config_sel of the input register only. It will not reflect the physical CONFIG_SEL
pin setting.

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5. Dual Configuration Intel FPGA IP Core References

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5.2. Dual Configuration Intel FPGA IP Core Parameters

Table 35. Dual Configuration Intel FPGA IP Core Parameter for Intel MAX 10

Parameter Value Description

Clock frequency Up to 80 MHz

Specifies the number of cycle to assert RU_nRSTIMER and RU_nCONFIG signals.
Note that maximum RU_CLK is 40 MHz, the Dual Configuration Intel FPGA IP
core has restriction to run at 80 MHz maximum, which is twice faster than
hardware limitation. This is because the Dual Configuration Intel FPGA IP core
generates RU_CLK at half rate of the input frequency.

Intel® MAX® 10 FPGA Configuration User Guide

64

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6. Unique Chip ID Intel FPGA IP Core References

6.1. Unique Chip ID Intel FPGA IP Core Ports

Table 36. Unique Chip ID Intel FPGA IP Core Ports

Port Input/Output Width (Bits) Description

clkin

reset

data_valid

chip_id

Input 1 • Feeds clock signal to the unique chip ID block. The

maximum supported frequency is 100 MHz.

• When you provide a clock signal, the IP core reads the
value of the unique chip ID and sends the value to the

chip_id output port.

Input 1 •

Output 1 • Indicates that the unique chip ID is ready for retrieval. If

Output 64 • Indicates the unique chip ID according to its respective

Resets the IP core when you assert the reset signal to
high for at least one clock cycle.

•

The chip_id [63:0]output port holds the value of the
unique chip ID until you reconfigure the device or reset
the IP core.

the signal is low, the IP core is in initial state or in
progress to load data from a fuse ID.

• After the IP core asserts the signal, the data is ready for
retrieval at the chip_id[63..0] output port.

fuse ID location. The data is only valid after the IP core
asserts the data_valid signal.

•

The value at power-up resets to 0.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.

ISO
9001:2015
Registered

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7. Document Revision History for the Intel MAX 10 FPGA Configuration User Guide

Document

Version

2020.11.05 Updated the guidelines for JTAG pins in table Dual-Purpose Configuration Pin Guidelines for Intel MAX
10 Devices.

2020.06.30 • Updated Table: Configuration Flash Memory Programming Time for Sectors in Intel MAX 10 Devices

to include a footnote for 10M02.

• Added specifications for 10M02SCU324 device in the following tables:

— Internal Configuration Time for Intel MAX 10 Devices (Uncompressed .rbf)
— Internal Configuration Time for Intel MAX 10 Devices (Compressed .rbf)

• Updated Table: Cyclic Redundancy Check Calculation Time for Intel® MAX® 10 Devices to include

specification for device 10M02SCU324.

• Updated topic Generating Third-Party Programming Files using Command Line with commands to

generate JAM and JBC.

2019.12.23 Updated Table: ICB Values and Descriptions for Intel MAX 10 Devices to correct the default watchdog
timer value from 0x1FFF to 0xFFF.

2019.10.07 Updated the description about generating third-party programming files using command line for

Generating Third-Party Programming Files using Intel Quartus Prime Programmer in the Configuring
Intel MAX 10 Devices using JTAG Configuration and Configuring Intel MAX 10 Devices using Internal
Configuration sections.

2019.06.14 • Added guideline for JTAG pin sharing feature in Table: Dual-Purpose Configuration Pin Guidelines for

Intel MAX 10 Devices.

• Renamed sections to Internal and External JTAG Interfaces and JTAG WYSIWYG Atom for JTAG

Control Block Access Using Internal JTAG Interface under the section Intel MAX 10 JTAG Secure
Design Example.

• Updated Figure: Internal and External JTAG Interface Connections to correct external JTAG pin

directions, remove ports from internal JTAG block, and add labels for JTAG WYSIWYG atom, JTAG
WYSIWYG interface, and external JTAG pins.

• Added description that offset 2 bits are not one-hot and description for offset 3 on busy signal

deassertion in Table: Dual Configuration Intel FPGA IP Core Avalon-MM Address Map for Intel MAX
10 Devices.

2019.04.30 Updated Table: Dual Configuration Intel FPGA IP Core Avalon-MM Address Map for Intel MAX 10
Devices to correct the offset 2 descriptions for bits 1 and 2.

Changes

continued...

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.

ISO
9001:2015
Registered

7. Document Revision History for the Intel MAX 10 FPGA Configuration User Guide

UG-M10CONFIG | 2020.11.05

Document

Version

2019.01.07 • Updated the steps in following topics:
— Enabling Dual-purpose Pin
— Selecting Internal Configuration Modes
— Auto-Generated .pof
— Generating .pof using Convert Programming Files
— Programming .pof into Internal Flash
— Enabling Error Detection
— Enabling Compression Before Design Compilation
— Enabling Compression After Design Compilation

• Updated the note in step 4b in Generating .pof using Convert Programming Files.

• Added a note in Accessing Remote System Upgrade through User Logic.

• Renamed the following IP core names as per Intel rebranding:
— "Altera Dual Configuration IP core" to "Dual Configuration Intel FPGA IP"
— "Altera Unique Chip ID IP core" to "Unique Chip ID Intel FPGA IP"

2018.10.29 • Updated Table: ICB Values and Descriptions for Intel MAX 10 Devices to update the footnote for

2018.06.01 Added 1 as valid value for n in Minimum and Maximum Error Detection Frequencies for Intel MAX 10

2018.02.12

JTAG Secure feature.

• Updated the description in User Watchdog Timer.

• Updated the note for JTAG Secure option in Generating .pof using Convert Programming Files.

• Updated the description of step 5 in Generating .ekp File and Encrypt Configuration File.

• Added a note in step 4 in Enabling Dual-purpose Pin.

• Updated Figure: Configuration Sequence for Intel MAX 10 Devices to add a Read ICB Settings block
and a note for the Read ICB Settings block.

• Updated Table: Dual-Purpose Configuration Pin Guidelines for Intel MAX 10 Devices to update the
guidelines for JTAG pins.

• Updated Figure: Connection Setup for JTAG Single-Device Configuration using Download Cable.

Devices table.

Added steps to generate third-party programming tool files (.jbc, .jam, and .svf).

Changes

Date Version Changes

July 2017 2017.07.20 • Updated CFM term to configuration flash memory in High-Level

June 2017 2017.06.15 Updated methods to clear the CRC error and restore the original CRC value

April 2017 2017.04.06 Updated Auto-recofigure from secondary image when initial image fails

February 2017 2017.02.21 Rebranded as Intel.

October 2016 2016.10.31 • Updated Voltage Overshoot Prevention description.

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Overview of JTAG Configuration and Internal Configuration for MAX 10
Devices figure.

• Added BST definition that is boundary-scan test.

in Verifying Error Detection Functionality.

(enabled by default) option to Configure device from CFM0 only reflecting
user interface update.

• Updated note in Connection Setup for JTAG Single-Device Configuration

using Download Cable and Connection Setup for JTAG Multi-Device
Configuration using Download Cable figures.

• Added steps to implement ISP clamp feature.

• Updated Configuration Flash Memory Sectors Utilization for all Intel
MAX 10 with Analog and Flash Feature Options figure to include UFM
sectors.

continued...

Intel® MAX® 10 FPGA Configuration User Guide

67

7. Document Revision History for the Intel MAX 10 FPGA Configuration User Guide

UG-M10CONFIG | 2020.11.05

Date Version Changes

May 2016 2016.05.13 • Changed instances of Standard POR to Slow POR to reflect Intel

Quartus Prime GUI.

• Updated t

•

Corrected file type from .ekp to .pof in Step 8 of Programming .ekp

CFG

to t

RU_nCONFIG

.

File and Encrypted .pof Separately.

• Corrected Use secondary image ISP data as default setting when
available description in ICB Values and Descriptions for Intel MAX 10
Devices table.

• Corrected CFM programming time.

• Added note on JTAG pin requirements when using JTAG pin sharing.

• Moved JTAG Pin Sharing Behavior under Guidelines: Dual-Purpose
Configuration Pin.

• Updated configuration sequence diagram by moving 'Clears
configuration RAM bits from Power-up state to Reset state.

•

Corrected error detection port input and output for <crcblock_name>
from input to none.

• Added example of remote system upgrade access through user
interface and port definitions.

• Removed preliminary terms for Error Detection Frequency and Cyclic
Redundancy Check Calculation Timing.

• Added Connection Setup for JTAG Multi-Device Configuration using
Download Cable diagram.

• Updated Connection Setup for JTAG Single-Device Configuration using
Download Cable diagram.

• Added new JTAG Secure design example.

• Edited Remote System Upgrade section title by removing in Dual Image
Configuration.

• Updated Monitored Power Supplies Ramp Time Requirement for MAX 10
Devices table.

• Added Internal Configuration Time.

• Removed Instant ON feature.

• Updated User Flash Memory instances to additional UFM in

Configuration Flash Memory Sectors Utilization for all MAX 10 with
Analog and Flash Feature Options figure.

December

2015.12.14 • Updated ICB setting description for Set I/O to weak pull-up prior
usermode option to state the weak pull-up is enabled during
configuration.

• Removed Accessing the Remote System Upgrade Block Through User

Interface.

• Added input and output port definition for error detection WYSIWYG
atom.

• Updated the I/O pin state to be dependent on ICB bit setting during
reconfiguration.

November 2015 2015.11.02 • Removed JRunner support for JTAG configuration and link to AN 414.

• Updated differences in supported internal configuration mode supported
based on device feature options in a table.

• Removed maximum number of compressed configuration image table
do to redundancy.

• Updated Initialization Configuration Bits setting and description to
reflect Quartus Prime 15.1 update.

• Updated Enable JTAG pin sharing and Enable nCONFIG, nSTATUS,
and CONF_DONE pins to reflect Quartus II 15.1 update.

• Added information about ISP clamp feature.

• Updated information about steps to generate Raw Programming Data
(.rpd).

• Renamed section title from Configuration Total Flash Memory
Programming Time to Configuration Flash Memory Programming Time.

continued...

Intel® MAX® 10 FPGA Configuration User Guide

68

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7. Document Revision History for the Intel MAX 10 FPGA Configuration User Guide

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Date Version Changes

• Renamed table title from Configuration Total Flash Memory
Programming Time for Sectors in Intel MAX 10 Devices to Configuration
Flash Memory Programming Time for Sectors in Intel MAX 10 Devices.

• Added note to Configuration Flash Memory Programming Time for
Sectors in Intel MAX 10 Devices table.

• Added information about internal JTAG interface and accessing internal
JTAG block through user interface.

• Added Intel MAX 10 JTAG Secure design example.

June 2015 2015.06.15 • Added related information link to AN 741: Remote System Upgrade for

May 2015 2015.05.04 • Rearranged and updated Configuration Setting names 'Initialization

December 2014

2014.12.15 • Rename BOOT_SEL pin to CONFIG_SEL pin.

MAX 10 FPGA Devices over UART with the Nios II Processor in Altera

Dual Configuration IP Core References and Remote System Upgrade in
Dual Compressed Images.

•

Added pulse holding requirement time for RU_nRSTIMER in Remote
System Upgrade Circuitry Signals for Intel MAX 10 Devices table.

• Added link to Remote System Upgrade Status Register—Previous State

Bit for Intel MAX 10 Devices table for related entries in Altera Dual
Configuration IP Core Avalon-MM Address Map for Intel MAX 10 Devices

table.

Configuration Bits for MAX 10 Devices' table.

• Updated 'High-Level Overview of Internal Configuration for MAX 10
Devices' figure with JTAG configuration and moved the figure to
'Configuration Schemes' section.

• Added link to corresponding description of configuration settings in
'Initialization Configuration Bits for MAX 10 Devices' table.

• Updated the default watchdog time value from hexadecimal to decimal
value in 'Initialization Configuration Bits for MAX 10 Devices' table.

• Updated the ISP data description in 'Initialization Configuration Bits for
MAX 10 Devices' table.

• Updated 'User Watchdog Timer' by adding time-out formula.

• Added link to 'User Watchdog Internal Circuitry Timing Specifications' in
MAX 10 FPGA Device Datasheet.

• Added footnote to indicate that JTAG secure is disabled by default and
require Altera support to enable in 'Initialization Configuration Bits for
MAX 10 Devices' table.

• Updated minimum and maximum CRC calculation time for divisor 2.

• Updated remote system upgrade flow diagram.

• Updated 'Encryption in Internal Configuration' table by adding 'Key'
terms and changed Image 1 and Image 2 to Image 0 and Image 1
respectively.

• Added footnote to 'Encryption in Internal Configuration' to indicate
auto-reconfiguration when image fails.

• Added formula to calculate minimum and maximum CRC calculation
time for other than divisor 2.

• Added caution when JTAG Secure is turned on.

• Added information about auto-generated .pof for certain type of
internal configuration modes.

• Added .pof and ICB setting guide through Device and Pin Options and
convert programming file.

• Added configuration RAM (CRAM) in 'Overview'

• Editorial changes.

• Update Altera IP Core name from Dual Boot IP Core to Altera Dual
Configuration IP Core.

• Added information about the AES encryption key part of ICB.

continued...

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Intel® MAX® 10 FPGA Configuration User Guide

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7. Document Revision History for the Intel MAX 10 FPGA Configuration User Guide

Date Version Changes

• Added encryption feature guidelines.

• Updated ICB settings options available in 14.1 release.

• Updated Programmer options on CFM programming available in 14.1
release.

September 2014 2014.09.22 Initial release.

UG-M10CONFIG | 2020.11.05

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