Intel MAX 10 FPGA User Manual
Intel® MAX® 10 FPGA Configuration
User Guide
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Contents
Contents
1. Intel® MAX® 10 FPGA Configuration Overview................................................................ 4
2. Intel MAX 10 FPGA Configuration Schemes and Features...............................................5
2.1. Configuration Schemes..........................................................................................5
2.1.1. JTAG Configuration.................................................................................... 5
2.1.2. Internal Configuration................................................................................ 6
2.2. Configuration Features.........................................................................................13
2.2.1. Remote System Upgrade...........................................................................13
2.2.2. Configuration Design Security....................................................................20
2.2.3. SEU Mitigation and Configuration Error Detection........................................ 24
2.2.4. Configuration Data Compression................................................................ 27
2.3. Configuration Details............................................................................................ 28
2.3.1. Configuration Sequence............................................................................ 28
2.3.2. Intel MAX 10 Configuration Pins................................................................. 31
3. Intel MAX 10 FPGA Configuration Design Guidelines.....................................................32
3.1. Dual-Purpose Configuration Pins............................................................................ 32
3.1.1. Guidelines: Dual-Purpose Configuration Pin................................................. 32
3.1.2. Enabling Dual-Purpose Pin.........................................................................33
3.2. Configuring Intel MAX 10 Devices using JTAG Configuration....................................... 33
3.2.1. Auto-Generating Configuration Files for Third-Party Programming Tools...........34
3.2.2. Generating Third-Party Programming Files using Intel Quartus Prime
Programmer............................................................................................34
3.2.3. JTAG Configuration Setup..........................................................................35
3.2.4. ICB Settings in JTAG Configuration............................................................. 37
3.3. Configuring Intel MAX 10 Devices using Internal Configuration...................................37
3.3.1. Selecting Internal Configuration Modes....................................................... 38
3.3.2. .pof and ICB Settings............................................................................... 38
3.3.3. Programming .pof into Internal Flash..........................................................41
3.4. Implementing ISP Clamp in Intel Quartus Prime Software......................................... 42
3.4.1. Creating IPS File...................................................................................... 43
3.4.2. Executing IPS File.................................................................................... 43
3.5. Accessing Remote System Upgrade through User Logic.............................................43
3.6. Error Detection....................................................................................................44
3.6.1. Verifying Error Detection Functionality........................................................ 44
3.6.2. Enabling Error Detection........................................................................... 46
3.6.3. Accessing Error Detection Block Through User Logic..................................... 46
3.7. Enabling Data Compression...................................................................................48
3.7.1. Enabling Compression Before Design Compilation.........................................48
3.7.2. Enabling Compression After Design Compilation........................................... 49
3.8. AES Encryption....................................................................................................49
3.8.1. Generating .ekp File and Encrypt Configuration File...................................... 49
3.8.2. Generating .jam/.jbc/.svf file from .ekp file................................................. 51
3.8.3. Programming .ekp File and Encrypted POF File.............................................51
3.8.4. Encryption in Internal Configuration........................................................... 52
3.9. Intel MAX 10 JTAG Secure Design Example..............................................................54
3.9.1. Internal and External JTAG Interfaces.........................................................55
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3.9.2. JTAG WYSIWYG Atom for JTAG Control Block Access Using Internal JTAG
Interface.................................................................................................55
3.9.3. Executing LOCK and UNLOCK JTAG Instructions........................................... 57
3.9.4. Verifying the JTAG Secure Mode.................................................................58
4. Intel MAX 10 FPGA Configuration IP Core Implementation Guides............................... 60
4.1. Unique Chip ID Intel FPGA IP Core......................................................................... 60
4.1.1. Instantiating the Unique Chip ID Intel FPGA IP Core..................................... 60
4.1.2. Resetting the Unique Chip ID Intel FPGA IP Core.......................................... 61
4.2. Dual Configuration Intel FPGA IP Core.................................................................... 61
4.2.1. Instantiating the Dual Configuration Intel FPGA IP Core.................................61
5. Dual Configuration Intel FPGA IP Core References....................................................... 62
5.1. Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map................62
5.2. Dual Configuration Intel FPGA IP Core Parameters....................................................64
6. Unique Chip ID Intel FPGA IP Core References............................................................. 65
6.1. Unique Chip ID Intel FPGA IP Core Ports................................................................. 65
7. Document Revision History for the Intel MAX 10 FPGA Configuration User Guide......... 66
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1. Intel® MAX® 10 FPGA Configuration Overview
You can configure Intel® MAX® 10 configuration RAM (CRAM) using the following
configuration schemes:
• JTAG configuration—using JTAG interface.
• Internal configuration—using internal flash.
Supported Configuration Features
Table 1. Configuration Schemes and Features Supported by Intel MAX 10 Devices
Configuration Scheme
JTAG configuration — — — Yes
Internal configuration Yes Yes Yes Yes
Remote System
Upgrade
Compression Design Security SEU Mitigation
Related IP Cores
• Dual Configuration Intel FPGA IP—used in the remote system upgrade feature.
• Unique Chip ID Intel FPGA IP—retrieves the chip ID of Intel MAX 10 devices.
Related Information
• Intel MAX 10 FPGA Configuration Schemes and Features on page 5
Provides information about the configuration schemes and features.
• Intel MAX 10 FPGA Configuration Design Guidelines on page 32
Provides information about using the configuration schemes and features.
• Unique Chip ID Intel FPGA IP Core on page 21
• Dual Configuration Intel FPGA IP Core on page 19
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
CRAM
Intel MAX 10 Device
JTAG In-System Programming
Configuration
Flash Memory
Configuration Data
Internal
Configuration
JTAG Configuration
.sof
.pof
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2. Intel MAX 10 FPGA Configuration Schemes and Features
2.1. Configuration Schemes
Figure 1. High-Level Overview of JTAG Configuration and Internal Configuration for
Intel MAX 10 Devices
2.1.1. JTAG Configuration
In Intel MAX 10 devices, JTAG instructions take precedence over the internal
configuration scheme.
Using the JTAG configuration scheme, you can directly configure the device CRAM
through the JTAG interface—TDI, TDO, TMS, and TCK pins. The Intel Quartus
software automatically generates an SRAM Object File (.sof). You can program
the .sof using a download cable with the Intel Quartus Prime software programmer.
Related Information
Configuring Intel MAX 10 Devices using JTAG Configuration on page 33
Provides more information about JTAG configuration using download cable with
Intel Quartus Prime software programmer.
2.1.1.1. JTAG Pins
Table 2. JTAG Pin
Pin Function Description
TDI
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
Serial input pin for: •
TDI is sampled on the rising edge of TCK
•
TDI pins have internal weak pull-up resistors.
®
Prime
continued...
ISO
9001:2015
Registered
2. Intel MAX 10 FPGA Configuration Schemes and Features
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Pin Function Description
• instructions
• boundary-scan test (BST) data
• programming data
TDO
TMS
TCK
Serial output pin for:
• instructions
• boundary-scan test data
• programming data
Input pin that provides the control signal to
determine the transitions of the TAP
controller state machine.
Clock input to the BST circuitry. —
•
TDO is sampled on the falling edge of TCK
• The pin is tri-stated if data is not shifted out of the
device.
•
TMS is sampled on the rising edge of TCK
•
TMS pins have internal weak pull-up resistors.
All the JTAG pins are powered by the V
1B. In JTAG mode, the I/O pins support the
CCIO
LVTTL/LVCMOS 3.3-1.5V standards.
Related Information
• Intel MAX 10 Device Datasheet
Provides more information about supported I/O standards in Intel MAX 10
devices.
• Guidelines: Dual-Purpose Configuration Pin on page 32
• Enabling Dual-Purpose Pin on page 33
2.1.2. Internal Configuration
You need to program the configuration data into the configuration flash memory (CFM)
before internal configuration can take place. The configuration data to be written to
CFM will be part of the programmer object file (.pof). Using JTAG In-System
Programming (ISP), you can program the .pof into the internal flash.
During internal configuration, Intel MAX 10 devices load the CRAM with configuration
data from the CFM.
2.1.2.1. Internal Configuration Modes
Table 3. Supported Internal Configuration Modes Based on Intel MAX 10 Feature
Options
Intel MAX 10 Feature Options Supported Internal Configuration Mode
Compact
Flash and Analog
• Single Compressed Image
• Single Uncompressed Image
• Dual Compressed Images
• Single Compressed Image
• Single Compressed Image with Memory Initialization
• Single Uncompressed Image
• Single Uncompressed Image with Memory Initialization
Note:
In dual compressed images mode, you can use the CONFIG_SEL pin to select the
configuration image.
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Configuration Flash Memory SectorsUser Flash Memory Sectors
CFM0UFM0UFM1 CFM1CFM2
Dual Compressed Image
Single Uncompressed Image
Single Uncompressed Image
with Memory Initialization
Single Compressed Image
with Memory Initialization
Single Compressed Image
Compressed
Image 0
Compressed
Image 0
Uncompressed Image 0 with Memory Initialization
Compressed Image 0 with Memory Initialization
Uncompressed Image 0
Compressed Image 1
Additional UFM
UFM
UFM
UFM
UFM
UFM Additional UFM
Internal Configuration
Mode
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Related Information
• Configuring Intel MAX 10 Devices using Internal Configuration on page 37
• Remote System Upgrade on page 13
2.1.2.2. Configuration Flash Memory
The CFM is a non-volatile internal flash that is used to store configuration images. The
CFM may store up to two compressed configuration images, depending on the
compression and the Intel MAX 10 devices. The compression ratio for the configuration
image should be at least 30% for the device to be able store two configuration
images.
Related Information
Configuration Flash Memory Permissions on page 23
2.1.2.2.1. Configuration Flash Memory Sectors
All CFM in Intel MAX 10 devices consist of three sectors, CFM0, CFM1, and CFM2
except for the 10M02. The sectors are programmed differently depending on the
internal configuration mode you select.
The 10M02 device consists of only CFM0. The CFM0 sector in 10M02 devices is
programmed similarly when you select single compressed image or single
uncompressed image.
Figure 2. Configuration Flash Memory Sectors Utilization for all Intel MAX 10 with
Analog and Flash Feature Options
Unutilized CFM1 and CFM2 sectors can be used for additional user flash memory (UFM).
Related Information
CFM and UFM Array Size
Provides more information about UFM and CFM sector sizes.
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2.1.2.2.2. Configuration Flash Memory Programming Time
Table 4. Configuration Flash Memory Programming Time for Sectors in Intel MAX 10
Devices
Note: The programming time reflects JTAG interface programming time only without any system
Device
(1)
10M02
10M04 and 10M08 6.5 4.6 11.1
10M16 12.0 8.9 20.8
10M25 16.4 12.6 29.0
10M40 and 10M50 30.2 22.7 52.9
overhead. It does not reflect the actual programming time that you face. To compensate the
system overhead, Intel Quartus Prime Programmer is enhanced to utilize flash parallel mode
during device programming for Intel MAX 10 10M04/08/16/25/40/50 devices. The 10M02
device does not support flash parallel mode, you may experience a relatively slow
programming time if compare to other device.
In-System Programming Time (s)
CFM2 CFM1 CFM0
— — 5.4
2.1.2.3. In-System Programming
You can program the internal flash including the CFM of Intel MAX 10 devices with ISP
through industry standard IEEE 1149.1 JTAG interface. ISP offers the capability to
program, erase, and verify the CFM. The JTAG circuitry and ISP instructions for Intel
MAX 10 devices are compliant to the IEEE-1532-2002 programming specification.
During ISP, the Intel MAX 10 receives the IEEE Std. 1532 instructions, addresses, and
data through the TDI input pin. Data is shifted out through the TDO output pin and
compared with the expected data.
The following are the generic flow of an ISP operation:
1. Check ID—the JTAG ID is checked before any program or verify process. The time
required to read this JTAG ID is relatively small compared to the overall
programming time.
2. Enter ISP—ensures the I/O pins transition smoothly from user mode to the ISP
mode.
3. Sector Erase—shifting in the address and instruction to erase the device and
applying erase pulses.
4. Program—shifting in the address, data, and program instructions and generating
the program pulse to program the flash cells. This process is repeated for each
address in the internal flash sector.
5. Verify—shifting in addresses, applying the verify instruction to generate the read
pulse, and shifting out the data for comparison. This process is repeated for each
internal flash address.
6. Exit ISP—ensures that the I/O pins transition smoothly from the ISP mode to the
user mode.
(1)
The CFM0 programming time for the 10M02SCU324 device is 11.1 s.
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You can also use the Intel Quartus Prime Programmer to program the CFM.
Related Information
Programming .pof into Internal Flash on page 41
Provides the steps to program the .pof using Intel Quartus Prime Programmer.
2.1.2.3.1. ISP Clamp
When a normal ISP operation begins, all I/O pins are tri-stated. For situations when
the I/O pins of the device should not be tri-stated when the device is in ISP operation,
you can use the ISP clamp feature.
When the ISP clamp feature is used, you can set the I/O pins to tri-state, high, low, or
sample and sustain. The Intel Quartus Prime software determines the values to be
scanned into the boundary-scan registers of each I/O pin, based on your settings. This
will determine the state of the pins to be clamped to when the device programming is
in progress.
Before clamping the I/O pins, the SAMPLE/PRELOAD JTAG instruction is first executed
to load the appropriate values to the boundary-scan registers. After loading the
boundary-scan registers with the appropriate values, the EXTEST instruction is
executed to clamp the I/O pins to the specific values loaded into the boundary-scan
registers during SAMPLE/PRELOAD.
If you choose to sample the existing state of a pin and hold the pin to that state when
the device enters ISP clamp mode, you must ensure that the signal is in steady state.
A steady state signal is needed because you cannot control the sample set-up time as
it depends on the TCK frequency as well as the download cable and software. You
might not capture the correct value when sampling a signal that toggles or is not
static for long periods of time.
Related Information
Implementing ISP Clamp in Intel Quartus Prime Software on page 42
2.1.2.3.2. Real-Time ISP
In a normal ISP operation, to update the internal flash with a new design image, the
device exits from user mode and all I/O pins remain tri-stated. After the device
completes programing the new design image, it resets and enters user mode.
The real-time ISP feature updates the internal flash with a new design image while
operating in user mode. During the internal flash programming, the device continues
to operate using the existing design. After the new design image programming
process completes, the device will not reset. The new design image update only takes
effect in the next reconfiguration cycle.
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2.1.2.3.3. ISP and Real-Time ISP Instructions
Table 5. ISP and Real-Time ISP Instructions for Intel MAX 10 Devices
Instruction Instruction Code Description
CONFIG_IO 00 0000 1101
PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration
ISC_ENABLE_HIZ
ISC_ENABLE_CLAMP
(2)
(2)
10 1100 1100
10 0011 0011
ISC_DISABLE 10 0000 0001
(3)
(3)
(3)
(3)
10 1111 0100
10 0001 0000
10 0000 0011
10 1111 0010
ISC_PROGRAM
ISC_NOOP
ISC_ADDRESS_SHIFT
ISC_ERASE
• Allows I/O reconfiguration through JTAG ports using the
IOCSR for JTAG testing. This is executed after or during
configurations.
•
nSTATUS pin must go high before you can issue the
CONFIG_IO instruction.
even though the physical pin is unaffected.
• Puts the device in ISP mode, tri-states all I/O pins, and drives
all core drivers, logic, and registers.
•
Device remains in the ISP mode until the ISC_DISABLE
instruction is loaded and updated.
•
The ISC_ENABLE instruction is a mandatory instruction. This
requirement is met by the ISC_ENABLE_CLAMP or
ISC_ENABLE_HIZ instruction.
• Puts the device in ISP mode and forces all I/O pins to follow
the contents of the JTAG boundary-scan register.
• When this instruction is activated, all core drivers, logics, and
registers are frozen. The I/O pins remain clamped until the
device exits ISP mode successfully.
• Brings the device out of ISP mode.
•
Successful completion of the ISC_DISABLE instruction
happens immediately after waiting 200 µs in the Run-Test/Idle
state.
Sets the device up for in-system programming. Programming
occurs in the run-test or idle state.
• Sets the device to a no-operation mode without leaving the
ISP mode and targets the ISC_Default register.
• Use when:
— two or more ISP-compliant devices are being accessed in
ISP mode and;
— a subset of the devices perform some instructions while
other more complex devices are completing extra steps in
a given process.
Sets the device up to load the flash address. It targets the
ISC_Address register, which is the flash address register.
• Sets the device up to erase the internal flash.
•
Issue after ISC_ADDRESS_SHIFT instruction.
continued...
(2)
Do not issue the ISC_ENABLE_HIZ and ISC_ENABLE_CLAMP instructions from the core logic.
(3)
All ISP and real-time ISP instructions are disabled when the device is not in the ISP or realtime ISP mode, except for the enabling and disabling instructions.
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Instruction Instruction Code Description
ISC_READ
(3)
10 0000 0101
BGP_ENABLE 01 1001 1001
BGP_DISABLE 01 0110 0110
• Sets the device up for verifying the internal flash under
normal user bias conditions.
•
The ISC_READ instruction supports explicit addressing and
auto-increment, also known as the Burst mode.
• Sets the device to the real-time ISP mode.
• Allows access to the internal flash configuration sector while
the device is still in user mode.
• Brings the device out of the real-time ISP mode.
• The device has to exit the real-time ISP mode using the
BGP_DISABLE instruction after it is interrupted by
reconfiguration.
Caution: Do not use unsupported JTAG instructions. It will put the device into an unknown state
and requires a power cycle to recover the operation.
2.1.2.4. Initialization Configuration Bits
Initialization Configuration Bits (ICB) stores the configuration feature settings of the
Intel MAX 10 device. You can set the ICB settings in the Convert Programming File
tool.
Table 6. ICB Values and Descriptions for Intel MAX 10 Devices
Configuration Settings Description Default State/
Set I/O to weak pull-up prior usermode • Enable: Sets I/O to weak pull-up during device
Configure device from CFM0 only. Enable:
Use secondary image ISP data as
default setting when available.
Verify Protect To disable or enable the Verify Protect feature. Disable
Allow encrypted POF only If enabled, configuration error will occur if
configuration.
• Disable: Tri-states I/O
•
CONFIG_SEL pin setting is disabled.
• Device automatically loads image 0.
• Device does not load image 1 if image 0 fails.
Disable:
• Device automatically loads secondary image if initial
image fails.
Select ISP data from initial or secondary image to include in
the POF.
• Disable: Use ISP data from initial image
• Enable: Use ISP data from secondary image
ISP data contains the information about state of the pin
during ISP. This can be either tri-state with weak pull-up or
clamp the I/O state. You can set the ISP clamp through
Device and Pin Option, or Pin Assignment tool.
unencrypted .pof is used.
Value
Enable
Disable
Disable
Disable
continued...
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Configuration Settings Description Default State/
JTAG Secure
Enable Watchdog To disable or enable the watchdog timer for remote system
Watchdog value To set the watchdog timer value for remote system
(4)
To disable or enable the JTAG Secure feature. Disable
upgrade.
upgrade.
Related Information
• .pof and ICB Settings on page 38
• Verify Protect on page 22
• JTAG Secure Mode on page 22
• ISP and Real-Time ISP Instructions on page 10
• User Watchdog Timer on page 18
• Generating .pof using Convert Programming Files on page 39
Provides more information about setting the ICB during .pof generation using
Convert Programming File.
2.1.2.5. Internal Configuration Time
The internal configuration time measurement is from the rising edge of nSTATUS
signal to the rising edge of CONF_DONE signal.
Value
Enable
0xFFF
(5)
Table 7. Internal Configuration Time for Intel MAX 10 Devices (Uncompressed .rbf)
Device Internal Configuration Time (ms)
Unencrypted Encrypted
Without Memory
Initialization
Min Max Min Max Min Max Min Max
10M02/
10M02SCU324
10M04 0.6 2.7 1.0 3.4 5.0 15.0 6.8 19.6
10M08 0.6 2.7 1.0 3.4 5.0 15.0 6.8 19.6
10M16 1.1 3.7 1.4 4.5 9.3 25.3 11.7 31.5
10M25 1.0 3.7 1.3 4.4 14.0 38.1 16.9 45.7
10M40 2.6 6.9 3.2 9.8 41.5 112.1 51.7 139.6
10M50 2.6 6.9 3.2 9.8 41.5 112.1 51.7 139.6
(4)
The JTAG Secure feature will be disabled by default in Intel Quartus Prime software. To make
0.3/0.6 1.7/2.7 — — 1.7/5.0 5.4/15.0 — —
With Memory
Initialization
Without Memory
Initialization
With Memory
Initialization
this option visible, refer to Generating .pof using Convert Programming Files on page 39 for
more information.
(5)
The watchdog timer value depends on the Intel MAX 10 you are using. Refer to the Watchdog
Timer section for more information.
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Table 8. Internal Configuration Time for Intel MAX 10 Devices (Compressed .rbf)
Compression ratio depends on design complexity. The minimum value is based on the best case (25% of
original .rbf sizes) and the maximum value is based on the typical case (70% of original .rbf sizes).
Device Internal Configuration Time (ms)
Unencrypted/Encrypted
Without Memory Initialization With Memory Initialization
Min Max Min Max
10M02/10M02SCU324 0.3/0.6 5.2/10.7 — —
10M04 0.6 10.7 1.0 13.9
10M08 0.6 10.7 1.0 13.9
10M16 1.1 17.9 1.4 22.3
10M25 1.1 26.9 1.4 32.2
10M40 2.6 66.1 3.2 82.2
10M50 2.6 66.1 3.2 82.2
2.2. Configuration Features
2.2.1. Remote System Upgrade
Intel MAX 10 devices support the remote system upgrade feature. By default, the
remote system upgrade feature is enabled when you select the dual compressed
image internal configuration mode.
The remote system upgrade feature in Intel MAX 10 devices offers the following
capabilities:
• Manages remote configuration
• Provides error detection, recovery, and information
• Supports direct-to-application configuration image
•
Supports compressed and encrypted .pof
There are two methods to access remote system upgrade in Intel MAX 10 devices:
• Dual Configuration Intel FPGA IP core
• User interface
Related Information
• Dual Configuration Intel FPGA IP Core on page 19
• Accessing Remote System Upgrade through User Logic on page 43
• AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the
Nios II Processor
Provides reference design for remote system upgrade in Intel MAX 10 FPGA
devices.
• I2C Remote System Update Example
This example demonstrates a remote system upgrade using the I2C protocol.
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Intel® MAX® 10 FPGA Configuration User Guide
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Sample CONFIG_SEL pin
Image 0 Image 1
CONFIG_SEL=0
CONFIG_SEL=1
Wait for Reconfiguration
Power-up
Reconfiguration
Reconfiguration
First Error Occurs
First Error Occurs
Second Error Occurs
Flow when
Configure device
from CFM0 only
is enabled.
Second Error Occurs
Error Occurs
Reconfiguration
Reconfiguration
Power-up
2. Intel MAX 10 FPGA Configuration Schemes and Features
2.2.1.1. Remote System Upgrade Flow
Both the application configuration images, image 0 and image 1, are stored in the
CFM. The Intel MAX 10 device loads either one of the application configuration image
from the CFM.
Figure 3. Remote System Upgrade Flow for Intel MAX 10 Devices
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The remote system upgrade feature detects errors in the following sequence:
1.
After power-up, the device samples the CONFIG_SEL pin to determine which
application configuration image to load. The CONFIG_SEL pin setting can be
overwritten by the input register of the remote system upgrade circuitry for the
subsequent reconfiguration.
2. If an error occurs, the remote system upgrade feature reverts by loading the other
application configuration image. These errors cause the remote system upgrade
feature to load another application configuration image:
• Internal CRC error
• User watchdog timer time-out
3. Once the revert configuration completes and the device is in user mode, you can
use the remote system upgrade circuitry to query the cause of error and which
application image failed.
4. If a second error occurs, the device waits for a reconfiguration source. If the
Auto-restart configuration after error is enabled, the device will reconfigure
without waiting for any reconfiguration source.
5. Reconfiguration is triggered by the following actions:
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Status Register (SR)
Previous
State
Register 2
Bit[31..0]
State
Register 1
Bit[31..0]
Current
State
Logic
Bit[33..0]
Internal Oscillator
Control Register
Bit [38..0]
Logic
Input Register
Bit [38..0]
update
Logic
Bit [40..39]
doutdin
Bit [38..0]
dout
din
capture
Shift Register
clkout
capture
update
Logic
clkin
RU_DIN
RU_SHIFTnLD
RU_CAPTnUPDT
RU_CLK
RU_nRSTIMER
Logic Array
RU
Reconfiguration
State
Machine
User
Watchdog
Timer
RU
Master
State
Machine
timeout
RU_nCONFIGRU_DOUT
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•
Driving the nSTATUS low externally.
•
Driving the nCONFIG low externally.
•
Driving RU_nCONFIG low.
2.2.1.2. Remote System Upgrade Circuitry
Figure 4. Remote System Upgrade Circuitry
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The remote system upgrade circuitry does the following functions:
• Tracks the current state of configuration
• Monitors all reconfiguration sources
• Provides access to set up the application configuration image
• Returns the device to fallback configuration if an error occurs
• Provides access to the information on the failed application configuration image
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2.2.1.2.1. Remote System Upgrade Circuitry Signals
Table 9. Remote System Upgrade Circuitry Signals for Intel MAX 10 Devices
Core Signal Name Logical
Signal
Name
RU_DIN regin
RU_DOUT regout
RU_nRSTIMER rsttimer
RU_nCONFIG rconfig
RU_CLK clk
RU_SHIFTnLD shiftnld
RU_CAPTnUPDT captnupdt
Input/
Output
Input
Output
Input
Input
Input
Input
Input
Description
Use this signal to write data to the shift register on the rising edge of
RU_CLK. To load data to the shift register, assert RU_SHIFTnLD.
Use this signal to get output data from the shift register. Data is
clocked out on each rising edge of RU_CLK if RU_SHIFTnLD is
asserted.
• Use this signal to reset the user watchdog timer. A falling edge of
this signal triggers a reset of the user watchdog timer.
•
To reset the timer, pulse the RU_nRSTIMER signal for a minimum of
250 ns.
Use this signal to reconfigure the device. Driving this signal low
triggers the device to reconfigure if you enable the remote system
upgrade feature.
The clock to the remote system upgrade circuitry. All registers in this
clock domain are enabled in user mode if you enable the remote
system upgrade. Shift register and input register are positive edge flipflops.
Control signals that determine the mode of remote system upgrade
circuitry.
•
When RU_SHIFTnLD is driven low and RU_CAPTnUPDT is driven
low, the input register is loaded with the contents of the shift
register on the rising edge of RU_CLK.
•
When RU_SHIFTnLD is driven low and RU_CAPTnUPDT is driven
high, the shift register captures values from the input_cs_ps
module on the rising edge of RU_CLK.
•
When RU_SHIFTnLD is driven high, the RU_CAPTnUPDT will be
ignored and the shift register shifts data on each rising edge of
RU_CLK.
Related Information
Intel MAX 10 FPGA Device Datasheet
Provides more information about Remote System Upgrade timing specifications.
2.2.1.2.2. Remote System Upgrade Circuitry Input Control
The remote system upgrade circuitry has three modes of operation.
• Update—loads the values in the shift register into the input register.
• Capture—loads the shift register with data to be shifted out.
• Shift—shifts out data to the user logic.
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Table 10. Control Inputs to the Remote System Upgrade Circuitry
Remote System Upgrade Circuitry Control Inputs Operation
RU_SHIFTnLD RU_CAPTnUPDT
0 0 Don't Care Don't Care Update
0 1 0 0 Capture Current State
0 1 0 1 Capture
0 1 1 0 Capture
0 1 1 1 Capture
1 Don't Care Don't Care Don't Care Shift
Shift register
[40]
Shift register
[39]
Mode
The following shows examples of driving the control inputs in the remote system
upgrade circuitry:
•
When you drive RU_SHIFTnLD high to 1’b1, the shift register shifts data on each
rising edge of RU_CLK and RU_CAPTnUPDT has no function.
•
When you drive both RU_SHIFTnLD and RU_CAPTnUPDT low to 1’b0, the input
register is loaded with the contents of the shift register on the rising edge of
RU_CLK.
•
When you drive RU_SHIFTnLD low to 1’b0 and RU_CAPTnUPDT high to 1’b1, the
shift register captures values on the rising edge of RU_DCLK.
Input Settings for Registers
Shift
Register[38:0]
Shift Register
[38:0]
{8’b0, Previous
State
Application1}
{8’b0, Previous
State
Application2}
Input
Register[38:0]
{ru_din, Shift
Register
[38:1]}
Input
Register[38:0]
Shift Register
[38:0]
Input
Register[38:0]
Input
Register[38:0]
Input
Register[38:0]
Input
Register[38:0]
Input
Register[38:0]
2.2.1.2.3. Remote System Upgrade Input Register
Table 11. Remote System Upgrade Input Register for Intel MAX 10 Devices
Bits Name Description
38:14 Reserved
13
12
11:0 Reserved
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ru_config_sel
ru_config_sel_overwrit
e
Reserved—set to 0.
• 0: Load configuration image 0
• 1: Load configuration image 1
This bit will only work if the ru_config_sel_overwrite bit is set to 1.
•
0: Disable overwrite CONFIG_SEL pin
•
1: Enable overwrite CONFIG_SEL pin
Reserved—set to 0.
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2.2.1.2.4. Remote System Upgrade Status Registers
Table 12. Remote System Upgrade Status Register—Current State Logic Bit for Intel
MAX 10 Devices
Bits Name Description
33:30
29
28:0
msm_cs
ru_wd_en
wd_timeout_value
The current state of the master state machine (MSM).
The current state of the enabled user watchdog timer. The default state is active
high.
The current, entire 29-bit watchdog time-out value.
Table 13. Remote System Upgrade Status Register—Previous State Bit for Intel MAX 10
Devices
Bits Name Description
31
30
29
28
27:26
25:22
21:0
nconfig
crcerror
nstatus
wdtimer
An active high field that describes the reconfiguration sources which caused the
Intel MAX 10 device to leave the previous application configuration. In the event
of a tie, the higher bit order takes precedence. For example, if the nconfig and
the ru_nconfig triggered at the same time, the nconfig takes precedence
over the ru_nconfig.
Reserved Reserved—set to 0.
msm_cs
The state of the MSM when a reconfiguration event occurred. The reconfiguration
will cause the device to leave the previous application configuration.
Reserved Reserved—set to 0.
Related Information
Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map on page
62
2.2.1.2.5. Master State Machine
The master state machine (MSM) tracks current configuration mode and enables the
user watchdog timer.
Table 14. Remote System Upgrade Master State Machine Current State Descriptions for
Intel MAX 10 Devices
msm_cs Values
0010
0011
0100
0101
Image 0 is being loaded.
Image 1 is being loaded after a revert in application image happens.
Image 1 is being loaded.
Image 0 is being loaded after a revert in application image happens.
State Description
2.2.1.3. User Watchdog Timer
The user watchdog timer prevents a faulty application configuration from stalling the
device indefinitely. You can use the timer to detect functional errors when an
application configuration is successfully loaded into the device.
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Dual
Configuration
clk
nreset
avmm_rcv_address[2..0]
avmm_rcv_read
avmm_rcv_writedata[31..0]
avmm_rcv_write
avmm_rcv_readdata[31..0]
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The counter is 29 bits wide and has a maximum count value of 229. When specifying
the user watchdog timer value, specify only the most significant 12 bits. The
granularity of the timer setting is 217 cycles. The cycle time is based on the frequency
of the user watchdog timer internal oscillator. Depending on the counter and the
internal oscillator of the device, you can set the cycle time from 9 ms to 244 s.
Figure 5. Watchdog Timer Formula for Intel MAX 10 Devices
The timer begins counting as soon as the application configuration enters user mode.
When the timer expires, the remote system upgrade circuitry generates a time-out
signal, updates the status register, and triggers the loading of the revert configuration
image. To reset the timer and ensure that the application configuration is valid, pulse
the RU_NRSTIMER continuously for a minimum of 250 ns per reset pulse.
When you enable the watchdog timer, the setting will apply to all images, all images
should contain the soft logic configuration to reset the timer. Application configuration
will reset the control block registers.
Related Information
• User Watchdog Internal Circuitry Timing Specifications
Provides more information about the user watchdog frequency.
• Initialization Configuration Bits on page 11
2.2.1.4. Dual Configuration Intel FPGA IP Core
The Dual Configuration Intel FPGA IP core offers the following capabilities through
Avalon® memory-mapped interface:
•
Asserts RU_nCONFIG to trigger reconfiguration.
•
Asserts RU_nRSTIMER to reset watchdog timer if the watchdog timer is enabled.
• Writes configuration setting to the input register of the remote system upgrade
circuitry.
• Reads information from the remote system upgrade circuitry.
Figure 6. Dual Configuration Intel FPGA IP Core Block Diagram
Related Information
• Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map on
page 62
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• Avalon Interface Specifications
Provides more information about the Avalon memory-mapped interface
specifications applied in Dual Configuration Intel FPGA IP core.
• Instantiating the Dual Configuration Intel FPGA IP Core on page 61
• Dual Configuration Intel FPGA IP Core References on page 62
• Remote System Upgrade on page 13
• AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the
Nios II Processor
Provides reference design for remote system upgrade in Intel MAX 10 FPGA
devices.
• I2C Remote System Update Example
This example demonstrates a remote system upgrade using the I2C protocol.
2.2.2. Configuration Design Security
The Intel MAX 10 design security feature supports the following capabilities:
• Encryption—Built-in encryption standard (AES) to support 128-bit key industry-
standard design security algorithm
• Chip ID—Unique device identification
• JTAG secure mode—limits access to JTAG instructions
• Verify Protect—allows optional disabling of CFM content read-back
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2.2.2.1. AES Encryption Protection
The Intel MAX 10 design security feature provides the following security protection for
your designs:
• Security against copying—the non-volatile key is securely stored in the Intel MAX
10 devices and cannot be read through any interface. Without this key, attacker
will not be able to decrypt the encrypted configuration image.
• Security against reverse engineering—reverse engineering from an encrypted
configuration file is very difficult and time consuming because the file requires
decryption.
• Security against tampering—after you enable the JTAG Secure and Encrypted POF
(EPOF) only, the Intel MAX 10 device can only accept configuration files encrypted
with the same key. Additionally, configuration through the JTAG interface is
blocked.
Related Information
Generating .pof using Convert Programming Files on page 39
2.2.2.1.1. Encryption and Decryption
Intel MAX 10 supports AES encryption. Programming bitstream is encrypted based on
the encryption key that is specified by you. In Intel MAX 10 devices, the key is part of
the ICB settings stored in the internal flash. Hence, the key will be non-volatile but
you can clear/delete the key by a full chip erase the device.
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clkin data_valid
chip_id[63..0]reset
Unique Chip ID
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When you use compression with encryption, the configuration file is first compressed,
and then encrypted using the Intel Quartus Prime software. During configuration, the
device first decrypts, and then decompresses the configuration file.
The header and I/O configuration shift register (IOCSR) data will not be encrypted.
The decryption block is activated after the IOCSR chain is programmed. The
decryption block only decrypts core data and postamble.
Related Information
JTAG Instruction Availability on page 23
2.2.2.2. Unique Chip ID
Unique chip ID provides the following features:
• Identifies your device in your design as part of a security feature to protect your
design from an unauthorized device.
• Provides non-volatile 64-bits unique ID for each Intel MAX 10 device with write
protection.
You can use the Unique Chip ID Intel FPGA IP core to acquire the chip ID of your Intel
MAX 10 device.
Related Information
• Unique Chip ID Intel FPGA IP Core on page 60
• Unique Chip ID Intel FPGA IP Core Ports on page 65
2.2.2.2.1. Unique Chip ID Intel FPGA IP Core
Figure 7. Unique Chip ID Intel FPGA IP Core Block Diagram
At the initial state, the data_valid signal is low because no data is read from the
unique chip ID block. After feeding a clock signal to the clkin input port, the Unique
Chip ID Intel FPGA IP core begins to acquire the chip ID of your device through the
unique chip ID block. After acquiring the chip ID of your device, the Unique Chip ID
Intel FPGA IP core asserts the data_valid signal to indicate that the chip ID value at
the output port is ready for retrieval.
The operation repeats only when you provide another clock signal when the
data_valid signal is low. If the data_valid signal is high when you provide
another clock signal, the operation stops because the chip_id[63..0] output holds
the chip ID of your device.
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A minimum of 67 clock cycles are required for the data_valid signal to go high.
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