Intel MAX 10 User Manual

Intel® MAX® 10 General Purpose I/O User Guide

Updated for Intel® Quartus® Prime Design Suite: 20.1

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1. Intel® MAX® 10 I/O Overview

The Intel® MAX® 10 general purpose I/O (GPIO) system consists of the I/O elements (IOE) and the GPIO Lite Intel FPGA IP. You can use GPIOs in non-transceiver general applications, memory-like interfaces, or LVDS applications.

• The IOEs contain bidirectional I/O buffers and I/O registers located in I/O banks around the periphery of the device.

• The GPIO Lite IP core supports the GPIO components and features, including double data rate I/O (DDIO), delay chains, I/O buffers, control signals, and clocking.

Related Information

• Intel MAX 10 I/O Architecture and Features on page 6

Provides information about the architecture and features of the I/Os in Intel MAX 10 devices.

• Intel MAX 10 I/O Design Considerations on page 30

Provides I/O design guidelines for Intel MAX 10 Devices.

• Intel MAX 10 I/O Implementation Guides on page 41

Provides guides to implement I/Os in Intel MAX 10 Devices.

• GPIO Lite Intel FPGA IP References on page 46

Lists the parameters and signals of GPIO Lite IP core for Intel MAX 10 Devices.

• Intel MAX 10 General Purpose I/O User Guide Archives on page 50

Provides a list of user guides for previous versions of the GPIO Lite IP core.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, eASIC, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

ISO 9001:2015 Registered

1. Intel

MAX® 10 I/O Overview

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1.1. Intel MAX 10 Devices I/O Resources Per Package

Table 1. Package Plan for Intel MAX 10 Single Power Supply Devices

Device Package

Type M153

153-pin MBGA

Size 8 mm × 8 mm 11 mm × 11 mm 15 mm × 15 mm 22 mm × 22 mm

Ball Pitch 0.5 mm 0.8 mm 0.8 mm 0.5 mm

10M02 112 130 246 101

10M04 112 130 246 101

10M08 112 130 246 101

10M16 — 130 246 101

10M25 — — — 101

10M40 — — — 101

10M50 — — — 101

Table 2. Package Plan for Intel MAX 10 Dual Power Supply Devices

U169

169-pin UBGA

U324

324-pin UBGA

E144

144-pin EQFP

Device Package

Type V36

36-pin WLCSP

Size 3 mm × 3 mm 4 mm × 4 mm 15 mm × 15mm17 mm × 17mm23 mm × 23mm27 mm × 27

Ball Pitch 0.4 mm 0.4 mm 0.8 mm 1.0 mm 1.0 mm 1.0 mm

10M02 27 — 160 — — —

10M04 — — 246 178 — —

10M08 — 56 246 178 250 —

10M16 — — 246 178 320 —

10M25 — — — 178 360 —

10M40 — — — 178 360 500

10M50 — — — 178 360 500

V81

81-pin WLCSP

U324

324-pin UBGA

F256

256-pin FBGA

F484

484-pin FBGA

F672

672-pin FBGA

Related Information

Development Kits and Boards, Intel MAX Design Tools

Intel® MAX® 10 General Purpose I/O User Guide

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Device

V36 V81 M153 U169 U324 F256 E144 F484 F672

10M02

10M04

10M08

10M16

10M25

10M40

10M50

Package

Single Power Supply Devices

Dual Power Supply Devices

1. Intel

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MAX® 10 I/O Overview

1.2. Intel MAX 10 I/O Vertical Migration Support

Figure 1. Migration Capability Across Intel MAX 10 Devices

• The arrows indicate the migration paths. The devices included in each vertical migration path are shaded. Non-migratable devices are omitted. Some packages have several migration paths. Devices with lesser I/O resources in the same path have lighter shades.

• To achieve the full I/O migration across product lines in the same migration path, restrict I/Os usage to match the product line with the lowest I/O count.

Note: Before starting migration work, Intel recommends that you verify the pin migration

compatibility through the Pin Migration View window in the Intel Quartus® Prime software Pin Planner. For example, not all Intel MAX 10 devices support 1.0 V I/O.

Related Information

Verifying Pin Migration Compatibility on page 44

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2. Intel MAX 10 I/O Architecture and Features

The I/O system of Intel MAX 10 devices support various I/O standards. In the Intel MAX 10 devices, the I/O pins are located in I/O banks at the periphery of the devices. The I/O pins and I/O buffers have several programmable features.

Related Information

Intel MAX 10 I/O Overview on page 3

2.1. Intel MAX 10 I/O Standards Support

Intel MAX 10 devices support a wide range of I/O standards, including single-ended, voltage-referenced single-ended, and differential I/O standards.

Table 3. Supported I/O Standards in Intel MAX 10 Devices

The voltage-referenced I/O standards are not supported in the following I/O banks of these device packages:

• All I/O banks of V36 package of 10M02.

• All I/O banks of V81 package of 10M08.

• Banks 1A and 1B of E144 package of 10M50.

I/O Standard

3.3 V LVTTL/3.3 V LVCMOS

3.0 V LVTTL/3.0 V LVCMOS

2.5 V LVCMOS Single-ended All Yes Yes General purpose JESD8-5

1.8 V LVCMOS Single-ended All Yes Yes General purpose JESD8-7

1.5 V LVCMOS Single-ended All Yes Yes General purpose JESD8-11

1.2 V LVCMOS Single-ended All Yes Yes General purpose JESD8-12

1.0 V LVCMOS

3.0 V PCI Single-ended All Yes Yes General purpose PCI Rev. 2.2

3.3 V Schmitt Trigger Single-ended All Yes — General purpose —

(1)

Available only for the following devices: 10M02SCU324C8G, 10M04SCU324C8G,

(1)

Type Device

Single-ended All Yes Yes General purpose JESD8-B

Single-ended Specific

Support

devices

(1)

Direction Application Standard

Input Output

Yes Yes General purpose —

continued...

Support

10M08SCU324C8G, 10M16SCU324C8G, 10M16SCU169C8G, 10M16SAU169C8G, 10M16DCF484C8G, 10M16DAF484C8G, 10M25DCF484C8G, 10M25DAF484C8G, 10M40DCF484C8G, 10M40DAF484C8G, 10M50DCF484C8G, and 10M50DAF484C8G.

ISO 9001:2015 Registered

2. Intel MAX 10 I/O Architecture and Features

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I/O Standard Type Device

Support

Direction Application Standard

Input Output

Support

2.5 V Schmitt Trigger Single-ended All Yes — General purpose —

1.8 V Schmitt Trigger Single-ended All Yes — General purpose —

1.5 V Schmitt Trigger Single-ended All Yes — General purpose —

SSTL-2 Class I Voltage-

All Yes Yes DDR1 JESD8-9B

referenced

SSTL-2 Class II Voltage-

All Yes Yes DDR1 JESD8-9B

referenced

SSTL-18 Class I Voltage-

All Yes Yes DDR2 JESD8-15

referenced

SSTL-18 Class II Voltage-

All Yes Yes DDR2 JESD8-15

referenced

SSTL-15 Class I Voltage-

All Yes Yes DDR3 —

referenced

SSTL-15 Class II Voltage-

All Yes Yes DDR3 —

referenced

(2)

SSTL-15

Voltage-

All Yes Yes DDR3 JESD79-3D

referenced

SSTL-135

(2)

Voltage-

All Yes Yes DDR3L —

referenced

1.8 V HSTL Class I Voltagereferenced

1.8 V HSTL Class II Voltagereferenced

1.5 V HSTL Class I Voltagereferenced

All Yes Yes DDR II+, QDR II+,

and RLDRAM 2

All Yes Yes DDR II+, QDR II+,

and RLDRAM 2

All Yes Yes DDR II+, QDR II+,

QDR II, and

JESD8-6

RLDRAM 2

1.5 V HSTL Class II Voltagereferenced

All Yes Yes DDR II+, QDR II+,

QDR II, and

JESD8-6

RLDRAM 2

1.2 V HSTL Class I Voltage-

All Yes Yes General purpose JESD8-16A

referenced

1.2 V HSTL Class II Voltage-

All Yes Yes General purpose JESD8-16A

referenced

HSUL-12

(2)

Voltage-

All Yes Yes LPDDR2 —

referenced

Differential SSTL-2 Class I

Differential All Yes

(3)

Yes

(4)

DDR1 JESD8-9B

and II

Differential SSTL-18 Class

Differential All Yes

(3)

Yes

(4)

DDR2 JESD8-15

I and Class II

continued...

(2)

Available in Intel MAX 10 16, 25, 40, and 50 devices only.

(3)

The inputs treat differential inputs as two single-ended inputs and decode only one of them.

(4)

The outputs use two single-ended output buffers with the second output buffer programmed as inverted.

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I/O Standard Type Device

Differential SSTL-15 Class

Differential All Yes

Support

Direction Application Standard

Input Output

(3)

Yes

(4)

DDR3 —

Support

I and Class II

Differential SSTL-15 Differential All Yes

Differential SSTL-135 Differential All Yes

Differential 1.8 V HSTL

Differential All Yes

Class I and Class II

Differential 1.5 V HSTL

Differential All Yes

Class I and Class II

(3)

Yes

(4)

DDR3 JESD79-3D

DDR3L —

DDR II+, QDR II+,

and RLDRAM 2

DDR II+, QDR II+,

QDR II, and

JESD8-6

RLDRAM 2

Differential 1.2 V HSTL

Differential All Yes

(3)

Yes

(4)

General purpose JESD8-16A

Class I and Class II

Differential HSUL-12 Differential All Yes

LVDS (dedicated)

(5)

Differential All Yes Yes — ANSI/TIA/

(3)

Yes

(4)

LPDDR2 —

EIA-644

LVDS (emulated, external resistors)

Mini-LVDS (dedicated)

(5)

Mini-LVDS (emulated, external resistor)

Differential All — Yes — ANSI/TIA/

EIA-644

Differential All — Yes — —

Differential Dual

— Yes — —

supply

devices

RSDS (dedicated)

RSDS (emulated, external resistor, 1R)

(5)

Differential All — Yes — —

Differential Dual

— Yes — —

supply

devices

RSDS (emulated, external

Differential All — Yes — —

resistors, 3R)

PPDS (dedicated)

(5)

Differential Dual

— Yes — —

supply

devices

PPDS (emulated, external resistor)

Differential Dual

supply

— Yes — —

devices

LVPECL Differential All Yes — — —

Bus LVDS Differential All Yes Yes

TMDS Differential Dual

Yes — — —

(6)

— —

supply

devices

continued...

(5)

You can use dedicated LVDS transmitters only on the bottom I/O banks. You can use LVDS receivers on all I/O banks.

(6)

The outputs use two single-ended output buffers with the second output buffer programmed as inverted. A single series resistor is required.

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I/O Standard Type Device

Support

Sub-LVDS Differential Dual

supply

devices

SLVS Differential Dual

supply

devices

HiSpi Differential Dual

supply

devices

Direction Application Standard

Input Output

Yes Yes

Yes — — —

(7)

(8)

— —

Related Information

• Intel MAX 10 I/O Buffers on page 17 Provides more information about available I/O buffer types and supported I/O standards.

• LVDS Transmitter I/O Termination Schemes, Intel MAX 10 High-Speed LVDS I/O

User Guide

Provides the required external termination schemes and resistor values for the emulated LVDS, Sub-LVDS, SLVS, emulated RSDS, emulated mini-LVDS, and emulated PPDS I/O standards.

2.1.1. Intel MAX 10 I/O Standards Voltage and Pin Support

Table 4. Intel MAX 10 I/O Standards Voltage Levels and Pin Support

Support

Note: The I/O standards that each pin type supports depends on the I/O standards that the pin's

I/O Standard V

3.3 V LVTTL/3.3 V LVCMOS

3.0 V LVTTL/3.0 V LVCMOS

2.5 V LVCMOS 3.0/2.5 2.5 — Yes Yes Yes Yes Yes

1.8 V LVCMOS 1.8/1.5 1.8 — Yes Yes Yes Yes Yes

1.5 V LVCMOS 1.8/1.5 1.5 — Yes Yes Yes Yes Yes

1.2 V LVCMOS 1.2 1.2 — Yes Yes Yes Yes Yes

1.0 V LVCMOS 1.0

(7)

Requires external termination resistors.

(8)

The outputs uses two single-ended output buffers as emulated differential outputs. Requires

I/O bank supports. For example, only the bottom I/O banks support the LVDS (dedicated) I/O standard. You can use the LVDS (dedicated) I/O standard for the PLL_CLKOUT pin only if the pin is available in your device's bottom I/O banks. To determine the pin's I/O bank locations for your device, check your device's pin out file.

(V) V

CCIO

Input Output

3.3/3.0/2. 5

3.0/2.5 3.0 — Yes Yes Yes Yes Yes

(9)

3.3 — Yes Yes Yes Yes Yes

(9)

1.0

(V) Pin Type Support

REF

PLL_CLKOUTMEM_CLK CLK DQS

— — — Yes — Yes

continued...

external termination resistors.

User

I/O

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2. Intel MAX 10 I/O Architecture and Features

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I/O Standard V

Input Output

(V) V

CCIO

(V) Pin Type Support

REF

PLL_CLKOUTMEM_CLK CLK DQS

User

I/O

3.0 V PCI 3.0 3.0 — Yes Yes Yes Yes Yes

3.3 V Schmitt Trigger 3.3 — — — — Yes Yes

2.5 V Schmitt Trigger 2.5 — — — — Yes Yes

1.8 V Schmitt Trigger 1.8 — — — — Yes Yes

1.5 V Schmitt Trigger 1.5 — — — — Yes Yes

(10)

Yes

SSTL-2 Class I 2.5 2.5 1.25 Yes Yes Yes Yes Yes

SSTL-2 Class II 2.5 2.5 1.25 Yes Yes Yes Yes Yes

SSTL-18 Class I 1.8 1.8 0.9 Yes Yes Yes Yes Yes

SSTL-18 Class II 1.8 1.8 0.9 Yes Yes Yes Yes Yes

SSTL-15 Class I 1.5 1.5 0.75 Yes Yes Yes Yes Yes

SSTL-15 Class II 1.5 1.5 0.75 Yes Yes Yes Yes Yes

SSTL-15 1.5 1.5 0.75 Yes Yes Yes Yes Yes

SSTL-135 1.35 1.35 0.675 Yes Yes Yes Yes Yes

1.8 V HSTL Class I 1.8 1.8 0.9 Yes Yes Yes Yes Yes

1.8 V HSTL Class II 1.8 1.8 0.9 Yes Yes Yes Yes Yes

1.5 V HSTL Class I 1.5 1.5 0.75 Yes Yes Yes Yes Yes

1.5 V HSTL Class II 1.5 1.5 0.75 Yes Yes Yes Yes Yes

1.2 V HSTL Class I 1.2 1.2 0.6 Yes Yes Yes Yes Yes

1.2 V HSTL Class II 1.2 1.2 0.6 Yes Yes Yes Yes Yes

HSUL-12 1.2 1.2 0.6 Yes Yes Yes Yes Yes

Differential SSTL-2 Class I and II

Differential SSTL-18 Class I and Class II

Differential SSTL-15 Class I and Class II

— 2.5 — Yes Yes — Yes —

2.5 — 1.25 — — Yes Yes —

— 1.8 — Yes Yes — Yes —

1.8 — 0.9 — — Yes Yes —

— 1.5 — Yes Yes — Yes —

1.5 — 0.75 — — Yes Yes —

Differential SSTL-15 — 1.5 — Yes Yes — Yes —

1.5 — 0.75 — — Yes Yes —

Differential SSTL-135 — 1.35 — Yes Yes — Yes —

1.35 — 0.675 — — Yes Yes —

Differential 1.8 V HSTL

— 1.8 — Yes Yes — Yes —

Class I and Class II

continued...

(9)

Not supported on bank 1B and bank 8.

(10)

Bidirectional—use Schmitt Trigger input with LVTTL output.

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I/O Standard V

Input Output

1.8 — 0.9 — — Yes Yes —

Differential 1.5 V HSTL Class I and Class II

Differential 1.2 V HSTL Class I and Class II

Differential HSUL-12 — 1.2 — Yes Yes — Yes —

LVDS (dedicated) 2.5 2.5 — Yes Yes Yes — Yes

LVDS (emulated, external resistors)

Mini-LVDS (dedicated) — 2.5 — Yes Yes — — Yes

Mini-LVDS (emulated, external resistor)

RSDS (dedicated) — 2.5 — Yes Yes — — Yes

RSDS (emulated, external resistor, 1R)

RSDS (emulated, external resistors, 3R)

PPDS (dedicated) — 2.5 — Yes Yes — — Yes

PPDS (emulated, external resistor)

LVPECL 2.5 — — — — Yes — —

Bus LVDS 2.5 2.5 — — — — — Yes

TMDS 2.5 — — — — Yes — Yes

Sub-LVDS 2.5 1.8 — Yes Yes Yes — Yes

SLVS 2.5 2.5 — Yes Yes Yes — Yes

HiSpi 2.5 — — — — Yes — Yes

1.5 — 0.75 — — Yes Yes —

1.2 — 0.6 — — Yes Yes —

(V) V

CCIO

— 1.5 — Yes Yes — Yes —

— 1.2 — Yes Yes — Yes —

— 2.5 — Yes Yes — — Yes

(V) Pin Type Support

REF

PLL_CLKOUTMEM_CLK CLK DQS

User

I/O

Related Information

• Intel MAX 10 Device Pin-Out Files

• Intel MAX 10 I/O Standards Support on page 6

• Intel MAX 10 I/O Banks Locations on page 14

• Intel MAX 10 LVDS SERDES I/O Standards Support

• Intel MAX 10 High-Speed LVDS I/O Location

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2.2. Intel MAX 10 I/O Elements

The Intel MAX 10 I/O elements (IOEs) contain a bidirectional I/O buffer and five registers for registering input, output, output-enable signals, and complete embedded bidirectional single data rate (SDR) and double data rate (DDR) transfer.

The I/O buffers are grouped into groups of four I/O modules per I/O bank:

•

The Intel MAX 10 devices share the user I/O pins with the VREF, RUP, RDN,

CLKPIN, PLLCLKOUT, configuration, and test pins.

• Schmitt Trigger input buffer is available in all I/O buffers.

• When the Intel MAX 10 device is blank or erased, the I/Os are tri-stated.

Each IOE contains one input register, two output registers, and two output-enable (OE) registers:

• The two output registers and two OE registers are used for DDR applications.

• You can use the input registers for fast setup times and output registers for fast clock-to-output times.

• You can use the OE registers for fast clock-to-output enable times.

You can use the IOEs for input, output, or bidirectional data paths. The I/O pins support various single-ended and differential I/O standards.

2. Intel MAX 10 I/O Architecture and Features

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Intel® MAX® 10 General Purpose I/O User Guide

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D Q

ENA

D Q

ENA

CCIO

Optional

PCI Clamp

Programmable

Pull-Up Resistor

Bus Hold

Input Pin to

Input Register

Delay

or Input Pin to

Logic Array

Delay

Output

Pin Delay

clkin

oe_in

data_in0

data_in1

sclr/

preset

Chip-Wide Reset

aclr/prn

oe_out

clkout

OE Register

Current Strength Control

Open-Drain Out

Column

or Row

Interconnect

io_clk[5..0]

Slew Rate Control

ACLR/PRN

Output Register

D Q

ENA

ACLR/PRN

Input Register

2. Intel MAX 10 I/O Architecture and Features

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Figure 2. IOE Structure in Bidirectional Configuration

Related Information

• Intel MAX 10 Power Management User Guide Provides more information about the I/O buffers in different power cycles and hot socketing.

• Schmitt-Trigger Input Buffer on page 17

2.2.1. Intel MAX 10 I/O Banks Architecture

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The I/O elements are located in a group of four modules per I/O bank:

• High speed DDR3 I/O banks—supports various I/O standards and protocols

including DDR3. These I/O banks are available only on the right side of the device.

• High speed I/O banks—supports various I/O standards and protocols except

DDR3. These I/O banks are available on the top, left, and bottom sides of the device.

• Low speed I/O banks—lower speeds I/O banks that are located at the top left side

of the device.

For more information about I/O pins support, refer to the pinout files for your device.

Intel® MAX® 10 General Purpose I/O User Guide

Related Information

Intel MAX 10 Device Pin-Out Files

2.2.2. Intel MAX 10 I/O Banks Performance

The performance of the I/O banks differs for different I/O standards and I/O bank types. You must ensure that the frequency you specified passes timing check in the Intel Quartus Prime software.

The low speed I/O banks have lower maximum frequency than other I/O banks because of longer propagation delays. However, the delays do not affect the timing parameters such as slew rate, rise time, and fall time.

For details about the location of the high speed and low speed I/O banks, refer to the device pinout files.

Related Information

• High-Speed I/O Specifications Provides the performance information for different I/O standards in the lowspeed and high-speed I/O banks.

• IBIS Models for Intel Devices

• SPICE Models for Altera Devices

2. Intel MAX 10 I/O Architecture and Features

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2.2.3. Intel MAX 10 I/O Banks Locations

The I/O banks are located at the periphery of the device.

For more details about the modular I/O banks available in each device package, refer to the relevant device pin-out file.

Intel® MAX® 10 General Purpose I/O User Guide

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VREF1

VCCIO8VREF8

VCCIO1

VCCIO5VCCIO2

VCCIO3 VREF3

VCCIO6

VREF6

VREF2

VREF5

Low Speed I/O

High Speed I/O

3 4

8 7

VCCIO5VCCIO2

VCCIO3 VREF3 VREF4VCCIO4

VCCIO7VCCIO8

VCCIO1B

VCCIO1A

VCCIO6

VREF6

VREF1

VREF2

VREF8 VREF7

VREF5

Low Speed I/O

High Speed I/O

2. Intel MAX 10 I/O Architecture and Features

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Figure 3. I/O Banks for 10M02 Devices (Except Single Power Supply U324 Package)

Figure 4. I/O Banks for 10M02 (Single Power Supply U324 Package), 10M04, and

10M08 Devices

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3 4

8 7

VCCIO5VCCIO2

VCCIO3 VREF3 VREF4VCCIO4

VCCIO7VCCIO8

VCCIO1B

VCCIO1A

VCCIO6

VREF6

VREF1

VREF2

VREF8 VREF7

VREF5

Low Speed I/O

High Speed I/O

High Speed DDR3 I/O

OCT

2. Intel MAX 10 I/O Architecture and Features

Figure 5. I/O Banks for 10M16, 10M25 , 10M40, and 10M50 Devices

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Related Information

• Intel MAX 10 Device Pin-Out Files

• High-Speed I/O Specifications Provides the performance information for different I/O standards in the lowspeed and high-speed I/O banks.

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+ 37 hidden pages

Intel MAX 10 User Manual

Contents

1. Intel® MAX® 10 I/O Overview

1.1. Intel MAX 10 Devices I/O Resources Per Package

1.2. Intel MAX 10 I/O Vertical Migration Support

2. Intel MAX 10 I/O Architecture and Features

2.1. Intel MAX 10 I/O Standards Support

2.1.1. Intel MAX 10 I/O Standards Voltage and Pin Support

2.2. Intel MAX 10 I/O Elements

2.2.1. Intel MAX 10 I/O Banks Architecture

2.2.2. Intel MAX 10 I/O Banks Performance

2.2.3. Intel MAX 10 I/O Banks Locations