Intel Matanzas Schematic

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Matanzas

Table of Contents

Page Description

1a

This Page

1b

Revision History

2

D D

C C

B B

NOTES

3

Intel® Core™2 Duo Mobile Processor (1 of 2)

4

Intel® Core™2 Duo Mobile Processor (2 of 2)

5

CPU Thermal Sensor & Fan

6

Mobile Intel® 965 Express Chipset Family (1 OF 6)

7

Mobile Intel® 965 Express Chipset Family (2 OF 6)

8

Mobile Intel® 965 Express Chipset Family (3 OF 6)

9

Mobile Intel® 965 Express Chipset Family (4 OF 6)

10

Mobile Intel® 965 Express Chipset Family (5 OF 6)

11

Mobile Intel® 965 Express Chipset Family (6 OF 6)

12

Mobile Intel® 965 Express Chipset Family Strapping

13

DDR2 SODIMM 0

14

DDR2 SODIMM 1

15

DDR2 TERMINATION AND THERMAL SENSOR

16

CRT

17

LVDS

18

TV

19

PCIE GRAPHICS

20

XDP

21

ICH8M (1 of 4)

22

ICH8M (2 of 4)

23

ICH8M (3 of 4)

24

ICH8M (4 of 4)

25

PCI-E Slots (1 & 2)

26

PCI-E Slots (3,4 & 5)

27

High Definition Audio

28

HDA Power Supply

29

USB 1.1/2.0

30

SATA (1 of 3)

31

SATA (2 and 3 of 3)

32

IDE

33

PCI Slot 3

34

PCI Edge Connector (Goldfinger)

35

Intel® 82566 MM/MC LAN & Ekron-N Option

36

LAN Docking and SPI

37

CK505

38

DB800 & Buffers

39

FWH and I/O Port Expander

40

SIO

41

Legacy Support

42

H8 2104 KBC

43

PS2

44

LPC Slot, TPM Header, and EMA

45

Docking

46

TPS51120 System Power

47

DDR VR

48

Crestline VR

49

Graphics Core VR

50

DDR2 VREF

51

System Charger VR

52

IMVP-6

53

IMVP-6 Core VR

54

CPU Decoupling

55

Start Up Sequence

56

DISCHARGE CIRCUITS

57

Sleep control

58

POWER SEQUENCING TIMING BLOCK DIAGRAM

Intel® Core™2 Duo Mobile Processor, Mobile Intel® 965 Express Chipset Family and ICH8M

Customer Reference Board

Rev 1.5

A A

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Matanzas

Title

Size Document Number Rev

Date: Sheet

A

TITLE PAGE

NDA

2

Intel Confidential

1a 58Thursday, November 30, 2006

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Rev 1.5 (Changes from Rev 1.301)

Note: Revision 1.5 of the CRB Schematics is based on Fab 3 of Matanzas boards.

D D

Page:3

-The PROCHOT signal pull up value changed from 75 Ohms to 1K Ohms,1%. This fixes the PROCHOT# failure when driven by thermal sensor on the CRB. Page:7

-Updated Crestline symbol to indicate LVDSB_DATA_3 and LVDSB_DATA#3 pins to support Dual Channel 24-bit LVDS Support. Page:10

-Crestline CRT/TV QDAC Filter Change (Refer to WW44 Santa Rosa MOW)

-Changed FB5T1 to R5U20 Resistor 100 ohms, 5%,1/16W

-Changed no-stuff R5T5 with C5T20 1.0uF,20% Page:13

-Corrected net name RSVD-M_A_A14 to M_A_A14 Page:14

-Corrected net name RSVD-M_B_A14 to M_B_A14 Page:17

-LVDS Connector updated to indicate LVDSB_DATA_3 and LVDSB_DATA#3 pins Page:21

-Added a note that ICH8M Internal VR should not be disabled. Page:22

C C

-Added strapping configuration information for PCIe x2 Page:23

-Removed the pull-up to +V3.3S circuit on CRB_SV_DET. Customer platforms should pull-up CRB_SV_DET (if used) to +V3.3A via 10k Ohm resistor. Page 31:

-Clarified SATA Port 1 impact with J7J2 No Shunt Page:36

-Auto Connect Battery Saver Energy Detect Circuit Update: R5A3 changed from 3.92KOhms to 1.87KOhms. This is an update to the recommendation in the WW44 Santa Rosa MOW. Page:41 If SPI Descriptor Lock is removed, a 1k Ohms resistor is required between pins 9 and 7 of J8F1 to avoid damage to I/Os. Page:44

-ME_SMC_ALERT# should be pulled-up to +V3.3A instead of +V3.3M. On the CRB,R6G17 is made no-stuff & the internal pull up on the H8 is enabled. Customer platforms need to pull this signal to +V3.3A.

-Added note on ME_SMC_ALERT# assertion/de-assertion indication Page:48

-499 Ohms value of R5G10 causes +V1.05S to be +V1.09S. R5G10 changed from 499Ohms to 0Ohms. Page:49

B B

-R3G13, R3G12, R3G11, R3G9, R3G10 stuff with 20K resistors

-R3G14 stuff with 30K resistor

-R2G16 value changed to 100K resistor

-J2G1 – Removed jumper shunts. No shunts to be installed.

-The pull up on GVR_VID3 (R3G10) and GVR_VR_EN (R3G14) should be connected to +V3.3S instead of +V3.3

-Modified sheet Graphics Controller symbol Page:52 & 53

-Modified sheet IMVP Controller and FET Symbols Page:55

-J3G1 Pin1 and 2 should be shorted for ME support in G3 state.

-Corrected net name XDP_DBRESET#_R to XDP_DBRESET#

A A

Title

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Date: Sheet of

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Date: Sheet

Revision History

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SANTA ROSA CUSTOMER REFERENCE PLATFORM

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

D D

Voltage Rails

+VBATA +VBAT +VBATS +V12S

-V12A

-V12S +V5A +V5 +V5S +V3.3A +V3.3M +V3.3M_CK505 +V3.3 +V3.3S +V1.8 +V1.5S +V1.25M +V1.25S +V1.05M +V1.05S +V0.9 +VCC_CORE +VCC_GFXCORE

VOLTAGE DESCRIPTIONACTIVE INPOWER PLANE

9V-12.5V 9V-12.5V 9V-12.5V 12V

-12V

-12V 5V 5V 5V

3.3V

1.8V

1.5V

1.25V

1.05V

0.9V

0.700V-1.77V

0.7V-1.25V

S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0 S0/M0 S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0 S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0,° 3/M1, S3/M-off

ٛ

S0/M0 S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0, (S3-S5)/M1, S3/(M-off w/WOL_EN) S0/M0, (S3-S5)/M1 S0/M0, S3/M1, S3/M-off S0/M0 S0/M0, (S3-S5)/M1, S3/M-off S0/M0 S0/M0, (S3-S5)/M1 S0/M0 S0/M0, (S3-S5)/M1 S0/M0 S0/M0, (S3-S5)/M1, S3/M-off S0/M0 S0/M0

Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Only on in DT Power Mode Only on in DT Power Mode Only on in DT Power Mode

LAN Clock, MCH

DDR core

GMCH, ICH core, and FSB rail DDR command & control pull up. CPU core rail GMCH Graphics core rail

2

I C / SMB Addresses

Clock Generator DB800 Clock Buffer SO-DIMM0 SO-DIMM1 SO-DIMM0 Thermal Sensor SO-DIMM1 Thermal Sensor DDR Thermal Sensor I2C Bus Expander Ambient Lighr Sensor EMA Display CPU Thermal Sensor IMVP6 Amb. Temp. Sensor Battery A Battery B Board ID Port Expander Docking Port Expander Skin Temperature Sensor H8 PCI-Slot3 PCI-Gold Finger PCI-Express Slot1-5 Docking PCIe x16 Slot (PEG) TPM Header ITP-XDP

AddressDevice 1101 001x 1101 110x 1010 000x 1010 010x 0011 000x 0011 010x 0100 110x 0011 xxxx 0111 001x 0011 110x 1001 100x 1001 101x 0001 011x 0001 111x 0011 000x 0011 001x 1001 100x TBD TBD TBD TBD TBD TBD TBD TBD

BusHex PageJumper DescriptionDefault

D2

SMB_ICH_M3

DC

SMB_ICH_M3

A0

SMB_ICH_M2

A4

SMB_ICH_M2

30

SMB_ICH_M2

34

SMB_ICH_M2

4C

SMB_ICH_M2

3x

SMB_ICH

72

ALS

3C

EMA

98

SMB_THRM

9A

SMB_THRM

16

SMB_BS

1E

SMB_BS

30

SMB_BS

32

SMB_BS

98

SMB_BS

TBD

SMB_ME

TBD

SMB_ICH_A1

TBD

SMB_ICH_A1

TBD

SMB_ICH_A1

TBD

SMB_ICH_A1

TBD

SMB_ICH_S4

TBD

SMB_ICH_S4

TBD

SMB_ICH_S4

C C

Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. The rest come out of EC.

Jumper / Switch Settings

J1G2

1-2 J1G5 J1G8 J2G1 J2G1 J2G1 J2G1 J2G1 J2H1 J3B2 J3G1 J4H1 J5H2 J6H2 J7D1 J7J2 J8B1 J8B2 J8E2 J8F2 J9F1 J9G2 J9H1 J9H2 J9H3 J9H4 J9H5 J9H6 J9H7 J9H8 J9H9

BSEL0

1-2

BSEL1

1-2

BSEL2

1-2

GFX CORE

3-4

GFX CORE

5-6

GFX CORE

7-8

GFX CORE

11-12

GFX CORE

1-X

Force Shutdown

1-2, 3-4

CPU thermal sensor

1-X

Power ON Latch

1-X

ME G3 to M1

1-X

CMOS Clear

1-2

CRB/SV Detect

1-2

SIO Reset

1-2

SATA Power Enable

1-2

In-circuit SMC Programming

1-2

In-circuit SMC Programming

1-X

Boot BIOS Strap

1-X

BIOS recovery

1-2

KSC Enable

1-2

Boot Block Programming

1-X

Virtual Docking

1-X

NMI

1-X

KBC disable

1-2

SMC MD0

1-2

SATA device detect

1-X

SMC MD2

1-2

SMC MD1

1-X

LID Position

1-X

Virtual Battery

37 37 37 49 49 49 49 49 55 5 55 55 21 23 40 31 41 41 22 23 42 43 42 43 42 42 31 42 42 42 42

Changes for Matanzas with PM GMCH SKU

SL No NO_STUFF STUFF

U6E2, U6E3, U6E4

1

L5F1

2

3

4

5

6

R5E5, R5F9, R5T16, R5U3, R5U11, R5U14, R5U21, R6V1

C5E8, C5E9, C5E11, C5E12, C5E13, C5E14, C5E15, C5T12, C5T13, C5U1, C5U2, C5U3

FB5F1, FB5F2, FB5T1

J2G1(3 4), J2G1(5 6),

R5E4, R5T5, R5T8, R5T9, R5T10, R5T12, R5T17

C5E8,C5E9,C5T13,C5U3 with 0 Ohm 0402 size res IPN A93549-001

J2G1(1 2), J2G1(13 14)

PCI Devices

PageSwitch Default Description

42 42 42

Wake Events

Wake Events RI# from serial port PME# from PCI, mini PCI slot/device, LPC slot/device PCI Express, mini PCI Express, Express-card wake event Wake on LAN LID switch attached to SMC USB HDA wake on ring SmLink for AOLII Hot Key from Scan matrix keyboard PS/2 Keyboard/mouse PWRBTN# Netdetect

PCB Footprints

1

2

SOT-23

3

As seen from top

1

2

3

2

State Supported S3 S3 S3 S3/M1 S3 S3 S3 S3 S3 S3 S3 S3, S4, S5 / M1

SOT23-5

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SLP_S4#

HIGH

LOW

Interrupts

SLP_S5#

HIGH

LOW

HIGH

LOW

SLP_M#

HIGH

LOW

HIGH

LOW

+V*A

ON

+V3.3M

ON

OFF

ON

OFF

+V1.25M/ +V1.05M

ON

OFF

ON

OFF

4

+V3.3M_CK505

ON

OFF

ON

OFF

+V1.8/+V0.9

ON

OFF

+V5/+V3.3

ON

OFF

+V*S

ON

OFF

Clocks

ON

only MCH BCLK

OFF

only MCH BCLK

OFF

3

SW9H1

1 - 2

Virtual Docking Virtual Battery LID Switch

SW9H2 SW9J1

LEDs and Switches

LED xTA Activity VID0 VID1 VID2 VID3 VID4 VID5 VID6 Num Lock Scroll Lock Caps Lock S3 M0/M1 S4 S5 S0 System Power Good

Switch Page Reference Power Button Reset Button Net Detect Virtual Docking Virtual Battery LID Switch

21 41 41 41 41 41 41 41 42 42 42 57 57 57 57 57 57

55 55 55 42 42 42

Matanzas

Title

Size Document Number Rev

Date: Sheet

ReferencePage CR6J1 CR1B1 CR1B2 CR1B3 CR1B4 CR1B5 CR1B6 CR1B7 CR9G1 CR9G2 CR9G3 CR3G2 CR4H1 CR5H3 CR5H4 CR5H5 CR5J1

SW1C1 SW1C2 SW8E1 SW9H1 SW9H2 SW9J1

NOTES

A

NDA

Device

LAN

IDSEL # AD18 D, C, A, BSlot 3

(AD24 internal)

REQ/GNT # 22

Net Naming Conventions

Suffix # = Active Low Signal

Prefix H = Host M = DDR Memory TP = Test Point (does not connect anywhere else)

B B

Power States

S0 (Full on)/M0

S3 (Suspend to RAM)/M1

S3 (Suspend to RAM)/Moff

S3 (Susp to RAM)/Moff w/WOL_EN

S4 (Suspend to Disk)/M1

S5 (Soft Off)/M1

S4 (Suspend to Disk)/Moff

S5 (Soft Off)/Moff

SLP_S3#

HIGH

LOW

S4_STATE#

HIGH

LOW

A A

5

4

+V1.05S_CPU4,20,37,41,44,54

3

2

1

H_A#[35:3]6

D D

H_ADSTB#06 H_REQ#[4:0]6

H_A#[35:3]6

Layout note: no stub on H_STPCLK TP. H_STPCLK# to be routed in daisy chain fashion from ICH to LPC slot and then to CPU.

C C

H_STPCLK#_R

TP1E1NO_STUFF TP1E1NO_STUFF

H_STPCLK#21,44

Layout Note: TP1E1 should be placed close to J1F4

H_ADSTB#16

H_A20M#21 H_FERR#21

H_IGNNE#21

R2U4 0

H_INTR21 H_NMI21,44 H_SMI#21,44

CPU_RSVD07

CPU_RSVD10

.

TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05 TP_CPU_RSVD06

TP_CPU_RSVD08 TP_CPU_RSVD09

B B

XDP_TMS

XDP_TDI

XDP_BPM#5

XDP_TCK XDP_TRST#

H_A#3 H_A#4

L5

H_A#5

L4

H_A#6

K5

H_A#7

M3

H_A#8

N2

H_A#9 H_A#10

N3

H_A#11

P5

H_A#12

P2

H_A#13

L2

H_A#14

P4

H_A#15

P1

H_A#16

R1

M1

H_REQ#0

K3

H_REQ#1

H2

H_REQ#2

K2

H_REQ#3 H_REQ#4

L1

H_A#17

Y2

H_A#18

U5

H_A#19

R3

H_A#20

W6

H_A#21

U4

H_A#22

Y5

H_A#23

U1

H_A#24

R4

H_A#25

T5

H_A#26

T3

H_A#27

W2

H_A#28

W5

H_A#29

Y4

H_A#30

U2

H_A#31

V4

H_A#32

W3

H_A#33

AA4

H_A#34

AB2

H_A#35

AA3

V1 A6

A5 C4

D5 C6 B4 A3

M4

N5 T2 V3 B2 C3 D2

D22

D3 F6

R1R5 54.9

R2R3 54.9

R1R4 54.9

R2R4 54.9

R2R4 54.9 R2R5 649

R2R5 649

U2E1A

J4

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]#

J1

A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]#

J3

REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]

Merom Ball-out Rev 1a

+V1.05S_CPU4,20,37,41,44,54

1%

1% 1%

1%

.

ADDR GROUP 0 ADDR GROUP 1

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

XDP/ITP SIGNALS

TRST#

DBR#

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RESERVED

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

H_PROCHOT#_D

D21 A24 B25

C7

A22 A21

H_ADS# 6 H_BNR# 6 H_BPRI# 6

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6

H_BREQ# 6

H_INIT# 21 H_LOCK# 6

H_CPURST# 6,20

H_RS#[2:0] 6

H_TRDY# 6 H_HIT# 6

H_HITM# 6

XDP_BPM#1 37 XDP_BPM#2 37

XDP_BPM#3 37 XDP_BPM#4 20 XDP_BPM#5 20

XDP_TCK 20

XDP_TDI 20

XDP_TDO 20

XDP_TMS 20

XDP_TRST# 20

XDP_DBRESET# 20, 55

H_THERMDA 5

H_THERMDC 5

PM_THRMTRIP# 7,21

CLK_CPU_BCLK 37

CLK_CPU_BCLK# 37

CPU_TEST1 CPU_TEST2

R2U956R2U9 56

Connect H_IERR# with no stub to the connector J2F3 and then connect to the 56 ohm pull up Resistor R2U9.

H_IERR#

Place testpoint on H_IERR# with a GND

0.1" away

NO_STUFF

TP1D1

XDP_BPM#0 20

+V1.05S_CPU4,20,37,41,44,54

TP2F1

R3E1

R3E1 1K

1K

1%

1% .

.

NO_STUFF

PM_THRMTRIP# should connect to ICH8 and GMCH without T-ing (No stub)

H_GTLREF

Layout note: Zo=55 ohm,

0.5" max for GTLREF.

C3R1

0.1uF

10%

NO_STUFF

R2U7 1K

NO_STUFF

R2U6 1K

Place C3R1 close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signals.

Place TP close to CPU.

+V1.05S_CPU4,20,37,41,44,54

R3R5

R3R5 1K

1K

1%

1% .

.

R3R4

R3R4 2K

2K

1%

1% .

.

R2F30R2F3 0

H_PROCHOT# 52

H_DSTBN#06 H_DSTBP#06 H_DINV#06 H_D#[63:0]6

CPU_TEST3 CPU_TEST5

CPU_TEST6

H_D#[63:0]6

H_DSTBN#16 H_DSTBP#16 H_DINV#16

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

CPU_TEST4 CPU_TEST6

CPU_BSEL037 CPU_BSEL137 CPU_BSEL237

U2E1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

DATA GRP 0

DATA GRP 2DATA GRP 3

DSTBN[2]# DSTBP[2]#

DATA GRP 1

DSTBN[3]# DSTBP[3]#

MISC

PWRGOOD

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

DINV[2]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

Layout: Connect test point TP3E1 with no stub

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_DPRSTP# 7,21,44,52 H_DPSLP# 21,44

H_CPUSLP# 6,44 PSI# 52

R3T1 27.4 1%R3T1 27.4 1% R3R6 54.9 1%R3R6 54.9 1% R2R7 27.4 1%R2R7 27.4 1% R2R6 54.9 1%R2R6 54.9 1%

H_D#[63:0] 6

H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#[63:0] 6

Layout note: Comp0,2 connect with Zo=27.4ohm, make trace length shorter than 0.5". Comp1,3 connect with Zo=55ohm, make trace length shorter than 0.5".

H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6

H_DPWR# 6

TP3E1

NO_STUFF

R2T3 1K

.

Place Series Resistor on H_PWRGD_XDP Without Stub

5%

H_PWRGD 21,44

H_PWRGD_XDP 20

A A

Intel Confidential

358Tuesday, December 05, 2006

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Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

Intel® Core™2 Duo Mobile Processor (1 of 2)

NDA

2

5

4

3

2

1

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

+VCC_CORE53,54,56

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

CPU_G21

G21

CPU_V6

V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

.

R2T1 and R3T3 are for testing purposes only

R3T3 0

R3T3 0 R2T1 0

R2T1 0

.

H_VID0 52 H_VID1 52 H_VID2 52 H_VID3 52 H_VID4 52 H_VID5 52 H_VID6 52

C3T1

C3T1 270uF

270uF

20%

20% .

.

+V1.05S_CPU3,20,37,41,44,54

+VCC_CORE53,54,56

R2R1

R2R1 100

100

1%

1% .

.

R2R2

R2R2 100

100

1%

1% .

.

C3T4

0.01uF

10%

.

VCCSENSE 52

VSSSENSE 52

R3T2

0

R3R7

0

+VCCA_PROC

C3T3

C3T3 10uF

10uF

20%

20% .

.

Layout Note: Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU.

R3U1 0.01

Layout Note: Place C3T4 near pin-B26

12

NO_STUFF

12

NO_STUFF

1%

+V1.05S9,10,24,48,56

+V1.5S10,11,24,28,48,56

U2E1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

.

+VCC_CORE53,54,56

D D

C C

U2E1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VCCSENSE

VSSSENSE

B B

A A

Intel Confidential

458Tuesday, November 21, 2006

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Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

Intel® Core™2 Duo Mobile Processor (2 of 2)

NDA

2

5

4

3

2

1

D D

C C

Layout Note: Route H_THERMDA and H_THERMDC on same layer w/ 10 mil trace & 10 mil spacing. Route away from noise sources with ground guard tracks on each side.

H_THERMDA3 H_THERMDC3

GND0

GND0 GND1

GND1

Thermal Diode Connector

J3B2 Default Stuffing: 1-2 3-4 Option Stuffing: 1-X 3-X

1 3

J4A1

J4A1 3Pin_Recepticle

3Pin_Recepticle

12

THERMDNTHERMDP

GND2

3 4 5 6

GND3

J3B2

2X2HDR

NO_STUFF

THERM_DXP

2 4

THERM_DXN

R3N26 499

R3N25 499

+V3.3S7,10,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R3N21

R3N21 10K

10K

5%

5% .

.

1%

.

1%

.

ADT_THERM_DXP

C3N10

C3N10 1000pF

1000pF

ADT_THERM_DXN

5%

.

ADT_THM# THRM_ALERT#

CPU Thermal Sensor

C3N9

0.1uF

20%

20% .

.

U3B4

1

VDD

2

D+

3

D-

ALRT#/THM2#

4

THM#

ADT7461A-TEMP MON

SCLK

SDATA

GND

8 7 6 5

+V3.3S7,10,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R3N19

R3N22

10K

5%

.

SMB_THRM_CLK 12,42,44

SMB_THRM_DATA 12,42,44

R3N20 0

NO_STUFF

Note: No-Stuff R3N20 for normal operation, No Stuff (R9G18 P42) if R3N20 is stuffed

PM_THRM# 12,23,42,44

CPU Fan Power Control

+V5S11,12,16..18,24,30..32,34,41,49,50,52,53,55..57

C3N3

C3N5

0.1uF

4.7uF

10%

B B

R3N14 15K

CPU_PWM_FAN42,44

R3N14 15K

OPA567_POSIN

1%

.

10%

.

1

101112

EU3B1

V+

_

C3B4

C3B4 1uF

1uF

10%

.

_

8

OPA567

9

+

V-

456

HS

TF

EN

EN IF

IF

IS

13

OPA567_ISIN_R

2

OUT

3

.

7

OPA567_NEGIN

R3N7

R3N7 20K

20K

5%

5% .

.

VOUT_OPAMP

CR2N1

CR2N1 BAT54

BAT54

R3N8

1.74K

1%

1% .

.

R3N10

3.32K

1%

1% .

.

2

CPU_TACHO_R_FAN

11332

3

1

J2B3

CONN3_HDR

.

R2N5 0

A A

5

4

3

+V3.3S7,10,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R2N8

R2N8 1K

1K

1%

1% .

.

CPU_TACHO_FAN 42,44

.

Intel Confidential

558Tuesday, December 05, 2006

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Title

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CPU Thermal Sensor & Fan

A

NDA

2

5

D D

+VCCP_GMCH10

R4E5

R4E5 221

221

1%

1% .

.

R4E4

R4E4 100

100

1%

1% .

.

R4E3

C C

R4E3

24.9

1%

1% .

.

+VCCP_GMCH10

R4E2

54.9

1%

+VCCP_GMCH10

R4E1

54.9

1%

C4E10

0.1uF

20%

20% .

.

H_RCOMP

H_SCOMP

H_SCOMP#

H_SWING

B B

+VCCP_GMCH10

R4F7

R4F7 1K

1K

1%

1% .

H_AVREF

H_DVREF

R4F4

R4F4 0

0

.

R4F2

R4F2 2K

2K

1%

1% .

.

C4E12

0.1uF

10%

4

U5E1A

M10

W10

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

AB2

AD7

AB1

AC6

AE2

AC5

AG3

AH8

AJ14

AE9 AE11 AH12

AH5

AE7

AE5

AH2 AH13

E2

G2 G7 M6 H7 H3 G4

F3 N8 H2

N12

N9 H5

P13

K9 M2

Y8

V4 M3

J1 N5 N3

W6 W9

N2

Y7

Y9

P4

W3

N1

Y3

AJ9

AJ5 AJ6 AJ7

AJ2 AJ3

B3 C2

W1 W2

B6

E5

B9

A9

U5E1A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CRESTLINE_1p0

H_D#[63:0]3

H_CPURST#3,20

H_CPUSLP#3,44

.

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

3

HOST

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

2

H_A#[35:3] 3

H_DINV#0 3 H_DINV#1 3 H_DINV#2 3 H_DINV#3 3

H_DSTBN#0 3 H_DSTBN#1 3 H_DSTBN#2 3 H_DSTBN#3 3

H_DSTBP#0 3 H_DSTBP#1 3 H_DSTBP#2 3 H_DSTBP#3 3

H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 H_BNR# 3

H_BPRI# 3

H_BREQ# 3

H_DEFER# 3

H_DBSY# 3 CLK_MCH_BCLK 37 CLK_MCH_BCLK# 37 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3

H_TRDY# 3

H_RS#[2:0] 3

1

H_REQ#[4:0] 3

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

Mobile Intel® 965 Express Chipset Family (1 OF 6)

A

NDA

2

658Tuesday, December 05, 2006

1

Intel Confidential

1.5

of

5

U5E1B

P36

MCH_RSVD_1 MCH_RSVD_2 MCH_RSVD_3 MCH_RSVD_4 MCH_RSVD_5 MCH_RSVD_6 MCH_RSVD_7 MCH_RSVD_8

MCH_RSVD_10 MCH_RSVD_11 MCH_RSVD_12 MCH_RSVD_13

D D

MCH_RSVD_14

MCH_RSVD_20

MCH_RSVD_21

MCH_RSVD_24 MCH_RSVD_25

MCH_RSVD_41 MCH_RSVD_42 MCH_RSVD_43 MCH_RSVD_44 MCH_RSVD_45

C C

MCH_CFG_[17:3]12

MCH_CFG_18 MCH_CFG_1912 MCH_CFG_2012,19 PM_DPRSTP#_R

B B

PM_BMBUSY#23

H_DPRSTP#3,21,44,52 PM_EXTTS#013,15 PM_EXTTS#114,15

DELAY_VR_PWRGOOD23,52

PM_THRMTRIP#3,21

PM_DPRSLPVR23,44,52

PM_BM_BUSY# is renamed as PMSYNC# in

Mobile Intel® 965 Express

Chipset Family EDS

A A

TP_MCH_RSVD9

TP_MCH_RSVD22 TP_MCH_RSVD23

TP_MCH_RSVD26 TP_MCH_RSVD27 TP_MCH_RSVD28 TP_MCH_RSVD29 TP_MCH_RSVD30 TP_MCH_RSVD31

TP_MCH_RSVD34 TP_MCH_RSVD35 TP_MCH_RSVD36

MCH_BSEL037 MCH_BSEL137 MCH_BSEL237

R5F13 0R5F13 0 TP5U1 NO_STUFFTP5U1 NO_STUFF R5U22 0R5U22 0

R5U23 0R5U23 0

R5T4 0R5T4 0

MCH_CFG_20_R

PM_BMBUSY#_R

PM_DPRSTP#_R PM_EXTTS#1_R RST_IN#_MCH

R5U15 0R5U15 0

TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16

C5T18

0.1uF

10%

.

MCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17

DPRSLPVR_R

+V1.8_GMCH9,10

R4D2

R4D2 20

20

.

. 1%

1%

R4D1

R4D1 20

20

.

. 1%

1%

P37 R35

N35 AR12 AR13 AM12 AN13

J12 AR37 AM36

AL36

AM37

D20

H10 B51

BJ20 BK22 BF19 BH20 BK18

BJ18 BF23 BG23 BC23 BD24

BH39

AW20

BK20

A35 B37 B36 B34 C34

P27 N27 N24 C21 C23 F23 N23

G23

J20 C20 R24

L23

J23 E23 E20 K23 M20 M24

L32

N33

L35

G41

L39

L36

J36

AW49

AV20

N20 G36

BJ51 BK51 BK50

BL50

BL49

BL3 BL2 BK1

BJ1

E1

A5 C51 B50 A50 A49 BK2

CRESTLINE_1p0

SM_RCOMP SM_RCOMP#

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31

RSVD34 RSVD35 RSVD36

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16

CFGRSVD

PM

NC

5

4

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

SM_VREF_0 SM_VREF_1

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLK_REQ#

ICH_SYNC#

TEST_1 TEST_2

BK14 BK31

BL31 AR49

AW4

B42 C42 H48 H47

K44 K45

AN47 AJ38 AN42 AN46

AM47 AJ39 AN41 AN45

AJ46 AJ41 AM40 AM44

AJ47 AJ42 AM39 AM43

E35 A39 C38 B39 E36

AM49 AK50 AT43 AN49 AM50

H35 K36 G39 G40

A37 R32

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

DDR MUXINGCLK

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

DMI

GFX_VR_EN

GRAPHICS VID

ME

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MISC

MCH_TEST_2

4

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

R5T7

R5T7 20K

20K

5%

5% .

.

3

M_CLK_DDR0 13 M_CLK_DDR1 13 M_CLK_DDR3 14 M_CLK_DDR4 14

M_CLK_DDR#0 13 M_CLK_DDR#1 13 M_CLK_DDR#3 14 M_CLK_DDR#4 14

M_CKE0 13,15 M_CKE1 13,15 M_CKE3 14,15 M_CKE4 14,15

M_CS#0 13,15 M_CS#1 13,15 M_CS#2 14,15 M_CS#3 14,15

M_ODT0 13,15 M_ODT1 13,15 M_ODT2 14,15 M_ODT3 14,15

DREFCLK 37 DREFCLK# 37 DREFSSCLK 37 DREFSSCLK# 37

CLK_PCIE_3GPLL 37 CLK_PCIE_3GPLL# 37

DFGT_VID_0 49 DFGT_VID_1 49 DFGT_VID_2 49 DFGT_VID_3 49 DFGT_VR_EN 49

MCH_CLVREF

SDVO_CTRLCLK 19 SDVO_CTRLDATA 19

CLK_MCH_OE# 37

MCH_ICH_SYNC# 23

R5T130R5T13 0

EPOT_WIPER

Default For EVMC No_Stuff

+V1.8_GMCH9,10

R5R2

R5R2 1K

1K

1%

NO_STUFF

R5R3

R5R3 1K

1K

1%

NO_STUFF

DMI_TXN[3:0] 22

DMI_TXP[3:0] 22

DMI_RXN[3:0] 22

DMI_RXP[3:0] 22 PEG_TX[15:0] 19

CL_CLK0 23 CL_DATA0 23 MPWROK 23,47

CL_RST#0 23

MCH_TEST_1

R7N4

No_Stuff Stuff

Layout Note: Place 150 Ohm termination resistors and jumpers close to GMCH

Layout Note: Place 150 Ohm termination resistors close to GMCH

+V1.25M_AXD10

C5D7

0.1uF

10%

PLT_RST#19,22,25,26,39,40,42,57

R7N4 0

NO_STUFF

R7N2

Stuff

L_BKLT_CTRL17 L_BKLT_EN17

L_CTRL_CLK17,20

L_CTRL_DATA17,20

LVDS_DDC_CLK17

LVDS_DDC_DATA17

LVDS_VDD_EN17

M_VREF_MCH 47,50

TVA_DAC18 TVB_DAC18

TVC_DAC18

R5U7 150R5U7 150 R5U5 150R5U5 150 R5U6 150R5U6 150

CRT_HSYNC16

CRT_VSYNC16

R5D6

R5D6 1K

1K

1%

R5D7 0

NO_STUFF

R5D8

R5D8 392

392

1%

R5R4

LVDS_IBG

R7N2

2.37K

1%

.

3

TP6E1

NO_STUFF

R5U12 150 1%R5U12 150 1% R5U4 150 1%R5U4 150 1% R5U13 150 1%R5U13 150 1%

CRT_BLUE16

CRT_GREEN16

CRT_RED16

CRT_DDC_CLK_MCH16

CRT_DDC_DATA_MCH16

R5U16

EV_VCC_V1.25_AXD

RST_IN#_MCH

100

R5U27 0R5U27 0

LVDSA_CLK#17 LVDSA_CLK17 LVDSB_CLK#17 LVDSB_CLK17

LVDSA_DATA#017 LVDSA_DATA#117 LVDSA_DATA#217 LVDSA_DATA#317

LVDSA_DATA017 LVDSA_DATA117 LVDSA_DATA217 LVDSA_DATA317

LVDSB_DATA#017 LVDSB_DATA#117 LVDSB_DATA#217 LVDSB_DATA#317

LVDSB_DATA017 LVDSB_DATA117 LVDSB_DATA217 LVDSB_DATA317

R5U11 0R5U11 0 R5U3 0R5U3 0 R5U14 0R5U14 0

TV_DCONSEL0_MCH18 TV_DCONSEL1_MCH18

R5U17 30.1

R5U18 30.1

L_VDD_EN_R

LVDS_IBG LVDS_VBG

MCH_TVA_DAC MCH_TVB_DAC MCH_TVC_DAC

HSYNC

.

CRTIREF

1.3k_5%

VSYNC

.

+V1.8_GMCH9,10

R5R1

R5R1 1K

1K

0.10%

R5D5

3.01k

R5D3

R5D3 1K

1K

0.10%

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

2

U5E1C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

C48

LVDSA_DATA#_3

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

D47

LVDSA_DATA_3

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

B44

LVDSB_DATA#_3

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

C44

LVDSB_DATA_3

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

CRESTLINE_1p0

SM_RCOMP_VOH

C5R5

C5R6

2.2uF

0.01uF

10%

10% 402

402

SM_RCOMP_VOL

C5D4

C5D3

0.01uF

2.2uF

10%

402

Mobile Intel® 965 Express Chipset Family (2 OF 6)

NDA

LVDS

TV VGA

PEG_COMPO

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_TX#_10 PEG_TX#_11

PCI-EXPRESS GRAPHICS

PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_COMPI

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

+V3.3S5,10,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

N43 M43

J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41

J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42

N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44

M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

2

PEG_COMP

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8

PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

R5F6 10KR5F6 10K R5P1 10KR5P1 10K R5P4 10KR5P4 10K

758Tuesday, December 05, 2006

1

+VCC_PEG10

R5T2 24.9

1%

PEG_RX#[15:0] 19

PEG_RX[15:0] 19

PEG_TX#[15:0] 19

CLK_MCH_OE#

PM_EXTTS#0 PM_EXTTS#1

Intel Confidential

1.5

of

5

4

3

2

1

M_A_DQ[63:0]13

D D

C C

B B

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AR43

AW44

BA45 AY46 AR41 AR45 AT42

AW47

BB45 BF48 BG47

BJ45 BB47 BG50 BH49 BE45

AW43

BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40

AW40

AT39

AW36 AW41

AY41 AV38 AT38 AV13 AT13

AW11

AV11 AU15 AT11 BA13 BA11 BE10 BD10

BG10

AW9

AN10

AN11

BD8 AY9

BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8

AT9 AN9 AM9

U5E1D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CRESTLINE_1p0

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

BL17

SA_CAS#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

SA_WE#

AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BJ29

BE18 AY20

BA19

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6

M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

TP_SA_RCVEN#

M_A_BS1 13,15 M_A_BS2 13,15 M_A_CAS# 13,15

M_A_DM[7:0] 13

M_A_DQS[7:0] 13

M_A_DQS#[7:0] 13

M_A_A[13:0] 13,15

M_A_A14 14 M_B_A14 15 M_A_RAS# 13,15

M_A_WE# 13,15

M_B_DQ[63:0]14

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AP49

AR51 AW50 AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50 BJ44 BJ43

BL43 BK47 BK49 BK43 BK42

BJ41

BL41

BJ37

BJ36 BK41

BJ40

BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

BJ10

BK10

BK5 BK9

BF4 BH5 BG1 BC2 BK3 BE4 BD3

BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2

BL9 BL5

BJ8 BJ6

BJ2

U5E1E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CRESTLINE_1p0

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS# SB_DM_0

SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

SB_RAS#

SB_RCVEN#

DDR SYSTEM MEMORY B

SB_WE#

AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 BE24

AV16 AY18

BC17

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

TP_SB_RCVEN#

M_B_BS0 14,15M_A_BS0 13,15 M_B_BS1 14,15 M_B_BS2 14,15 M_B_CAS# 14,15

M_B_DM[7:0] 14

M_B_DQS[7:0] 14

M_B_DQS#[7:0] 14

M_B_A[13:0] 14,15

M_B_RAS# 14,15

M_B_WE# 14,15

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

Mobile Intel® 965 Express Chipset Family (3 OF 6)

A

NDA

2

858Tuesday, December 05, 2006

1

Intel Confidential

1.5

of

5

4

3

2

1

+V3.3S_SYNC10 +VCC_GMCH

R5U21 10

1 2

T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31

AW45 BC39 BE39 BD17 BD4 AW8 AT6

+VGFX_CORE49

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

4

C4R7

0.1uF

10%

.

R3F8 0.002

C4R8

0.1uF

10%

.

R6E1 0.002

1%

Place C5C7 where LVDS and DDR2 taps.

C4R6

C4R5

0.22uF

1%

12

C4T2

+

330uF

3

20%

370mils from the Edge Cavity Capacitors

C5R12

0.47uF

C5E3

C5E3 270uF

270uF

20%

308 mils from the Edge

+VGFX_CORE49+VCC_GFXCORE49

12

C4T1

+

330uF

3

20%

+V1.05M 48,56

+V1.8 10,13,14,47,50,56

R6R1

1 2

0.002

R5D1 0.002

C5C7

0.1uF

10%

.

C5R13

1.0uF

20%

20% 402

402

.

+VCC_AXM

C5R16

1.0uF

20%

20% 402

402

.

1%

C5R7

22uF

20%

C5C8

C5C8 330uF

330uF

20%

C5T7

0.47uF

C5R11

0.22uF

20%

C5T1

C5T1 22uF

22uF

20%

20% SMC0805

SMC0805

3

+VCC_GMCH

D D

R4F110R4F11

MCH_VCC_13

0

+V1.8_GMCH7,10

C C

B B

+VGFX_CORE49

A A

AT35 AT34 AH28 AC32 AC31 AK32

AJ31

AJ28 AH32 AH31 AH29 AF32

AU32 AU33 AU35 AV33

AW33 AW35

AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35

BJ32

BJ33

BJ34 BK32 BK33 BK34 BK35

BL33 AU30

W13

W14 AA20

AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31

AJ20 AN14

R30

R20 T14

Y12

U5E1G

VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34

CRESTLINE_1p0

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

5

VCCGFOLLOW

5%

C5T6

C5T8

0.22uF

20%

Cavity Capacitors

C5T9

C5T2

10uF

1uF

20%

.

C5R3

0.22uF

20%

C5D5

22uF

20%

PLACE ON THE EDGE

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

CR5F2

13

BAT54

+VCC_GMCH+V1.05S4,10,24,48,56

U5E1F

AB33

C5T4

0.1uF

0.22uF

10%

20%

.

SMC0402

.

SMC0402

C5R19

C5R19 22uF

22uF

20%

20% SMC0805

SMC0805

C5R15

0.1uF

10%

.

Cavity CapacitorsPLACE ON THE EDGE

C5D1

22uF

20%

Mobile Intel® 965 Express Chipset Family (4 OF 6)

NDA

C5T5

0.1uF

10%

.

SMC0402

.

SMC0402

C5R14

0.1uF

10%

.

+V1.8_GMCH 7,10

C5T3

0.1uF

10%

.

SMC0402

.

SMC0402

C5R18

0.1uF

10%

.

AB36 AB37 AC33 AC35 AC36 AD35 AD36

AF33

AF36 AH33 AH35 AH36 AH37

AJ33

AJ35 AK33 AK35 AK36 AK37 AD33

AJ36 AM35

AL33

AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36

AL24

AL26

AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33

AL29

AL31

AL32 AR31 AR32 AR33

Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37

CRESTLINE_1p0

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50

VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19

VCC NCTF

POWER

2

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15

VSS NCTF

VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21

VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7

VCC AXM NCTF

Intel Confidential

958Tuesday, December 05, 2006

of

1

T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28

A3 B2 C1 BL1 BL51 A51

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

+VCC_AXM

1.5

5

6

+V3.3S_TVDAC11,50,56

+V1.25S

12

R5U24

0.002

0.002 L5F3

L5F3

1 2

10uH

D D

C C

10uH

10%

L5F2

V1.25S_MCH_PLLV1.25M_MCH_PLL2

1 2

10uH

10%

+V1.25M

12

R4D6

0.002

0.002 FB4D1

FB4D1

120ohm@100MHz

FB4D2

120ohm@100MHz

R4D9 0.51

V1.25M_MPLL_RC

C4D4

C4D4 22uF

22uF

20%

+V3.3S_TVDAC

FB5F1

180ohm@100MHz

NOTE: CAPS USED IN +V3.3S_TVDAC should be within 250mils of edge of MCH

12

C5U4

C5U4 470uF

470uF

20%

12

C5F7

C5F7 470uF

470uF

20%

+V1.25M_HPLL

C4D2

C4D2 22uF

22uF

20%

+V1.25M_MPLL

1%

C5F6

C5F6 10uF

10uF

80%

180ohm@100MHz

+V1.25S_DPLLA

C5T14

0.1uF

10%

.

+V1.25S_DPLLB

C5T11

0.1uF

10%

.

5,7,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

C4D3

0.1uF

10%

.

C4E1

0.1uF

10%

.

+VCCA_TVDAC

C5F3

0.1uF

10%

.

C5F5

0.1uF

10%

.

B B

C5F1

0.1uF

10%

.

+V1.5S,5

R5U8

1 2

0.002

+V1.25S

R5E3

1 2

A A

0.002

TVDAC_FB

R5U20

100

PEGPLL_FB_L

220ohm_at_100MHz

+V1.25S_PEGPLL_RC

C5E6

C5E6 10uF

10uF

20%

5

QTVDAC_FB

R5E2

FB5F2

+VCCA_TVDAC

R5U19 0.03_1%R5U19 0.03_1%

+V3.3S

12

+

1

3

2

.

1

3

2

.

1

3

2

.

C5T17

0.1uF

10%

.

C5T15

0.1uF

10%

.

FB5E1

1.00

1%

+V3.3S_CRTDAC

12

R6E3

1 2

+V1.25M37,48,56,57

1 2

C4D1

C4D1 100uF

100uF

+V1.25M37,48,56,57

1 2

+V3.3S_TVDACA

C5E13

C5E13 22nF

22nF

20%

R5T8 0

+V3.3S_TVDACB

C5E14

C5E14 22nF

22nF

20%

R5T9 0

+V3.3S_TVDACC

C5E12

C5E12 22nF

22nF

20%

R5T10 0

+V1.5S_TVDAC

C5T16

C5T16 22nF

22nF

123

20%

.

C5T12

C5T12 22nF

22nF

123

20%

.

123

C5F4

0.1uF

10%

.

VCCA_TVDAC_ATVBG

+V3.3S_PEG_BG

0.002

R4R2

0.002

R5P5

0.002

NO_STUFF

+V1.5S_QDAC

C5T20

C5T20 1uF

1uF

20%

C5E4

0.1uF

10%

.

C5E15

C5E15 22nF

22nF

20%

.

NO_STUFF

C5E7

0.1uF

10%

.

+V1.25M_A_SM_LR

+V1.25M_R

+V1.5S_TVDAC

+V1.25S_PEGPLL

R5E4

R5E4 0

0

C5F2

0.1uF

10%

.

+V1.25M_A_SM_CK

0

R5P60R5P6

R5T17

R5T17 0

0

NO_STUFF

3

R4R1

.

R5T160R5T16 0

2

NO_STUFF

4

+V3.3S5,7,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

+VCCA_CRTDAC

+V3.3S_DAC_BG

C5E11

C5E11 22nF

22nF

1

20%

.

NO_STUFF

+V1.8_TXLVDS

+V1.25M_A_SM

0

C4R2

22uF

20%

NO_STUFF

C4R4: Edge Cap

C5R2

C5R2 1uF

1uF

20%

NO_STUFF

+V3.3S_TVDACC

+V1.5S_TVDAC

V1.25M_MCH_PLL2

C4R9

0.1uF

10%

.

4

R5F9

1 2

0.002

R5T12

R5T12 0

0

C4R4

4.7uF

10%

.

C5R8

C5R8 1uF

1uF

20%

+V3.3S_TVDACB

+V1.5S_QDAC

Topside Cap

R5E5

1 2

C5U3

0.1uF

10%

.

+V1.25S_DPLLA +V1.25S_DPLLB +V1.25M_HPLL +V1.25M_MPLL

C5E9

C5E9 1000pF

1000pF

10%

10% .

.

+V1.25S_PEGPLL

C5R9:Cavity Cap

C4R3

22uF

20%

.

C5R10

C5R1

0.1uF

22uF

10%

20%

.

+V3.3S_TVDACA

+V1.5S_TVDAC_R

+V1.25S_PEGPLL

C5E5

0.1uF

10%

.

+V1.8_DLVDS59+V1.89,13,14,47,50,56

0.002

3

+V3.3S_SYNC9

U5E1H

C5R9

1.0uF

20%

20% 402

402

C5E8

1.0uF

20%

20% 402

402

H49

AM2

U51

AW18

AV19 AU19 AU18 AU17

AT22

AT21

AT19

AT18

AT17 AR17 AR16

BC29

BB29

C25 C27

M32

N28 AN2 U48

H42

J32 A33

B33

A30 B32

B49

AL2

A41 B41

K50 K49

B25 B27

B28 A28

L29

J41

VCCSYNC VCCA_CRT_DAC_1

VCCA_CRT_DAC_2

VCCA_DAC_BG VSSA_DAC_BG

VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL

VCCA_LVDS VSSA_LVDS

VCCA_PEG_BG VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5

VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2

VCCA_SM_CK_1 VCCA_SM_CK_2

VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2

VCCD_CRT VCCD_TVDAC

VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS_1

VCCD_LVDS_2

CRESTLINE_1p0

C5U1

C5U1 10uF

10uF

20%

NO_STUFF

+V3.3S

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

+V1.05S4,9,24,48,56

1

CR5F1

CR5F1 BAT54

BAT54

V1_05S_SD

3 12

R5U28

R5U28 10

10

5%

R5U2

1 2

AXD

VCC_AXD_NCTF

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

PEG

VCC_RXR_DMI_1 VCC_RXR_DMI_2

DMI

5,7,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V3.3S_HV

0.002

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

U3

VTT_8

U2

VTT_9

U1

VTT_10

T13

VTT_11

T11

VTT_12

T10

VTT_13

T9

VTT

VTT_14

T7

VTT_15

T6

VTT_16

T5

VTT_17

T3

VTT_18

T2

VTT_19

R3

VTT_20

R2

VTT_21

R1

VTT_22

AT23

VCC_AXD_1

AU28

VCC_AXD_2

AU24

VCC_AXD_3

AT29

VCC_AXD_4

AT25

VCC_AXD_5

AT30

VCC_AXD_6

AR29

B23

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

AJ50

VCC_DMI

BK24 BK23 BJ24 BJ23

A43

C40

VCC_HV_1

B40

VCC_HV_2

HV

AD51

VCC_PEG_1

W50

VCC_PEG_2

W51

VCC_PEG_3

V49

VCC_PEG_4

V50

VCC_PEG_5

AH50 AH51

A7

VTTLF1

F2

VTTLF2

AH1

VTTLF3

VTTLF

+VCC_DMI +VCC_PEG 7

To use seperate filters for VCC_PEG & VCC_RXR_DMI rails No-Stuff R5E1 and stuff L6E2, C5E2 & C6E11

C5E10

0.1uF

10%

.

C4E4

C4E7

4.7uF

10%

PLACE ON THE EDGE

+V1.25M_AXD7

+V1.25S_AXF

+V3.3S_HV

+VCC_DMI

VTTLF_CAP1 VTTLF_CAP2 VTTLF_CAP3

C4E2

0.47uF

R5E1 0

.

Matanzas

Title

Size Document Number Rev

Date: Sheet

Mobile Intel® 965 Express Chipset Family (5 OF 6)

A

NDA

3

C4E6

2.2uF

10%

C5R17

1.0uF

20%

20% 402

402

C4E11

1.0uF

20%

20% 402

402

+V1.25S_DMI

+V1.8_SM_CK

C5D6

0.1uF

10%

+VCC_PEG7

C4E8

0.47uF

2

NO_STUFF

C4R1

C4R1 22uF

22uF

20%

C4E15

C4E15 10uF

10uF

20%

.

+V1.8_TXLVDS

C4E14

0.47uF

2

C4E5

0.47uF

R4F50R4F5

1 2

C5D2

22uF

20%

.

NO_STUFF

+VCCP_GMCH6 +V1.05S 4,9,24,48,56

C4E3

C4E3 270uF

270uF

20%

R4D4

0 5%

L4R1 5.6nH

NO_STUFF

+V1.25S_AXF_LR

0

C5T13

C5T13 1000pF

1000pF

10%

10% .

.

+

C6E10

+

C6E10

C5T10

220uF

10uF

10%

20%

NO_STUFF

C6E11

C5E2

+

220uF

10uF

10%

20%

R5U26

1 2

+V1.25M_AXD_LR

C5E1

0.1uF

10%

.

1 2

1uH

30%

R5D4

+V1.8_SMCK_RC

1.001%

L5F1

1 2

1uH

20%

C5U2

+

.

220uF

10%

L6E1

+V1.05S_PEG_LR

91nH

20%

L6E2

91nH

20%

20% NO_STUFF

NO_STUFF

0.002

R4F9

1 2

L5D1

+V1.05S_DMI_LR

R4C27

12

0.002

+V1.25S24,56,57

0.002

R6D5

0.002

+V1.8_SM_CK_RR

C5R4

C5R4 10uF

10uF

20%

V_TXLVDS_PM

1

+V1.25M37,48,56,57

+V1.25S 24,56,57

R5D2

1 2

R5U25

1 2

NO_STUFF

R6T13

1 2

0.002

R6T14

1 2

0.002

.

NO_STUFF

R6E2

1 2

0.002

R6T11

1 2

0.002

.

10 58Tuesday, December 05, 2006

1

+V1.8_GMCH 7,9

0.002

+V1.8 9,13,14,47,50,56

0.002

+V1.25S 24,56,57

+V1.05S 4,9,24,48,56

+V1.25S 24,56,57

+V1.05S 4,9,24,48,56

Intel Confidential

of

1.5

5

U5E1I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

AB23

VSS_9

AB26

D D

C C

B B

A A

AB28 AB31 AC10 AC13

AC3 AC39 AC43

AC47

AD1 AD21 AD26 AD29

AD3 AD41 AD45 AD49

AD5 AD50

AD8 AE10 AE14

AE6 AF20 AF23 AF24 AF31

AG2 AG38 AG43 AG47 AG50

AH3 AH40 AH41

AH7

AH9

AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45

AJ49 AK20 AK21 AK26 AK28 AK31 AK51

AM11 AM13

AM3

AM4

AM41 AM45

AN1 AN38 AN39 AN43

AN5

AN7

AP4

AP48 AP50

AR11

AR2 AR39 AR44 AR47

AR7

AT10 AT14 AT41 AT49

AU1 AU23 AU29

AU3 AU36 AU49 AU51

AV39 AV48

AW1 AW12 AW16

AL1

VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CRESTLINE_1p0

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

5

4

U5E1J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0

VSS

VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

MCH_VSS_302 MCH_VSS_303 MCH_VSS_304 MCH_VSS_305

3

R4F10 0R4F10 0 R5F11 0R5F11 0 R5F10 0R5F10 0 R5F8 0R5F8 0

3

2

+V5S5,12,16..18,24,30..32,34,41,49,50,52,53,55..57

3

PM_SLP_S3#23,26,42,44,45,48,56,57

1

2

Matanzas

Title

Size Document Number Rev

Date: Sheet

Mobile Intel® 965 Express Chipset Family (6 OF 6)

NDA

A

NDA

A

NDA

A

C3E1

1.0uF

10%

Q4U1

Q4U1 BSS138

BSS138

R3T6

R3T6 10K

10K

5%

U3E1 SC1563U3E1 SC1563

5

IN

1

SHDN

GND2ADJ

PM_SLP_S3_SHDN2

R3T7

R3T7 100

100

5%

5% NO_STUFF

NO_STUFF

2

4

OUT

3

TVDAC_ADJ2

V3.3S_TVDAC_R2

R3T4

17.8K

1%

R3T5

R3T5 10K

10K

1%

C3F1

C3F1 22uF

22uF

C4E9

0.1uF

10%

.

R3E2

0.011%

11 58Tuesday, December 05, 2006

1

+V1.5S4,10,24,28,48,56

1

CR4F1

CR4F1 BAT54

BAT54

NO_STUFF

3

V1_5SFOLLOW

12

R4U1

R4U1 10

10

5%

5% NO_STUFF

NO_STUFF

+V3.3S_TVDAC10,50,56

Intel Confidential

of

1.5

5

4

3

2

1

Layout Note: Location of all MCH_CFG strap resistors needs to be close to trace to minimize stub

MCH_CFG_57

DMI X2 Select

D D

MCH_CFG_5

Low = DMIx2 High = DMIx4 (default)

R1D4

4.02K

1%

1% NO_STUFF

NO_STUFF

SDVO/PCIE Concurrent Operation

MCH_CFG_20 Low = Only SDVO or PCIE x1 is operational (default)

High = SDVO and PCIE x1 are operating simultaneously via the PEG port

MCH_CFG_207,19

+V3.3S5,7,10,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R6P3

4.02K

1%

1% NO_STUFF

NO_STUFF

GMCH Fan Power Control

MCH_CFG_167

C3P3

0.1uF

FSB Dynamic ODT

MCH_CFG_16

Low = Dynamic ODT Disabled High = Dynamic ODT Enabled (default)

R1E1

4.02K

1%

1% NO_STUFF

NO_STUFF

R4P2 15K

MCH_PWM_FAN42,44

R4P2 15K

1%

0.1uF

10%

OPA567_POSIN_R

.

C C

MCH_CFG_97

R1E7

PCI Express Graphics Lane

MCH_CFG_9 Low = Reverse Lane (default)

High = Normal operation

R1E7

4.02K

1%

1% .

.

C4C18

C4C18 1uF

1uF

10%

C3C8

4.7uF

10%

EU4C1

8 9

+V5S5,11,16..18,24,30..32,34,41,49,50,52,53,55..57

_

OPA567

+

1

V+

HS

V-

456

101112

TF

EN

EN IF

IF

IS

13

OPA567_ISIN_MCH_R

OUT

7

R4P1

R4P1 20K

20K

5%

2

MCH_TACHO_OP_FAN

3

.

OPA567_NEGIN_R

R3P1

1.74K

1%

R4C26

3.32K

1%

CR3P1

CR3P1 BAT54

BAT54

+V3.3S5,7,10,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R3P2

R3P2 1K

1K

1%

R3P3 0R3P3 0

MCH_TACHO_FAN 42,44

2

11332

MCH_TACHO_R_FAN

J3C1

3

1

CONN3_HDR

+V3.3S5,7,10,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

DMI Lane Reversal

MCH_CFG_19

B B

XOR / ALLZ / Clock Un-gating

A A

MCH_CFG_12 MCH_CFG_13 Configuration

00 01 10

Low = Normal (default) High = Lanes Reversed

MCH_CFG_197

Clock Gating Disabled XOR Mode Enabled All-Z Mode Enabled

11

Normal Operation (Default)

MCH_CFG_127

MCH_CFG_137

5

R5F15

4.02K

1%

1% NO_STUFF

NO_STUFF

R1E11

4.02K

1%

1% NO_STUFF

NO_STUFF

Place in IMVP_6 Hot Spot

R1E10

4.02K

1%

1% NO_STUFF

NO_STUFF

Q3C6

+V3.3S5,7,10,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

C3B6

R3B23

R3B23 10K

10K

1%

1

2N3904

7481_D1P_Q

7481_D1N_Q

3

2

R3B20 0R3B20 0

R3B22 0R3B22 0

C3N8

C3N8 1000pF

1000pF

10%

7481_D1P 7481_D1N

4

C3B6

0.1uF

20%

U3B3

1

VDD

2

D1+

3

D1-

ALRT#/THM2#

4

THM#

5

GND

ADT7481ARMZ-1 TEMP MON

Place ADT7481 near Air inlet not under SODIMM

SCLK

SDATA

D2+

10 9 8 7 6

D2-

7481_THRM#

3

IMVP6 & Amb Thermal sensors

+V3.3S5,7,10,16..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R3B24

R3B24 10K

10K

1%

SMB_THRM_CLK 5,42,44

7481_D2P 7481_D2P_Q

7481_D2N

Title

Size Document Number Rev

Date: Sheet

SMB_THRM_DATA 5,42,44

R3B19 0R3B19 0 C3N7

C3N7 1000pF

1000pF

10%

Matanzas

Mobile Intel® 965 Express Chipset Family STRAPPING

A

NDA

R3B21 0R3B21 0

7481_D2N_Q

2

7481_THRM2#

3

Q3B1

1

2N3904

2

Spare sensor, For Amb. temp sensor

R3N24 0

NO_STUFF

R3N23 0

NO_STUFF

12 58Tuesday, November 21, 2006

1

Intel Confidential

of

PM_THRM# 5,23,42,44

1.5

5

4

3

2

1

D D

J5P1A

M_A_A[13:0]8,15

M_A_A148

M_A_BS28,15 M_A_BS08,15

M_A_BS18,15 M_CS#07,15 M_CS#17,15

R3C2

R3C2 10K

10K

5%

M_CLK_DDR07 M_CLK_DDR#07 M_CLK_DDR17 M_CLK_DDR#17 M_CKE07,15 M_CKE17,15 M_A_CAS#8,15 M_A_RAS#8,15 M_A_WE#8,15

SMB_CLK_M214,15,23 SMB_DATA_M214,15,23

M_ODT07,15 M_ODT17,15 M_A_DM[7:0]8

M_A_DQS[7:0]8

M_A_DQS#[7:0]8

C C

Note: SO-DIMM0 SPD Address is 0xA0 SO-DIMM0 TS Address is 0x30

R3C1

R3C1 10K

10K

5%

B B

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

SA0_DIM0 SA1_DIM0

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

J5P1A

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

CON200_DDR2-SODIMM-STAN

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

M_A_DQ0

5

M_A_DQ1

7

M_A_DQ2

17

M_A_DQ3

19

M_A_DQ4

4

M_A_DQ5

6

M_A_DQ6

14

M_A_DQ7

16

M_A_DQ8

23

M_A_DQ9

25

M_A_DQ10

35

M_A_DQ11

37

M_A_DQ12

20

M_A_DQ13

22

M_A_DQ14

36

M_A_DQ15

38

M_A_DQ16

43

M_A_DQ17

45

M_A_DQ18

55

M_A_DQ19

57

M_A_DQ20

44

M_A_DQ21

46

M_A_DQ22

56

M_A_DQ23

58

M_A_DQ24

61

M_A_DQ25

63

M_A_DQ26

73

M_A_DQ27

75

M_A_DQ28

62

M_A_DQ29

64

M_A_DQ30

74

M_A_DQ31

76

M_A_DQ32

123

M_A_DQ33

125

M_A_DQ34

135

M_A_DQ35

137

M_A_DQ36

124

M_A_DQ37

126

M_A_DQ38

134

M_A_DQ39

136

M_A_DQ40

141

M_A_DQ41

143

M_A_DQ42

151

M_A_DQ43

153

M_A_DQ44

140

M_A_DQ45

142

M_A_DQ46

152

M_A_DQ47

154

M_A_DQ48

157

M_A_DQ49

159

M_A_DQ50

173

M_A_DQ51

175

M_A_DQ52

158

M_A_DQ53

160

M_A_DQ54

174

M_A_DQ55

176

M_A_DQ56

179

M_A_DQ57

181

M_A_DQ58

189

M_A_DQ59

191

M_A_DQ60

180

M_A_DQ61

182

M_A_DQ62

192

M_A_DQ63

194

M_A_DQ[63:0] 8

+V3.3M14,15,23,24,35,36,42,44,50,56,57

R4C1 0.022R4C1 0.022

PM_EXTTS#07,15

M_VREF_DIMM050

+V1.8_DIMM0

C4C8

C4C9

C4C10

0.1uF

10%

.

C4C10

0.1uF

10%

C4C13

2.2uF

10%

.

0.1uF

10%

.

Layout Note: Place these Caps near SO-DIMM0.

+V1.89,10,14,47,50,56

R5C2 0.002

Layout Note: Place these Caps near SO-DIMM0.

1%

C5C1

C5C1 330uF

330uF

20%

2.5V

+V3.3M_DIMM0

C3C4

0.1uF

10%

C5C4

0.1uF

10%

.

C5C3

2.2uF

10%

C4C12

2.2uF

10%

C4C7

2.2uF

10%

C6P2

0.1uF

10%

C5C5

2.2uF

10%

C6P1

2.2uF

10%

+V1.8_DIMM0

C4C11

2.2uF

10%

J5P1B

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

NC3

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

CON200_DDR2-SODIMM-STAN

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

DDR2 SODIMM 0

A

NDA

2

13 58Tuesday, December 05, 2006

1

Intel Confidential

1.5

of

5

4

3

2

1

D D

J5N1A

M_B_A[13:0]8,15

M_B_A148

C C

Note: SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 TS Address is 0x34

+V3.3M13,15,23,24,35,36,42,44,50,56,57

R3B26 10K

5%

B B

R4B27

R4B27 10K

10K

5%

M_B_BS28,15 M_B_BS08,15

M_B_BS18,15 M_CS#27,15

M_CS#37,15 M_CLK_DDR37 M_CLK_DDR#37 M_CLK_DDR47 M_CLK_DDR#47 M_CKE37,15 M_CKE47,15 M_B_CAS#8,15 M_B_RAS#8,15 M_B_WE#8,15

SMB_CLK_M213,15,23 SMB_DATA_M213,15,23

M_ODT27,15 M_ODT37,15 M_B_DM[7:0]8

M_B_DQS[7:0]8

M_B_DQS#[7:0]8

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

SA0_DIM1 SA1_DIM1

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

J5N1A

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

CON200_DDR2-SODIMM-REV

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_B_DQ0

5

M_B_DQ1

7

M_B_DQ2

17

M_B_DQ3

19

M_B_DQ4

4

M_B_DQ5

6

M_B_DQ6

14

M_B_DQ7

16

M_B_DQ8

23

M_B_DQ9

25

M_B_DQ10

35

M_B_DQ11

37

M_B_DQ12

20

M_B_DQ13

22

M_B_DQ14

36

M_B_DQ15

38

M_B_DQ16

43

M_B_DQ17

45

M_B_DQ18

55

M_B_DQ19

57

M_B_DQ20

44

M_B_DQ21

46

M_B_DQ22

56

M_B_DQ23

58

M_B_DQ24

61

M_B_DQ25

63

M_B_DQ26

73

M_B_DQ27

75

M_B_DQ28

62

M_B_DQ29

64

M_B_DQ30

74

M_B_DQ31

76

M_B_DQ32

123

M_B_DQ33

125

M_B_DQ34

135

M_B_DQ35

137

M_B_DQ36

124

M_B_DQ37

126

M_B_DQ38

134

M_B_DQ39

136

M_B_DQ40

141

M_B_DQ41

143

M_B_DQ42

151

M_B_DQ43

153

M_B_DQ44

140

M_B_DQ45

142

M_B_DQ46

152

M_B_DQ47

154

M_B_DQ48

157

M_B_DQ49

159

M_B_DQ50

173

M_B_DQ51

175

M_B_DQ52

158

M_B_DQ53

160

M_B_DQ54

174

M_B_DQ55

176

M_B_DQ56

179

M_B_DQ57

181

M_B_DQ58

189

M_B_DQ59

191

M_B_DQ60

180

M_B_DQ61

182

M_B_DQ62

192

M_B_DQ63

194

M_B_DQ[63:0] 8

+V1.8_DIMM1

C4B18

C4B17

C4B19

2.2uF

10%

0.1uF

10%

.

C4B15

2.2uF

10%

C4B17

0.1uF

10%

.

C4B20

0.1uF

10%

.

Layout Note: Place these Caps near SO-DIMM1.

+V1.8_DIMM1

C5B5

2.2uF

10%

Layout Note: Place these Caps near SO-DIMM1.

C5B6

2.2uF

10%

C4B21

0.1uF

10%

.

C4B16

2.2uF

10%

C5B8

C5B8 330uF

330uF

20%

+V3.3M13,15,23,24,35,36,42,44,50,56,57

R4B26 0.022R4B26 0.022

PM_EXTTS#17,15

M_VREF_DIMM150

R5B10 0.002

1%

+V3.3M_DIMM1

C6N9

0.1uF

10%

+V1.89,10,13,47,50,56

C3B7

0.1uF

10%

+V1.8_DIMM1

C6N10

2.2uF

10%

C3B9

2.2uF

10%

J5N1B

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

NC3

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

CON200_DDR2-SODIMM-REV

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

SO-DIMM1 is placed farther from the GMCH than SO-DIMM0

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

DDR2 SODIMM 1

A

NDA

2

14 58Tuesday, December 05, 2006

1

Intel Confidential

1.5

of

Layout Note: Place Q5N2 under DIMM0

5

4

3

2

1

On Board DDR2 Thermal Sensor

DDR_THERM1

2

Q5N2

1

2N3904

D D

C C

2N3904

3

PM_EXTTS#17,14

+V0.9 14,47,56

R5P3 0R5P3 0

C4C3

0.1uF

10%

.

C5C6

0.1uF

10%

.

DDR_THERM2

C4C15

0.1uF

10%

.

C5B7

0.1uF

10%

.

B B

+V3.3M 13,14,23,24,35,36,42,44,50,56,57

U5P1

1

VDD

2

SDATA

D+

3

D-

PM_EXTTS#1_D

C4C1

0.1uF

10%

.

C4B23

0.1uF

10%

.

Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9

THERM#4GND

ADM1032AR

Layout Note: Place U5P1 under DIMM1

C4C5

0.1uF

10%

.

C4B12

0.1uF

10%

.

ALERT#

C4B24

0.1uF

10%

.

C4B22

0.1uF

10%

.

SCLK

8 7

PM_EXTTS#0_D

6 5

C4B14

0.1uF

10%

.

C4C17

0.1uF

10%

.

C4B9

0.1uF

10%

.

C4C14

0.1uF

10%

.

R5P2 0R5P2 0

C4B25

0.1uF

10%

.

C4C16

0.1uF

10%

.

SMB_CLK_M2 13,14,23 SMB_DATA_M2 13,14,23 PM_EXTTS#0 7,13

C4B10

C4B26

0.1uF

10%

.

C5B4

C4C2

0.1uF

10%

.

C4C6

0.1uF

10%

.

C5C2

0.1uF

10%

.

C4C4

0.1uF

10%

.

C4B11

0.1uF

10%

.

C4B8

0.1uF

10%

.

C4B13

0.1uF

10%

.

+V0.9 14,47,56

R5C1 56R5C1 56 R5C3 56R5C3 56 R5B8 56R5B8 56 R5B11 56R5B11 56

R4C24 56R4C24 56 R4C13 56R4C13 56 R4B37 56R4B37 56 R4B25 56R4B25 56

R4C14 56R4C14 56 R4C21 56R4C21 56 R4C2 56R4C2 56

R4C10 56R4C10 56 R4C11 56R4C11 56 R4C22 56R4C22 56

R4B21 56R4B21 56 R4B34 56R4B34 56 R5B9 56R5B9 56

R4B22 56R4B22 56 R4B23 56R4B23 56 R4B35 56R4B35 56

R4C23 56R4C23 56 R4C12 56R4C12 56 R4B36 56R4B36 56 R4B24 56R4B24 56

R4C20 56R4C20 56 R4C8 56R4C8 56 R4C19 56R4C19 56 R4C7 56R4C7 56 R4C18 56R4C18 56 R4C6 56R4C6 56 R4C16 56R4C16 56 R4C17 56R4C17 56 R4C5 56R4C5 56 R4C4 56R4C4 56 R4C9 56R4C9 56 R5C4 56R5C4 56 R4C3 56R4C3 56 R4C25 56R4C25 56

R4B33 56R4B33 56 R4B18 56R4B18 56 R4B32 56R4B32 56 R4B19 56R4B19 56 R4B31 56R4B31 56 R4B17 56R4B17 56 R4B28 56R4B28 56 R4B30 56R4B30 56 R4B16 56R4B16 56 R4B15 56R4B15 56 R4B20 56R4B20 56 R5B12 56R5B12 56 R4B14 56R4B14 56 R4B38 56R4B38 56

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

M_CKE0 7,13 M_CKE1 7,13 M_CKE3 7,14 M_CKE4 7,14

M_ODT0 7,13 M_ODT1 7,13 M_ODT2 7,14 M_ODT3 7,14

M_A_BS0 8,13 M_A_BS1 8,13 M_A_BS2 8,13

M_A_WE# 8,13 M_A_CAS# 8,13 M_A_RAS# 8,13

M_B_BS0 8,14 M_B_BS1 8,14 M_B_BS2 8,14

M_B_WE# 8,14 M_B_CAS# 8,14 M_B_RAS# 8,14

M_CS#0 7,13 M_CS#1 7,13 M_CS#2 7,14 M_CS#3 7,14

M_A_A[13:0] 8,13

M_B_A[13:0] 8,14

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

DDR2 TERMINATION AND THERMAL SENSOR

A

NDA

2

Intel Confidential

15 58Tuesday, December 05, 2006

1

1.5

of

5

7

+V3.3S28,30..32,34,37..42,44,45,49,50,52,55..5

R6T8

R6T8 10K

10K

D D

DOCK_CRT_TV_EN#

R6T7

R6T7 1K

1K

NO_STUFF

4

CRT_L2_RED CRT_L2_BLUE CRT_L2_GREEN CRT_Q_HSYNC

U2M2

1

I/O1

2

I/O2

3

I/O3

4

I/O4

ESD DIODE ARRAY

3

+V3.3S5,7,10,12,17..26,28,30..32,34,37..42,44,45,49,50,52,55..57

C2N2

0.1uF

20%

8

VP

10

I/O8

9

I/O7

7

I/O6 I/O5

VN

5

6

CRT_Q_VSYNC

CRT_DDC_DATA_ISO CRT_DDC_CLK_ISO

2

U2A2

1

I/O1

2

I/O2

3

I/O3

4

I/O4

ESD DIODE ARRAY

1

+V5S5,11,12,17,18,24,30..32,34,41,49,50,52,53,55..57

C2M2

0.1uF

20%

8

VP

10

I/O8

9

I/O7

7

I/O6

6

I/O5

VN

5

DLINE1_IO 18 DLINE2_IO 18 DLINE3_IO 18

+V3.3S5,7,10,12,17..26,28,30..32,34,37..42,44,45,49,50,52,55..57

U6E4

C C

DOCK_CRT_TV_EN#18,45

+V3.3S

CRT_RED7 CRT_GREEN7 CRT_BLUE7 CRT_VSYNC7 CRT_HSYNC7

5,7,10,12,17..26,28,30..32,34,37..42,44,45,49,50,52,55..57

C6T7

C6T6

0.1uF

20%

C6T7

0.1uF

20%

C6E7

0.1uF

20%

B B

CRT_DDC_DATA_MCH7

A A

CRT_DDC_CLK_MCH7

CRT_DDC_CLK_DOCK45

5

U6E4

12

SEL

2

Y_A

5

Y_B

6

Y_C

8

Y_D

11

Y_E

3

GND1

7

GND2

10

GND3

20

GND4

PI3V512QE

C6T9

0.1uF

20%

+V3.3S5,7,10,12,17..26,28,30..32,34,37..42,44,45,49,50,52,55..57

CRT_DDC_DATA_DOCK45

+V3.3S5,7,10,12,17..26,28,30..32,34,37..42,44,45,49,50,52,55..57

1

VDD1

4

VDD2

9

VDD3

19

VDD4

24

I_A0

22

I_B0

18

I_C0

17

I_D0

14

I_E0

CRT_Q_RED

23

I_A1

CRT_Q_GREEN

21

I_B1

CRT_Q_BLUE

16

I_C1

CRT_Q_VSYNC

15

I_D1

CRT_Q_HSYNC

13

I_E1

DOCK_CRT_TV_EN# CRT_TV_EN#

R6T2

Q6T1

2.2K

2.2K BSS138

BSS138

3

2

1

+V3.3S5,7,10,12,17..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R6T5

Q6T2

2.2K

2.2K BSS138

BSS138

3

2

1

+V3.3S5,7,10,12,17..26,28,30..32,34,37..42,44,45,49,50,52,55..57

CRT_RED_DOCK 45 CRT_GRN_DOCK 45 CRT_BLUE_DOCK 45 CRT_VSYNC_DOCK 45 CRT_HSYNC_DOCK 45

1 2 3

CRT_DDC_DATA

CRT_DDC_CLK

4

5

U6T1

2 4

INVERTER

3

U6E2

OE1# 1A

OE2# 1B GND42A

74CBT3306

U6E3

1

OE1#

2

1A

3

1B GND42A

74CBT3306

VCC

2B

VCC

OE2#

Note: For video bandwidths > 200MHz: C3B1, C3A4, C2B1, C2A5, C2B2, C2N1 = 3.3pF C3M4, C2A4, C2A6 = No_Stuff FB3A1, FB2A4, FB2B1 = Short

CRT_DDC_DATA_ISO

CRT_DDC_CLK_ISO

CRT_Q_RED

R3B2

R3B2 150

150

1%

+V3.3S5,7,10,12,17..26,28,30..32,34,37..42,44,45,49,50,52,55..57

C6T3

0.1uF

20%

CRT_TV_EN# 18

+V5S 5,11,12,17,18,24,30..32,34,41,49,50,52,53,55..57

C6T1

0.1uF

20%

8 7

CRT_DDC_DATA_ISO

6 5

+V5S 5,11,12,17,18,24,30..32,34,41,49,50,52,53,55..57

8 7

CRT_DDC_CLK_ISO

6

2B

5

20%

C6T5

0.1uF

20%

3

CRT_Q_GREEN CRT_L2_GREEN

CRT_Q_BLUE

CRT_Q_VSYNC

CRT_Q_HSYNC

R3B3

R3B3 150

150

1%

R2B1

R2B1 150

150

1%

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

CRT

NDA

C3B1

C3B1 10pF

10pF

5%

5% .

.

C2B1

C2B1 10pF

10pF

5%

5% .

.

C2B2

C2B2 10pF

10pF

5%

5% .

.

2

FB3B1

CRT_L_RED

47ohm@100MHz

FB3B2

CRT_L_GREEN

47ohm@100MHz

FB2B2

CRT_L_BLUE

47ohm@100MHz

+VBATS19,27,56,57

R2N21KR2N2 1K

DDC_GATE

R2N3

R2N3 100K

100K

C3A4

C3A4 22pF

22pF

5%

5% .

.

C2A5

C2A5 22pF

22pF

5%

5% .

.

C2N1

C2N1 22pF

22pF

5%

5% .

.

C3M5

C3M5 33pF

33pF

5%

5% NO_STUFF

NO_STUFF

1

.

FB3A1

47ohm@100MHz

FB2A4

47ohm@100MHz

FB2B1

47ohm@100MHz

+V5S5,11,12,17,18,24,30..32,34,41,49,50,52,53,55..57

DDC_SRC

R2A8

2.2K

C3M6

C3M6 33pF

33pF

5%

5% NO_STUFF

NO_STUFF

+

2

3

F2A1

1 2

1.1A

Q2A1

Q2A1 BSS138

BSS138

R2A9

2.2K

.

C3M4

C3M4 10pF

10pF

5%

5% .

.

C2A4

CRT_L2_BLUE

10pF

5%

5% .

.

C2A6

C2A6 10pF

10pF

5%

5% .

.

CRT_L2_RED

+V5S_F_DAC

FB2M1

50OHM

+V5S_L_DAC

GND1

GND1 RED

RED GND2

GND2 GRN

GRN GND3

GND3 BLU

BLU VCC

VCC NC1

NC1 GND4

GND4 GND5 CLK

GND5 CLK

16 58Tuesday, December 05, 2006

1

J2A2B

19 14 18 13 17 12 16 11 15 10 20

Intel Confidential

of

2IN1

NC2

24

DATA

23

HSYNC

22

VSYNC

21

1.5

5

4

+V5S5,11,12,16,18,24,30..32,34,41,49,50,52,53,55..57

R6U8

0.002

1%

3

+V3.3S5,7,10,12,16,18..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R6F9

0.002

1%

+V5S_LVDS_BKLT

1%

+V5S5,11,12,16,18,24,30..32,34,41,49,50,52,53,55..57

12

R6U9

0.002

NO_STUFF

2

+VBAT49,53,55..57

R6F1

0.002

1%

1

+VCC_LVDS_BKLT+V3.3S_LVDS_DDC

D D

C6U6

C6U7

0.1uF

20%

C6U6

0.1uF

20%

C6F5

0.1uF

10%

+V3.3S5,7,10,12,16,18..26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V5S5,11,12,16,18,24,30..32,34,41,49,50,52,53,55..57

C7T25

0.1uF

20%

U7E8

LVDS Panel Backlight

C C

BIOS Note: Disable both BKLTSEL lines before enabling one.

B B

+V3.3S5,7,10,12,16,18..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R6U13 0.002

1%

For 3.3V LVDS Panel For 5V LVDS Panel

STUFF UNSTUFF R6U13, R6F9 R6U9, R6U16

R6U9, R6U16 R6U13, R6F9

LVDS_VDD_EN7

A A

5

+V5S5,11,12,16,18,24,30..32,34,41,49,50,52,53,55..57

12

R6U16

0.002

NO_STUFF

L_BKLTSEL0#40 L_BKLT_CTRL7

GMCH_PWM Support

+V3.3S_L

L_VDDEN#

1

R6V1

R6V1 100K

100K

4

R6U151MR6U15 1M

R6U12 100KR6U12 100K

3

Q6F3

Q6F3 BSS138

BSS138

2

U7E8

1

OE1#

2

1A

3

1B GND42A

74CBT3306

L_BRIGHTNESS

C6U13

C6U13 1000pF

1000pF

10%

VCC

OE2#

2B

L_VDDEN_D#

8 7 6 5

20%

L_BKLTSEL1# 40

GM_Data_D Support

LVDS_DDC_CLK7 LVDS_DDC_DATA7

Q6F2

SI2307DS

32

C6F1

C6F1 22UF

22UF

1

3

5,7,10,12,16,18..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R7U2

R7U2 10K

10K

5%

C6U2

0.1uF

20%

+V3.3S5,7,10,12,16,18..26,28,30..32,34,37..42,44,45,49,50,52,55..57

L_VDD_VDL

L_CTRL_DATA 7,20

R6U6

2.2K

5%

R6U5

2.2K

5%

L_CTRL_CLK7,20

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

+V3.3S

R6U3

R6U3 10K

10K

5%

GM_CLK_D Support

+V3.3S5,7,10,12,16,18..26,28,30..32,34,37..42,44,45,49,50,52,55..57

LVDSA_DATA#37

LVDSA_DATA37

LVDSB_DATA#37

LVDSB_DATA37

LVDS

NDA

L_BKLTSEL1#

ALS_CLK42 ALS_DATA42 KBC_PROG_TX#41,42

2

U6F1

1

OE#

2

A GND3Y

74CBTLV1G125

L_BKLT_EN7

+V3.3S_LVDS_DDC

LVDSA_DATA#07 LVDSA_DATA07

LVDSA_DATA#17 LVDSA_DATA17

LVDSA_DATA#27 LVDSA_DATA27

SH6F2SH6F2 SH6F1SH6F1

LVDSA_CLK#7 LVDSA_CLK7

LVDSB_DATA#07 LVDSB_DATA07

LVDSB_DATA#17 LVDSB_DATA17

LVDSB_DATA#27 LVDSB_DATA27

SH5F1SH5F1 SH5F2SH5F2

LVDSB_CLK#7 LVDSB_CLK7

VCC

LVDS_RSVD_1 LVDS_RSVD_2

LVDS_RSVD_3 LVDS_RSVD_4

+V3.3S5,7,10,12,16,18..26,28,30..32,34,37..42,44,45,49,50,52,55..57

C6U1

0.1uF

20%

+VCC_LVDS_BKLT

5

4

L_VDD_VDL

+V5S_LVDS_BKLT

DBL_CLK

R6U7

R6U7 100K

100K

Intel Confidential

17 58Tuesday, December 05, 2006

1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

of

J6F1

VDD_BLI VSS_BLI VSS_DBC VDD_DBC DBL_CLK DBL_DATA ENA_BL NC1 VDD_ALS VSS_ALS ALS_CLK ALS_DATA ALS_INTR NC2 VSS_VDL VDD_VDL1 VDD_VDL2 VDD_VCL RSVD VCL_CLK VCL_DATA A0M A0P VSS_SHIELD1 A1M A1P VSS_SHIELD2 A2M A2P VSS_SHIELD3 A3M A3P VSS_SHIELD4 VDL_CLKAM VDL_CLKAP VSS B0M B0P VSS_SHIELD5 B1M B1P VSS_SHIELD6 B2M B2P VSS_SHIELD7 B3M B3P VSS_SHIELD8 VDL_CLKBM VDL_CLKBP

LVDS,CONN50

1.5

5

+V3.3S5,7,10,12,16,17,19..26,28,30..32,34,37..42,44,45,49,50,52,55..57

D D

U6B1

DOCK_CRT_TV_EN#16,45

5,7,10,12,16,17,19..26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V3.3S

C C

C6N7

0.1uF

20%

C6N5

0.1uF

20%

C6N3

0.1uF

20%

TVA_DAC7 TVB_DAC7 TVC_DAC7

C6N4

0.1uF

20%

12

2 5 6 8

11

3

7 10 20

SEL Y_A

Y_B Y_C Y_D Y_E

GND1 GND2 GND3 GND4

PI3V512QE

VDD1 VDD2 VDD3 VDD4

I_C0 I_D0 I_E0

I_A1 I_B1 I_C1 I_D1 I_E1

I_A0 I_B0

1 4 9 19

24 22 18 17 14

DACA

23 21 16 15

DACC

13

4

TV_DACA_OUT_DOCK 45 TV_DACB_OUT_DOCK 45 TV_DACC_OUT_DOCK 45

3

Layout Note: Place 150 Ohm termination resistors, ferrite beads and capicators close to connector

FB2A2

DACA

R1M2

R1M2 150

150

1%

DACBDACB

R2N1

R2N1 150

150

1%

DACC DACC_L

R1M1

R1M1 150

150

1%

+V5S5,11,12,16,17,24,30..32,34,41,49,50,52,53,55..57

12

C1A3

5.6pF

8.9%

8.9% .

.

12

C2A3

5.6pF

8.9%

8.9% .

.

12

C1A4

5.6pF

8.9%

8.9% .

.

FB2A2

150ohm@100MHz

FB2A1

150ohm@100MHz

FB1A1

150ohm@100MHz

2

Port Value

IO2 IO1 IO0

0 0 0b

0 0 Xb 0 1 0b 0 1 1b 0 1 Xb X 1 0b X 1 1b 1 0 0b 1 0 1b 1 1 0b 1 1 1b

+V3.3S5,7,10,12,16,17,19..26,28,30..32,34,37..42,44,45,49,50,52,55..57

DACA_L

12

C1A1

5.6pF

8.9%

8.9% .

.

DACA_L DACB_L

DACB_L

12

C2A1

5.6pF

8.9%

8.9% .

.

12

C1A2

5.6pF

8.9%

8.9% .

.

+V5S5,11,12,16,17,24,30..32,34,41,49,50,52,53,55..57

J2A1

1 2 3 4 5 6 7

CON14_DCONN-CP4120

DACC_L

8 9 10 11 12 13 14

U2M1

1

I/O1

2

I/O2

3

I/O3

4

I/O4

ESD DIODE ARRAY

Note: Pins 12 & 14 are shorted inside D-Connector plug.

8

VP

VN

5

Format 525i (480) 525i (480)0 0 1b 525i (480) 525p (480) 525p (480) 525p (480) 750p (720) 750p (720) 1125i (1080) 1125i (1080) 1125p (1080) 1125p (1080)

C2M1

0.1uF

20%

Aspect Ratio

I/O8 I/O7 I/O6 I/O5

1

Voltage

Line2

Line1 4:3 16:9 4:3

Letterbox 4:3 16:9 4:3

Letterbox 2.2V 4:3 16:9 4:3 16:9 4:3 16:9

10 9 7 6

Note: ESD Diode Array for the TV DAC A, DAC B, DAC C signals located on CRT page.

0V 0V 0V 0V 0V 0V

2.2V

2.2V 5V 5V 5V 5V

0V 0V 0V 5V 5V 5V 5V 5V 0V 0V 5V 5V

Line3

0V 5V

2.2V 0V 5V

0V 5V 0V 5V 0V 5V

C2A2

1.0uF

R2A6

R2A6 10K

10K

1%

TV_DCONSEL1_LVL TV_DCONSEL0_LVL

I2C_RST#

B B

5,7,10,12,16,17,19..26,28,30..32,34,37..42,44,45,49,50,52,55..57

TV_DCONSEL1_MCH7

5,7,10,12,16,17,19..26,28,30..32,34,37..42,44,45,49,50,52,55..57

A A

TV_DCONSEL0_MCH7

5,7,10,12,16,17,19..26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V3.3S

R7D16

Q7T1

2.2K

2.2K BSS138

BSS138

5%

+V3.3S

R6D6

2.2K

5%

2

3

2

1

+V3.3S 5,7,10,12,16,17,19..26,28,30..32,34,37..42,44,45,49,50,52,55..57

TV_DCONSEL1_DOCK45

Q7R2

Q7R2 BSS138

BSS138

3

1

+V3.3S

TV_DCONSEL0_DOCK45

5

TV_DCONSEL1

TV_DCONSEL0

DOCK_CRT_TV_EN#

U7D3

1

OE1#

VCC

2

1A

OE2#

3

1B

2B

GND42A

74CBT3306

U6D1

1

OE1#

VCC

2

1A

OE2#

3

1B GND42A

74CBT3306

4

1.0uF

10%

U2A1

10

VDD

9

SDA

8

SCL

7

INT#

6

RESET#

I2C - PCA9537

8 7 6 5

8 7 6

2B

5

1

IO_0

2

IO_1

3

IO_2

4

IO_3

5

VSS

CRT_TV_EN#

+V5S5,11,12,16,17,24,30..32,34,41,49,50,52,53,55..57

.

R6D7

2.2K

5%

TV_DCONSEL1_LVL

+V5S 5,11,12,16,17,24,30..32,34,41,49,50,52,53,55..57

.

R6D4

2.2K

5%

TV_DCONSEL0_LVL

R2A1

5.90K

DLINE3_IO 16 DLINE2_IO 16 DLINE1_IO 16

CRT_TV_EN# 16

C7D6

0.1uF

20%

C6D10

0.1uF

20%

3

R2A7

5.90K

R2A3

4.7K

R2A2 10KR2A2 10K R2A4 10KR2A4 10K R2M1 10KR2M1 10K

R2A5

4.7K

DLINE3 DLINE2 DLINE1

TV-OUT DAC Channel Definition

Channel A (DACA) Channel B(DACB) Luminance (Y) Channel C (DACC)

Matanzas

Title

Size Document Number Rev

Date: Sheet

TV

A

NDA

2

Composite Video S-Video Component Video CVBS Signal

X X

X

Chrominance (C)

Chrominance (Pb) Luminance (Y) Chrominance (Pr)

18 58Tuesday, December 05, 2006

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Intel Confidential

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1.5

5

4

3

2

1

PRSNT1#

+12V4 +12V5

GND6 JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3

PWRGD

GND7

REFCLK+

REFCLK-

GND8

HSIP_0 HSIN_0

GND9

RSVD5 GND16 HSIP_1 HSIN_1 GND17 GND18 HSIP_2 HSIN_2 GND19 GND20 HSIP_3 HSIN_3 GND21 RSVD6 RSVD7 GND30 HSIP_4 HSIN_4 GND31 GND32 HSIP_5 HSIN_5 GND33 GND34 HSIP_6 HSIN_6 GND35 GND36 HSIP_7 HSIN_7 GND37 RSVD8 GND54 HSIP_8 HSIN_8 GND55 GND56 HSIP_9 HSIN_9 GND57

GND58 HSIP_10 HSIN_10

GND59

GND60 HSIP_11 HSIN_11

GND61

GND62 HSIP_12 HSIN_12

GND63

GND64 HSIP_13 HSIN_13

GND65

GND66 HSIP_14 HSIN_14

GND67

GND68 HSIP_15 HSIN_15

GND69

+V12S_PEG

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

+V3.3S_PEG

PEG_RX15 PEG_RX#15

PEG_RX14 PEG_RX#14

PEG_RX13 PEG_RX#13

PEG_RX12 PEG_RX#12

PEG_RX11 PEG_RX#11

PEG_RX10 PEG_RX#10

PEG_RX9 PEG_RX#9

PEG_RX8 PEG_RX#8

PEG_RX7 PEG_RX#7

PEG_RX6 PEG_RX#6

PEG_RX5 PEG_RX#5

PEG_RX4 PEG_RX#4

PEG_RX3 PEG_RX#3

PEG_RX2 PEG_RX#2

PEG_RX1 PEG_RX#1

PEG_RX0 PEG_RX#0

PEG_SLT_RST#

CLK_PCIE_PEG 37PEG_TX[15:0]7 PEG_RX[15:0] 7

PEG_RX#[15:0] 7

For D3 HOT/ D3 ON: Stuff R6N5, R6P2, and R6N7, unstuff R6N9, R6C1 and R6N6.

R6N7 0

NO_STUFF

R6N6 0R6N6 0

PLT_GATED_RST# 42,44

PLT_RST# 7,22,25,26,39,40,42,57

+V12S_PEG

C6B7

C6B7 22UF

22UF

+V3.3S_PEG

+VBAT_S456,57

+VBATS16,27,56,57

R6N5

R6N9

0.002

1%

NO_STUFF

C6N8

C6B6

0.1uF

C6B8

C6B2

22UF

12

+

C6B11

C6B9

0.1uF

10%

0.1uF

10%

.

C6B13

C6B13 100uF

100uF

C6B4

C6B4 22UF

22UF

27,33,41..44,49,56,57

+V3.3S5,7,10,12,16..18,20..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R6C1

0.002

1%

+V3.3

0.1uF

10%

R6P2

0.002

1%

1% NO_STUFF

NO_STUFF

+V3.3A21,23..29,33,34,39..42,44..48,50..52,55..57

C6C1

C6C1 22uF

22uF

10%

C6B12

0.1uF

10%

.

+V12S_PEG

D D

SMB_CLK_S423,44 SMB_DATA_S423,44

PCIE_WAKE#23,25,26,45

C6C2

0.1uF

C6C3

PEG_TX#[15:0]7 CLK_PCIE_PEG# 37

SDVO_CTRLCLK7

C C

SDVO_CTRLDATA7

MCH_CFG_207,12

B B

PEG_RSVD_B81

PEG_TX15 PEG_TX#15

PEG_TX14 PEG_TX#14

PEG_TX13 PEG_TX#13

PEG_TX12 PEG_TX#12

PEG_TX11 PEG_TX#11

PEG_TX10 PEG_TX#10

PEG_TX9 PEG_TX#9

PEG_TX8 PEG_TX#8

PEG_TX7 PEG_TX#7

PEG_TX6 PEG_TX#6

PEG_TX5 PEG_TX#5

PEG_TX4 PEG_TX#4

PEG_TX3 PEG_TX#3

PEG_TX2 PEG_TX#2

PEG_TX1 PEG_TX#1

PEG_TX0 PEG_TX#0

Layout Note: place AC coupling caps close to GMCH. All AC coupling caps are 0402 size.

10%

.

C6C4

0.1uF

10%

.

C6C6

0.1uF

10%

.

C6C8

0.1uF

10%

.

C6C10

0.1uF

10%

.

C6D1

0.1uF

10%

.

C6D3

0.1uF

10%

.

C6D6

0.1uF

10%

.

C6D8

0.1uF

10%

.

C6D11

0.1uF

10%

.

C6D13

0.1uF

10%

.

C6D15

0.1uF

10%

.

C6E1

0.1uF

10%

.

C6E3

0.1uF

10%

.

C6E5

0.1uF

10%

.

C6E8

0.1uF

10%

.

C6C3

0.1uF

10%

.

C6C5

0.1uF

10%

.

C6C7

0.1uF

10%

.

C6C9

0.1uF

10%

.

C6C11

0.1uF

10%

.

C6D2

0.1uF

10%

.

C6D4

0.1uF

10%

.

C6D7

0.1uF

10%

.

C6D9

0.1uF

10%

.

C6D12

0.1uF

10%

.

C6D14

0.1uF

10%

.

C6D16

0.1uF

10%

.

C6E2

0.1uF

10%

.

C6E4

0.1uF

10%

.

C6E6

0.1uF

10%

.

C6E9

0.1uF

10%

.

+V3.3S_PEG

+V3.3A21,23..29,33,34,39..42,44..48,50..52,55..57

PEG_C_TX15 PEG_C_TX#15

PEG_C_TX14 PEG_C_TX#14

PEG_C_TX13 PEG_C_TX#13

PEG_C_TX12 PEG_C_TX#12

PEG_C_TX11 PEG_C_TX#11

PEG_C_TX10 PEG_C_TX#10

PEG_C_TX9 PEG_C_TX#9

PEG_C_TX8 PEG_C_TX#8

PEG_C_TX7 PEG_C_TX#7

PEG_C_TX6 PEG_C_TX#6

PEG_C_TX5 PEG_C_TX#5

PEG_C_TX4 PEG_C_TX#4

PEG_C_TX3 PEG_C_TX#3

PEG_C_TX2 PEG_C_TX#2

PEG_C_TX1 PEG_C_TX#1

PEG_C_TX0 PEG_C_TX#0

J6B2

B1

+12V1

B2

+12V2

B3

+12V3

B4

GND1

B5

SMCLK

B6

SMDAT

B7

GND2

B8

+3.3V1

B9

JTAG1

B10

3.3VAUX

B11

WAKE#

Key

RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5 HSOP_1 HSON_1 GND10 GND11 HSOP_2 HSON_2 GND12 GND13 HSOP_3 HSON_3 GND14 RSVD3 PRSNT2#1 GND15 HSOP_4 HSON_4 GND22 GND23 HSOP_5 HSON_5 GND24 GND25 HSOP_6 HSON_6 GND26 GND27 HSOP_7 HSON_7 GND28 PRSNT2#2 GND29 HSOP_8 HSON_8 GND38 GND39 HSOP_9 HSON_9 GND40 GND41 HSOP_10 HSON_10 GND42 GND43 HSOP_11 HSON_11 GND44 GND45 HSOP_12 HSON_12 GND46 GND47 HSOP_13 HSON_13 GND48 GND49 HSOP_14 HSON_14 GND50 GND51 HSOP_15 HSON_15 GND52 PRSNT2#3 RSVD4

Key

PCIE_X16

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

PCIE GRAPHICS

A

NDA

2

Intel Confidential

19 58Tuesday, December 05, 2006

1

1.5

of

5

4

3

2

1

D D

C C

XDP_OBS037 XDP_OBS137

XDP_OBS237 XDP_OBS3

+V1.05S_CPU3,4,37,41,44,54

C1R1

0.1uF

10%

.

XDP_BPM#03

XDP_OBS20 CLK_XDP# 37

B B

XDP_BPM#53 XDP_BPM#43

R1R1 0

NO_STUFF

R1R3

54.9

1%

H_PWRGD_XDP3

CLK_PCIE_XDP_3GPLL37

CLK_PCIE_XDP_3GPLL#37

R1D1 0R1D1 0

XDP_OBS5 XDP_OBS6

XDP_OBS7

L_CTRL_DATA7,17 L_CTRL_CLK7,17

XDP_TCK3

XDP_OBS3_R

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

XDP

J1D1

GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16

CONN60_ITP-XDP

CAD NOTE: Place the XDP connector on the primary side of the CRB and place all components near the connector.

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRSTN

GND17

GND1

GND3

GND5

GND7

GND9

TDO

TMS

Layout note: R2T2 should

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56

TDI

58 60

RST_SNS1

XDP_OBS8 XDP_OBS9

XDP_OBS16 XDP_OBS17

XDP_OBS10 XDP_OBS11

XDP_OBS12XDP_OBS4 XDP_OBS13

XDP_OBS14 XDP_OBS15

CLK_XDP 37

R2T2 100R2T2 100

XDP_TRST# 3 XDP_TDI 3 XDP_TMS 3

5,7,10,12,16..19,21..26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V1.05S_CPU3,4,37,41,44,54 +V3.3S

R6Y2

R6Y2 1K

R1R2

54.9

1%

1K

5%

C1R2

0.1uF

10%

.

H_CPURST# 3,6

connect to H_CPURST# with no stub.

XDP_DBRESET# 3, 55 XDP_TDO 3

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

XDP

A

NDA

2

Intel Confidential

20 58Tuesday, December 05, 2006

1

1.5

of

5

+V3.3A 19,23..29,33,34,39..42,44..48,50..52,55..57

CR5H1

1 3

BAT54

BAT_D

1 3

R5W31KR5W3

BT5H1

ATA_LED#55

R7V31

8.2K

1K

BAT

132

5,7,10,12,16..20,22..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R6H8

R6H8 330

330

LED_R

CR6J1

GREEN

1 2

SATA_RXN2_DOCK45 SATA_RXP2_DOCK45

SATA_TXN2_DOCK45 SATA_TXP2_DOCK45

HDA_DOCK_EN#_R

D D

Battery_Holder

C C

B B

5,7,10,12,16..20,22..26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V3.3S

CR5H2

BAT54

U6H4

4

+V3.3S

SATA_RXN030 SATA_RXP030

SATA_TXN030 SATA_TXP030

SATA_RXN131 SATA_RXP131

SATA_TXN131 SATA_TXP131

SATA_RXN231 SATA_RXP231

SATA_TXN231 SATA_TXP231

53

+V3.3A_RTC 24

C7V12

C7V12 1uF

1uF

80%

R5W2 20KR5W2 20K

R5W11MR5W1 1M

CMOS Settings J5H2 Clear CMOS Keep CMOS

C6J1

0.1uF

20%

1 2

74AHC1G08

RTC Circuitry

C5H3

C5H3 1uF

1uF

J5H2J5H2

1 2

Shunt Open

R7G17

R6W7

R6W7 10K

10K

ICH_SATA_LED#

IDE_PDACTIVE# 32

HDA_DOCK_EN#27,42

HDA_DOCK_EN#_R

HDA_DOCK_RST#27,45

C7G7 3900pFC7G7 3900pF C7G6 3900pFC7G6 3900pF C7V14 3900pFC7V14 3900pF C7V13 3900pFC7V13 3900pF

C7G4 3900pFC7G4 3900pF C7G5 3900pFC7G5 3900pF C7G11 3900pFC7G11 3900pF C7G10 3900pFC7G10 3900pF

C8G7 3900pFC8G7 3900pF C8G5 3900pFC8G5 3900pF C8G4 3900pFC8G4 3900pF C8G6 3900pFC8G6 3900pF

C8V3 3900pF NO_STUFFC8V3 3900pF NO_STUFF C8V2 3900pF NO_STUFFC8V2 3900pF NO_STUFF C8V1 3900pF NO_STUFFC8V1 3900pF NO_STUFF C8V4 3900pF NO_STUFFC8V4 3900pF NO_STUFF

Distance between the ICH8-M and cap on the "P" signal should be identical distance between the ICH8-M and cap on the "N" signal for same pair.

+V3.3A_RTC24

4

RTC_RST# 42

Cap values depend on Xtal

+V1.5S_PCIE_ICH22,24

R7U19

24.9

1%

R7G26 0R7G26 0

Layout Note: Short pins AG1, AG2 and place R7G1 within 500 mils from them.

C7G8

C7G8 10pF

10pF

32.7680KHZ

C7G9

C7G9 10pF

10pF

GLAN_CLK35

LAN_RSTSYNC35

LAN_RXD035 LAN_RXD135 LAN_RXD235

LAN_TXD035 LAN_TXD135 LAN_TXD235

ENERGY_DET36

GLAN_COMP

HDA_BIT_CLK27

HDA_SDIN027 HDA_SDIN127 HDA_SDIN227 HDA_SDIN327

HDA_SDOUT27

CLK_PCIE_SATA#37 CLK_PCIE_SATA37

Y7G1

HDA_SYNC27 HDA_RST#27

3

R7G8

R7G8 10M

10M

4 1

RTC_X1

RTC_RST# SM_INTRUDER#

RTC_X2

ICH_INTVRMEN LAN100_SLP

ICH_SATA_LED#

SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C

SATA_RXN1_C IDE_PDD14 SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C

SATA_RXN2_C SATA_RXP2_C SATA_TXN2_C SATA_TXP2_C

SATA_RBIAS_PN

R7G1

24.9

1%

U7F1A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

+V3.3A_RTC24

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD/GPIO49

IGNNE#

RCIN#

STPCLK#

THRMTRIP#

IHDA

DD10 DD11 DD12 DD13 DD14 DD15

IDE

SATA

DCS1# DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

INIT# INTR

SMI#

NMI

TP8 DD0

DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9

DA0 DA1 DA2

E5 F5 G8 F6

C4 G9

E6 AF13

AG26 AF26

AE26 AD24 AG29 AF27 AE24

AC20 AH14

AD23 AG28

AA24 AE27 AA23 V1

U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6

AA4 AA1 AB3

Y6 Y5

W4 W3 Y2 Y3 Y1 W5

H_DPRSTP#_R H_DPSLP#_R

H_SMI#_R

H_THERMTRIP_R

IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13

IDE_PDD15

2

LPC_AD0 39,40,42,44 LPC_AD1 39,40,42,44 LPC_AD2 39,40,42,44 LPC_AD3 39,40,42,44

LPC_FRAME# 39,40,42,44

ICH_DRQ#0 40 ICH_DRQ#1 40

H_A20GATE 42,44 H_A20M# 3

R6V9 0R6V9 0 R6V7 0R6V7 0

H_PWRGD 3,44 H_IGNNE# 3

H_INTR 3 H_RCIN# 42,44

H_NMI 3,44

R6V4 0R6V4 0

H_STPCLK# 3,44

ICH_TP8

IDE_PDD[15:0] 32

IDE_PDA0 32 IDE_PDA1 32 IDE_PDA2 32

IDE_PDCS1# 32 IDE_PDCS3# 32

IDE_PDIOR# 32 IDE_PDIOW# 32 IDE_PDDACK# 32 INT_IRQ14 32 IDE_PDIORDY 32 IDE_PDDREQ 32

+V1.05S_ICH_IO24

NO_STUFF

R6V3 0R6V3 0

+V3.3S_1.5S_HDA_IO24,27,28

R6V5

R6V8

56

NO_STUFF

H_DPRSTP# 3,7,44,52 H_DPSLP# 3,44

+V1.05S_ICH_IO 24

H_INIT# 3 H_INIT#_R 39

H_SMI# 3,44

R6V10 24.9

1%

Layout note: R6V10 needs to placed within 2" of ICH8-M, R6V6 must be placed within 2" of R6V10 w/o stub.

R7G18

R7G18 1K

1K

NO_STUFF

HDA_SDOUT

ICH_TP3 23

R7G13

R7G13 1K

1K

NO_STUFF

R6V656R6V6 56

XOR Chain Entrance Strap

ICH_RSVD

HDA_SDOUT 0 0 1 1

1

+V1.05S_ICH_IO24

R6V256R6V2 56

H_FERR# 3

PM_THRMTRIP# 3,7

H_RCIN#

1 Enter XOR Chain 0 1

R7V32 10KR7V32 10K

Description RSVD0

Normal Operation (Default) Set PCIE port config bit 1

+V3.3S5,7,10,12,16..20,22..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R6V17

R6V17 332K

332K

1%

A A

ICH8-M Internal VR Enable Strap (Internal VR for VccSus1_05, VccSus1_5 and VccCL1_5)

ICH_INTVRMEN

INTERNAL VR SHOULD NOT BE DISABLED High = Internal VR Enabled (Default)

ICH_INTVRMEN

5

1%

R6G16

R6G16 0

0

NO_STUFF

ICH8-M LAN100_SLP Strap (Internal VR for VccLAN1_05 and VccCL1_05)

LAN100_SLP

INTERNAL VR SHOULD NOT BE DISABLED

High = Internal VR Enabled (Default)

4

LAN100_SLP

R7V33

R7V33 332K

332K

1%

R7G14

R7G14 0

0

NO_STUFF

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

ICH8M (1 of 4)

NDA 1.5

A

NDA 1.5

A

NDA 1.5

A

2

21 58Tuesday, December 05, 2006

1

Intel Confidential

of

5

PCIE_RXN1_DOCK45

PCIE_RXP1_DOCK45 PCIE_TXN1_DOCK45 PCIE_TXP1_DOCK45

PCIE_RXN2_DOCK45 PCIE_RXP2_DOCK45

PCIE_TXN2_DOCK45 PCIE_TXP2_DOCK45

PCIE_RXN1_SLOT125

PCIE_RXP1_SLOT125

PCI

+V3.3S5,7,10,12,16..21,23..26,28,30..32,34,37..42,44,45,49,50,52,55..57

NO_STUFF

53

74AHC1G08

.

. Buffer to reduce

loading on PLT_RST#

REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

DEVSEL#

PLTRST#

PIRQE#/GPIO2

PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PCIE_TXN1_SLOT125 PCIE_TXP1_SLOT125

PCIE_RXN2_SLOT225 PCIE_RXP2_SLOT225

PCIE_TXN2_SLOT225 PCIE_TXP2_SLOT225

1 2

REQ0# GNT0#

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PAR

PCIRST#

PERR#

PLOCK#

SERR# STOP# TRDY#

FRAME#

PCICLK

PME#

A4 D7 E18 C18 B19 F18 A11 C10

C17 E15 F16 E17

C8 D9 G6 D16 A7 B7 F10 C16 C9 A17

AG24 B10 G7

F8 G11 F12 B3

PLT_RST#

D D

SPI_CS#136

C C

BUF_PLT_RST#42,44,45

PCI_AD[31:0]33,34

B B

A A

INT_PIRQA#33

INT_PIRQC#33 INT_PIRQD#33

LAN_PHYPC23,35

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

5

R9R2

R9R2 100K

100K

R7U15 15R7U15 15

R6U4 0

C7T3

0.1uF

20%

20% .

.

U8E2

4

U7F1B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10

PIRQD#

ICH8M REV 1.0

4

R6U17 0 NO_STUFFR6U17 0 NO_STUFF R6U14 0 NO_STUFFR6U14 0 NO_STUFF C6F11 0.1uF NO_STUFFC6F11 0.1uF NO_STUFF C6F10 0.1uF NO_STUFFC6F10 0.1uF NO_STUFF

R6U11 0 NO_STUFFR6U11 0 NO_STUFF R6U10 0 NO_STUFFR6U10 0 NO_STUFF C6U10 0.1uF NO_STUFFC6U10 0.1uF NO_STUFF C6U9 0.1uF NO_STUFFC6U9 0.1uF NO_STUFF

R6F11 0R6F11 0 R6F10 0R6F10 0 C6U12 0.1uFC6U12 0.1uF C6U11 0.1uFC6U11 0.1uF

R6F8 0R6F8 0 R6F7 0R6F7 0 C6F9 0.1uFC6F9 0.1uF C6F8 0.1uFC6F8 0.1uF

PCIE_RXN3_SLOT326 PCIE_RXP3_SLOT326 PCIE_TXN3_SLOT326 PCIE_TXP3_SLOT326

PCIE_RXN4_SLOT426 PCIE_RXP4_SLOT426 PCIE_TXN4_SLOT426 PCIE_TXP4_SLOT426

PCIE_RXN5_SLOT526 PCIE_RXP5_SLOT526 PCIE_TXN5_SLOT526 PCIE_TXP5_SLOT526

GLAN_RXN35 GLAN_RXP35 GLAN_TXN35 GLAN_TXP35

USB_OC#029 USB_OC#129 USB_OC#229 USB_OC#329 USB_OC#429 USB_OC#529 USB_OC#629 USB_OC#729 USB_OC#829 USB_OC#945

USB_OC#0_R USB_OC#1_R USB_OC#2_R USB_OC#3_R USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_R

R7U16 15R7U16 15 R7U17 15R7U17 15

SPI_CLK36 SPI_CS#036

SPI_SI36 SPI_SO36

PCI_REQ#0 34 PCI_GNT#0 34 PCI_REQ#1 34 PCI_GNT#1 34 PCI_REQ#2 33 PCI_GNT#2 33 PCI_REQ#3 34 PCI_GNT#3 34

PCI_CBE#0 33,34 PCI_CBE#1 33,34 PCI_CBE#2 33,34 PCI_CBE#3 33,34

PCI_IRDY# 33,34 PCI_PAR 33,34 PCI_RST# 33,34,42 PCI_DEVSEL# 33,34 PCI_PERR# 33,34 PCI_LOCK# 33,34 PCI_SERR# 33,34 PCI_STOP# 33,34 PCI_TRDY# 33,34 PCI_FRAME# 33,34

PLT_RST# 7,19,25,26,39,40,42,57 CLK_PCIF_ICH 38 PCI_PME# 33,34,44

INT_PIRQE# 34 INT_PIRQF# 34INT_PIRQB#33,34 INT_PIRQG# 34 INT_PIRQH# 34

4

C6U8 0.1uFC6U8 0.1uF C6U5 0.1uFC6U5 0.1uF

C6U4 0.1uFC6U4 0.1uF C6U3 0.1uFC6U3 0.1uF

R6F4 0R6F4 0 R6F6 0R6F6 0 C6F7 0.1uFC6F7 0.1uF C6F4 0.1uFC6F4 0.1uF

R6F3 0R6F3 0 R6F5 0R6F5 0 C6F6 0.1uFC6F6 0.1uF C6F3 0.1uFC6F3 0.1uF

R7F11 0R7F11 0 R7F3 0R7F3 0 R7F10 0R7F10 0 R7F9 0R7F9 0 R7F5 0R7F5 0 R7F6 0R7F6 0 R7F8 0R7F8 0 R7F7 0R7F7 0

3

Layout note:

1. PCIE AC coupling caps need to be within 250 mils of the driver.

2. Place the strapping resistors/capacitors without any stub

U7F1D

AJ19 AG16 AG15 AE15 AF15 AG17 AD12

AJ18 AD14 AH18

P27 P26 N29 N28

M27 M26

L29 L28

K27 K26

J29 J28

H27 H26 G29 G28

F27 F26 E29 E28

D27 D26 C29 C28

C23 B23 E22

D23 F21

U7F1D

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0# SPI_CS1#

SPI_MOSI SPI_MISO

OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#

ICH8M REV 1.0

PCIE_RXN1_R PCIE_RXP1_R PCIE_TXN1_C PCIE_TXP1_C

PCIE_RXN2_R PCIE_RXP2_R PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_RXN5_SLOT5_R PCIE_RXP5_SLOT5_R

PCIE_TXN5_C PCIE_TXP5_C

GLAN_RXN_R GLAN_RXP_R PCIE_TXN6_C PCIE_TXP6_C

SPI_CLK_R SPI_CS#0_R SPI_CS#1_R

ICH8-M Pullups

PCI_FRAME#

PCI_IRDY#

PCI_TRDY#

PCI_STOP#

PCI_SERR#

PCI_DEVSEL#

PCI_PERR#

PCI_LOCK#

PCI_REQ#0

PCI_REQ#1

PCI_REQ#2

PCI_REQ#3

INT_PIRQA#

INT_PIRQB#

INT_PIRQC#

INT_PIRQD#

INT_PIRQE#

INT_PIRQF#

INT_PIRQG#

INT_PIRQH#

PCI_REQ64#33 PCI_ACK64#33

PCI_REQ64# PCI_ACK64#

3

RP8C2A 8.2KRP8C2A 8.2K RP8C2B 8.2KRP8C2B 8.2K RP8C2C 8.2KRP8C2C 8.2K RP9D1A 8.2KRP9D1A 8.2K RP9D1D 8.2KRP9D1D 8.2K RP8C2D 8.2KRP8C2D 8.2K RP9D1C 8.2KRP9D1C 8.2K RP9D1B 8.2KRP9D1B 8.2K RP9B1A 8.2KRP9B1A 8.2K RP9B3B 8.2KRP9B3B 8.2K RP8C1D 8.2KRP8C1D 8.2K RP8C1C 8.2KRP8C1C 8.2K

RP9B3A 8.2KRP9B3A 8.2K RP9B1D 8.2KRP9B1D 8.2K RP9B2A 8.2KRP9B2A 8.2K RP9B1C 8.2KRP9B1C 8.2K RP9B2B 8.2KRP9B2B 8.2K RP9B2C 8.2KRP9B2C 8.2K RP9B2D 8.2KRP9B2D 8.2K RP9B1B 8.2KRP9B1B 8.2K RP9B3D 8.2KRP9B3D 8.2K RP9B3C 8.2KRP9B3C 8.2K

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

PCI-Express

DMI_ZCOMP

DMI_IRCOMP

SPI

USB

RP8C1B

2 7

RP8C1A

1 8

1 8 2 7 3 6 1 8 4 5 4 5 3 6 2 7 1 8 2 7 4 5 3 6

1 8 4 5 1 8 3 6 2 7 3 6 4 5 2 7 4 5 3 6

T26

DMI_CLKN

T25

DMI_CLKP

Y23 Y24

Direct Media Interface

G3

USBP0N

G2

USBP0P

H5

USBP1N

H4

USBP1P

H2

USBP2N

H1

USBP2P

J3

USBP3N

J2

USBP3P

K5

USBP4N

K4

USBP4P

K2

USBP5N

K1

USBP5P

L3

USBP6N

L2

USBP6P

M5

USBP7N

M4

USBP7P

M2

USBP8N

M1

USBP8P

N3

USBP9N

N2

USBP9P

F2

USBRBIAS#

F3

USBRBIAS

Place within 500 mils of ICH

8.2K

+V3.3S5,7,10,12,16..21,23..26,28,30..32,34,37..42,44,45,49,50,52,55..57

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

DMI_IRCOMP_R

USB_RBIAS_PN

ICH8M (2 of 4)

NDA

2

DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7

DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7

DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7

DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7

CLK_PCIE_ICH# 37

CLK_PCIE_ICH 37

USB_PN0 29 USB_PP0 29 USB_PN1 29 USB_PP1 29 USB_PN2 29 USB_PP2 29 USB_PN3 29 USB_PP3 29 USB_PN4 29 USB_PP4 29 USB_PN5 29 USB_PP5 29 USB_PN6 29 USB_PP6 29 USB_PN7 29 USB_PP7 29 USB_PN8 29 USB_PP8 29 USB_PN9 45 USB_PP9 45

R7U18

22.6

1%

2

+V1.5S_PCIE_ICH 21,24

Place within 500

R6G1

24.9

mils of ICH

1%

1% .

.

PCIe Port Configuration 1 (Ports 1-4)

HDA_SDOUT HDA_SYNC

00 01 10

A16 swap override Strap

PCI_GNT#3 Low = A16 swap override enabled

Boot BIOS Strap

SPI_CS#1

1 0

1

Ports Routing Port 1 (x1), Port 2 (x1), Port 3 (x1), Port 4 (x1) [Default] Port 1 (x2), port 3 (x1), port 4 (x1) Port 1 (x2), port 3 (x2) Reserved

11

R8C10

R8C10 1K

1K

NO_STUFF

High = Default

PCI_GNT#0 SPI_CS#1

Boot BIOS LocationPCI_GNT#0 SPI0 PCI LPC (Default)

1

HDA_SYNC21,27

PCI_GNT#2 22,33

PCIe Port Configuration 2 (Ports 5-6)

GNT#

Ports Routing

1

Port 5 (x1), Port 6 (x1) [Default]

0 Port 5 (x2)

PCI_GNT#3

R7U13

R7U13 1K

1K

NO_STUFF

5%

R7U12

R7U12 1K

1K

NO_STUFF

22 58Tuesday, December 05, 2006

PCI_GNT#0_R

1

Intel Confidential

of

R7U14 1K

+V3.3S_1.5S_HDA_IO21,24,27,28

R7G22

R7G22 1K

1K

NO_STUFF

J8E2J8E2

1 2

Default : Open

1.5

5

+V3.3M13..15,24,35,36,42,44,50,56,57

SMB_CLK SMB_DATA

CL_RST#126 SMB_CLK_ME42,44 SMB_DATA_ME42,44

R5G5

R5G6

10K

NO_STUFF

D D

PM_STPPCI#37,44 PM_STPCPU#37,44

5,7,10,12,16..22,24..26,28,30..32,34,37..42,44,45,49,50,52,55..57

VR_PWRGD_CLKEN#52

5,7,10,12,16..22,24..26,28,30..32,34,37..42,44,45,49,50,52,55..57

C C

MCH_ICH_SYNC#7

5,7,10,12,16..22,24..26,28,30..32,34,37..42,44,45,49,50,52,55..57

Default is 1-X for BIOS recovery 1-2

B B

MFG-TEST-JUMPER

A A

PM_ICH_PWROK

R8C8

R8C8 10K

10K

5%

NO_STUFF

R7V34 0

+V3.3S

C7W1

0.1uF

10%

5

.

U6H1

2 4

INVERTER

3

R7G28 0R7G28 0

+V3.3S

R8F6

R8F6 10K

10K

R7G16 0R7G16 0

J8F2J8F2

1 2

5,7,10,12,16..22,24..26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V3.3S

J9J1

2 1

NO_STUFF

MFG-TEST-JUMPER

+V3.3A 19,21,24..29,33,34,39..42,44..48,50..52,55..57

C8C6

0.1uF

10%

.

53

U8C1

4

1 2

74AHC1G08

.

5

BIOS_REC_RBIOS_REC

R9Y2

R9Y2 10K

10K

MFG_MODE

+V3.3S 5,7,10,12,16..22,24..26,28,30..32,34,37..42,44,45,49,50,52,55..57

R7P2

R7P2 2K

2K

1%

.

R7H10

R7H10 100K

100K

5%

+V3.3S

NO_STUFF

J7J1J7J1

R7G27

R7G27 10K

10K

ALL_SYS_PWRGD 42,44,48 DELAY_VR_PWRGOOD 7,52

PM_SUS_STAT#40,42,44

1 2

CLK_SATA_OE#37

BIOS_REC 42

PM_RI#40,44

PM_SYSRST#55

PM_BMBUSY#7

R7G9 0R7G9 0

PM_CLKRUN#33,34,40,42,44

PCIE_WAKE#19,25,26,45

INT_SERIRQ33,40,42,44

PM_THRM#5,12,42,44

BIOS_REC_R

SV_SET_UP ICH_GPIO20

FWH_WP#39,44

IDE_PATADET32,44

HDA_SPKR27,45

ICH_TP321

GLAN_DOCK#

4

SMB_ALERT# PM_STPPCI_ICH#

PM_STPCPU_ICH#

VR_PWRGD_CLKEN

ICH_TP7 SMC_EXTSMI#_R SMC_RUNTIME_SCI#_R

SMC_WAKE_SCI#_R

LAN_PHYPC_R

FWH_TBL#_R

SATA_PWR_EN#0_R SATA_PWR_EN#1_R

ICH_GPIO39

MCH_ICH_SYNC_R#

+V3.3A19,21,24..29,33,34,39..42,44..48,50..52,55..57

R7V6

R7V6 10K

10K

5%

SATA_PWR_EN#1_R

R7V20 0R7V20 0

4

MFG_MODE

R7V21 0

U7F1C

AJ26 AD19 AG21 AC17 AE19

AF17

F4

AD15 AG12 AG22 AE20

AG18 AH11 AE17

AF12 AC13

AJ20

AJ22

AJ8 AJ9

AH9 AE16 AC19

AG8 AH12 AE11 AG10 AH25 AD16 AG13

AF9

AJ11

AD10

AD9

AJ13 AJ21

ICH8M REV 1.0

NO_STUFF

SMB_CLK SMB_DATA

SATA_PWR_EN#1_R SATA_PWR_EN#1 31

SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1

RI# SUS_STAT#/LPCPD#

SYS_RESET# BMBUSY#/GPIO0 SMBALERT#/GPIO11 STP_PCI#/GPIO15

STP_CPU#/GPIO25 CLKRUN#/GPIO32 WAKE#

SERIRQ THRM#

VRMPWRGD TP7 TACH1/GPIO1

TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48

SPKR MCH_SYNC# TP3

DOCK_LAN_EN# 36,45

+V3.3S5,7,10,12,16..22,24..26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V3.3M13..15,24,35,36,42,44,50,56,57

+V3.3A19,21,24..29,33,34,39..42,44..48,50..52,55..57

R7R2 10KR7R2 10K R7R4 10KR7R4 10K R7R5 10KR7R5 10K R7R3 10KR7R3 10K

R7R8 10KR7R8 10K R7R11 10KR7R11 10K R7R9 10KR7R9 10K R7R7 10KR7R7 10K

3

SATA0GP

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

PWROK

BATLOW# PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST#

R8C9 10KR8C9 10K R8D1 10KR8D1 10K

R7D3 10KR7D3 10K R7D1 10KR7D1 10K

R7R10 10KR7R10 10K R7R12 10KR7R12 10K

R9A9 10KR9A9 10K R9A10 10KR9A10 10K

U7D1

1

EXPSCL1

2

EXPSCL2

18

EXPSDA1

19

EXPSDA2

3

SCL0

4

SDA0

7

EN1

11

EN2

14

EN3

17

EN4

10

VSS

EXP. 5-CH-I2C HUB

GLAN_DOCK#

3

AJ12

SATA1GP

AJ10 AF11 AG11

AG9 G5

D3

SLP_S3#_R

AG23

SLP_S4#_R

AF21 AD18

AH27

PM_ICH_PWROK

AE23

PM_DPRSLPVR_R

AJ14

PM_BATLOW#_R

AE21 C2 AH20

PM_RSMRST#_R

AG27 E1 E3 AJ25 F23

AE18 F22

AF19

CL_VREF0_ICH

D24

CL_VREF1_ICH

AH23 AJ23 AJ27

AJ24 AF22 AG19

LAN_PHYPC_R

LAN_PHYPC 22,35

SMC_RUNTIME_SCI#_R

SMC_RUNTIME_SCI# 42,44

SMC_WAKE_SCI#_R

SMC_WAKE_SCI# 42,44

FWH_TBL#_R

FWH_TBL# 39,44

SMC_EXTSMI#_R

SMC_EXTSMI# 40,42,44,45

SATA_PWR_EN#0_R

SATA_PWR_EN#0 30

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36

SATA

GPIO

SATA

GPIO

SATA3GP/GPIO37

SMB

Clocks

S4_STATE#/GPIO26

SYS

GPIO

SYS

GPIO

DPRSLPVR/GPIO16

Power MGTController Link

GPIO

MEM_LED/GPIO24

ALERT#/GPIO10

NETDETECT/GPIO14

WOL_EN/GPIO9

MISC

+V3.3A 19,21,24..29,33,34,39..42,44..48,50..52,55..57

+V3.3M 13..15,24,35,36,42,44,50,56,57

+V3.3S5,7,10,12,16..22,24..26,28,30..32,34,37..42,44,45,49,50,52,55..57

CL1 CL2 DA1 DA2

I2C_EN1 I2C_EN2 I2C_EN3 I2C_EN4

LAN_PHYPC_R ICH_GPIO39

R7V22 0

.

R7G7 0

NO_STUFF

SMC_RUNTIME_SCI#_R

R7V27 0R7V27 0

SMC_WAKE_SCI#_R

R7V18 0R7V18 0

FWH_TBL#_R

R7V12 0R7V12 0

SMC_EXTSMI#_R

R7G3 0R7G3 0

SATA_PWR_EN#0_R

R7V29 0R7V29 0

R8G8

R8G8 100K

100K

5%

SMB_CLK_A1 SMB_DATA_A1

SMB_CLK_M3 SMB_DATA_M3

SMB_CLK_M2 SMB_DATA_M2

SMB_CLK_S4 SMB_DATA_S4

20

VCC

5

SCL1

6

SDA1

8

SCL2

9

SDA2

12

SCL3

13

SDA3

15

SCL4

16

SDA4

R7V35 100R7V35 100 R7V13 100R7V13 100 R7V5 100R7V5 100 R7V14 100R7V14 100

CLK_REF_ICH 37 CLK_USB48 37

SUS_CLK 44

R7G25 100R7G25 100 R7G15 100R7G15 100

PM_S4_STATE# 34,42,44,45,56,57

R7G21 100R7G21 100 R7G24 0R7G24 0

R6G14 100R6G14 100

CLK_PWRGD 37,38 MPWROK 7,47 PM_SLP_M# 42,44,45,48,56,57

CL_CLK0 7 CL_CLK1 26

CL_DATA0 7 CL_DATA1 26

CL_RST#0 7

CRB_SV_DET ME_SMC_ALERT# 42,44

SMC_ME_ALERT 42,44,55

LAN_WOL_EN 42,44,56,57

If used, pull-up on CRB_SV_DET

must be to +V3.3A

+V3.3A19,21,24..29,33,34,39..42,44..48,50..52,55..57

SMB_CLK_A1 25,26,33,34,45 SMB_DATA_A1 25,26,33,34,45

SMB_CLK_M2 13..15 SMB_DATA_M2 13..15

SMB_CLK_M3 37,38 SMB_DATA_M3 37,38

SMB_CLK_S4 19,44 SMB_DATA_S4 19,44

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

2

ICH_GPIO37_R ICH_GPIO36_R

SATA_DET#1 31,42 ICH_GPIO36

PATA_PWR_EN# 32,44

PM_SLP_S3# 11,26,42,44,45,48,56,57 PM_SLP_S4# 47,56 PM_SLP_S5# 57

PM_DPRSLPVR 7,44,52

PM_BATLOW# 42,44 PM_PWRBTN# 42,44 PM_LAN_ENABLE 35,42,44

PM_RSMRST# 42,44

C7R2

0.1uF

20%

20% .

.

ICH8M (3 of 4)

NDA

2

13..15,24,35,36,42,44,50,56,57 +V3.3M

R7F13

3.24K

1%

12

R7F14

C7F2

453_1%

0.1uF

10%

.

+V3.3A 19,21,24..29,33,34,39..42,44..48,50..52,55..57

R7G10

3.24K

1%

12

C7V11

R7V16

0.1uF

453_1%

10%

.

ICH8-M Pullups

No Reboot Strap

HDA_SPKR

PM_RI#

CL_RST#1 SMB_CLK_ME SMB_DATA_ME

SMB_CLK SMB_DATA

SMB_ALERT# PCIE_WAKE# PM_BATLOW#_R LAN_PHYPC

CLK_SATA_OE# PM_THRM# INT_SERIRQ PM_CLKRUN# FWH_WP#

ALL_SYS_PWRGD PM_RSMRST#

1

Low = Default High = No Reboot

CL_RST#0

CL_CLK0

CL_DATA0

CL_RST#1

CL_CLK1

CL_DATA1

23 58Tuesday, December 05, 2006

1

+V3.3S5,7,10,12,16..22,24..26,28,30..32,34,37..42,44,45,49,50,52,55..57

HDA_SPKR

RP6U1A

RP6U1B

RP6U1C

RP6U1D

RP8U1A

RP8U1B

RP8U1C

RP8U1D

R7T21 10KR7T21 10K

NO_STUFF

R7V8 10K

R7V8 10K R7V11 10KR7V11 10K R7V10 10KR7V10 10K

R7D10 2.2KR7D10 2.2K R7D12 2.2KR7D12 2.2K

R7V7 10KR7V7 10K R7U1 1KR7U1 1K R7V36 8.2KR7V36 8.2K R7V9 10KR7V9 10K

R7V24 10KR7V24 10K R9V14 8.2KR9V14 8.2K R7T13 10KR7T13 10K R9V18 8.2KR9V18 8.2K R7V23 10KR7V23 10K

R8V1 10KR8V1 10K

R8G5 10KR8G5 10K R8G6 10KR8G6 10K

Intel Confidential

of

R7G20

R7G20 1K

1K

NO_STUFF

18

0NO_STUFF

27

0NO_STUFF

36

0NO_STUFF

45

0NO_STUFF

18

0NO_STUFF

27

0NO_STUFF

36

0NO_STUFF

45

0NO_STUFF

+V3.3A19,21,24..29,33,34,39..42,44..48,50..52,55..57

+V3.3S5,7,10,12,16..22,24..26,28,30..32,34,37..42,44,45,49,50,52,55..57

1.5

5

6

+V3.3A_RTC21

5,7,10,12,16..23,25,26,28,30..32,34,37..42,44,45,49,50,52,55..57

5,11,12,16..18,30..32,34,41,49,50,52,53,55..57

29,40,42,47,48,51,55,57

19,21,23,25..29,33,34,39..42,44..48,50..52,55..57

D D

+V1.5S,5

+V5A

R6F13 0.002

1%

+V3.3A

R8U1

R8U1 10

10

5%

+V1.5S_PCIE_R

1

3

CR8U1

CR8U1 BAT54

BAT54

+V5S

R7F4

R7F4 100

100

C7U6

0.1uF

10% 10V

.

SMC0402

.

SMC0402

FB6V1

330ohm@100MHz

+V1.5S_PCIE_ICH21,22

+V3.3S

C6G2

C6G2 220uF

220uF

20%

20% 4V

4V

1

3

CR7F1

CR7F1 BAT54

BAT54

C7V1

0.1uF

10% 10V

.

SMC0402

.

SMC0402

C6V2

C6V2 22uF

22uF

20%

VCC5REF

C6V4

0.1uF

10%10V

.

SMC0402

.

SMC0402

C6F2

C6F2 22uF

22uF

20%

C C

+V1.5S,5

+V1.5S_SATA_ICH

1%

GLANPLL_R

5

+V1.5S_APLL_ICH_R

+V1.5S_SATA_ICH

+V1.5S_USB_ICH

+V3.3M_VCCPAUX

C7U5

0.1uF

10%10V

.

SMC0402

.

SMC0402

1 2

1uH

+V1.5S_PCIE_ICH21,22

L7E1

+V3.3S5,7,10,12,16..23,25,26,28,30..32,34,37..42,44,45,49,50,52,55..57

10uH

+V1.5S_SATA_ICH

R6F2 0.002

R8G2 0.002

R8G2 0.0021%R7V3 0R7V3 0

1%

B B

R8F7 0.002

13..15,23,35,36,42,44,50,56,57

4,10,11,28,48,56

+V1.5S

1%

+V3.3M

R7F1 0.002

R7F2 1R7F2 1

A A

L8G1

C7U7

0.1uF

10% 10V

.

SMC0402

.

SMC0402

GLANPLL_R_L

C7U1

C7U1 10uF

10uF

20%

+V1.5S_APLL_ICH

C7G1

C7G1 10uF

10uF

20%

20% SMC0805

SMC0805

C7U4

0.1uF

10% 10V

10% 10V SMC0402

SMC0402

TP_VCCLAN1_05_ICH_1 TP_VCCLAN1_05_ICH_2

C7F3

2.2uF

10%

10% SMC0603

SMC0603

C7F4

4.7uF

10%

+V3.3S_GLAN_ICH

1%

C6V5

0.1uF

10% 10V

.

SMC0402

.

SMC0402

C6G1

2.2uF

10%

10% SMC0603

SMC0603

C7G2

C7G2 1uF

1uF

20%

C7G3

C7G3 1UF

1UF

20%

C8G2

C8G2 1UF

1UF

20%

.

V5REF_SUS

4

AD25

AA25 AA26 AA27 AB27 AB28 AB29

M24 M25

W25

AG7 AH7

AC1 AC2 AC3 AC4 AC5

AC10

AC9

AC7 AD7

W23

A16

T7

G4

D28 D29 E25 E26 E27 F24 F25 G24 H23 H24

J23

J24 K24 K25 L23 L24 L25

N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25

Y25 AJ6 AE7

AF7

AJ7

AA5 AA6

G12 G17

H7

D1

F1 L6

L7 M6 M7

F17 G18

F19 G20

A24 A26

A27 B26 B27 B28

B25

U7F1F

VCCRTC V5REF[1]

V5REF[2] V5REF_SUS VCC1_5_B[01]

VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46]

VCCSATAPLL VCC1_5_A[01]

VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05]

VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10]

VCC1_5_A[11] VCC1_5_A[12]

VCC1_5_A[13] VCC1_5_A[14]

VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17]

VCC1_5_A[18] VCC1_5_A[19]

VCCUSBPLL VCC1_5_A[20]

VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24]

VCC1_5_A[25] VCCLAN1_05[1]

VCCLAN1_05[2] VCCLAN3_3[1]

VCCLAN3_3[2] VCCGLANPLL VCCGLAN1_5[1]

VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

CORE

VCCA3GP ATXARX

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2] VCCSUS3_3[01] VCCSUS3_3[02]

VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06] VCCSUS3_3[07]

VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19]

GLAN POWER

VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28]

VCCDMIPLL VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1] V_CPU_IO[2]

VCC3_3[01] VCC3_3[02] VCC3_3[03]

VCC3_3[04] VCC3_3[05] VCC3_3[06]

VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]

VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24]

VCCHDA

VCCSUSHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1] VCCCL3_3[2]

A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

R29 AE28

AE29 AC23

AC24 AF29 AD2 AC8

AD8 AE8 AF8

AA3 U7 V7 W1 W6 W7 Y7

A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11

AC12 AD11

TP_VCCSUS1_05_ICH_1

J6

TP_VCCSUS1_05_ICH_2

AF20

TP_VCCSUS1_5_ICH_1

AC16

TP_VCCSUS1_5_ICH_2

J7 C3 AC18

AC21 AC22 AG20 AH28

P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6

TP_VCCCL1_05_ICH

G22

VCCCL1_5_INT_ICH

A22 F20

G21

3

VCCDMIPLL_ICH

+V1.25S_DMI_ICH

C7V2

0.1uF

10% 10V

.

SMC0402

.

SMC0402

C7U2

0.1uF

10% 10V

.

SMC0402

.

SMC0402

+V3.3A_USB_ICH

+V3.3M_ICH

R7U3 0.002

3

C7V3

0.1uF

10% 10V

.

SMC0402

.

SMC0402

C7F6

0.1uF

10% 10V

.

SMC0402

.

SMC0402

+V3.3S_1.5S_HDA_IO_ICH

C8F3

4.7uF

20%

C7F1

C7F1 1UF

1UF

20%

20% NO_STUFF

NO_STUFF

13..15,23,35,36,42,44,50,56,57

1%

C6F12

0.01uF

10%

10% 402

402

R6G3 0.002

C6G4

C6G4 22uF

22uF

20%

C7V9

0.1uF

10% 10V

.

SMC0402

.

SMC0402

C7U3

0.1uF

10% 10V

.

SMC0402

.

SMC0402

+V3.3A_ICH

C7V5

0.1uF

10% 10V

.

SMC0402

.

SMC0402

C7F5

0.1uF

10% 10V

10% 10V SMC0402

SMC0402

NO_STUFF

+V3.3M

C7U8

0.1uF

10% 10V

.

SMC0402

.

SMC0402

C6V1

C6V1 10uF

10uF

20%

+V3.3A_1.5A_HDA_IO27,28,45

C7V10

0.1uF

10% 10V

.

SMC0402

.

SMC0402

+V1.05S_ICH

R7F12 0.002

L6G1

GPLL_R

1 2

1uH

+V1.25S10,56,57

1%

C7V7

0.1uF

10% 10V

.

SMC0402

.

SMC0402

C6V3

0.1uF

10% 10V

.

SMC0402

.

SMC0402

Layout Note: Distribute in PCI section

C7V8

0.1uF

10% 10V

.

SMC0402

.

SMC0402

R6V12 0.002

1%

R8F4 0.002

1%

Title

Size Document Number Rev

Date: Sheet

R6F12 1R6F12 1

+V1.05S_ICH_IO21

C7V6

0.1uF

10% 10V

.

SMC0402

.

SMC0402

+V3.3S_DMI_ICH

+V3.3S_SATA_ICH

+V3.3S_VCCPCORE_ICH

+V3.3S_IDE_ICH

+V3.3S_PCI_ICH

R7V4 0.022R7V4 0.022

C7V4

0.1uF

10% 10V

.

SMC0402

.

SMC0402

+V3.3A 19,21,23,25..29,33,34,39..42,44..48,50..52,55..57

Matanzas

ICH8M (4 of 4)

NDA

A

2

+V1.05S4,9,10,48,56

1%

+V1.5S4,10,11,28,48,56

R6V11 0.002

C6G3

4.7uF

10%

R6G4 0.002

R8G7 0.002

R8V14 0.002

R8G1 0.002

R8F5 0.002

+V3.3S_1.5S_HDA_IO21,27,28

2

1

U7F1E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

+V1.05S4,9,10,48,56

1%

+V3.3S5,7,10,12,16..23,25,26,28,30..32,34,37..42,44,45,49,50,52,55..57

1%

AF14 AF16 AF18

AH10 AH13 AH16 AH19

AF28 AH22 AH24 AH26

AE6 AE9

AF3 AF4 AG5 AG6

AH2

AH3 AH4 AH8

C24 C26 C27

D12 D15 D18

G10 G13 G19 G23 G25 G26 G27 H25 H28 H29

AJ5 B11 B14 B17

B2 B20 B22

B8

C6

D2

D4 E21 E24

E4

E9 F15 E23 F28 F29

F7

G1

E2

H3 H6

J1 J25 J26 J27

J4

J5 K23 K28 K29

K3

K6

VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098]

ICH8M REV 1.0

VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]

VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184]

24 58Tuesday, December 05, 2006

K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24

A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29

Intel Confidential

of

1.5

1

5

4

3

2

1

D D

+V3.3S5,7,10,12,16..24,26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V3.3A 19,21,23,24,26..29,33,34,39..42,44..48,50..52,55..57

1%

+V12S26,30..33,44,56,57

1%

C7B13

C7B13 22uF

22uF

C7B11

0.1uF

10%

.

+12V3 +12V4

GND6 JTAG2 JTAG3 JTAG4 JTAG5

+3.3V2 +3.3V3

PWRGD

GND7

GND8

HSLP_0 HSLN_0

GND9

+V12S_PCIESLOT1

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

+V3.3S_PCIESLOT1

PCIESLOT1_PRSNT#1

PLT_RST# 7,19,22,26,39,40,42,57

CLK_PCIE_SLOT1 38 CLK_PCIE_SLOT1# 38

PCIE_RXP1_SLOT1 22 PCIE_RXN1_SLOT1 22

R6N80R6N8 0

+V3.3S_PCIESLOT1

C6B10

C6B10 22uF

22uF

+V12S_PCIESLOT1

C7B8

C7B8 22uF

22uF

C6B14

0.1uF

10%

.

C7B6

0.1uF

10%

R7N10 0.002

C7B10

0.1uF

10%

.

R7N11 0.002

C6B5

0.1uF

10%

+V12S_PCIESLOT1

+V3.3S_PCIESLOT1

+V3.3A19,21,23,24,26..29,33,34,39..42,44..48,50..52,55..57

SMB_CLK_A123,26,33,34,45 SMB_DATA_A123,26,33,34,45

+V3.3S_PCIESLOT1

PCIE_WAKE#19,23,26,45

R7C4

R7C4 10K

10K

5%

C C

CLK_SLOT1_OE#38

PCIE_TXP1_SLOT122 PCIE_TXN1_SLOT122

J6B1

B1

+12V1 +12V2 RSVD1 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG

3.3VAUX WAKE#

RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5

PCIE_X1

Key

PRSNT1#

REFCLK+

REFCLK-

B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18

SLOT 1

NOTE: SLOTS 1 AND 2 ARE PHYSICALY IN-LINE

+V12S_PCIESLOT2

+V3.3S_PCIESLOT2

+V3.3A19,21,23,24,26..29,33,34,39..42,44..48,50..52,55..57

SMB_CLK_A1 SMB_DATA_A1

B B

CLK_SLOT2_OE#38

+V3.3S_PCIESLOT2

R7D13

R7D13 10K

10K

5%

PCIE_WAKE# PLT_RST#

PCIE_TXP2_SLOT222 PCIE_TXN2_SLOT222

J6D1

B1

+12V1 +12V2 RSVD1 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG

3.3VAUX WAKE#

RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5

PCIE_X1

Key

PRSNT1#

REFCLK+

REFCLK-

B2

B3

B4

B5

B6

B7

B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18

+12V3 +12V4

GND6 JTAG2 JTAG3 JTAG4 JTAG5

+3.3V2 +3.3V3

PWRGD

GND7

GND8

HSLP_0 HSLN_0

GND9

+V12S_PCIESLOT2

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

+V3.3S_PCIESLOT2

PCIESLOT2_PRSNT#1

CLK_PCIE_SLOT2 38 CLK_PCIE_SLOT2# 38

PCIE_RXP2_SLOT2 22 PCIE_RXN2_SLOT2 22

R7R60R7R6 0

+V3.3S_PCIESLOT2

C7D1

C7D1 22uF

22uF

+V12S_PCIESLOT2

C7C1

C7C1 22uF

22uF

C7D2

0.1uF

10%

.

C6C12

0.1uF

10%

R7R1 0.002

C6D5

0.1uF

10%

.

R7C20 0.002

C7C3

0.1uF

10%

+V3.3S5,7,10,12,16..24,26,28,30..32,34,37..42,44,45,49,50,52,55..57

+V3.3A 19,21,23,24,26..29,33,34,39..42,44..48,50..52,55..57

1%

+V12S26,30..33,44,56,57

1%

C7B16

C7B16 22uF

22uF

C7B14

0.1uF

10%

.

SLOT 2

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

PCI-E Slots (1 & 2)

NDA

2

25 58Tuesday, November 21, 2006

1

Intel Confidential

1.5

of

5

4

3

2

1

+V3.3A19,21,23..25,27..29,33,34,39..42,44..48,50..52,55..57

+V12S_PCIESLOT3

B1

+12V1

B2

+12V2

B3

RSVD1

B4

GND1

B5

SMCLK

B6

SMDAT

B7

GND2

B8

+3.3V1

B9

JTAG

B10

3.3VAUX

B11

WAKE#

B12

RSVD2

B13

GND3

B14

HSOP_0

B15

HSON_0

B16

GND4

B17

PRSNT2#

B18

GND5

+V12S_PCIESLOT4

B1

+12V1

B2

+12V2

B3

RSVD1

B4

GND1

B5

SMCLK

B6

SMDAT

B7

GND2

B8

+3.3V1

B9

JTAG

B10

3.3VAUX

B11

WAKE#

B12

RSVD2

B13

GND3

B14

HSOP_0

B15

HSON_0

B16

GND4

B17

PRSNT2#

B18

GND5

J8B4

Key

PCIE_X1

SLOT 3

J8D1

Key

PCIE_X1

PRSNT1#

REFCLK+

REFCLK-

PRSNT1#

REFCLK+

REFCLK-

+V3.3S_PCIESLOT3

D D

CLK_SLOT3_OE#38

NOTE: SLOTS 3 AND 4 ARE PHYSICALY IN-LINE

C C

CLK_SLOT4_OE#38

SMB_CLK_A123,25,33,34,45 SMB_DATA_A123,25,33,34,45

+V3.3S_PCIESLOT3

R8C1

R8C1 10K

10K

5%

PCIE_TXP3_SLOT322 PCIE_TXN3_SLOT322

+V3.3S_PCIESLOT4

R8D5

R8D5 10K

10K

5%

PCIE_TXP4_SLOT422

PCIE_TXN4_SLOT422

PCIE_WAKE#19,23,25,45

+V3.3S_PCIESLOT4

+V3.3_PCIE_VAUX

SMB_CLK_A1 PCIESLOT4_A5 SMB_DATA_A1

PCIE_WAKE#

SLOT 4

B B

+V3.3S_PCIESLOT5

+V3.3A19,21,23..25,27..29,33,34,39..42,44..48,50..52,55..57

SMB_CLK_A1 SMB_DATA_A1

+V3.3S_PCIESLOT5

R7C3

R7C3 10K

10K

5%

CLK_SLOT5_OE#38 PCIE_RXN5_SLOT5 22

PCIE_WAKE#

PCIE_TXP5_SLOT522

PCIE_TXN5_SLOT522

A A

5

B10 B11

B12 B13 B14 B15 B16 B17 B18

B1 B2 B3 B4 B5 B6 B7 B8 B9

J7B1

+12V1 +12V2 RSVD1 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG

3.3VAUX WAKE#

Key

RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5

PCIE_X1

SLOT 5

PRSNT1#

JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3

PWRGD

REFCLK+

REFCLK-

HSLP_0 HSLN_0

+12V3 +12V4

GND6 JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3

PWRGD

GND7

GND8

HSLP_0 HSLN_0

GND9

+12V3

+12V4

GND6 JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3

PWRGD

GND7

GND8

HSLP_0 HSLN_0

GND9

+12V3 +12V4

GND6

GND7

GND8

GND9

+V12S_PCIESLOT3

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

+V12S_PCIESLOT4

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

+V12S_PCIESLOT5+V12S_PCIESLOT5

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

4

+V3.3S_PCIESLOT3

PCIESLOT3_PRSNT1#

PLT_RST# 7,19,22,25,39,40,42,57

CLK_PCIE_SLOT3 38 CLK_PCIE_SLOT3# 38

PCIE_RXP3_SLOT3 22 PCIE_RXN3_SLOT3 22

+V3.3S_PCIESLOT4

PCIESLOT4_PRSNT1#

PCIESLOT4_A6 PCIESLOT4_A8

PLT_RST#

CLK_PCIE_SLOT4 38 CLK_PCIE_SLOT4# 38

PCIE_RXP4_SLOT4 22 PCIE_RXN4_SLOT4 22

+V3.3S_PCIESLOT5

PCIESLOT5_PRSNT1#

PLT_RST#

CLK_PCIE_SLOT5 38 CLK_PCIE_SLOT5# 38

PCIE_RXP5_SLOT5 22

R7N70R7N7 0

R8B40R8B4 0

R7P130R7P13 0

+V3.3S_PCIESLOT3

+V12S_PCIESLOT3

+V3.3S_PCIESLOT4

+V12S_PCIESLOT4

+V3.3S_PCIESLOT5

C7B15

C7B15 22uF

22uF

+V12S_PCIESLOT5

C7B4

C7B4 22uF

22uF

+V3.3A19,21,23..25,27..29,33,34,39..42,44..48,50..52,55..57

C7D4

C7D4 22uF

22uF

C7B17

C7B17 22uF

22uF

C8D1

C8D1 22uF

22uF

C8C7

C8C7 22uF

22uF

C8B2

C8B2 22uF

22uF

C7B12

0.1uF

10%

.

C7B5

0.1uF

10%

C7D3

0.1uF

10%

.

3

C8B10

0.1uF

10%

.

C8D4

0.1uF

10%

.

C8C8

0.1uF

10%

C8B6

0.1uF

10%

C7B9

0.1uF

10%

.

C7B7

0.1uF

10%

R7N5 0.002

R7N5 0.002 C8B11

C8B11

0.1uF

10%

.

R8B2 0.002

C8B4

0.1uF

10%

R8D2 0.002

C8D3

0.1uF

10%

.

R8C7 0.002

C8C10

0.1uF

10%

R7N8 0.002

1%

R7N9 0.002

1%

+V3.3S5,7,10,12,16..25,28,30..32,34,37..42,44,45,49,50,52,55..57

1%

+V3.3S5,7,10,12,16..25,28,30..32,34,37..42,44,45,49,50,52,55..57

1%

+V12S25,30..33,44,56,57

+V3.3A 19,21,23..25,27..29,33,34,39..42,44..48,50..52,55..57

C8B12

0.1uF

C8B13

C8B13 22uF

22uF

10%

.

+V12S25,30..33,44,56,57

+V3.3_PCIE_VAUX

C8D5

0.1uF

C8D6

C8D6 22uF

22uF

10%

.

Net Detect VAUX Switch

1%

+VBATA46..48,55,57

+V3.3A19,21,23..25,27..29,33,34,39..42,44..48,50..52,55..57

R7P3

SLP_S3M_OK

100K

+V3.3S5,7,10,12,16..25,28,30..32,34,37..42,44,45,49,50,52,55..57

PM_SLP_S3#11,23,42,44,45,48,56,57

EC_VAUX_ON42

+V12S25,30..33,44,56,57

Matanzas

Title

Size Document Number Rev

Date: Sheet

PCI-E Slots (3,4 & 5)

NDA

2

3

1

2

Q7P2

BSS138

Q7P3

Q7P3 BSS138

BSS138

.

PCIESLOT4_A6 PCIESLOT4_A8 PCIESLOT4_A5

R7P5 100KR7P5 100K

R7P4

R7P4 100K

100K

.

1

3

1

2

R7D9 0R7D9 0 R7D11 0R7D11 0 R7D8 0R7D8 0

+V3.3A19,21,23..25,27..29,33,34,39..42,44..48,50..52,55..57

783 6 5

VAUX_G_SWITCH

3

Q7P1

Q7P1 BSS138

BSS138

.

2

26 58Tuesday, November 21, 2006

+V3.3_PCIE_VAUX

Q7R1

Q7R1 IRF7822

IRF7822

.

2 1

4

C7R1

0.01UF

.

. 10%

10%

CL_RST#1 23 CL_DATA1 23 CL_CLK1 23

Intel Confidential

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1

1.5

5

4

3

2

1

Layout Toplogy for HDA Clk,Sync,RST,SDout,Enable

*

HDA_BIT_CLK21

HDA_RST#21

D D

HDA_SYNC21

HDA_SDOUT21

R7W3 0R7W3 0 R7H4 33R7H4 33

R7W2 0R7W2 0 R7H2 33R7H2 33 R7W4 0R7W4 0

R7H5 33R7H5 33 R7W1 0R7W1 0 R7H3 33R7H3 33

HDA_CODEC_0_1_2_CLK

HDA_CODEC_0_1_2_RST#

HDA_CODEC_0_1_2_SYNC

HDA_CODEC_0_1_2_SDATAOUT

HDA_SDIN2

R9N4 0

NO_STUFF

HDA_CODEC_3_CLK

HDA_CODEC_3_RST#

HDA_CODEC_3_SYNC

HDA_CODEC_3_SDATAOUT

HDA_DOCK_SDATAIN

ICH

13x2 HeaderDocking Connector

***

Note: Place the resistors "*" as

**

Marked in the Diagram

* *

8x2 Header

GMCH

HDA Header for MDC Interposer

**

C C

B B

A A

HDA_CODEC_0_1_2_CLK HDA_MDC_BITCLK HDA_CODEC_0_1_2_SYNC

HDA_SDIN021 HDA_SDIN121 HDA_SDIN321

HDA_SDIN221

HDA_DOCK_RST#21,45

HDA_DOCK_EN#

HDA_CODEC_0_1_2_CLK

U9D2

1 2

NC7SV125L

OE#

VCC A GND3Y

R9D4 33R9D4 33 R9E1 33R9E1 33 R9D8 33R9D8 33 R9E3 33R9E3 33

R9E8 0R9E8 0 R9E11 0R9E11 0

R9E7 0

NO_STUFF

R9E10 0R9E10 0

+V3.3S_1.5S_HDA_IO21,24,28

6 5

NC

4

R9D5 33R9D5 33

HDA_BCLK_R

R9D7

R9D7 20K

20K

5

HDA_MDC_RST#HDA_CODEC_0_1_2_RST# HDA_MDC_SYNC HDA_MDC_SDOHDA_CODEC_0_1_2_SDATAOUT

HDA_MDC_SDATAIN1 HDA_MDC_SDATAIN3 HDA_MDC_SDATAIN2

HDA_AUDIO_PWRDN_NET

R9E15

R9E15 10K

10K

5%

C9D5

0.1uF

20%

+V3.3A19,21,23..26,28,29,33,34,39..42,44..48,50..52,55..57

J9E2

15

16

13

14

11

12

9

10

8

7 6 4

3 2

1

2X8_HDR_KEY12

1 2 3 4 5 6 7 8

J9E4

8Pin HDR

Layout Note: Place both headers in-line and exactly 200 mils from each other, pin-to-pin. Draw one silkscreen box around both parts.

U9D3

1

OE#

HDA_CODEC_0_1_2_SYNC HDA_CODEC_0_1_2_SDATAOUT

HDA_BCLK_DOCK 45

2

A GND3Y

NC7SV125L

VCC

4

+V5 33,43..45,50,52,55..57

+V3.319,33,41..44,49,56,57

+V3.3A_1.5A_HDA_IO24,28,45

+VBATS_HDA_R1

HDA_SPKR_R

HDA_DOCK_EN#_J

R9E14 0R9E14 0

R9E16 0R9E16 0

HDA_SPKR 23,45

HDA Docking Circuit

+V3.3S_1.5S_HDA_IO21,24,28 +V3.3S_1.5S_HDA_IO21,24,28

C9D6

0.1uF

20%

6 5

NC

R9D9 33R9D9 33

4

HDA_SYNC_R

R9E2

R9E2 20K

20K

20%

+VBATS16,19,56,57

R9E60R9E6 0

HDA_DOCK_EN# 21,42

U9E1

1

OE#

VCC

2

A

NC

GND3Y

NC7SV125L

3

6 5 4

HDA Header for External HDMI Support

+V3.319,33,41..44,49,56,57

J6C2

HDA_CODEC_3_CLK HDA_CODEC_3_RST# HDA_CODEC_3_SYNC HDA_CODEC_3_SDATAOUT

R9E4 33R9E4 33

HDA_SDO_R

R9E5

R9E5 20K

20K

R9E13 0

R9E13 0 R9E12 0

R9E12 0 R9E9 0

R9E9 0

These Resistors need to be Mounted appropriately when SDIN2 & SDIN3 need to get tested using the MDC.

C9E1

0.1uF

20%

HDA_SDO_DOCK 45HDA_SYNC_DOCK 45

Matanzas

Title

Size Document Number Rev

Date: Sheet

High Definition Audio

A

NDA

HDA_SDIN2_RHDA_SDIN2

NO_STUFF

HDA_SDIN3_R1HDA_SDIN3

NO_STUFF

HDA_SDIN3_R2

NO_STUFF

HDA_DOCK_EN# HDA_DOCK_SDATAIN

2

J6C2

15

16

13

14

11

12

9

10

8

7 6 4

3 2

1

2X8_HDR_KEY12

U9B2

1

OE1#

2

1A

3

1B GND42A

74CBT3306

R9N5 20KR9N5 20K

VCC

OE2#

2B

+V3.3A_1.5A_HDA_IO24,28,45

+VBATS_HDA_R2

+V5 33,43..45,50,52,55..57

C9B4

0.1uF

20%

8 7 6 5

20%

27 58Tuesday, December 05, 2006

Intel Confidential

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1

+VBATS16,19,56,57

R6C60R6C6 0

HDA_SDATAIN_DOCK 45

1.5

5

4

3

2

1

D D

Power Supply for High Definiton Audio

+V3.3A19,21,23..27,29,33,34,39..42,44..48,50..52,55..57

R8R1

R8R1 10K

10K

5%

C8E1

1.0uF

10%

5%

U8E1 SC1563U8E1 SC1563

5

IN

1

SHDN

GND2ADJ

SC1563_SHDN

R8T1

R8T1 100

100

OUT

3

HDA_IO_ADJ

+V1.5A_HDA_IO

4

R8T3

2.55K

1%

R8T2

R8T2 10K

10K

1%

C8E3

C8E3 22uF

22uF

C8T1

0.1uF

10%

.

+V3.3A19,21,23..27,29,33,34,39..42,44..48,50..52,55..57

3

Q8T1

C C

VR_ALW_ENABLE46,55

1

Q8T1 BSS138

BSS138

2

Selection of I/O Voltage for the High Definition Audio

B B

+V3.3A19,21,23..27,29,33,34,39..42,44..48,50..52,55..57 +V1.5A_HDA_IO

Layout Notes:Place the Two Resistors Next to each Other

NO_STUFF

R8E8 0.002

R8E8 0.002 R8E7 0.002

R8E7 0.002

1%

1% 1%

1%

5,7,10,12,16..26,30..32,34,37..42,44,45,49,50,52,55..57

+V3.3A_1.5A_HDA_IO24,27,45

A A

5

4

3

+V3.3S

+V1.5S 4,10,11,24,48,56

+V3.3S_1.5S_HDA_IO21,24,27

NO_STUFF

R7H6 0.002

R7H6 0.002 R7W5 0.002

R7W5 0.002

Layout Notes:Place the Two Resistors Next to each Other

Matanzas

Title

Size Document Number Rev

Date: Sheet

HDA Power Supply

NDA

A

NDA

A

NDA

A

2

1%

1% 1%

1%

Intel Confidential

28 58Tuesday, November 21, 2006

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1

1.5

5

8 7 6 5

+V3.3A19,21,23..28,33,34,39..42,44..48,50..52,55..57

18

RP3B1A

RP3B1A 10K

10K

+V3.3A19,21,23..28,33,34,39..42,44..48,50..52,55..57

36

RP3B1C

RP3B1C 10K

10K

+V5A_USBPWR_PN3

24,40,42,47,48,51,55,57

+V5A

R3B5

0.002

1%

+V5A_USBPWR_IN3

C3B3

0.1uF

20%

C3B2

0.1uF

20%

R3B12 1KR3B12 1K R3B11 1KR3B11 1K

USB_PN022 USB_PP022

USB_PN122 USB_PP122

USB_PN322 USB_PP322

R3B10 1KR3B10 1K R3B8 1KR3B8 1K

EN1_B EN2_B

D D

C C

+V5A_USBPWR_IN3

EN1_A EN2_A

U3N1

1

GND

2

IN

3

EN1 EN24OC2#

TPS2052B

L3A2

1 4 2 3

90@100MHz

L3A1

1 4 2 3

90@100MHz

L3A3

1 4 2 3

90@100MHz

U3N2

1

GND

2

IN

3

EN1 EN24OC2#

TPS2052B

OC1# OUT1 OUT2

4

27

RP3B1B

RP3B1B 10K

10K

+V5A_USBPWR_PN0 +V5A_USBPWR_PN1

U3A3

B1

ESD_CH2

A1

V-

CM1230_02

U3A1

B1

ESD_CH2

A1

V-

CM1230_02

U3A2

B1

ESD_CH2

A1

V-

CM1230_02

FB3N3

50OHM

USB_OC#0 22

FB3N1 50OHMFB3N1 50OHM FB3N2 50OHMFB3N2 50OHM

USB_OC#1 22

USBAUSBA+

ESD_CH1

V+

ESD_CH1

V+

USBCUSBC+

ESD_CH1

V+

USB_OC#3 22

+V5A_L_USBPWR_PN3

12

+

C3A3

C3A3 220uF

220uF

10%

+V3.3A19,21,23..28,33,34,39..42,44..48,50..52,55..57

A2 B2

+V3.3A19,21,23..28,33,34,39..42,44..48,50..52,55..57

A2 B2

+V3.3A19,21,23..28,33,34,39..42,44..48,50..52,55..57

A2 B2

+V5A_L_USBPWR_PN0 +V5A_L_USBPWR_PN1

12

C3A1

C3A2

+

220uF

10%

C3M2

C3M2 470PF

470PF

C3M1

C3M1 470PF

470PF

USBBUSBB+

Place ESD diodes as close to the connector as possible.

C3M3

C3M3 470PF

470PF

1 2 3 4

5 6 7 8

9 10 11 12

Triple USB Connector

J3A1

VCC1 P#0 P0 GND1

VCC2 P#1 P1 GND2

VCC3 P#2 P2 GND3

3_stack_USB

3

MIDDLE

MIDDLE PORT

PORT

BOTTOM

BOTTOM PORT

PORT

TOP

TOP PORT

PORT

GND4 GND5 GND6 GND7

+V5A 24,40,42,47,48,51,55,57

R5W9

0.002

1%

R5W12 1KR5W12 1K R5W13 1KR5W13 1K

C5W10

0.1uF

13

10%

14 15 16

+V5A 24,40,42,47,48,51,55,57

R7H7

0.002

1%

R6W5 1KR6W5 1K R6W6 1KR6W6 1K

C7H4

0.1uF

10%

2

1

Header-1: FPIO - Port 2, 4

+V5A_L_USBPWR_PN2_PN4

J6H4

1

2

USB_PN422 USB_PP422

+V5A_USBPWR_IN1 +V5A_USBPWR_PN2_PN4 +V5A_L_USBPWR_PN2_PN4

EN1_C EN2_C

3 4 5 7108

USB_2X5-Header

Header-1

U5H3

1

GND

2

IN

3

EN1 EN24OC2#

TPS2052B

6

OC1# OUT1 OUT2

USB_PN2 22 USB_PP2 22

+V3.3A 19,21,23..28,33,34,39..42,44..48,50..52,55..57

18

27

RP5W1A

RP5W1B

10K

8 7 6 5

USB_OC#2 22

USB_OC#4 22

FB6H2

50OHM

12

C6H3

+

220uF

10%

Header-2: FPIO - Port 6, 8

+V5A_L_USBPWR_PN6_PN8

J6H3

1

2

+V5A_USBPWR_IN2

EN1_D EN2_D

USB_PN822 USB_PP822

3 4 5 7108

USB_2X5-Header

Header-2

U6H3

1

GND

2

IN

3

EN1 EN24OC2#

TPS2052B

OC1# OUT1 OUT2

USB_PN7 22

6

USB_PP7 22

+V3.3A 19,21,23..28,33,34,39..42,44..48,50..52,55..57

45

36

RP5W1D

RP5W1C

10K

USB_OC#7 22

FB6H1

8 7 6 5

+V5A_USBPWR_PN6_PN8 +V5A_L_USBPWR_PN6_PN8

USB_OC#8 22

FB6H1

50OHM

12

C6H1

+

220uF

10%

C6H4

C6H4 470PF

470PF

C6H2

C6H2 470PF

470PF

B B

+V3.3A19,21,23..28,33,34,39..42,44..48,50..52,55..57

R4A3

R4A2

10K

5%

U4A2

1

+V5A_USBPWR_IN3

C4M4

0.1uF

20%

R4M6 1KR4M6 1K R4M5 1KR4M5 1K

USB_PN522 USB_PP522

A A

USB_PN622 USB_PP622

GND

2

IN

EN1_E +V5A_USBPWR_PN7

3

EN1

EN2_E

EN24OC2#

TPS2052B

L5B1

1 4 2 3

90@100MHz

L5B2

1 4 2 3

90@100MHz

OC1# OUT1 OUT2

8 7 6 5

U5A2

B1

ESD_CH2

A1

V-

CM1230_02

U5A3

B1

ESD_CH2

A1

V-

CM1230_02

5

USB_OC#5 22

+V5A_USBPWR_PN5

USB_OC#6 22

A2

ESD_CH1

B2

V+

A2

ESD_CH1

B2

V+

4

FB4M1

+V5A_L_USBPWR_PN5

12

50OHM

C4A3

+

220uF

10%

FB4M2

+V5A_L_USBPWR_PN7

12

50OHM

+V3.3A19,21,23..28,33,34,39..42,44..48,50..52,55..57

+

C4A6

C4A6 220uF

220uF

10%

4 5

RP3B1D

10K

C4M6

C4M6 470PF

470PF

C4M3

C4M3 470PF

470PF

USBDUSBD+

USBE-

USBE+

Spare

RJ45 1000 with Dual USB Connector

J5A1B

1

VCC1

2

P0#

3

P0

4

GND1

5

VCC2

6

P1#

7

P1

8

GND2

RJ45 1000 WITH DUAL USB

3

LAYOUT NOTE FOR ESD DIODE: CM1230

Need to have minimum of 150mil clearance step down stencil definition around the ESD diodes CM1230 in layout too. Step down stencil area can accomodate other components. If needed, area for step down stencil definition can even be extended to cover other nearby components to avoid step down area covering the components half way, meaning, if extended step down area should cover other nearby coponents fullly.

USB Port Routing Locations

USB Port Location

USB Port 0 USB Port 1 USB Port 2 USB Port 3 USB Port 4 USB Port 5 USB Port 6 USB Port 7 USB Port 8 USB Port 9

Back of Chassis Back of Chassis FPIO/Duckbay Back of Chassis FPIO/Duckbay Back of Chassis FPIO/Duckbay Back of Chassis FPIO/DuckBay Docking

Matanzas

Title

Size Document Number Rev

Date: Sheet

USB 1.1/2.0

NDA

USB FPIO Header to PCIe connector mapping USB Header USB Port PCIESlot

Header-1 Port 2 & Port 4 Slot 1 & Slot 2 Header-2 Port 6 & Port 8 Slot 3 & Slot 4

2

Intel Confidential

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4

3

2

1

SATA Port-0,Direct Connect

D D

+V3.3S5,7,10,12,16..26,28,31,32,34,37..42,44,45,49,50,52,55..57

+V5S5,11,12,16..18,24,31,32,34,41,49,50,52,53,55..57

R8J1

R8J1 100K

100K

R8H51MR8H5 1M

3

Q8H4

Q8H4 BSS138

BSS138

1

2

R8H41MR8H4 1M

C9Y1

C9Y1 1000pF

1000pF

10%

SATA_3.3V_EN0_3SATA_3.3V_EN0_2

C C

R8W101MR8W10

C8W3

1M

1000pF

147

U5J1F

SATA_PWR_EN#0_5V

3

Q8J1

Q8J1 BSS138

BSS138

R8J2

R8J2 10K

10K

1%

1

2

SATA_PWR_EN#023

B B

13 12

SATA_5V_EN0_1

74HC14

SATA_PWR_EN#0_5V

1000pF

10%

SATA_5V_EN0_2

R8W91MR8W9 1M

4

5 6

3

Q9H1

Q9H1 2N7002

2N7002

1

2

+V5S5,11,12,16..18,24,31,32,34,41,49,50,52,53,55..57

3

Q8H6B

Q8H6B SI4925DY

SI4925DY

+V12S25,26,31..33,44,56,57

R9H151MR9H15 1M

R8H3 1MR8H3 1M

Q9Y1

Q9Y1 SI3433DV

SI3433DV

SATA_3.3V_EN0_4

3

7 8

1

Q8H6A

Q8H6A SI4925DY

SI4925DY

SATA_12V_EN0_2SATA_12V_EN0_1

6 5 2 1

SATA_5V_EN0_3

4

2

C9H3

C9H3 1000pF

1000pF

10%

R8Y2 0.002

R8H6 0.002

1

+V3.3S_SATA_P0

1%

Q9H3

SI2307DS

3 2

SATA_12V_EN0_3 +V12S_SATA_P0

C8J2

C8J2 22uF

22uF

+V5S_SATA_P0

12

+

C8J1

C8J1 100uF

100uF

C8J3

0.1uF

10%

.

SATA_TXP021 SATA_TXN021

SATA_RXN021 SATA_RXP021

NO_STUFF

C8Y2

C8Y2 22uF

22uF

R8W11 0.002

R8J3 4.3R8J3 4.3 R8Y3 1R8Y3 1

TP_SATA_RESEV

TP9H1

C8J4

0.1uF

10%

.

1%

C8J5

0.1uF

10%

.

+

C9J1

C9J1 15uF

15uF

20%

R9Y1

5.1

V_3.3_3_PC V_5.0_7_PC

V_12_13_PC

C9J2

0.1uF

20%

SATA Port 0, Direct Connect

J8J1

2

TX

3

TX#

5

RX#

6

RX

8

V_3.3_1

9

V_3.3_2

10

V_3.3_3_PC

14

V_5.0_7_PC

15

V_5.0_8

16

V_5.0_9

18

P_RESERVE_11

20

V_12_13_PC

21

V_12_14

22

V_12_15

Serial ATA Recepticle

C9J3

0.1uF

20%

GND_2M_S_1 GND_2M_S_4 GND_2M_S_7

GND_1M_P_4 GND_2M_P_5 GND_2M_P_6

GND_2M_P_10

GND_1M_P_12

Layout Note: Place this connector on the edge of CRB

1 4 7

11 12 13

17

19

+V12S is only for desktop type SATA devices

A A

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4

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NDA

2

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2

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SATA Port-1 and Port-2, Cable Connect

SATA Power Connector

Q7H1A

D D

+V5S5,11,12,16..18,24,30,32,34,41,49,50,52,53,55..57

R7J1

R7J1 100K

3

1

2

SATA_PWR_EN#1_5V

100K

SATA_PWR_EN#1_5V

Q7H2

Q7H2 BSS138

BSS138

SATA_PWR_EN#1_5V

C5Y2

0.1uF

10%

.

+V12S25,26,30,32,33,44,56,57

R8W81MR8W8 1M

SATA_12V_EN1_1

3

1

2

11 10

Q8H5

Q8H5 2N7002

2N7002

+V3.3S5,7,10,12,16..26,28,30,32,34,37..42,44,45,49,50,52,55..57

R9H11

R9H11 43K

43K

SATA_DET#123,42

Hot plug implemented on Port 1 only

SATA Device Status J9H5

Presence Shunt (Default)

C C

Removed No Shunt

This jumper simulates the drive status. For proper function of the hot plug, this jumper must be "No Shunt" when drive is removed and "Shunt" after the drive is plugged in.

SATA_PWR_EN#123

SATA Port-2 SATA Port-1 Jumper (J7J2)

Device not connected thru cable

Device connected thru cable

Hot plug/removal supported

Power to device

cant be turned off

Shunt (Default)

No Shunt

J9H5J9H5

1 2

J7J2J7J2

SATA_PWR_EN#1_J

12

R7W8

R7W8 10K

10K

1%

B B

147

1

U5J1E

74HC14

+V3.3S5,7,10,12,16..26,28,30,32,34,37..42,44,45,49,50,52,55..57

R7W71MR7W7 1M

3

2

SATA_12V_EN1_2

R8W71MR8W7 1M

SATA_3.3V_EN1_1

Q7H3

Q7H3 BSS138

BSS138

R8W121MR8W12 1M

SATA_5V_EN1_1

R7W61MR7W6 1M

C8W2

C8W2 1000pF

1000pF

10%

4

C7W2

C7W2 1000pF

1000pF

10%

SATA_3.3V_EN1_2

R8Y11MR8Y1 1M

1238

Q8H3

Q8H3 SI4835BDY

SI4835BDY

765

SATA_12V_EN1_3

C8Y1

C8Y1 1000pF

1000pF

10%

SATA_5V_EN1_2

1

3

Q7H1A

SI4965DY

2

Q7H1B

SI4965DY

4

R8H2 0.002

+V5S5,11,12,16..18,24,30,32,34,41,49,50,52,53,55..57

4

8 7

6 5

SATA_3.3V_EN1_3

1238

Q8H7

Q8H7 SI4835BDY

SI4835BDY

765

1%

+

C8H1

C8H1 15uF

15uF

20%

C7H1

0.1uF

20%

R7H9 0.002

1%

R8H7 0.002

C7H2

0.1uF

20%

C7H8

0.1uF

C7H6

C7H6 22uF

22uF

10%

.

J7H2

C7H5

0.1uF

10%

.

J7H2

1

V_3.3_1

2 3

4 5

GND_1

V_3.3_2

GND_2

V_5_1

GND_3

V_5_2

GND_4

V_12_1

GND_5

SATA_POWER_CONNECTOR

6 7

8 9

10

+V3.3S_SATA_P1

1%

+V5S_SATA_P1SATA_5V_EN1_3

12

+

C8H3

C8H3 100uF

100uF

C8H4

C8H4 22uF

22uF

+V12S_SATA_P1

C7H3

0.1uF

10%

10% .

.

SATA Signal Connectors

SATA Port-1

J7J3

SATA_TXP121 SATA_TXN121

SATA_RXN121 SATA_RXP121

2 3

5 6

SATA_Signal_Plug

1

TX

GND1

4

TX#

GND4

7

RX#

GND7

RX

SATA_TXP221 SATA_TXN221

SATA_RXN221 SATA_RXP221

A A

Notes:

-- Both SATA Port-1 and SATA Port-2 share the same power connector, J7H2

-- Use Y-Cable available with Kit to feed the power from J7H2 to SATA device on port-1 and SATA device on Port-2.

-- Connect Power cable first before connecting SATA signal cable.

5

4

SATA Port-2

J7H1

2

TX

3

TX#

5

RX#

6

RX

SATA_Signal_Plug

GND1 GND4

GND7

1 4

7

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SATA (2 and 3 of 3)

NDA

2

Intel Confidential

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1

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5

4

3

2

1

D D

+V5S_PATA

R4Y4

R4Y4 100K

100K

PATA_PWR_EN_2#

R4Y31MR4Y3 1M

PATA_PWR_EN#

1

C3J2

0.1uF

20%

3

2

1 2

Q3J3

Q3J3 BSS138

BSS138

147

U5J1A

74HC14

+V5S5,11,12,16..18,24,30,31,34,41,49,50,52,53,55..57

147

U5J1B

3 4

74HC14

IDE_D_PRST# IDE_D_PRST#_R

R7J2 47R7J2 47

+V3.3S5,7,10,12,16..26,28,30,31,34,37..42,44,45,49,50,52,55..57

IDE_D_PRST#_R IDE_PDD7 IDE_PDD6

IDE_PDD4

R6H9

R7V2

4.7K

8.2K

IDE_PDDREQ21

IDE_PDIOW#21

IDE_PDIORDY21 INT_IRQ1421

IDE_PDIOR#21 IDE_PDDACK#21 IDE_PDA121

IDE_PDA021 IDE_PDCS1#21

IDE_PDACTIVE#21

IDE_PDD2 IDE_PDD1PATA_PWR_EN_2 IDE_PDD0

7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

20x2-HDR

J7J4

21

IDE_PDD8

43

IDE_PDD9

685

IDE_PDD10IDE_PDD5 IDE_PDD11

10

IDE_PDD12IDE_PDD3

12

IDE_PDD13

14

IDE_PDD14

16

IDE_PDD15

18 22

24 26

IDE_PD_CSEL

28 30 32 34 36 38 40

IDE_PDCS3#21 IDE_PDA221

R6J2 470R6J2 470

IDE_PDD[15:0] 21IDE_PDD[15:0]21

R6J3

R6J3 10K

10K

IDE_PATADET 23,44

C C

+V12S25,26,30,31,33,44,56,57

+V5S5,11,12,16..18,24,30,31,34,41,49,50,52,53,55..57

R5Y2

R5Y2 100K

100K

PATA_PWR_EN_1#

C5Y1

0.1uF

10%

.

B B

PATA_PWR_EN#23,44

R3Y1

R3Y1 10K

10K

1

PATA_PWR_EN_1#

3

Q3J1

Q3J1 BSS138

BSS138

2

5 6

147

1

U5J1C

74HC14

PATA_12V_EN_1

3

2

R3J2 1MR3J2 1M

Q3Y2

Q3Y2 BSS138

BSS138

R5Y41MR5Y4 1M

PATA_5V_EN_1 PATA_5V_EN_2

R5Y51MR5Y5 1M

R3Y41MR3Y4 1M

PATA_12V_EN_2

C3Y2

C3Y2 1000pF

1000pF

10%

4

C5Y3

C5Y3 1000pF

1000pF

10%

.

5 6

3

Q3J2

Q3J2 SI3433DV

SI3433DV

C4J5

C4J5 22uF

22uF

C4J2

0.1uF

20%

+V12S_PATA

C4J4

0.1uF

10%

10% .

.

J4J2

1 2 3 4

4Pin_HD_PWR-CON

C4J6

0.1uF

10%

.

12V

12V GND1

GND1 GND2

GND2 5V

5V

3

14256

+V5S5,11,12,16..18,24,30,31,34,41,49,50,52,53,55..57

Q5J2B

Q5J2B SI4925DY

SI4925DY

PATA_12VS_EN_3

2

7 8

1

Q5J2A

Q5J2A SI4925DY

SI4925DY

PATA_5V_EN_3

R3Y2 0.002

1%

R5Y6 0.002

+

C4J3

C4J1

0.1uF

15uF

20%

+V5S_PATA

1%

12

+

C5J1

C5J1 100uF

100uF

+V5S5,11,12,16..18,24,30,31,34,41,49,50,52,53,55..57

R5Y3

R5Y3 100K

100K

A A

5

74HC14_SP9

4

+V5S 5,11,12,16..18,24,30,31,34,41,49,50,52,53,55..57

147

U5J1D

9 8

74HC14

Spare 74HC14 Inverter

Intel Confidential

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Date: Sheet

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Date: Sheet

IDE

NDA

2

Intel Confidential

32 58Tuesday, December 05, 2006

1

1.5

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5

4

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2

1

+V3.319,27,41..44,49,56,57

+V3.3S_PCI34

R9D3 0.002

1%

D D

+V5S_PCI34

+V527,43..45,50,52,55..57

Note: To Power PCI Slot 3 in suspend, Stuff R8B3, R8C5, R8B5 and Unstuff R9B2 R9D3, R8B6

INT_PIRQD#22 INT_PIRQA#22

R9B2 0.002

1%

R8B3 0.002

1%

NO_STUFF

R8C5 0.002

NO_STUFF

C C

1%

C8B9 0.01uFC8B9 0.01uF

C8B14 0.01uFC8B14 0.01uF

CLK_PCI_PCISLOT338

PCI_REQ#222

INT_SERIRQ23,40,42,44

PCI_AD3122,34 PCI_AD2922,34

PCI_AD2722,34 PCI_AD2522,34

PCI_CBE#322,34 PCI_AD2322,34

PCI_AD2122,34 PCI_AD1922,34

PCI_AD1722,34 PCI_CBE#222,34

PCI_IRDY#22,34 PCI_DEVSEL#22,34 PCI_LOCK#22,34

PCI_PERR#22,34 PCI_SERR#22,34 PCI_CBE#122,34

PCI_AD1422,34 PCI_AD1222,34

PCI_AD1022,34

PCI_AD822,34 PCI_AD722,34

PCI_AD522,34 PCI_AD322,34

PCI_AD122,34 PCI_ACK64#22

B B

+V527,43..45,50,52,55..57

R9A11 0.002

NO_STUFF

+V12S25,26,30..32,44,56,57

R8B1 0.002

C8B1

C8B1 10uF

10uF

+V5_PCI34

1%

+V12S_PCI34

1%

C9B3

C8B5

0.1uF

20%

SLT3_PRSNT1# SLT3_PRSNT2#

+V3.3_PCISLT3

+V5_PCISLT3

+V5_PCI 34

-V12S34,57

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62

Place close to PCI Slot 3

C8B8

C8C1

22uF

0.1uF

20%

Place close to PCI Slot 3

C9D2

C8C5

22uF

-12V

TRST#

TCK

+12V

GND1

TMS TDO +5V (1)

+5V (7)

+5V (2)

INTA#

INTB#

INTC#

INTD#

+5V (8)

PRSNT1#

RSV3

RSV1

+5V (9)

PRSNT2#

RSV4

GND2

GND14

GND3

GND15

RSV2

3.3VAUX

GND4

RST#

CLK

+5V (10)

GND5

GNT#

REQ#

GND16

+5V (3)

PME#

AD31

AD30

AD29

+3.3V (7)

GND6

AD28

AD27

AD26

AD25

GND17

+3.3V (1)

AD24

C/BE3#

IDSEL

AD23

+3.3V (8)

GND8

AD22

AD21

AD20

AD19

GND18

+3.3V (2)

AD18

AD17

AD16

C/BE2#

+3.3V (9)

GND9

FRAME#

IRDY#

GND19

+3.3V (3)

TRDY#

DEVSEL#

GND20

GND10

STOP#

LOCK#

+3.3V (10)

PERR#

SMBCLK

+3.3V (4)

SMBDAT

SERR#

GND21

+3.3V (5)

PAR C/BE1#

AD15

AD14

+3.3V (11)

GND11

AD13

AD12

AD11

AD10

GND22

GND12

AD09

KEY

AD08

C/BE0#

AD07

+3.3V (12)

+3.3V (6)

AD06

AD05

AD04

AD03

GND23

GND13

AD02

AD01

AD00

+5V (4)

+5V (11)

ACK64#

REQ64#

+5V (5)

+5V (12)

+5V (6)

+5V (13)

J8B3 CON120_PCI

PCI SLOT3

C8C2

0.1uF

20%

C8C4

0.1uF

20%

TDI

C8E2

0.1uF

20%

C8D7

0.1uF

20%

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

+V12S_PCI34

+V3.3A 19,21,23..29,34,39..42,44..48,50..52,55..57

+V5_PCISLT3

+V3.3_PCISLT3

PM_CLKRUN# 23,34,40,42,44

R8B5 0

NO_STUFF

PCIRST#

R8B6 0R8B6 0

S3_PCI_GNT#2

PCI_PME# 22,34,44

PCI_AD30 22,34 PCI_AD28 22,34

PCI_AD26 22,34

C8C3

0.1uF

20%

PCI_AD24 22,34

R8C6 680R8C6 680

PCI_AD22 22,34 PCI_AD20 22,34

PCI_AD18 22,34 PCI_AD16 22,34

PCI_FRAME# 22,34 PCI_TRDY# 22,34 PCI_STOP# 22,34 SMB_CLK_A1 23,25,26,34,45

SMB_DATA_A1 23,25,26,34,45 PCI_PAR 22,34

PCI_AD15 22,34 PCI_AD13 22,34

PCI_AD11 22,34 PCI_AD9 22,34

PCI_CBE#0 22,34 PCI_AD6 22,34

PCI_AD4 22,34 PCI_AD2 22,34

PCI_AD0 22,34 PCI_REQ64# 22

C8D2

0.1uF

20%

SLT3_IDSEL

PCI Slots 1&2&4 are on the Extension Board.

C8B7

0.1uF

20%

C8C9

0.1uF

20%

PCI_AD18

INT_PIRQC# 22 INT_PIRQB# 22,34

PCI_GATED_RST# 42

PCI_RST# 22,34,42

+V3.3S_PCI34

R8C21KR8C2 1K

V3.3S_PCI_D

1

+V3.3_PCISLT3

3

Q8C1

Q8C1 2N3904

2N3904

2

R8C3

R8C3 10K

10K

PCI_GNT#2 22

-V12S34,57

A A

5

4

C9B1

C9B1 22uF

22uF

C9A3

0.1uF

20%

C8B3

0.1uF

20%

C9B2

0.1uF

20%

Note: Place one 0.1uF cap next to PCI Slot and the Goldfinger

3

Intel Confidential

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Date: Sheet

PCI Slot 3

NDA

2

Intel Confidential

33 58Tuesday, November 21, 2006

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5

4

3

2

1

D D

-V12S33,57

+V5_PCI33 +V12S_PCI33

+V5S_PCI33

+V3.3S_PCI33

PCI_REQ#022

INT_PIRQE#22 INT_PIRQF#22

PCI_REQ#122

PCI_GNT#122

CLK_PCI_PCIGOLDF38

C C

B B

PCI_REQ#322

PCI_AD3122,33 PCI_AD2922,33

PCI_AD2722,33 PCI_AD2522,33

PCI_CBE#322,33 PCI_AD2322,33

PCI_AD2122,33 PCI_AD1922,33

PCI_AD1722,33 PCI_CBE#222,33

PCI_IRDY#22,33 PCI_DEVSEL#22,33 PCI_LOCK#22,33

PCI_PERR#22,33 PCI_SERR#22,33 PCI_CBE#122,33

PCI_AD1422,33 PCI_AD1222,33

PCI_AD1022,33

PCI_AD822,33 PCI_AD722,33

PCI_AD522,33 PCI_AD322,33

PCI_AD122,33

S9B1

B1

-12V

B2

GND(TCK)

B3

GND1

B4

REQ#0(TDO)

B5

+5V_1

B6

+5V_2

B7

INTB#

B8

INTD#

B9

REQ#1(PRSNT1#)

B10

RSV1

B11

GNT#1(PRSNT2#)

B12

GND2

B13

GND3

B14

+3.3V(RSV2)

B15

GND4

B16

CLK

B17

GND5

B18

REQ#5(REQ#)

B19

+5V(+V_I/O1)

B20

AD31

B21

AD29

B22

GND6

B23

AD27

B24

AD25

B25

+3.3V_2

B26

C/BE3#

B27

AD23

B28

GND7

B29

AD21

B30

AD19

B31

+3.3V_3

B32

AD17

B33

C/BE2#

B34

GND8

B35

IRDY#

B36

+3.3V_4

B37

DEVSEL#

B38

GND9

B39

LOCK#

B40

PERR#

B41

+3.3V_5

B42

SERR#

B43

+3.3V_6

B44

C/BE1#

B45

AD14

B46

GND10

B47

AD12

B48

AD10

B49

GND11

B52

AD08

B53

AD07

B54

+3.3V_7

B55

AD05

B56

AD03

B57

GND12

B58

AD01

B59

+5V(+V_I/O2)

B60

+5V(ACK64#)

B61

+5V_3

B62

+5V_4

PCI_EXTENSION_GOLDFINGERS_5V

NO_STUFF

5V KEY

GND(TRST#)

INT#(TMS)

GNT#0(TDI)

+5V(+V_I/O3)

+5V(RSV4)

3.3VAUX

+5V(+V_I/O4)

GNT#5(GNT#)

+3.3V_11

+3.3V(IDSEL)

+3.3V_12

+3.3V_13

FRAME#

+3.3V_14

SMBCLK

SMBDAT

+3.3V_15

+3.3V_16

+5V(+V_I/O5) +5V(REQ64#)

+12V

+5V_5 INTA# INTC# +5V_6

RSV3

GND13 GND14

RST#

GND15

PME#

AD30 AD28

AD26

GND16

AD24

AD22 AD20

GND17

AD18 AD16

GND18

TRDY#

GND19

STOP#

GND20

AD15 AD13

AD11

GND21

AD09

C/BE0#

AD06 AD04

GND22

AD02 AD00

+5V (7) +5V (8)

PAR

PCI - EDGE CONNECTOR

(GOLDFINGER)

+V3.3A 19,21,23..29,33,39..42,44..48,50..52,55..57

+V5S_PCI 33

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

+V3.3S_PCI 33

INT_PIRQH# 22 PCI_GNT#0 22

INT_PIRQB# 22,33 INT_PIRQG# 22

PM_CLKRUN# 23,33,40,42,44

PM_SLP_S4#_R

PCI_RST# 22,33,42 PCI_GNT#3 22

PCI_PME# 22,33,44

PCI_AD30 22,33 PCI_AD28 22,33

PCI_AD26 22,33 PCI_AD24 22,33

PCI_AD22 22,33 PCI_AD20 22,33

PCI_AD18 22,33 PCI_AD16 22,33

PCI_FRAME# 22,33 PCI_TRDY# 22,33 PCI_STOP# 22,33 SMB_CLK_A1 23,25,26,33,45

SMB_DATA_A1 23,25,26,33,45 PCI_PAR 22,33

PCI_AD15 22,33 PCI_AD13 22,33

PCI_AD11 22,33 PCI_AD9 22,33

PCI_CBE#0 22,33 PCI_AD6 22,33

PCI_AD4 22,33 PCI_AD2 22,33

PCI_AD0 22,33

+V5S 5,11,12,16..18,24,30..32,41,49,50,52,53,55..57

R9N2 0R9N2 0 R9N3 0

R9N3 0

NO_STUFF

Default is to use pin A11 as a +V5S power pin (R9N2 stuffed)

Stuff R9N3 and unstuff R9N2 if using ATX power supply directly on extension board.

DO NOT STUFF BOTH R9N3 AND R9N2 AT THE SAME TIME

PM_S4_STATE# 23,42,44,45,56,57

+V5S5,11,12,16..18,24,30..32,41,49,50,52,53,55..57

Place close to PCI Edge Connector

R9B1

0.002

1%

C9C3

C9D7

0.1uF

22uF

20%

+V3.3S5,7,10,12,16..26,28,30..32,37..42,44,45,49,50,52,55..57

R9D2

0.002

1%

C9C4

C9D3

0.1uF

22uF

0.1uF

20%

Place close to PCI Edge Connector

C9C2

0.1uF

20%

C9D4

0.1uF

20%

+V5S_PCI33

C9E2

0.1uF

20%

+V3.3S_PCI33

C9C1

0.1uF

20%

A A

Intel Confidential

Matanzas

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

5

4

3

Date: Sheet

PCI Edge Connector (Goldfinger)

NDA

2

Intel Confidential

34 58Tuesday, November 21, 2006

1

1.5

of

Note: LAN controller symbol pin-out naming convention is (Intel® 82566 MM/MC LAN-Ekron-N). e.g. GLAN_TXP-NC

Place GLAN_CLK series resistor close to LAN Controller

U6A1

GLAN_CLK_R

GLAN_RXP_C GLAN_RXN_C

LAN_KMRN_RCOMP_P LAN_KMRN_RCOMP_N

LAN_ATEST_P LAN_ATEST_N

LAN_DISABLE#

5%

LAN_TEST_EN

LAN_RXD021 LAN_RXD121 LAN_RXD221

LAN_LED_100#36

NO_STUFF

C6A14 0.1uFC6A14 0.1uF

GLAN_TXP22 GLAN_TXN22

1%

LAN_MDI0P36 LAN_MDI0N36

LAN_MDI1P36 LAN_MDI1N36

LAN_MDI2P36 LAN_MDI2N36

LAN_MDI3P36 LAN_MDI3N36

R6A4

R6A4 0

0

LAN_RBIAS_P

R6A3 0

R6A5

R6A5 100

100

1%

R6A16 33R6A16 33

NO_STUFF

R6A20

R6A20 619

619

1%

GLAN_CLK21

GLAN_RXP22 GLAN_RXN22

R6A22 649

NO_STUFF

1%

LAN_LED_LNK#_ACT36

LAN_RSTSYNC21

LAN_TXD021 LAN_TXD121 LAN_TXD221

C6A12 0.1uFC6A12 0.1uF

R6A21 1.40K

LAN_LED_1000#36

D D

Add test points on LAN_TXD[2:0] and LAN_RXD[2:0]

Place C6A12 & C6A14 close to LAN Controller

Add test points on GLAN_TXP/N

NO_STUFF

C C

Place THE RComp resistor within 1" from LAN Controller

Layout Note: Keep this resistor on top side

CAD Note: Connect resistor to GND near ball E6

R6A11 1.40K

PM_LAN_ENABLE23,42,44

1%

U6A1

E2

JKCLK-JCLK

E3

JRSTSYNC

D1

JTXD0

F3

JTXD1

F1

JTXD2

D3

JRXD0

D2

JRXD1

C1

JRXD2

H2

GLAN_TXP-NC

J2

GLAN_TXN-NC

J4

GLAN_RXP-NC

H4

GLAN_RXN-NC

G7

KBIAS_P-RBIAS100

H7

KBIAS_N-RBIAS10

A4

LED0-LINK_UP_N

B4

LED1-ACT_LED_N

A5

LED2-SPEED_LED_N

B8

MDI_PLUS[0]-TDP

B9

MDI_MINUS[0]-TDN

D9

MDI_PLUS[1]-RDP

D8

MDI_MINUS[1]-RDN

F9

MDI_PLUS[2]-NC

F8

MDI_MINUS[2]-NC

H8

MDI_PLUS[3]-NC

H9

MDI_MINUS[3]-NC

A7

IEEE_TEST_P-NC

B7

IEEE_TEST_N-NC

J6

RSVD_J6-NC

J7

RSVD_J7-NC

E7

RBIAS_P-NC

E6

RBIAS_N-NC

B5

RSVD_B5-NC

A6

RSVD_A6-ADV10/LAN_DIS_N

C5

RSVD_C5-NC

B6

TEST_EN

NINEVEH-EKRON_N (REV 1p0)

B B

5

4

LCI

GLCI

MDI

R6A14

R6A14 200

200

5%

5% NO_STUFF

NO_STUFF

TP7A2

TP7A1

H6

XTAL2-X2H5XTAL1-X1

JTAG

JTAG_TCK-ISOL_TCKG1JTAG_TDI-ISOL_TIH1JTAG_TDO-TOUTG3JTAG_TMS-ISOL_EXEC

LAN_JTAG_TCK

LAN_JTAG_TDI

LAN_XTAL2 LAN_XTAL1

G2

LAN_JTAG_TDO

LAN_JTAG_TMS

TP7A3

VSSA[17]-NC VSSA[16]-NC

VSSA[15]-VSSA2

VSSA[14]-VSS

VSSA[13]-NC VSSA[12]-VSS VSSA[11]-VSS VSSA[10]-VSS VSSA[09]-VSS VSSA[08]-VSS VSSA[07]-VSS VSSA[06]-VSS VSSA[05]-VSS VSSA[04]-VSS

VSSA[03]-VSSR

VSSA[02]-NC VSSA[01]-VSS

VSS[04]-VSS VSS[03]-VSSP

VSS[02]-VSS

VSS[01]-NC

VDD1P0[03]-VCCA

VDD1P0[02]-VCCT

VDD1P0[01]-VCCR

VCCF1P0-VCC

VCCFC1P0-VCC

VCC3P3[02]-VCCP

VCC3P3[01]-VCC

VCC1P8[04]-NC VCC1P8[03]-NC VCC1P8[02]-NC VCC1P8[01]-NC

VCC1P0-VCCA2

V1P0_OUT-NC

CTRL_10-NC

CTRL_18-NC

THERM_D_P-NC THERM_D_N-NC

+V3.3M_LAN+V3.3M_LAN

R6A12

R6A12 200

200

5%

5% NO_STUFF

NO_STUFF

TP6A1

41

VCC[02] VCC[01]

Y6B1

Y6B1 25MHZ

25MHZ

C6A16

C6A16 27pF

27pF

5%

5% .

.

C6A15

C6A15 27pF

27pF

5%

5% .

.

J9 J8 J5 J3 J1 G9 G8 G6 F6 E9 D6 C9 C8 C7 C6 A9 A8 F4 E1 C4 A1

F7 E8 D7

E5

H3 F2

B3

G5 F5 D5 C2

G4 E4

D4 B1

C3 B2

A2 A3

3

Place crystal less than

0.75 (~1.9 cm) inches from LAN Controller

R6M3

+V1.0_LAN_M_IN

+V3.3M_LAN

+V1.0_LAN_M_IN

V1P0_OUT

CTRL_10

CTRL_18

LAN_THERM_D_P LAN_THERM_D_N

R6M3

1 2

0.002

+V1.8_LAN_M36

Layout Note: Keep this resistor on top side

+V3.3M_LAN_SW36 +V3.3M_LAN +V1.8_LAN_M36+V1.8_LAN

R6A23

1 2

0.002

+V1.0_LAN_M

+V3.3M_LAN

R6A19

R6A19 0

0

NO_STUFF

Ekron-Mode supply, Place resistor close to ball D7

C6A3

R6A20R6A2 0

NO_STUFF

R6A1

R6A1 0

0

C6A3

4.7uF

10%

Place atleast 1.3cm X

1.3cm mounting PAD for collector (pin 4 of Q7A2)

C6A7

0.1uF

10%

.

2

LAN_PHYPC22,23

R6M1

1 2

0.002

+V3.3M13..15,23,24,36,42,44,50,56,57

1

C8A4

NO_STUFF

10%

0.01uF

402 25V

CTRL_18

402 25V

Place C6M2 close to PNP Collector (pin4)

NO_STUFF

CTRL_10

LAN_PHYPC_EN#

3

2

+V3.3M_LAN

1

+V1.8_LAN

C6M2

C6M2 10uF

10uF

20%

C7A1

0.01uF

402 25V

R6M41MR6M4 1M

R6A10 100K

Q6A1

Q6A1 BSS138

BSS138

3

Q7A1

Q7A1 BCP69

BCP69

2 4

10%

1

5%

C7M2

0.1uF

10%

.

+V3.3M_LAN

3

Q7A2

Q7A2 BCP69

BCP69

2 4

C7M7

0.1uF

10%

.

C6A1

C6A1 10uF

10uF

80%

+V1.0_LAN_M

C6M7

C6M7 1000pF

1000pF

10%

LAN_EDC_3.3EN#

C7M1

4.7uF

10%

+V1.8_LAN

1

Q6A2

Place C7M1 & C7M2 close to pin3

Place atleast 1.3cm X

1.3cm mounting PAD for collector (pin 4 of Q7A1)

C6M1

0.1uF

10%

.

C7M5

4.7uF

10%

+V3.3M_LAN_SW36

SI2307DS

32

C6A8

C6A8 22uF

22uF

1

.

C6M5

C6A2

C6A2 470PF

470PF

0.1uF

10%

.

Place C6A1, C6M1, C6M5, C6A2, C6A4 close to LAN Controller (U6A1)

Place C7M5 & C7M7 close to pin3

+V1.8_LAN_M

C6A4

C6A4 470PF

470PF

NO_STUFF

Stuff:

A A

R6A21, R6A11, R6M1, R6M3, R5N9, R5B4, R5N11, R9D1, R6A2, R5M1, R5B1 C7M1, C7M2, C6A1, C6M1, C6M2, C7M5, C7M7, C6M8, C6A5, C6A6, C5A1, C9D1, C6A12, C6A14, C5N3, C9R1, C6M5, C6A2, C6A4, C6A9, C6A11 Q7A1, Q7A2

NO stuff :

R6A22, R6A20, R6A3, R6A14, R6A12, R6A19, R5N8, R5B6, R5B3, R5B5

Others :

R6A6, R6A7, R6A9, R6A8, R6A13, R6A15, R6A18, R6A17 = 49.9 ohm 1% C6A5, C6A6 = 0.1uF 10% J5A1 - 10/100/1000Mbps Integrated Magnetics RJ45-USB combo module U6A1 - Intel® 82566 MM/MC LAN

5

Intel® 82566 MM/MC LAN Ekron-N

Stuff:

R6A22, R6A20, R6A3, R6A14, R6A12, R6A19, R5N8, R5B6, R5B3, R5B5

NO stuff :

R6A21, R6A11, R6A13, R6A15, R6A17, R6A18, R6M1, R6M3, R5N9,

R5B4, R5N11, R9D1, R6A2, R5M1, R5B1

C7M1, C7M2, C6A1, C6M1, C6M2, C7M5, C7M7, C6M8, C6A5, C6A6, C5A1,

C9D1, C6A12, C6A14, C5N3, C9R1, C6M5, C6A2, C6A4, C6A9, C6A11

Q7A1, Q7A2

Others :

R6A6, R6A7, R6A9, R6A8 = 54.9 ohm 1%

J5A1 - 10/100Mbps Integrated Magnetics RJ45 - USB combo module

(Pin compatible with Existing part)

U6A1 - Ekron-N

4

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

3

Date: Sheet

Place C6M8 close to PNP Collector (pin4)

Intel® 82566 MM/MC LAN & Ekron-N Option

NDA

2

+V1.0_LAN_M

C6M8

C6M8 10uF

10uF

20%

C6A10

C6A10 10uF

10uF

80%

+V1.0_LAN_M_IN

C6M6

C6M3

0.1uF

10%

.

Place C6A10, C6M3, C6M6, C6A13, C6M4 close to LAN Controller (UU6A1)

Intel Confidential

35 58Thursday, November 30, 2006

of

1

C6A13

C6A13 470PF

470PF

C6M4

C6M4 470PF

470PF

1.5

5

+V3.3M13..15,23,24,35,42,44,50,56,57

EU5A1

LAN_DOCK_EN#_R

LAN_MDI0P35

D D

LAN_MDI0N35 LAN_MDI1P35 LAN_MDI1N35 LAN_MDI2P35 LAN_MDI2N35 LAN_MDI3P35 LAN_MDI3N35

LAN_LED_LNK#_ACT35

LAN_LED_1000#35 LAN_LED_100#35

CAD Note: This is thermal PAD of IC (at bottom) and to be shorted to GND

EU5A1

17

SEL

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

19

LED0

20

LED1

54

LED2

57

THRM

56

VDD438VDD327VDD218VDD110VDD0

VDD550VDD6

PI3L500 LAN Switch

GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13

+V3.3M13..15,23,24,35,42,44,50,56,57

4

5

NC

55

0LED1 1LED1 2LED1

0LED2 1LED2 2LED2

0B1 1B1 2B1 3B1 4B1 5B1 6B1 7B1

0B2 1B2 2B2 3B2 4B2 5B2 6B2 7B2

48 47 43 42 37 36 32 31

LED_LNK#_Q_DOCK

22

LED_1000#_Q_DOCK

23

LED_100#_Q_DOCK

52

46 45 41 40 35 34 30 29

LAN_LED_LNK#_ACT_Q

25

LAN_LED_1000#_Q

26

LAN_LED_100#_Q

51

LAN_MDI0P_Q_DOCK 45 LAN_MDI0N_Q_DOCK 45 LAN_MDI1P_Q_DOCK 45 LAN_MDI1N_Q_DOCK 45 LAN_MDI2P_Q_DOCK 45 LAN_MDI2N_Q_DOCK 45 LAN_MDI3P_Q_DOCK 45 LAN_MDI3N_Q_DOCK 45

R5N10 0R5N10 0 R5B4 0R5B4 0 R5A1 0R5A1 0

LAN_MDI0P_Q LAN_MDI0N_Q LAN_MDI1P_Q

LAN_MDI1N_Q LAN_MDI2P_Q LAN_MDI2N_Q LAN_MDI3P_Q LAN_MDI3N_Q

+V3.3M_LAN_SW35

3

+V3.3M_LAN_SW35

0

0 R5N8

R5N8

NO_STUFF

LAN_LED_LINK#_DOCK 45 LAN_LED_1000#_DOCK 45 LAN_LED_100#_DOCK 45

LAN_LED_100#_Q LAN_LED_1000#_Q

R5B6 0

NO_STUFF

R5N9 0R5N9 0

R5N12 0R5N12 0 R5M1 0R5M1 0 R5A2 0R5A2 0 R5N11 0R5N11 0

+V1.8_LAN_M35

R5B10R5B1 0

LAN_RJ45_VCT

LED_LINK#_CONLAN_LED_LNK#_ACT_Q LED_ACT_CON LED_100#_CON LED_1000#_CON

+V1.8_LAN_M35

R9D1 0R9D1 0

LAN_LED_ACT#_DOCK 45

C5N3

0.01uF

10%

10% 402

402

Place C5A1 & C5N3 close

C5A1

to RJ45

0.01uF

10%

10% 402

402

J5A1A

9

VCC0

10

0+

11

0-

12

1+

13

1-

14

2+

15

2-

16

3+

17

3-

19

LED_LINK#

20

LED_ACT

21

LED_100#

22

LED_1000#

18

GND0

RJ45 1000 WITH DUAL USB

2

C9R1

0.01uF

10%

402

+V1.8_VCT_LAN_DOCK45

C9D1

0.01uF

10%

10% 402

402

Place C9R1 & C9D1 close to docking connector

LAN_MDI3N LAN_MDI3P

LAN_MDI2N LAN_MDI2P LAN_MDI1N LAN_MDI1P

LAN_MDI0N LAN_MDI0P

If 10/100BASE-T RJ-45 (Integrated magnetics) connector part used with Ekron-N

R6A6, R6A7, RR6A9, R6A8 = 54.9 ohm 1% R6A13, R6A15, R6A18, R6A17 = NO STUFF C6A5, C6A6, C6A9, C6A11 = NO STUFF

R6A7

R6A6

49.9

1%

C6A5

0.1uF

10%

.

R6A7

49.9

1%

R6A8

R6A9

49.9

1%

LANMDI1_R

C6A6

0.1uF

10%

.

CAD Note: Place termination resistors and caps near to Lan controller (less than 0.25")

1

R6A17

R6A18

49.9

1%

LANMDI3_R

C6A11

0.1uF

10%

10% .

.

R6A17

49.9

1%

LANMDI2_RLANMDI0_R

R6A13

49.9

1%

C6A9

0.1uF

10%

10% .

.

R6A15

49.9

1%

C C

+V3.3M13..15,23,24,35,42,44,50,56,57

R6B1

R6B1 10K

10K

5%

R5N4

R5N4 1K

1K

5%

NO_STUFF

LAN_DOCK_EN#_R

LAN_MDI0P_Q LAN_MDI0N_Q LAN_MDI1P_Q LAN_MDI1N_Q

DOCK_LAN_EN#23,45

R5B2 0R5B2 0

C5M3

C5M1

0.1uF

10%

.

U5M1

1

I/O1

2

I/O2

3

I/O3

4

I/O4

B B

ESD DIODE ARRAY

C5M2

0.1uF

10%

.

C5N5

0.1uF

10%

.

8

VP

LAN_MDI2P_Q

10

I/O8

LAN_MDI2N_Q

9

I/O7

LAN_MDI3P_Q

7

I/O6

LAN_MDI3N_Q

6

I/O5

VN

5

R5B3 0

R5B3 0 R5B5 0

R5B5 0

EKRON-N Resistor Strapping

SPI Interface

+V3.3M13..15,23,24,35,42,44,50,56,57 +V3.3M_SPI

R6D8

1 2

0.002

0.002 R6R5

R6R5

SPI1_WP# SPI_CS#1_CLK SPI_CS#0_CLK

3.3K

R6R2

LAYOUT NOTE:

Place SPI flash U7E1(SOIC-8) and UU6E1(SOIC-16) as shown below. At a time single package can be stuffed.

U6E1

1

HOLD#

VCC

A A

2

NC

3

NC

4

NC

NC NC

CS#

DO WP#

U7E1

5

1234

6 7 89

CLK

16

DI

15

NC

14

NC

5678

13

NC

12 11

VSS

10

SPI_CS#0 SPI_CS#0_SI_R SPI0_WP# SPI0_HOLD# +V3.3M_SPI

5

U6E1

7

CS#

15

DI

9

WP#

1

HOLD#

2

VCC

3

NC1

4

NC2

5

NC3

6

NC4

32Mb SPI FLASH

4

CLK

NC5 NC6 NC7 NC8

GND

NO_STUFF

DO

SPI_CS#0_CLK

16

SPI_CS#0_SO_R

8

11 12 13 14

10

SPI1_HOLD#

3.3K

U6D2

8

VDD

3

WP#

7

HOLD#

SST SPI FLASH

+V3.3M_SPI +V3.3M_SPI

C6R2

0.1uF

10%

.

NO_STUFF

NO_STUFF NO_STUFF

NO_STUFF

CE# SCK

VSS

3

SI

SO

C6R1

0.1uF

10%

.

LAN_LED_ACT#_DOCKLED_1000#_Q_DOCK

LED_ACT_CONLAN_LED_1000#_Q

LAN_MDI0P

LAN_MDI0P_Q

LAN_MDI1P

LAN_MDI1P_Q

SPI_CS#1_SI_R

5

SPI_CS#1_SO_R

2 1 6

4

0.01uF

10%

25V

.

NO_STUFF

C5N2

C5A2

.

C5A2

.

0.01uF

402

0.01uF

402 10%

25V

10%

25V

NO_STUFF

C5N1

Keep the caps very close to the MDI lines

C6T4

0.1uF

10%

.

ACTIVITY LED Green = LINK UP BLINKING = TX/RX ACTIVITY

SPEED LED Off = Link 10 Mbps Green = Link 100 Mbps

+V3.3M13..15,23,24,35,42,44,50,56,57

52

U5A4

LMV331M5X

R6T4 47R6T4 47 R7T2 15 1%R7T2 15 1%

Orange = Link 1000 Mbps

C5N4

0.1uF

20%

R5N5

1.5K

1%

4

R7U20 15

SPI_CS#0 22SPI_CS#1 22

R6T347R6T3 47

36 58Tuesday, December 05, 2006

1

Intel Confidential

of

LAN Energy Detect

402

C5A3

ED_MDI0P_R

0.01uF

ED_MDI1P_R

0.01uF

R6R6 47R6R6 47

C6T2

0.1uF

10%

.

R5N3 10KR5N3 10K

ED_ACT

R5N1 10KR5N1 10K

R5N6

100K

SPI_SI_R

+V3.3M_SPI

R7T3

R6R3

R6T1

15

1%

SPI_SO_R

Matanzas

Title

Size Document Number Rev

Date: Sheet

LAN Docking and SPI

A

NDA

SPI0_WP#

3.3K

SPI0_HOLD#

3.3K

R7T1 0R7T1 0

2

C5N6

C5N6 10pF

10pF

5%

5% .

.

R5N7

R5N7 100K

100K

5%

R5A3

1.87k

1%

U7E1

8

VDD

3

WP#

7

HOLD#

SST SPI FLASH

R6R4 47R6R4 47

R5N2

R5N2 200K

200K

NO_STUFF

ED_VREF

SI

SO CE# SCK

VSS

1 3

SPI_CS#0_SI_R

5

SPI_CS#0_SO_R

2 1 6

4

+

-

1%

SPI_CLK 22

ENERGY_DET 21

SPI_SI 22

SPI_SO 22

1.5

5

+V3.3M_CK505

R5G11 0.002

D D

C C

J6H1

NO_STUFF

J6H1

5Pin_JACK

35 412

B B

A A

R6W2 0R6W2 0

1%

C5V5

4.7uF

10%

R6W1 0R6W1 0

R5V9 0R5V9 0

VDD_CK505

R6G8 0R6G8 0

R6V15 0R6V15 0

+V3.3S5,7,10,12,16..26,28,30..32,34,38..42,44,45,49,50,52,55..57

CLK_PCIF38

21

Y6H1

14.318MHZ

C6V6

NO_STUFF

C6V6 33pF

33pF

5%

5% .

.

(Default

C6W1

C6W1 33pF

33pF

5%

5% .

.

XTAL_IN_D XTAL_IN

R6V16 0

R6V18 0

FSB Frequency Select:

CPU

J1G2 -> 1 - 2

Driven

J1G5 -> 1 - 2 J1G8 -> 1 - 2

533

800

J1G2 -> 2 - 3 J1G5 -> 2 - 3 J1G8 -> 2 - 3

J1G2 -> Open J1G5 -> Open J1G8 -> 2-3

FSB Freq (MHz)

C6W4

0.1uF

10%

10% .

.

C6W2

4.7uF

10%

C5V6

0.1uF

10%

10% .

.

R6W3

R6W3 10K

10K

5%

Setting)

CLK_PCI38

XTAL_OUT

C6W3

0.1uF

10%

.

C5W6

0.1uF

10%

.

C6V7

0.1uF

10%

.

CLK_REF_ICH23 CLK_REF_SIO40 CLK_REF_LPC44

CLK_USB4823

CLK_BSEL0 CLK_BSEL1

CLK_BSEL2

CPU_BSEL03

CPU_BSEL13

CPU_BSEL23

+V3.3S5,7,10,12,16..26,28,30..32,34,38..42,44,45,49,50,52,55..57

NO_STUFF

R6W4

R6W4 10K

10K

5%

5

4

VDD_CK_VDD_PCI

VDD_CK_VDD_48

VDD_CK_VDD_SRC

VDD_CK_VDD_REF

C6G5

0.1uF

10%

.

VDD_CK_VDD_CPU

R6H5

R6H5 10K

10K

5%

R6H6

R6H6 10K

10K

5%

+V1.05S_CPU 3,4,20,41,44,54

R6H7 2.2KR6H7 2.2K

R6G6 10KR6G6 10K

R6G7 33R6G7 33 R6V14 33R6V14 33 R6V13 33R6V13 33

R1G456R1G4 56

BSEL0_PULLUP

J1G2

1 3

CON3_HDR

J1G5

1 3

CON3_HDR

J1G8

1 3

CON3_HDR

CLK_SATA_OE#23

PCI2_TME

2

4

+VDDIO_CLK

XTAL_IN XTAL_OUT

3,4,20,41,44,54 +V1.05S_CPU

R1E121KR1E12 1K

R6H1 475R6H1 475

R6H2 22R6H2 22 R6H3 22R6H3 22

+VDDIO_CLK

R1G11KR1G1 1K

R1T11KR1T1 1K

R6H4 33R6H4 33

CLK_BSEL0

XDP_OBS020

CLK_BSEL1

XDP_OBS120

CLK_BSEL2

XDP_OBS220

PCI0_OE#_R

PCI4_SRC5_EN

PCIF5_ITP_EN

FSA

FSC

U6H2

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

61

VDD_REF

39

VDD_SRC

55

VDD_CPU

12

VDD_IO

20

VDD_PLL3_IO

26

VDD_SRC_IO_1

42

VSS_SRC3

36

VDD_SRC_IO_2

49

VDD_CPU_IO

1

PCI0/OE#0/2

3

PCI1/OE#1/4

4

PCI2/LTE

5

PCI3

6

PCI4/SRC5_EN

7

PCIF5/ITP_EN

60

XTAL_IN

59

XTAL_OUT

10

USB/FSA

57

FSB/TESTMODE

62

REF/FSC/TESTSEL

8

VSS_PCI

11

VSS_48

15

VSS_IO

19

VSS_PLL3

52

VSS_CPU

23

VSS_SRC1

29

VSS_SRC2

45

VDD_SRC_IO_3

58

VSS_REF

CK505

RP1E1D

RP1D1D0RP1D1D

RP1E1A

RP1D1A0RP1D1A

R1G2 1KR1G2 1K

RP1E1B

RP1D1B0RP1D1B

R1E6 1KR1E6 1K

RP1E1C

RP1D1C0RP1D1C

CK505 TSSOP64

CKPWRGD/PWRDWN#

SPARE

R1E5 1KR1E5 1K

0NO_STUFF

0

0NO_STUFF

0

0NO_STUFF

0

3

IO_VOUT

SCLK

SRC5/PCI_STOP#

SRC5#/CPU_STOP#

CPU0

CPU0#

CPU1

CPU1#

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC11/OE#10 SRC11#/OE#9

SRC9

SRC9#

SRC7/OE#8

SRC7#/OE#6

SRC6

SRC6#

SRC4

SRC4#

SRC3/OE#_0/2 SRC3#/OE#1/4

SRC2/SATA

SRC2#/SATA#

SRC1/SE1

SRC1#/SE2

SRC0/DOT96

SRC0#/DOT96#

45

0NO_STUFF

45

0

18

27

36

3

SDA

48

64 63

38 37

CPU0

54

CPU#0

53

CPU1

51

CPU#1

50

SRC8_ITP

47

SRC#8_ITP#

46

SRC10#

35

SRC10

34

CLK_MCH_R_OE#

33 32

SRC9

30

SRC#9

31

SRC7

44

SRC#7

43

SRC6

41

SRC#6

40

SRC4

27

SRC#4

28

SRC3

24

SRC#3

25

SRC2

21

SRC2#

22

SS_CLK

17

SS_CLK#

18

DOT96

13

DOT96#

14 56

MCH_BSEL0 7

XDP_BPM#3 3

MCH_BSEL1 7

XDP_BPM#2 3

MCH_BSEL2 7

XDP_BPM#1 3

IO_VOUT

SMB_CLK_M3 23,38 SMB_DATA_M3 23,38

PM_STPPCI# 23,44 PM_STPCPU# 23,44

R6G10 33R6G10 33 R6G11 33R6G11 33

R6G12 33R6G12 33 R6G13 33R6G13 33

R5G14 33R5G14 33 R5G15 33R5G15 33

R5G20 33R5G20 33 R5G21 33R5G21 33

R5G8 475R5G8 475

R5H11 33R5H11 33 R5H12 33R5H12 33

R5G16 33R5G16 33 R5G17 33R5G17 33

R5G18 33R5G18 33 R5G19 33R5G19 33

R5H9 33R5H9 33 R5H10 33R5H10 33

R5H7 33R5H7 33 R5H8 33R5H8 33

R5H5 33R5H5 33 R5H6 33R5H6 33

R5H3 33R5H3 33 R5H4 33R5H4 33

R5H1 33R5H1 33 R5H2 33R5H2 33

2

CPU,MCH and XDP BCLK FREQUENCY SELECTION TABLE

FSC

FSB

BSEL1

BSEL2

1 0 0 0 0

+V1.25M10,48,56,57

1 1 1

3

Q5G4

Q5G4 BSS138

BSS138

1

.

2

IO_VOUT_D

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6

CLK_XDP 20 CLK_XDP# 20

CLK_PCIE_3GPLL# 7 CLK_PCIE_3GPLL 7

CLK_MCH_OE# 7

CLK_PCIE_PEG 19 CLK_PCIE_PEG# 19

CLK_SRC_DB800 38 CLK_SRC_DB800# 38

CLK_PCIE_ICH 22 CLK_PCIE_ICH# 22

CLK_PCIE_DMI_LAI CLK_PCIE_DMI_LAI#

CLK_PCIE_XDP_3GPLL 20 CLK_PCIE_XDP_3GPLL# 20

CLK_PCIE_SATA 21 CLK_PCIE_SATA# 21

DREFSSCLK 7 DREFSSCLK# 7

DREFCLK 7 DREFCLK# 7

CLK_PWRGD 23,38

Matanzas

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

CK505

NDA

R5V11 0.002

1%

+VDDIO_CLK

C5V10

C5W4

0.1uF

10%

.

C5W1

C5W5

10uF

20%

Place each 0.1uF cap as close as possible to each VDD_IO pin. Place the 10uF cap on the VDD_IO plane.

2

0

0 1 1

0

1

Host Clock

FSA

frequency MHz

BSEL0

1 1 1 0 0 0 0 1

C5V9

C5V8

0.1uF

10%

.

C5G12

C5G11

10uF

20%

37 58Tuesday, November 21, 2006

1

100 133 166 200 266 333 400 Reserved

C5W3

0.1uF

10%

10% .

.

Intel Confidential

of

1

C5V7

0.1uF

10%

.

C5W2

0.1uF

10%

.

1.5

5

5,7,10,12,16..26,28,30..32,34,37,39..42,44,45,49,50,52,55..57

D D

CLK_PWRGD23,37

C7P4

0.1uF

10%

.

2 4

+V3.3S

5

U7C1

INVERTER

3

R7C10

0.002

1%

1% .

.

R7P8

R7P8 10K

10K

5%

5% .

.

+V3.3S_DB800

R7P9

R7P9 10K

10K

5%

5% NO_STUFF

NO_STUFF

R7C15

R7C15 10K

10K

5%

5% .

.

C7C2

C7C2 22uF

22uF

+V3.3S_DB800

C7P3

0.1uF

10%

.

R7C111R7C11 1

R7D2

R7D2 10K

10K

5%

5% .

.

R7P14

R7P14 10K

10K

5%

5% NO_STUFF

NO_STUFF

4

C7P5

0.1uF

10%

.

AGND_DB800

C7P1

0.1uF

10%

.

R7P10

R7P10 10K

10K

5%

5% NO_STUFF

NO_STUFF

R7P12

R7P12 10K

10K

5%

5% .

.

C7P2

0.1uF

10%

.

3

C7P6

C7P7

0.1uF

10%

.

CLK_SRC_DB80037

CLK_SRC_DB800#37

SMB_CLK_M323,37 SMB_DATA_M323,37

R7P11

R7P11 10K

10K

5%

5% .

.

DB800_OEINV

DB800_PD DB800_SRC_STOP

DB800_HIGH_BW# DB800_SRC_DIV#

DB800_BYPASS#_PLL DB800_IREF

R7C12

R7C12 475

475

R7P7 0

.

AGND_DB800

U7C2

2 11 19 31 39 48 40

4

5 23

24 26

27 45

28

1 22 46

3 10 18 25 32 47

DB800

VDD1 VDD2 VDD3 VDD4 VDD5 VDDA OE_INV

SRC_IN SRC_IN#

SCLK SDATA

PWRDWN SRC_STOP

LOCK HIGH_BW# SRC_DIV#

BYPASS#/PLL IREF GND1

GND2 GND3 GND4 GND5 GNDA

DIF0

DIF#0

OE0#

DIF1

DIF#1

OE1#

DIF2

DIF#2

OE2#

DIF3

DIF#3

OE3#

DIF4

DIF#4

OE4#

DIF5

DIF#5

OE5#

DIF6

DIF#6

OE6#

DIF7

DIF#7

OE7#

DIF0

8

DIF#0

9 6

DIF1

12

DIF#1+V3.3S_DB800_VDDA

13 14

DIF2

16

DIF#2

17 15

DIF3

20

DIF#3

21 7

DIF4

30

DIF#4

29 43

34 33

DB800_OE5#

35 38

37

DB800_OE6#

36

DIF7

42

DIF7#

41 44

R7C2133R7C21 R7C2233R7C22

R7C2333R7C23 R7C2433R7C24

R7C1633R7C16 R7C1733R7C17

R7C2533R7C25 R7C2633R7C26

R7P633R7P6 R7P133R7P1

R7C14 10KR7C14 10K

R7C13 10KR7C13 10K R7C1833R7C18

R7C1933R7C19

33 33

2

CLK_PCIE_SLOT1 25 CLK_PCIE_SLOT1# 25

CLK_SLOT1_OE# 25

CLK_PCIE_SLOT2 25 CLK_PCIE_SLOT2# 25

CLK_SLOT2_OE# 25

CLK_PCIE_SLOT3 26 CLK_PCIE_SLOT3# 26

CLK_SLOT3_OE# 26

CLK_PCIE_SLOT4 26 CLK_PCIE_SLOT4# 26

CLK_SLOT4_OE# 26

CLK_PCIE_SLOT5 26 CLK_PCIE_SLOT5# 26

CLK_SLOT5_OE# 26

CLK_PCIE_DOCK 45 CLK_PCIE_DOCK# 45

CLK_REQ#_DOCK 45

+V3.3S_DB800

CLK_PCIE_SLOT1 CLK_PCIE_SLOT1# CLK_PCIE_SLOT2 CLK_PCIE_SLOT2# CLK_PCIE_SLOT3 CLK_PCIE_SLOT3# CLK_PCIE_SLOT4 CLK_PCIE_SLOT4# CLK_PCIE_SLOT5 CLK_PCIE_SLOT5# CLK_PCIE_DOCK CLK_PCIE_DOCK#

1

R7D4 49.9R7D4 49.9 R7D5 49.9R7D5 49.9 R7D6 49.9R7D6 49.9 R7D7 49.9R7D7 49.9 R7C8 49.9R7C8 49.9 R7C9 49.9R7C9 49.9 R8D3 49.9R8D3 49.9 R8D4 49.9R8D4 49.9 R7C1 49.9R7C1 49.9 R7C2 49.9R7C2 49.9 R7C6 49.9R7C6 49.9 R7C7 49.9R7C7 49.9

C C

5,7,10,12,16..26,28,30..32,34,37,39..42,44,45,49,50,52,55..57

+V3.3S5,7,10,12,16..26,28,30..32,34,37,39..42,44,45,49,50,52,55..57

U7E4

1

GND1

2

VDD1

3

1Y0

4

1Y1

5

1Y2

6

GND2

7

GND3

8

1Y3

9

1Y4

10

B B

CLK_PCI_KBC42

CLK_PCI_PCISLOT333

CLK_PCI_LPC44

CLK_PCI_TPM44

R7T17 10KR7T17 10K R7T20 680R7T20 680

R7T4 33R7T4 33 R7T5 33R7T5 33 C7T12

R7T10 33R7T10 33

+V3.3S5,7,10,12,16..26,28,30..32,34,37,39..42,44,45,49,50,52,55..57

R7T15 10KR7T15 10K R7T18 33R7T18 33

PCIF_OE1_DIS PCIF_2Y4

PCI_1Y0 PCI_1Y1

PCI_1Y3

PCI_OE1_EN PCI_2Y4

A A

5

4

11 12

1 2 3 4 5 6 7 8

9 10 11 12

VDD2 1G 2Y4

CDCVF2310

U7E5

GND1 VDD1 1Y0 1Y1 1Y2 GND2 GND3 1Y3 1Y4 VDD2 1G 2Y4

CDCVF2310

VDD6 VDD5

GND5 GND4

VDD4 VDD3

VDD6 VDD5

GND5 GND4

VDD4 VDD3

+V3.3S

24

CLK

23 22 21

2Y0

20

2Y1

19 18 17

2Y2

16

2Y3

15 14 13

2G

24

CLK

23 22 21

2Y0

20

2Y1

19 18 17

2Y2

16

2Y3

15 14 13

2G

PCIF_2Y0

PCIF_2Y3

PCIF_OE2_EN

PCI_2Y0 PCI_2Y1

PCI_2Y2 PCI_2Y3

PCI_OE2_EN

CLK_PCIF 37

CLK_PCI 37

R6T633R6T6

R6T1033R6T10

5,7,10,12,16..26,28,30..32,34,37,39..42,44,45,49,50,52,55..57

R6T12 10KR6T12 10K

R7T615R7T6 R7T933R7T9

R7T1233R7T12 R7T1633R7T16

R7T19 10KR7T19 10K

33

15 33

33 33

CLK_PCIF_ICH 22

CLK_PCIF_2Y2 CLK_PCIF_FWH 39

+V3.3S

CLK_PCI_SIODOCK 40 CLK_PCI_PCIGOLDF 34

CLK_PCI_XDP CLK_PCI_SIO 40

+V3.3S 5,7,10,12,16..26,28,30..32,34,37,39..42,44,45,49,50,52,55..57

3

+V3.3S5,7,10,12,16..26,28,30..32,34,37,39..42,44,45,49,50,52,55..57

C7T13

C7T7

0.1uF

10%

.

38 58Tuesday, November 21, 2006

C7T12

0.1uF

10%

.

1

C7T7

0.1uF

10%

.

C7T16

0.1uF

10%

.

Intel Confidential

of

C6T8

C7T15

0.1uF

10%

.

Decoupling caps for both CDCVF2310 devices

+V3.3S5,7,10,12,16..26,28,30..32,34,37,39..42,44,45,49,50,52,55..57

C7T6

C7T14

0.1uF

10%

.

Matanzas

Title

Size Document Number Rev

Date: Sheet

A

DB800 & Buffers

NDA

2

C7T10

0.1uF

10%

.

C7T21

0.1uF

10%

.

C7T18

0.1uF

10%

.

1.5

C7T22

0.1uF

10%

10% .

.

5

4

3

2

1

+V3.3S_FWH

R8V3

R8V6

R8V4

R8W5

R8V8

10K

R8V8

10K

D D

FWH INIT Voltage Translation Circuit

+V3.3S5,7,10,12,16..26,28,30..32,34,37,38,40..42,44,45,49,50,52,55..57

R8W2

R8W2 330

330

R8W1

1.3K

FWH_INIT#

3

CR8H1A

5

3904

4

H_INIT#_DQ

H_INIT#_R21

R7V30 330R7V30 330

H_INIT#_D

6

CR8H1B

2

3904

1

C C

R8V6

10K

U8G1

FWH_INIT#

PLT_RST#7,19,22,25,26,40,42,57

CLK_PCIF_FWH38

R8V16 100R8V16 100

PLT_RST#_D

FGPI4 FGPI3 FGPI2 FGPI1 FGPI0

TP_FWH_ID3 TP_FWH_ID2 TP_FWH_ID1 TP_FWH_ID0

TP_FWH_RSVD2 TP_FWH_RSVD1 TP_FWH_RSVD5 TP_FWH_RSVD4

U8G1

37 12

9

7 15 16 17 18

21 22 23 24

32 33 34 35 36

29 30 40

INIT# RST#

CLK FGPI4

FGPI3 FGPI2 FGPI1 FGPI0

ID3 ID2 ID1 ID0

RSVD2 RSVD1 RSVD5 RSVD4 RSVD3

GND2 GND1 GNDA

FWH sits in the FWH_TSOP_Socket, Not on the board

FWH

VCC2 VCC1 VCCA

TBL#

FWH4 FWH3 FWH2 FWH1 FWH0

VPP

WP#

NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8

11 10 31 39

TBL#

20

WP#

19 38

28 27 26 25

IC_R

2

IC

TP_FWH_NC1

1

TP_FWH_NC2

3

TP_FWH_NC3

4

TP_FWH_NC4TP_FWH_RSVD3

5

TP_FWH_NC5

6

TP_FWH_NC6

8

TP_FWH_NC7

13

TP_FWH_NC8

14

BOARD REVISION

+V3.3A19,21,23..29,33,34,40..42,44..48,50..52,55..57

PCA9557_RST#

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 REV_FAB_ID0 REV_FAB_ID1 REV_FAB_ID2 REV_FAB_ID3

+V3.3A19,21,23..29,33,34,40..42,44..48,50..52,55..57

R9G5

R9G5 1K

1K

5%

R9G23

R9V4

R9V5

R9V5 10K

10K

NO_STUFF

R9V7

B B

R9V7 10K

10K

R9V4 10K

10K

NO_STUFF

R9V6

R9V6 10K

10K

R9G24

R9G24 10K

10K

NO_STUFF

R9G21

R9G21 10K

10K

R9G23 10K

10K

.

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3

R9G20

R9G20 10K

10K

NO_STUFF

SMB_BS_CLK42,44,45,51,52

SMB_BS_DATA42,44,45,51,52

C9G2

0.1uF

20%

R9V8 0R9V8 0 R9V10 0R9V10 0 R9V9 0R9V9 0

+V3.3A19,21,23..29,33,34,40..42,44..48,50..52,55..57

U9G1

A0_R A1_R A2_R

16

8 1

2 3

4 5

VDD VSS

SCLK SDATA

A0 A1 A2

PCA9557PW

RESET#

15 6

I/O0

7

I/O1

9

I/O2

10

I/O3

11

I/O4

12

I/O5

13

I/O6

14

I/O7

8-bit I/O Port Expander

+V3.3S5,7,10,12,16..26,28,30..32,34,37,38,40..42,44,45,49,50,52,55..57

R8V17 0.002

C8V5

0.1uF

20%

R8F1 100R8F1 100 R8V12 100R8V12 100

LPC_FRAME# 21,40,42,44 LPC_AD3 21,40,42,44 LPC_AD2 21,40,42,44 LPC_AD1 21,40,42,44 LPC_AD0 21,40,42,44

FAB ID Strapping Table

FAB_REV

3

2

0

0 0

0

04

0

1

0 0

180

0

1

0

1

0

1

0 0

1

01

1

1 1

1

BOARD REVISION Strapping Table

BOARD REVISION

3

2

1

0

+V3.3S_FWH

1%

C8V6

C8V6 10UF

10UF

FWH_TBL# 23,44 FWH_WP# 23,44

R8V7

R8V7 10K

10K

5%

0

1

0

0 0

1 0

1 1

1

00

1 0

1

0

0 0

1 0

1 1

00

1

0

1

0

1

C8W1

0.1uF

20%

BOARD FAB

BOARD ID

Matanzas

1 2 3

5 6 7

9 10 11 12

13 14 15 16

FAB REVISION

+V3.3A19,21,23..29,33,34,40..42,44..48,50..52,55..57

slave address

0 0 1 1 A2 A1 A0 R/W

R9G9

R9G8

R9G8 10K

10K

5%

5% NO_STUFF

NO_STUFF

R9G13

R9G13 10K

10K

5%

5% NO_STUFF

NO_STUFF

R9G9 10K

10K

5%

5% .

.

R9G10

R9G10 10K

10K

5%

5% NO_STUFF

NO_STUFF

fixed

PCA9557 Address

programmable

REV_FAB_ID0

R9G16

R9G16 10K

10K

5%

5% .

.

REV_FAB_ID1 REV_FAB_ID2 REV_FAB_ID3

4

Intel Confidential

Matanzas

Title

Size Document Number Rev

Date: Sheet

3

Date: Sheet

FWH and I/O Port Expander

A

NDA

2

Intel Confidential

39 58Tuesday, December 05, 2006

1

1.5

of

A A

R9G14

R9G14 10K

10K

5%

R9G22 10K

10K

5%

R9G15

R9G15 10K

10K

5%

NO_STUFF

R9G22

5

+V3.3S_SIO

+V3.3A19,21,23..29,33,34,39,41,42,44..48,50..52,55..57

D D

C7T5

0.1uF

20%

NO_STUFF

20%

TP_SIO_GPIO13

LPCD_OPNREQ_OUT#

LPCD_RI#

TP_GPIO32 TP_GPIO33 LPCD_LPCPD# LPCD_LPCRST# LPCD_PWREN#

Base Address:

00 = 0x002E 01 = 0x004E 10 = 0x162E 11 = 0x164E

Default:

11= 0x164E

R7T11

8.2K

RS232_EN41

IRDA_CIR_SLT41

SMC_EXTSMI#23,42,44,45

RS232_RI#41

LPCD_PWRGD

C C

+V3.3S_SIO

R7E4 10KR7E4 10K

R7E3 10KR7E3 10K

SER_RTSA#

SER_DTRA#

R7T7

R7T7 100K

100K

5%

LPCS_PME#44

L_BKLTSEL1#17

L_BKLTSEL0#17

IR_TXD41 IR_RXD41

IR_MODE41

R7E6 10K

R7E5 10K

NO_STUFF

SMSC PORT-SWITCH

U7E6

5

VCC1

17

VCC2

31

VCC3

42

VCC4

60

VCC5

48

VTR

8

VSS1

20

VSS2

29

VSS3

37

VSS4

45

VSS5

62

VSS6

27

GPIO10

28

GPIO11

30

GPIO12/IO_SMI#

32

GPIO13/IRQIN1

33

GPIO14/IRQIN2

34

GPIO15

35

GPIO16

36

GPIO17

38

GPIO30

39

GPIO31

40

GPIO32

41

GPIO33

43

GPIO34

44

GPIO35

46

GPIO36

61

GPIO37

49

IRTX2

50

IRRX2

51

IRMODE/IRRX3

SIO1007-JV

IR

POWER & GROUND

GENERAL PURPOSE I/O

UART2

4

LPC INTERFACE

DOCKING LPC INTERFACE

LFRAME

LDRQ0 LDRQ1

PCI_RESET

LPCPD

CLKRUN

SER_IRQ

IO_PME

PCI_CLK

LPC_CLK_33

SIO_14M

DLAD(0) DLAD(1) DLAD(2) DLAD(3)

DLFRAME

DLDRQ1

DCLKRUN

DSER_IRQ

DLPC_CLK_33

DSIO_14M

UART1

RTS1#/SYSOPT0 DTR1#/SYSOPT1

LAD0 LAD1 LAD2 LAD3

RXD1

TXD1

DSR1

CTS1

DCD1

3

+V3.3S5,7,10,12,16..26,28,30..32,34,37..39,41,42,44,45,49,50,52,55..57

C7T17

R8T5

R8E6

10K

5%

64 2 4 7 14

SIO_DRQ#0

24

SIO_DRQ#1

12

SIO_RST#

22 25 16 19

PM_RI_SIO

47 21 10 23

D_LAD_0

63

D_LAD_1

1

D_LAD_2

3

D_LAD_3

6

D_LFRAME#

13

D_LDRQ1

11

D_CLKRUN

15

D_SER_IRQ

18

D_CLK_33

9

D_CLK_14

26

52 53 54 56 58

RI1

59 55 57

+V3.3S5,7,10,12,16..26,28,30..32,34,37..39,41,42,44,45,49,50,52,55..57

R9F9

R9F9 100K

100K

5%

1

2

R7T8 0R7T8 0

SER_DTRA# SER_RTSA#

U9F1

VCC

GND

OUT

IN

MAX6816

LPC_AD0 21,39,42,44 LPC_AD1 21,39,42,44 LPC_AD2 21,39,42,44 LPC_AD3 21,39,42,44

LPC_FRAME# 21,39,42,44

PM_SUS_STAT# 23,42,44 PM_CLKRUN# 23,33,34,42,44 INT_SERIRQ 23,33,42,44 PM_RI# 23,44 CLK_PCI_SIO 38

CLK_PCI_SIODOCK 38

CLK_REF_SIO 37

SER_SINA 41 SER_SOUTA 41 SER_DSRA# 41 SER_CTSA# 41 SER_RIA# 41 SER_DCDA# 41 SER_RTSA# 41 SER_DTRA# 41

C9F1 0.1uFC9F1 0.1uF

4

LPCD_OPNREQ_OUT#LPCD_OPNREQ#

3

5%

TPM_DRQ#044

R8T4

R8T4 10K

10K

5%

C7T17

0.1uF

20%

U8E4

1 2

KSC_LPC_DOCK#42

2

5,7,10,12,16..26,28,30..32,34,37..39,41,42,44,45,49,50,52,55..57

+V3.3S

53

74AHC1G08

4

LPC_DRQ#144

+V3.3A19,21,23..29,33,34,39,41,42,44..48,50..52,55..57

+V3.3S5,7,10,12,16..26,28,30..32,34,37..39,41,42,44,45,49,50,52,55..57

R9F12

R9F12 100K

100K

5%

LPC_DRQ#044

R8E5

R8E5 10K

10K

5%

D_LAD_0 D_LAD_2 D_LAD_1 LPCD_PWRGD

D_LFRAME#

LPCD_SMC_EXTSMI#

D_CLKRUN

D_CLK_33

R7E1 0.002

1%

R7T14

R7T14 10K

10K

5%

AND_DRQ#0

+V3.3S5,7,10,12,16..26,28,30..32,34,37..39,41,42,44,45,49,50,52,55..57

C7T8

0.1uF

20%

U8E3

1 2

LPC HOT DOCKING

J9E3

1

2 3 4 5

6 798

10

11

12

13

14

15

16

17

18

19

20

21

22

23 24

2X12-HDR_SHRD

+V3.3S_SIO

C7T20

0.1uF

C7E1

C7E1 22UF

22UF

20%

+V3.3S5,7,10,12,16..26,28,30..32,34,37..39,41,42,44,45,49,50,52,55..57

C7T23

0.1uF

20%

U8E5

1 2

53

74AHC1G08

D_LAD_3

LPCD_PWREN#

LPCD_PCI_PME#

D_LDRQ1 LPCD_PD# D_SER_IRQ LPCD_RST#

LPCD_OPNREQ#

D_CLK_14

C7T19

0.1uF

20%

53

4

1

74AHC1G08

C7T9

0.1uF

20%

4

ICH_DRQ#0 21

ICH_DRQ#1 21

C7T11

0.1uF

20%

C7T4

0.1uF

20%

B B

LPC DOCKING

5,7,10,12,16..26,28,30..32,34,37..39,41,42,44,45,49,50,52,55..57

LPCD_LPCPD#

PM_SUS_STAT#

5,7,10,12,16..26,28,30..32,34,37..39,41,42,44,45,49,50,52,55..57

A A

LPCD_LPCRST# PLT_RST#

+V3.3S

53

U7E2

1 2

+V3.3S

53

U7E3

1 2

74AHC1G08

5

4

74AHC1G08

4

C7T2

0.1uF

20%

C7T1

0.1uF

20%

LPCD_PD#

R7E2

R7E2 0

0

NO_STUFF

LPCD_PWRGD

LPCD_RST#

4

+V3.3A19,21,23..29,33,34,39,41,42,44..48,50..52,55..57

R8E9

R8E9 10K

10K

5%

LPCD_QSEN#

3

Q8E4

Q8E4 BSS138

BSS138

1

2

LPCD_PCI_PME#

LPCD_RI# SMC_EXTSMI#

U7E7

1

OE1#

2

1A

3

1B GND42A

74CBT3306

3

VCC

OE2#

2B

+V5A24,29,42,47,48,51,55,57

C7T24

0.1uF

20%

8 7 6

LPCD_SMC_EXTSMI#

5

Default: 1 - 2

J7D1

PLT_RST#7,19,22,25,26,39,42,57

Matanzas

Title

Size Document Number Rev

Date: Sheet

SIO

A

NDA

2

RST_PD

R7E7

R7E7 10K

10K

5%

1 3

CON3_HDR

SIO_RST#

2

40 58Tuesday, December 05, 2006

1

Intel Confidential

1.5

of

5

RS-232 TRANSCEIVER

U7D2

SERBUF_C1+

C7R5

0.1uF

10%

D D

RS232_RI#40

+V3.319,27,33,42..44,49,56,57

RS232_EN40

Q7C1

BSS138

R7R13

R7R13 1K

1K

5%

R7C5

R7C5 1K

1K

5%

3

2

SERBUF_C1-

SERBUF_C2+

C7R6

0.1uF

10%

SERBUF_C2-

1

SER_RIA

SER_CTSA#40

SER_RIA#40 SER_SINA40

SER_DSRA#40

SER_DCDA#40 SER_DTRA#40

SER_SOUTA40 SER_RTSA#40

SER_ON

28

24

1

2

20 19 18 17 16 15

14 13 12

23 22 21

U7D2

MAX3243

C C

SIO VID VOLTAGE TRANSLATION

4

+V3.3 19,27,33,42..44,49,56,57

26

VCC

C1+

C1-

C2+

C2R2OUTB

R1OUT R2OUT R3OUT R4OUT R5OUT

T1IN T2IN T3IN

FORCEON FORCEOFF# INVALID#

R1IN R2IN R3IN R4IN R5IN

T1OUT T2OUT T3OUT

GND

C7R7

0.1uF

20%

V+

V-

27

3

4 5 6 7 8

9 10 11

25

SERBUF_V+

SERBUF_V-

Spare

C7D5

C7D5 22UF

22UF

SERBUF_CTSA SERBUF_RIA SERBUF_SINA# SERBUF_DSRA SERBUF_DCDA

SERBUF_DTRA SERBUF_SOUTA# SERBUF_RTSA

R1P2 10KR1P2 10K

C7R4

0.1uF

10%

C7R3

0.1uF

10%

U1C1D_SPARE

3

+V3.3A 19,21,23..29,33,34,39,40,42,44..48,50..52,55..57

C7B2 0.1uF

10%

C1-3

R7N1

R7N1 10K

10K

C7B3 0.1uF

5%

KBC_PROG_RX#42

KBC_PROG_TX#17,42

+V5S5,11,12,16..18,24,30..32,34,49,50,52,53,55..57

3

U1B3D

11

+

10

13

-

LM339

12

10%

C2-5

+V3.3S5,7,10,12,16..26,28,30..32,34,37..40,42,44,45,49,50,52,55..57

C4A2,C4A5 Should be near U4A1.

U7B2

C1+1

1 3

C2+4

4

5 12 11

MAX3232_RS232_TRNCVR

R4M3

0.002

1%

+V3.3S_IR

R4A1 4.7R4A1 4.7

C1+ C1C2+ C2R1OUT

R2OUT9R2IN T1IN T2IN10T2OUT

C4M2

0.1uF

10%

T1OUT

C4A2

0.1uF

10%

2

+V3.3A19,21,23..29,33,34,39,40,42,44..48,50..52,55..57

C7M6

0.1uF

C7N2

C7N2 22UF

22UF

20%

16

VCC

V_C_2

C7N1 0.1uF

2

V+

V_C_6

6

V-

SER_KBCPROG_RX_IN SER_KBCPROG_RX_IN

13

R1IN

8 14 7 15

GND

10%

C7B1 0.1uF

10%

SER_TX_OUT

SERIAL PORT CONNECTOR

SERBUF_RIA SERBUF_DTRA SERBUF_CTSA TX_OUT SERBUF_RTSA RX_IN SERBUF_DSRA SERBUF_DCDA

C4A4

+

C4A1

6.8uF

0.1uF

10%

C4A5

+

6.8uF

10%

FB2A3A 60OHM-100MHZFB2A3A 60OHM-100MHZ FB2A3B 60OHM-100MHZFB2A3B 60OHM-100MHZ FB2A3C 60OHM-100MHZFB2A3C 60OHM-100MHZ FB2A3D 60OHM-100MHZFB2A3D 60OHM-100MHZ FB2A5A 60OHM-100MHZFB2A5A 60OHM-100MHZ FB2A5B 60OHM-100MHZFB2A5B 60OHM-100MHZ FB2A5C 60OHM-100MHZFB2A5C 60OHM-100MHZ FB2A5D 60OHM-100MHZFB2A5D 60OHM-100MHZ

VCC_HSDL

1 8 2 7 3 6 4 5 1 8 2 7 3 6 4 5

1

In Ckt H8 Programming J8B1 and J8B2

Disable 1-2 (Default) Enable 2-3 (In Ckt Programming)

J8B1

SERBUF_SOUTA# SER_TX_OUT

SERBUF_SINA#

J8B1

1

2

3

CON3_HDR

J8B2

1

2

3

CON3_HDR

SERPRT_RIA SERPRT_DTRA SERPRT_CTSA SERPRT_TX_OUT SERPRT_RTSA SERPRT_RX_IN SERPRT_DSRA SERPRT_DCDA

TX_OUT

RX_IN

IR

U4A1

R4M4 3.9R4M4 3.9

IR_RXD40

IR_MODE40

R4M2

R4M2 10K

10K

R4M1

R4M1 10K

10K

LED_A IRDA_TXD

CIR_TXD

U4A1

1

LED_A

2

IO_VCC

3

TXD_IR

4

RXD

5

SD

6

VCC

7

TXD_RC

8

GND

HSDL-3021_021

GND

GND RI

RI DTR

DTR CTS

CTS TXD

TXD RTS

RTS RXD

RXD DSR

DSR DCD

DCD

SHLD

J2A2A

5 9 4 8 3 7 2 6 1

2IN1

9

U4M1

+V5S5,11,12,16..18,24,30..32,34,49,50,52,53,55..57

3

U1B1A

VR_VID052

R1N17 1KR1N17 1K

VID_COMP

VID_0_D

B B

+V1.05S_CPU3,4,20,37,44,54

VID_COMP

VID_1_D

VID_COMP

VID_2_D

R1N41 1K

1%

VR_VID152

VR_VID252

5,11,12,16..18,24,30..32,34,49,50,52,53,55..57

+V5S

R1N22 1KR1N22 1K

R1N26 1KR1N26 1K

A A

C1N1

C1N4

0.1uF

20%

CAD NOTE:

Place near U1B1 & U1B3

5

+

4

-

+V5S5,11,12,16..18,24,30..32,34,49,50,52,53,55..57

7

+

6

-

+V5S5,11,12,16..18,24,30..32,34,49,50,52,53,55..57

9

+

8

-

R1P3 1K

C1N7

0.1uF

20%

12

3

12

3

12

U1B1A

LM339

U1B1B

LM339

U1B1C

LM339

1%

SIO_VID0

2

SIO_VID1

1

SIO_VID2

14

VID_COMP

VR_VID352

VR_VID452

VR_VID552

VR_VID652

R1N18 1KR1N18 1K

R1N38 1KR1N38 1K

4

R1P5 1KR1P5 1K

R1P4 1KR1P4 1K

VID_COMP

VID_3_D

VID_COMP

VID_4_D

VID_COMP

VID_5_D

VID_COMP

VID_6_D

+V5S5,11,12,16..18,24,30..32,34,49,50,52,53,55..57

3

U1B1D

11

+

10

-

LM339

12

+V5S5,11,12,16..18,24,30..32,34,49,50,52,53,55..57

3

U1B3A

5

+

4

-

LM339

12

+V5S5,11,12,16..18,24,30..32,34,49,50,52,53,55..57

3

U1B3B

7

+

6

-

LM339

12

+V5S5,11,12,16..18,24,30..32,34,49,50,52,53,55..57

3

U1B3C

9

+

8

-

LM339

12

SIO_VID3

13

SIO_VID4

2

SIO_VID5

1

SIO_VID6

14

IRDA_CIR_SLT =0, then Y0=A, IRDA_CIR_SLT=1,then Y1=A.

SIO_VID0 SIO_VID1 SIO_VID2 SIO_VID3 SIO_VID4 SIO_VID5 SIO_VID6

3

IRDA_CIR_SLT40

IR_TXD40

R1N33 10KR1N33 10K

R1N16 10KR1N16 10K

R1N13 10KR1N13 10K

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

R1N37 10KR1N37 10K

R1N24 10KR1N24 10K

R1N29 10KR1N29 10K

Legacy Support

NDA

U4M1

1 2

NON-INV DMUX

R1N12

R1N12 330

330

LED_VID0

R1N43 10KR1N43 10K

1 2

2

S GND

VCC

A3Y1

CR1B1

CR1B1 GREEN

GREEN

Y0

6 5 4

+V3.3S5,7,10,12,16..26,28,30..32,34,37..40,42,44,45,49,50,52,55..57

R1N15

R1N15 330

330

LED_VID1

CR1B2

CR1B2 GREEN

GREEN

1 2

C4M1

0.1uF

10%

.

R1N23

R1N23 330

330

LED_VID2

CR1B3

CR1B3 GREEN

GREEN

1 2

R1N28

R1N28 330

330

LED_VID3

CR1B4

CR1B4 GREEN

GREEN

1 2

R1N32

R1N32 330

330

LED_VID4

CR1B5

CR1B5 GREEN

GREEN

1 2

41 58Tuesday, December 05, 2006

R1N36

R1N36 330

330

LED_VID5

CR1B6

CR1B6 GREEN

GREEN

1 2

Intel Confidential

of

1

R1N42

R1N42 330

330

LED_VID6

CR1B7

CR1B7 GREEN

GREEN

1 2

1.5

5

CAD NOTE: Place C8H2 and C9V3 close to ADC AVCC pin (pin76). Route must go from power rail to caps, and then to the AVCC pin. Place

Shunt both J9H4 and J9H7 as default and as external programming

D D

+V3.3A_KBC

J9H3J9H3

C C

1 2

EC_BRK_CURRENT51

5,7,10,12,16..26,28,30..32,34,37..41,44,45,49,50,52,55..57

19,21,23..29,33,34,39..41,44..48,50..52,55..57

B B

+V3.3A

R8W3 10K NO_STUFFR8W3 10K NO_STUFF R9G12 10K NO_STUFFR9G12 10K NO_STUFF

R9V11 8.2KR9V11 8.2K

R9H8 10KR9H8 10K

R9W8 10KR9W8 10K R9G27 10K

R9G27 10K

R9G26 10KR9G26 10K R9G25 10KR9G25 10K

R9H7 10KR9H7 10K

A A

R9H10

R9H10 10K

10K

+VAC_IN_L51

SMC_RST#43

Y8G1

10MHZ

C9G4

C9G4 18PF

18PF

SMC/KSC

Enable Disable

KBC

Enable Disable

PSYS51

PBATT51

IMVP_VR_ON44,52

PM_THRM#5,12,23,44

NO_STUFF

R9H5

24.3K

1%

VBRK_MON_IN

R9W6

4.02K

1%

1% .

.

21

J9F1

1-2 (Default) 2-3

J9F1

1

2

3

CON3_HDR

J9H3

1-X (Default) 1-2

R9H9 0 NO_STUFFR9H9 0 NO_STUFF R9H6 0R9H6 0 R9W7 0 NO_STUFFR9W7 0 NO_STUFF

R9G18 0R9G18 0

H_A20GATE21,44

EC_VAUX_ON26

SMB_CLK_EC

SMB_DATA_EC

H8_P91_IRQ1#

P75_EXIRQ5#_AN5

PG1_EXIRQ9#_EXTMCI1

SMC_ME_ALERT

DOCK_SYS_PWRGD# DOCK_PE_DET#

PBATT_R

+V5A 24,29,40,47,48,51,55,57

3

+

2

-

C1W13

C1W13 1uF

1uF

20%

20% .

.

C9G3

C9G3 18PF

18PF

H8_P91_IRQ1#

TP9G1 NO_STUFFTP9G1 NO_STUFF

R9V17 0R9V17 0

+V3.3S

C1W10

0.1uF

10%16V

8

.

U1W1A

1

AD8552

4

GND_SYS_CURRENT

ALL_SYS_PWRGD23,44,48

PM_THERM#_R

R8G12

8.2K

R9G28 0R9G28 0

ALS_CLK17 ALS_DATA17

VBRK_MON

+V3.3A_KBC 43

R9G3

R9G3 10K

10K

J9H4J9H4

SMC_INITCLK43

SMB_BS_ALRT#44,51

PM_S4_STATE#23,34,44,45,56,57

PBATT_R PM_LAN_ENABLE_H8 IMVP_VR_ON_R

CPU_TACHO_FAN5,44 MCH_TACHO_FAN12,44

NETDETECT#44,55

DOCK_SYS_PWRGD#45

SW9H1

1

2

3

SPDT_SLIDE

C9V3 closest to the pin.

+VREF_ADC51

R9G2

R9V15

10K

J9H7J9H7

1 2

R9G17 100R9G17 100

R9G1 0R9G1 0

SMB_BS_CLK39,44,45,51,52 SMB_BS_DATA39,44,45,51,52

BC_ACOK44,51

SMC_ONOFF#44,55 LAN_WOL_EN23,44,56,57

PM_SLP_M#23,44,45,48,56,57

ATX_DETECT#44,55

EC_BRK_CURRENT_R

EC_CS_GAIN_SEL51

PM_PWRBTN#23,44

NMI_GATE43

PM_RSMRST#23,44

CPU_PWM_FAN5,44

MCH_PWM_FAN12,44

H_RCIN#21,44

SMC_RSTGATE#44

SMB_THRM_CLK5,12,44 SMB_THRM_DATA5,12,44

SMC_RUNTIME_SCI#23,44

SMC_EXTSMI#23,40,44,45

SMC_WAKE_SCI#23,44

BS_DISA#44,51

PM_BATLOW#23,44

KBC_PROG_TX#17,41

RSMRST#_PWRGD

R9H1 0R9H1 0 R8V5 0R8V5 0

PG1_EXIRQ9#_EXTMCI1

SMC_ME_ALERT23,44,55

ICHRM51

DOCK_PE_DET#45

VCHRM51

PE_OPNREQ#45

ME_SMC_ALERT#23,44

PM_SLP_S3#11,23,26,44,45,48,56,57

DOCK_PE_DET#

VIRTUAL DOCKING

J9H1 1-X (Default) SW9H1 1-2 (Default)

J9H1J9H1

1 2

LAYOUT NOTE: Bring test point to edge of board

5

C9V2

0.1uF

10%

.

SMC_XTAL SMC_EXTAL

SMC_RES# SMC_STBY#

KBC_DISABLE#

ALL_SYS_PWRGD_R

VBRK_MON P75_EXIRQ5#_AN5

H_A20GATE_R

TP_KSC_RES0

ALS_CLK_EC ALS_DATA_EC

4

+V3.3A_KBC 43

1

86

VCL

13 36 77 76

MD1

9

MD0

10

140 141 143 144

8

12

NMI_R

11 15

16 14 17 18 22 23 24

68 69 70 71 72 73 74 75 40

41 136 137

2 3 4 5

6 115 116

117 118 119 120 129 130

113 114

133 142

51 52 53 54 55 56 57 58

43 44 45 46 47 48 49 50

PCI_GATED_RST#33

PLT_GATED_RST#19,44

4

NOTE: Place C9V2 decoupling cap close to VCL pin 13

U9G2

VCC1 VCC3

VCL VCC2 AVREF AVCC

MD1 MD0

X1 X2 XTAL EXTAL

RES# STBY# NMI

P51/TMOY P50/EXEXCL P52/EXIRQ6#/SCL0 P97/IRQ15#/SDA0 P96/0/EXCL P92/IRQ0# P91/IRQ1# P90/IRQ2#/ADTRG#

P70/EXIRQ0#/AN0 P71/EXIRQ1#/AN1 P72/EXIRQ2#/AN2 P73/EXIRQ3#/AN3 P74/EXIRQ4#/AN4 P75/EXIRQ5#/AN5 P76/AN6 P77/AN7 PA1/KIN9# PA0/KIN8# P40/TMCI0/TXD2/DSERIRQ P41/TMO0/RXD2/DCLKRUN# P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 PB5/WUE5#/DLAD2 PB4/WUE4#/DLAD3

PB3/WUE3#/DLFRAME# PB2/WUE2# PB1/WUE1#/LSCI PB0/WUE0#/LSMI# P80/PME# P81/GA20

PB7/WUE7#/DLAD0 PB6/WUE6#/DLAD1

P84/IRQ3#/TXD1/IRTXD RESO# PG7/EXIRQ15#/EXSCLB

PG6/EXIRQ14#/EXSDAB PG5/EXIRQ13#/EXSCLA PG4/EXIRQ12#/EXSDAA PG3/EXIRQ11#/EXTMIY PG2/EXIRQ10#/EXTMIX PG1/EXIRQ9#/EXTMCI1 PG0/EXIRQ8#/EXTMCI0

PF7/EXPW15 PF6/EXPW14 PF5/EXPW13 PF4/EXPW12 PF3/IRQ11#/EXTMOX PF2/IRQ10# PF1/IRQ9# PF0/IRQ8#

H8S/2104

+V3.3 19,27,33,41,43,44,49,56,57

R8W4

10K

+V3.3A19,21,23..29,33,34,39..41,44..48,50..52,55..57

R8H1 0.002

PA7/KIN15#/PS2CD

PA6/KIN14/PS2CC

PA3/KIN11#/PS2AD PA2/KIN10#/PS2AC

PA5/KIN13#/PS2BD PA4/KIN12#/PS2BC

P95/IRQ14# P94/IRQ13# P93/IRQ12#

P60/KIN0#/FTCI/TMIX

P61/KIN1#/FTOA

P62/KIN2#/FTIA/TMIY

P63/KIN3#/FTIB P64/KIN4#/FTIC P65/KIN5#/FTID

P66/IRQ6#/KIN6#/FTOB

P67/IRQ7#/KIN7#/TMOX

P27/PW15 P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10

P21/PW9 P20/PW8

P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3

P34/LFRAME#

P35/LRESET#

P36/LCLK

P37/SERIRQ

P82/CLKRUN#

P83/LPCPD#

P85/IRQ4#/RXD1/IRRXD

P86/IRQ5#/SCK1/SCL1

P42/EXIRQ7#/TMRI0/SCK2/SDA1

PC7/WUE15#/DLDRQ

PC6/WUE14#/LDRQ

PC5/WUE13# PC4/WUE12# PC3/WUE11# PC2/WUE10#

PC1/WUE9# PC0/WUE8#

PD7/TIOCB2/TCLKD

PD6/TIOCA2

PD5/TIOCB1/TCLKC

PD4/TIOCA1 PD3/TIOCD0/TCLKB PD2/TIOCC0/TCLKA

PD1/TIOCB0

PD0/TIOCA0

ETRST# PE4/ETMS PE3/ETDO

PE2/ETDI PE1/ETCK PE0/LID3#

R8W6

R8W6 10K

10K

Q8H1

Q8H1 BSS138

BSS138

3

2

Q8H2

1

Q8H2

3

1

3

1%

33 34

38 39

35 37 19 20 21

78 79 80 81 82 83 84 85

96 97 98 99 100 101 102 103 104

P17

105

P16

106

P15

107

P14

108

P13

109

P12

110

P11

112

P10

121 122 123 124 125 126 127 128 131 132

134 135 138

7

VSS1

42

VSS2

95

VSS3

111

VSS4

139

VSS5

67

AVSS

87 88 89 90 91 92 93 94

59 60 61 62 63 64 65 66

25

MD2

26

FWE

27 28 29 30 31 32

BSS138

2

SMC_RSTGATE#

3

+V3.3A_KBC43

C9V3

C9W2

C8H2

C8H2 22uF

22uF

KBC_CAPSLOCK KBC_SCROLLOCK KBC_NUMLOCK

KBC_SCANIN0 KBC_SCANIN1 KBC_SCANIN2 KBC_SCANIN3 KBC_SCANIN4 KBC_SCANIN5 KBC_SCANIN6 KBC_SCANIN7

KBC_SCANOUT15 KBC_SCANOUT14 KBC_SCANOUT13 KBC_SCANOUT12 KBC_SCANOUT11 KBC_SCANOUT10 KBC_SCANOUT9 KBC_SCANOUT8 KBC_SCANOUT7 KBC_SCANOUT6 KBC_SCANOUT5 KBC_SCANOUT4 KBC_SCANOUT3 KBC_SCANOUT2 KBC_SCANOUT1 KBC_SCANOUT0

PLT_RST_R

SMB_CLK_EC SMB_DATA_EC

GND_SYS_CURRENT

SMC_LID VIRTUAL_BATTERY

KBC_MDE KBC_FWE KBC_PE5 KBC_PE4 KBC_PE3 KBC_PE2 KBC_PE1 KBC_PE0

PCI_RST# 22,33,34

PLT_RST# 7,19,22,25,26,39,40,57

C9W2

0.1uF

10%

.

LPC_AD0 21,39,40,44 LPC_AD1 21,39,40,44 LPC_AD2 21,39,40,44 LPC_AD3 21,39,40,44 LPC_FRAME# 21,39,40,44

CLK_PCI_KBC 38 INT_SERIRQ 23,33,40,44 PM_CLKRUN# 23,33,34,40,44 PM_SUS_STAT# 23,40,44

KBC_PROG_RX# 41

BS_CHGB# 44,51 BS_CHGA# 44,51 BS_CLR_LTCH# 44,51

ME_G3_TO_M1 55

SMC_SHUTDOWN 44,55

SATA_DET#1 23,31

BC_SHDN 51 BS_DISB# 44,51

KSC_LPC_DOCK# 40 EMA_DISP_UP 44 EMA_DISP_DOWN 44 EMA_DISP_SEL 44 EMA_DISP_ESC 44 EMA_DISP_GESC 44

R9F4 4.7KR9F4 4.7K R9F2 4.7KR9F2 4.7K R9F3 4.7KR9F3 4.7K R9F5 4.7KR9F5 4.7K R9F6 4.7KR9F6 4.7K R9F7 4.7KR9F7 4.7K

R9F8

R9F8 0

0

NO_STUFF

2

C9V1

C9W1

0.1uF

10%

.

KBC_GP_DATA 43 KBC_GP_CLK 43

KBC_MOUSE_DATA 43 KBC_MOUSE_CLK 43

KBC_KB_DATA 43 KBC_KB_CLK 43

KBC_SCANIN[7:0] 43

DOCK_PE_DET#

ND_SW#55

BIOS_REC23

If SPI Descriptor Lock is removed, a 1k Ohms resistor is required between pins 9 and 7 of J8F1

SMC_SHUTDOWN

KBC_SCANOUT[15:0] 43

R9G19 100R9G19 100

R8G14 0 NO_STUFFR8G14 0 NO_STUFF R8G9 0 NO_STUFFR8G9 0 NO_STUFF

R8G13 0R8G13 0 R8G10 0R8G10 0

+V3.3A_KBC43

LEDD1

CR9G3

CR9G3 GREEN

GREEN

1 2

LED_CAPS

3

1

2

J8F1

16 14 12 10

8 6 4 2

2X8_HDR_KEY12

PM_LAN_ENABLE_H8

R9G6

R9G7

240

LEDD2

CR9G2

CR9G1

GREEN

1 2

LED_SCROLL

Q9G3

Q9G3 BSS138

BSS138

3

Q9G2

Q9G2 BSS138

BSS138

1

2

1

SMC_LID

15 13

VIRTUAL_BATTERY

11 9 7

3 1

BUF_PLT_RST# 22,44,45

+V5A3A_MBL_PWRGD46

ATX_PWROK55

HDA_DOCK_EN# 21,27 RTC_RST# 21

1 3

CON3_HDR

EMA_CLK 44 EMA_DATA 44

SMB_CLK_ME 23,44 SMB_DATA_ME 23,44

J9F2

Boot Mode Programming Straps

P90-P92 needs to be at VCC for boot mode programming. They are already pulled up in the design. MD0, MD1 needs to be at Vss. System needs to supply +V3.3A to flash connector.

R9G4

R9G4 240

240

Mode Type

Run Mode STUFFED

LEDD3

Program Boot Block Program Flash

5,7,10,12,16..26,28,30..32,34,37..41,44,45,49,50,52,55..57

+V3.3S

1 2

LED_NUM

3

Q9G1

Q9G1 BSS138

BSS138

2

PM_LAN_ENABLE

Enable Disable 2-3

2

R9W4 10KR9W4 10K R9W2 10KR9W2 10K

R8V10 1.40K 1%R8V10 1.40K 1% R9H2 1.40K 1%R9H2 1.40K 1%

19,21,23..29,33,34,39..41,44..48,50..52,55..57

+V3.3A

R9W5 10KR9W5 10K R9V13 4.7K 5%R9V13 4.7K 5% R9V12 4.7K 5%R9V12 4.7K 5% R9W3 10KR9W3 10K R7N3 10KR7N3 10K

+V3.3M13..15,23,24,35,36,44,50,56,57

R6M2 10K 5%R6M2 10K 5%

+V3.3A 19,21,23..29,33,34,39..41,44..48,50..52,55..57

R9H12 10KR9H12 10K

SMC_LID44

J?

1-2 (Default)

PM_LAN_ENABLE

CR4W1

BAT54

LID JUMPER & SWITCH

LID OPEN (Default) LID Closed

+V3.3A 19,21,23..29,33,34,39..41,44..48,50..52,55..57

R9H14 10KR9H14 10K

VIRTUAL_BATTERY

VIRTUAL BATTERY JUMPER & SWITCH

Default Virtual Battery Mode

R9W1 0R9W1 0

13

CPU Thermal Monitor Strap

+V3.3A 19,21,23..29,33,34,39..41,44..48,50..52,55..57

R9F13 4.7KR9F13 4.7K R9F11 4.7KR9F11 4.7K

J9H6J9H6

R9F10

R9F10 0

0

1 2

NO_STUFF

Matanzas

Title

Size Document Number Rev

Date: Sheet

A

H8 2104 KBC

NDA

2

+V3.3A_KBC43

NOTE: Stuff R9F10 for write protect

Normal Operation 1-X Advanced Single Chip Mode 1-2

EC_CS_GAIN_SEL

J9H6MD2

1

MD2

MD1

MD0

0X

1

0

1

000

SMC_RUNTIME_SCI#

J9H8J9H8

1 2

19,21,23..29,33,34,39..41,44..48,50..52,55..57

+V3.3A

R9W9

R9W9 100K

100K

NO_STUFF

R9W10

100K

42 58Tuesday, December 05, 2006

1

J9H2

NMI

0 1 1

SMC_EXTSMI#

ALS_DATA ALS_CLK

SMC_WAKE_SCI#

SMB_BS_DATA SMB_BS_CLK NMI_GATE KBC_PROG_TX#

PM_LAN_ENABLE 23,35,44

J9H8 = 1-X or SW9J1 = 1-2 J9H8 = 1-2 or SW9J1 = 2-3

J9H9J9H9

1 2

J9H9 = 1-X or SW9H2 = 1-2 J9H9 = 1-2 or SW9H2 = 2-3

RSMRST#_PWRGD

Pullup = Disable Pull down = Enable

Intel Confidential

of

J9G2

(page 43)

OPEN1 STUFFED

STUFFED X

SW9J1

1

2

3

SPDT_SLIDE

SW9H2

1 3

SPDT_SLIDE

RSMRST#_PWRGD 44

2

1.5

5

+V3.3A_KBC42

3

U9V1

D D

Circuitry provides an interrupt to the SMC every 1s while in suspend (this allows the SMC to complete housekeeping functions while suspended)

VCC

GND

1

RST#

MAX809

2

SMC_RST#_D

R9V3 100

R9V1

R9V1 100K

100K

.

4

+V3.3A_KBC42

14

9 8

7

SMC_RST# 42

3

+V3.3A_KBC42

14

U9F2A

SMC_INIT_CLK1

1

Q9H2

Q9H2 BSS138

BSS138

.

R9H13 1MR9H13 1M

NMI_GATE42

C9U1

0.1uF

20%

.

U9F2D

SMC_RST SMC_INITCLK#

74HC04

3

1

2

1 2

74HC04

7

3

Q9W2

Q9W2 BSS138

BSS138

.

2

U9F2A

SMC_INIT_CLK4

J9H2J9H2

1 2

14

U9F2B

74HC04

7

R9F1 100

SMC_INIT_CLK3SMC_INIT_CLK2

C9G1

4.7uF

10%

.

R9V2

J9H2

INVD2

13 12

.

3 4

1Hz Clock

Disable Shunt Enable No Shunt (Default)

NMI Jumper NOTE: Shunt J9H2 for SMC Programming

Spare gate

2

14

5 6

74HC04

7

100K

+V3.3A_KBC42

14

7

U9F2C

U9F2F

74HC04

TP_INVD2

14

11 10

7

R9G11 100KR9G11 100K

U9F2E

SMC_INITCLK_J

74HC04

J9G2J9G2

1 2

Boot Block Programming

Normal Program

J9G2 Shunt (Default) No Shunt

1

SMC_INITCLK 42

Scan Matrix Key Board

C C

J9E1

KBC_SCANOUT1 KBC_SCANOUT0 KBC_SCANOUT3 KBC_SCANOUT5 KBC_SCANOUT7 KBC_SCANOUT9 KBC_SCANOUT11 KBC_SCANOUT10 KBC_SCANOUT13

+V3.319,27,33,41,42,44,49,56,57 +V3.3 19,27,33,41,42,44,49,56,57

+V5_PS2

.

FB1A3

.

Spare

+V5_PS2

FB1A5

60ohm@100MHz

.

+V5_PS2

27

RP1B2B

4.7K

4

5

36

RP1B1C

4.7K

KBD_DATA

C7M3

C7M3 47pF

47pF

MOUSE_DATA

CP1B1D

CP1B1D 47PF

47PF

+V5_PS2

27

C1A6

C1A6 47pF

47pF

RP1B1B

4.7K

GP_DATA

+V5_PS2 +V5 27,33,44,45,50,52,55..57

R1A1 0.002

1%

.

+V5_PS2

C1A5

C1A5 22uF

22uF

3

C1B1

0.1uF

20%

20% .

.

+V5_PS2

18

RP1B1A

4.7K

FB1A2

KBD_CLK

B B

+V5_PS2

45

RP1B1D

4.7K

GP_CLK

+V5_PS2

A A

MOUSE_CLK

18

1

CP1B1A

CP1B1A 47PF

47PF

8

FB1A7

60ohm@100MHz

2

CP1B1B

CP1B1B 47PF

47PF

7

RP1B2A

4.7K

4.7K FB1A8

FB1A8

60ohm@100MHz

3

CP1B1C

CP1B1C 47PF

47PF

6

FB1A2

60ohm@100MHz

.

L_GP_CLK L_MOUSE_CLK

.

L_PS2_PWR KBD_DATA

L_KBD_CLK

5

13 14

10 12 11

6 5

6 5 13

14 151516

10 12 11

1 2

+

PS2_PWR_L

4

17

9

F1A1

1.1A

FB1A6

31Ohm@100MHz

.

J1A1

2

1

3

16 17

8

7

DUAL_PS2

L_KBD_DATA

L_GP_DATA L_MOUSE_DATA

36

RP1B2C

FB1A4

60ohm@100MHz

45

4.7K

4.7K RP1B2D

RP1B2D

4

KBC_SCANOUT15

KBC_SCANIN1 KBC_SCANIN3 KBC_SCANIN2

KBC_SCANIN7

KBC_GP_DATA42 KBC_GP_CLK42 KBC_MOUSE_DATA42 KBC_MOUSE_CLK42 KBC_KB_DATA42

KBC_KB_CLK42

OE#_PS2

R7A1

R7A1 100

100

.

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30

2x15-SHD-HDR

3 4 7 8

11 14

17 18 21 22

1

13

SN74CBTD3384

PS2

NDA

J9E1

1A1 1A2 1A3 1A4 1A5

2A1 2A2 2A3 2A4 2A5

1OE# 2OE#

U7A1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

2

KBC_SCANOUT2 KBC_SCANOUT4 KBC_SCANOUT6 KBC_SCANOUT8

KBC_SCANOUT12 KBC_SCANOUT14

KBC_SCANIN0 KBC_SCANIN4KBC_SCANIN5

KBC_SCANIN6

CBTD has integrated diode for 5V to 3.3V voltage translation

24

VCC

2

1B1

5

1B2

6

1B3

9

1B4

10

1B5

15

2B1

16

2B2

19

2B3

20

2B4

23

2B5

12

GND

.

+V5_PS2

GP_DATA GP_CLK MOUSE_DATA MOUSE_CLK

KBD_CLK

KBC_SCANOUT[15:0] 42

KBC_SCANIN[7:0] 42

C7M4

0.1uF

20%

.

Intel Confidential

43 58Tuesday, December 05, 2006

1

1.5

of

5

+V3.3_LPCSLOT

+V3.3A19,21,23..29,33,34,39..42,45..48,50..52,55..57

+V12S 25,26,30..33,56,57

SUS_CLK23

D D

H_STPCLK#3,21

MCH_TACHO_FAN12,42

SMC_ME_ALERT23,42,55

NETDETECT#42,55

PATA_PWR_EN#23,32

LPCSLOT_B12

NO_STUFF

R7V1 0

H_RCIN#21,42

H_A20GATE21,42

SMC_EXTSMI#23,40,42,45

LPC_DRQ#140

LPC_FRAME#21,39,40,42

LPC_AD221,39,40,42 LPC_AD021,39,40,42

BUF_PLT_RST#22,42,45

CLK_REF_LPC37

STPCLK#

+V5_LPCSLOT

LPC SLOT

J8E1

B1

+V12S_1 SUSCLK_32KHZB2NC(-12V)

B3

GND1

B4

BT_WAKE

B5

+V3_3

B6

NC3

B7

GND3

B8

FWH_WP#

B9

NC4

B10

GND4

B11

IDE_SPWR_EN#

B12

NC5

B13

GND6

B14

+V3ALWAYS

B15

NC6

B16

CPU_RESET#

B17

KBC_A20_GATE

B18

GND8

B19

LSMI#

KEY

+V53 LDRQ1# LFRAME1# GND9 LAD2 LAD0 GND11 LRST# GND13 OSC_14MHZ +V3_4

60Pin_CardCon

KEY

B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30

+12VS_2

PM_DPRSLPVR

FWH_TBL#

BT_DETACH

IDE_PATA_DET IDE_SATA_DET

SERIRQ

CLKRUN#

LDRQ0#

LPCPD#

C C

Note: LPC_SLOT_B12 , H_STPCLK# and +V1.05S_CPU have been routed to LPC slot pins testing purpose.

+V3.319,27,33,41..43,49,56,57

R8F2 0.002

+V5 27,33,43,45,50,52,55..57

R8E2 0.002

B B

Decaps for LPC Slots

1%

C8F1

C8F1 22uF

22uF

1%

C8E5

C8E5 22uF

22uF

+V3.3_LPCSLOT

C8G1

0.1uF

20%

+V5_LPCSLOT

C8F2

0.1uF

20%

4

+V12S25,26,30..33,56,57

+V3.3_LPCSLOT

A1 A2 A3

GND2

A4 A5

+V3_1

A6

NC1

A7

GND5

A8 A9 A10

GND7

A11 A12 A13

+V5_1

A14

NC2

A15

GND10

A16 A17 A18

GND12

A19

NC7

A20

+V52

A21 A22

GND14

A23

LAD3

A24

LAD1

A25

GND15

A26

LCLK

A27 A28

GND16

A29

PME#

A30

+V3_2

C8E6

C8G3

0.1uF

20%

CAD NOTE: Place close to LPC Slot J8E1

+V5_LPCSLOT

+V1.05S_CPU_RSVD

PM_DPRSLPVR 7,23,52 SMB_CLK_ME 23,42 FWH_TBL# 23,39FWH_WP#23,39

SMB_DATA_ME 23,42 IDE_PATADET 23,32

R8F3 0

NO_STUFF

INT_SERIRQ 23,33,40,42 PM_CLKRUN# 23,33,34,40,42

MCH_PWM_FAN 12,42

LPC_DRQ#0 40 LPC_AD3 21,39,40,42

LPC_AD1 21,39,40,42 CLK_PCI_LPC 38

PM_SUS_STAT# 23,40,42 LPCS_PME# 40

NO_STUFF

3

+V1.05S_CPU 3,4,20,37,41,54

J7J5

VDD1

VDD1 VDD2

VDD2 RST#

RST# SCL

SCL SDA

SDA VSS

VSS

P_SAVE1

VLCD1

P_SAVE2

Molex 52746_1090

VLCD2

A05477-006

ALWAYS_ON_DISPLAY

2

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,45,49,50,52,55..57

R9M8 0.002

+V3.3A19,21,23..29,33,34,39..42,45..48,50..52,55..57 +V5

R9M8 0.002

R9A8 0.002

1%

+V3.3A_R1_TPM

CLK_PCI_TPM38

SMB_CLK_S419,23

+V3.3S_R1_TPM

C9A4

0.1uF

20%

LPC_FRAME# BUF_PLT_RST# LPC_AD3

LPC_AD0

PM_SUS_STAT#

TPM HEADER

C9A2

0.1uF

20%

J9A1

1 3 5 7

9 11 13 15 17 18 19 20

2x10-HDR_P4KEY

EMA

+V3.319,27,33,41..43,49,56,57 +V3.319,27,33,41..43,49,56,57

C7J1

0.1uF

20%

1 2 3 4 5 6 7 8 9 10

20%

PLT_GATED_RST# 19,42 EMA_CLK 42 EMA_DATA 42

PSAVE1 VLCD1 PSAVE2 VLCD2

C7J3

0.1uF

20%

C7Y1

C7Y1 1uF

1uF

20%

C7J2

0.1uF

20%

C7Y2

C7Y2 1uF

1uF

20%

J8G2

6 5 4 3 2 1

6Pin_HDR

6 5 4 3 2 1

R8V9

R8V9 10K

10K

5%

R8V11

R8V11 10K

10K

5%

1

27,33,43,45,50,52,55..57

+V5_R1_TPM

2 6

LPC_AD2

8

LPC_AD1

10 12 14

INT_SERIRQ

16

PM_CLKRUN#

R8V2

R8V2 10K

10K

5%

C9A1

0.1uF

20%

R8V15

R8V15 10K

10K

5%

R9M7 0.002

SMB_DATA_S4 19,23

TPM_DRQ#0 40

R8G3

R8G3 10K

10K

5%

1%

EMA_DISP_UP 42 EMA_DISP_DOWN 42 EMA_DISP_SEL 42 EMA_DISP_ESC 42 EMA_DISP_GESC 42

ME_SMC_ALERT# should be pulled-up to +V3.3A instead of +V3.3M. R6G17 made no-stuff & the internal pull up on the H8 is enabled.

Customer platforms need to pull this signal to +V3.3A.

LPC SIDE BAND HEADER

J9G1

PM_PWRBTN#23,42 PM_RSMRST#23,42 PM_THRM#5,12,23,42 PM_BATLOW#23,42 PM_SLP_S3#11,23,26,42,45,48,56,57 PM_S4_STATE#23,34,42,45,56,57 PM_LAN_ENABLE23,35,42

SMC_RUNTIME_SCI#23,42 SMC_WAKE_SCI#23,42 SMC_RSTGATE#42 SMC_ONOFF#42,55

A A

SMC_LID42 SMC_SHUTDOWN42,55

SMB_THRM_CLK5,12,42 SMB_THRM_DATA5,12,42 SMB_BS_CLK39,42,45,51,52 SMB_BS_DATA39,42,45,51,52 SMB_BS_ALRT#42,51

1

A1

3

A3

5

A5

7

A7

9

A9

11

A11

13

A13

15

A15

17

A17

19

A19

21

A21

23

A23

25

A25

27

A27

29

A29

31

A31

33

A33

35

A35

37

A37

39

A39

LPC Sideband Header

5

2

A2

4

A4

6

A6

8

A8

10

A10

12

A12

14

A14

16

A16

18

A18

20

A20

22

A22

24

A24

26

A26

28

A28

30

A30

32

A32

34

A34

36

A36

38

A38

40

A40

ALL_SYS_PWRGD 23,42,48 IMVP_VR_ON 42,52 CPU_PWM_FAN 5,42 CPU_TACHO_FAN 5,42

ATX_DETECT# 42,55 SMB_DATA_ME 23,42 SMB_CLK_ME 23,42

SMC_ME_ALERT 23,42,55

BC_ACOK 42,51 PM_SLP_M# 23,42,45,48,56,57

BS_CLR_LTCH# 42,51

RSMRST#_PWRGD 42

BS_CHGA# 42,51

BS_CHGB# 42,51

BS_DISA# 42,51

BS_DISB# 42,51 LAN_WOL_EN 23,42,56,57

4

+V3.3M13..15,23,24,35,36,42,50,56,57

R6G17

R6G17 10K

10K

5%

NO_STUFF

ME_SMC_ALERT# 23,42

When ME_SMC_ALERT# is asserted, indicates SUSPWRACK

When ME_SMC_ALERT# is de-asserted, indicates AC_PRESENT

3

H_NMI3,21 H_SMI#3,21 H_PWRGD3,21

PM_DPRSLPVR

Intel Confidential

44 58Thursday, November 30, 2006

1

of

PM_RI# 23,40 PM_STPCPU# 23,37 PM_STPPCI# 23,37

PCI_PME# 22,33,34 PM_SLP_M# 23,42,45,48,56,57

1.5

TP7E1NO_STUFF TP7E1NO_STUFF

J1F4

1 2 3 4 5 6 7 8

8Pin HDR

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

H_DPRSTP# 3,7,21,52 H_DPSLP# 3,21 H_CPUSLP# 3,6

LPC Slot, TPM Header, and EMA

NDA

2

TP5G2NO_STUFF TP5G2NO_STUFF TP5G1NO_STUFF TP5G1NO_STUFF

PM_CLKRUN#

TP8E1NO_STUFF TP8E1NO_STUFF TP8C1NO_STUFF TP8C1NO_STUFF TP7B1NO_STUFF TP7B1NO_STUFF

5

D D

+V3.3A19,21,23..29,33,34,39..42,44,46..48,50..52,55..57

R9P11

C C

USB_OC#922

DOCK_PE_DET#42

+V3.3A_1.5A_HDA_IO24,27,28

R9C1

R9C1 100K

100K

5%

R9P11 10K

10K

5%

CRT_DDC_CLK_DOCK16 CRT_DDC_DATA_DOCK16

B B

DOCK_PE_QSEN# DOCK_GFX_QSW

0 0

DOCK_PE_QSEN#

0 1

DOCK_CRT_TV_EN#

+V3.3A19,21,23..29,33,34,39..42,44,46..48,50..52,55..57

USB_PN922 USB_PP922

CRT_BLUE_DOCK16

CRT_GRN_DOCK16 CRT_RED_DOCK16

CRT_HSYNC_DOCK16

HDA_SDATAIN_DOCK27

LAN_LED_1000#_DOCK36

LAN_MDI2N_Q_DOCK36 LAN_MDI3P_Q_DOCK36 LAN_MDI3N_Q_DOCK36

LAN_LED_LINK#_DOCK36

Note: PE_DET# - GND in CRB, Shorted to PE_DET# in Docking Board

PM_S4_STATE#23,34,42,44,56,57

CRT_VSYNC_DOCK16

TV_DCONSEL0_DOCK18

HDA_SYNC_DOCK27 HDA_SDO_DOCK27

LAN_MDI2P_Q_DOCK36 LAN_MDI1N_Q_DOCK36

PM_SLP_S3#11,23,26,42,44,48,56,57

PM_SLP_M#23,42,44,48,56,57

PS_ON_SW#55

DOCK_SYS_PWRGD#42

GRAPHICS SELECTION 0 1

DOCK CRB CRB1X1

A A

R9R1

DOCK_GFX_QSW

R9R1 10K

10K

5%

5

U9C5

1 2

74AHC1G32

3

C9P5

0.1uF

20%

4

DOCK_CRT_TV_EN# 16,18

5

4

SMB_DATA_DOCK

Reserved

SMB_CLK_DOCK

Reserved

4

PCI-Express Docking Interface

J9C1

S1

S2

S3

S4

S5

S7

S8

S9

S10

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S43

S44

S45

S46

S47

S48

S49

S51

S52

S53

S54

S56

S57

S58

S60

S61

S62

S64

S65

S66

S67

S68

S69

S70

S71

S72

S73

S74

S75

S79

S77

S80

S85

S86

S87

S88

S89

S90

S91

S92

S93

S95

S96

S97

PCI-E DOCKING CONN

DOCK_PE_QSEN# DOCK_LAN_QSW DOCK_LAN_EN#

0 0

DOCK_LAN_QSW

S100 S101 S103 S104 S105 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S119 S120 S121 S122 S127 S128 S129 S130 S131 S132 S133 S135 S136 S137 S139 S140 S141 S143 S144 S145 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S161 S162 S163 S164

M84

M126

S99

P1 P2 P3 P4

G1 G2 G3 G4 G5 G6 G7 G8

G9 G10 G11 G12

0 1

S99 S100 S101 S103 S104 S105 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S119 S120 S121 S122 S127 S128 S129 S130 S131 S132 S133 S135 S136 S137 S139 S140 S141 S143 S144 S145 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S161 S162 S163 S164

M84 M126

P1 P2 P3 P4

G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12

R9P1

R9P1 10K

10K

5%

PCIE_WAKE#_DOCK DOCK_PWR_EN#

HDA_SPKR_DOCK

PE_OPNREQ# DOCK_PE_PWRGD#

SMI#_DOCK

0 1

+V3.3A19,21,23..29,33,34,39..42,44,46..48,50..52,55..57

1 2

5

3

LAN_LED_ACT#_DOCK 36 LAN_MDI1P_Q_DOCK 36

SATA_RXP2_DOCK 21 SATA_RXN2_DOCK 21

SATA_TXP2_DOCK 21 SATA_TXN2_DOCK 21

RSTBTNDB 55

LAN_MDI0N_Q_DOCK 36 LAN_MDI0P_Q_DOCK 36

+VAC_IN_L42,51

NOTE: Power pins rated at 7A per pin.

LAN SELECTION

DOCK CRB CRBX11

U9C1

4

74AHC1G32

3

CLK_REQ#_DOCK 38 PCIE_TXP1_DOCK 22 PCIE_TXN2_DOCK 22

PCIE_TXP2_DOCK 22 PCIE_RXN2_DOCK 22

PCIE_RXP2_DOCK 22 TV_DCONSEL1_DOCK 18 HDA_DOCK_RST# 21,27

PCIE_TXN1_DOCK 22

PCIE_RXN1_DOCK 22

PCIE_RXP1_DOCK 22 TV_DACA_OUT_DOCK 18 TV_DACB_OUT_DOCK 18

TV_DACC_OUT_DOCK 18

HDA_BCLK_DOCK 27

LAN_LED_100#_DOCK 36

CLK_PCIE_DOCK 38

CLK_PCIE_DOCK# 38

C9P1

0.1uF

20%

DOCK_LAN_EN# 23,36

R9D6 0

NO_STUFF

+V1.8_VCT_LAN_DOCK36

SMB_BS_CLK39,42,44,51,52 SMB_BS_DATA39,42,44,51,52

2

HDA_SPKR 23,27

DOCK_PERST#

R9P8 1KR9P8 1K R9P7 0R9P7 0 R9P6 0R9P6 0

+V3.3A19,21,23..29,33,34,39..42,44,46..48,50..52,55..57

R9P4 10KR9P4 10K R9P9 10KR9P9 10K R9P3 10KR9P3 10K

+V3.3A19,21,23..29,33,34,39..42,44,46..48,50..52,55..57

R9P2

R9P2 10K

10K

5%

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,44,49,50,52,55..57

53

U9D1

4

74AHC1G08

+V3.3A19,21,23..29,33,34,39..42,44,46..48,50..52,55..57 +V3.3A19,21,23..29,33,34,39..42,44,46..48,50..52,55..57

C9P3

0.1uF

20%

U9C3

16

VDD

RESET#

8

VSS

1

SCLK

2

SDATA

DOCK_A0

3

A0

DOCK_A1

4

A1

DOCK_A2

5

A2

PCA9557PW

1 2

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

DOCK_PWR_EN# DOCK_PE_PWRGD#

PE_OPNREQ# 42

C9R2

0.1uF

20%

DOCK_PE_RST#

DOCK_PCA9557_RST#

15 6

7 9 10 11 12 13 14

DOCK_PE_RST#

BUF_PLT_RST# 22,42,44

DOCK_PWR_EN# DOCK_PE_PWRGD# DOCK_PE_RST#

DOCK_PE_QSEN# DOCK_GFX_QSW DOCK_LAN_QSW

1

8-bit I/O Port Expander - Slave address 32h

slave address

0 0 1 1 A2 A1 A0 R/W

fixed

programmable

PCA9557 Address

SMB_CLK_A123,25,26,33,34 SMB_DATA_A123,25,26,33,34

PCIE_WAKE#19,23,25,26

+V3.3A19,21,23..29,33,34,39..42,44,46..48,50..52,55..57

R9P10

R9P10 10K

10K

5%

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

SMC_EXTSMI#23,40,42,44

Docking

NDA 1.5

TP_1A5 TP_2A1

TP_2A2 TP_2A4

TP_2A5

3

1A1

4

1A2

7

1A3

8

1A4

11

1A5

14

2A1

17

2A2

18

2A3

21

2A4

22

2A5

1

1OE#

13

2OE#

SN74CBTD3384

2

+V5 27,33,43,44,50,52,55..57

C9P4

0.1uF

20%

U9C4

24

VCC

2

1B1

5

1B2

6

1B3

9

1B4

10

1B5

15

2B1

16

2B2

19

2B3

20

2B4

23

2B5

12

GND

45 58Tuesday, December 05, 2006

SMB_CLK_DOCK SMB_DATA_DOCK PCIE_WAKE#_DOCK SMI#_DOCK TP_1B5

TP_2B1TP_2A3 TP_2B2 TP_2B3 TP_2B4 TP_2B5

Intel Confidential

of

1

R9P5

R9P5 1K

1K

5%

5

+V5A_MBL 55

C3H9

C3H9 1000pF

1000pF

R3W12

5%

40.2K

1%

D D

C C

R3H12

R3H12 10K

10K

1%

AGND_51120

+V5_LDO_FILT

+V5_LDO_FILT_RC2

AGND_51120

VR_ALW_ENABLE28,55

+V5_LDO_FILT_RC1

AGND_51120

R3H70R3H7 0

R3W7

30.1K

1%

1% NO_STUFF

NO_STUFF

C3W2

C3W2 470pF

470pF

5%

5% NO_STUFF

NO_STUFF

R3W140R3W14 0

R3H13

9.76k_1%

NO_STUFF

C3W5

C3W5 2200PF

2200PF

NO_STUFF

C3H4

C3H4 100pF

5%

100pF

5% NO_STUFF

NO_STUFF

B B

R3Y3

3.3V_EV

R3Y3 0NO_STUFF

0NO_STUFF

VREF2

C3W4

C3W4 1000pF

1000pF

5%

AGND_51120

C3H10

C3H10 470pF

470pF

5%

5% NO_STUFF

NO_STUFF

R3H11 0

R3H9 0

NO_STUFF

R3H4

R3H4 100K

100K

+V5A3A_MBL_PWRGD42

AGND_51120

+V3.3A_MBL 55

R3H10

23.7K

1%

R3W9

R3W9 10K

10K

1%

AGND_51120

+V5A_MBL55

NO_STUFF

51120_VFB2

51120_COMP2

+V5_LDO

C3W3

C3W3 1000pF

1000pF

5%

VREF2

R3W150R3W15 0

R3W16

R3W16 0

0

NO_STUFF

AGND_51120

51120_COMP1 51120_VFB1

VREF2

+V3.3A_MBL55

NO_STUFF

AGND_51120

51120_SKIPSEL

EU3H1

1 2 3 4 5 6 7 8

R3W30R3W3 0

A A

5

4

R3H170R3H17 0

R3H16

R3H16 0

0

31

32

SKIPSEL VO1 COMP1 VFB1 VREF2 GND VFB2 COMP2 VO2

EN59EN310PGOOD211EN2

+V5_LDO_EN3

VR_ALW_ENABLE_R

R3H30R3H3 0

R3W6

10K

5%

PROGRAMMING TABLE

SKIPSEL COMP TONSEL(CH1/2) VFB1 VFB2 EN1,EN2 EN3,EN5

4

3

R3W11

V5A_MBL_PWRGD

+V3_LDO

R3H19

R3H19 10K

10K

5%

51120_EN1

51120_TONSEL

TONSEL

TPS51120

51120_DRVH1_R

C3H11

0.47uF

51120_VBST1

30

28

27

29

26

EN1

VBST1

DRVH1

PGOOD1

VBST213DRVH214LL215DRVL2

12

51120DRVH2

51120VBST2

C3H3

0.47uF

51120_VR_ALW_ENABLE

+V3.3A 19,21,23..29,33,34,39..42,44,45,47,48,50..52,55..57

AGND

AUTO-SKIP N/A 380KHz/590KHz N/A N/A SWITCHER OFF LDO OFF

AGND_51120

51120_+V5A_MBL_Q

51120_DRVL1_Q

25

TH

LL1

DRVL1

PGND1

CS1

VIN VREG5 V5FILT VREG3

CS2

PGND2

16

51120VBST2_Q

51120_DRVL2_Q

C3H2

0.1uF

10%

10% NO_STUFF

NO_STUFF

AGND_51120

VREF2

AUTO-SKIP FAULTS OFF N/A 290KHz/440KHz SHOULD NOT BE USED SHOULD NOT BE USED SHOULD NOT BE USED SHOULD NOT BE USED

R2H4

R2H4 0

0

Q3H4

NO_STUFF

.

2

R3H18

R3H18 100K

100K

1

51120_DRVH1_Q

R3H150R3H15 0

33

AGND_51120

24

51120_CS1_R

23 22 21 20 19

51120_CS2_R

18 17

R3H60R3H6 0

567

4

R3W40R3W4 0

R3W5 0

NO_STUFF

Note: RC network for manually adjusting soft start delay

R3W11 0

0

NO_STUFF

3

BSS138

VR_ALW_ENABLE 28,55

567

4

R3W13

1 2

R3W8

12.4K

1%

567

51120DRVH2_RQ

4

312

8

Q3H1

Q3H1 IRF7822

IRF7822

312

FLOAT

PWM FAULTS OFF N/A 220KHz/330KHz N/A N/A N/A N/A

+V5A3A_MBL_PWRGD

51120_EN1_C

C3W6

0.1uF

10%

10% NO_STUFF

NO_STUFF

AGND_51120

567

8

4

312

8

Q3H5

Q3H5 IRF7822

IRF7822

312

+V3_LDO

10.7K

1%

51120DRVH2_+VBATA_Q

8

Q3H2

Q3H2 IRF7811A

IRF7811A

1 2

CR3G4

B320A

2 1

V5A_MBL_PWRGD

+V3_LDO

+V5_LDO_FILTPIN

PWM D-CAP MODE 180KHz/280KHz 5V FIXED OUTPUT

3.3V FIXED OUTPUT SWITCHER ON LDO ON

Q3H6

Q3H6 IRF7811A

IRF7811A

B320A

3

R3W170R3W17 0

51120_DRVH1_+VBATA

L3H1

1 2

3.3uH

CR3H1

2 1

C3H6

C3H6 10uF

10uF

20%

AGND_51120

51120VBST2_LR

L3G1

3.3uH

2

R3H140R3H14

+V3_LDO

+VBATA 26,47,48,55,57

R3H20

0.002

1%

C3H13

0.1uF

10%

51120_+V5A_MBL_QL

+V5_LDO_FILT

R3W10

49.9

1%

C3H7

1.0uF

20%

20% 402

402

1%

C3H1

C3H1 22uF

22uF

R3G3

0.002

1%

V5 Output Mode Selection

Fixed Output Mode

V5 Mode Selection

Current Mode D_CAP Mode (default)

Title

Size Document Number Rev

Date: Sheet

1%

C3H12

C3H12 22uF

22uF

R3J1 0.002

1%

+VBATA26,47,48,55,57

C3H8

0.1uF

10%

C3H5

C3H5 10uF

10uF

20%

R3H5

0.002

1%

C3G5

0.1uF

10%

Matanzas

A

1%

C4H1

0.1uF

10%

+

TPS51120 System Power

NDA 1.5

0

AGND_51120

12

+

C4Y2

0.1uF

10%

+V5_LDO

+VBATA 26,47,48,55,57

+V3.3A_MBL 55

Icc-max=15A OCP=18A

C4G10

C3G4

+

330uF

20%

C3H9, R3W12 & R3H12

STUFF

R3W14

R3H13, C3H10 & C3W5

NO_STUFF STUFF

STUFF NO_STUFF

C3Y1

C3Y1 220uF

220uF

10%

10% NO_STUFF

NO_STUFF

R3H11

STUFFNO_STUFF NO_STUFFAdjustable Mode (default)

+V5A_MBL 55

Icc-max=12A OCP=15A

12

+

C3J1

+

C3J1 220uF

220uF

10%

V3.3 Output Mode Selection

Fixed Output Mode Adjustable Mode (default)

V3.3 Mode Selection

Current Mode D_CAP Mode (default)

2

1

C3W3, R3H10 & R3W9

NO_STUFF STUFF

R3H7

NO_STUFF STUFF

46 58Tuesday, November 21, 2006

1

R3H9

STUFF NO_STUFF

R3W7, C3H4 & C3W2

STUFF NO_STUFF

Intel Confidential

of

5

Discharge Selection

Tracking Discharge (Default) Non-tracking Discharge

D D

+V0.9 14,15,56

R4B13

0.002

1%

1% .

.

R4A6

AGND_DDR

C C

R4A6 0

0

NO_STUFF

M_VREF_MCH7,50

Layout Note: C4N4, R4N4 & RR4B12 shoud be place close to chipset.

R4B1

R4B1 0

0

.

+V1.8_EVMC_V_CNTL

R4B1

STUFF NO_STUFF

DDR_MODE_P2_HDR

+V1.89,10,13,14,50,56

R4A6

NO_STUFF STUFF

+V0.9_R

C4B7

C4B7 10uF

10uF

25V

R4B12

R4B12 0

0

.

DDR_VTTREF_RC

C4N4

0.033uF

5%

5% .

.

R4N4

R4N4 0 .

0 .

C4N3

C4N3 10uF

10uF

25V

Mode Selection

Current Mode D_CAP Mode (default)

+V1.89,10,13,14,50,56

C4B5

C4B5 10uF

10uF

25V

+V5A_FILT

R4B11

R4B11 0

0

.

R4B10

2.05K

1%

1% NO_STUFF

NO_STUFF

DDR_COMP_RC2

C4N5

0.01uF

10%

10% NO_STUFF

NO_STUFF

AGND_DDR

NO_STUFF

+V1.8

DDR_VTTREF_R

DDR_COMP_RC

C4B4

C4B4 1000pF

1000pF

10%

NO_STUFF

+V1.8

+V1.8_EVMC_V_CNTL_R

R4B8

R4B8 0

0

R4B11 R4B10, C4N5 & C4B4

NO_STUFF STUFF

C4B3

C4B3 1uF

1uF

20%

20% .

.

1 2 3 4 5 6

B B

DDR_VDDQSNS_P3_HDR

R4B3

R4B3 0

0

NO_STUFF

VDDQSET

VOUT 1.8V (Default) VOUT 1.5V

R4B6 R4B3

NO_STUFF

STUFF NO_STUFF

STUFF

DDR_VDDQSET_P2_HDR

R4B6 10

EU4B1

VTTGND VTTSNS GND MODE VTTREF COMP

4

NO_STUFFSTUFF

DDR2 VREG

C4N2

0.1uF

.

DDR_LX2

5%

.

+V5A24,29,40,42,48,51,55,57

0.1uF

10%16V

.

5%

DDR_LDR2_RC

C4B1

C4B1 1uF

1uF

20%

20% .

.

PM_SLP_S4# 23,56

.

CS

DDR_LDR2

DDR_VBST_RC

5%

DDR_DRVH_R

18 17 16 15 14 13

25

AGND_DDR

R4B4 0

R4B2 0

DDR_CS_RC

DDR_PGGOD_RU

+V5A24,29,40,42,48,51,55,57

R4B7 0

DDR_VBST_R

21

19

20

23

22

24

LL

VTT

VBST

DRVL

DRVH

PGND

VLDOIN

CS_GND

V5IN

TPS51116

V5FILT

PGOOD

THRM

NC212S511S3

VDDQSNS

NC1

VDDQSET

8

7

9

10

R4B9

R4B9 10

10

5%

5% .

.

R4N3

R4N3 75K

75K

1%

R4N2

R4N2 75K

75K

1%

AGND_DDR

5%

.

DDR_DRVH_RQ

+V5A_FILT

3

1.8_VIN

C5B3

C4B6

10uF

25V

L4B1

1.0uH

25V

1 2

25V

567

8

Q4B1

Q4B1 IRF7811A

567

C4N1

C4N1 1000pF

1000pF

5%

.

IRF7811A

.

312

1 2

8

Q4A1

Q4A1 IRF7822

IRF7822

.

312

C4B2

C4B2 1uF

1uF

20%

20% .

.

AGND_DDR

R4A5

R4A5 10K

10K

5%

5% .

.

2 1

R4M8

5.90K

R4A7 10

PM_SYS_PWRGD50

5130_PWRGD48

VRPWRGD_3.3M_R50

CR4B1

CR4B1 MBR0530

MBR0530

.

Note: OCP set point at 14A

.5%

+V3.3A19,21,23..29,33,34,39..42,44..46,48,50..52,55..57

4

C4N6

C4N6 10uF

10uF

U4M2

U4A3

+V3.3A19,21,23..29,33,34,39..42,44..46,48,50..52,55..57

NO_STUFF

+V5A24,29,40,42,48,51,55,57

53

74AHC1G08

53

74AHC1G08

2

TP5B1

4

.

4

.

+VBATA26,46,48,55,57

C5B1

C5B1 330uF

330uF

20%

2.5V

2.5V NO_STUFF

NO_STUFF

PM_PWROK 48

19,21,23..29,33,34,39..42,44..46,48,50..52,55..57

5130_DDR_PWRGD

C4A8

0.1uF

10%16V

.

C4M5

0.1uF

10%16V

.

R5N13

0.002

1%

1% .

.

+V1.89,10,13,14,50,56

Vout = 1.8/1.5V V Iout = 10A

C5N7

0.1uF

10%

.

. 16V

16V

+V3.3A

U4A4

1 2

Adds 3.3M to the MPWROK tree. Needed to support G3->M1 and Moff to M1 transitions.

53

74AHC1G08

C4A7

0.1uF

10%16V

.

4

.

1

R4A4

R4A4 0

0

.

MPWROK 7,23

AGND_DDR

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

DDR2 VR

NDA 1.5

A

NDA 1.5

A

NDA 1.5

A

2

47 58Tuesday, December 05, 2006

1

Intel Confidential

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5

+V1.5S 4,10,11,24,28,56

EV_VCC_V1.5S

D D

+V1.05S 4,9,10,24,56

EV_VCC_V1.05S

10,37,56,57

+V1.25M

EV_VCC_V1.25M

C C

R4G13 332

R5G10

R4V10 332

R4G5

Refdes

R4V5 R4G3

R5G12 332

R5V12

R5V6 0

1%

.

0

.

R5V10 0

NO_STUFF

1%

1% .

.

0

.

R4V9 0

NO_STUFF

1.25V

4.87K 10K

B B

PM_SLP_S3#11,23,26,42,44,45,56,57

PM_SLP_M#23,42,44,45,56,57

A A

IMVP pulls 5130 PWRGD down to 1.3V via IMVP internal bleed path back to S-rails when in sub S0 states. Buffer needed to isolate 5130 PWRGD from IMVP6 controller. Needed for ME.

V1.5RC

1%

.

EV_VCC_V1.5S_R

0

.

NO_STUFF

C4G9

C4G9 5600pF

5ONG

AGND_5130

53

74AHC1G08

1

R5G13

R5G13 100K

100K

.

R5V5

2.37K

1%

1% .

.

R4V5

4.87K.1%

C4G7

0.1uF

10%16V

.

4

+V5REF

5600pF

AGND_5130

1.05ONG

R4V21

R4V21 0

0

.

5130_PWRGD_AND

V_EV_GMCH_RC

EV_VCC_V1.05S_R

V1.25M_RC

EV_VCC_V1.25M_R

1.5V

10.7K

13.7K

R4G15

R4G15 0

0

.

+V3.3A 19,21,23..29,33,34,39..42,44..47,50..52,55..57

U4G3

1 2

AGND_5130

R5G22

R5G22 10K

10K

5%

5% .

.

4N1_5ON

3

2

1 2

R5G4

R5G4 10K

10K

1%

1% .

.

C4G4

C4G4 5600pF

5600pF

R4G3

R4G3 10K

10K

1%

1% .

.

AGND_5130

1

Q4V2

Q4V2 BSS138

BSS138

.

1

AGND_5130

R5G9

10.7K

1%

AGND_5130

V_EV_GMCH_INV

C4V5

C4V5 3300pF

3300pF

V1.25M_INV

C4V3

C4V3 3300pF

3300pF

AGND_5130

+V5REF

R4G16

R4G16 100K

100K

AGND_5130

R4G17

R4G17 100K

100K

AGND_5130

R4G6

10K 5%

V1.5S_INV

C5G10

C5G10 5600pF

5600pF

R5G7

13.7K

1%

1% .

.

V_EV_GMCH_FBRC

V1.25M_FBRC

+VBATA26,46,47,55,57

3

Q5G5

Q5G5 BSS138

BSS138

.

2

R5V14

R5V14 10K

10K

5%

5% .

.

1

4N1_1.05ON

3

Q4G9

Q4G9 BSS138

BSS138

.

2

1.5_1.05_PWRGD_R 52

C5G8

C5G8 3300pF

3300pF

R4V6 2.49K

AGND_5130

5

V1.5S_FBRC

R4G7

2.49K

1%

1% .

.

1%

.

R4G10 10K

R4G10 10K R4G12 10K

R4G12 10K

AGND_5130

3

Q5V1

Q5V1 BSS138

BSS138

.

2

4

R5G3

V1.5S_FB

2.49K

1%

1% .

.

V_EV_GMCH_FB

+V5REF

R4G9

R4G9 0

+V1.25M_FB

.

. .

.

0

.

R4G11

R4G11 0

0

NO_STUFF

AGND_5130

C5V3

0.01uF

.

. 10%

10%

R4V7

R4V7 100

100

5%

5% .

.

1

19,21,23..29,33,34,39..42,44..47,50..52,55..57

PM_PWROK47

4

V1.5S_TG

CR5V3

2 1

MBR0530

+V5REF

1

3

V_EV_GMCH_INV V_EV_GMCH_FB

+V1.05S_VRON

5130VREFON

5130VREFON_3

C4G8

0.1uF

C5V4

0.01uF

10%

.

. 10%

10%

LDO_VRON

+V5REF

R4G14

R4G14 10K

10K

5%

V1.25M_ON_INV

.

1

3

Q4W1

BSS138

.

2

AGND_5130

+V3.3A 19,21,23..29,33,34,39..42,44..47,50..52,55..57

R4V13

R4V13 10K

10K

5%

5% .

.

5130_PWRGD 47

.

CR5V4

CR5V4 BAT54

BAT54

AGND_5130

V1.5S_FB

V1.5_VRON

5130PWMSEL

5130CT

C4G5

C4G5 33pF

33pF

5%

5% .

.

3

2

AGND_5130

+V3.3A

U4G2

1 2

C5G4

0.1uF

10%

.

V1.5S_BST

R5G2

V1.5S_INV

1 2 3 4 5 6 7 8

5130REF

9 10 11 12

R4V14

0

V1.25M_VRON

.

Q4G6

Q4G6 BSS138

BSS138

.

53

74AHC1G08

.

R5G1

R5G1 0

0

.

2.2

5%

.

C5G5

0.01uF

10%

.

4N1_FLT

V1.5S_TG_R

4N1_LH1

45

47

48

46

FLT

LH1

INV1 FB1 SS_STBY1 INV2 FB2 SS_STBY2

TPS5130PT

PWM_SEL CT

4 IN 1

GND

Controller

REF STBY_VREF5 STBY_VREF3_3 STBY_LDO

SS_STBY3

TPS5130PT

13

14

V1.25M_SS

+V1.25M_FB

C4G6

0.01uF

10%

.

AGND_5130

5130_PWRGD

C4V6

0.1uF

10%16V

.

4

5130_PWRGD used to generate M_PWROK to chipset.

1.5_1.05_PWRGD_R used to as PGD_IN (pin2) to IMVP.

3

6

2

V1.5S_SW

1

5

Q5G2B

Q5G2B Si7904DN

Si7904DN

4

3

R5V2 10K

C5V1

0.1uF

10%

.

R5V1 10K

C5G2

0.1uF

10%

.

V1.5S_BG

43

OUT1_D

PGOUT

16

C4V2

0.1uF

10%

V1.5SOCP

42

41

OUTGND1

PG_DELAY

17

18

5130PGDELAY

V1.25M_OCP

.

TRIP1

TRIP3

MCH_ICH_CORE_BG

MCH_ICH_CORE_OCP

37

38

39

40

TRIP2

OUT2_D

OUT2_U

OUTGND2

VIN_SENSE12

VREF3.3

VREF5

REG5V_IN

LDO_VIN

LDO_CUR

LDO_GATE

LDO_OUT

INV_LDO

LH3

OUT3_U

VIN_SENSE3

LL322OUTGND324OUT3_D

20

21

19

23

V1.25MBG

5130LH3

V1.25MSW

R4G2

2.2

V1.25MTG

5%

5% .

.

V1.25MBST

R4V3

R4V3 10K

10K

1%

1% .

.

V1.5S_SW

44

LL1

OUT1_U

FB3

INV3

15

V1.25M_INV

C4G3

0.01uF

10%

.

This is system power good representing power good for all rails from the Crestline VR.

ALL_SYS_PWRGD 23,42,44

3

V1.5S_VIN

Q5G2A

Q5G2A Si7904DN

Si7904DN

1%

.

U4G1

LL2 LH2

VIN

C4V1

0.1uF

10%

.

+VBATA 26,46,47,55,57

B320A

1%

36 35 34 33 32 31 30 29 28 27 26 25

1 2

CR5V2

2 1

+VBATA26,46,47,55,57

5130_OUT2

VGMCH_SW

5130LH2 5130VIN 3VREF 5VREF 5130REG5V

V1.05G

1.05M_EV_R

CR4V1

MBR0530

2 1

CR4G1

C5G6

0.1uF

10%

10% .

.

L5G1

3.3uH

.

V1.05SNS-

R4U2

5.11K

1%

AGND_5130

.

BAT54

2

+VBATA26,46,47,55,57

R5V3 0.002

1%

C5G7

.

22uF

R5G23

V1.5S_SW_L

.

R5F19

R5F19 0

0

.

2

CR5V1

21

MBR0530

C5U6 0.1uF

.

10%

.

R5U29

V1.25M_VIN

R4G1

13

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

VGMCH_BST

2.2

.

R5F18

1 2

C4U6

C4U6 1000pF

1000pF

10%

.

R4F15 1.21K

C4G1

0.1uF

C4G2

10%

22uF

.

V1.25M_TG

4

0

.

78

Q4F3A

Q4F3A IRF9910

IRF9910

2

1

+V5REF

1.05M_EV_R

Crestline VR

NDA 1.5

0.002

1%

12

+

4

5130_OUT2_R

78

Q5G1A

Q5G1A IRF9910

IRF9910

1

CR5U1

CR5U1 BAT54

BAT54

1

1 2

5%

5% .

.

1%

C4F3

C4F3 1000pFNO_STUFF10%

1000pFNO_STUFF10%

3

R4F16 0

NO_STUFF

2

C5G1

C5G1 220uF

220uF

10%

10% .

.

13

R4V4

0.002

1%

56

.

CR4F2

B320A

Q4F3B

Q4F3B IRF9910

IRF9910

2 1

+V1.5S

+V1.5S4,10,11,24,28,56

56

Q5G1B

Q5G1B IRF9910

IRF9910

3

CR5G1

B320A

+V5REF

R4V1

R4V1 1

1

5%

5% .

.

R4F14

2.2

5%

5% .

.

+VBATA26,46,47,55,57

1 2

C5G3

0.1uF

10%

10% .

.

2 1

L4F1

3.3uH

.

C5F10

0.1uF

10%

10% .

.

1 2

L5F4

3.3uH

.

+V3REF

+V5REF

4N1_1.25MG

1.05M_EV

NO_STUFF

+V5A24,29,40,42,47,51,55,57

1

3

+V1.25M_OUT

C5F8

C5F8 22uF

22uF

R5F17

1.00

.

VGMCH_IN

TP5F1

C5F12

C5F12 270uF

270uF

20%

20% .

.

652

4

V1.05OUT

R5F16 0.002

GMCH & ICH Core Rails

C5F9

0.1uF

10%

10% .

.

C5F13

0.1uF

C5G9

10%

22UF

.

C4U7

0.22uF

10%

10% .

.

C4U2

C4U2 1000pF

1000pF

10%

NO_STUFF

R4F12

0.050

Q4F2

Q4F2 SI3442BDV

SI3442BDV

R4V2

0.002

1%

+

.

1

R4G8

R4G8 0

0

AGND_5130

.

+VBATA26,46,47,55,57

1%

.

+V1.05S4,9,10,24,56

C5U5

C5U5 270uF

270uF

20%

20% .

.

+VBATA26,46,47,55,57

R5V4

1.00

.

+V5REF

C5V2

C5V2 10uF

10uF

10%

10% .

.

+V1.05M LDO

+V1.05M9,56

R4F13

0.01

+V1.25M10,37,56,57

C4F1

C4U4

+

330uF

20%

.

+V1.25M

Intel Confidential

48 58Tuesday, December 05, 2006

of

1

+V3REF

C4F2

0.1uF

10%

10% .

.

+V1.25M10,37,56,57

C4U5

0.1uF

10%

10% .

.

C5F11

C5F11 10uF

10uF

10%

10% .

.

C4U1

C4U1 10uF

10uF

10%

10% .

.

12

+

C4U3

C4U3 100uF

100uF

5

R3U7 0R3U7 0

R3V1 0R3V1 0

GND_GVR

D D

GFX_VR_PWRIN52

C C

AGND_VCORE

Connect Power ground to Controller ground under the controller

C2G1

0.1uF

10%

+V5S5,11,12,16..18,24,30..32,34,41,50,52,53,55..57

GND_GVR

4

5,7,10,12,16..26,28,30..32,34,37..42,44,45,50,52,55..57

GVR_POUT

R2G3

10K5%

.

5,7,10,12,16..26,28,30..32,34,37..42,44,45,50,52,55..57

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,44,45,50,52,55..57

R2G7

10K

5%

GVR_PGDLY

+V5S_GVR

.

GVR_VR_EN

IMVP Graphics Controller

GVR_VID0

GVR_VID1

GVR_CSN

+V3.3S

GVR_VID2

GVR_VID3

GVR_CSP

R3G10

R3G10 20K

20K

.

. 1%

1%

GVR_VID4

+V3.3S

GND_GVR

R3G14

30.1K

1%

1% .

.

R2G16

R2G16 100K

100K

GVR_BST GVR_DRVH_G GVR_SW_PHASE

GVR_DRVL_G

3

GVR_VCC

GND_GVR

19,27,33,41..44,56,57

+V5S

R3F12

0.002

1%

1% .

.

12

R3F11

R3F11 10

10

5%

5% .

.

C3F7

1.0uF

20%

20% 402

402

GND_GVR

R3G10R3G1

GVR_BST_R

0

C3U1

1.0uF

20%

20% 402

402

0.22uF

C3G1

2

+VBAT17,53,55..57

R3V2

R3V2 .002

.002

5%

C3V2

C3V1

0.01uF

10%

10% 402

402

C3V3

C3V3 47uF

47uF

20%

Q3U2

HAT2164H

C3G2

C3G2 47uF

47uF

20%

NO_STUFF

C3V1

0.01uF

10%

10% 402

402

B320A

2 1

CR3G1

C3V6

4.7uF

20%

R3F6

3.57K

1%

1% .

.

C3V5

4.7uF

20%

1 2

R3F5

1.78k

L3F1

0.88uH

C3V7

C3V8

0.01uF

10%

402

GVR_VBAT

NO_STUFF

D

Q3V1

G

HAT2168H

4

S

2 531

D

G

4

S

2 531

C3V4

C3V4 47uF

47uF

20%

Q3U3

Q3U3 HAT2164H

HAT2164H

C3G3

C3G3 47uF

47uF

20%

D

G

4

S

2 531

NO_STUFF

GVR_VID0

GVR_VID1

GVR_VID2

GVR_VID4

GVR_NTC

1

R3G13

.

R3G12

.

R3G11

.

R3G9

.

RT3F11KRT3F1

1 2

1K

20K

1%

20K

1%

20K

1%

20K

1%

+VCC_GFXCORE9

C3F5

0.1uF

C3F3

0.01uF

10%

.402

.402 25V

25V

0.1uF

10%

.

Intel Confidential

49 58Tuesday, December 05, 2006

1

Intel Confidential

1.5

of

Matanzas

Title

Size Document Number Rev

Date: Sheet

Graphics Core VR

NDA

A

NDA

A

NDA

A

2

C3F4

0.22uF

S2Input

1 1 1 1

0.22uF

GND_GVR

S1DS0

1

0 1

1 11 1

0

3

R3F9 0R3F9 0

J2G1J2G1

+V5S5,11,12,16..18,24,30..32,34,41,50,52,53,55..57

R2G10 8.2KR2G10 8.2K

246

13579

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,44,45,50,52,55..57

Output

C

A

CB A B

D

R2F8 8.2KR2F8 8.2K

R2G6 8.2KR2G6 8.2K

R2G9 8.2KR2G9 8.2K

8

R2G8 8.2KR2G8 8.2K

GVR_STRAP_VID0 GVR_STRAP_VID1 GVR_STRAP_VID2 GVR_STRAP_VID3 GVR_STRAP_VID4

GVR_STRAP_EXTRA

101214

16

111315

GVR_V5_S0

+V5S5,11,12,16..18,24,30..32,34,41,50,52,53,55..57

R2G2 8.2KR2G2 8.2K

R3G2 0R3G2 0

DFGT_VID_07 DFGT_VID_17

GND_GVR

DFGT_VID_27 DFGT_VID_37

DFGT_VR_EN7

R2G11 10KR2G11 10K

R2F7 8.2KR2F7 8.2K

DFGT_XTRA_VID

GVR_S2_S1

R2F6 8.2KR2F6 8.2K

U2V1

2

A0

5

A1

8

A2

11

A3

13

A4

16

A5

18

A6

21

A7

23

A8

3

B0

6

B1

9

B2

12

B3

14

B4

17

B5

19

B6

22

B7

24

B8

1

S0

48

S1 S247GND1

34

GND5

39

GND6

42

GND7

74CBT16209A

VCC

GND0 GND2

GND3 GND4

GVR_VID0

46

C0

GVR_VID1

44

C1

GVR_VID2

41

C2

GVR_VID3

38

C3

GVR_VID4

36

C4

GVR_VR_ENGVR_STRAP_VR_EN

33

C5

31

C6

28

C7

26

C8

45

D0

43

D1

40

D2

37

D3

35

D4

32

D5

30

D6

5,11,12,16..18,24,30..32,34,41,50,52,53,55..57

27

D7

+V5S

25

D8

7 4 10

C2V2

15

.01uF

20

20%

29

4

B B

A A

5

4

3

2

1

+V3.3A19,21,23..29,33,34,39..42,44..48,51,52,55..57

+V3.3M13..15,23,24,35,36,42,44,56,57

+V5S5,11,12,16..18,24,30..32,34,41,49,52,53,55..57

D D

VRPWRGD_3.3M_R47

Adds 3.3M to the MPWROK tree.

R4W13

24.9K

1%

1% .

.

R4W11

R4W11 10K

10K

1%

1% .

.

R4W10

R4W10 13K

13K

1%

+V5S_PWRGD +V1.5A_PWRGD

R4W9

R4W9 10K

10K

1%

1% .

.

R4W8

R4W8 100K

100K

C4W1

0.1uF

10%

.

R4W12

R4W12 100K

100K

U4H1

1

OUTB

2

OUTA

3

V+

4

INA-

5

INA+

6

INB-

7

INB+

8

REF

LTC1444

PP_REFIN

VREF = 1.221V

OUTC OUTD

HYST

IND+ INC+

INDINC-

PM_SYS_PWRGD 47

16 15

PP_HYST

14

+V2.5S_PWRGD

13 12

+V3.3S_PWRGD

11 10 9

V-

R4W7

R4W7 10K

10K

5%

5% .

.

R4W1

2.4M

.

+V3.3S_TVDAC10,11,56

R4W3

R4W3 13K

13K

1%

NO_STUFF

TP4H1

R4W5

R4W5 10K

10K

1%

1% .

.

C C

+V527,33,43..45,52,55..57

+V1.89,10,13,14,47,56

R3N13

R3N13 10K

R3B13

R3B13 10K

10K

1%

1% .

.

10K

1%

1% .

.

C3B5

C3B5 220pF

220pF

10%

.

B B

M_VREF_DIMM_B

+V5 27,33,43..45,52,55..57

+V527,33,43..45,52,55..57

VDD+

2

-

3

+

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,44,45,49,52,55..57

+V527,33,43..45,52,55..57

10

VDD+

U3B1A

U3B1A TLV2463

R4W2

R4W2 13K

13K

1%

R4W4

R4W4 10K

10K

1%

1% .

.

M_VREF_MCH_A

+V527,33,43..45,52,55..57

R3B18

R3B18 10K

10K

5%

5% NO_STUFF

10

U3B2A

U3B2A TLV2463

TLV2463

VREF_DIMM1_MARG

1

OPAMP2_SHTDN#

5

GND

4

NO_STUFF

R3N17

R3N17 10K

10K

5%

5% .

.

NO_STUFF

R3N11

R3N11 0

0

UNUSED_BUF_U6A1A_P2

R3N5

R3N5 0

0

.

UNUSED_BUF_U6A1A_P1

+V1.89,10,13,14,47,56

R3N4

R3N4 0

0

.

R3B6

R3B6 10K

10K

1%

1% .

.

R3N3

R3N3 10K

10K

1%

1% .

.

2

3

UNUSED_BUF_U6A1A_P3

R4N1

R4N1 0

0

.

C3N2

C3N2 220pF

220pF

10%

.

TLV2463

-

+

1

OPAMP4_SHTDN#

5

GND

4

+V527,33,43..45,52,55..57

C3N1

0.1uF

10%

.

10

VDD+

U3B1B

8

-

7

+

GND

4

TLV2463

VREF_MCH_MARG

9

OPAMP3_SHTDN#

6

R3B7

R3B7 10K

10K

5%

5% NO_STUFF

NO_STUFF

R4B5

R4B5 10K

10K

5%

5% .

.

+V527,33,43..45,52,55..57

R3N2

R3N2 10K

10K

5%

5% NO_STUFF

NO_STUFF

R3B4

R3B4 10K

10K

5%

5% .

.

R3N1

R3N1 0

0

NO_STUFF

M_VREF_MCH 7,47

C3N4

0.1uF

10%

.

+V1.89,10,13,14,47,56

R3N15

R3N15 10K

10K

1%

1% .

M_VREF_DIMM_A

A A

.

R3B15

R3B15 10K

10K

1%

1% .

.

C3N6

C3N6 220pF

220pF

10%

.

VDD+

8

-

7

+

.

10

U3B2B

U3B2B TLV2463

TLV2463

VREF_DIMM0_MARG

9

OPAMP1_SHTDN#

6

GND

4

5

R3N16

R3N16 10K

10K

5%

5% NO_STUFF

NO_STUFF

R3N9 0

NO_STUFF

R3B16

R3B16 10K

10K

5%

5% .

.

4

R6P1

R6P1 0

0

.

M_VREF_DIMM0 13

M_VREF_DIMM1 14

Intel Confidential

50 58Tuesday, December 05, 2006

1

Intel Confidential

of

Matanzas

Title

Size Document Number Rev

Date: Sheet

3

Date: Sheet

DDR2 VREF

NDA 1.5

A

NDA 1.5

A

NDA 1.5

A

2

5

4

3

2

1

+VBS55

R3G7 10K

.

BC_ACOK_BATT55

+V3.3A19,21,23..29,33,34,39..42,44..48,50,52,55..57

R2G12 10K

+VBC_LDO

BC_BATT

BC_SHDN42

R2G15

R2G15 130K

130K

5%

5% .

.

R2W11

R3H1

45.3K

49.9K

1%

.

C2W7

R2W10

49.9K

0.01uF

1%

10%

.

.402

+VBC_REF+VBC_LDO

C2H4

C2H4 1uF

1uF

10%

10% .

.

1 2 3

BC_THERMB

4 5

CHGB

6

DISB#

7

NO_STUFF

NO_STUFF NO_STUFF

NO_STUFF

Battery Address Key

Address

14 16 18 1A 1C 1E 20 22

1 2 3

BC_THERMA

4 5

CHGA

6

DISA#

7

U1H7

1

SHDN# RS-2VCC

3

RS+

4

GND

MAX4072

EC_CS_GAIN_SEL42

Current Sense Range

0 - 3A: EN_CS_GAIN_SEL = 3.3V 0-6A EN_CS_GAIN_SEL = 0V

BC_ACOK42,44

.

R3W2 10K

.

1

R3H2

R3H2 100K

100K

5%

5% .

.

AGND_BC

+VBC_REF

R2V16

37.4k_1%

R3V4

49.9K

1%

1% .

.

AGND_BC AGND_BC

SMB_BS_CLK 39,42,44,45,52 SMB_BS_DATA 39,42,44,45,52

R1W2 100KR1W2 100K R1H1 10K

R1H1 10K

BC_THERMB

R1W5 6.81K

BC_THERMA

R1W17 1.74K

Host Resistor

820 1800 2700 3900 4700

9100 11000

SMB_BS_CLK 39,42,44,45,52 SMB_BS_DATA 39,42,44,45,52

R1W16 100KR1W16 100K R1H5 10K

R1H5 10K

8

GSEL

7

MAX4072_OUT MAX4072_OUT_RC

6

OUT

MAX4072_REFIN

5

RFIN

C1H3

0.1uF

10%

.

. 16V

16V

D D

+VBC_LDO

R3G5

41.2K

1%

1% .

.

CR3G3

1 3

BAT54

BC_REFIN_D

R3G6

C2H1

49.9K

0.1uF

1%

20%

.

16V

AGND_BC

C C

C2H3

4.7uF

80%

80% .

.

16V

AGND_BC AGND_BC

J1G7

1 2 3

Batt B

4 5 6 7

CON_1X7_156mil_HDR

19,21,23..29,33,34,39..42,44..48,50,52,55..57

B B

A A

+V3.3A

R1W3 0

R1W3 0 R1W14 0

R1W14 0

SMBUS Address for Battery B = 1E

SMBUS Address for Battery A = 16

J1H1

1 2 3

Batt A

4 5 6 7

CON_1X7_156mil_HDR

System Current Sense Amp (6A Dynamic Range)

(Place close to the sense resistor near the brick connector)

R1G10

R1G10 1K

1K

1%

POS_SENSE POS_SENSE_A +VAC_IN_L +VAC_IN_L_A

C1G2

R1G8

0.1uF

C1G1

1K

10%

.

0.1uF

1%

.

10%

GND_SYS_CURRENT

5

3

Q2G4

Q2G4 BSS138

BSS138

1

.

2

3

Q2G5

Q2G5 BSS138

BSS138

1

.

2

+VBC_LDO

3

Q3H3

Q3H3 BSS138

BSS138

.

2

BC_ICHG

R3W1

C2V11

20K

0.01uF

10%

10% .402

.402

BC_IINP

R2W9

24.9K

1%

1% .

.

1%

1% 1%

1%

.

. .

.

Total (Host + 200)

1020 2000 2900 4100 4900 70006800 9300 11200

5%

5% .

.

+VREF_ADC42

R1W18

R1W18 22

22

5%

5% .

.

R1W19 20KR1W19 20K

C1W12

0.1uF

C1W14

C1W14 22UF

22UF

10%

10% .

.

Rsense for total system current (10mV/A).

POS_SENSE

R1G9

R1G9 .01

.01

1%

R2V9 10K

C2V5 0.1uF

R2V10 10K

AGND_BC

+VBC_LDO

R2V14 10K

C3W1

0.1uF

10%

.

. 16V

16V

BC_CCV_C

C2W8

0.1uF

10%

.

. 16V

16V

AGND_BC AGND_BC AGND_BC

AGND_BC

C1W11

C1W11 1uF

1uF

20%

20% .

.

L1G1

1k@100MHz

4A, 50V, DCresist=12mohm-1 line-

**

*

**

*

CAD Note: Place VIAs inside the sense resistor pads. Cannot be in the current flow path. Use Kelvin sense layout.

C1V2

C1V1

22uF

0.1uF

20%

10%

25V

.

1%R2V9 10K

1%

NO_STUFF

20% NO_STUFF16V

1%R2V10 10K

1%

NO_STUFF

+VBC_REF

5%

.

R2W3

R2W7

25.5K

0

1%

1% .

.

BC_CCI_C

C2W5

C2W6

0.1uF

0.022uF

0.1uF

10%

.

402

.

16V

5

+

6

-

GND_SYS_CURRENT

23 14

CR2V1

1 3

BAT54

EU2W1

BC_CELLS

17

CELLS

BC_ACOK#

11

ACOK#

BC_SHDN#

8

SHDN#

BC_REFIN

12

REFIN

4

REF

BC_CLS

3

CLS

BC_VCTL

15

VCTL

BC_ICTL

13

ICTL

BC_ICHG

9

ICHG

BC_IINP

28

IINP

BC_CCV

7

CCV

BC_CCI

6

CCI

BC_CCS

5

CCS

R2W6

MAX8724

178

1%

1 2

BC_CCS_C

C2W4

C2W4 220pF

220pF

10%

.

+V3.3A19,21,23..29,33,34,39..42,44..48,50,52,55..57

+V5A 24,29,40,42,47,48,55,57

8

U1W1B

7

AD8552

4

R1H20R1H2

0

4

+VCHGR_OUT

C1H2

C1H2 10UF

10UF

25V

5

U1H1

74AHC1G02

3

53

U1H2

74AHC1G08

5

U1H4

74AHC1G02

3

53

U1H5

74AHC1G08

EC_BRK_CURRENT 42

AGND_BC

C1H1

C1H1 10UF

10UF

25V

1 2

.

1 2

.

*

4

VAC_BRCK_IN

R2W1 6.65K

GND

GND2

14

29

*

CAD Note: System current groud trace needs to be 20 mil or larger going from the brick to the EC and MAX4072 current sense amp.

2

1%

.

BC_DCIN

C2G5

C2G5 1uF

1uF

10%

10% .

.

AGND_BC

1

DCIN

BC_ACIN

10

ACIN

2

LDO

BC_DLOV

22

DLOV

BC_BST

24

BST

BC_DHI

25

DHI

BC_LX

23

LX

BC_DLO

21

DLO

20

PGND

BC_CSIP

19

CSIP

BC_CSIN

18

CSIN

BC_CSSP

27

CSSP

BC_CSSN

26

CSSN

BC_BATT

16

BATT

R3G8

R3G8 0

0

.

** *

CAD Note: Place VIA close to each sense resistor pad

R1W4 10K

BS_CHGB# 42,44

.

BS_DISB# 42,44

R1W8 100KR1W8 100K

R1W12 10K

BS_CHGA# 42,44 BS_CLR_LTCH# 42,44

.

BS_DISA# 42,44

R1W11 100KR1W11 100K

H8 ADC Reference

(Place very close to the EC)

3.0V Precision ADC Reference circuit

J1G6

3

SHUNT

+AC_INPUT

1

GND

AC_JACK

BRCK_IN_GND

R2W2 1K

1%

.

AGND_BC

+VBC_LDO

R2G13 33

5%

R2V17 0

R2V17 0 R2G14 0

R2G14 0

R2V15 0

.

C2W1

0.1uF

10%

10% .

.

R2W4

R2V13

10_1%

0

.

R1W15

0.020

+V3.3A19,21,23..29,33,34,39..42,44..48,50,52,55..57

C1W6

0.1uF

10%

.

. 16V

16V

FLIPFLOP_Q

FLIPFLOP_Q#

19,21,23..29,33,34,39..42,44..48,50,52,55..57

+V5A 24,29,40,42,47,48,55,57

R9H4

R9H4 475

475

1%

1% .

.

1

LM4040

LM4040 U9H1

U9H1

2

GND_SYS_CURRENT

BRCK_IN_GND

C2G6 1uF.80%

16V

AGND_BC

CR2G3

.

1 3

BAT54

BC_BST_R

C1W9

0.1uF

10%

.

. 16V

16V

R2V12

R2V12 10_1%

10_1%

C2V10

0.1uF

10%

10% .

.

*

C1W1

0.1uF

10%

.

. 16V

16V

PRE_L

U1H6

8

VCC

7

PRE#

6

CLR#

5

Q

1G D-FLIP FLOP

BC_DHI_R

BC_DLO_R

R2V11

R2V11 10_1%

10_1%

R2H5 0.005

GND

+V3.3A

1%

C1W2

0.1uF

10%

.

. 16V

16V

CLK

Q#

R2W5

R2W5 10_1%

10_1%

.

. .

.

3.3V ADC reference

The precision ADC and and 3.3 ADC reference optons are mutually exclusive. DO NOT STUFF BOTH AT THE SAME TIME OR THE PRECISION REFERNCE COULD BE DAMAGED.

3

+VAC_IN_L42,45

*

R1W13

R1W13 1K

1K

5%

D

R9H3

R9H3 0

0

NO_STUFF

MAX8724 Set Points Table

ACOK# trip point with AC adapter = ~15.6V Battery Charging Current (Vcls) = ~2.1A Charging Voltage (Vvctl) = 12.6V

C2G4

C2G4 22uF

22uF

20%

20% 25V

25V

.

D

S

2 531

C2J1

C2J1 22uF

22uF

20%.25V

MAX809 Trip Point = 2.93V VBS Trip Point = 8.7V

2

Q2H2

Q2H2 HAT2168H

HAT2168H

NO_STUFF

CELLS -> Floating -> 3 cells

Discontinuous Mode -> Imin = 0.75A Continuous - Conduction Mode

9.3V < Vbatt < 11.088V

REF Voltage = 4.096V LDO Voltage = 5.4V

3

Q2J2

Q2J2 BSS138

BSS138

.

2

BC_CSIP

C2V9 0.1uF

10%

.

C2V8 0.1uF C2W3 0.1uF

C2W3 0.1uF C2W2 0.1uF

C2W2 0.1uF C2V7 0.1uF

C2V7 0.1uF

VBS_DIV

3

VCC

GND

1

. 10%

10%

.

. 10%

10%

.

. 10%

10%

.

. 10%

10%

.

+VBS55

R1H6

24.3K

1%

1% .

.

R1H4

12.4K

1%

1% .

.

BC_CSIN BC_CSSP BC_CSSN BC_BATT

C2W10

C2W10 10UF

10UF

25V

U1H3

2

RST#

MAX809

AGND_BC

J2Y1

BC_SHDN

+VCHGR_OUT

51 58Tuesday, December 05, 2006

J2Y1

2

1

4

3

6

5

+VCHGR_OUT

8

7 9

10

11

12

13

14

15

16 17 18 19 20

2221

2x11-PLG

NO_STUFF

Intel Confidential

of

1

VCHRM 42

PSYS 42

+VBS

1

16VC2V9 0.1uF

16V 16VC2V8 0.1uF

16V 16V

16V

AGND_BC

C1W7

0.1uF

10%

.

. 16V

16V

ACOK

ICHRM42

PBATT42

R2J1

R2J1 100K

100K

1%

1% .

.

+VBS

CR1V1

2 1

RB081L-20

.

Q2G6

3 2

5

1

SI7483ADP

R1V2

4

100K

1%

1% .

.

ACOK#_R

R1V1

R1V1 100K

100K

1%

1% .

.

C2H2

0.1uF

10%

10% .

.

D

G

4

S

2 531

C1W4

0.1uF

10%

.

. 16V

16V

1 2 3 4

Q1G1

Q1G1 HAT2164H

HAT2164H

VBS_TRIP

C9H1

C9H1 22UF

22UF

SMB_BS_ALRT#42,44

+V_BC_OUT

+VREF_ADC42

C1W8

0.1uF

10%

.

. 16V

16V

C9H2

0.1uF

10%

10% .

.

G

4

S

C2G3

C2G3 22uF

22uF

C1V3

20%

0.1uF

25V

10%

.

D

G

Q2H1

4

HAT2168H

S

2 531

D

Q2H3

Q2H3 HAT2164H

HAT2164H

2 1

NO_STUFF

2 531

C2H5

C2H5 47uF

47uF

20%

.

R1H3

R1H3 10K

10K

5%

5% .

.

3

Q1H2

Q1H2 BSS138

BSS138

1

.

2

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

+VAC_IN

C2V6

C2G2

22uF

20%

25V

.

BC_ACOK#

G

4

CR2W1

CR2W1 MBRS130LT3

MBRS130LT3

.

12

L2H1

3.3uH

13A

.

C2H7

C2J3

47uF

0.1uF

20%

10%

.

+V3.3A19,21,23..29,33,34,39..42,44..48,50,52,55..57

R1W1

R1W1 10K

10K

5%

5% .

.

3

Q1H1

Q1H1 BSS138

BSS138

VBS_TRIP#

1

.

2

Crestline VR

NDA 1.5

5

3

CPU VCC_Core VR and MUX Buffer

D D

H_DPRSTP#3,7,21,44,60

VR_VID641 VR_VID541 VR_VID441 VR_VID341 VR_VID241 VR_VID141 VR_VID041

TP1C1

NO_STUFF

VCCSENSE4 VSSSENSE4

NO_STUFF

R2N18 0

AGND_VCORE

PM_DPRSLPVR7,23,44 PSI#3

J2B1

1 2

NO_STUFF

R2N6

27.4

Place near Controller

Layout Note: Use

27.4 Ohm routing for Vssense and Vccsense

5%

.

C C

B B

A A

1.5_1.05_PWRGD_R48

VR_PWRGD_CLKEN#23 DELAY_VR_PWRGOOD7,23

C2N7

0.01uF

10%

10% .402

.402

R2M2

27.4

NO_STUFF

Power Monitoring VCORE Signal

5

R2N23 499

PM_DPRSLPVR_IMVP6

1%

.

IMVP_VR_ON42,44

R2N19 49.9K

1%

R2N20 49.9K

.

1%

.

SPR_GT_5 SPR_GT_6

IMVP Controller

R2N15 49.9K

8

U2B1B

5

+

7

6

-

AD8552

4

AGND_VCORE

R2N21 49.9K

OP_CPU_ICC_R

.

4

LAYOUT NOTE: PLACE Q2C5 AS CLOSE TO Q2C4 AS POSSIBLE

Q2C5

1

GND1

2

GND2

3

HYST

MAX6501

Temperature Monitor

PWM1 53

ISEN1 53

PWM2 53

ISEN2 53

FCCM 53

R2N7

7.5K

1%

1% .

.

6260_VO_R

C2N3

0.1uF

10%

10% NO_STUFF

AGND_VCORE

NO_STUFF

6260_DROOP

1%

.

1%

AGND_VCORE

4

R2N4 7.5K

R2N4 7.5K R2B6 15K

R2B6 15K

.

. .

.

TOVER#

VCC

1%

6260_DROOP_R

1%

AGND_VCORE

3

5 4

6260_VO_RR

R2N14

R2N14 402K

402K

1%

1% .

.

3

2 3

C2N4

0.1uF

10%

10% 16V

16V

NO_STUFF

H_PROCHOT# 3

C2C8

2.2uF

10%

.

R2B3

R2B3 402K

402K

1%

1% .

.

AGND_VCORE

4

U2B1A

-

1

+

AD8552

8

OP_CPU_ICC_R

C2B7

0.1uF

10%

.

. 16V

16V

AGND_VCORE

+V5S5,11,12,16..18,24,30..32,34,41,49,50,53,55..57

C2C9

0.1uF

10%

.

10V

SMB_BS_DATA39,42,44,45,51

SMB_BS_CLK39,42,44,45,51

GAIN ADJUSTED FOR 27

+V3.3S 5,7,10,12,16..26,28,30..32,34,37..42,44,45,49,50,55..57+V5S5,11,12,16..18,24,30..32,34,41,49,50,53,55..57

R1N19

R1N7

8.2K

15

J2B2.J2B2

101214

16

.

AGND_VCORE

+V5 27,33,43..45,50,55..57

R2B8

R2B8 10_1%

10_1%

Matanzas

Title

Size Document Number Rev

Date: Sheet

IMVP-6

NDA

A

2

R1N5

R1N11

R1N14

R1N9

8.2K

IMVP-4STRAP_VID0 IMVP-4STRAP_VID1 IMVP-4STRAP_VID2 IMVP-4STRAP_VID3 IMVP-4STRAP_VID4 IMVP-4STRAP_VID5 IMVP-4STRAP_VID6

135791113

H_VID04,59 H_VID14,59

246

8

V5_S0

+V5S5,11,12,16..18,24,30..32,34,41,49,50,53,55..57

C1B3

0.1uF

10%

10% .

.

CPU_ICC

CPU_VCC

H_VID24,59 H_VID34,59 H_VID44,59 H_VID54,59 H_VID64,59

R1N20

R1N20 10K

10K

5%

5% .

.

+V3.3A 19,21,23..29,33,34,39..42,44..48,50,51,55..57

R1P1

R1P1 10K

10K

5%

5% .

.

TP_OTI

GFX_VR_PWRIN49

CPU_ICC_R

CPU_VCC_R

R1B3

R1B3 100

100

1%

1% .

.

R1B2

R1B2 100

100

1%

1% .

.

2

R1N3

8.2K

S2_S1

U1N1

1 2 3 4 5 6 7 8

AD7417

AGND_VCORE

R1N1

8.2K

NC1 SDA SCL OTI REF_IN GND A_IN1 A_IN2

R1N27

R1N27 0

0

5%

5% .

.

C1B2

0.1uF

10%

10% .

.

2 5

8 11 13 16 18 21 23

3

6

9 12 14 17 19 22 24

1 48

34 39 42

U1B2

A0 A1 A2 A3 A4 A5 A6 A7 A8

B0 B1 B2 B3 B4 B5 B6 B7 B8

S0 S1 S247GND1 GND5 GND6 GND7

74CBT16209A

GFX_VR_PWRIN_R

AGND_VCORE

GND0 GND2

GND3 GND4

CONVST#

A_IN4 A_IN3

C1N3

0.1uF

10%

10% .

.

VCC

NC2 VDD

C0 C1 C2 C3 C4 C5 C6 C7 C8

D0 D1 D2 D3 D4 D5 D6 D7 D8

A0 A1 A2

46 44 41 38 36 33 31 28 26

45 43 40 37 35 32 30 27 25

7 4 10 15 20 29

+V3.3A19,21,23..29,33,34,39..42,44..48,50,51,55..57

16 15 14 13 12 11 10 9

.

AD7417_A0 AD7417_A1 AD7417_A2

R1N44

R1N44 10K

10K

5%

5% .

.

1

Input

Output A B

B

VR_VID0 41 VR_VID1 41 VR_VID2 41 VR_VID3 41 VR_VID4 41 VR_VID5 41 VR_VID6 41

5,11,12,16..18,24,30..32,34,41,49,50,53,55..57

C1N2

C1N2 .01uF

.01uF

20%

20% .

.

CONVST# AD7417_A0

AD7417_A1 AD7417_A2

AGND_VCORE

19,21,23..29,33,34,39..42,44..48,50,51,55..57

+V3.3A

NO_STUFF

AGND_VCORE AGND_VCORE AGND_VCORE

SMBUS address: 100

52 58Wednesday, November 29, 2006

1

S1

S2

S0

1

C C DA D

R1N39

R1N39 10K

10K

5%

NO_STUFF

R1N30

R1N30 10K

10K

5%

5% .

.

NO_STUFF

R1N31

R1N31 10K

10K

5%

Intel Confidential

of

0

1

101

C1N5

0.1uF

10%

.

AGND_VCORE AGND_VCORE

R1N34

R1N45

10K

5%

5% NO_STUFF

NO_STUFF

R1N40

R1N35

10K

5%

.

1.5

+V5S

+V3.3A 19,21,23..29,33,

C1N6

C1N6 10uF

10uF

20%

.

5

4

3

2

1

+VDC_PHASE52

R2P12 .002

D

S

D

2 531

+VDC_PHASE52

G

D

2 531

R2P12 .002

D

Q3C2

Q3C2 HAT2168H

HAT2168H

2 531

Q3C3

Q3C3 HAT2164H

HAT2164H

NO_STUFF

D

Q2P2

Q2P2 HAT2168H

HAT2168H

2 531

Q2P1

Q2P1 HAT2164H

HAT2164H

NO_STUFF

D

S

2 531

Q2C1

Q2C1 HAT2164H

HAT2164H

5% 1W

.

C3C2

0.01uF

10%

.402

.402 25V

25V

6208_1_PHASE_U3B3

2 1

+VDC_PHASE52

C2C1

C2C1 47uF

47uF

20%

.

. 16V

16V

6208_2_PHASE

CR2C2

B320A

2 1

C1C4

0.01uF

10%

10% .402

.402 25V

25V

Q1C1

Q1C1 HAT2168H

HAT2168H

NO_STUFF

CR2C1

1 2

B320A

2 1

R3B25

R3B25 0

0

+V5S_IMVP6 52

C2B15

C2B15 1uF

D D

FCCM52

Phase1

PWM152

FCCM

C C

Phase2

PWM3

B B

1uF

10%

.

IMVP Driver

+V5S_IMVP652

R2B20

R2B20 0

0

.

FCCM_R

IMVP Driver

R2B11

R2B11 0

0

NO_STUFF

+V5S_IMVP6 52

FCCM52

Phase3

PWM252

A A

5

C2B13

C2B13 1uF

1uF

10%

.

6208_1_BOOT_U3B3

R2P6

R2P6 0

0

.

6208_2_BOOT_U2C2

C2C2

C2C2 1uF

1uF

10%

.

IMVP Driver

C3B8

0.22uF

10%

6208_1_LGATE

6208_2_UGATE

6208_2_LGATE

R1B4

R1B4 0

0

.

6208_3_BOOT_U2C1

6208_3_PHASE

6208_3_LGATE

6208_1_BOOT_U3B3_R

G

4

.

6208_2_BOOT_U2C2_R

C2P1

0.22uF

10%

10% .

.

6208_3_BOOT_U2C1_R

6208_3_UGATE

6208_1_UGATE

D

S

2 531

G

4

S

C2C6

0.01uF

10%

10% .402

.402 25V

25V

G

4

S

G

4

C1B5

0.22uF

10%

10% .

.

G

4

Q3C4

Q3C4 HAT2168H

HAT2168H

D

2 531

C2C3

0.01uF

10%

.402

.402 25V

25V

D

2 531

S

G

4

S

4

Q3C5

Q3C5 HAT2164H

HAT2164H

Q2C3

Q2C3 HAT2168H

HAT2168H

D

Q2C4

Q2C4 HAT2164H

HAT2164H

2 531

D

S

2 531

D

Q2C2

Q2C2 HAT2164H

HAT2164H

2 531

NO_STUFF

G

4

C2C5

0.01uF

10%

.402

.402 25V

25V

NO_STUFF

G

4

Q1C2

Q1C2 HAT2168H

HAT2168H

G

4

NO_STUFF

4

G

S

VCC_PRM52

S

2 531

C2C4

0.01uF

10%

10% .402

.402 25V

25V

G

4

S

4

S

VSUM52

ISEN252

+VBAT 17,49,55..57 +V5S5,11,12,16..18,24,30..32,34,41,49,50,52,55..57

C3C7

C3C3

0.01uF

10%

10% .402

.402 25V

25V

CR3C1

CR3C1 B320A

B320A

C2P2

C2P2 47uF

47uF

20%

.

. 16V

16V

R2P5

76.8K

1%

C3C7

0.01uF

.402

.402 25V

25V

10%

C3C6

0.01uF

10%

.402

.402 25V

25V

12

R2N24

76.8K

1%

C2C7

4.7uF

20%

.

12

R2P11

76.8K

1%

C1C5

0.01uF

10%

10% .402

.402 25V

25V

C1C2

0.01uF

10%

.402

.402 25V

25V

L2C2 0.45uH

12

R2P7

10.7K

1%

DCR3_RC

C2N10

0.22uF

.10%

R2P4 0

NO_STUFF

Place near Controller

3

20%

12

C3P2

12

R2N30

10.7K

1%

R2P10

10.7K

1%

C1C3

0.01uF

10%

10% .402

.402 25V

25V

R2N29

R2N29 0

0

.

C3P2 47uF

47uF

20%

.

. 16V

16V

C3P1

C3P1 47uF

47uF

20%

.

. 16V

16V

NO_STUFF

L3C1

6208_1_PHASE_LOUT

0.45uH

20%

C2N9

DCR1_RC

0.22uF

10%

10% .

.

L2C1

0.45uH

20%

C2N8

0.22uF

10%

10% .

.

C1P2

C1P2 47uF

47uF

20%

.

. 16V

16V

R2P8

R2P8 10_1%

10_1%

Matanzas

Title

Size Document Number Rev

Date: Sheet

6208_2_PHASE_LOUT

DCR2_RC

R2P2

R2P2 0NO_STUFF

0NO_STUFF

C1P1

C1P1 47uF

47uF

20%

.

. 16V

16V

6208_3_PHASE_LOUT

IMVP-6 Core VR

NDA 1.5

A

NDA 1.5

A

NDA 1.5

A

C3C5

C3C5 47uF

47uF

20%

20% 16V

16V

R2P3

R2P3 0NO_STUFF

0NO_STUFF

NO_STUFF

R2N28

R2N28 0

0

.

R2N25

R2N25 0

0

.

C1C1

C1C1 47uF

47uF

20%

20% 16V

16V

NO_STUFF

2

C1B6

C3C1

C3C1 47uF

47uF

20%

20% 16V

16V

R2P1

R2P1 10_1%

10_1%

R2P9

R2P9 10_1%

10_1%

C1B6

4.7uF

20%

.

Place near Controller

C1C6

C1C6 47uF

47uF

20%

20% 16V

16V NO_STUFF

NO_STUFF

R1B1 .002

C3B10

4.7uF

20%

.

R3D1

R3D1 .002

.002

5%

5% .

.

VCC_PRM 52

ISEN1 52 VSUM 52

R2D1

R2D1 .002

.002

5%

5% .

.

VCC_PRM 52

ISEN3 52 VSUM 52

C3B11

4.7uF

20%

.

R2D2

R2D2 .002

.002

5%

5% .

.

5% 1W

5% 1W .

.

+VCC_CORE4,54,56

C1B4

4.7uF

20%

.

+V5S_IMVP6 52

LAYOUT NOTES:

Place R2N24 & R2N30 right next to each other. Route a single trace from the input pad of the inductor and T at the resistors. --> Do not use plane flood. This applies for R2P11 & R2P10 and R2P5 & R2P7 as well.

Place CR3C1 near Q3C4 and Q3C5. Route sharing the ground and switch nodes with low side FETs. This applies for CR2C1 and CR2C2 as well.

Place the 0402 caps near the drain of the high side FETs for each phase.

Intel Confidential

of

53 58Wednesday, November 29, 2006

1

5

4

3

2

1

Vccp Core Decoupling

+V1.05S_CPU3,4,20,37,41,44

Place these inside socket

C3T2

0.1uF

10%

.

C2T2

0.1uF

10%

.

C2T4

0.1uF

10%

.

C2T5

0.1uF

10%

.

C2T3

0.1uF

10%

.

cavity on L8 ( North side

C2T1

Secondary)

0.1uF

10%

.

D D

Vcc Core Decoupling

+VCC_CORE4,53,56

Place these inside socket cavity on L8 ( North side Secondary)

C2R2

C2R2 10uF

10uF

20%

.

C2R13

C2R13 10uF

10uF

20%

.

C2R12

C2R12 10uF

10uF

20%

.

C2R11

C2R11 10uF

10uF

20%

.

C2R10

C2R10 10uF

10uF

20%

.

C2R9

C2R9 10uF

10uF

20%

.

C2R8

C2R8 10uF

10uF

20%

.

C2R7

C2R7 10uF

10uF

20%

.

C2R6

C2R6 10uF

10uF

20%

.

C2R1

C2R1 10uF

10uF

20%

.

Place these inside socket cavity on L8 ( South side Secondary)

Place these inside socket cavity on L1 ( North side

C C

Primary)

Place these inside socket cavity on L1 ( South side Primary)

South Side Secondary

C2T18

C2T18 10uF

10uF

20%

.

C2T14

C2T14 330uF

330uF

10%

10% .

.

C2T13

C2T13 10uF

10uF

20%

.

C2D1

C2D1 10uF

10uF

20%

.

C2E1

C2E1 10uF

10uF

20%

.

C2T12

C2T12 10uF

10uF

20%

.

C2D2

C2D2 10uF

10uF

20%

.

C2E2

C2E2 10uF

10uF

20%

.

C2T16

C2T16 330uF

330uF

10%

10% .

.

C2T11

C2T11 10uF

10uF

20%

.

C2D3

C2D3 10uF

10uF

20%

.

C2E3

C2E3 10uF

10uF

20%

.

C2T15

C2T15 330uF

330uF

10%

10% NO_STUFF

NO_STUFF

C2T10

C2T10 10uF

10uF

20%

.

C2D4

C2D4 10uF

10uF

20%

.

C2E4

C2E4 10uF

10uF

20%

.

C2T9

C2T9 10uF

10uF

20%

.

C2D5

C2D5 10uF

10uF

20%

.

C2E5

C2E5 10uF

10uF

20%

.

C2R3

C2R3 330uF

330uF

10%

10% .

.

C2T8

C2T8 10uF

10uF

20%

.

C2D6

C2D6 10uF

10uF

20%

.

C2E6

C2E6 10uF

10uF

20%

.

C2T7

C2T7 10uF

10uF

20%

.

C2R4

C2R4 330uF

330uF

10%

NO_STUFF

C2R5

C2R5 330uF

330uF

10%

10% .

.

C2T6

C2T17

10uF

20%

.

North Side Secondary

B B

A A

5

4

3

Matanzas

Title

Size Document Number Rev

Date: Sheet

CPU Decoupling

NDA 1.5

A

NDA 1.5

A

NDA 1.5

A

2

Intel Confidential

54 58Tuesday, November 21, 2006

1

of

5

8

Q4J1

7

3

+V5A_MBL46 +V5A 24,29,40,42,47,48,51,57

+VBATA26,46..48,57

D D

+V5SB_ATXA

R4V11 0

+V3.3A_MBL

Q4G10

IRF7811A

C C

MOBILE OPTION

PS_LATCH#

CR4W2

CR4W2 BAT54A

BAT54A

PS_ON_SW#

3 2 1

.

4

R3V3 100KR3V3 100K

R4V12

R4V12 1K

1K

5%

8 7

Q4V3

6

.

IRF7811A

5

8 7 6

.

5

1

3

2

B B

ME_G3_TO_M142

+V5SB_ATX

R5H18

R5H18 10K

10K

5%

A A

5% .

.

+V5_DL_Q

5V MIN CURRENT DUMMY LOAD: Gives

0.5A min current load

1

3

2 1

3 2 1

ATXPWR

19,21,23..29,33,34,39..42,44..48,50..52,56,57

+V3.3A

BC_ACOK_BATT

Active High: When AC brick present charger starts and asserts this signal, which starts the on board always rails by forcing the assertion on VR_ALW_ENABLE assuming ATX_PWR_CNTRL is asserted. Ignored by H8 in ATX mode.

PS_ON#

PS_ON# internally pulled up to 5V standby in all ATX supply per ATX 12V spec.

+V5SB_ATX

R4W24

R4W24 200K

200K

1%

1% .

.

ME_G3_TO_M1_JUMP

J4H1J4H1

1 2

1

R4W25

R4W25 392K

392K

1%

1% .

.

5V_DL

R5J1 3.0

652

Q5Y1

Q5Y1 SI3442BDV

SI3442BDV

4

+

3

2

1

C4H5

C4H5 220uF

220uF

10%

10% .

.

Q4W6

Q4W6 BSS138

BSS138

.

6 5

8 7 6 5

+

BC_ACOK_BATT51

ATX ALWAYS ON DT OPTION

R4W20

R4W20 1K

1K

NO_STUFF

NO_STUFF 5%

5%

.

IRF7811A

.

Q3Y1

Q3Y1 IRF7811A

IRF7811A

.

3

Q4G2

Q4G2 BSS138

BSS138

.

2

C4H2

C4H2 220uF

220uF

10%

10% .

.

PS_ON#

R4W23

1 2

0

NO_STUFF

+V5_ATX

5V_DL_R

R5W14

3.0

5%

5% .

.

12

C5H2

+

220uF

10%

10% .

.

C4V4

0.1uF

10%

10% .

.

+V3.3_ATX

R2H2

R2H3

R2H3 100K

100K

NO_STUFF

SHUTDWN#

Active High: Goes high on pwr button press turing on the on board always rails in battery mode. Forces VR_ALW_ENABLE high when ATX_PWR_CNTRL is high (in mobile mode). Also allows H8 to shut the board down via SMC_SHUTDOWN when R3H8 is stuffed.

R4Y2 0.002

R5H16

3.0

5%

+V5SB_ATXA

.

PS_ATXSENS

+V3.3_DL_Q

C4H6

C4H6 220uF

220uF

10%

10% .

.

1

0

.

+V3.3_ATX +V3.3_ATX

R5H15

R5H15 10K

10K

5%

5% .

.

5

4

+V5_ATX

R4J1

1 2

0

NO_STUFF

R2Y2

R2Y2 10K

10K

5%

5% .

.

V12ATXSW

3

Q3G1

Q3G1 BSS138

BSS138

ATX_PWR_CNTRL

Battery Mode: ATX_PWR_CNTRL = VBATA

.

2

ADAPT_PRES_R

SHUTDWN#

.

3

Brick Mode: ATX_PWR_CNTRL = VBATA ATX Mode: ATX_PWR_CNTRL=0V

VR_ALW_ENABLE

Active High: SHUTDWN#||BC_ACOK_BATT)&ATX_PWR_CNTRL

Enables on board Always VRs (5MBL,

3.3MBL, and 1.5A) when running off AC brick or battery. Low in ATX

2

CR3W1

CR3W1 BAT54C

BAT54C

3

1

1 2 3 4 5 6 7 8 9

10

Q4H10

Q4H10 SI3442BDV

SI3442BDV

mode.

PS_ACENABLE

R3H8 0

NO_STUFF

Stuff R3H8 only for G3 Mobile power cycling

1 2 3 4 5 6 7 8 9 10

R4H2 3.0

R2W8

R2W8 100K

100K

-V12A57-V12_ATX

1%

ATX POWER

J4J1

11

12

13

14

15

16

17

18

19

20

CON20_PWR

+V3.3_DL_QR 3.3V_DL_R

652

1

4

VBSGT

3

5%

.

+VBS51

5

ATX_PWR_CNTRL 57

Q3W1

Q3W1 BSS138

BSS138

2

.

1

+V5_ATX

R4W21

3.0

5%

5% .

.

Q2J1

SI7483ADP

3 2 1

4

POWER ON and S5 ENTER/EXIT Button

VR_ALW_ENABLE 28,46

+V12_ATX

ATX_PWROK 42

3V MIN CURRENT DUMMY LOAD: Gives 0.5A min current load

3

+VBATA26,46..48,57 +VBAT17,49,53,56,57

+

C2Y1

C2J2

0.1uF

15uF

10%

10% .

.

+V5SB_ATX

R5H17 0.002

15uF

20%

20% .

.

PS_ON_SW# 45

3

1

2

3

4

SW8E1

SW8E1 Push_Button

Push_Button

1

2

+V5SB_ATXA

1%

.

5SB_ATXA_R

R2V7

R2V7 100K

100K

PS_PWRBTN

1

Q2G1

Q2G1 BSS138

BSS138

.

CR8E1

BAT54

R9V20

R9V20 10K

10K

5%

5% .

.

1

R9V16

R9V16 10K

10K

5%

5% .

.

R2V61MR2V6 1M

C2V3

R2V1

R2V1 390K

390K

0.33uF

80%

.

PWRONLATCHG

CR2G2

13

BAT54

BAT54 CR3V1

3

2

CR3V1

BAT54

R2V3

R2V3 100K

100K

19,21,23..29,33,34,39..42,44..48,50..52,56,57

13

SMC_ONOFF# 42,44

Q2V2

Q2V2 BSS138

BSS138

.

R8E4

R8E4 100K

100K

Button Latch

13

RESET BUTTON

+V3.3A19,21,23..29,33,34,39..42,44..48,50..52,56,57

NETDETECT_12V#

3

Q8E3

BSS138

R9V19

R9V19 10K

10K

5%

3

2

123

.

Q9W1

Q9W1 BSS138

BSS138

.

Push_Button

1

.

2

C8E4

C8E4 1000PF

1000PF

10%

SW1C2

4

Shunt pins 13 & 15 for SV forcing ATX on and VBAT on for power cycling

ATX_DETECT#

Acitve Low: Indicates system is powered by ATX supply to H8: Note H8 looks at this signal before BC_ACOK#.

3.3V=Mobile Mode (BATT or Brick) 0V=ATX mode powerd by ATX supply

ATX_DETECT# 42,44

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

R2Y1

R2Y1 100K

100K

3

4

SW1C1

SW1C1 Push_Button

Push_Button

1

2

ND_SW#42

Net Detect Button

+VBATA26,46..48,57

R4Y1

0.002

1%

1% .

.

3

2

Q2Y1

SI4425DY

3 8 2 1

PS_LATCH#

+V3.3A

+VBATA26,46..48,57

Net Detect

R8E1

R8E1 43K

43K

NO_STUFF

.

RSTBTNDB 45

ATA_LED#21

Start Up Sequence

NDA 1.5

Tuesday, December 05, 2006

7 6 5

J3G1J3G1

4

J3G1 Pin 1 and 2 should be shorted for ME support in G3

R2V8

R2V8 100K

100K

Force Shutdown

SMC_SHUTDOWN42,44

R8E3

R8E3 100K

100K

NETDETECT_12V

3

Q8E1

Q8E1 BSS138

BSS138

1

.

2

R5W7 10K

+V5S5,11,12,16..18,24,30..32,34,41,49,50,52,53,56,57

1

CR6Y1

CR6Y1 BAT54

BAT54

3

RST_PUSH#_D

PS_LATCH#

C6W5

C6W5 470pF

470pF

5%

5% .

.

+

C5B2

C2W9

15uF

20%

.

12

132

1

.

R7H8

R7H8 330

330

.

FRONT1

C7H7

C7H7 470pF

470pF

5%

5% .

.

12

J2H1J2H1

1

CR2G1

R2H1

BAR43S

100K

19,21,23..29,33,34,39..42,44..48,50..52,56,57

3

Q8E2

1

BSS138

.

2

SMC_ME_ALERT 23,42,44

+V3.3A19,21,23..29,33,34,39..42,44..48,50..52,56,57

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,44,45,49,50,52,56,57

U5H1

1

VCC

GND

2

OUT

IN

MAX6816

R5H13 100KR5H13 100K

3, 20 XDP_DBRESET#

+V5 27,33,43..45,50,52,56,57

1 3 5 7

9 11 13 15

HDR_2x8

C6J2

C6J2 470pF

470pF

5%

5% .

.

Front Panel Header

+

C2H6

C2H6 15uF

15uF

20%

20% .

.

Q2V1

BSS138

3

2

+V3.3A

4

MASTER_RESET#

3

J6H5

2 4 6 8 10 12

16

.

Q2G2

Q2G2 BSS138

BSS138

.

3

2

3

2

R8D6

R8D6 100K

100K

Q8D1

Q8D1 BSS138

BSS138

.

. 10%

10%

C5W7

0.01uF

2

1

+VBATA26,46..48,57

R2V5

R2V5 100K

100K

Power

Button Latch

1

C2V4

C2V4 1000PF

1000PF

10%

NETDETECT# 42,44

SMC_NET_DETECT: Net Detect trigger signal to ICH8. Also clears netdetect button latch.

1 2

PWR_CONN_D

R2V2

R2V2 43K

43K

.

NO_STUFF

Signals EC of a net detect button event.

3.3V Net Detect Level Shifter

53

U5W1

74AHC1G08

.

FRONT2

55

1

R2V4

R2V4 100K

100K

SHUTDWN#

3

Q2G3

Q2G3 BSS138

BSS138

1

.

2

C5H1

0.1uF

10%

.

4

PM_SYSRST# 23

+V5S5,11,12,16..18,24,30..32,34,41,49,50,52,53,56,57

R6J1

R6J1 330

330

.

C6H5

C6H5 470pF

470pF

5%

5% .

.

CR6J2

PS_ON_SW#

13

BAT54

C6H6

C6H6 470pF

470pF

5%

5% .

.

Intel Confidential

58

of

5

4

3

SLP_S3# DISCHARGE CKT DESIGNED FOR ~100ms DISCHARGE ON ALL S3 RAILS.

2

SLP_S4# DISCHARGE CKT DESIGNED FOR ~100ms DISCHARGE ON ALL S4 RAILS.

1

Insures that 1.05S and 1.5S ramp down together by discharging 1.5S into 1.05S.

D D

6 5 2 1

3

Q5G3

4

SI3442BDV

PM_SLP_S3#11,23,26,42,44,45,48,57

+V1.05S4,9,10,24,48+V1.5S4,10,11,24,28,48

1

C C

+V1.05S4,9,10,24,48

+V3.3A19,21,23..29,33,34,39..42,44..48,50..52,55,57

R4M7

R4M7 100K

100K

PM_SLP_S3_BUF

3

Q4A2

Q4A2 BSS138

BSS138

PM_SLP_S3#11,23,26,42,44,45,48,57

B B

1

.

2

1

+VCC_CORE4,53,54

1

+VBAT17,49,53,55,57

C3T5

C3T5 22UF

22UF

3

Q3C1

Q3C1 BSS138

BSS138

.

2

R3U2

R3U2 470

470

5%

5% .

.

PM_SLP_S3_BUF_R

3

Q3U1

Q3U1 BSS138

BSS138

.

2

R3D247R3D2 47

PP_VIMVPDIS

3

Q3D1

Q3D1 BSS138

BSS138

.

2

1

3

CR3U1

CR3U1 BAT54

BAT54

R3U4

R3U4 100K

100K

R3U31MR3U3 1M

PM_SLP_S3

+V12S25,26,30..33,44,57

1

VBATA_DISCHARGE

+V5S5,11,12,16..18,24,30..32,34,41,49,50,52,53,55,57

1

+V1.5S4,10,11,24,28,48

1

12

R7B1

R7B1 180

180

PP_V12SDIS

3

Q7B1

Q7B1 BSS138

BSS138

.

2

R4W14

97.6

.

PP_V5SDIS

3

Q4W2

Q4W2 BSS138

BSS138

.

2

R4V847R4V8 47

PP_V1.5SDIS

3

Q4V1

Q4V1 BSS138

BSS138

.

2

R4V16

R4V16 10K

10K

.

PM_SLP_M#23,42,44,45,48,57

ATX Mounting Holes

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55,57

R4W15

97.6

.

PP_V3SDIS

3

Q4H3

Q4H3 BSS138

BSS138

1

.

2

R4V19

R4V19 100K

100K

Q4G8

Q4G8 BSS138

BSS138

.

PP_V3MDIS

3

2

27,33,43..45,50,52,55,57

R5W4

97.6

.

PP_V5DIS

3

1

2

+V0.914,15,47

1

R4V17

97.6

.

Q4G4

Q4G4 BSS138

BSS138

.

3

1

2

Q5W2

Q5W2 BSS138

BSS138

.

R4N5

220

PP_V0.9DIS

3

Q4B2

Q4B2 BSS138

BSS138

.

2

Q4G11

Q4G11 BSS138

BSS138

.

LAN_WOL_EN 23,42,44,57

1

+V1.25S10,24,57

R4G4

R4G4 470

470

5%

5% .

.

PP_V1.25SDIS

3

Q4G1

Q4G1 BSS138

BSS138

1

.

2

+VBATS16,19,27,57

12

R5H14

R5H14 180

180

PP_12DIS

3

Q5H1

Q5H1 BSS138

BSS138

1

.

2

PM_S4_STATE#23,34,42,44,45,57

+V3.3S_TVDAC10,11,50

R3U6

4.87K

1%

1% .

.

PP_V3STVDIS

3

Q3F1

Q3F1 BSS138

BSS138

1

.

2

PM_SLP_M

3

Q4G3

R4V151MR4V15

BSS138

1

2

1M

.

R3U5

R3U5 100K

100K

PP_S4GT

R5V131MR5V13 1M

3

Q4U2

Q4U2 BSS138

BSS138

1

.

2

PM_SLP_S4#23,47

+V1.05M9,48

R4V18

R4V18 470

470

5%

5% .

.

PP_V105M_DIS

3

Q4G5

Q4G5 BSS138

BSS138

1

.

2

1

DDR_DIS

3

2

1

PP_V33M_DIS

R4G18

R4G18 100K

100K

5%

1

+V1.25M10,37,48,57+V3.3M13..15,23,24,35,36,42,44,50,57

PP_V125MDIS

3

2

R4V20

R4V20 470

470

5%

5% .

.

Q4G7

Q4G7 BSS138

BSS138

.

+V3.319,27,33,41..44,49,57

PP_V3DIS

3

2

+VBAT_S419,57+V5

12

PP_BATS4DIS

3

2

+V1.89,10,13,14,47,50

PP_V1.8DIS

3

2

R5V15

97.6

.

Q5G6

Q5G6 BSS138

BSS138

.

R6N4

R6N4 180

180

Q6N2

Q6N2 BSS138

BSS138

.

R5B7

R5B7 68

68

5%

5% .

.

Q5N1

Q5N1 BSS138

BSS138

.

1

+V3.3M_CK50537,57

R4H1

R4H1 470

470

5%

5% .

.

PP_V33MCKDIS

3

2

Q4H1

Q4H1 BSS138

BSS138

.

A A

MT1B1

236 4

5

MT156

236 7 8

4 9

5

NO_STUFF

MT1J1

7 8 9

MT156

NO_STUFF

MT1F1

236 4

5

MT156

7 8 9

NO_STUFF

5

236 4

5

MT5A1

7 8 9

MT156

NO_STUFF

MT9A1

236 4

5

MT156

7 8 9

NO_STUFF

MT9F1

236 4

5

MT156

7 8 9

NO_STUFF

MT9J1

236 4

5

MT156

7 8 9

NO_STUFF

MT5J1

236 4

5

MT156

7 8 9

NO_STUFF

4

Intel Confidential

Matanzas

Title

Size Document Number Rev

Date: Sheet

3

Date: Sheet

DISCHARGE CIRCUITS

A

NDA

2

Intel Confidential

56 58Tuesday, December 05, 2006

1

1.5

of

5

1

6

+V5A24,29,40,42,47,48,51,55

PS_S3CNTRL

3

Q4H6

Q4H6 BSS138

BSS138

.

2

1

7 6 5

R6B2

R6B2 100K

100K

Q6A3

Q6A3 BSS138

BSS138

.

U9B1

1

TLP280

+VBATA26,46..48,55

R4W16

R4W16 100K

100K

R4W17

R4W17 100K

100K

3

Q4H7

Q4H7 BSS138

BSS138

.

2

53

U5H2

1 2

74AHC1G08

+VBATS 16,19,27,56

C6B3

0.33uF

80%

80% .

.

PS_S3CNTRL

PS_S4CNTRL

+VBATA26,46..48,55

C5W8

0.1uF

10%

.

4

.

PM_S3#_AND

R9A12

R9A12 10K

10K

5%

5% .

.

PS_-12SSW

4

32

C5W9

0.1uF

10%

10% .

.

PM_S4_STATE#23,34,42,44,45,56

19,21,23..29,33,34,39..42,44..48,50..52,55,56

D D

PM_SLP_S3#11,23,26,42,44,45,48,56

C C

ATX_PWR_CNTRL55

B B

PM_SLP_S3#11,23,26,42,44,45,48,56

+V3.3A

R4H3

R4H3 10K

10K

5%

NO_STUFF

1

PM_S4_STATE#23,34,42,44,45,56

+V3.3A19,21,23..29,33,34,39..42,44..48,50..52,55,56

R5W10

R5W10 10K

10K

5%

ATX_PWR_CTRL_1

.

3

Q4H9

Q4H9 BSS138

BSS138

1

.

2

PM_SLP_S3#11,23,26,42,44,45,48,56

+VBAT17,49,53,55,56

C6B1

0.33uF

80%

80% .

.

3 8 2 1

R6B3

R6B3 100K

100K

1

Q6B2

Q6B2 SI4425DY

SI4425DY

PS_VBATSG

4

PS_VBATSW

3

2

A A

8,24,30..32,34,41,49,50,52,53,55,5

+V5S

R9N1

PS_-12OPTSW

330

.

5

R4W18

R4W18 100K

100K

1

R4W19

R4W19 100K

100K

1

3 8 2 1

R5W11

R5W11 100K

100K

1%

1% .

.

PS_12SSW

1

+VBAT17,49,53,55,56

C6N1

0.1uF

10%

10% .

.

4

C9A6

0.1uF

10%

10% .

.

C9A5

0.1uF

10%

10% .

.

4

3

2

-V12A55

1238

4

783 6 5

3

Q4H5

Q4H5 BSS138

BSS138

.

2

783 6 5

Q4W4

Q4W4 BSS138

BSS138

.

Q5H2

Q5H2 SI4425DY

SI4425DY

4

R4W22

R4W22 100K

100K

PS_12SG

3

Q4H8

Q4H8 BSS138

BSS138

.

2

3 8 2 1

R6N2

R6N2 100K

100K

1

Q9A1

Q9A1 SI4420DY

SI4420DY

-V12S 33,34

765

Q4H4

Q4H4 IRF7811A

IRF7811A

.

2 1

4

+V5 27,33,43..45,50,52,55,56

Q4W5

Q4W5 IRF7811A

IRF7811A

2

.

1

4

C4H3

0.1uF

10%

10% .

.

+V12S25,26,30..33,44,56

7

C4Y1

6

0.33uF

5

80%

.

Q6N1

SI4425DY

7 6 5

PS_VBAT_S4_G

4

R6N1

R6N1 100K

100K

PS_VBAT_S4_D

3

Q6M1

Q6M1 BSS138

BSS138

.

2

.

. 10%

10%

C4H4

0.01UF

+VBAT_S419,56

+V5S5,11,12,16..18,24,30..32,34,41,49,50,52,53,55,56

+V3.3A19,21,23..29,33,34,39..42,44..48,50..52,55,56

783 6 5

VBATA_SLEEP

+V3.3A 19,21,23..29,33,34,39..42,44..48,50..52,55,56

783 6 5

SLPS4#_CONTROL

System Power Good

PLT_RST#7,19,22,25,26,39,40,42

C6N6

0.33uF

80%

80% .

.

PM_SLP_M#23,42,44,45,48,56

1

Added to isolate CK505 from 3.3M when WOL/Moff is enabled.

3

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55,56

2 1

4

+V3.319,27,33,41..44,49,56

2 1

4

+VBATA26,46..48,55

R5V8 100KR5V8 100K

R5V7

R5V7 100K

100K

V3.3M_CK505_INV

3

Q5W7

Q5W7 BSS138

BSS138

.

2

3

Q4W3

Q4W3 IRF7822

IRF7822

.

Q4H2

Q4H2 IRF7822

IRF7822

.

1

+V1.25M10,37,48,56

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55,56

SYS_STATUS_PU

1 2

SYS_STATUS_CR

3

2

+V3.3A19,21,23..29,33,34,39..42,44..48,50..52,55,56

1

783 6

2

5

1

4

PM_SLP_S3#11,23,26,42,44,45,48,56

R5Y175R5Y1 75

CR5J1

CR5J1 GREEN

GREEN

.

Q5J1

Q5J1 BSS138

BSS138

.

+VBATA26,46..48,55

R7N6

R7N6 100K

100K

3

Q7B2

Q7B2 BSS138

BSS138

.

2

Q5W1

Q5W1 IRF7822

IRF7822

783 6

2

5

1

4

V3.3M_CK505_SWITCH

3

Q5W3

Q5W3 BSS138

BSS138

.

2

+V1.25S10,24,56

Q4F1

Q4F1 IRF7822

IRF7822

.

R4W675R4W6 75

PP_M0LED

CR4H1

CR4H1 GREEN

GREEN

.

1

S5

0V

PM_SLP_S5#23

+V3.319,27,33,41..44,49,56

Q3V3

SI2307DS

1

.

3 2

PP_S3CLED

R3G475R3G4 75

PP_S3CLEDSW

CR3G2

CR3G2 GREEN

S3 COLD

PS_S3CNTRL

R6N3

R6N3 100K

100K

V3M_G_SWITCH_OR

Q6B4

BSS138

.

+V3.3M_CK50537,56

.

C5V11

.

. 10%

10%

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

GREEN

1 2

PP_S3CLEDSW_D

.

3

Q3V2

Q3V2 BSS138

BSS138

1

2

V3M_G_SWITCH

1

3

1

2

0.01UF

Sleep control

NDA 1.5

75 ohms chosen for ~16mA of LED current

.

+V3.3A19,21,23..29,33,34,39..42,44..48,50..52,55,56

13..15,23,24,35,36,42,44,50,56

783 6 5

3

Q6B1

Q6B1 BSS138

BSS138

.

2

LAN_WOL_EN 23,42,44,56

SLP_M# LAN_WOL_EN 3.3M 3.3M_CK505 SYSTEM STATE

00 0

1 01

11

+V3.3M_CK50537,56

M0/M1

1 2

+V3.3M

Q6B3

Q6B3 IRF7822

IRF7822

2

.

1

4

C6N2

0.01UF

.

. 10%

10%

Added for WOL in S3/Moff. Enabled by CLGPIO3=LAN_WOL_EN.

0V

3.3V 0V

3.3V 3.3V

+V3.3A19,21,23..29,33,34,39..42,44..48,50..52,55,56

Q5W4

SI2307DS

.

3 2

PP_S5LED

R5W575R5W5 75

PP_S5LEDSW

CR5H4

CR5H4 GREEN

GREEN

1 2

.

Moff / No WOL Legacy WOL / Moff

23,34,42,44,45,56

PM_S4_STATE#

PM_SLP_S5#23

M1 M1

2

1

S4

1

SO

PM_SLP_S3#11,23,26,42,44,45,48,56

57 58Tuesday, December 05, 2006

1

Intel Confidential

of

1

+V3.3A19,21,23..29,33,34,39..42,44..48,50..52,55,56

Q5W6

SI2307DS

.

3 2

PP_S4LEDSW1

R5W675R5W6 75

PP_S4LED

1 2

PP_S4LEDSW2

3

2

+V3.3S5,7,10,12,16..26,28,30..32,34,37..42,44,45,49,50,52,55,56

CR5H3

CR5H3 GREEN

GREEN

.

Q5W5

Q5W5 BSS138

BSS138

.

R5W875R5W8 75

PP_S0LED

CR5H5

CR5H5 GREEN

GREEN

1 2

.

PP_S0LEDSW

3

Q5W8

Q5W8 BSS138

BSS138

.

2

5

4

3

2

1

Steps 1 leads to either 1BAT for battery only mode or 1AC for AC mode. 5AC leads to 5a to 5b to 5c to 6. Battery mode requires button press to begin power up. AC mode requires button press to boot.

D D

PM_SLP_S3#

+VBATS

+V3.3A

7

+V5S

7

+VBAT_S4

7

7 7

+V3.3S +V1.25S

+V5

+V3.3

+V1.8

+V0.9

6

SLP_S3 SWITCHES

SHT 57

PM_S4_STATE#

6

SLP_S4 SWITCHES

SHT 57

PM_SLP_S4#

6

DDR VR

SHT 47

+V3.3S_TVDAC

LDO

SHT 11

7

+V3.3_PCIE_AUX

7

C C

SWITCH

SHT 57

OR

PM_SLP_S3#

EC_VAUX_ON

+V3.3M

+VBAT

+V5A

+V3.3A

+V1.25M

+VBAT

+V5A

+V3.3A

+VBAT

MATANZAS Mobile Power On Sequence

Sequence waits here for button press before doing step 1BAT = 5AC.

PG 54

+VBATA

SYSTEM

+V5A

3

+V1.5A_HDA_IO

+V5A3A_MBL_PWRGD

3a

VR

+V3.3A

3

SHT 46

PWRGD

LDO

SHT 28

RSMRST#_PWRGD

IMVP_VR_ON

EC_VAUX_ON

6

to line switches

1BAT

5AC

PS_ON_SW#

VR_ALW_ENABLE

+V3.3A

H8 SMC

SHT 42 & 44

(300ms MAX)

99ms DELAY

11

Startup Circuit

SHT 55

2

+VBATA+VBAT

SMC_ONOFF#

5a

4

SMC_RST#_D

PM_PWRBTN#

PM_RSMRST#

10

+VBS

BC_ACOK_BATT

1

+V3.3A

MAX-809

SHT 43

MPWROK

5b

5c

PM_ICH_PWROK

SHT 23

Battery OR AC insertion cause 1

Charger Circuit

1AC

CLPWROK

PWROK

16

SHT 51

ICH8

SHT 21,22,23,24

VRMPWRGD

CLGPIO3/GPIO9

Only AC insertion causes 1AC

14

CLK_PWRGD

H_PWRGD

17

18

SHT 51

Battery Pack

AC Adapter

SHT 51

PWRGD

SHT 50

SYSTEM

B B

VR POWER GOOD MONITOR

+V3.3M

CK505

VRPWRGD_3.3M_R

+V5S

+V3.3S

+V3.3S_TVDAC

8

PM_SYS_PWRGD

CLK_PWRGD

ENABLE

DDR_PGGOD_RU

8

14

+VCC_CORE

VR_PWRGD_CLKEN#

+V3.3A

SHT 47

12

System Clock

A A

+V3.3S

SHT 37

DB800M CLOCK BUFFERS

SHT 38

5

EN

+V3.3S

13

VR_PWRGD_CLKEN

+V3.3A

SHT 47

9

PM_PWROK

11

IMVP_VR_ON

ENABLE

IMVP CPU CORE VR

SHT 52

MPWROK

to ICH & MCH

5130_PWRGD

PGD_IN

DELAY_VR_PWRGOOD

15

4

9

8

+V3.3M

7

+V3.3M_CK505

7

+V1.5S

ICH LOGIC

+V1.05S

VCCP

MCH,ICH CORE

5130_PWRGD

PM_PWROK

SWITCH

SHT 57

SWITCH

SHT 57

+VBAT

7

+V3.3A

SHT 48

6

PM_S4_STATE# PM_SLP_S3#

6

+V3.3A

SHT 48

+V1.25M

7

+V1.05M LDO

7

3

OR

ALL_SYS_PWRGD

10

PM_SLP_S4#

6

to DDR VR

PM_SLP_M#

6

LAN_WOL_EN

CRESTLINE

MCH

SHT 6,7,8,9,10,11

PWROK

MPWROK

Matanzas

Title

Size Document Number Rev

A

Date: Sheet

CLPWROK

+VBAT

POWER SEQUENCING TIMING BLOCK DIAGRAM

NDA

2

GVR_VR_EN

GFX VR

SHT 49

PLT_RST#

+VCC_GMCH_CORE, +VCCP

H_CPURST#

19

+VCC_GFXCORE

PWRGD

SHT 3,4

Intel Confidential

58 58Tuesday, November 21, 2006

1

CPU

of

+VCC_CORE, +VCCP

1.5

Intel Matanzas Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual