INTEL LXT974, LXT975 User Manual
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LXT974/LXT975
Fast Ethernet 10/100 Quad Transceivers
Datasheet
The LXT974 and LXT975 are four-port PHY Fast Ethernet Transceivers which support IEEE
802.3 physical layer applications at both 10 Mbps and 100 Mbps. They provide all of the active
circuitry to interface four 802.3 Media Independent Interface (MII) compliant controllers to
10BASE-T and/or 100BASE-TX media.
This data sheet applies to all versions of the LXT974 and LXT975 products including
LXT974A, LXT974B, LXT975A, and LXT975B. As a result of product changes, Revision 4
parts are labeled LXT974B and LXT975B. Revision 3 parts are labeled LXT974A and
LXT975A. The differences in these product revisions are described in the LXT974/975
Specification Update.
All four ports on the LXT974 provide a combination twisted-pair (TP) or pseudo-ECL (PECL)
interface for a 10/100BASE-TX or 100BASE-FX connection.
The LXT975 is pin compatible with the LXT974 except for the network ports. The LXT975 is
optimized for dual-high stacked RJ-45 modular applications and provides a twisted-pair
interface on every port, but the PECL interface on only two.
The LXT974/975 provides three separate LED drivers for each of the four PHY ports and a
serial LED interface. In addition to standard Ethernet, each chip supports full- duplex operation
at 10 Mbps and 100 Mbps. The LXT974/975 requires only a single 5V power supply. The MII
may be operated independently with either a 3.3V or 5V supply.
Applications
■ 10BASE-T, 10/100-TX, or 100BASE-
FX Switches and multi-port NICs.
■ LXT975 optimized for dual-high stacked
modular RJ-45 applications.
Product Features
■ Four independent IEEE 802.3-
compliant 10BASE-T or 100BASETX ports in a single chip.
■ 100BASE-FX fiber-optic capable.
■ Standard CSMA/CD or full-duplex
operation.
■ Supports auto-negotiation and legacy
systems without auto-negotiation
capability.
■ Baseline wander correction.
■ 100BASE-TX line performance over
130 meters.
■ Configurable LED drivers and serial LED output.
■ Configurable through MII serial port or via
external control pins.
■ Available in 160-pin PQFP with heat spreader.
■ Commercial temperature range (0-70
o
C
ambient).
■ Part numbers:
—LXT974AHC
—LXT974BHC
—LXT975AHC
—LXT975BHC
As of January 15, 2001, this document replaces the Level One document Order Number: 249274-001
LXT974/LXT975 Fast Ethernet 10/100 Quad Transceivers. January 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT974/LXT975 may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Contents
1.0 Pin Assignments and Signal Descriptions....................................................10
2.0 Functional Description...........................................................................................19
2.1 Introduction..........................................................................................................19
2.2 Network Media / Protocol Support.......................................................................20
2.2.1 10/100 Mbps Network Interface .............................................................20
2.2.1.1 Twisted-Pair Interface ...............................................................20
2.2.1.2 Fiber Interface ...........................................................................21
2.2.2 MII Interface ...........................................................................................21
2.2.2.1 MII Data Interface...................................................................... 21
2.2.2.2 MII Management Interface ........................................................24
2.2.3 Hardware Control Interface ....................................................................25
2.3 Initialization.......................................................................................................... 27
2.3.1 MDIO Control Mode ...............................................................................27
2.3.2 Manual Control Mode ............................................................................. 27
2.3.3 Link Configuration ..................................................................................28
2.4 Auto-Negotiation..................................................................................................29
2.4.1 Parallel Detection ...................................................................................29
2.4.2 Controlling Auto-Negotiation .................................................................. 29
2.4.3 Monitoring Auto-Negotiation...................................................................29
2.5 100 Mbps Operation............................................................................................30
2.5.1 100BASE-X MII Operations....................................................................30
2.5.2 100BASE-X Network Operations ...........................................................30
2.5.3 100BASE-X Protocol Sublayer Operations ............................................33
2.5.4 PCS Sublayer.........................................................................................33
2.5.4.1 Preamble Handling .................................................................... 33
2.5.4.2 Data Errors ................................................................................ 34
2.5.4.3 Collision Indication ....................................................................34
2.5.5 PMA Sublayer ........................................................................................ 35
2.5.5.1 Link............................................................................................35
2.5.5.2 Link Failure Override .................................................................35
2.5.5.3 Carrier Sense (CRS) .................................................................35
2.5.6 Twisted-Pair PMD Sublayer ................................................................... 35
2.5.6.1 Scrambler/Descrambler (100TX Only) ......................................35
2.5.6.2 Baseline Wander Correction .....................................................36
2.5.6.3 Polarity Correction .....................................................................36
2.5.7 Fiber PMD Sublayer ............................................................................... 36
2.6 10 Mbps Operation..............................................................................................36
2.6.1 10BASE-T MII Operation........................................................................36
2.6.2 10BASE-T Network Operations..............................................................36
2.6.2.1 Preamble Handling .................................................................... 37
2.6.2.2 Link Test....................................................................................37
2.6.2.3 Link Failure................................................................................37
2.6.2.4 SQE (Heartbeat)........................................................................37
2.6.2.5 Jabber .......................................................................................37
2.7 LED Functions.....................................................................................................37
2.7.1 Serial LED Output .................................................................................. 38
Datasheet 3
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
2.7.2 Per Port LEDs ........................................................................................38
2.7.2.1 LEDn_0 ..................................................................................... 38
2.7.2.2 LEDn_1 ..................................................................................... 38
2.7.2.3 LEDn_2 ..................................................................................... 38
2.8 Operating Requirements ..................................................................................... 39
2.8.1 Power Requirements.............................................................................. 39
2.8.1.1 MII Power Requirements........................................................... 39
2.8.1.2 Low-Voltage Fault Detect .......................................................... 39
2.8.1.3 Power Down Mode ....................................................................39
2.8.2 Clock Requirements............................................................................... 39
3.0 Application Information.........................................................................................40
3.1 Design Recommendations .................................................................................. 40
3.1.1 General Design Guidelines ....................................................................40
3.1.2 Power Supply Filtering ........................................................................... 40
3.1.2.1 Ground Noise ............................................................................41
3.1.3 Power and Ground Plane Layout Considerations .................................. 41
3.1.3.1 Chassis Ground......................................................................... 41
3.1.4 MII Terminations .................................................................................... 41
3.1.5 The RBIAS Pin .......................................................................................42
3.1.6 The Twisted-Pair Interface ..................................................................... 42
3.1.7 The Fiber Interface ................................................................................. 42
3.2 Magnetics Information ......................................................................................... 43
3.2.1 Magnetics With Improved Return Loss Performance............................. 43
3.3 Twisted-Pair/ RJ-45 Interface.............................................................................. 44
4.0 Test Specifications..................................................................................................50
5.0 Register Definitions ................................................................................................ 63
6.0 Package Specification............................................................................................ 73
4 Datasheet
Figures
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
1 LXT974/975 Block Diagram .................................................................................. 9
2 LXT974 Pin Assignments ...................................................................................10
3 LXT975 Pin Assignments ...................................................................................12
4 LXT974 Switch Application .................................................................................19
5 LXT975 Switch Application .................................................................................20
6 MII Data Interface ...............................................................................................22
7 Loopback Paths ..................................................................................................24
8 Management Interface - Read Frame Structure .................................................25
9 Management Interface - Write Frame Structure .................................................25
10 MDIO Interrupt Signaling ....................................................................................25
11 Hardware Interface Mode Selection ...................................................................28
12 LXT974/975 Auto-Negotiation Operation ........................................................... 30
13 100BASE-TX Data Flow ..................................................................................... 31
14 100BASE-TX Frame Structure ...........................................................................31
15 LXT974/975 Protocol Sublayers .........................................................................33
16 100BASE-TX Reception with No Errors .............................................................34
17 100BASE-TX Reception with Invalid Symbol .....................................................34
18 100BASE-TX Transmission with No Errors ........................................................34
19 100BASE-TX Transmission with Collision .......................................................... 34
20 Typical LXT974 Twisted-Pair Single RJ-45 Modular Application .......................44
21 Typical LXT975 Twisted-Pair Stacked RJ-45 Modular Application ....................45
22 LXT974/975 Power and Ground Connections ....................................................46
23 Typical Twisted-Pair Interface and Supply Filtering ...........................................47
24 Typical Fiber Interface ........................................................................................48
25 Typical MII Interface ...........................................................................................49
26 MII - 100BASE-TX Receive Timing ....................................................................53
27 MII - 100BASE-TX Transmit Timing ................................................................... 54
28 MII - 100BASE-FX Receive Timing ....................................................................55
29 MII - 100BASE-FX Transmit Timing ................................................................... 56
30 MII - 10BASE-T Receive Timing ........................................................................57
31 MII - 10BASE-T Transmit Timing .......................................................................58
32 10BASE-T SQE (Heartbeat) Timing ...................................................................58
33 10BASE-T Jab and Unjab Timing ...................................................................... 59
34 Auto Negotiation and Fast Link Pulse Timing .................................................... 60
35 Fast Link Pulse Timing ....................................................................................... 60
36 MDIO Timing when Sourced by STA ................................................................. 61
37 MDIO Timing When Sourced by PHY ................................................................61
38 Power Down Timing ........................................................................................... 62
39 Serial LED Timing ..............................................................................................62
40 PHY Identifier Bit Mapping ..................................................................................66
41 LXT974/975 Package Specification ................................................................... 73
Datasheet 5
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Tables
1 LXT974 Signal Detect/TP Select Signal Descriptions......................................... 11
2 LXT974 Twisted-Pair Interface Signal Descriptions............................................ 11
3 LXT974 Fiber Interface Signal Descriptions........................................................ 11
4 LXT975 Signal Detect/TP Select Signal Descriptions......................................... 13
5 LXT975 Twisted-Pair Interface Signal Descriptions............................................ 13
6 LXT975 Fiber Interface Signal Descriptions........................................................ 13
7 LXT974 and LXT975 MII Signal Descriptions .....................................................14
8 LXT974 and LXT975 Hardware Control Interface Signal Descriptions ...............16
9 LXT974 and LXT975 Miscellaneous Signal Descriptions ................................... 17
10 LXT974 and LXT975 LED Indicator Signal Descriptions .................................... 17
11 LXT974 Power Supply Signal Descriptions......................................................... 18
12 LXT975 Power Supply Signal Descriptions......................................................... 18
13 Test Loopback Operation....................................................................................23
14 Carrier Sense, Loopback, and Collision Conditions............................................24
15 Configuring the LXT974/975 via Hardware Control ............................................ 26
16 Configuring LXT974/975 Auto-Negotiation Advertisements Via
Hardware Control ................................................................................................26
17 Configuring the LXT974/975 with Auto-Negotiation Disabled ............................. 27
18 Mode Control Settings.........................................................................................28
19 4B/5B Coding ......................................................................................................32
20 LED-DAT Serial Port Bit Assignments ................................................................39
21 Magnetics Requirements ....................................................................................43
22 Absolute Maximum Ratings ................................................................................50
23 Operating Conditions ..........................................................................................50
24 Digital I/O Characteristics 1................................................................................. 50
25 Digital I/O Characteristics - MII Pins) .................................................................. 51
26 Required CLK25M Characteristics...................................................................... 51
27 Low-Voltage Fault Detect Characteristics ........................................................... 51
28 100BASE-TX Transceiver Characteristics ..........................................................51
29 100BASE-FX Transceiver Characteristics ..........................................................52
30 10BASE-T Transceiver Characteristics............................................................... 52
31 MII - 100BASE-TX Receive Timing Parameters ................................................. 53
32 MII - 100BASE-TX Transmit Timing Parameters ................................................ 54
33 MII - 100BASE-FX Receive Timing Parameters ................................................. 55
34 MII - 100BASE-FX Transmit Timing Parameters ................................................ 56
35 MII - 10BASE-T Receive Timing Parameters......................................................57
36 MII - 10BASE-T Transmit Timing Parameters..................................................... 58
37 10BASE-T SQE (Heartbeat) Timing Parameters ................................................ 58
38 10BASE-T Jab and Unjab Timing Parameters.................................................... 59
39 Auto Negotiation and Fast Link Pulse Timing Parameters..................................60
40 MII Timing Parameters ........................................................................................ 61
41 Power Down Timing Parameters ........................................................................ 62
42 Serial LED Timing Parameters............................................................................62
43 Register Set ........................................................................................................ 63
44 Control Register .................................................................................................. 64
45 Status Register (Address 1) ................................................................................ 65
46 PHY Identification Register 1 (Address 2)...........................................................66
47 PHY Identification Register 2 (Address 3)...........................................................66
48 Auto Negotiation Advertisement Register (Address 4)........................................ 67
6 Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
49 Auto Negotiation Link Partner Ability Register (Address 5)................................. 67
50 Auto Negotiation Expansion (Address 6) ............................................................68
51 LED Configuration Register (Address 16, Hex 10)..............................................68
52 Interrupt Enable Register (Address 17, Hex 11) ................................................. 69
53 Interrupt Status Register (Address 18, Hex 12) .................................................. 70
54 Port Configuration Register (Address 19, Hex 13) ..............................................70
55 Port Status Register (Address 20, Hex 14) ......................................................... 71
56 QUAD FLAT PACKAGE......................................................................................73
Datasheet 7
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Revision History
Revision Date Description
1.4 11/00 Replace all references to LXT974A and LXT975A with LXT974 and LXT975
(applied to all versions, including A and B)
8 Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Figure 1. LXT974/975 Block Diagram
MII
MII
VCCMII
MII_MD<1:0>
CFG<2:0>
ADDR<4:2>
MDIO
MDC
MDINT
TX_ENn
TX_ERn
TXDn<3:0>
TRSTEn
TX_CLKn
RX_CLKn
RXDn<3:0>
CRSn
COLn
RX_DVn
RX_ERn
Tristate Control
Carrier Sense
Collision Detect
Data Valid
Error Detect
Management /
Mode Select
Logic
Register Set
Parallel/Serial
Converter
Serial to
Parallel
Converter
Global Functions
MII Power
Supply
3.3V or 5V
Manchester
10
Auto
Negotiation
Clock
Generator
Manchester
10
Decoder &
100
Descrambler
Encoder
Scrambler
& Encoder
Decoder
Pulse
100
Shaper
Media Select &
Line Energy Monitor
Slicer
Per-Port Functions
Baseline
Wander
Correction
Internal Clocks
TP
Driver
ECL
Driver
PORT 0
PORT 1
PORT 2
+
-
+
-
FDX Status
& LED
Drivers
TP
Rcvr
ECL
Rcvr
PORT 3
CLK25M
Pwr Supply /
PwrDown
TP Out
/
Fiber In
+
-
+
Fiber Out
/
TP In
VCC
GND
PWRDN
RESET
SerLED
3
LEDENA
LEDCLK
LEDDAT
TPOP/FIBINn
TPON/FIBIPn
LEDn<2:0>
3
SD/TXn
TPIP/FIBOPn
TPIN/FIBONn
-
Datasheet 9
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
1.0 Pin Assignments and Signal Descriptions
Figure 2. LXT974 Pin Assignments
160....... GND
159....... TEST
158....... SD0/TP0
157....... TPON/FIBIP0
156....... VCCT
155....... GNDT
154....... TPOP/FIBIN0
153....... VCCR
152....... TPIN/FIBON0
151....... TPIP/FIBOP0
150....... GNDR
149....... SD1/TP1
148....... TPON/FIBIP1
147....... VCCT
146....... GNDT
145....... TPOP/FIBIN1
144....... VCCR
143....... TPIN/FIBON1
142....... TPIP/FIBOP1
141....... GNDR
140....... RBIAS
139....... SD2/TP2
138....... TPON/FIBIP2
137....... VCCT
136....... GNDT
135....... TPOP/FIBIN2
134....... VCCR
133....... TPIN/FIBON2
132....... TPIP/FIBOP2
131....... GNDR
130....... SD3/TP3
129....... TPON/FIBIP3
128....... VCCT
127....... GNDT
126....... TPOP/FIBIN3
125....... VCCR
124....... TPIN/FIBON3
123....... TPIP/FIBOP3
122....... GNDR
121....... GNDR
LED3_0 .....1
LED3_1 .....2
LED3_2 .....3
LED2_0 .....4
LED2_1 .....5
LED2_2 .....6
GND .....7
LED1_0 .....8
LED1_1 .....9
LED1_2 .....10
LED0_0 .....11
LED0_1 .....12
LED0_2 .....13
GND .....14
LEDCLK .....15
LEDDAT .....16
LEDENA .....17
ADD2 .....18
ADD3 .....19
ADD4 .....20
GNDA .....21
VCC .....22
RXD0_3 .....23
RXD0_2 .....24
RXD0_1 .....25
RXD0_0 .....26
RX_DV0 .....27
RX_CLK0 .....28
RX_ER0 .....29
TX_ER0 .....30
TX_CLK0 ..... 31
TX_EN0 .....32
TXD0_0 .....33
TXD0_1 .....34
TXD0_2 .....35
TXD0_3 .....36
COL0 .....37
CRS0 ..... 38
GND .....39
VCCMII .....40
Part #
Part #
LOT #
LOT #
FPO #
FPO #
LXT974 XX
XXXXXX
XXXXXXXX
Rev #
120 .......N/C
119 .......N/C
118 .......CLK25M
117 .......FDE_FX
116 .......CFG_0
115 .......CFG_1
114 .......CFG_2
113 .......BYPSCR
112 .......TEST
111 .......AUTOENA
110 .......FDE
109 .......RESET
108 .......GNDH
107 .......VCCH
106 .......TRSTE0
105 .......TRSTE1
104 .......TRSTE2
103 .......TRSTE3
102 .......PWRDN
101 .......TEST
100 .......MDDIS
99 .........MDC
98 .........MDINT
97 .........MDIO
96 .........VCC
95 .........GND
94 .........CRS3
93 .........COL3
92 .........TXD3_3
91 .........TXD3_2
90 .........TXD3_1
89 .........TXD3_0
88 .........TX_EN3
87 .........TX_CLK3
86 .........TX_ER3
85 .........RX_ER3
84 .........RX_CLK3
83 .........RX_DV3
82 .........RXD3_0
81 .........RXD3_1
N/C .................41
RXD1_3 .......... 42
RXD1_2 .......... 43
RXD1_1 .......... 44
RXD1_0 .......... 45
RX_DV1.......... 46
RX_CLK1........ 47
RX_ER1.......... 48
TX_ER1 .......... 49
TX_CLK1........ 50
TX_EN1 .......... 51
TXD1_0 ..........52
TXD1_1 ..........53
TXD1_2 ..........54
TXD1_3 ..........55
GND................ 56
COL1 ..............57
CRS1 .............. 58
GND................ 59
VCC................ 60
RXD2_3 .......... 61
RXD2_2 .......... 62
RXD2_1 .......... 63
RXD2_0 .......... 64
RX_DV2.......... 65
RX_CLK2........ 66
RX_ER2.......... 67
TX_ER2 .......... 68
TX_CLK2........ 69
TX_EN2 .......... 70
TXD2_0 ..........71
TXD2_1 ..........72
TXD2_2 ..........73
TXD2_3 ..........74
COL2 ..............75
CRS2 .............. 76
GND................ 77
VCCMII ........... 78
RXD3_3 .......... 79
RXD3_2 .......... 80
Package Topside Markings
Marking Definition
Part # LXT974 is the unique identifier for this product family.
Rev #
Identifies the particular silicon “stepping” (Refer to Specification Update for additional stepping
information.)
Lot # Identifies the batch.
FPO # Identifies the Finish Process Order.
10 Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Table 1. LXT974 Signal Detect/TP Select Signal Descriptions
2
Pin#
158
149
139
130
1. Type Column Coding: I = Input, O = Output.
2. When not using fiber mode, SD/TPn pins should be tied to GNDT.
Symbol Type
SD0/TP0
SD1/TP1
SD2/TP2
SD3/TP3
1
Signal Detect - Ports 0 - 3. When SD/TPn pins are tied High or to a 5V PECL input, bit
19.2 = 1 and the operating mode of each respective port is forced to FX mode. In this
mode, full-duplex is set via pin 117 (FDE_FX). When not using FX mode, SD/TPn pins
should be tied to GNDT.
TP Select - Ports 0 - 3. When SD/TPn pins are tied Low, bit 19.2 = 0. The operating mode
of each port can be set to 10BASE-T, 100BASE-TX, or 100BASE-FX via the hardware
I
control interface pins as shown in Table 8 on page 16.
Note: Hardware control interface pins (CFG_0, CFG_1, CFG_2, FDE, BYPSCR, and
AUTOENA) are global and set all ports simultaneously.
In TP mode, network pins operate as described in Tab le 2 .
In FX mode, network pins are re-mapped and operate as described in Table 3.
Signal Description
Table 2. LXT974 Twisted-Pair Interface Signal Descriptions
Pin# Symbol Type
1
Signal Description
154, 157
145, 148
135, 138
126, 129
151, 152
142, 143
132, 133
123, 124
1. Type Column Coding: I = Input, O = Output.
TPOP0, TPON0
TPOP1, TPON1
TPOP2, TPON2
TPOP3, TPON3
TPIP0, TPIN0
TPIP1, TPIN1
TPIP2, TPIN2
TPIP3, TPIN3
Twisted-Pair Outputs, Positive & Negative - Ports 0-3.
O
During 100BASE-TX or 10BASE-T operation, TPO pins drive 802.3 compliant
pulses onto the line.
Twisted-Pair Inputs, Positive & Negative - Ports 0-3.
I
During 100BASE-TX or 10BASE-T operation, TPI pins receive differential
100BASE-TX or 10BASE-T signals from the line.
Table 3. LXT974 Fiber Interface Signal Descriptions
Pin# Symbol Type
154, 157
145, 148
135, 138
126, 129
151, 152
142, 143
132, 133
123, 124
1. Type Column Coding: I = Input, O = Output.
FIBIN0, FIBIP0
FIBIN1, FIBIP1
FIBIN2, FIBIP2
FIBIN3, FIBIP3
FIBOP0, FIBON0
FIBOP1, FIBON1
FIBOP2, FIBON2
FIBOP3, FIBON3
1
Fiber Inputs, Positive & Negative - Ports 0-3.
I
During 100BASE-FX operation, FIBI pins receive differential PECL inputs
from fiber transceivers.
Fiber Outputs, Positive & Negative - Ports 0-3.
O
During 100BASE-FX operation, FIBO pins produce differential PECL
outputs for fiber transceivers.
Signal Description
Datasheet 11
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Figure 3. LXT975 Pin Assignments
160....... GND
159....... TEST
158....... TPIP0
157....... TPIN0
156....... GNDR
155....... TPOP0
154....... VCCT
153....... GNDT
152....... TPON0
151....... VCCR
150....... GNDR
149....... SD1/TP1
148....... TPON/FIBIP1
147....... VCCT
146....... GNDT
145....... TPOP/FIBIN1
144....... VCCR
143....... TPIN/FIBON1
142....... TPIP/FIBOP1
141....... GNDR
140....... RBIAS
139....... TPIP2
138....... TPIN2
137....... GNDR
LED3_0 .....1
LED3_1 .....2
LED3_2 .....3
LED2_0 .....4
LED2_1 .....5
LED2_2 .....6
GND .....7
LED1_0 .....8
LED1_1 .....9
LED1_2 .....10
LED0_0 .....11
LED0_1 .....12
LED0_2 .....13
GND .....14
LEDCLK .....15
LEDDAT .....16
LEDENA .....17
ADD2 .....18
ADD3 .....19
ADD4 .....20
GNDA .....21
VCC .....22
RXD0_3 .....23
RXD0_2 .....24
RXD0_1 .....25
RXD0_0 .....26
RX_DV0 .....27
RX_CLK0 .....28
RX_ER0 .....29
TX_ER0 .....30
TX_CLK0 ..... 31
TX_EN0 .....32
TXD0_0 .....33
TXD0_1 .....34
TXD0_2 .....35
TXD0_3 .....36
COL0 .....37
CRS0 .....38
GND .....39
VCCMII .....40
(Date Code)
(Part#)
(Lot#)
XXXX XXXX
LXT974AHC or
LXT974BHC
XXXXXX
136....... TPOP2
135....... VCCT
134....... GNDT
133....... TPON2
132....... VCCR
131....... GNDR
130....... SD3/TP3
129....... TPON/FIBIP3
128....... VCCT
127....... GNDT
126....... TPOP/FIBIN3
125....... VCCR
124....... TPIN/FIBON3
123....... TPIP/FIBOP3
122....... GNDR
121....... GNDR
120 .......N/C
119 .......N/C
118 .......CLK25M
117 .......FDE_FX
116 .......CFG_0
115 .......CFG_1
114 .......CFG_2
113 .......BYPSCR
112 .......TEST
111 .......AUTOENA
110 .......FDE
109 .......RESET
108 .......GNDH
107 .......VCCH
106 .......TRSTE0
105 .......TRSTE1
104 .......TRSTE2
103 .......TRSTE3
102 .......PWRDN
101 .......TEST
100 .......MDDIS
99 .........MDC
98 .........MDINT
97 .........MDIO
96 .........VCC
95 .........GND
94 .........CRS3
93 .........COL3
92 .........TXD3_3
91 .........TXD3_2
90 .........TXD3_1
89 .........TXD3_0
88 .........TX_EN3
87 .........TX_CLK3
86 .........TX_ER3
85 .........RX_ER3
84 .........RX_CLK3
83 .........RX_DV3
82 .........RXD3_0
81 .........RXD3_1
N/C .................41
RXD1_3 .......... 42
RXD1_2 .......... 43
RXD1_1 .......... 44
RXD1_0 .......... 45
RX_DV1.......... 46
RX_CLK1........ 47
RX_ER1.......... 48
TX_ER1 .......... 49
TX_CLK1 ........ 50
TX_EN1 .......... 51
TXD1_0 ..........52
TXD1_1 ..........53
TXD1_2 ..........54
TXD1_3 ..........55
GND................ 56
COL1 ..............57
CRS1 ..............58
GND................ 59
VCC ................ 60
RXD2_3 .......... 61
RXD2_2 .......... 62
RXD2_1 .......... 63
RXD2_0 .......... 64
RX_DV2.......... 65
RX_CLK2........ 66
RX_ER2.......... 67
TX_ER2 .......... 68
TX_CLK2 ........ 69
TX_EN2 .......... 70
TXD2_0 ..........71
TXD2_1 ..........72
TXD2_2 ..........73
TXD2_3 ..........74
COL2 ..............75
CRS2 ..............76
GND................ 77
VCCMII ........... 78
RXD3_3 .......... 79
RXD3_2 .......... 80
12 Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Table 4. LXT975 Signal Detect/TP Select Signal Descriptions
2
Pin#
149
130
1. Type Column Coding: I = Input, O = Output.
2. When not using fiber mode, SD/TPn pins should be tied to GNDT.
Symbol Type
SD1/TP1
SD3/TP3
1
Signal Detect - Ports 1 & 3. When SD/TPn pins are tied High or to a 5V PECL input, bit
19.2 = 1 and the operating mode of each respective port is forced to FX mode. In this
mode, full-duplex is set via pin 117 (FDE_FX). When not using fiber mode, SD/TPn pins
should be tied to GNDT.
TP Select - Ports 1 & 3. When SD/TPn pins are tied Low, bit 19.2 = 0. The operating mode
of each port can be set to 10BASE-T, 100BASE-TX, or 100BASE-FX via the hardware
I
control interface pins as shown in Table 8 on page 16.
Note: Hardware control interface pins (CFG_0, CFG_1, CFG_2, FDE, BYPSCR, and
AUTOENA) are global and set all ports simultaneously.
In TP mode, network pins operate as described in Tab le 5 .
In FX mode, network pins are re-mapped and operate as described in Table 6.
Signal Description
Table 5. LXT975 Twisted-Pair Interface Signal Descriptions
Pin# Symbol Type
1
Signal Description
155, 152
145, 148
136, 133
126, 129
158, 157
142, 143
139, 138
123, 124
1. Type Column Coding: I = Input, O = Output.
TPOP0, TPON0
TPOP1, TPON1
TPOP2, TPON2
TPOP3, TPON3
TPIP0, TPIN0
TPIP1, TPIN1
TPIP2, TPIN2
TPIP3, TPIN3
Twisted-Pair Outputs, Positive & Negative - Ports 0-3.
O
During 100BASE-TX or 10BASE-T operation, TPO pins drive 802.3 compliant
pulses onto the line.
Twisted-Pair Inputs, Positive & Negative - Ports 0-3.
I
During 100BASE-TX or 10BASE-T operation, TPI pins receive differential
100BASE-TX or 10BASE-T signals from the line.
Table 6. LXT975 Fiber Interface Signal Descriptions
Pin# Symbol Type
145, 148
126, 129
142, 143
123, 124
1. Type Column Coding: I = Input, O = Output.
FIBIN1, FIBIP1
FIBIN3, FIBIP3
FIBOP1, FIBON1
FIBOP3, FIBON3
1
Fiber Network Interface - Ports 1 and 3
I
During 100BASE-FX operation, FIBI pins receive differential PECL inputs
from fiber transceivers.
Fiber Network Interface - Ports 1 and 3
O
During 100BASE-FX operation, FIBO pins produce differential PECL
outputs for fiber transceivers.
Signal Description
Datasheet 13
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Table 7. LXT974 and LXT975 MII Signal Descriptions
3
Pin#
33
34
35
36
52
53
54
55
71
72
73
74
89
90
91
92
32
51
70
88
31
50
69
87
30
49
68
86
26
25
24
23
45
44
43
42
64
63
62
61
82
81
80
79
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
3. Unused pins should be tied Low.
Symbol Type
TXD0_0
TXD0_1
TXD0_2
TXD0_3
TXD1_0
TXD1_1
TXD1_2
TXD1_3
TXD2_0
TXD2_1
TXD2_2
TXD2_3
TXD3_0
TXD3_1
TXD3_2
TXD3_3
TX_EN0
TX_EN1
TX_EN2
TX_EN3
TX_CLK0
TX_CLK1
TX_CLK2
TX_CLK3
TX_ER0
TX_ER1
TX_ER2
TX_ER3
RXD0_0
RXD0_1
RXD0_2
RXD0_3
RXD1_0
RXD1_1
RXD1_2
RXD1_3
RXD2_0
RXD2_1
RXD2_2
RXD2_3
RXD3_0
RXD3_1
RXD3_2
RXD3_3
1
MII Data Interface Pins
I Transmit Data - Port 0. Inputs containing NRZ data to be transmitted from port 0.
I Transmit Data - Port 1. Inputs containing NRZ data to be transmitted from port 1.
I Transmit Data - Port 2. Inputs containing NRZ data to be transmitted from port 2.
I Transmit Data - Port 3. Inputs containing NRZ data to be transmitted from port 3.
Transmit Enable - Ports 0 - 3. Active High input enables respective port transmitter. This
I
signal must be synchronous to the TX_CLK.
Transmit Clock - Ports 0 - 3. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps
operation. The transmit data and control signals must always be synchronized to TX_CLK
by the MAC. The LXT974/975 normally samples these signals on the rising edge of
O
TX_CLK. However, Advanced TX_CLK Mode is available by setting MII register bit 19.5=1.
In this mode, the LXT974/975 samples the transmit data and control signals on the falling
edge of TX_CLK.
Transmit Coding Error - Ports 0 - 3. This signal must be driven synchronously to TX_CLK.
I
When High, forces the respective port to transmit Halt (H) code group.
Receive Data - Port 0. Receive data signals (4-bit parallel nibbles) are driven synchronously
O
to RX_CLK0.
Receive Data - Port 1. Receive data signals (4-bit parallel nibbles) are driven synchronously
O
to RX_CLK1.
Receive Data - Port 2. Receive data signals (4-bit parallel nibbles) are driven synchronously
O
to RX_CLK2.
Receive Data - Port 3. Receive data signals (4-bit parallel nibbles) are driven synchronously
O
to RX_CLK3.
Signal Description
2
14 Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Table 7. LXT974 and LXT975 MII Signal Descriptions (Continued)
Pin#
27
46
65
83
29
48
67
85
28
47
66
84
37
57
75
93
38
58
76
94
3
Symbol Type
RX_DV0
RX_DV1
RX_DV2
RX_DV3
RX_ER0
RX_ER1
RX_ER2
RX_ER3
RX_CLK0
RX_CLK1
RX_CLK2
RX_CLK3
COL0
COL1
COL2
COL3
CRS0
CRS1
CRS2
CRS3
1
Receive Data Valid - Ports 0 - 3. These signals are synchronous to the respective
O
RX_CLKn. Active High indication that received code group maps to valid data.
Receive Error - Ports 0 - 3. These signals are synchronous to the respective RX_CLKn.
O
Active High indicates that received code group is invalid, or that PLL is not locked.
O Receive Clock - Ports 0 - 3. 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.
Collision Detected - Ports 0 - 3. Active High outputs asserted upon detection of a collision.
O
Remain High for the duration of the collision. These signals are generated asynchronously.
Inactive during full-duplex operation.
Carrier Sense - Ports 0 - 3. Active High signals. During half-duplex operation
(bit 0.8 = 0), CRSn is asserted when either transmit or receive medium is non-idle. During
O
full-duplex operation (bit 0.8 = 1), CRSn is asserted only when the receive medium is nonidle.
Signal Description
2
MII Control Interface Pins
97 MDIO I/O
98 MDINT OD
99 MDC I
100 MDDIS I
TRSTE0
106
TRSTE1
105
TRSTE2
104
TRSTE3
103
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
3. Unused pins should be tied Low.
Management Data Input/Output. Bidirectional serial data channel for PHY/STA
communication.
Management Data Interrupt. An active Low output on this pin indicates status change.
Interrupt is cleared by sequentially reading Register 1, then Register 18.
Management Data Clock. Clock for the MDIO serial data channel.
Maximum frequency is 2.5 MHz.
Management Disable.
When MDDIS is High, the MDIO is restricted to Read Only and the Hardware Control
Interface pins provide continual control of their respective bits.
When MDDIS is Low at power up or Reset, the Hardware Control Interface pins control only
the initial or “default” values of their respective register bits. After the power-up/reset cycle is
complete, bit control reverts to the MDIO serial channel.
Tristate - Ports 0 - 3. This bit controls bit 0.10 (Isolate bit). When TRSTEn is High, the
respective port isolates itself from the MII Data Interface.
I
When MDDIS is High, TRSTE provides continuous control over bit 0.10.
When MDDIS is Low, TRSTE sets the initial (default) value of bit 0.10 at Reset and then bit
control reverts back to the MDIO interface.
Datasheet 15
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Table 8. LXT974 and LXT975 Hardware Control Interface Signal Descriptions
Pin# Symbol Type
CFG_0
116
(Global)
CFG_1
115
(Global)
CFG_2
114
(Global)
FDE
110
(Global)
FDE_FX
117
BYPSCR
113
(Global)
AUTOENA
111
(Global)
1. Type Column Coding: I = Input, O = Output, OD = Open Drain.
2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
1
Configuration Control 0.
When A/N is enabled, Low to High transition on CFG_0 causes auto-negotiate to restart on
all ports and 0.9 = 1.
I
When A/N is disabled, this input selects operating speed and directly affects bit 0.13.
When CFG_0 is High, 100 Mbps is selected and bit 0.13 = 1.
When CFG_0 is Low, 10 Mbps is selected and bit 0.13 = 0.
Configuration Control 1.
When A/N is enabled, CFG_1 determines operating speed advertisement capabilities in
combination with CFG_2 and FDE on all ports. See Table 16 on page 26 for details.
I
When A/N is disabled, CFG_1 enables 10 Mbps link test and directly affects bit 19.8.
When CFG_1 is High, 10 Mbps link test is disabled and bit 19.8 = 1.
When CFG_1 is Low, 10 Mbps link test is enabled and bit 19.8 = 0.
Configuration Control 2.
When A/N is enabled, CFG_2 determines operating speed advertisement capabilities in
combination with CFG_1 on all ports. See Table 16 on page 26 for details.
When A/N is disabled, this input selects either TP or FX interface. When FX interface is
selected, the LXT974/975 automatically disables the scrambler. For correct FX operation,
100 Mbps operation must also be selected.
I
Note: It is recommended to set the network interface for each port independently, via the SD/
TPn pins. See Table 1 and Table 4 for Signal Detect / TP Select signal descriptions and
operation.
When CFG_2 is Low, TP is enabled and bit 19.2 = 0.
When CFG_2 is High, FX is enabled and bit 19.2 = 1.
Full-Duplex Enable - All Ports.
I
When High, enables full-duplex operation on all ports.
Full-Duplex Enable - FX Ports only.
I
When High, enables full-duplex operation on all ports set for FX mode operation. This pin is
ignored on ports set for TP mode.
Bypass Scrambler.
In TP mode, enables or bypasses Scrambler operation and directly affects MDIO
register bit 19.3.
When High, Scrambler is bypassed and bit 19.3 = 1.
I
When Low, Scrambler is enabled and bit 19.3 = 0.
In FX mode, the LXT974/975_ automatically bypasses the Scrambler. This pin has no
effect selecting Scrambler bypass.
I Auto-Negotiation Enable. When High, enables auto-negotiation on all ports.
Signal Description
2
16 Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Table 9. LXT974 and LXT975 Miscellaneous Signal Descriptions
Pin# Symbol Type
1
Signal Description
2
ADD1 ADD0 Port
Address <4:2>. Set upper three bits of PHY
20
19
18
101, 112, 159 TEST I Test. Must be tied Low.
140 RBIAS I
118 CLK25M I
109 RESET I
102 PWRDN I
41, 119, 120 N/C - No Connection. Leave open.
1. Type Column Coding: I = Input, O = Output, A = Analog.
2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
ADD4
ADD3
ADD2
I
address. ADD<1:0> are set internally to match
I
port number as shown at right.
I
Bias. This pin provides bias current for the internal circuitry. Must be tied to
ground through a 22 k
Clock Input. A 25 MHz clock input is required at this pin. Refer to Functional
Description for detailed clock requirements.
Reset. This active Low input is OR’ed with the control register Reset bit (0.15).
The LXT974/975 reset cycle is extended 205
asserted.
Power Down. When High, forces LXT974/975 into power down mode. This pin is
OR’ed with the Power Down bit (0.11). Refer to Table 44 on page 64 for more
information.
Ω resistor.
µs (nominal) after Reset is de-
00 0
01 1
10 2
11 3
Table 10. LXT974 and LXT975 LED Indicator Signal Descriptions
2
Pin#
11
12
13
10
17 LEDENA O LED Enable. Active High output signals external device that LEDDAT is active.
15 LEDCLK O LED Clock. 25 MHz clock for LED serial data output.
16 LEDDAT O LED Data. Serial data output for 24 LEDs (6 x 4 ports) data.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain.
2. Unused pins should be tied Low.
3. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
Symbol Type
LED0_0
LED1_0
8
LED2_0
4
LED3_0
1
LED0_1
LED1_1
9
LED2_1
5
LED3_1
2
LED0_2
LED1_2
LED2_2
6
LED3_2
3
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
OD
OD
OD
1
LED0 - Ports 0 - 3. In default mode, active Low output indicates transmitter active. However,
LED0 is programmable and may also be set to indicate receiver active, link status or duplex
status. Refer to LED Configuration Register, Table 51 on page 68, for details on
programming options.
LED1 - Ports 0 - 3. In default mode, active Low output indicates receiver active. However,
LED1 is programmable and may also be set to indicate link status, duplex status, or operating
speed. Refer to LED Configuration Register, Table 51 on page 68, for details on
programming options.
LED2 - Ports 0 - 3. In default mode, active Low output indicates link up. However, LED2 is
programmable and may also be set to indicate duplex status, operating speed or collision.
Refer to LED Configuration Register, Table 51 on page 68, for details on
programming options.
Signal Description
3
Datasheet 17
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Table 11. LXT974 Power Supply Signal Descriptions
Pin# Symbol Type Signal Description
22, 60, 96 VCC - Power Supply. +5V supply for all digital circuits.
40, 78 VCCMII -
7, 14, 39, 56, 59, 77, 95, 160 GND - Digital Ground. Ground return for digital supply.
21 GNDA - Analog Ground. Ground return for analog supply.
108 GNDH - Ground. Ground return for core analog circuitry.
107 VCCH - Supply. +5V supply for core analog circuitry.
128, 137, 147, 156 VCCT - Transmit Power Supply. +5V supply for transmit circuits.
127, 136, 146, 155 GNDT - Transmit Ground. Ground return for transmit supply.
125, 134, 144, 153, VCCR - Receive Power Supply. +5V supply for all receive circuits.
121, 122, 131, 141, 150 GNDR - Receive Ground. Ground return for receive supply.
MII Supply. +3.3V or +5V supply for MII. A decoupling capacitor
to digital ground should be supplied for these pins.
Table 12. LXT975 Power Supply Signal Descriptions
Pin# Symbol Type Signal Description
22, 60, 96 VCC - Power Supply. +5V supply for all digital circuits.
40, 78 VCCMII -
7, 14, 39, 56, 59, 77, 95, 160 GND - Digital Ground. Ground return for digital supply.
21 GNDA - Analog Ground. Ground return for analog supply.
108 GNDH - Ground. Ground return for core analog circuitry.
107 VCCH - Supply. +5V supply for core analog circuitry.
128, 135, 147, 154 VCCT - Transmit Power Supply. +5V supply for transmit circuits.
127, 134, 146, 153 GNDT - Transmit Ground. Ground return for transmit supply.
125, 132, 144, 151, VCCR - Receive Power Supply. +5V supply for all receive circuits.
121, 122, 131, 137, 141, 150, 156 GNDR - Receive Ground. Ground return for receive supply.
MII Supply. +3.3V or +5V supply for MII. A decoupling capacitor
to digital ground should be supplied for these pins.
18 Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
2.0 Functional Description
2.1 Introduction
The LXT974 and LXT975 are four-port Fast Ethernet 10/100 Transceivers that support 10 Mbps
and 100 Mbps networks. They comply with all applicable requirements of IEEE 802.3. Each port
can directly drive either a 100BASE-TX line (>130 meters) or a 10BASE-T line (>185 meters).
Figure 4 shows the LXT974 in a typical switch application.
Figure 4. LXT974 Switch Application
Fiber
Module
Fiber
Module
Fiber
Module
Fiber
Module
LXT974
10/100
Quad Transceiver
LXT974
10/100
Quad Transceiver
Transformer
Backplane
Switch
MAC ASIC
QUAD
Single RJ-45
Selectable 10 or 100 Mbps
Memory
LXT974
10/100
Quad Transceiver
QUAD
Transformer
On power-up, the LXT974/975 uses auto-negotiation/parallel detection on each port to
automatically determine line operating conditions. If the PHY device on the other side of the link
supports auto-negotiation, the LXT974/975 auto-negotiates with it using Fast Link Pulse (FLP)
Bursts. If the PHY partner does not support auto-negotiation, the LXT974/975 automatically
detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set
its operating conditions accordingly.
The LXT974/975 interfaces to four 10/100 Media Access Controllers (MAC)s through the MII
interfaces. It performs all functions of the Physical Coding Sublayer (PCS) and Physical Media
Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device
also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX
connections. The MII speeds are automatically set once port operating conditions have been
determined.
The LXT974/975 provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps. It also
offers standard Loopback Mode for switch applications. The LXT974/975 supports the 802.3
MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is
the register number (0-6 or 16-20) and Y is the bit number (0-15).
The LXT975 is pin compatible with the LXT974 except for the network ports. Each port on the
LXT974 provides a combination twisted-pair or PECL interface for a 10/100BASE-TX or
100BASE-FX connection.
The LXT975 is optimized for stacked RJ-45 modular applications as shown in Figure 5. Ports 1
and 3 support the PECL interface for fiber connections and all four ports support the twisted-pair
interface for 10/100BASE-TX connections.
Datasheet 19
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Figure 5. LXT975 Switch Application
Fiber
Module
Fiber
Module
Fiber
Module
Fiber
Module
LXT974
10/100
Quad Transceiver
LXT975
10/100 Quad
Transceiver
QUAD
Transformer
Backplane
MAC ASIC
LXT975
10/100 Quad
Transceiver
QUAD
Transformer
Stacked RJ-45
10 or 100 Mbps
Switch
Memory
LXT975
10/100 Quad
Transceiver
QUAD
Transformer
LXT975
10/100 Quad
Transceiver
QUAD
Transformer
2.2 Network Media / Protocol Support
The LXT974/975 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100
Mbps Ethernet over fiber media (100BASE-FX). A Media Independent Interface (MII) is used for
communication with the Media Access Controller (MAC).
2.2.1 10/100 Mbps Network Interface
Each of the four network interface ports consists of four external pins (two differential signal
pairs). The pins are shared between twisted-pair (TP) and fiber. Signal assignments (input or
output, positive or negative) vary depending on whether the port is configured for TP or fiber
media. Refer to Table 1 through Table 6 for specific pin assignments.
The LXT974/975 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX
output. When not transmitting data, the LXT974/975 generates 802.3-compliant link pulses or idle
code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input,
depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to
determine the speed of this interface.
2.2.1.1 Twisted-Pair Interface
When operating at 100 Mbps, MLT3 symbols are continuously transmitted and received. When not
transmitting data, the LXT974/975 generates “IDLE” symbols.
During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being
exchanged, the line is left in an idle state.
In 100 Mbps mode, the LXT974/975 is capable of driving a 100BASE-TX connection over 100
Category 5, Unshielded Twisted Pair (UTP). A 10BASE-T connection can be supported using
Ω Category 3, UTP.
100
Ω,
20 Datasheet
Only a transformer (1:1 on receive side, 2:1 on transmit side), load resistors, and bypass capacitors
are needed to complete this interface. Using Intel’s patented waveshaping technology, the
transmitter pre-distorts the outgoing signal to reduce the need for external filters for EMI
compliance.
Ω passive load is always present across the twisted-pair inputs. When enabled, the twisted-
A 4k
pair inputs are actively biased to approximately 2.8V.
2.2.1.2 Fiber Interface
The LXT974/975 provides a PECL interface that complies with the ANSI X3.166 specification.
This interface is suitable for driving a fiber-optic coupler.
The twisted-pair pin assignments are remapped to support the PECL interface. The LXT974
supports both the twisted-pair and fiber interface on all four ports. The LXT975, optimized for TP
operation with dual-high RJ-45 connectors, provides dual interfaces on ports 1 and 3.
During 100BASE-FX operation, the FIBI pins receive differential PECL signals and the FIBO pins
produce differential PECL output signals.
Fiber ports cannot be enabled via auto-negotiation; they must be enabled via the Hardware Control
Interface or MDIO registers.
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
2.2.2 MII Interface
The LXT974/975 supports four standard MIIs (one per port). This interface consists of a data
interface and a management interface. The MII Data Interface passes data between the LXT974/
975 and one or more Media Access Controllers (MACs). Separate signals are provided for
transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set
automatically, once the operating conditions of the network link have been determined.
Nine signals are used to pass received data to the MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER,
COL and CRS. Seven signals are used to transmit data from the MAC: TXD<3:0>, TX_CLK,
TX_EN, and TX_ER.
2.2.2.1 MII Data Interface
Figure 6 shows the data portion of the MII interface. Separate channels are provided for
transmitting data from the MAC to the LXT974/975 (TXD), and for receiving data (RXD) from the
line.
Each channel has its own clock, data bus, and control signals. The LXT974/975 supplies both
clock signals as well as separate outputs for carrier sense and collision. Data transmission across
the MII is implemented in 4-bit-wide nibbles.
Tristating the MII
The LXT974/975 asserts RX_DV, RXD, RX_CLK and RX_ER as soon as it receives a packet from
the network. When TRSTEn is High, the associated port output signals are tristated.
Datasheet 21
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Figure 6. MII Data Interface
TX_CLKn
TX_ENn
TXD<3:0>n
LXT974/975
TX_ERn
RX_CLKn
RX_DVn
RXD<3:0>n
RX_ERn
CRSn
COLn
Media Access
Controller
MAC
Transmit Clock
The LXT974/975 is the master clock source for data transmission. The LXT974/975 automatically
sets the speed of TX_CLK to match port conditions. If the port is operating at 100 Mbps, TX_CLK
is set to 25 MHz. If the port is operating at 10 Mbps, TX_CLK is set to 2.5 MHz. The transmit data
and control signals must always be synchronized to TX_CLK by the MAC. The LXT974/975
normally samples these signals on the rising edge of TX_CLK.
However, Advanced TX_CLK Mode is available by setting MII register bit 19.5=1. In this mode,
the LXT974/975 samples the transmit data and control signals on the falling edge of TX_CLK.
When operating under MDIO Control, the user can advance the transmit clock relative to
TXD<3:0> and TX_ER. When Advance TX_CLK Mode is selected, the LXT974/975 clocks TXD
data in on the falling edge of TX_CLK, instead of the rising edge. This mode provides an increase
in timing margins of TXD, relative to TX_CLK. Advance TX_CLK Mode is enabled when bit 19.5
= 1.
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN
after the last bit of the packet.
Receive Data Valid
The LXT974/975 asserts RX_DV when it receives a valid packet. Timing changes depend on line
operating speed:
• For 100TX and 100FX links, RX_DV is asserted from the first nibble of preamble to the last
nibble of the data packet.
• For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of
the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
Error Signals
Whenever the LXT974/975 receives an errored symbol from the network, it asserts RX_ER and
drives “1110” on the RXD pins.
When the MAC asserts TX_ER, the LXT974/975 drives “H” symbols out on the line.
22 Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Carrier Sense
Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received
from the line and in some modes when a packet is transmitted.
On transmit, CRS is asserted on a 10 Mbps or 100 Mbps half-duplex link. Carrier sense is not
generated on transmit when the link is operating in full-duplex mode.
Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:
• De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to
appear somewhat shorter to the MAC than it actually is on the wire.
• CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-
duplex mode.
Operational Loopback
Operational loopback is provided for 10 Mbps half-duplex links when bit 19.11 = 0. Data
transmitted by the MAC is looped back on the receive side of the MII. Operational loopback is not
provided for 100 Mbps links, full-duplex links, or when 19.11 = 1.
Test Loopback
A test loopback function is provided for diagnostic testing of the LXT974/LXT975. During test
loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally
looped back by the LXT974/975 and returned to the MAC.
Test loopback is available for 100TX, 100FX, and 10T operation. Test loopback is enabled by
setting bit 0.14 = 1, bit 0.8 = 1 (full-duplex), and bit 0.12 = 0 (disable auto-negotiation). The
desired mode of operation for test loopback is set using bits 0.13 and 19.2 as shown in Table 13.
Loopback paths for the three modes of operation are shown in Figure 7.
Table 13. Test Loopback Operation
Mode of Operation
10T Test Loopback 0 0
100TX Test Loopback 0 1
100FX Test Loopback 1 1
1. Bit 0.14 = 1, bit 0.8 = 1, and 0.12 = 0 must also be set to enable Test Loopback.
Bit
19.2 0.13
Datasheet 23
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