The Intel® Desktop Board D850GB may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized
errata are documented in the Intel Desktop Board D850GB Specification Update.
Order Number A26080-002
Revision History
Revision Revision History Date
-001 First release of the Intel® Desktop Board D850GB Technical Product
Specification.
-002 Second release of the Intel Desktop Board D850GB Technical Product
Specification. Changes include (but not limited to) the following:
• Added caution statement in processor section regarding the use of
ATX12V-compliant power supplies
• Changed Firmware Hub component to SST 49LF004A
• Added AD1885 analog codec as an option to audio subsystem
• Listed Diagnostic LEDs as a manufacturing option
• Updated fan connector section
• Updated BIOS Setup program chapter to reflect latest version of BIOS
• Included document changes from the most recent specification update
This product specification applies to only standard D850GB boards with BIOS identifier
GB85010A.86A.
Changes to this specification will be published in the Intel Desktop Board D850GB Specification
Update before being incorporated into a revision of this document.
September 2000
April 2001
Information in this doc um ent is provided in connection wi t h Intel
otherwise, to any intell ectual property rights is granted by this document. E x cept as provided in Intel’s Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and I nt el dis claims any express or implied
warranty, relating to sale and/or use of I ntel products including liability or warranties relat i ng t o f i t ness for a particular
purpose, merchantability, or infringement of any patent, copyright or other int ellec t ual propert y right. Intel products are not
intended for use in medical, l i f e saving, or life sustai ni ng appl i cations.
Intel may make changes t o specifications and produc t descriptions at any tim e, without notice.
®
The Intel
deviate from published spec i fications. Current charac terized errata are available on request.
Contact your local Int el sales office or your distributor to obtain the latest specifications before pl acing your product order.
Copies of documents whic h hav e an orderi ng number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
Third-party brands and names are the property of their respective owners.
Copyright 2000, 2001, Intel Corporat i on. All rights reserved.
Desktop Board D850GB may contain design defects or errors k nown as errata that may cause the produc t to
®
products. No license, express or implied, by est oppel or
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for the Intel Desktop Board D850GB. It
describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the D850GB board and its
components to the vendors, system integrators, and other engineers and technicians who need this
level of information. It is specifically not intended for general audiences.
What This Document Contains
Chapter Description
1 A description of the hardware used on the D850GB board
2 A map of the resources of the board
3 The features supported by the BIOS Setup program
4 The contents of the BIOS Setup program’s menus and submenus
5 A description of the BIOS error messages, beep codes, POST codes, and diagnostic
LEDs
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
# Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX) When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the D850GB board, and X is the instance of the particular part at
that general location. For example, J5J1 is a connector, located at 5J. It is the first connector
in the 5J area.
GB Gigabyte (1,073,741,824 bytes)
GB/sec Gigabytes per second
KB Kilobyte (1024 bytes)
Kbit Kilobit (1024 bits)
kbits/sec 1000 bits per second
MB Megabyte (1,048,576 bytes)
MB/sec Megabytes per second
Mbit Megabit (1,048,576 bits)
Mbit/sec Megabits per second
xxh An address or data value ending with a lowercase h indicates a hexadecimal value.
x.x V Volts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
Table 1 summarizes the D850GB board’s major features.
Table 1. Feature Summary
Form Factor
Processor
Memory
Chipset
I/O Control
Video
Peripheral
Interfaces
Expansion
Capabilities
BIOS
Instantly Available
PC
Wake on LAN†
Technology
Connector
Hardware
Monitoring features
Enhanced thermal
monitor and fan
control device
For information about Refer to
The board’s compliance level with APM, ACPI, Plug and Play, and SMBIOS. Section 1.3, page 16
ATX (12.0 inches by 9.6 inches)
• Support for an Intel
• 400 MHz system data bus
• Two Direct-RDRAM banks with two RIMM
• Support for up to 2 GB of system memory using PC600 or PC800 RDRAM
Intel® 850 Chipset, consisting of:
®
• Intel
• Intel
• SST 49LF004A 4 Mbit Firmware Hub (FWH)
SMSC LPC47M102 LPC bus I/O controller
• AGP connector supporting 1.5 V 4X AGP cards
• Four Universal Serial Bus (USB) ports
• One serial port
• One parallel port
• Two IDE interfaces with Ultra DMA, ATA-33/66/100 support
• One diskette drive interface
• PS/2
• Five PCI bus add-in card connectors (SMBus routed to PCI bus connector 2)
• Intel/AMI BIOS (resident in the SST 49LF004A 4 Mbit FWH)
• Support for Advanced Power Management (APM), Advanced Configuration and
• Support for
• Suspend to RAM support
• Wake on PCI, CNR, RS-232, front panel, PS/2 keyboard, and USB ports
Support for system wake up using an add-in network interface card with remote
wake up capability
Two fan sense inputs used to monitor fan activity
• Two additional fan sense inputs
• Two additional thermal sense inputs
82850 Memory Controller Hub (MCH)
®
82801BA I/O Controller Hub (ICH2)
†
keyboard and mouse ports
Power Interface (ACPI), Plug and Play, and SMBIOS
PCI Local Bus Specification Revision 2.2
®
Pentium® 4 processor
†
s per bank (four RIMM sockets)
12
Product Description
1.1.2 Manufacturing Options
Table 2 describes the D850GB board’s manufacturing options. Not every manufacturing option is
available in all marketing channels. Please contact your Intel representative to determine which
manufacturing options are available to you.
Table 2. Manufacturing Options
Audio (Integrated)
Video
LAN
Hardware Monitor
Subsystem
CNR
Diagnostic LEDs
Audio subsyst em that uses the Analog Devices AD1881/AD1885 analog codec for
AC 97 processing
AGP Pro50 interface (50 W maximum); backward compatible with 1.5 V AGP video
cards.
This option uses an AGP Pro 1.5 V connector, also known as an AGP Pro50
connector.
®
Intel
82562EM 10/100 Mbit/sec Platform LAN Connect (PLC) device
Heceta 4 Hardware Monitor:
• Voltage sense to detect out of range power supply voltages
• Thermal sense to detect out of range thermal values
One Communication and Networking Riser (CNR) connector (slot shared with PCI
bus connector 5, J4A1)
Figure 1 shows the location of the major components on the D850GB board.
B
C
DA
E
V
U
F
G
T
S
H
I
R
Q
PLJO
N
M
K
A AD1881/AD1885 audio codec (optional) L Diskette drive connector
B AGP connector (AGP Pro 1.5V connector
optional)
C Intel 82850 Memory Controller Hub (MCH) O SMSC LPC47M102 I/O Controller
D Back panel connectors P Front panel connector
E +12V power connector (ATX12V) Q Enhanced thermal monitor and fan control device
F Pentium 4 Processor socket R Battery
G Hardware monitor S SST 49LF004A 4 Mbit Firmware Hub (FWH)
†
H RAMBUS
I RAMBUS Bank 1 (RIMM3 and RIMM4) U PCI bus add-in card connectors
J K Power connector
Auxiliary Power connector
Bank 0 (RIMM1 and RIMM2) T Speaker
M N IDE connectors
Intel 82801BA I/O Controller Hub (ICH2)
V Communication and Networking Riser (CNR)
connector (optional)
OM10441
Figure 1. D850GB Board Components
14
1.1.4 Block Diagram
Figure 2 is a block diagram of the major functional areas of the D850GB board.
Version 2.3.1,
March 16, 1999,
American Megatrends Inc.,
Award Software International Inc.,
Compaq Computer Corporation
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
and SystemSoft Corporation.
Version 1.1,
March 1996,
Intel Corporation
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation,
Microsoft Corporation, and
NEC Corporation
Version 2.0,
December 18, 1998,
Intel Corporation
The information is
available from…
http://developer.intel.com/
ial/wfm/design/smbios
http://www.usb.org/
developers
http://www.usb.org/
developers
http://developer.intel.com/
ial/WfM/wfmspecs.htm
18
Product Description
1.4 Processor
CAUTION
Use only the processors listed below. Use of unsupported processors can damage the D850GB
®
board, the processor, and the power supply. See the Intel
Update for the most up-to-date list of supported processors for the D850GB board.
The D850GB board supports a single Pentium 4 processor with a system bus of 400 MHz. The
D850GB board supports the processors listed in Table 4. All supported onboard memory can be
cached, up to the cachability limit of the processor. See the processor’s data sheet for cachability
Use only an ATX12V-compliant power suppIy with this board. ATX12V power supplies have two
additional power leads that provide required supplemental power for the Intel Pentium
processor and the Intel 850 chipset. Always connect both additional power supply leads of the
ATX12V power supply, otherwise the board and the processor could be damaged.
Desktop Board 850GB Specification
4
Do not use a standard ATX power supply. Doing so could damage the board and the processor.
For information about Refer to
Processor support Section 1.2, page 16
Processor usage Section 1.2, page 16
Power supply connectors Section 2.8.2.3, page 56
Turn off the power and unplug the power cord before installing or removing RIMM modules.
Failure to do so could damage the memory and the D850GB board. (After removing AC power the
standby power indicator LED should not be lit. See Figure 7 on page 40 for the location of the
standby power indicator LED.)
NOTE
✏
The board supports combinations of no more than 32 RDRAM components per RDRAM bank. If
the total number of RDRAM components installed in all RIMM sockets exceeds 64, the computer
will not boot.
1.5.1 Memory Features
The 82850 Memory Controller Hub integrates two lock-stepped Direct Rambus banks, providing a
processor-to-memory bandwidth up to 3.2 GB/sec. The D850GB board has four RIMM sockets
(two sockets for each bank) and supports the following memory features:
• Single- or double-sided RIMM configurations
• Maximum of 32 Direct Rambus devices per bank
• Memory configurations from 128 MB (minimum) to 2 GB (maximum) utilizing 128 Mbit or
256 Mbit technology PC600 or PC800 compliant RDRAM
• Serial Presence Detect (SPD) based configuration for optimal memory operation
• Suspend to RAM support
• ECC and non-ECC support
1.5.2 Continuity RIMM Modules
All RIMM sockets must be populated to achieve continuity for termination at the Rambus
interface. Continuity RIMMs (or “pass-through” modules) must be installed in the second
RDRAM bank if memory is not installed. If any of the RIMM sockets are not populated, the
computer will not complete the Power-On Self-Test (POST) and the BIOS beep codes will not be
heard.
20
Product Description
1.5.3 RDRAM Memory Configuration
When installing memory, note the following:
• The four RIMM sockets are grouped into two banks:
Bank 0 (labeled on the board as RIMM1 and RIMM2)
Bank 1 (labeled on the board as RIMM3 and RIMM4)
• Bank 0 must be populated first ensuring that the RDRAM installed in RIMM1 and RIMM2 is
identical in speed, size, and density. For example, the minimum system configuration would
use two 64 MB RIMM modules of PC600 or PC800 RDRAM.
• If the desired memory configuration has been achieved by populating Bank 0, then Bank 1
should be filled with two Continuity RIMMs.
• If memory is to be installed in Bank 1, the RIMM modules installed in RIMM3 and RIMM4
must be identical in size and density to each other, and match the speed of the RIMM modules
in Bank 0. The RIMM modules do not, however, need to match those in Bank 0 in size and
density. For example, if Bank 0 has two 128 MB RIMMs of PC800 RDRAM, Bank 1 would
require PC800 RDRAM also, however, any other supported RIMM modules such as 64 MB or
192 MB could be used.
• If ECC functionality is required, all installed RIMM modules must be ECC-compliant
Table 5 gives examples of RDRAM component density for various RIMM modules. Component
density (counts) can be identified on the RIMM label.
The Intel 850 chipset consists of the following devices:
• 82850 Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus
• 82801BA I/O Controller Hub (ICH2) with AHA bus
• SST 49LF004A Firmware Hub (FWH)
The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
Accelerated Hub Architecture interface. The ICH2 is a centralized controller for the board’s I/O
paths. The FWH provides the nonvolatile storage of the BIOS. The component combination
provides the chipset interfaces as shown in Figure 3.
ATA-33/66/100
System Bus
Network
USB
850 Chipset
82850
Memory Controller
Hub (MCH)
Dual RAMBUS
Channels
AHA
Bus
AGP
Interface
82801BA
I/O Controller Hub
(ICH2)
SST 49LF004A
Firmware Hub
(FWH)
LPC Bus
AC LinkPCI BusSMBus
OM11732
Figure 3. Intel 850 Chipset Block Diagram
For information about Refer to
The Intel 850 chipset http://developer.intel.com
The SST 49LF004A Firmware Hub http://www.ssti.com
Chipset resources Section 1.3, page 16
22
Product Description
1.6.1 AGP
NOTE
✏
The AGP connector is keyed for 1.5 V AGP cards only. Do not attempt to install a legacy 3.3 V
AGP card. The AGP connector is not mechanically compatible with legacy 3.3 V AGP cards.
The AGP connector supports AGP add-in cards with 1.5 V Switching Voltage Level (SVL). An
AGP Pro50 interface is available (for a 50 W maximum power draw) as a manufacturing option.
Legacy 3.3 V AGP cards are not supported and will prevent the system from booting if installed.
For information about Refer to
The location of the AGP connector Figure 1, page 14
The signal names of the AGP connector Table 40, page 62
AGP is a high-performance interface for graphics-intensive applications, such as 3D applications.
While based on the PCI Local Bus Specification, Rev. 2.1, AGP is independent of the PCI bus and
is intended for exclusive use with graphical display devices. AGP overcomes certain limitations of
the PCI bus related to handling large amounts of graphics data with the following features:
• Pipelined memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for nearly 100 percent efficiency
For information about Refer to
Obtaining the
Accelerated Graphics Port Interface Specification
Section 1.3, page 16
1.6.2 USB
The ICH2 contains two separate USB controllers supporting four USB ports. One USB peripheral
can be connected to each port. For more than four USB devices, an external hub can be connected
to any of the ports. Two of the USB ports are implemented with stacked back panel connectors.
The other two are accessible via the front panel USB connector at location J9C1. One of the front
panel USB connectors can be routed to the optional CNR connector. The D850GB board fully
supports UHCI and uses UHCI-compatible software drivers.
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device is attached to the cable. Use shielded cable that meets the
requirements for full-speed devices.
For information about Refer to
The location of the USB connectors on the back panel Figure 8, page 50
The signal names of the back panel USB connectors Table 18, page 51
The location of the front panel USB connector Figure 12, page 65
The signal names of the front panel USB connector Table 44, page 66
The USB specification and UHCI Section 1.3, page 16
The ICH2’s IDE controller has two independent bus-mastering IDE interfaces that can be
independently enabled. The IDE interfaces support the following modes:
• Programmed I/O (PIO): processor controls data transfer.
• 8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH2’s ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to
88 MB/sec.
✏ NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce reflections,
noise, and inductive coupling.
The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using
the transfer modes listed in Section 4.4.3.1 on page 98.
The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The D850GB board supports Laser Servo (LS-120) diskette technology through its IDE interfaces.
An LS-120 drive can be configured as a boot device by setting the BIOS Setup program’s Boot
menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information about Refer to
The location of the IDE connectors Figure 11, page 59
The signal names of the IDE connectors Table 41, page 63
BIOS Setup program’s Boot menu Table 73, page 105
24
Product Description
1.6.3.2 SCSI Hard Drive Activity LED Connector
The SCSI hard drive activity LED connector is a 1 x 2-pin connector that allows an add-in
SCSI controller to use the same LED as the onboard IDE controller. For proper operation, this
connector should be wired to the LED output of the add-in SCSI controller. The LED indicates
when data is being read from, or written to, both the add-in SCSI controller and the IDE controller.
For information about Refer to
The location of the SCSI hard drive activity LED connector Figure 12, page 65
The signal names of the SCSI hard drive activity LED connector Table 43, page 66
1.6.4 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock provides a time-of-day clock and a multicentury calendar with alarm features.
The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are
reserved for BIOS use.
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
✏ NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS
RAM at power-on.
For information about Refer to
Proper date access in systems with D850GB boards Section 1.2, page 16
1.6.5 SST 49LF004A 4 Mbit Firmware Hub (FWH)
The FWH provides the following:
• System BIOS program
• System security and manageability logic that enables protection for storing and updating of
The SMSC LPC47M102 I/O controller provides the following features:
• 3.3 V operation
• One serial port
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
• Serial IRQ interface compatible with serialized IRQ support for PCI systems
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.2 MB or 1.44 MB diskette drive
• Intelligent power management, including a programmable wake up event interface
• PCI power management support
• One fan tachometer input
The BIOS Setup program provides configuration options for the I/O controller.
For information about Refer to
SMSC LPC47M102 I/O controller http://www.smsc.com
1.7.1 Serial Port
The D850GB board has one serial port connector on the back panel. The serial port’s NS16C550compatible UART supports data transfers at speeds up to 115.2 kbits/sec with BIOS support. The
serial port can be assigned as COM1 (3F8h), COM2 (2F8h), COM3 (3E8h), or COM4 (2E8h).
For information about Refer to
The location of the serial port connector Figure 8, page 50
The signal names of the serial port connector Table 20, page 52
1.7.2 Parallel Port
The 25-pin D-Sub parallel port connector located on the back panel. In the BIOS Setup program,
the parallel port can be set to the following modes:
†
• Output only (PC AT
• Bi-directional (PS/2 compatible)
• EPP
• ECP
For information about Refer to
The location of the parallel port connector Figure 8, page 50
The signal names of the parallel port connector Table 19, page 51
Setting the parallel port’s mode Table 65, page 95
-compatible mode)
26
Product Description
1.7.3 Diskette Drive Controller
The I/O controller supports one diskette drive that is compatible with the 82077 diskette drive
controller and supports both PC-AT and PS/2 modes.
For information about Refer to
The location of the diskette drive connector Figure 11, page 59
The signal names of the diskette drive connector Table 42, page 64
The supported diskette drive capacities and sizes Table 68, page 100
1.7.4 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these
†
connectors are protected with a PolySwitch
connection after an overcurrent condition is removed.
NOTE
✏
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top
PS/2 connector. Power to the computer should be turned off before a keyboard or mouse is
connected or disconnected.
circuit that, like a self-healing fuse, reestablishes the
The keyboard controller contains the AMI keyboard and mouse controller code, provides the
keyboard and mouse control functions, and supports password protection for power-on/reset. A
power-on/reset password can be specified in the BIOS Setup program.
For information about Refer to
The location of the keyboard and mouse connectors Figure 8, page 50
The signal names of the keyboard and mouse connectors Table 17, page 51
The pins on both the legacy-style 2-mm and the ATAPI CD-ROM connectors are wired to the same
inputs on the audio mixer. Do not attach CD-ROM drives to both connectors, otherwise, the board
or drives could be damaged.
The audio subsystem includes these features:
• Split digital/analog architecture for improved S/N (signal-to-noise) ratio: ≥ 85 dB
• Power management support for APM 1.2 and ACPI 1.0 (driver dependant)
• 3-D stereo enhancement
Even though all connectors may not appear on all boards, the audio subsystem supports the
following audio interfaces:
• CD-ROM (legacy-style 2-mm connector)
• ATAPI-style connectors:
CD-ROM
Auxiliary line in
• Back panel audio connectors:
Line out
Line in
Mic in
The audio subsystem consists of the following devices:
• Intel 82801BA I/O Controller Hub (ICH2)
• Analog Devices AD1881/AD1885 analog codec
Figure 4 is a block diagram of the audio subsystem.
82801BA
I/O Controller Hub
(ICH2)
Figure 4. Audio Subsystem Block Diagram
For information about Refer to
The back panel audio connectors Section 2.8.1, page 50
The Network Interface Controller subsystem consists of the ICH2 (with integrated LAN Media
Access Controller) and a physical layer interface device. Features of the LAN subsystem include:
• PCI Bus Master interface
• CSMA/CD Protocol Engine
• Serial CSMA/CD unit interface that supports the following physical layer interface devices:
82562EM onboard LAN
82562ET/EM (10/100 Mbit/sec Ethernet) on CNR bus
†
82562EH (1 Mbit/sec HomePNA
• PCI Power Management
Supports APM
Supports ACPI technology
Supports Wake up from suspend state (Wake on LAN
1.9.1 Intel® 82562EM Platform LAN Connect Device (Optional)
) on CNR bus
†
technology)
The Intel 82562EM component provides an interface to the back panel RJ-45 connector with
integrated LEDs. This physical interface may alternately be provided through the CNR connector.
The Intel 82562EM provides the following functions:
• Basic 10/100 Ethernet LAN connectivity
• Supports RJ-45 connector with status indicator LEDs on the back panel
• Full device driver compatibility
• Advanced Power Management and ACPI support
• Programmable transit threshold
• Configuration EEPROM that contains the MAC address
• Remote monitoring (alerting)
1.9.2 RJ-45 LAN Connector with Integrated LEDs (Optional)
Two LEDs are built into the RJ-45 LAN connector. Table 6 describes the LED states when the
board is powered up and the LAN subsystem is operating.
Table 6. LAN Connector LED States
LED Color LED State Condition
Off 10 Mbit/sec data rate is selected. Green
On 100 Mbit/sec data rate is selected.
Yellow
Off LAN link is not established.
On (steady state) LAN link is established.
On (brighter and pulsing) The computer is communicating with another computer on
the LAN.
30
Product Description
1.9.3 LAN Subsystem Software
LAN software and drivers are available from Intel’s World Wide Web site.
For information about Refer to
Obtaining LAN software and drivers Section 1.2, page 16
1.10 CNR (Optional)
The CNR connector provides an interface that supports the audio, modem, USB, and LAN
interfaces of the Intel 850 chipset. Figure 5 shows the signal interface between the riser and the
ICH2.
Intel 82801BA
I/O Controller Hub
(ICH2)
Figure 5. ICH2 and CNR Signal Interface
AC ’97 Interface
LAN Interfaces
SMBus
USB
Power
Communication and
Networking Riser
(Up to two AC ’97 codecs
and one LAN device)
CNR Connector
OM10412
The interfaces supported by the CNR include the following:
• AC ’97 interface: supports audio and/or modem functions on the CNR board.
• LAN interfaces: provides one of two LAN interfaces for networking functions. Interfaces
include an eight-pin interface for use with Platform LAN Connection (PLC) based devices, and
a 17-pin interface for Media Independent Interface (MII) based devices (commonly referred to
as a PHY).
• SMBus interface: provides Plug-and-Play functionality for the CNR board.
• USB interface: provides a USB interface for the CNR board.
The CNR connector includes power signals required for power management and for CNR board
operation. To learn more about the CNR, refer to the CNR specification.
NOTE
✏
If you install a CNR card with an audio codec that cannot support a mutilchannel audio upgrade,
the D850GB board’s integrated audio codec will be disabled. This only applies to D850GB
boards that have both the onboard audio subystem and a CNR.
For information about Refer to
Obtaining the CNR specification Section 1.3, page 16
The hardware management features enable the board to be compatible with the Wired for
Management (WfM) specification. The board has several hardware management features,
including the following:
• Fan control and monitoring
• Thermal and voltage monitoring
For information about Refer to
The WfM specification Table 3, page 16
1.11.1 Hardware Monitor Component
The hardware monitor component provides low-cost instrumentation capabilities. The features of
the component include:
• Internal ambient temperature sensing
• Remote thermal diode sensing for direct monitoring of processor temperature
• Power supply monitoring (+5 V, +3.3 V, +2.5 V, 3.3 VSB, Vccp) to detect levels above or
below acceptable values
• SMBus interface
1.11.2 Fan Control and Monitoring
The SMSC LPC47M102 I/O controller provides one fan tachometer input. The enhanced thermal
monitor and fan control device provides two fan sense inputs and two fan control outputs.
Monitoring and control can be implemented using third-party software.
For information about Refer to
The functions of the fan connectors Section 1.12.2.2, page 38
The location of the fan connectors Figure 10, page 56
The signal names of the fan connectors Section 2.8.2.2, page 54
32
1.12 Power Management
Power management is implemented at several levels, including:
• Software support:
Advanced Power Management (APM)
Advanced Configuration and Power Interface (ACPI)
• Hardware support:
Power connector
Fan connectors
Wake on LAN technology
Instantly Available technology
Resume on Ring
Wake from USB
Wake from PS/2 keyboard
PME# wakeup support
Product Description
1.12.1 Software Support
The software support for power management includes:
• APM
• ACPI
If an ACPI-aware operating system is used, the BIOS can provide ACPI support. Otherwise, it
defaults to APM support.
1.12.1.1 APM
APM makes it possible for the computer to enter an energy-saving standby mode. The standby
mode can be initiated in the following ways:
• Time-out period specified in the BIOS Setup program
†
• From the operating system, such as the Standby menu item in Windows
In standby mode, the D850GB board can reduce power consumption by spinning down hard
drives, and reducing power to, or turning off of, VESA
†
DPMS-compliant monitors. Power
management mode can be enabled or disabled in the BIOS Setup program.
While in standby mode, the system retains the ability to respond to external interrupts and service
requests, such as incoming faxes or network messages. Any keyboard or mouse activity brings the
system out of standby mode and immediately restores power to the monitor.
The BIOS enables APM by default, but the operating system must support an APM driver for the
power management features to work. For example, Windows 98 supports the power management
features upon detecting that APM is enabled in the BIOS.
For information about Refer to
Enabling or disabling power management in the BIOS Setup program Table 72, page 104
The D850GB board’s compliance level with APM Table 3, page 16
1.12.1.2 ACPI
ACPI gives the operating system direct control over the power management and Plug and Play
functions of a computer. The use of ACPI with the D850GB board requires an operating system
that provides full ACPI support. ACPI features include:
• Plug and Play (including bus and device enumeration) and APM support (normally contained
in the BIOS)
• Power management control of individual devices, add-in boards (some add-in boards may
require an ACPI-aware driver), video displays, and hard disk drives
• Methods for achieving less than 15-watt system operation in the power-on/standby sleeping
state
• A Soft-off feature that enables the operating system to power-off the computer
• Support for multiple wake up events (see Table 9 on page 36)
• Support for a front panel power and sleep mode switch. Table 7 lists the system states based
on how long the power switch is pressed, depending on how ACPI is configured with an
ACPI-aware operating system.
Table 7. Effects of Pressing the Power Switch
If the system is in this state…
Off
(ACPI G2/G5 – Soft off)
On
(ACPI G0 – working state)
On
(ACPI G0 – working state)
Sleep
(ACPI G1 – sleeping state)
Sleep
(ACPI G1 – sleeping state)
…and the power switch is
pressed for
Less than four seconds Power-on
Less than four seconds Soft-off/Standby
More than four seconds Fail safe power-off
Less than four seconds Wake up
More than four seconds Power-off
…the system enters this state
(ACPI G0 – working state)
(ACPI G1 – sleeping state)
(ACPI G2/G5 – Soft off)
(ACPI G0 – working state)
(ACPI G2/G5 – Soft off)
For information about Refer to
The D850GB board’s compliance level with ACPI Section 1.3, page 16
34
Product Description
1.12.1.2.1 System States and Power States
Under ACPI, the operating system directs all system and device power state transitions. The
operating system puts devices in and out of low-power states based on user preferences and
knowledge of how devices are being used by applications. Devices that are not being used can be
turned off. The operating system uses information from applications and user settings to put the
system as a whole into a low-power state.
Table 8 lists the power states supported by the D850GB board along with the associated system
power targets. See the ACPI specification for a complete description of the various system and
power states.
Table 8. Power States and Targeted System Power
Global States Sleeping States
G0 – working
state
G1 – sleeping
state
G1 – sleeping
state
G1 – sleeping
state
G2/S5 S5 – Soft off.
G3 –
mechanical off
AC power is
disconnected
from the
computer.
Notes:
1. Total system power is dependent on the system configuration, including add-in boards and peripherals powered
by the system chassis’ power supply.
2. Dependent on the standby power consumpt i on of wake-up devices used in the system.
S0 – working C0 – working D0 – working
S1 – Processor
stopped
S3 – Suspend to
RAM. Context
saved to RAM.
S4 – Suspend to
disk. Context
saved to di sk.
Context not saved.
Cold boot is
required.
No power to the
system.
Processor
States
C1 – stop
grant
No power D3 – no power
No power D3 – no power
No power D3 – no power
No power D3 – no power for
Device States
state.
D1, D2, D3 –
device
specification
specific.
except for wake
up logic.
except for wake
up logic.
except for wake
up logic.
wake up logic,
except when
provided by
battery or external
source.
Targeted System
(Note 1)
Power
Full power > 30 W
5 W < power < 52.5 W
Power < 5 W
Power < 5 W
Power < 5 W
No power to t he system so
that service can be
performed.
Table 9 lists the devices or specific events that can wake the computer from specific states.
Table 9. Wake Up Devices and Events
These devices/events can wake up the computer… …from this state
Power switch S1, S3, S4, S5
RTC alarm S1, S3, S4, S5
LAN S1, S3, S4, S5
CNR S1, S3 , S4, S5
PME# S1, S3, S4, S5
Modem (back panel Serial Port A) S1, S3
IR command S1, S3
USB S1, S3
PS/2 keyboard S1, S3
Note: For LAN and PM E #, S5 is disabled by default in the BIOS S et up program. Setting this option to Power On will
enable a wake-up event from LAN in the S 5 state.
(Note)
NOTE
✏
The use of these wake up events from an ACPI state requires a properly configured operating
system that provides full ACPI support. In addition, software, drivers, and peripherals must fully
support ACPI wake events.
1.12.1.2.3 Plug and Play
In addition to power management, ACPI provides control information so that operating systems
can facilitate Plug and Play. ACPI is used only to configure devices that do not use other hardware
configuration standards. PCI devices for example, are not configured by ACPI.
36
Product Description
1.12.2 Hardware Support
CAUTION
Ensure that the power supply provides adequate +5 V standby current if the Wake on LAN and
Instantly Available technology features are used. Failure to do so can damage the power supply.
The total amount of standby current required depends on the wake devices supported and
manufacturing options. Refer to Section 2.11.3 on page 73 for additional information.
The D850GB board provides several power management hardware features, including:
• Power connector
• Fan connectors
• Wake on LAN technology
• Instantly Available technology
• Resume on Ring
• Wake from USB
• Wake from PS/2 keyboard
• PME# wakeup support
Wake on LAN technology and Instantly Available technology require power from the +5 V
standby line. The sections discussing these features describe the incremental standby power
requirements for each.
Resume on Ring enables telephony devices to access the computer when it is in a power-managed
state. The method used depends on the type of telephony device (external or internal) and the
power management mode being used (APM or ACPI).
NOTE
✏
The use of Resume on Ring and Wake from USB technologies from an ACPI state requires an
operating system that provides full ACPI support.
1.12.2.1 Power Connector
When used with an ATX12V-compliant power supply that supports remote power on/off, the
D850GB board can turn off the system power through software control. To enable soft-off control
in software, advanced power management must be enabled in the BIOS Setup program and in the
operating system. When the system BIOS receives the correct APM command from the operating
system, the BIOS turns off power to the computer.
With soft-off enabled, if power to the computer is interrupted by a power outage or a disconnected
power cord, when power resumes, the computer returns to the power state it was in before power
was interrupted (on or off). The computer’s response can be set using the After Power Failure
feature in the BIOS Setup program’s Boot menu.
The location of the power connector Figure 10, page 56
The signal names of the power connector Table 33, page 58
The BIOS Setup program’s Boot menu Table 73, page 105
The ATX specification Section 1.3, page 16
1.12.2.2 Fan Connectors
The D850GB board has two fan connectors with thermal control signals (fan 1 at location J10A2
and fan 2 at location J7M2) that are used to switch the fans on and off or adjust the fan speed as
determined by the thermal sensors.
The ambient temperature of a D850GB-based system is thermally monitored by separate
temperature sensors that control voltage to the fan 1 and fan 2 connectors. If the fans attached to
these connectors provide a tachometer signal, the sensor reports the fan speed to the hardware
monitor component.
The temperature sensors that control the fans are initialized by the BIOS at power-up to turn on
only when the sensor reaches 36
cool down to 31
o
C (87.8 oF). This prevents the fans from turning off and on when the ambient air
around the sensor fluctuates around 35-36
slowly because the fan’s duty cycle starts at 70% and rises to 100% when the sensor reaches 46
(114.8
o
F).
o
C (96.8 oF). The fans switch off when their respective sensors
o
C. When the fans switch on, they may appear to rotate
o
C
All fans (fan 1, fan 2, fan 3, and fan 4) and the thermal control circuits are off during ACPI S3, S4,
and S5 states. Fan 3 and fan 4 (and the associated thermal control fan circuits) are enabled during
ACPI S0 and S1 states. Table 10 summarizes the functions of the four fan connectors.
Table 10. Fan Connector Descriptions
Connector Function
Chassis fan (fan 1) Provides +12 V DC for the syste m or chassis fan. A tachometer feedback
connection is also provided. A fan attached to this connector can be monitored
and controlled by the enhanced thermal monitor and fan control device.
RIMM fan (fan 2) Provides +12 V DC for the fan to cool the RIMM modules. A tachometer feedback
connection is also provided. A fan attached to this connector can be monitored
and controlled by the enhanced thermal monitor and fan control device.
Processor fan (fan 3) Provides +12 V DC for the processor fan or active fan heatsink. This fan is on in
the S0 or S1 state and is off only when the system is off or in the S3 or S5 state.
There are no user controls, however, this fan connector is wired to the fan
tachometer input of the SMSC LPC47M102 I/O controller.
Processor voltage
regulator fan (fan 4)
Provides +12 V DC for the fan to cool the processor voltage regulator area. This
fan is on in the S0 or S1 state and is off only when the system is off or in the S3 or
S5 state. There are no user controls.
38
Product Description
For information about Refer to
The location of the fan connectors Figure 10, page 56
The signal names of the fan connectors Section 2.8.2.2, page 54
1.12.2.3 Wake on LAN Technology
CAUTION
For Wake on LAN technology, the 5-V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing Wake on LAN technology can damage the power supply. Refer to Section 2.11.3 on
page 73 for additional information.
Wake on LAN technology enables remote wakeup of the computer through a network. The LAN
subsystem PCI bus network adapter monitors network traffic at the Media Independent Interface.
†
Upon detecting a Magic Packet
the computer. Depending on the LAN implementation, the D850GB board supports Wake on LAN
technology in the following ways:
• With APM, through the Wake on LAN technology connector
• With ACPI,
through the PCI bus PME# signal for PCI 2.2 compliant LAN designs
through the onboard LAN subsystem
through a CNR-based LAN subsystem
frame, the LAN subsystem asserts a wakeup signal that powers up
The Wake on LAN technology connector can be used with PCI bus network interface cards that
have a remote wake up connector, as shown in Figure 6. Network interface cards that are PCI 2.2
compliant assert the wakeup signal through the PCI bus signal PME# (pin A19 on the PCI bus
connectors).
Network
Interface
Card
Figure 6. Using the Wake on LAN Technology Connector
For information about Refer to
The location of the Wake on LAN technology connector Figure 10, page 56
The signal names of the Wake on LAN technology connector Table 36, page 58
For Instantly Available technology, the 5-V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing Instantly Available technology can damage the power supply. Refer to
Section 2.11.3 on page 73 for additional information.
Instantly Available technology enables the D850GB board to enter the ACPI S3 (Suspend-toRAM) sleep-state. While in the S3 sleep-state, the computer will appear to be off (the power
supply is off, and the front panel LED is amber if dual-color, or off if single-color.) When
signaled by a wake-up device or event, the system quickly returns to its last known wake state.
Table 9 on page 36 lists the devices and events that can wake the computer from the S3 state.
The D850GB board supports the PCI Bus Power Management Interface Specification. For
information on the versions of this specification, see Section 1.3. Add-in boards that also support
this specification can participate in power management and can be used to wake the computer.
The use of Instantly Available technology requires operating system support and PCI 2.2
compliant add-in cards and drivers.
The standby power indicator LED shows that power is still present at the RIMM, PCI bus, AGP,
and CNR connectors, even when the computer appears to be off. Figure 7 shows the location of
the standby power indicator LED.
CR6F1
OM10442
Figure 7. Location of the Standby Power Indicator LED
40
1.12.2.5 Resume on Ring
The operation of Resume on Ring can be summarized as follows:
• Resumes operation from either the APM sleep mode or the ACPI S1 or S3 states
• Requires only one call to access the computer
• Detects incoming call similarly for external and internal modems
• Requires modem interrupt be unmasked for correct operation
1.12.2.6 Wake from USB
USB bus activity wakes the computer from an ACPI S1 or S3 state.
NOTE
✏
Wake from USB requires the use of a USB peripheral that supports Wake from USB.
1.12.2.7 Wake from PS/2 Keyboard
PS/2 keyboard activity wakes the computer from an ACPI S1 or S3 state.
Product Description
1.12.2.8 PME# Wakeup Support
When the PME# signal on the PCI bus is asserted, the computer wakes from an ACPI S1, S3, S4,
or S5 state (with BIOS support).
1.12.2.9 Wake on LAN (Legacy)
This provision allows legacy internal LAN cards that require separate internal board connection to
support Wake on LAN technology. (More recent PCI LAN cards use the PME# signal available at
the PCI connector for this purpose.)
When a Wake on LAN technology supporting LAN card is connected to the Wake on LAN
connector, LAN activity wakes the computer from the APM sleep mode, or the ACPI S1, S3, S4,
or S5 states.
Sections 2.2 - 2.6 contain several standalone tables. Table 11 describes the system memory map,
Table 12 shows the I/O map, Table 13 lists the DMA channels, Table 14 defines the PCI
configuration space map, and Table 15 describes the interrupts. The remaining sections in this
chapter are introduced by text found with their respective section headings.
2.2 Memory Map
Table 11. System Memory Map
Address Range (decimal) Address Range (hex) Size Description
1024 K - 2097152 K 100000 - 7FFFFFFF 2047 MB Extended memory
960 K - 1024 K F0000 - FFFFF 64 KB Runtime BIOS
896 K - 960 K E0000 - EFFFF 64 KB Reserved
800 K - 896 K C8000 - DFFFF 96 KB Available high DOS memory (open
to the PCI bus)
640 K - 800 K A0000 - C7FFF 160 KB Video memory and BIOS
639 K - 640 K 9FC00 - 9FFFF 1 KB Extended BIOS data (movable by
memory manager software)
512 K - 639 K 80000 - 9FBFF 127 KB Extended conventional memory
0 K - 512 K 00000 - 7FFFF 512 KB Conventional memory
0 8 or 16 bits Audio
1 8 or 16 bits Audio / parallel port
2 8 or 16 bits Diskette drive
3 8 or 16-bits Parallel port (for ECP or EPP) / audio
4 8 or 16 bits DMA controller
5 16 bits Open
6 16 bits Open
7 16 bits Open
2.5 PCI Configuration Space Map
Table 14. PCI Configuration Space Map
Bus
Number (hex)
00 00 00 Memory controller of Intel 82850 component
00 01 00 PCI to AGP bridge
00 1E 00 Hub link to PCI bridge
00 1F 00 Intel 82801BA ICH2 PCI to LPC bridge
00 1F 01 IDE controller
00 1F 02 USB
00 1F 03 SMBus controller
00 1F 04 USB
00 1F 05 AC ’97 audio controller (optional)
00 1F 06 AC ’97 modem controller (optional)
01 00 00 Add-in AGP adapter card
02 08 00 LAN controller (optional)
02 09 00 PCI bus connector 1 (J4E1)
02 0A 00 PCI bus connector 2 (J4D1)
02 0B 00 PCI bus connector 3 (J4C1)
02 0C 00 PCI bus connector 4 (J4B1)
02 0D 00 PCI bus connector 5 (J4A1)
Device
Number (hex)
Function
Number (hex) Description
46
2.6 Interrupts
Table 15. Interrupts
IRQ System Resource
NMI I/O channel check
0 Reserved, interval timer
1 Reserved, keyboard buffer full
2 Reserved, cascade interrupt from slave PIC
3 COM2
4 COM1
5 LPT2 (Plug and Play option) / Audio / User available
6 Diskette drive
7 LPT1
8 Real-time clock
9 Reserved for ICH2 system management bus
10 User available
11 User available
12 Onboard mouse port (if present, else user available)
13 Reserved, math coprocessor
14 Primary IDE (if present, else user available)
15 Secondary IDE (if present, else user available)
Note: Default, but can be changed to another IRQ.
(Note)
(Note)
(Note)
Technical Reference
2.7 PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between the
PCI bus connectors and onboard PCI devices. The PCI specification specifies how interrupts can
be shared between devices attached to the PCI bus. In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices. In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt
with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
• INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
The ICH2 has eight programmable interrupt request (PIRQ) input signals. All PCI interrupt
sources either onboard or from a PCI add-in card connect to one of these PIRQ signals. Some PCI
interrupt sources are electrically tied together on the D850GB board and therefore share the same
interrupt. Table 16 shows an example of how the PIRQ signals are routed on the D850GB board.
For example, using Table 16 as a reference, assume an add-in card using INTA is plugged into PCI
bus connector 4. In PCI bus connector 4, INTA is connected to PIRQB, which is already
connected to the SMBus. The add-in card in PCI bus connector 4 now shares interrupts with these
onboard interrupt sources.
Table 16. PCI Interrupt Routing Map
PCI Interrupt Source
AGP connector INTB INTA to PIRQA
ICH2 USB controller INTD to PIRQD
SMBus controller INTB
ICH2 USB controller INTC to PIRQC
ICH2 Audio / Modem INTB
ICH2 LAN INTA to PIRQE
PCI Bus Connector 1 (J4E1) INTA INTB INTC INTD
PCI Bus Connector 2 (J4D1) INTD INTA INTB INTC
PCI Bus Connector 3 (J4C1) INTC INTD INTA INTB
PCI Bus Connector 4 (J4B1) INTB INTC INTD INTA
PCI Bus Connector 5 (J4A1) INTA INTB INTC INTD
PIRQF PIRQG PIRQH PIRQB Other
ICH2 PIRQ Signal Name
NOTE
✏
The ICH2 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11,
12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ
lines to be connected to the same IRQ signal.
48
Technical Reference
2.8 Connectors
CAUTION
Only the back panel connectors of the D850GB board have overcurrent protection. The D850GB
board’s internal connectors are not overcurrent protected and should connect only to devices
inside the computer’s chassis, such as fans and internal peripherals. Do not use these connectors
to power devices external to the computer’s chassis. A fault in the load presented by the external
devices could cause damage to the computer, the interconnecting cable, and the external devices
themselves.
This section describes the board’s connectors. The connectors can be divided into the following
groups:
• Back panel I/O connectors (see page 50)
PS/2 keyboard and mouse
USB (two)
Parallel port
Serial port
LAN
Audio (Line out, Line in, and Mic in)
• Internal I/O connectors (see page 53)
Audio (ATAPI CD-ROM, legacy-style CD-ROM, and auxiliary line input)
Fans (four)
Power (three)
Wake on LAN technology
Wake on Ring
Add-in boards (one CNR connector, one AGP connector, and five PCI bus connectors)
IDE (two)
Diskette drive
SCSI LED
• External I/O connectors (see page 65)
Front panel USB
Front panel (power/sleep/message-waiting LED, power switch, hard drive activity LED,
reset switch, infrared port, and auxiliary front panel power LED)
Figure 8 shows the location of the back panel connectors. The back panel connectors are colorcoded in compliance with PC 99 recommendations. The figure legend below lists the colors used.
A
C
E
H
I
J
B
D
Item Description Color For more information see:
A PS/2 mouse port Green Table 17
B PS/2 keyboard port Purple Table 17
C USB port 0 Black Table 18
D USB port 1 Black Table 18
E Parallel port Burgundy Table 19
F Serial port Teal Table 20
G LAN (optional) Black Table 21
H Audio line in (optional) Light blue Table 22
I Audio line out (optional) Lime green Table 23
J Mic in (optional) Pink Table 24
F
G
OM10443
Figure 8. Back Panel Connectors
NOTE
✏
The back panel audio line out connector is designed to power headphones or amplified speakers
only. Poor audio quality occurs if passive (non-amplified) speakers are connected to this output.
50
Table 17. PS/2 Mouse/Keyboard Connector
Pin Signal Name
1 Data
2 Not connected
3 Ground
4 +5 V
5 Clock
6 Not connected
Table 18. USB Connectors
Pin Signal Name
1 +5 V
2 USBP0# [USBP1#]
3 USBP0 [USBP1]
4 Ground
Signal names in brackets ([ ]) are for USB port 1.
Technical Reference
Table 19. Parallel Port Connector
Pin Standard Signal Name ECP Signal Name EPP Signal Name
Tip Audio left in
Ring Audio right in
Sleeve Ground
Table 23. Audio Line Out Connector (optional)
Pin Signal Name
Tip Audio left out
Ring Audio right out
Sleeve Ground
Table 24. Mic In Connector (optional)
Pin Signal Name
Tip Mono in
Ring Mic bias voltage
Sleeve Ground
52
2.8.2 Internal I/O Connectors
The internal I/O connectors are divided into the following functional groups:
• Audio (see page 54)
Auxiliary line in (optional)
ATAPI CD-ROM (optional)
Legacy style (2-mm) CD-ROM (optional)
PC/PCI
• Power and hardware control (see page 56)
Fans (four)
ATX12V
Main power
Auxiliary power
Wake on LAN technology
Wake on ring connector
• Add-in boards and peripheral interfaces (see page 59)
CNR (communication and networking riser)
PCI bus (five)
AGP
IDE (two)
SCSI LED
Diskette drive
Technical Reference
2.8.2.1 Expansion Slots
The board has the following expansion slots:
• One AGP connector or an optional AGP Pro50 connector at location J5E1 (ATX expansion
slot 6). The AGP connector is keyed for 1.5 V AGP cards only. Do not attempt to install a
legacy 3.3 V AGP card. The AGP connector is not mechanically compatible with legacy 3.3 V
AGP cards.
• Five PCI local bus slots (compliant with PCI rev 2.2 specification). The SMBus is routed to
PCI bus connector 2 only at location J4D1 (ATX expansion slot 4). PCI add-in cards with
SMBus support can access sensor data and other information residing on the desktop board.
• One CNR (optional), shared with PCI bus connector 5 at location J4A1 (ATX expansion
slot 1).
NOTE
✏
This document references back-panel slot numbering with respect to processor location on the
board. The AGP slot is not numbered. PCI slots are identified as PCI slot #x, starting with the
slot closest to the processor. The CNR slot shares PCI slot 5. The ATX/MicroATX specifications
identify expansion slot locations with respect to the far edge of a full-sized ATX chassis. The ATX
specification and the board’s silkscreen are opposite and could cause confusion. The ATX
numbering convention is made without respect to slot type (PCI vs. AGP), but refers to an actual
slot location on a chassis. Figure 11 on page 59 illustrates the board’s PCI slot numbering.
Figure 10 shows the location of the power and hardware control connectors.
A
21
4
3
1
1
B
1
1
1
1
1
F
20
10
EGHDCI
11
1
OM10445
Item Description Reference Designator For more information see:
A ATX12V power connector J3H1 Table 29
B Processor voltage regulator fan (Fan 4) J3M1 Table 30
C RIMM fan (Fan 2) J7M2 Table 31
D Processor fan (Fan 3) J6L1 Table 32
E Main power J10K1 Table 33
F Auxiliary power J9J1 Table 34
G Wake on Ring J8C1 Table 35
H Wake on LAN technology J7C1 Table 36
I Chassis fan (Fan 1) J10A2 Table 37
Figure 10. Power and Hardware Control Connectors
56
Technical Reference
For information about Refer to
The power connector Section 1.12.2.1, page 37
The functions of the fan connectors Section 1.12.2.2, page 38
Wake on LAN technology Section 1.12.2.3, page 39
CAUTION
Use only an ATX12V-compliant power suppIy with this board. ATX12V power supplies have two
additional power leads that provide required supplemental power for the Intel Pentium
processor and the Intel 850 chipset. Always connect both additional power supply leads of the
ATX12V power supply, otherwise the board and the processor could be damaged.
Do not use a standard ATX power supply. Doing so could damage the board and the processor.
Table 29. ATX12V Power Connector (J3H1)
Pin Signal Name Pin Signal Name
1 Ground 3 +12 V
2 Ground 4 +12 V
4
Table 30. Processor Voltage Regulator Fan Connector (J3M1)
1 +3.3 V 11 +3.3 V
2 +3.3 V 12 -12 V
3 Ground 13 Ground
4 +5 V 14 PS-ON# (power supply remote on/off)
5 Ground 15 Ground
6 +5 V 16 Ground
7 Ground 17 Ground
8 PWRGD (Power Good) 18 TP_PWRCONN_18
9 +5 V (Standby) 19 +5 V
10 +12 V 20 +5 V
Table 34. Auxiliary Power (J9J1)
Pin Signal Name
1 Ground
2 Ground
3 Ground
4 +3.3 V
5 +3.3 V
6 +5 V
Table 35. Wake on Ring Connector (J8C1)
Pin Signal Name
1 Ground
2 Ring Indicate
Table 36. Wake on LAN Technology Connector (J7C1)
Pin Signal Name
1 +5 VSB
2 Ground
3 WOL
Table 37. Chassis Fan Connector (J10A2)
Pin Signal Name
1 FAN_CNTRL
2 +12 V
3 Tachometer (FAN_1)
58
Technical Reference
2.8.2.4 Add-in Board and Peripheral Interface Connectors
Figure 11 shows the location of the add-in board connector and peripheral connectors. Note the
following considerations for the PCI bus connectors:
• All of the PCI bus connectors are bus master capable.
• PCI bus connector 2 has SMBus signals routed to it. This enables PCI bus add-in boards with
SMBus support to access sensor data on the board. The specific SMBus signals are as follows:
The SMBus clock line is connected to pin A40
The SMBus data line is connected to pin A41
CDEABFG
240
1
240
1
2
1
IJ
39
39
34
33
H
OM10446
Item Description Reference Designator For more information see:
A Communication and networking riser (CNR) J3A1 Table 38
B PCI bus connector 5 J4A1 Table 39
C PCI bus connector 4 J4B1 Table 39
D PCI bus connector 3 J4C1 Table 39
E PCI bus connector 2 J4D1 Table 39
F PCI bus connector 1 J4E1 Table 39
G AGP connector J5E1 Table 40
H Diskette drive J10G1 Table 42
I Primary IDE J9G2 Table 41
J Secondary IDE J9G1 Table 41
Figure 11. Add-in Board and Peripheral Interface Connectors
Table 39. PCI Bus Connectors (J4A1, J4B1, J4C1, J4D1, J4E1)
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 Ground (TRST#)* B1 -12 V A32 AD16 B32 AD17
A2 +12 V B2 Ground (TCK)* A33 +3.3 V B33 C/BE2#
A3 +5 V (TMS)* B3 Ground A34 FRAME# B34 Ground
A4 +5 V (TDI)* B4 Not connected (TDO)* A35 Ground B35 IRDY#
A5 +5 V B5 +5 V A36 TRDY# B36 +3.3 V
A6 INTA# B6 +5 V A37 Ground B37 DEVSEL#
A7 INTC# B7 INTB# A38 STOP# B38 Ground
A8 +5 V B8 INTD# A39 +3.3 V B39 LOCK#
A9 Reserved B9 Not connected
(PRSNT1#)*
A10 +5 V (I/O) B10 Reserved A41 Reserved *** B41 +3.3 V
A11 Reserved B11 Not connected
(PRSNT2#)*
A12 Ground B12 Ground A43 PAR B43 +3.3 V
A13 Ground B13 Ground A44 AD15 B44 C/BE1#
A14 +3.3 V aux B14 Reserved A45 +3.3 V B45 AD14
A15 RST# B15 Ground A46 AD13 B46 Ground
A16 +5 V (I/O) B16 CLK A47 AD11 B47 AD12
A17 GNT# B17 Ground A48 Ground B48 AD10
A18 Ground B18 REQ# A49 AD09 B49 Ground
A19 PME# B19 +5 V (I/O) A50 Key B50 Key
A20 AD30 B20 AD31 A51 Key B51 Key
A21 +3.3 V B21 AD29 A52 C/BE0# B52 AD08
A22 AD28 B22 Ground A53 +3.3 V B53 AD07
A23 AD26 B23 AD27 A54 AD06 B54 +3.3 V
A24 Ground B24 AD25 A55 AD04 B55 AD05
A25 AD24 B25 +3.3 V A56 Ground B56 AD03
A26 IDSEL B26 C/BE3# A57 AD02 B57 Ground
A27 +3.3 V B27 AD23 A58 AD00 B58 AD01
A28 AD22 B28 Ground A59 +5 V (I/O) B59 +5 V (I/O)
A29 AD20 B29 AD21 A60 REQ64C# B60 ACK64C#
A30 Ground B30 AD19 A61 +5 V B61 +5 V
A31 AD18 B31 +3.3 V A62 +5 V B62 +5 V
* These signals (in parentheses) are optional in the P CI specification and are not currently implemented.
** On PCI bus c onnector 2 (J4D1), this pin is connected to the SMBus c l ock line.
*** On PCI bus connector 2 (J4D1), this pin is connected to the SMBus dat a line.
The AGP connector is keyed for 1.5 V AGP cards only. Do not attempt to install a legacy 3.3 V
AGP card. The AGP connector is not mechanically compatible with legacy 3.3 V AGP cards.
62
Table 41. PCI IDE Connectors (J9G2, Primary and J9G1, Secondary)
Pin Signal Name Pin Signal Name
1 Reset IDE 2 Ground
3 Data 7 4 Data 8
5 Data 6 6 Data 9
7 Data 5 8 Data 10
9 Data 4 10 Data 11
11 Data 3 12 Data 12
13 Data 2 14 Data 13
15 Data 1 16 Data 14
17 Data 0 18 Data 15
19 Ground 20 Key
21 DDRQ0 [DDRQ1] 22 Ground
23 I/O Write# 24 Ground
25 I/O Read# 26 Ground
27 IOCHRDY 28 P_ALE (Cable Select pull-up)
29 DDACK0# [DDACK1#] 30 Ground
31 IRQ 14 [IRQ 15] 32 Reserved
33 DAG1 (Address 1) 34 GPIO_DMA66_Detect_Pri (GPIO_DMA66_Detect_Sec)
35 DAG0 (Address 0) 36 DAG2 (Address 2)
37 Chip Select 1P# [Chip Select 1S#] 38 Chip Select 3P# [Chip Select 3S#]
39 Activity# 40 Ground
Signal names in brackets ([ ]) are for the secondary IDE connector.
2.8.3.1 Auxiliary Front Panel Power/Sleep/Message Waiting LED Connector
This connector duplicates on pins 1 and 3, the signals on pins 2 and 4 of the front panel connector.
Table 45. Auxiliary Front Panel Power/Sleep/Message Waiting LED Connector (J8C3)
Pin Signal Name In/Out Description
1 HDR_BLNK_GRN Out Front panel green LED
2 Not connected
3 HDR_BLNK_YEL Out Front panel yellow LED
2.8.3.2 Front Panel Connector
This section describes the functions of the front panel connector. Table 46 lists the signal names
of the front panel connector.
Table 46. Front Panel Connector (J9D2)
Pin Signal In/Out Description Pin Signal In/Out Description
1 HD_PWR Out Hard disk LED pull-
up (330 Ω) to +5 V
3 HAD# Out Hard disk active LED 4 HDR_BLNK_
5 Ground Ground 6 FPBUT_IN In Power switch
7 FP_RESET# In Reset switch 8 Ground Ground
9 +5 V Out IR Power 10 N/C
11 Reserved In Reserved 12 Ground Ground
13 Ground Ground 14 (pin removed) Not connected
15 Reserved Out Reserved 16 +5 V Out Power
2 HDR_BLNK_
GRN
YEL
Out Front panel green
LED
Out Front panel yellow
LED
66
Technical Reference
2.8.3.2.1 Reset Switch Connector
Pins 5 and 7 can be connected to a momentary SPST type switch that is normally open. When the
switch is closed, the D850GB board resets and runs the POST.
2.8.3.2.2 Hard Drive Activity LED Connector
Pins 1 and 3 can be connected to an LED to provide a visual indicator that data is being read from
or written to a hard drive. For the LED to function properly, an IDE drive must be connected to
the onboard IDE interface. The LED will also show activity for devices connected to the SCSI
hard drive activity LED connector.
For information about Refer to
The SCSI hard drive activity LED connector Section 1.6.3.2, page 25
2.8.3.2.3 Power/Sleep/Message Waiting LED Connector
Pins 2 and 4 can be connected to a one- or two-colored LED. Table 47 shows the possible states
for a one-colored LED. Table 48 shows the possible states for a two-colored LED.
Table 47. States for a One Color Power LED
LED State Description
Off Power off/sleeping
Steady Green Running
Blinking Green Running/message waiting
Table 48. States for a Two Color Power LED
LED State Description
Off Power off
Steady Green Running
Blinking Green Running/message waiting
Steady Yellow Sleeping
Blinking Yellow Sleeping/message waiting
✏ NOTE
To use the message waiting function, ACPI must be enabled in the operating system and a
message-capturing application must be invoked.
2.8.3.2.4 Power Switch Connector
Pins 6 and 8 can be connected to a front panel momentary-contact power switch. The switch must
pull the SW_ON# pin to ground for at least 50 ms to signal the power supply to switch on or off.
(The time requirement is due to internal debounce circuitry on the D850GB board.) At least two
seconds must pass before the power supply will recognize another on/off signal.
Do not move any jumpers with the power on. Always turn off the power and unplug the power
cord from the computer before changing a jumper setting. Otherwise, the board could be
damaged.
The board has two jumper blocks. Figure 13 shows the location of the jumper blocks.
4
3
1
J8C2
Reference Designator Description
J8C2 BIOS configuration jumper block
J8D1 USB front panel / CNR jumper block
1
3
J8D1
6
OM10448
Figure 13. Location of the Jumper Blocks
68
Technical Reference
2.9.1 BIOS Setup Configuration Jumper Bl ock
This 3-pin jumper block determines the BIOS Setup program’s mode. Table 49 describes the
jumper settings for the three modes: normal, configure, and recovery. When the jumper is set to
configuration mode and the computer is powered-up, the BIOS compares the processor version and
the microcode version in the BIOS and reports if the two match.
The BIOS uses current configuration information and
passwords for booting.
After the POST runs, Setup runs automatically. The
maintenance menu is displayed.
The BIOS attempts to recover the BIOS configuration. A
recovery diskette is required.
For information about Refer to
How to access the BIOS Setup program Section 4.1, page 89
The maintenance menu of the BIOS Setup program Section 4.2, page 90
BIOS recovery Section 3.7, page 85
2.9.2 USB Port 2 Routing Jumper Block
This 6-pin jumper block routes the signals of USB port 2. Table 50 describes the jumper settings
for USB port 2. Figure 13 shows the location of the Front Panel USB connector.
Table 50. USB Port 2 Routing Jumper Settings (J8D1)
Jumper Setting Configuration
USB port 2 signals are routed to the Front Panel USB connector.
4
6
USB port 2 signals are routed to the CNR connector.
4
6
2-3 and 5-6
1-2 and 4-5
For information about Refer to
The location of the Front Panel USB connector Figure 12, page 65
The location of the CNR connector Figure 11, page 59
The D850GB board is designed to fit into an ATX-form-factor chassis. Figure 14 illustrates the
mechanical form factor for the D850GB board. Dimensions are given in inches [millimeters]. The
outer dimensions are 9.60 inches by 12.00 inches [243.84 millimeters by 304.80 millimeters].
Location of the I/O connectors and mounting holes are in compliance with the ATX specification
(see Section 1.3).
6.50[165.10]
6.10[154.94]
5.20[132.08]
0.00
2.850[72.39]
3.10[78.74]
0.65[16.51]
0.00
3.10
[78.74]
4.90
[124.46]
11.10[281.94]
Figure 14. D850GB Board Dimensions
NOTE
✏
There may be mechanical interference with installed RDRAM modules in some combinations of
ATX chassis and peripherals, such as CD-ROM drives.
11.35[288.29]
OM10449
70
Technical Reference
2.10.2 I/O Shield
The back panel I/O shield for the D850GB board must meet specific dimension and material
requirements. Systems based on this board need the back panel I/O shield to pass certification
testing. Figure 15 shows the critical dimensions of the chassis-dependent I/O shield. Dimensions
are given in inches to a tolerance of ±0.02 inches.
The figure also indicates the position of each cutout. Additional design considerations for I/O
shields relative to chassis requirements are described in the ATX specification. See Section 1.3 for
information about the ATX specification.
NOTE
✏
An I/O shield compliant with the ATX chassis specification 2.01 is available from Intel.
Table 51 lists voltage and current measurements for a computer that contains the D850GB board
and the following:
• 1.4 GHz Intel Pentium 4 processor with a 256 KB cache
• 128 MB RDRAM
• 3.5-inch diskette drive
• 6.4 GB IDE hard disk drive
• 40X IDE CD-ROM drive
This information is provided only as a guide for calculating approximate power usage with
additional resources added.
Values for the Windows 98 desktop mode are measured at 640 x 480 x 256 colors and 60 Hz
refresh rate. AC watts are measured with the computer is connected to a typical 250 W power
supply, at nominal input voltage and frequency, with a true RMS wattmeter at the line input.
✏ NOTE
Actual system power consumption depends upon system configuration. The power supply should
comply with the recommendations found in the ATX / ATX12V Power Supply Design Guide,
Version 1.1 (see Table 3 on page 16 for specification information).
Table 51. Power Usage
DC Current at:
Mode AC Power +3.3 V +5 V +12 V -12 V +5 VSB
Windows 98 APM full on 88.6 W 3.95 A 1.0 A 0.68 A -0.27 A 0.18 A
Windows 98 APM Suspend 54.3 W 3.96 A 0.99 A 0.30 A -0.24 A 0.14 A
Windows 98 ACPI S0 57.6 W 3.91 A 0.99 A 0.30 A -0.26 A 0.21 A
Windows 98 ACPI S1 54.1 W 3.88 A 0.89 A 0.31 A -0.27 A 0.21 A
Windows 98 ACPI S3 4.1 W 0.0 A 0.0 A 0.0 A 0.0 A 0.37 A
2.11.2 Add-in Board Considerations
The D850GB board is designed to provide 2 A (average) of +5 V current for each add-in board.
The total +5 V current draw for add-in boards in a fully-loaded D850GB board (all six expansion
slots filled) must not exceed 12 A.
72
Technical Reference
2.11.3 Standby Current Requirements
CAUTION
If the standby current necessary to support multiple wake events from the PCI and/or USB buses
exceeds power supply capacity, the D850GB board may lose register settings stored in memory,
etc. Calculate the standby current requirements using the steps described below.
Power supplies used with the D850GB board must be able to provide enough standby current to
support the Instantly Available (ACPI S3 sleep state) configuration as outlined in
Table 52 below.
Values are determined by specifications such as PCI 2.2. Actual measured values may vary.
To estimate the amount of standby current required for a particular system configuration, standby
current requirements of all installed components must be added to determine the total standby
current requirement. Refer to the descriptions in Table 52 and review the following steps.
1. Note the total D850GB board standby current requirement.
2. Add to that the total PS/2 port standby current requirement if a wake-enabled device is
connected.
3. Add, from the PCI 2.2 slots (wake enabled) row, the total number of wake-enabled devices
installed (PCI and AGP) and multiply by the standby current requirement.
4. Add, from the PCI 2.2 slots (nonwake enabled) row, the total number of wake-enabled devices
installed (PCI and AGP) and multiply by the standby current requirement.
5. Add all additional wake-enabled devices’ and nonwake-enabled devices’ standby current
requirements as applicable.
6. Add all the required current totals from steps 1 through 5 to determine the total estimated
standby current power supply requirement.
Table 52. Standby Current Requirements
Instantly Available Current
Support (Estimated for
Integrated Board Components)
Instantly Available Stand-by
Current Support
• Estimated for add-on
components
• Add to Instantly Available
total current requirement
(See instructions above)
Note: Dependent upon system configuration
Description
Total for D850GB board 300
PS/2 ports
PCI 2.2 slots (wake enabled) 375
PCI 2.2 slots (nonwake enabled) 20
WOL header 525
CNR (Note) 375
USB ports
PCI/AGP requirements are calculated by totaling the following:
• One wake-enabled device @ 375 mA, plus
• Five nonwake-enabled devices @ 20 mA each, plus
USB requirements are calculated as:
• One wake-enabled device @ 500 mA
• USB hub @ 100 mA
• Three USB nonwake-enabled devices connected @ 2.5 mA each
NOTE
✏
Both USB ports are capable of providing up to 500 mA during normal G0/S0 operation. Only one
USB port will support up to 500 mA of stand-by-current (wake-enabled device) during G1/S3
suspended operation. The other port may provide up to 7.5 mA (three nonwake-enabled devices.)
during G1/S3 suspended operation.
2.11.4 Fan Connector Current Capability
The D850GB board is designed to supply a maximum of 225 mA per fan connector.
2.11.5 Power Supply Considerations
CAUTION
The +5 V standby line for the power supply must be capable of providing adequate +5 V standby
current. Failure to do so can damage the power supply. The total amount of standby current
required depends on the wake devices supported and manufacturing options. Refer to
Section 2.11.3 on page 73 for additional information.
System integrators should refer to the power usage values listed in Table 51 when selecting a
power supply for use with the D850GB board.
Measurements account only for current sourced by the D850GB board while running in idle modes
of the started operating systems.
Additional power required will depend on configurations chosen by the integrator.
The power supply must comply with the following recommendations found in the indicated
sections of the ATX form factor specification.
• The potential relation between 3.3 VDC and +5 VDC power rails (Section 4.2)
• The current capability of the +5 VSB line (Section 4.2.1.2)
• All timing parameters (Section 4.2.1.3)
• All voltage tolerances (Section 4.2.2)
For information about Refer to
The ATX form factor specification Section 1.3, page 16
74
Technical Reference
2.12 Thermal Considerations
CAUTION
Ensure that the ambient temperature does not exceed the board’s maximum operating temperature
by more than 10
temperature and malfunction. For information about the maximum operating temperature, see the
environmental specifications in Section 2.14.
CAUTION
Ensure that proper airflow is maintained in the processor voltage regulator circuit. Failure to do
so may result in damage to the voltage regulator circuit. The processor voltage regulator area
(item A in Figure 16) can reach a temperature of up to 85
Figure 16 shows the locations of the localized high temperature zones.
o
C. Failure to do so could cause components to exceed their maximum case
o
C in an open chassis.
D
A Processor voltage regulator area
B Processor
C Intel 82850 MCH
D Intel 82801BA ICH2
Table 53 provides maximum case temperatures for D850GB board components that are sensitive
to thermal changes. Case temperatures could be affected by the operating temperature, current
load, or operating frequency. Maximum case temperatures are important when considering proper
airflow to cool the D850GB board.
Table 53. Thermal Considerations for Components
Component Maximum Case Temperature
Intel Pentium 4 processor For processor case temperature, see processor datasheets and
The mean time between failures (MTBF) prediction is calculated using component and
subassembly random failure rates. The calculation is based on the Bellcore Reliability Prediction
Procedure, TR-NWT-000332, Issue 4, September 1991. The MTBF prediction is used to estimate
repair rates and spare parts requirements.
The Mean Time Between Failures (MTBF) data is calculated from predicted data at 55 ºC.
D850GB board MTBF: 104769.75 hours
76
Technical Reference
2.14 Environmental
Table 54 lists the environmental specifications for the D850GB board.
The D850GB board uses an Intel/AMI BIOS, which is stored in flash memory and can be updated
using a disk-based program. In addition to the BIOS, the flash memory contains the BIOS Setup
program, POST, APM, the PCI auto-configuration utility, and Plug and Play support.
The D850GB board supports system BIOS shadowing, allowing the BIOS to execute from 64-bit
onboard write-protected system memory.
The BIOS displays a message during POST identifying the type of BIOS and a revision code. The
initial production BIOS is identified as GB85010A.86A.
For information about Refer to
The D850GB board’s compliance level with APM and Plug and Play Section 1.3, page 16
The SST 49LF004A Firmware Hub (FWH) includes a 4 Mbit (512 KB) symmetrical flash memory
device. Internally, the device is grouped into eight 64-KB blocks that are individually erasable,
lockable, and unlockable.
3.3 Resource Configuration
3.3.1 PCI Autoconfiguration
The BIOS can automatically configure PCI devices. PCI devices may be onboard or add-in cards.
Autoconfiguration lets a user insert or remove PCI cards without having to configure the system.
When a user turns on the system after adding a PCI card, the BIOS automatically configures
interrupts, the I/O space, and other system resources. Any interrupts set to Available in Setup are
considered to be available for use by the add-in card. Autoconfiguration information is stored in
ESCD format.
For information about the versions of PCI and Plug and Play supported by the BIOS, see
Section 1.3.
3.3.2 PCI IDE Support
If you select Auto in the BIOS Setup program, the BIOS automatically sets up the two
PCI IDE connectors with independent I/O channel support. The IDE interface supports hard drives
up to ATA-66/100 and recognizes any ATAPI compliant devices, including CD-ROM drives, tape
drives, and Ultra DMA drives (see Section 1.3 for the supported version of ATAPI). The BIOS
determines the capabilities of each drive and configures them to optimize capacity and
performance. To take advantage of the high capacities typically available today, hard drives are
automatically configured for Logical Block Addressing (LBA) and to PIO Mode 3 or 4, depending
on the capability of the drive. You can override the auto-configuration options by specifying
manual configuration in the BIOS Setup program.
To use ATA-66/100 features the following items are required:
• An ATA-66/100 peripheral device
• An ATA-66/100 compatible cable
• ATA-66/100 operating system device drivers
NOTE
✏
ATA-66/100 compatible cables are backward compatible with drives using slower IDE transfer
protocols. If an ATA-66/100 disk drive and a disk drive using any other IDE transfer protocol are
attached to the same cable, the maximum transfer rate between the drives is reduced to that of the
slowest device.
NOTE
✏
Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device. For
example, do not connect an ATA hard drive as a slave to an ATAPI CD-ROM drive.
82
Overview of BIOS Features
3.4 System Management BIOS (SMBIOS)
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing computers in
a managed network.
The main component of SMBIOS is the management information format (MIF) database, which
contains information about the computing system and its components. Using SMBIOS, a system
administrator can obtain the system types, capabilities, operational status, and installation dates for
system components. The MIF database defines the data and provides the method for accessing this
information. The BIOS enables applications such as third-party management software to use
SMBIOS. The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
†
Non-Plug and Play operating systems, such as Windows NT
obtaining the SMBIOS information. The BIOS supports an SMBIOS table interface for such
operating systems. Using this support, an SMBIOS service-level application running on a
non-Plug and Play operating system can obtain the SMBIOS information.
, require an additional interface for
For information about Refer to
The D850GB board’s compliance level with SMBIOS Section 1.3, page 16
3.5 Legacy USB Support
Legacy USB support enables USB devices such as keyboards, mice, and hubs to be used even
when the operating system’s USB drivers are not yet available. Legacy USB support is used to
access the BIOS Setup program, and to install an operating system that supports USB. By default,
Legacy USB support is set to Enabled.
Legacy USB support operates as follows:
1. When you apply power to the computer, legacy support is disabled.
2. POST begins.
3. Legacy USB support is enabled by the BIOS allowing you to use a USB keyboard to enter and
configure the BIOS Setup program and the maintenance menu.
4. POST completes.
5. The operating system loads. While the operating system is loading, USB keyboards and mice
are recognized and may be used to configure the operating system. (Keyboards and mice are
not recognized during this period if Legacy USB support was set to Disabled in the BIOS
Setup program.)
6. After the operating system loads the USB drivers, all legacy and non-legacy USB devices are
recognized by the operating system, and Legacy USB support from the BIOS is no longer
used.
To install an operating system that supports USB, verify that Legacy USB support in the BIOS
Setup program is set to Enabled and follow the operating system’s installation instructions.
Legacy USB support is for keyboards, mice, and hubs only. Other USB devices are not supported
in legacy mode.
3.6 BIOS Updates
The BIOS can be updated using either of the following utilities, which are available on the Intel
World Wide Web site:
®
• Intel
• Intel
Both utilities support the following BIOS maintenance functions:
• Verifying that the updated BIOS matches the target system to prevent accidentally installing
• Updating both the BIOS boot block and the main BIOS. This process is fault tolerant to
• Updating the BIOS boot block separately.
• Changing the language section of the BIOS.
• Updating replaceable BIOS modules, such as the video BIOS module.
• Inserting a custom splash screen.
Express BIOS Update utility, which enables automated updating while in the Windows
environment. Using this utility, the BIOS can be updated from a file on a hard disk, a 1.44 MB
diskette, or a CD-ROM, or from the file location on the Web.
®
Flash Memory Update Utility, which requires creation of a boot diskette and manual
rebooting of the system. Using this utility, the BIOS can be updated from a file on a 1.44 MB
diskette (from a legacy diskette drive or an LS-120 diskette drive) or a CD-ROM.
an incompatible BIOS.
prevent boot block corruption.
NOTE
✏
Review the instructions distributed with the upgrade utility before attempting a BIOS update.
For information about Refer to
The Intel World Wide Web site Section 1.2, page 16
3.6.1 Language Support
The BIOS Setup program and help messages are supported in five languages: US English,
German, Italian, French, and Spanish. The default language is US English, which is present unless
another language is selected in the BIOS Setup program.
84
Overview of BIOS Features
3.6.2 Custom Splash Screen
During POST, an Intel splash screen is displayed by default. This splash screen can be replaced
with a custom splash screen. A utility is available from Intel to assist with creating a custom
splash screen. The custom splash screen can be programmed into the flash memory using the
BIOS upgrade utility. Information about this capability is available on the Intel Support World
Wide Web site.
For information about Refer to
The Intel World Wide Web site Section 1.2, page 16
3.7 Recovering BIOS Data
Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage
occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from a
diskette using the BIOS recovery mode. When recovering the BIOS, be aware of the following:
• Because of the small amount of code available in the non-erasable boot block area, there is no
video support. You can only monitor this procedure by listening to the speaker or looking at
the diskette drive LED.
• The recovery process may take several minutes; larger BIOS flash memory devices require
more time.
• Two beeps and the end of activity in the diskette drive indicate successful BIOS recovery.
• A series of continuous beeps indicates a failed BIOS recovery.
To create a BIOS recovery diskette, a bootable diskette must be created and the BIOS update files
copied to it. BIOS upgrades and the Intel Flash Memory Update Utility are available from Intel
Customer Support through the Intel World Wide Web site.
NOTE
✏
Even if the computer is configured to boot from an LS-120 diskette (in the Setup program’s
Removable Devices submenu), the BIOS recovery diskette must be a standard 1.44 MB diskette not
a 120 MB diskette.
For information about Refer to
The BIOS recovery mode jumper settings Section 2.9.1, page 69
The Boot menu in the BIOS Setup program Section 4.7, page 105
Contacting Intel customer support Section 1.2, page 16
In the BIOS Setup program, the user can choose to boot from a diskette drive, hard drives,
CD-ROM, or the network. The default setting is for the diskette drive to be the first boot device,
the hard drive second, and the ATAPI CD-ROM third. The fourth device is disabled.
3.8.1 CD-ROM and Network Boot
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format
specification. Under the Boot menu in the BIOS Setup program, ATAPI CD-ROM is listed as a
boot device. Boot devices are defined in priority order. Accordingly, if there is not a bootable CD
in the CD-ROM drive, the system will attempt to boot from the next defined drive.
The network can be selected as a boot device. This selection allows booting from the onboard
LAN or a network add-in card with a remote boot ROM installed.
For information about Refer to
The El Torito specification Section 1.3, page 16
3.8.2 Booting Without Attached Devices
For use in embedded applications, the BIOS has been designed so that after passing the POST, the
operating system loader is invoked even if the following devices are not present:
• Video adapter
• Keyboard
• Mouse
3.9 Fast Booting Systems with Intel® Rapid BIOS Boot
Three factors affect system boot speed:
• Selecting and configuring peripherals properly
®
• Using an optimized BIOS, such as the Intel
• Selecting a compatible operating system
3.9.1 Peripheral Selecti on and Configuration
The following techniques help improve system boot speed:
• Choose a hard drive with parameters such as “power-up to data ready” less than eight seconds,
that minimize hard drive startup delays.
• Select a CD-ROM drive with a fast initialization rate. This rate can influence POST execution
time.
• Eliminate unnecessary add-in adapter features, such as logo displays, screen repaints, or mode
changes in POST. These features may add time to the boot process.
• Try different monitors. Some monitors initialize and communicate with the BIOS more
quickly, which enables the system to boot more quickly.
Rapid BIOS
86
Overview of BIOS Features
3.9.2 Intel Rapid BIOS Boot
Use of the following BIOS Setup program settings reduces the POST execution time.
In the Boot Menu:
• Set the hard disk drive as the first boot device. As a result, the POST does not first seek a
diskette drive, which saves about one second from the POST execution time.
• Disable Quiet Boot, which eliminates display of the logo splash screen. This could save
several seconds of painting complex graphic images and changing video modes.
• Enabled Intel Rapid BIOS Boot. This feature bypasses memory count and the search for a
diskette drive.
In the Peripheral Configuration submenu, disable the LAN device if it will not be used. This can
reduce up to four seconds of option ROM boot time.
NOTE
✏
It is possible to optimize the boot process to the point where the system boots so quickly that the
Intel logo screen (or a custom logo splash screen) will not be seen. Monitors and hard disk drives
with minimum initialization times can also contribute to a boot time that might be so fast that
necessary logo screens and POST messages cannot be seen.
This boot time may be so fast that some drives might be not be initialized at all. If this condition
should occur, it is possible to introduce a programmable delay ranging from 3 to 30 seconds
(using the Hard Disk Pre-Delay feature of the Advanced Menu in the IDE Configuration Submenu
of the BIOS Setup program).
For information about Refer to
IDE Configuration Submenu in the BIOS Setup program Section 4.4.3, page 97
3.9.3 Operating System
The Microsoft Windows Millennium Edition (Windows Me) operating system has built-in
capabilities for making PCs boot more quickly. To speed operating system availability at boot
time, limit the number of applications that load into the system tray or the task bar.
The BIOS includes security features that restrict access to the BIOS Setup program and who can
boot the computer. A supervisor password and a user password can be set for the BIOS Setup
program and for booting the computer, with the following restrictions:
• The supervisor password gives unrestricted access to view and change all the Setup options in
the BIOS Setup program. This is the supervisor mode.
• The user password gives restricted access to view and change Setup options in the BIOS Setup
program. This is the user mode.
• If only the supervisor password is set, pressing the <Enter> key at the password prompt of the
BIOS Setup program allows the user restricted access to Setup.
• If both the supervisor and user passwords are set, users can enter either the supervisor
password or the user password to access Setup. Users have access to Setup respective to
which password is entered.
• Setting the user password restricts who can boot the computer. The password prompt will be
displayed before the computer is booted. If only the supervisor password is set, the computer
boots without asking for a password. If both passwords are set, the user can enter either
password to boot the computer.
Table 57 shows the effects of setting the supervisor password and user password. This table is for
reference only and is not displayed on the screen.
Table 57. Supervisor and User Password Functions
Password Set
Neither Can change all
Supervisor
only
User only N/A Can change all
Supervisor
and user set
Note: If no password is set, any user c an change all Setup options.
Supervisor
Mode
options
Can change all
options
Can change all
options
(Note)
User Mode Setup Options
Can change all
options
Can change a
limited number
of options
options
Can change a
limited number
of options
(Note)
None None None
Supervisor Password Supervisor None
Enter Password
Clear User Password
Supervisor Password
Enter Password
Password to
Enter Setup
User User
Supervisor or
user
Password
During Boot
Supervisor or
user
For information about Refer to
Setting user and supervisor passwords Section 4.5, page 103
The BIOS Setup program can be used to view and change the BIOS settings for the computer. The
BIOS Setup program is accessed by pressing the <F2> key after the Power-On Self-Test (POST)
memory test begins and before the operating system boot begins. The menu bar is shown below.
Maintenance Main Advanced Security Power Boot Exit
Table 58 lists the BIOS Setup program menu features.
Table 58. BIOS Setup Program Menu Bar
Maintenance Main Advanced Security Power Boot Exit
Clears
passwords and
BIS credentials
and enables
extended
configuration
mode
Allocates
resources for
hardware
components
Configures
advanced
features
available
through the
chipset
Saves or
discards
changes to
Setup
program
options
NOTE
✏
In this chapter, all examples of the BIOS Setup program menu bar include the maintenance menu;
however, the maintenance menu is displayed only when the board is in configuration mode.
Section 2.9 on page 68 tells how to put the board in configuration mode.
Table 59 lists the function keys available for menu screens.
Table 59. BIOS Setup Program Function Keys
BIOS Setup Program Function Key Description
<←> or <→> Selects a different menu screen (Moves the cursor left or right)
<↑> or <↓> Selects an item (Moves the cursor up or down)
<Tab> Selects a field (Not implemented)
<Enter> Executes command or selects the submenu
<F9> Load the default configuration values for the current menu
<F10> Save the current values and exits the BIOS Setup program
<Esc> Exits the menu
4.2 Maintenance Menu
To access this menu, select Maintenance on the menu bar at the top of the screen.
Maintenance
Extended Configuration
The menu shown in Table 60 is for clearing Setup passwords and enabling extended configuration
mode. Setup only displays this menu in configuration mode. See Section 2.9 on page 68 for
configuration mode setting information.
Main Advanced Security Power Boot Exit
Table 60. Maintenance Menu
Feature Options Description
Clear All Passwords • Yes (default)
• No
Clear BIS Credentials • Yes (default)
• No
Extended
Configuration
Scan User Flash
Area
Fixed Disk Boot
Sector
CPU Information No options Displays CPU Information.
CPU Stepping
Signature
CPU Microcode
Update Revision
• Default (default)
• User-Defined
• Disabled
(default)
• Enabled
• Normal (default)
• Write Protect
No options Displays CPU’s Stepping Signature.
No options Displays CPU’s Microcode Update Revision.
Clears the user and supervisor passwords.
Clears the Wired for Management Boot Integrity Service (BIS)
credentials.
Invokes the Extended Configuration submenu.
Enables the BIOS to scan the flash memory for user binary
files that are executed at boot time.
Write Protect prevents write operations to the IDE boot sector.
Normal has no write protection and is used when formatting.
90
BIOS Setup Program
4.2.1 Extended Configuration Submenu
To access this submenu, select Maintenance on the menu bar, then Extended Configuration.
Maintenance
Extended Configuration
The submenu represented by Table 61 is for setting video memory cache mode. This submenu
becomes available when User Defined is selected under Extended Configuration.
User Defined allows setting memory control and video
(default)
• User Defined
• UC (default)
memory cache mode. If selected here, will also display in
the Advanced Menu as: “Extended Menu:
Selects Uncacheable Speculative Write-Combining
(USWC) video memory cache mode. Full 32 byte contents
of the Write Combining buffer are written to memory as
required. Cache lookups are not performed. Both the
video driver and the application must support Write
Combining.
Selects UnCacheable (UC) video memory cache mode.
This setting identifies the video memory range as
uncacheable by the processor. Memory writes are
performed in program order. Cache lookups are not
performed. Well suited for applications not supporting
Write Combining.
To access this menu, select Main on the menu bar at the top of the screen.
Maintenance
Main
Table 62 describes the Main menu. This menu reports processor and memory information and is
for configuring the system date and system time.
Table 62. Main Menu
Feature Options Description
BIOS Version No options Displays the version of the BIOS.
Processor Type No options Displays processor type.
Processor Speed No options Displays processor speed.
System Bus Speed No options Displays the system bus speed.
Cache RAM No options Displays the size of second-level cache and whether it is
Total Memory No options Displays the total amount of RAM.
RIMM 1
RIMM 2
RIMM 3
RIMM 4
Language • English (default)
Memory
Configuration
System Time Hour, minute, and
System Date Day of week
No options Displays the amount and type of RAM in the memory
• Deutsch
• Français
• Español
• Portugues
• Non-ECC
• ECC (default)
second
Month/day/year
Advanced Security Power Boot Exit
ECC-capable.
banks.
Selects the current default language used by the BIOS.
Allows the user to enable error reporting if the system and
all installed memory support ECC. If non-ECC memory is
installed, BIOS will detect and change the setting to
Non-ECC.
Specifies the current time.
Specifies the current date.
92
BIOS Setup Program
4.4 Advanced Menu
To access this menu, select Advanced on the menu bar at the top of the screen.
Maintenance Main
Advanced
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
Table 63 describes the Advanced Menu. This menu is used for setting advanced features that are
available through the chipset.
Table 63. Advanced Menu
Feature Options Description
Extended Configuration No options If
Boot Configuration Select to display
submenu
Peripheral Configuration Select to display
submenu
IDE Configuration Select to display
submenu
Diskette Configuration Select to display
submenu
Event Log Configuration Select to display
submenu
Video Configuration Select to display
submenu
Security Power Boot Exit
Used
is displayed,
Extended Configuration under the Maintenance Menu.
Configures Plug and Play and the Numlock key, and resets
configuration data. When selected, displays the Boot
Configuration submenu.
Configures peripheral ports and devices. When selected,
displays the Peripheral Configuration submenu.
Specifies type of connected IDE devices.
When selected, displays the Diskette Configuration
submenu.
Configures Event Logging. When selected, displays the
Event Log Configuration submenu.
Configures video features. When selected, displays the
Video Configuration submenu.
Base I/O address
(This feature is present
only when Parallel Port
is set to
Interrupt
(This feature is present
only when Parallel Port
is set to
DMA
(This feature is present
only when Parallel Port
Mode is set to
Audio Device • Disabled
LAN Device • Disabled
Modem Device • Disabled
Legacy USB Support • Disabled
Enabled
Enabled
ECP
)
)
)
• 378 (default)
• 278
• IRQ 5
• IRQ 7
(default)
• 1
• 3 (default)
• Enabled
(default)
• Enabled
(default)
• Enabled
(default)
• Enabled
(default)
Specifies the base I/O address for the parallel port.
Specifies the interrupt for the parallel port.
Specifies the DMA channel.
Enables or disables the onboard audio subsystem.
For boards with no onboard audio subsystem, this option
does not appear; however, this option does appear if a CNR
card with an audio subsystem is installed.
Enables or disables the onboard LAN device.
For boards with no onboard LAN audio subsystem, this option
will not appear; however, this option does appear if a CNR
card with a LAN subsystem is instal led.
Enables or disables a modem device on a CNR card.
This option appears only when a CNR card with a modem is
installed.
Enables or disables Legacy USB support.
96
4.4.3 IDE Configuration Submenu
To access this submenu, select Advanced on the menu bar, then IDE Configuration.
Maintenance Main
Advanced
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
The menu represented in Table 66 is used to configure IDE device options.
Table 66. IDE Configuration Submenu
Feature Options Description
IDE Controller • Disabled
• Primary
• Secondary
• Both (default)
Hard Disk Pre-Delay • Disabled (default)
• 3 Seconds
• 6 Seconds
• 9 Seconds
• 12 Seconds
• 15 Seconds
• 21 Seconds
• 30 Seconds
Primary IDE Master Select to display sub-
menu
Primary IDE Slave Select to display sub-
menu
Secondary IDE Master Select to display sub-
menu
Secondary IDE Slave Select to display sub-
menu
Security Power Boot Exit
Specifies the integrated IDE controller.
Primary
Secondary
Both
Specifies the hard disk drive pre-delay.
Reports type of connected IDE device. When selected,
displays the Primary IDE Master submenu.
Reports type of connected IDE device. When selected,
displays the Primary IDE Slave submenu.
Reports type of connected IDE device. When selected,
displays the Secondary IDE Master submenu.
Reports type of connected IDE device. When selected,
displays the Secondary IDE Slave submenu.
4.4.3.1 Primary/Secondary IDE Master/Slave Submenus
To access these submenus, select Advanced on the menu bar, then IDE Configuration and then the
master or slave to be configured.
Maintenance Main
Advanced
Boot Configuration
Peripheral Configuration
IDE Configuration
Primary IDE Master
Primary IDE Slave
Secondary IDE Master
Secondary IDE Slave
Diskette Configuration
Event Log Configuration
Video Configuration
There are four IDE submenus: primary master, primary slave, secondary master, and secondary
slave. Table 67 shows the format of the IDE submenus. For brevity, only one example is shown.
Security Power Boot Exit
Table 67. Primary/Secondary IDE Master/Slave Submenus
Feature Options Description
Drive Installed No options Displays the type of drive installed.
Type • None
• User
• Auto (default)
• CD-ROM
• ATAPI Removable
• Other ATAPI
• IDE Removable
Maximum Capacity No options Displays the capacity of the drive.
LBA Mode Control • Disabled
• Enabled (default)
Multi-Sector Transfers • Disabled (default)
• 2 Sectors
• 4 Sectors
• 8 Sectors
• 16 Sectors
Specifies the IDE configuration mode for IDE devices.
User
allows capabilities to be changed.
Auto
fills-in capabilities from ATA/ATAPI device.
Enables or disables LBA mode control.
Specifies number of sectors per block for transfers from
the hard disk drive to memory.
Check the hard disk drive’s specifications for optimum
setting.
continued
98
BIOS Setup Program
Table 67. Primary/Secondary IDE Master/Slave Submenus (continued)
Feature Options Description
PIO Mode • Auto (default)
• 0
• 1
• 2
• 3
• 4
Ultra DMA • Disabled (default)
• Mode 0
• Mode 1
• Mode 2
• Mode 3
• Mode 4
Cable Detected No options Displays the type of cable connected to the IDE
Specifies the PIO mode.
Specifies the Ultra DMA mode for the drive.
interface: 40-conductor or 80-conductor (for ATA-100
peripherals).