The Intel® Desktop Board D815BN may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized
errata are documented in the Intel Desktop Board D815BN Specification Update.
Revision History
RevisionRevision HistoryDate
-001First release of the Intel® Desktop Board D815BN Technical Product
Specification
This product specification applies to only standard D815BN boards with BIOS identifier
BN81510A.86A.
Changes to this specification will be published in the Intel Desktop Board D815BN Specification
Update before being incorporated into a revision of this document.
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Copies of documents whic h have an ordering number and are referenc ed in this docum ent, or other Intel lit erature, may be
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†
Copyright 2000 Intel Corporation. All rights reserved.
®
Desktop Board D815BN may cont ain design defects or errors known as errata whic h may cause t he product to
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Third party brands and names are the property of their respective owners.
September 2000
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
®
power and environmental requirements, and the BIOS for the Intel
describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the D815BN board and its
components to the vendors, system integrators, and other engineers and technicians who need this
level of information. It is specifically not intended for general audiences.
What This Document Contains
ChapterDescription
1A description of the hardware used on the D815BN board
2A map of board resources
3The features supported by the BIOS Setup program
4The contents of the BIOS Setup program’s menus and submenus
5A description of the BIOS error messages, beep codes, power-on self-test (POST)
codes, and diagnostic LEDs
Desktop Board D815BN. It
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
#Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX)When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the D815BN board, and X is the instance of the particular part at
that general location. For example, J6A3 is a connector, located at 6A. It is the first
connector in the 6A area.
GBGigabyte (1,073,741,824 bytes)
KBKilobyte (1024 bytes)
KbitKilobit (1024 bits)
kbits/sec1000 bits per second
MBMegabyte (1,048,576 bytes)
MB/secMegabytes per second
MbitMegabit (1,048,576 bits)
Mbit/secMegabits per second
xxhAn address or data value ending with a lowercase h indicates a hexadecimal value.
x.x VVolts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
PC SDRAM DIMM Serial
Presence Detect (SPD)
Specification
System Management
BIOS Reference
Specification
Universal Host Controller
Interface Design Guide
Universal Serial Bus
Specification
Wired for Management
Baseline
Version, Revision Date
and Ownership
Version 2.1,
September 1999,
Intel Corporation (with
contributions from SystemSoft
Corporation).
Revision 1.0,
February 1998,
Intel Corporation.
Revision 1.7,
November 1999,
Intel Corporation.
Revision 1.2B,
November 1999
Intel Corporation.
Version 2.3.1,
March 16, 1999
American Megatrends Inc.,
Award Software International Inc.,
Compaq Computer Corporation,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
and SystemSoft Corporation.
Version 1.1,
March 1996,
Intel Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation, Microsoft
Corporation, and NEC.
Version 2.0,
December 18, 1998,
Intel Corporation.
The D815BN board supports processors that have a 19.4 A maximum current draw with a 1.65 to
2.0 V core voltage. Using a processor not in compliance with the above guidelines can damage
the processor, the D815BN board, and the power supply. See the processor’s data sheet for
voltage and current usage requirements.
The D815BN board supports a single Pentium III or Celeron processor. The system bus speed is
automatically selected. The D815BN board supports the processors listed in Table 4.
Table 4.Supported Processors
TypeDesignationSystem Bus FrequencyL2 Cache Size
an FC-PGA package
Celeron processor in an
FC-PGA package
Celeron processor in a
PPGA package
533EB, 600EB, 667, 733,
800B, 866, 933, and 1.0
500E, 550E, 600E, 650, 700,
750, 800, and 850
533A, 566, 600, 633, 667, and
700
500 and 53366 MHz128 KB
133 MHz256 KBPentium III processor in
100 MHz256 KB
66 MHz128 KB
All supported onboard memory can be cached, up to the cachability limit of the processor. See the
The D815BN board has three DIMM sockets and supports the following memory features:
• 3.3 V (only) 168-pin SDRAM DIMMs with gold-plated contacts
• Unbuffered single- or double-sided DIMMs
• Maximum system memory: 512 MB; minimum system memory: 32 MB
• 133 MHz SDRAM or 100 MHz SDRAM
• Serial Presence Detect (SPD) and non-SPD memory
• Non-ECC and ECC DIMMs (ECC DIMMs will operate in non-ECC mode only.)
• Suspend to RAM
Table 5 lists the supported DIMM configurations. In the second column of Table 5:
• “DS” refers to double-sided memory modules (containing two rows of SDRAM)
• “SS” refers to single-sided memory modules (containing one row of SDRAM)
When installing memory, note the following:
• Non-SPD DIMMs will always revert to a 100 MHz SDRAM bus with 3-3-3 timing.
• Mixing non-SPD DIMMs with SPD DIMMs will always revert to a 100 MHz SDRAM bus
with 3-3-3 timing.
• The BIOS will not initialize installed memory above 512 MB. At boot, the BIOS displays a
message indicating that any installed memory above 512 MB has not been initialized.
• Mixed memory speed configurations (133 and 100 MHz) will default to 100 MHz.
• 133 MHz SDRAM operation requires a 133 MHz system bus frequency processor.
• The board should be populated with no more than four rows of 133 MHz SDRAM (two
double-sided or one double-sided plus two single-sided DIMMs).
• 100 MHz SDRAM may be populated with six rows of SDRAM (three double-sided DIMMs).
✏ NOTE
If more than four rows of 133 MHz SDRAM are populated, the BIOS will initialize installed
memory up to 512 MB at 100 MHz.
20
Product Description
Table 5.Supported Memory Configurations
DIMM
Capacity
Number of
Sides
SDRAM
Density
32 MBDS16 Mbit2 M X 82 M X 816
32 MBSS64 Mbit4 M X 16Empty4
48 MBDS64/16 Mbit4 M X 162 M X 812
64 MBDS64 Mbit4 M X 164 M X 168
64 MBSS64 Mbit8 M X 8Empty8
64 MBSS128 Mbit8 M X 16Empty4
96 MBDS64 Mbit8 M X 84 M x 1612
96 MBDS128/64 Mbit8 M X 164 M x 168
128 MBDS64 Mbit8 M X 88 M X 816
128 MBDS128 Mbit8 M X 168 M X 168
128 MBSS128 Mbit16 M X 8Empty8
128 MBSS256 Mbit16 M X 16Empty4
192 MBDS128 Mbit16 M X 88 M x 1612
192 MBDS128/64 Mbit16 M X 88 M x 816
256 MBDS128 Mbit16 M X 816 M X 816
256 MBDS256 Mbit16 M X 1616 M X 168
256 MBSS256 Mbit32 M X 8Empty8
512 MBDS256 Mbit32 M X 832 M X 816
Notes:
1If the number of SDRAM devices is great er t han nine, the DIMM will be double sided.
2Front side population/back si de popul ation indicated for SDRAM dens i t y and SDRAM organization.
SDRAM Organization
Front-sideBack-side
Number of
SDRAM Devices
(Note 1)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Note 1)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
CAUTION
To be fully compliant with all applicable Intel® SDRAM memory specifications, the motherboard
should be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. If
your memory modules do not support SPD, you will see a notification to this effect on the screen at
power up. The BIOS will attempt to configure the memory controller for normal operation.
However, DIMMs may not function under the determined frequency.
For information aboutRefer toThe PC Serial Presence Detect SpecificationSection 1.3, page 16
The Intel 815 chipset consists of the following devices:
• 82815 Graphics and Memory Controller Hub (GMCH) with Accelerated Hub Architecture
(AHA) bus
• 82801AA I/O Controller Hub (ICH) with AHA bus
• 82802AB Firmware Hub (FWH)
The GMCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
Accelerated Hub Architecture interface. The ICH is a centralized controller for the board’s I/O
paths. The FWH provides the nonvolatile storage of the BIOS as well as hardware-dependent
security features. The chipset provides the interfaces shown in Figure 3.
ATA-33/66
SystemBus
SDRAMBus
USB
815Chipset
82815
Graphics and
Memory Controller
Hub (GMCH)
Digitalvideo
output
Interface
AHA
Bus
AGP
82801AA
I/O Controller Hub
(ICH)
82802AB
Firmware Hub
(FWH)
LPCBus
ACLinkPCIBusSMBus
OM10733
Figure 3. Intel 815 Chipset Block Diagram
For information aboutRefer toThe Intel 815 chipsethttp://developer.intel.comThe resources used by the chipsetChapter 2The chipset’s compliance with AC ’97, ACPI, and APMSection 1.3, page 16
22
Product Description
1.6.1 Intel® 82815 Graphics and Memory Controller Hub (GMCH)
The GMCH provides the following:
• An integrated synchronous DRAM memory controller with autodetection of SDRAM
• An interface for a single AGP device or a Graphics Performance Accelerator (GPA) card
• An interface for a digital video output (DVO) connector for a flat panel digital CRT or
TV out
• Support for ACPI Rev 1.0 and APM Rev 1.2 compliant power management
1.6.2 Intel® 82801AA I/O Controller Hub (ICH)
The ICH provides the following:
• 33 MHz PCI bus interface with support for three PCI Local Bus Specification
Rev. 2.2-compliant slots
• Support for up to four PCI master devices
• One Advanced Graphics Port
• Low Pin Count (LPC) interface that supports an LPC-compatible I/O controller
• Support for two master/DMA devices
• Integrated IDE controller that supports Ultra DMA (33 MB/sec) and ATA-66 mode
(66 MB/sec)
• Universal Serial Bus interface with one USB controller providing two ports in a UHCI
implementation
• Power management logic for ACPI Rev 1.0b compliance
• System Management Bus (SMBus clock and data lines also routed to PCI bus connector 2)
• Real-Time Clock with 256-byte battery-backed CMOS RAM
• AC’97 digital link for Audio and telephony codecs, including:
AC’97 2.1 compliance
Logic for PCM in, PCM out, mic input, modem in, and modem out
Separate PCI functions for audio and modem
1.6.2.1 IDE Interfaces
The ICH’s IDE controller has two independent bus-mastering IDE interfaces that can be
independently enabled. The IDE interfaces support the following modes:
• Programmed I/O (PIO): CPU controls data transfer.
• 8237-style DMA: DMA offloads the CPU, supporting transfer rates of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• Ultra ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer
rates of up to 66 MB/sec. ATA-66 protocol is similar to ATA-33 and is device driver
compatible. ATA-66 uses faster timings and requires a specialized cable to reduce reflections,
noise, and inductive coupling.
The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using
the transfer modes listed in Table 64 on page 101.
The BIOS supports logical block addressing (LBA) and extended cylinder head sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The D815BN board supports laser servo (LS-120) diskette technology through its IDE interfaces.
The LS-120 drive can be configured as a boot device by setting the BIOS Setup program’s Boot
menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information aboutRefer to
The location of the IDE connectorsFigure 8, page 60
The signal names of the IDE connectorsTable 39, page 64
BIOS Setup program’s Boot menuTable 70, page 108
1.6.2.2 USB
The D815BN board has four USB ports. The ICH includes a USB controller and the LPC47M142
features a USB hub and drives three USB ports. One USB peripheral can be connected to each
port. For more than four USB devices, an external hub can be connected to any of the ports. Two
of the USB ports are implemented with stacked back panel connectors; the other two are accessible
via the front panel USB connector at location J8B1. The D815BN board fully supports UHCI and
uses UHCI-compatible software drivers.
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information aboutRefer to
The location of the USB connectors on the back panelFigure 6, page 52
The signal names of the back panel USB connectorsTable 20, page 53
The location of the front panel USB connectorFigure 9, page 65
The signal names of the front panel USB connectorTable 41, page 66
The USB specification and UHCISection 1.3, page 16
1.6.2.3 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock provides a time-of-day clock and a multicentury calendar with alarm features.
The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are
reserved for BIOS use.
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
24
Product Description
✏ NOTES
If the battery and AC power fail, the last saved defaults, custom or standard, will be loaded into
CMOS RAM at power-on.
The recommended method of accessing the date in systems with D815BN boards is indirectly from
the Real-Time Clock (RTC) via the BIOS. The BIOS on D815BN boards contains a century
checking and maintenance feature. This feature checks the two least significant digits of the year
stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less than 80 (i.e.,
1980 is the first year supported by the PC), updates the century byte to 20. This feature enables
operating systems and applications using the BIOS date/time services to reliably manipulate the
year as a four-digit value.
For information aboutRefer to
Proper date access in systems with D815BN boardsSection 1.2, page 16
1.6.3 Intel® 82802AB 4 Mbit Firmware Hub (FWH)
The FWH provides the following:
• System BIOS
• System security and manageability logic that enables protection for storing and updating of
platform information
1.7 I/O Controller
The SMSC LPC47M142 I/O controller provides the following features:
• Low pin count (LPC) interface
• 3.3 V operation
• One serial port
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
• One USB hub supporting three USB ports
• Serial IRQ interface compatible with serialized IRQ support for PCI systems
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.2 MB, 1.44 MB, or 2.88 MB diskette drive
• Intelligent power management, including a programmable wake up event interface
• PCI power management support
• Fan control:
Two fan tachometer inputs
Two fan control outputs
The BIOS Setup program provides configuration options for the I/O controller.
The D815BN board has one serial port, which is located on the back panel. The serial port’s
NS16C550-compatible UART supports data transfers at speeds up to 115.2 kbits/sec with BIOS
support. The serial port can be assigned as COM1 (3F8h), COM2 (2F8h), COM3 (3E8h), or
COM4 (2E8h).
For information aboutRefer to
The location of the serial port connectorFigure 6, page 52
The signal names of the serial port connectorTable 23, page 54
1.7.2 Parallel Port
The connector for the multimode bidirectional parallel port is a 25-pin D-sub connector located on
the back panel. In the BIOS Setup program, the parallel port can be configured for the following:
†
• Output only (PC AT
• Bi-directional (PS/2 compatible)
• EPP
• ECP
-compatible mode)
For information aboutRefer to
The location of the parallel port connectorFigure 6, page 52
The signal names of the parallel port connectorTable 22, page 54
1.7.3 Diskette Drive Controller
The I/O controller supports one diskette drive that is compatible with the 82077 diskette drive
controller and supports both PC-AT and PS/2 modes.
For information aboutRefer to
The location of the diskette drive connectorFigure 8, page 60
The signal names of the diskette drive connectorTable 38, page 63
The supported diskette drive capacities and sizesTable 65, page 103
1.7.4 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these
†
connectors are protected with a PolySwitch
connection after an overcurrent condition is removed.
NOTE
✏
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top
PS/2 connector. Power to the computer should be turned off before a keyboard or mouse is
connected or disconnected.
circuit that, like a self-healing fuse, reestablishes the
26
Product Description
The keyboard controller contains the AMI keyboard and mouse controller code, provides the
keyboard and mouse control functions, and supports password protection for power-on/reset. A
power-on/reset password can be specified in the BIOS Setup program.
For information aboutRefer to
The location of the keyboard and mouse connectorsFigure 6, page 52
The signal names of the keyboard and mouse connectorsTable 18, page 53
1.8 Graphics Subsystem
The 815 chipset supports three graphics options: using the integrated GMCH graphics controller,
using an add-in AGP adapter, or using an add-in PCI adapter.
When using the GMCH graphics controller, a Graphics Performance Accelerator (GPA) card can
be installed (in the AGP connector) for enhanced 2D and 3D graphics performance. The GPA card
has a 32-bit 133 MHz SDRAM display cache; which is controlled by the GMCH graphics memory
controller.
When an add-in AGP adapter is installed, the GMCH graphics controller is disabled.
For information aboutRefer to
GPA card supportSection 1.8.3.1, page 30
1.8.1 Integrated Graphics Controller
The GMCH features the following:
• Integrated graphics controller
3D hyper-pipelined architecture
Full 2D hardware acceleration
Motion video acceleration
• 3D graphics visual and texturing enhancement
• Display
Integrated 24-bit 230 MHz RAMDAC
Compliant with Display Data Channel Standard, Version 3.0, Level 2B protocol
• Video
Hardware motion compensation for software MPEG2 decode
Software DVD at 30 fps
256 colors60, 70, 72, 75KDO
256 colors85KD
64 K colors60, 70KD3O
64 K colors72, 75, 85KD3
16 M colors60KDO
16 M colors75, 85KD
1280 x 768
256 colors60 (reduced blanking)KDOF
64 K colors60 (reduced blanking)KD3F
16 M colors60 (reduced blanking)KDF
1280 x 1024
256 colors60KDO
256 colors70, 72, 75, 85KD
64 K colors60, 70, 72, 75, 85KD3
16 M colors60, 70, 75, 85KD
1600 x 1200
Notes:K = Desktop
D = DirectDraw
3 = Direct3D† and OpenGL
O = Overlay
F = Digital Display Device only. A mode will be support ed on bot h analog CRTs and digital display devices
(the KD3O flags above apply to both types of displays ), unless indicated otherwis e.
256 colors
†
†
Frequencies (Hz)Notes
60, 70, 72, 75KD
Product Description
For information aboutRefer to
Obtaining graphics software and utilitiesSection 1.2, page 16
The board routes the Intel 82815 GMCH DVO port to an onboard 40-pin DVO connector. When a
Digital Visual Interface (DVI) or TV out card is installed in a back panel slot and cabled to the
DVO connector, the system supports DVI-compliant digital displays or TV out functionality. Use
of the DVO connector requires use of the onboard GMCH graphics controller.
For information aboutRefer to
The location of the DVO connectorFigure 7, page 56
The signal names of the DVO connectorTable 31, page 58
1.8.3 AGP Universal Connector
The AGP universal connector supports either:
• A GPA card with 133 MHz SDRAM display cache
• An AGP add-in card with 3.3 V or 1.5 V I/O
NOTE
✏
The cable connectors inserted in the ATAPI connectors may interfere with the installation of some
AGP cards. This is due to the location of the ATAPI connectors and depends on the AGP card
layout. Interference does not occur when using the legacy-style 2-mm CD ROM connector.
For information aboutRefer to
The location of the AGP universal connectorFigure 8, page 60
The signal names of the AGP universal connectorTable 37, page 62
1.8.3.1 Graphics Performance Accelerator (GPA) Card Support
The BIOS detects if a GPA card is present in the AGP connector and initializes up to 4 MB of
display cache on the card. The GMCH graphics memory controller accesses the display cache
over a single channel 32-bit SDRAM interface.
✏ NOTE
In earlier documentation, the GPA card was referred to as the Add-In Memory Module (AIMM).
1.8.3.2 AGP Add-in Card Support
AGP is a high-performance interface for graphics-intensive applications, such as 3D applications.
While based on the PCI Local Bus Specification, Rev. 2.1, AGP is independent of the PCI bus and
is intended for exclusive use with graphical display devices. AGP overcomes certain limitations of
the PCI bus related to handling large amounts of graphics data with the following features:
• Pipelined memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for nearly 100 percent efficiency
30
For information aboutRefer to
Obtaining the
Accelerated Graphics Port Interface Specification
Section 1.3, page 16
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