INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING T O SALE AND/OR USE OF INTEL PRODUCT S INCLUDING
LIABILITY OR WARRANTIES RELA TING T O FITNES S FOR A PARTICULAR PURPOSE, MERCHANT ABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life savin g, or
life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoev er for conflicts or incompatibilities arising from future
changes to them.
The Dual-Core Intel
®
Xeon® Processor 5100 Series may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
®
64-bit Intel® Xeon
and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled
BIOS. Performance will vary depending on your hardware and software configurations. Intel EM64T-enabled OS, BIOS, device
drivers and applications may not be available. Check with your vendor for more information.
processors with Intel® EM64T requires a computer syste m with a processor, chipset, BIOS, OS, device driver s
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Intel Xeon, Intel SpeedStep, Intel Extended Memory 64 Technology, Intel Virtualization Technology, and the Intel
7-2Extended HALT Maximum Power B-step................................................................93
7-3Extended HALT Maximum Power G-step................................................................93
8-1PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution................108
8-2Fan Specifications for 4-Pin Active CEK Thermal Solution............................. .. ........108
8-3Fan Cable Connector P in Out for 4-Pin Active CEK Thermal Solution ........................108
6Dual-Core Intel
®
Xeon® Processor 5100 Series Datasheet
Revision History
RevisionDescriptionDate
001Initial releaseJune 2006
002Updated Sections 2, 3, and 6 with SKUs for 5148/5138/5128November 2006
003Updated Sections 2, 3, and 6 with G-step information.August 2007
§
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet
7
8Dual-Core Intel
®
Xeon® Processor 5100 Series Datasheet
Features
Features
• Dual-Core processing with Intel® Core™ microarchitecture
• FC-LGA6 package with 771 Lands
• Available at up to 3.00 GHz processor speed
• 65 nm process technology
• Performance optimized version available
• Dual processing (DP) server support
• Includes 32-KB Level 1 instruction and 32-KB Level 1 data cache per core
• Includes 4-MB L2 Cache shared between the cores
• Intel
• 1066/1333 MHz system bus with Dual Independent Bus architecture
• Intel
• Intel® Virtualization Technology
• Intel® Wide Dynamic Execution
• Intel
• Intel® Smart Memory Access
• Demand-Based Switching (DBS) with Enhanced Intel SpeedStep® Technolog y
• Enhanced thermal and power management capabilities:
• Platform Environment Control Interface (PECI) to monitor Digital Thermal Sensors
The Dual-Core Intel
dual processor server, workstation, and embedded applications. Based on the Intel
Core™ micro-architecture, it is binary compatible with previous Intel
(IA-32) processors. The Dual-Core Intel Xeon Processor 5100 series are scalable to two
processors in a multiprocessor system, providing exceptional performance for
applications running on advanced operating systems such as Windows* XP, Windows
Server 2003, Linux*, and UNIX*.
®
®
®
• Thermal Monitor (TM1)
• Thermal Monitor 2 (TM2)
Advanced Smart Cache
64 Technology (Intel® 64)
Advanced Digital Media Boost
®
Xeon® Processor 5100 series is designed for high-performance
®
Architecture
The Dual-Core Intel Xeon Processor 5100 series delivers compute power at
unparalleled value and flexibility for powerful servers, internet infrastructure, and
departmental server applications. The Intel
Virtualization Te chnology deliver outstanding performance and headroom for peak
internet server workloads, resulting in faster response times, support for more users,
and improved scalability.
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet9
®
Core™ microarchitecture and Intel
§
Features
10Dual-Core Intel® Xeon® Processor 5100 Series Datasheet
Introduction
1Introduction
The Dual-Core Intel® Xeon® Processor 5100 Series are 64-bit server/workstation
processors utilizing two Intel microarchitecture cores. These processors are based on
Intel’s 65 nanometer process technology combining high performance with the power
efficiencies of a low-power microarchitecture. The Dual-Core Intel® Xeon® Processor
5100 Series maintain the tradition of compatibility with IA-32 software. Some key
features include on-die, 32 KB Level 1 instruction and data caches and 4 MB Level 2
cache with Advanced Transfer Cache Architecture. The processors’ Data Prefetch Logic
speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting
in reduced bus cycle penalties and improved performance. The 1333 MHz Front Side
Bus (FSB) is a quad-pumped bus running off a 333 MHz system clock making
10.66 GBytes per second data transfer rates possible. Some lower speed SKU’s are
available which support a 1066 MHz Front Side Bus (FSB). This is a quad-pumped bus
running off a 266 MHz system clock making 8.5 GBytes per second data transfer rates
possible. The Dual-Core Intel® Xeon® Processor 5160 offers higher clock frequencies
than the Dual-Core Intel
for the performance optimized segment.
®
Xeon® Processor 5100 Series for platforms that are targeted
Enhanced thermal and power management capabilities are implemented including
Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep
®
Technology. These technologies are targeted for dual processor in enterprise
environments. TM1 and TM2 provide efficient and effective cooling in high temperature
situations. Enhanced Intel SpeedStep
®
Technology provides power management
capabilities to servers and workstations.
®
Dual-Core Intel
Xeon® Processor 5100 Series features include Advanced Dynamic
Execution, enhanced floating point and multi-media units, Streaming SIMD Extensions
2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic Execution
improves speculative execution and branch prediction internal to the processor. The
floating point and multi-media units include 128-bit wide registers and a separate
register for data movement. SSE3 instructions provide highly efficient double-precision
floating point, SIMD integer, and memory management operations.
®
The Dual-Core Intel
64 Technology (Intel
Xeon® Processor 5100 Series support Intel® Extended Memory
®
EM64T) as an enhancement to Intel's IA-32 architecture. This
enhancement allows the processor to execute operating systems and applications
written to take advantage of the 64-bit extension technology. Further details on Intel
Extended Memory 64 Technology and its programming model can be found in the 64-bit Extension Technology Software Developer's Guide at http://developer.intel.com/
technology/64bitextensions/.
®
In addition, the Dual-Core Intel
Xeon® Processor 5100 Series support the Execute
Disable Bit functionality . When used in conjunction with a supporting operating system,
Execute Disable allows memory to be marked as executable or non executable. This
feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. Further details on
Execute Disable can be found at http://www.in tel.com/cd/ids/developer/asmo-na/eng/
149308.htm.
®
The Dual-Core Intel
Xeon® Processor 5100 Series support Intel® Virtualization
T echnology for hardw are-assisted virtualization within the processor. Intel Virtualization
Technology is a set of hardware enhancements that can improve virtualization
solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet11
Monitor software enabling multiple, independent software environments inside a single
platform. Further details on Intel Virtualization Technology can be found at http://
developer.intel.com/technology/vt.
The Dual-Core Intel
server and workstation systems. The Dual-Core Intel
support a Dual Independent Bus (DIB) architecture with one processor on each bus, up
to two processor sockets in a system. The DIB architecture provides improved
performance by allowing increased FSB speeds and bandwidth. The Dual-Core Intel
Xeon® Processor 5100 Series are packaged in an FC-LGA6 Land Grid Array package
with 771 lands for improved power delivery. It utilizes a surface mount LGA771 socket
that supports Direct Socket Loading (DSL).
Table 1-1.Dual-Core Intel
®
Xeon® Processor 5100 Series are intended for high performance
®
Xeon® Processor 5100 Series
®
Xeon® Processor 5100 Series
Introduction
®
# of Processor
Cores
2
L1 Cache
32 KB instruction
32 KB data
L2 Advanced
Transfer Cache
4 MB shared
Front Side Bus
Frequencies
1333 MHz
1066 MHz
Package
FC-LGA6
771 Lands
The Dual-Core Intel® Xeon® Processor 5100 Series based platforms implement
independent core voltage (VCC) power planes for each processor. FSB termination
voltage (VTT) is shared and must connect to all FSB agents. The processor core voltage
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the
power requirements of all frequencies of the Dual-Core Intel
®
Xeon® Processor 5100
Series. Refer to the appropriate platform design guidelines for implementation details.
The Dual-Core Intel® Xeon® Processor 5100 Series support 1333 MHz Front Side Bus
operation. The Dual-Core Intel® Xeon® Processor LV 5138 and Dual-Core Intel®
Xeon® Processor LV 5128 support 1066MHz Front Side Bus operation. The FSB utilizes
a split-transaction, deferred reply protocol and Source-Synchronous Transfer (SST) of
address and data to improve performance. The processor transfers data four times per
bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the
address bus can deliver addresses two times per bus clock and is referred to as a
‘double-clocked’ or a 2X address bus. In addition, the Request Phase completes in one
clock cycle. The FSB is also used to deliver interrupts.
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
Section 2.1 contains the electrical specifications of the FSB while implementation
details are fully described in the appropriate platform design guidelines (refer to
Section 1.3).
1.1Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the asserted state when driven to a low level. For example, when RESET# is low, a
reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Commonly used terms are explained here for clarification:
12Dual-Core Intel
®
Xeon® Processor 5100 Series Datasheet
Introduction
• Dual-Core Intel® Xeon® Processor 5100 Series – Intel 64-bit microprocessor
intended for dual processor servers and workstations. The Dual-Core Intel® Xeon
®
Processor 5100 Series are based on Intel’s 65 nanometer process, in the FC-LGA6
package with two processor cores. For this document, “processor” is used as the
generic term for the Dual-Core Intel® Xeon® Processor 5100 Series.
• Dual-Core Intel® Xeon® Processor LV 5148, Dual-Core Intel® Xeon® Processor LV 5138 and Dual-Core Intel® Xeon® Processor LV 5128- Intel
64-bit microprocessor intended for dual processor server blades and embedded
servers requiring higher case temperatures. The Dual-Core Intel® Xeon®
Processor LV 5148, Dual-Core Intel® Xeon® Processor LV 5138, and Dual-Core
Intel® Xeon® Processor LV 5128 are lower voltage, lower power version of the
Dual-Core Intel
®
Xeon® Processor 5100 Series. For this document “Dual-Core
Intel® Xeon® Processor L V 5148/5138/5128” is used to call out specifications that
are unique to the Dual-Core Intel® Xeon® Processor LV 5148/5138/5128 SKU.
• Dual-Core Intel® Xeon® Processor 5160- A performance optimized version of
the Dual-Core Intel® Xeon® Processor 5100 Series. For this document “Dual-Core
Intel® Xeon® Processor 5160” is used to call out specifications that are unique to
the Dual-Core Intel® Xeon® Processor 5160 SKU.
• FC-LGA6 (Flip Chip Land Grid Array) Package – The Dual-Core Intel
®
Xeon
®
Processor 5100 Series package is a Land Grid Array, consisting of a processor core
mounted on a pinless substrate with 771 lands, and includes an integrated heat
spreader (IHS).
• LGA771 socket – The Dual-Core Intel® Xeon® Processor 5100 Series interfaces to
the baseboard through this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for details regarding this socket.
• Processor core – Processor core with integrated L1 cache. L2 cache and system
bus interface are shared between the two cores on the die. All AC timing and signal
integrity specifications are at the pads of the processor core.
• FSB (Front Side Bus) – The electrical interface that connects the processor to the
chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Dual Independent Bus (DIB) – A front side bus architecture with one processor
on each bus, rather than a FSB shared between two processor agents. The DIB
architecture provides improved performance by allowing increased FSB speeds and
bandwidth.
• Flexible Motherboard Guidelines (FMB) – Are estimates of the maximum
values the Dual-Core Intel
®
Xeon® Processor 5100 Series will have over certain
time periods. The values are only estimates and actual specifications for future
processors may differ.
• Functional Operation – Refers to the normal operating conditions in which all
processor specifications, including DC, AC, FSB, signal quality, mechanical and
thermal are satisfied.
• Storage Conditions – Refers to a non-operational state. The processor may be
installed in a platform, in a tray , or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased or receive any clocks.
Upon exposure to “free air” (that is, unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet13
Introduction
• Priority Agent – The priority agent is the host bridge to the processor and is
typically known as the chipset.
• Symmetric Agent – A symmetric agent is a processor which shares the same I/O
subsystem and memory array, and runs the same operating system as another
processor in a system. Systems using symmetric agents are known as Symmetric
Multiprocessing (SMP) systems.
• Integrated Heat Spreader (IHS) – A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Thermal Design Power – Processor thermal solutions should be designed to meet
this target. It is the highest expected sustainable power while running known
power intensive real applications. TDP is not the maximum power that the
processor can dissipate.
®
•Intel
Extended Memory 64 Technology (Intel® EM64T) – An enhancement
to Intel's IA-32 architecture that allows the processor to execute operating systems
and applications written to take advantage of the 64-bit extension technology.
Further details on can be found in the 64-bit Extension Technology Software
Developer's Guide at http://developer.intel.com/.
®
• Enhanced Intel SpeedStep
Technology(EIST) – Technology that provides
power management capabilities to servers and workstations.
• Platform Environment Control Interface (PECI) – A proprietary one-wire bus
interface that provides a communication channel between Intel processor and
chipset components to external thermal monitoring devices, for use in fan speed
control. PECI communicates readings from the processor’s digital thermal sensor.
PECI replaces the thermal diode available in previous processors.
®
• Intel
Virtualization Technology – Processor virtualization which when used in
conjunction with Virtual Machine Monitor software enables multiple, robust
independent software environments inside a single platform.
• VRM (Voltage Regulator Module) – DC-DC converter built onto a module that
interfaces with a card edge socket and supplies the correct voltage and current to
the processor based on the logic state of the processor VID bits.
• EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated onto
the system board that provides the correct voltage and current to the processor
based on the logic state of the processor VID bits.
• V
• V
• V
– The processor core power supply.
CC
– The processor ground.
SS
– FSB termination voltage. (Note: In some Intel processor EMTS documents,
TT
is instead called V
V
TT
CCP
.)
1.2State of Data
The data contained within this document is the most accurate information available by
the publication date of this document. Values are subject to change prior to production.
1.3References
Material and concepts available in the following documents may be beneficial when
reading this document:
Electromagnetic Compatibility and Electrical Safety - Generic Criteria for
Network Telecomminications Equipment (GR-1089-CORE)
Note: Contact your Intel representative for the latest revision of these documents.
www.ssiforum.org
www.ssiforum.org
313357
315225
www.intel.com/design/Xeon/
documentation.htm
info.telcordia.com
http://telecom-
info.telcordia.com
§
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet15
Introduction
16Dual-Core Intel
®
Xeon® Processor 5100 Series Datasheet
Electrical Specifications
2Electrical Specifications
2.1Front Side Bus and GTLREF
Most Dual-Core Intel® Xeon® Processor 5100 Series FSB signals uses Assisted Gunning
Transceiver Logic (AGTL+) signaling technology. This technology provides improved
noise margins and reduced ringing through low voltage swings and controlled edge
rates.AGTL+ buffers are open-drain and require pull-up resistors to provide the high
logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the
addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during the
first clock of a low-to-high voltage transition. Platforms implement a termination
voltage level for AGTL+ signals defined as V
power planes for each processor (and chipset), separate V
necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address buses have made
signal integrity considerations and platform design methods even more critical than
with previous processor families. Design guidelines for the processor FSB are detailed
in the appropriate platform design guidelines (refer to Section 1.3).
The AGTL+ inputs require reference voltages (GTLREF_DATA and GTLREF_ADD) which
are used by the receivers to determine if a signal is a logical 0 or a logical 1.
GTLREF_DATA is used for the 4X front side bus signaling group and GTLREF_ADD is
used for the 2X and common clock front side bus signaling groups. Both GTLREF_DA TA
and GTLREF_ADD must be generated on the baseboard. Refer to the applicable
platform design guidelines for details. T ermination resistors (R
provided on the processor silicon and are terminated to V
resistors are always enabled on the Dual-Core Intel® Xeon® Processor 5100 Series to
control reflections on the transmission line. Intel chipsets also provide on-die
termination, thus eliminating the need to terminate the bus on the baseboard for most
AGTL+ signals.
. Because platforms implement separate
TT
and V
CC
TT
. The on-die termination
TT
supplies are
TT
) for AGTL+ signals are
Some FSB signals do not include on-die termination (R
) and must be terminated on
TT
the baseboard. See Table 2-9 for details regarding these signals.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog
signal simulation of the FSB, including trace lengths, is highly recommended when
designing a system. Contact your Intel Field Representative to obtain the processor
signal integrity models, which includes buffer and package models.
2.2Power and Ground Lands
For clean on-chip processor core power distribution, the processor has 223 VCC (power)
and 273 V
plane, while all V
processor V
Voltage IDentification (VID) signals. See Table 2-3 for VID definitions.
Twenty two lands are specified as V
provides power to the I/O buffers. The platform must implement a separate supply for
these lands which meets the V
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet17
(ground) inputs. All Vcc lands must be connected to the processor power
SS
CC
lands must be connected to the system ground plane. The
SS
lands must be supplied with the voltage determined by the processor
, which provide termination for the FSB and
TT
specifications outlined in Table 2-13.
TT
2.3Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the Dual-Core
®
Intel
swings between low and full power states. This may cause voltages on power planes to
sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage
(C
current demand by the component, such as coming out of an idle condition. Similarly,
they act as a storage well for current when entering an idle condition from a running
condition. Care must be taken in the baseboard design to ensure that the voltage
provided to the processor remains within the specifications listed in Table 2-13. Failure
to do so can result in timing violations or reduced lifetime of the component. For further
information and guidelines, refer to the appropriate platform design guidelines.
Xeon® Processor 5100 Series are capable of generating large average current
), such as electrolytic capacitors, supply current during longer lasting changes in
BULK
Electrical Specifications
2.3.1V
2.3.2V
Decoupling
CC
Vcc regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR), and the baseboard designer must assure a low interconnect
resistance from the regulator (EVRD or VRM pins) to the LGA771 socket. Bulk
decoupling must be provided on the baseboard to handle large current swings. The
power delivery solution must insure the voltage and current specifications are met (as
defined in Table 2-13). For further information regarding power delivery, decoupling
and layout guidelines, refer to the appropriate platform design guidelines.
Decoupling
TT
Bulk decoupling must be provided on the baseboard. Decoupling solutions must be
sized to meet the expected load. To insure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.
2.3.3Front Side Bus AGTL+ Decoupling
The Dual-Core Intel® Xeon® Processor 5100 Seriesintegrates signal termination on the
die, as well as a portion of the required high frequency decoupling capacitance on the
processor package. However, additional high frequency capacitance must be added to
the baseboard to properly decouple the return currents from the FSB. Bulk decoupling
must also be provided by the baseboard for proper AGTL+ bus operation. Decoupling
guidelines are described in the appropriate platform design guidelines.
2.4Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous processor generations, the Dual-Core Intel
5100 Series core frequency is a multiple of the BCLK[1:0] frequency . The processor bus
ratio multiplier is set during manufacturing. The default setting is for the maximum
speed of the processor. It is possible to override this setting using software (see the
Conroe and Woodcrest Processor Family BIOS Writer’s Guide). This permits operation
at lower frequencies than the processor’s tested frequency.
18Dual-Core Intel
®
Xeon® Processor
®
Xeon® Processor 5100 Series Datasheet
Electrical Specifications
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX MSR. For details of operation at core
frequencies lower than the maximum rated processor speed, refer to the Conroe and
Woodcrest Processor Family BIOS Writer’s Guide.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. The Dual-Core Intel
®
Xeon® Processor 5100 Series utilizes
differential clocks. Details regarding BCLK[1:0] driver specifications are provided in the
1.Listed frequencies illustrate clock frequency multipliers and are not necessarily committed production
frequencies for 40 W, 65 W or 80 W versions of Dual-Core Intel
2.Individual processors operate only at or below the frequency marked on the package.
3.For valid processor core frequencies, refer to the Dual-Core IntelSpecification Update.
4.The lowest bus ratio supported by the Dual-Core Intel
Core Frequency with
333 MHz FSB Clock
ProcessorNotes
®
Xeon® Processor 5100 Series.
®
Xeon® Processor 5100 Series
®
Xeon® Processor 5100 Seriesis 1/6.
2.4.1Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are CMOS outputs which must be pulled up to V
to select the FSB frequency. Please refer to Table 2-16 for DC specifications. Table 2-2
defines the possible combinations of the signals and the frequency associated with each
combination. The frequency is determined by the processor(s), chipset, and clock
synthesizer. All FSB agents must operate at the same core and FSB frequency. See the
appropriate platform design guidelines for further details.
Table 2-2.BSEL[2:0] Frequency Tab le (Sheet 1 of 2)
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet19
Table 2-2.BSEL[2:0] Frequency Table (Sheet 2 of 2)
BSEL2BSEL1BSEL0Bus Clock Frequency
101Reserved
110Reserved
111Reserved
2.4.2PLL Power Supply
Electrical Specifications
An on-die PLL filter solution is implemented on the Dual-Core Intel® Xeon® Processor
5100 Series. The V
input is used for this configuration in Dual-Core Intel® Xeon
CCPLL
Processor 5100 Series based platforms. Please refer to Table 2-13 for DC specifications.
Refer to the appropriate platform design guidelines for decoupling and routing
guidelines.
2.5Voltage Identification (VID)
The Voltage Identi fication (VID) s pecification for the Dual-Core Intel® Xeon® Processor
5100 Series is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines. The voltage set by the VID signals is
the reference VR output voltage to be delivered to the processor Vcc pins. VID signals
are open drain outputs, which must be pulled up to V
the DC specifications for these signals. A voltage range is provided in Table 2-13 and
changes with frequency. The specifications have been set such that one voltage
regulator can operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in Table 2-3.
®
The Dual-Core Intel
signals, VID[6:1], to support automatic selection of power supply voltages. Table 2-3
specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. The definition
provided in Table 2-3 is not related in any way to previous Intel
voltage regulator designs. If the processor socket is empty (VID[6:1] = 111111), or
the voltage regulation circuit cannot supply the voltage that is requested, the voltage
regulator must disable itself. See the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details.
Xeon® Processor 5100 Series uses six voltage identification
. Please refer to Table 2-16 for
TT
®
Xeon® processors or
®
Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines defines VID[7:0], VID[7] and VID[0] are not used on
the Dual-Core Intel
The Dual-Core Intel
transitioning to an adjacent VID and its associated processor core voltage (V
will represent a DC shift in the load line. It should be noted that a low-to-high or highto-low voltage state change may result in as many VID transitions as necessary to
reach the target core voltage. Transitions above the specified VID are not permitted.
Table 2-13 includes VID step sizes and DC shift ranges. Minimum and maximum
voltages must be maintained as shown in Table 2-14 and Table 2-2.
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
Table 2-13 and Table 2-14.
20Dual-Core Intel
®
Xeon® Processor 5100 Series.
®
Xeon® Processor 5100 Series provides the ability to operate while
). This
CC
®
Xeon® Processor 5100 Series Datasheet
Electrical Specifications
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
1.When the “111111” VID pattern is observed, the voltage regulator output should be disabled.
2.Shading denotes the expected VID range of the Dual-Core Intel
3.The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see
Section 6.2.1.2), Extended HALT state transitions (see Section 7.2.2), or Enhanced Intel SpeedStep
(see Section 7.3). The Extended HALT state must be enabled for the processor to remain within its specifications.
4.Once the VRM/EVRD is operating after power-up, if either the Output Enab le signal is de-asserte d or a specific VID off code is
received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until
power is cycled. Refer to Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines.
22Dual-Core Intel
®
Xeon® Processor 5100 Series.
®
Xeon® Processor 5100 Series Datasheet
®
Technology transitions
Electrical Specifications
Table 2-5.Loadline Selection Truth Table for LL_ID[1:0]
Note: The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be
used for future processor compatibility or for keying.
®
Xeon® Processor 5100 Series
2.6Reserved or Unused Signals
All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT,
, or to any other signal (including each other) can result in component malfunction
V
SS
or incompatibility with future processors. See Section 4 for a land listing of the
processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (V
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noticed in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
Some TAP, CMOS Asynchronous inputs and CMOS Asynchronous outputs do not include
on-die termination. Inputs and utilized outputs must be terminated on the baseboard.
Unused outputs may be terminated on the baseboard or left unconnected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. Signal termination for
these signal types is discussed in the appropriate platform design guidelines.
Each of the TESTHI signals must be tied to the processor V
matched resistor, where a matched resistor has a resistance value within ± 20% of the
impedance of the board transmission line traces. F or example, if the trace impedance is
50 Ω, then a value between 40 Ω and 60 Ω is required.
). Unused outputs can be left unconnected; however, this may
SS
).
TT
individually using a
TT
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet23
2.7Front Side Bus Signal Groups
The FSB signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF_DA TA and GTLREF_ADD as reference
levels. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the
AGTL+ output group as well as the AGTL+ I/O group when driving. AGTL+
asynchronous outputs can become active anytime and include an active PMOS pull-up
transistor to assist during the first clock of a low-to-high voltage transition.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and
the second set is for the source synchronous signals which are relative to their
respective strobe lines (data and address) as well as rising edge of BCLK0.
Asynchronous signals are still present (A20M#, IGNNE#, and so forth) and can become
active at any time during the clock cycle. Table 2-7 identifies which signals are common
clock, source synchronous and asynchronous.
Table 2-7.FSB Signal Groups
Signal GroupTypeSignals
AGTL+ Common Clock InputSynchronous to BCLK[1:0]BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
AGTL+ Common Clock Output Synchronous to BCLK[1:0]BPM4#, BPM[2:1]#
AGTL+ Common Clock I/OSynchronous to BCLK[1:0]ADS#, AP[1:0]#, BINIT#
CMOS Asynchronous Output AsynchronousBSEL[2:0], VID[6:1]
FSB ClockClockBCLK[1:0]
TAP InputSynchronous to TCKTCK, TDI, TMS, TRST#
TAP OutputSynchronous to TCKTDO
Power/OtherPower/OtherGTLREF_ADD_MID, GTLREF_ADD_END,
2.8CMOS Asynchronous and Open Drain
Asynchronous Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain
signals are required to be asserted/deasserted for at least eight BCLKs in order for the
processor to recognize the proper signal state. See Chapter 6 for additional timing
requirements for entering and leaving the low power states.
2.9Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet25
Electrical Specifications
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TMS, TDO, and TRST#. Two copies of each signal may be required with each
driving a different voltage level.
2.10Platform Environmental Control Interface (PECI)
DC Specifications
The release of the Dual-Core Intel® Xeon® Processor 5100 Series marks the transition
from thermal diodes to digital thermal sensors for fan speed control. Digital Thermal
Sensors (DTS) are on-die, analog-to-digital temperature converters calibrated at the
factory for reasonable accuracy to provide a digital representation of relative processor
temperature. Data from the DTS are processed and stored in a processor register,
which is queried through the Platform Environment Control Interface (PECI). PECI is a
proprietary one-wire bus interface that provides a communication channel between
Intel processor and chipset components to external thermal monitoring devices. More
detailed information may be found in Section 6.3.
2.10.1DC Characteristics
A PECI device interface operates at a nominal voltage set by VTT. The set of DC
electrical specifications shown in Table 2-11 is used with devices normally operating
from a V
PECI devices will operate at the VTT level determined by the processor installed in the
system. For specific nominal V
interface supply . VTT nominal levels will vary between processor families. All
TT
levels, refer to the appropriate processor EMTS.
TT
Table 2-11. PECI DC Electrical Limits
SymbolDefinition and ConditionsMinMaxUnitsNotes
V
in
V
hysteresis
V
n
V
p
I
source
I
sink
I
leak+
I
leak-
C
bus
V
noise
Note:
1.V
2.The leakage specification applies to powered devices on the PECI bus.
supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.
TT
Input Voltage Range-0.150VTT + 0.150V
Negative-edge threshold
Positive-edge threshold
High level output source
(V
Low level output sink
(V
High impedance state
High impedance leakage
Bus capacitanceN/A10pF
Signal noise immunity
above 300 MHz
Hysteresis0.1 * V
voltage
voltage
= 0.75 * VTT)
OH
= 0.25 * VTT)
OL
leakage to V
= VOL)
(V
leak
TT
0.275 * V
0.550 * V
to GND
= VOH)
(V
leak
0.1 * V
TT
TT
TT
N/AV
0.500 * V
0.725 * V
V
TT
V
TT
-6.0N/AmA
0.51.0mA
N/A50µA2
N/A10µA2
TT
N/AV
p-p
1
26Dual-Core Intel
®
Xeon® Processor 5100 Series Datasheet
Electrical Specifications
2.10.2Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 2-1 as a guide for input buffer design.
Figure 2-1. Input Device Hysteresis
V
TT
Maximum V
Minimum V
Maximum V
Minimum V
P
P
N
N
PECI High Range
PECI Low Range
Minimum
Hysteresis
Valid Input
Signal Range
PECI Ground
2.11Mixing Processors
Intel supports and validates dual processor configurations only in which both
processors operate with the same FSB frequency , core frequency, power segments, and
have the same internal cache sizes. Mixing components operating at different internal
clock frequencies is not supported and will not be validated by Intel. Combining
processors from different power segments is also not supported.
Note:Processors within a system must operate at the same frequency per bits [12:8] of the
CLOCK_FLEX_MAX MSR; however this does not apply to frequency transitions initiated
due to thermal events, Extended HALT, Enhanced Intel SpeedStep
transitions, or assertion of the FORCEPR# signal (See Chapter 6).
®
Technology
Not all operating systems can support dual processors with mixed frequencies. Mixing
processors of different steppings but the same model (as per CPUID instruction) is
supported. Details regarding the CPUID instruction are provided in the Intel Processor Identification and the CPUID Instruction application note.
2.12Absolute Maximum and Minimum Ratings
Table 2-12 specifies absolute maximum and minimum ratings only, which lie outside
the functional limits of the processor. Only within specified operation limits, can
functionality and long-term reliability be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet27
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
.
electric fields.
Table 2-12. Processor Absolute Maximum Ratings
SymbolParameterMinMaxUnitNotes
V
CC
V
TT
T
CASE
T
STORAGE
Notes:
1.For functional operation, all processor el ectrical, sign al quality, mechanical and thermal specifications must
be satisfied.
2.Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 3.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
3.Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specifications.
4.This rating applies to the processor and does not include any tray or packaging.
5.Failure to adhere to this specification can affect the long-term reliability of the processor.
Core voltage with respect to VSS-0.301.55V
FSB termination voltage with respect to V
Processor case temperatureSee
Storage temperature-4085°C3, 4, 5
-0.301.55V
SS
Chapter 6
Electrical Specifications
See
Chapter 6
1, 2
°C
28Dual-Core Intel
®
Xeon® Processor 5100 Series Datasheet
Electrical Specifications
2.13Processor DC Specifications
The processor DC specifications in this section are defined at the processor
core (pads) unless noted otherwise. See Section 4-1 for the Dual-Core Intel
Xeon® Processor 5100 Series land listings and Section 5.1 for signal definitions.
Voltage and current specifications are detailed in Table 2-13. For platform planning
refer to Table 2-14, which provides VCC static and transient tolerances. This same
information is presented graphically in Figure 2-4.
The DC specifications for the AGTL+ signals are listed in Table 2-15. Legacy signals and
Test Access Port (TAP) signals follow DC specifications similar to CMOS. The DC
specifications for the PWRGOOD input and TAP signal group are listed in Table 2-16.
Table 2-13 through Table 2-18 list the DC specifications for the processor and are valid
only while meeting specifications for case temperature (T
“Thermal Specifications”), clock frequency, and input voltages. Care should be taken to
read all notes associated with each parameter.
Table 2-13. Voltage and Current Specifications (Sheet 1 of 2)
SymbolParameterMinTypMaxUnit
VID B2 stepVID range1.00001.5000V
VID G0 stepVID range0.85001.5000V
V
CC
V
CC_BOOT
V
VID_STEP
V
VID_SHIFT
V
TT
V
CCPLL
I
CC
I
CC
I
CC
I
CC_RESET
I
CC_RESET
I
CC_RESET
I
TT
VCC for processor coreSee Table 2-14 and Figure 2-4V2, 3, 4, 6,
Default VCC Voltage for
initial power up
VID step size during a
transition
Total allowable DC load line
shift from VID steps
FSB termination voltage (DC
+ AC specification)
PLL supply voltage (DC + AC
specification)
ICC for Dual-Core Intel®
Xeon® Processor LV 5148/
5138/5128 core with
multiple VID
ICC for Dual-Core Intel
Xeon® Processor 5100
Series core with multiple VID
ICC for Dual-Core Intel®
Xeon® Processor 5160 core
with multe VID
I
Intel® Xeon® Processor LV
5148/5138/5128 core with
multiple VID
I
Intel
Series core with multiple VID
I
Intel® Xeon® Processor
5160 core with multiple VID
FSB termination current4.60A16
for Dual-Core
CC_RESET
for Dual-Core
CC_RESET
®
Xeon® Processor 5100
for Dual-Core
CC_RESET
®
1.141.201.26V9, 14
1.4551.5001.605V
1.10V2
as specified in Chapter 6,
CASE
± 12.5mV
450mV11
45A4, 5, 6, 10
75A4, 5, 6, 10
90A4, 5, 6, 10
45A7
75A7
90A7
®
Notes
1,13
10
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet29
Table 2-13. Voltage and Current Specifications (Sheet 2 of 2)
Thermal Design Current
(TDC) Dual-Core Intel
Xeon® Processor 5100
®
4.5
4.6
35A6,15
60A6,15
Series
I
CC_TDC
Thermal Design Current
(TDC) Dual-Core Intel®
70A6,15
Xeon® Processor 5160
I
CC_VTT_OUT
I
CC_GTLREF
I
CC_VCCPLL
I
TCC
I
TCC
I
TCC
DC current that may be
drawn from V
ICC for
GTLREF_DATA and
GTLREF_ADD
TT_OUT
per land
ICC for PLL supply130mA13
I
for Dual-Core Intel®
CC
Xeon® Processor LV 5148/
5138/5128 during active
thermal control circuit (TCC)
I
for Dual-Core Intel
CC
Xeon® Processor 5100
Series during active thermal
control circuit (TCC)
I
for Dual-Core Intel®
CC
Xeon® Processor 5160
during active thermal control
®
580mA17
200µA8
45A
65A
90A
circuit (TCC)
Notes
1,13
A16
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processors and are based on estimates
and simulations, not empirical data. These specifications will be updated with characterized data from
silicon measurements at a later date.
2.These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.5 for more information.
3.The voltage specification requirements are m eas ured across the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with an oscilloscope set to 100 MHz
bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ens ure e xter nal no ise from the s yste m is not coupled
in the scope probe.
4.The processor must not be subjected to any static V
particular current. Failure to adhere to this specification can shorten processor lifetime.
5.I
6.I
7.This specification represents the total current for GTLREF_DATA and GTLREF_ADD.
8.V
9.Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE)
10. This specification refers to the total reduction of the load line due to VID transitions below the specified
11. Individual processor VID values may be calibrated du ring manufacturing such that t wo devices at the same
12. This specification applies to the VCCPLL land.
13. Baseboard bandwidth is limited to 20 MHz.
specification is based on maximum V
CC_MAX
to 10 ms.
measured at the land.
is specified while PWRGOOD and RESET# are asserted.
CC_RESET
must be provided via a separate voltage source and must not be connected to VCC. This specification is
TT
CC
shown in Figure 6-1.
VID.
frequency may have different VID settings.
level that exceeds the V
CC
loadline The processor is capable of drawing I
30Dual-Core Intel
associated with any
CC_MAX
CC_MAX
®
Xeon® Processor 5100 Series Datasheet
for up
Loading...
+ 82 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.