Intel 460GX User Manual

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Intel® 460GX Chipset System

Software Developer’s Manual

June 2001

Document Number: 248704-001

THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” elIntreserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel 460GX chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://developer.intel.com/design/litcentr.

Intel and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

Copyright © 2002, Intel Corporation

*Other names and brands may be claimed as the property of others.

ii

Intel® 460GX Chipset System Software Developer’s Manual

Contents

1

Introduction......................................................................................................................

 

1-1

 

1.1

System Overview ...............................................................................................

1-1

 

 

1.1.1

Component Overview............................................................................

1-2

 

1.2

Product Features................................................................................................

1-3

 

1.3

Itanium™ Processor System Bus Support .........................................................

1-3

 

1.4

DRAM Interface Support ....................................................................................

1-4

 

1.5

I/O Support .........................................................................................................

1-4

 

 

1.5.1

PXB Features ........................................................................................

1-4

 

 

1.5.2

WXB Features .......................................................................................

1-6

 

 

1.5.3

GXB Features........................................................................................

1-6

 

1.6

RAS Features.....................................................................................................

1-6

 

1.7

Other Platform Components...............................................................................

1-6

 

 

1.7.1 I/O & Firmware Bridge (IFB)..................................................................

1-6

 

 

1.7.2 Programmable Interrupt Device (PID) ...................................................

1-7

 

1.8

Reference Documents........................................................................................

1-7

 

1.9

Revision History .................................................................................................

1-7

2

Register Descriptions ......................................................................................................

2-1

 

2.1

Access Mechanism ............................................................................................

2-1

 

2.2

Access Restrictions ............................................................................................

2-2

 

 

2.2.1

Partitioning ............................................................................................

2-2

 

 

2.2.2

Register Attributes.................................................................................

2-3

 

 

2.2.3 Reserved Bits Defined in Registers.......................................................

2-3

 

 

2.2.4 Reserved or Undefined Register Locations...........................................

2-3

 

 

2.2.5

Default Upon Reset ...............................................................................

2-3

 

 

2.2.6

Consistency...........................................................................................

2-4

 

 

2.2.7

GART Programming Region .................................................................

2-4

 

2.3

I/O Mapped Registers ........................................................................................

2-4

 

 

2.3.1 CONFIG_ADDRESS: Configuration Address Register .........................

2-4

 

 

2.3.2 CONFIG_DATA: Configuration Data Register ......................................

2-5

 

2.4

Error Handling Registers ....................................................................................

2-5

 

 

2.4.1

SAC .......................................................................................................

2-5

 

 

2.4.2

SDC.....................................................................................................

2-11

 

 

2.4.3

MAC ....................................................................................................

2-21

 

 

2.4.4

PXB .....................................................................................................

2-22

 

 

2.4.5

GXB.....................................................................................................

2-24

 

 

2.4.6

WXB ....................................................................................................

2-27

 

2.5

Performance Monitor Registers........................................................................

2-30

 

 

2.5.1

SAC .....................................................................................................

2-30

 

 

2.5.2

SDC.....................................................................................................

2-34

 

 

2.5.3

PXB .....................................................................................................

2-36

 

 

2.5.4

GXB.....................................................................................................

2-38

 

 

2.5.5

WXB ....................................................................................................

2-43

 

2.6

Interrupt Related Registers ..............................................................................

2-44

 

 

2.6.1

SAC .....................................................................................................

2-44

 

 

2.6.2 PID PCI Memory-mapped Registers ...................................................

2-45

 

 

2.6.3 PID Indirect Access Registers.............................................................

2-46

Intel® 460GX Chipset System Software Developer’s Manual

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3

System Architecture ........................................................................................................

3-1

 

3.1

Coherency..........................................................................................................

3-1

 

 

3.1.1

Processor Coherency............................................................................

3-1

 

 

3.1.2

PCI Coherency......................................................................................

3-2

 

 

3.1.3

AGP Coherency ....................................................................................

3-2

 

3.2

Ordering .............................................................................................................

3-2

 

3.3

Processor to PCI Traffic and PCI to PCI (Peer-to-Peer) Traffic .........................

3-3

 

3.4

WXB Arbitration..................................................................................................

3-3

 

3.5

Big-endian Support ............................................................................................

3-4

 

3.6

Indivisible Operations.........................................................................................

3-4

 

 

3.6.1

Processor Locks....................................................................................

3-4

 

 

3.6.2

Inbound PCI Locks................................................................................

3-5

 

 

3.6.3

Atomic Writes ........................................................................................

3-5

 

 

3.6.4

Atomic Reads........................................................................................

3-5

 

 

3.6.5 Locks with AGP Non-coherent Traffic ...................................................

3-5

 

3.7

Interrupt Delivery................................................................................................

3-6

 

3.8

WXB PCI Hot-Plug Support ...............................................................................

3-6

 

 

3.8.1 Slot Power-up and Enable ....................................................................

3-7

 

 

3.8.2 Slot Power-down and Disable ..............................................................

3-7

4

System Address Map ......................................................................................................

4-1

 

4.1

Memory Map ......................................................................................................

4-1

 

 

4.1.1

Compatibility Region .............................................................................

4-1

 

 

4.1.2 Low Extended Memory Region .............................................................

4-3

 

 

4.1.3 Medium Extended Memory Region.......................................................

4-3

 

 

4.1.4 High Extended Memory (above 4G)......................................................

4-4

 

 

4.1.5

Re-mapped Memory Areas ...................................................................

4-4

 

4.2

I/O Address Map ................................................................................................

4-5

 

4.3

Devices View of the System Memory Map.........................................................

4-7

 

4.4

Legal and Illegal Address Disposition ................................................................

4-8

5

Memory Subsystem ........................................................................................................

5-1

 

5.1

Organization.......................................................................................................

5-1

 

 

5.1.1

DIMM Types..........................................................................................

5-3

 

5.2

Interleaving/Configurations ................................................................................

5-4

 

 

5.2.1 Summary of Configuration Rules ..........................................................

5-5

 

 

5.2.2

Non-uniform Memory Configurations ....................................................

5-5

 

5.3

Bandwidth ..........................................................................................................

5-5

 

5.4

Memory Subsystem Clocking.............................................................................

5-6

 

5.5

Supporting Features...........................................................................................

5-6

 

 

5.5.1

Auto Detection.......................................................................................

5-6

 

 

5.5.2 Removing a Bad Row ...........................................................................

5-6

 

 

5.5.3

Hardware Initialization...........................................................................

5-7

 

 

5.5.4

Memory Scrubbing ................................................................................

5-7

6

Data Integrity and Error Handling...................................................................................

6-1

 

6.1

Integrity

..............................................................................................................

6-1

 

 

6.1.1

System Bus ...........................................................................................

6-1

 

 

6.1.2

DRAM....................................................................................................

6-2

 

 

6.1.3

Expander Buses....................................................................................

6-2

 

 

6.1.4

PCI Buses .............................................................................................

6-2

 

 

6.1.5

AGP.......................................................................................................

6-2

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Intel® 460GX Chipset System Software Developer’s Manual

 

 

6.1.6

Private Bus between SAC and SDC .....................................................

6-2

 

6.2

Memory ECC Routing ........................................................................................

6-3

 

6.3

Data Poisoning ...................................................................................................

6-3

 

6.4

Usage of First-error and Next-error ....................................................................

6-3

 

 

6.4.1

Masked Bits...........................................................................................

6-4

 

 

6.4.2

BERR#/BINIT# Generation ...................................................................

6-4

 

 

6.4.3

INTREQ#...............................................................................................

6-4

 

 

6.4.4

XBINIT#.................................................................................................

6-5

 

 

6.4.5

XSERR# ................................................................................................

6-5

 

6.5

SAC/SDC Errors.................................................................................................

6-5

 

 

6.5.1

Data ECC or Parity Errors .....................................................................

6-5

 

 

6.5.2

System Bus Errors ................................................................................

6-6

 

 

6.5.3

SAC to SDC Interface Errors.................................................................

6-6

 

 

6.5.4

SAC to MAC Interface Errors ................................................................

6-7

 

 

6.5.5

SDC/Memory Card Interface Errors ......................................................

6-7

 

 

6.5.6

SDC/System Bus Errors........................................................................

6-8

 

 

6.5.7

SDC Internal Errors ...............................................................................

6-8

 

6.6

Error Determination ............................................................................................

6-8

 

 

6.6.1

SAC Address on an Error......................................................................

6-9

 

 

6.6.2

SDC Logging Registers.......................................................................

6-10

 

6.7

Clearing Errors .................................................................................................

6-11

 

 

6.7.1

SAC/SDC Error Clearing .....................................................................

6-11

 

6.8

Multiple Errors ..................................................................................................

6-11

 

 

6.8.1

SDC Multiple Errors.............................................................................

6-12

 

 

6.8.2

SAC Multiple Errors.............................................................................

6-13

 

 

6.8.3

Single Errors with Multiple Reporting ..................................................

6-13

 

 

6.8.4

Error Anomalies...................................................................................

6-13

 

6.9

Data Flow Errors ..............................................................................................

6-14

 

6.10

Error Conditions ...............................................................................................

6-15

 

 

6.10.1

Table of Errors.....................................................................................

6-15

 

6.11

PCI Integrity......................................................................................................

6-20

 

 

6.11.1

PCI Bus Monitoring .............................................................................

6-20

 

 

6.11.2

PXB as Master ....................................................................................

6-20

 

 

6.11.3

PXB as Target .....................................................................................

6-21

 

 

6.11.4

GXB Error Flow ...................................................................................

6-22

 

6.12

WXB Data Integrity and Error Handling............................................................

6-26

 

 

6.12.1

Integrity................................................................................................

6-26

 

 

6.12.2

Data Parity Poisoning..........................................................................

6-26

 

 

6.12.3

Usage of First Error and Next Error Registers ....................................

6-26

 

 

6.12.4

Error Mask Bits....................................................................................

6-27

 

 

6.12.5

Error Steering/Signaling ......................................................................

6-27

 

 

6.12.6

INTRQ# Interrupt.................................................................................

6-29

 

 

6.12.7

Error Determination and Logging ........................................................

6-29

 

 

6.12.8

Error Conditions ..................................................................................

6-30

7

AGP Subsystem ..............................................................................................................

7-1

 

7.1

Graphics Address Relocation Table (GART) .....................................................

7-1

 

 

7.1.1

GART Implementation...........................................................................

7-3

 

 

7.1.2

Programming GART..............................................................................

7-4

 

 

7.1.3

GART Implementation...........................................................................

7-5

 

 

7.1.4

Coherency .............................................................................................

7-5

 

 

7.1.5

Interrupt Handling..................................................................................

7-6

Intel® 460GX Chipset System Software Developer’s Manual

v

 

7.2

AGP Traffic.........................................................................................................

7-6

 

 

7.2.1

Addresses Used by the Graphics Card .................................................

7-6

 

 

7.2.2

Traffic Priority ........................................................................................

7-7

 

 

7.2.3

Coherency, Translation and Types of AGP Traffic ................................

7-7

 

 

7.2.4

Ordering Rules ......................................................................................

7-8

 

 

7.2.5

Processor Locks and AGP Traffic .........................................................

7-8

 

 

7.2.6

Address Alignment and Transfer Sizes .................................................

7-9

 

 

7.2.7

PCI Semantics Traffic ...........................................................................

7-9

 

7.3

Bandwidth ........................................................................................................

7-13

 

 

7.3.1

Inbound Read Prefetching ..................................................................

7-14

 

7.4

Latency

.............................................................................................................

7-14

 

7.5

GXB Address ...........................................................................................Map

7-14

8

WXB Hot-Plug .................................................................................................................

 

8-1

 

8.1

IHPC Configuration ............................................................................Registers

8-1

 

 

8.1.1 ...................

Page Number List for the IHPC PCI Register Descriptions

8-3

 

 

8.1.2 .......................................................

VID: Vendor Identification Register

8-3

 

 

8.1.3 ........................................................

DID: Device Identification Register

8-3

 

 

8.1.4 ........................................................

PCICMD: PCI Command Register

8-4

 

 

8.1.5 ................................................................

PCISTS: PCI Status Register

8-5

 

 

8.1.6 .....................................................

RID: Revision Identification Register

8-5

 

 

8.1.7 .........................................................................

CLASS: Class Register

8-6

 

 

8.1.8 ...........................................................................

CLS: Cache Line Size

8-6

 

 

8.1.9 ....................................................

MLT: Master Latency Timer Register

8-6

 

 

8.1.10 ..........................................................................

HDR: Header Register

8-6

 

 

8.1.11 ........................................................................................

Base Address

8-7

 

 

8.1.12 ................................................

SVID: Subsystem Vendor Identification

8-7

 

 

8.1.13 ................................................................................

SID: Subsystem ID

8-7

 

 

8.1.14 .........................................................................................

Interrupt Line

8-7

 

 

8.1.15 ...........................................................................................

Interrupt Pin

8-8

 

 

8.1.16 ..........................................................................

Hot - Plug Slot Identifier

8-8

 

 

8.1.17 ..................................................

Miscellaneous Hot - Plug Configuration

8-8

 

 

8.1.18 .................................................................................

Hot - Plug Features

8-9

 

 

8.1.19 ................................................................

Switch Change SERR Status

8-9

 

 

8.1.20 .....................................................................

Power Fault SERR Status

8-9

 

 

8.1.21 ...........................................................................

Arbiter SERR Status

8-10

 

 

8.1.22 .........................................................................

Memory Access Index

8-10

 

 

8.1.23 ...............................................

Memory Mapped Register Access Port

8-10

 

8.2

IHPC Memory ....................................................................Mapped Registers

8-10

8.2.1Page Number List for IHPC Memory Mapped Register Descriptions..8-12

8.2.2

Slot Enable..........................................................................................

8-12

8.2.3

Hot-Plug Miscellaneous ......................................................................

8-13

8.2.4

LED Control.........................................................................................

8-13

8.2.5

Hot-Plug Interrupt Input and Clear ......................................................

8-14

8.2.6

Hot-Plug Interrupt Mask ......................................................................

8-15

8.2.7

Serial Input Byte Data .........................................................................

8-16

8.2.8

Serial Input Byte Pointer .....................................................................

8-17

8.2.9

General Purpose Output .....................................................................

8-17

8.2.10

Hot-Plug Non-interrupt Inputs .............................................................

8-17

8.2.11

Hot-Plug Slot Identifier ........................................................................

8-17

8.2.12

Hot-Plug Switch Interrupt Redirect Enable..........................................

8-18

8.2.13

Slot Power Control ..............................................................................

8-18

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Intel® 460GX Chipset System Software Developer’s Manual

 

 

8.2.14

Extended Hot-Plug Miscellaneous ......................................................

8-18

9

IFB Register Mapping......................................................................................................

9-1

 

9.1

PCI / LPC / FWH Configuration..........................................................................

9-1

 

 

9.1.1

PCI Configuration Registers (Function 0)..............................................

9-1

 

9.2

IDE Configuration ...............................................................................................

9-3

 

 

9.2.1

PCI Configuration Registers (Function 1)..............................................

9-3

 

9.3

Universal Serial Bus (USB) Configuration..........................................................

9-4

 

 

9.3.1

PCI Configuration Registers (Function 2)..............................................

9-4

 

9.4

SMBus Controller Configuration.........................................................................

9-5

 

 

9.4.1

SMBus Configuration Registers (Function 3) ........................................

9-5

10

IFB Usage Considerations ............................................................................................

10-1

 

10.1

Usage of 1MIN Timer in Power Management ..................................................

10-1

 

10.2

Usage of the SW SMI# Timer...........................................................................

10-1

 

10.3

CD-ROM AUTO RUN Feature of the OS .........................................................

10-1

 

10.4

ACPI, SMBus, GPIO Base Address Reporting to the OS ................................

10-1

 

10.5

Ultra DMA Configuration ..................................................................................

10-2

 

 

10.5.1

UDMAC–Ultra DMA Control Register (IFB Function 1 PCI

 

 

 

 

Configuration Offset 48h) ....................................................................

10-2

 

 

10.5.2

UDMATIM–Ultra DMA Timing Register (IFB Function 1 PCI

 

 

 

 

Configuration Offsets 4A-4Bh) ............................................................

10-2

 

 

10.5.3

Determining a Drive’s Transfer Rate Capabilities ...............................

10-3

 

 

10.5.4

Determining a Drive’s Best Ultra DMA Capability ...............................

10-5

 

 

10.5.5

Determining a Drive’s Best Multi Word DMA/Single Word DMA

 

 

 

 

(Non-ultra DMA) Capability .................................................................

10-5

 

 

10.5.6

IFB Timing Settings .............................................................................

10-9

 

 

10.5.7

Drive Configuration for Selected Timings..........................................

10-11

 

 

10.5.8

Settings Checklist..............................................................................

10-13

 

 

10.5.9

Example Configurations ....................................................................

10-14

 

 

10.5.10

Ultra DMA System Software Considerations.....................................

10-16

 

 

10.5.11 Additional Ultra DMA/PCI Bus Master IDE Device Driver

 

 

 

 

Considerations ..................................................................................

10-17

 

10.6

USB Resume Enable Bit ................................................................................

10-19

11

LPC/FWH Interface Configuration.................................................................................

11-1

 

11.1

PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0) ..

11-1

 

 

11.1.1

VID–Vendor Identification Register (Function 0) .................................

11-1

 

 

11.1.2

DID–Device Identification Register (Function 0) .................................

11-1

 

 

11.1.3

PCICMD–PCI Command Register (Function 0) ..................................

11-2

 

 

11.1.4

PCISTS–PCI Device Status Register (Function 0)..............................

11-2

 

 

11.1.5

RID–Revision Identification Register (Function 0)...............................

11-3

 

 

11.1.6

CLASSC–Class Code Register (Function 0).......................................

11-3

 

 

11.1.7

HEDT–Header Type Register (Function 0) .........................................

11-3

 

 

11.1.8

ACPI Base Address (Function 0) ........................................................

11-4

 

 

11.1.9

ACPI Enable (Function 0)....................................................................

11-4

 

 

11.1.10

SCI IRQ Routing Control .....................................................................

11-4

 

 

11.1.11

BIOSEN–BIOS Enable Register (Function 0) .....................................

11-5

 

 

11.1.12

PIRQRC[A:D]–PIRQx Route Control Registers (Function 0) ..............

11-5

 

 

11.1.13

SerIRQC–Serial IRQ Control Register (Function 0) ............................

11-6

 

 

11.1.14

TOM–Top of Memory Register (Function 0)........................................

11-6

 

 

11.1.15

MSTAT–Miscellaneous Status Register (Function 0)..........................

11-7

Intel® 460GX Chipset System Software Developer’s Manual

vii

 

11.1.16 Deterministic Latency Control Register (Function 0)...........................

11-7

 

11.1.17 MGPIOC–Muxed GPIO Control (Function 0) ......................................

11-8

 

11.1.18 PDMACFG–PCI DMA Configuration Resister (Function O)................

11-8

 

11.1.19 DDMABP–Distributed DMA Slave Base Pointer

 

 

 

Registers (Function 0).........................................................................

11-8

 

11.1.20 RTCCFG–Real Time Clock Configuration Register (Function 0) ........

11-9

 

11.1.21 GPIO Base Address (Function 0)......................................................

11-10

 

11.1.22 GPIO Enable (Function 0).................................................................

11-10

 

11.1.23 LPC COM Decode Ranges (Function 0)...........................................

11-10

 

11.1.24 LPC FDD/LPT Decode Ranges (Function 0) ....................................

11-11

 

11.1.25 LPC Sound Decode Ranges (Function 0).........................................

11-12

 

11.1.26 LPC Generic Decode Range (Function 0).........................................

11-12

 

11.1.27 LPC Enables (Function 0) .................................................................

11-13

 

11.2 PCI to LPC I/O Space Registers ....................................................................

11-15

 

11.2.1

DMA Registers ..................................................................................

11-15

 

11.2.2

Interrupt Controller Registers ............................................................

11-20

 

11.2.3

Counter/Timer Registers ...................................................................

11-25

 

11.2.4

NMI Registers ...................................................................................

11-28

 

11.2.5

Real Time Clock Registers................................................................

11-29

 

11.2.6

Advanced Power Management (APM) Registers..............................

11-30

 

11.2.7

ACPI Registers..................................................................................

11-31

 

11.2.8

SMI Registers....................................................................................

11-35

 

11.2.9

General Purpose I/O Registers .........................................................

11-37

12

IDE Configuration..........................................................................................................

12-1

 

12.1 PCI Configuration Registers (Function 1) ........................................................

12-1

 

12.2 IDE Controller Register Descriptions (PCI Function 1) ....................................

12-1

 

12.2.1

VID–Vendor Identification Register (Function 1).................................

12-2

 

12.2.2

DID–Device Identification Register (Function 1) .................................

12-2

 

12.2.3

PCICMD–PCI Command Register (Function 1) ..................................

12-2

 

12.2.4

PCISTS–PCI Device Status Register (Function 1)..............................

12-3

 

12.2.5

CLASSC–Class Code Register (Function 1).......................................

12-3

 

12.2.6

MLT–Master Latency Timer Register (Function 1)..............................

12-4

 

12.2.7

BMIBA–Bus Master Interface Base Address Register

 

 

 

(Function 1) .........................................................................................

12-4

 

12.2.8

SVID–Subsystem Vendor ID (Function 1)...........................................

12-5

 

12.2.9

SID–Subsystem ID (Function 1)..........................................................

12-5

 

12.2.10

IDETIM–IDE Timing Register (Function 1)..........................................

12-5

 

12.2.11

SIDETIM–Slave IDE Timing Register (Function 1) .............................

12-6

 

12.2.12

DMACTL–Synchronous DMA Control Register (Function 1) ..............

12-7

 

12.2.13 SDMATIM–Synchronous DMA Timing Register (Function 1) .............

12-8

 

12.3 IDE Controller I/O Space Registers .................................................................

12-9

 

12.3.1

BMICx–Bus Master IDE Command Register (I/O) ..............................

12-9

 

12.3.2

BMISx–Bus Master IDE Status Register (I/O)...................................

12-10

 

12.3.3

BMIDTPx–Bus Master IDE Descriptor Table Pointer Register (I/O) .12-11

13

Universal Serial Bus (USB) Configuration.....................................................................

13-1

 

13.1 PCI Configuration Registers (Function 2) ........................................................

13-1

 

13.2 USB Host Controller Register Descriptions (PCI Function 2) ..........................

13-2

 

13.2.1

VID–Vendor Identification Register (Function 2).................................

13-2

 

13.2.2

DID–Device Identification Register (Function 2) .................................

13-2

 

13.2.3

PCICMD–PCI Command Register (Function 2) ..................................

13-2

viii

Intel® 460GX Chipset System Software Developer’s Manual

 

13.2.4

PCISTS–PCI Device Status Register (Function 2)..............................

13-3

 

13.2.5

RID–Revision Identification Register (Function 2)...............................

13-3

 

13.2.6

CLASSC–Class Code Register (Function 2).......................................

13-4

 

13.2.7

MLT–Master Latency Timer Register (Function 2)..............................

13-4

 

13.2.8

HEDT–Header Type Register (Function 2) .........................................

13-4

 

13.2.9

USBBA–USB I/O Space Base Address (Function 2) ..........................

13-5

 

13.2.10

SVID–Subsystem Vendor ID (Function 2)...........................................

13-5

 

13.2.11

SID–Subsystem ID (Function 2)..........................................................

13-5

 

13.2.12

INTLN–Interrupt Line Register (Function 2) ........................................

13-5

 

13.2.13

INTPN–Interrupt Pin (Function 2)........................................................

13-6

 

13.2.14 Miscellaneous Control (Function 2).....................................................

13-6

 

13.2.15 SBRNUM–Serial Bus Release Number (Function 2) ..........................

13-6

 

13.2.16 LEGSUP–Legacy Support Register (Function 2) ................................

13-6

 

13.2.17 USBREN–USB Resume Enable .........................................................

13-8

 

13.3 USB Host Controller I/O Space Registers........................................................

13-8

 

13.3.1

USBCMD–USB Command Register (I/O) ...........................................

13-8

 

13.3.2

USBSTS–USB Status Register (I/O).................................................

13-10

 

13.3.3

USBINTR–USB Interrupt Enable Register (I/O) ................................

13-10

 

13.3.4

FRNUM–Frame Number Register (I/O).............................................

13-11

 

13.3.5

FLBASEADD–Frame List Base Address Register (I/O) ....................

13-11

 

13.3.6

SOFMOD–Start of Frame (SOF) Modify Register (I/O).....................

13-11

 

13.3.7

PORTSC–Port Status and Control Register (I/O) .............................

13-12

14

SM Bus Controller Configuration...................................................................................

14-1

 

14.1 SM Bus Configuration Registers (Function 3) ..................................................

14-1

 

14.2 System Management Register Descriptions ....................................................

14-2

 

14.2.1

VID–Vendor Identification Register (Function 3) .................................

14-2

 

14.2.2

DID–Device Identification Register (Function 3) .................................

14-2

 

14.2.3

PCICMD–PCI Command Register (Function 3) ..................................

14-2

 

14.2.4

PCISTS–PCI Device Status Register (Function 3)..............................

14-3

 

14.2.5

RID–Revision Identification Register (Function 3)...............................

14-3

 

14.2.6

CLASSC–Class Code Register (Function 3).......................................

14-4

 

14.2.7

SMBBA–SMBus Base Address (Function 3).......................................

14-4

 

14.2.8

SVID–Subsystem Vendor ID (Function 3)...........................................

14-4

 

14.2.9

SID–Subsystem ID (Function 3)..........................................................

14-5

 

14.2.10

INTLN–Interrupt Line Register (Function 3) ........................................

14-5

 

14.2.11

INTPN–Interrupt Pin (Function 3)........................................................

14-5

 

14.2.12 Host Configuration...............................................................................

14-5

 

14.2.13 smbslvc–SMBus Slave Command (Function 3) ..................................

14-6

 

14.2.14 smbshdw1–SMBus Slave Shadow Port 1 (Function 3).......................

14-6

 

14.2.15 smbshdw2–SMBus Slave Shadow Port 2 (Function 3).......................

14-6

 

14.3 SMBus I/O Space Registers.............................................................................

14-6

 

14.3.1

smbhststs–SMBus Host Status Register (I/O) ....................................

14-7

 

14.3.2

smbslvsts–SMBus Slave Status Register (I/O) ...................................

14-7

 

14.3.3

smbhstcnt–SMBus Host Control Register (I/O)...................................

14-8

 

14.3.4

smbhstcmd–SMBus Host Command Register (I/O)............................

14-9

 

14.3.5

smbhstadd–SMBus Host Address Register (I/O) ................................

14-9

 

14.3.6

smbhstdat0–SMBus Host Data 0 Register (I/O)..................................

14-9

 

14.3.7

smbhstdat1–SMBus Host Data 1 Register (I/O)................................

14-10

 

14.3.8

smbblkdat–SMBus Block Data Register (I/O) ...................................

14-10

 

14.3.9

smbslvcnt–SMBus Slave Control Register (I/O)................................

14-10

 

14.3.10 smbslvdat–SMBus Slave Data Register (I/O) ...................................

14-11

Intel® 460GX Chipset System Software Developer’s Manual

ix

15

PCI/LPC Bridge Description..........................................................................................

15-1

 

15.1

PCI Interface ....................................................................................................

15-1

 

 

15.1.1

Transaction Termination .....................................................................

15-1

 

 

15.1.2

Parity Support .....................................................................................

15-1

 

 

15.1.3

PCI Arbitration.....................................................................................

15-1

 

15.2

Interrupt Controller ...........................................................................................

15-1

 

 

15.2.1 Programming the Interrupt Controller..................................................

15-2

 

 

15.2.2 End of Interrupt Operation...................................................................

15-3

 

 

15.2.3

Modes of Operation.............................................................................

15-4

 

 

15.2.4

Cascade Mode ....................................................................................

15-5

 

 

15.2.5 Edge and Level Triggered Mode.........................................................

15-6

 

 

15.2.6

Interrupt Masks ...................................................................................

15-6

 

 

15.2.7 Reading the Interrupt Controller Status...............................................

15-7

 

 

15.2.8

Interrupt Steering ................................................................................

15-7

 

15.3

Serial Interrupts................................................................................................

15-8

 

 

15.3.1

Protocol ...............................................................................................

15-8

 

15.4

Timer/Counters ..............................................................................................

15-10

 

 

15.4.1 Programming the Interval Timer........................................................

15-10

 

15.5

Real Time Clock.............................................................................................

15-13

 

 

15.5.1 RTC Registers and RAM...................................................................

15-14

 

 

15.5.2

RTC Update Cycle ............................................................................

15-17

 

 

15.5.3

RTC Interrupts...................................................................................

15-17

 

 

15.5.4

Lockable RAM Ranges .....................................................................

15-17

16

IFB Power Management ...............................................................................................

16-1

 

16.1

Overview ..........................................................................................................

16-1

 

16.2

IFB Power Planes ............................................................................................

16-2

 

 

16.2.1

Power Plane Descriptions ...................................................................

16-2

 

 

16.2.2

SMI# Generation .................................................................................

16-2

 

 

16.2.3

SCI Generation ...................................................................................

16-3

 

 

16.2.4

Sleep States........................................................................................

16-3

 

 

16.2.5 ACPI Bits Not Implemented by IFB .....................................................

16-4

 

 

16.2.6 Entry/Exit for the S4 and S5 States.....................................................

16-4

 

16.3

Handling of Power Failures in IFB....................................................................

16-5

Figures

 

 

 

 

 

1-1

Diagram of a Typical Intel® 460GX Chipset-based System with AGP ..............

1-1

 

4-1

System Memory Address Space........................................................................

4-2

 

4-2

Itanium™ Processor and Chipset-specific Memory Space ................................

4-5

 

4-3

System I/O Address Space ................................................................................

4-6

 

4-4

System Memory Address Space as Viewed from an Expander

 

 

 

Bridge (PXB/GXB)..............................................................................................

4-7

 

5-1

Maximum Memory Configuration Using Two Cards...........................................

5-2

 

5-2

Address Interleaving ..........................................................................................

5-4

 

6-1

SAC Error Flow on Data...................................................................................

6-14

 

6-2

SDC Error Data Flow .......................................................................................

6-15

 

6-3

GXB Error Flow ................................................................................................

6-25

 

7-1

GART Table Usage for 4k Pages.......................................................................

7-2

 

7-2

GART Table Usage for 4 MB Pages ..................................................................

7-2

 

7-3

GART Entry Format for 4kB Pages....................................................................

7-3

x

Intel® 460GX Chipset System Software Developer’s Manual

7-4

GART Entry Format for 4 MB Pages..................................................................

7-3

7-5

GART SRAM Timings ........................................................................................

7-5

Tables

1-1

Intel® 460GX Chipset Components ...................................................................

1-2

2-1

Device Mapping on Bus CBN.............................................................................

2-2

2-2

Memory-Mapped Register Summary ...............................................................

2-45

2-3

I/O Select Register Format...............................................................................

2-45

2-4

I/O Window Register Format ............................................................................

2-46

2-5

(x)APIC EOI Register Format...........................................................................

2-46

2-6

Memory-mapped Register Summary ...............................................................

2-47

2-7

I/O APIC ID Register Format............................................................................

2-49

2-8

I/O (x)APIC Version Register Format ...............................................................

2-49

2-9

I/O (x)APIC Arbitration ID Register Format ......................................................

2-50

2-10

I/O (x)APIC RTE Format ..................................................................................

2-50

4-1

Address Disposition............................................................................................

4-8

5-1

General Memory Characteristics........................................................................

5-1

5-2

Minimum/Maximum Memory Size per Configuration..........................................

5-3

5-3

Required DRAM Parameters..............................................................................

5-6

5-4

Scrubbing Time ..................................................................................................

5-7

6-1

Error Cases ......................................................................................................

6-16

6-2

List of WXB Error Sources Selectively Routable to XBINIT#, SERR_OUT#,

 

 

and P(A/B)INTRQ#...........................................................................................

6-27

6-3

Supported Error Escalation to XBINIT#............................................................

6-27

6-4

Supported Error Escalation to SERR_OUT#....................................................

6-28

6-5

Supported Error Escalation to P(A/B)INTRQ# .................................................

6-28

7-1

Coherency for AGP/PCI Streams.......................................................................

7-8

7-2

Delayed Read Matching Criteria ......................................................................

7-11

7-3

Burst Write Combining Modes..........................................................................

7-13

7-4

Burst Write Combining Examples with 3 Writes in 1X Transfer Mode .............

7-13

7-5

Bandwidth Estimates for Various Request Sizes .............................................

7-14

8-1

IHPC Configuration Register Space...................................................................

8-2

8-2

IHPC Memor Mapped Register Space .............................................................

8-11

9-1

PCI Configuration Registers–Function 0(PCI to LPC/FWH Interface Bridge) ....

9-1

9-2

PCI Configuration Registers–Function 1 (IDE Interface)....................................

9-3

9-3

PCI Configuration Registers–Function 2 (USB Interface) ..................................

9-4

9-4

PCI Configuration Registers–Function 3 (SMBus Controller Interface) .............

9-5

10-1

Identify Device Information Used for Determining Drive Capabilities...............

10-3

10-2

Identify Device Information Used for Determining Ultra DMA

 

 

Drive Capabilities .............................................................................................

10-5

10-3

Identify Device Information Used for Determining Multi/Single Word DMA

 

 

Drive Capabilities .............................................................................................

10-6

10-4

Drive Multi Word DMA/Single Word DMA Capability as a Function

 

 

of Cycle Time ...................................................................................................

10-7

10-5

Identify Device Information Used for Determining PIO Drive Capabilities........

10-8

10-6

Drive PIO Capability as a Function of Cycle Time ...........................................

10-8

10-7

IFB Drive Mode Based on DMA/PIO Capabilities ............................................

10-9

10-8

IDE Mode/Drive Feature Settings for Optimal DMA/PIO Operation ...............

10-10

10-9

DMA/PIO Timing Values Based on PIIX Cable Mode/System Speed............

10-11

Intel® 460GX Chipset System Software Developer’s Manual

xi

10-10

Ultra DMA Timing Value Based on Drive Mode .............................................

10-11

10-11

Ultra DMA/Multi Word DMA/Single Word Transfer/Mode Values ..................

10-12

10-12

PIO Transfer/Mode Values.............................................................................

10-12

10-13

Drive Capabilities Checklist............................................................................

10-13

10-14

IFB Settings Checklist ....................................................................................

10-14

12-1

PCI Configuration Registers–Function 1 (IDE Interface) .................................

12-1

12-2

Ultra DMA/33 Timing Mode Settings................................................................

12-9

12-3

DMA/PIO Timing Values Based on IFB Cable Mode and System Speed........

12-9

12-4

Interrupt/Activity Status Combinations ...........................................................

12-11

13-1

PCI Configuration Registers–Function 2..........................................................

13-1

13-2

Run/Stop, Debug Bit Interaction.......................................................................

13-9

15-1

SERIRQ Frames ..............................................................................................

15-9

15-2

RTC (Standard) RAM Bank............................................................................

15-14

16-1

IFB Power States and Consumption ................................................................

16-1

16-2

Causes of SMI#................................................................................................

16-2

16-3

Causes of SCI# ................................................................................................

16-3

16-4

ACPI Bits Not Implemented in IFB ...................................................................

16-4

xii

Intel® 460GX Chipset System Software Developer’s Manual

Introduction

1

This document provides information about the Intel® 460GX chipset components. The 460GX chipset is a high performance memory and I/O chipset for the Intel Itanium™ processor, targeted for multiprocessor server and high-end workstation designs.

This document describes the software programmer's interface to the 460GX chipset. It provides a brief summary of the system architecture supported by the 460GX chipset, a list of features within the chipset and a detailed description of software or other externally visible segments.

1.1System Overview

The Intel 460GX chipset is a high performance chipset for Intel Itanium processor-based systems, targeted for multiprocessor servers and high-performance workstations. It provides the memory controller interface and appropriate bridges to PCI, AGP 4X, and other standard I/O buses. Figure 1-1 illustrates the basic system configuration of a four-processor platform.

Figure 1-1. Diagram of a Typical Intel® 460GX Chipset-based System with AGP

 

Cache

 

Cache

 

 

 

Cache

 

 

 

Cache

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Processor

 

Processor

 

 

Processor

 

 

 

Processor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Itanium™ Processor System Bus

SAC

 

 

 

 

 

 

 

Private Bus

 

 

 

 

 

 

 

 

SDC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Address

 

MAC

 

 

 

MDC

 

 

 

 

 

 

 

 

 

System Data

Controller

 

 

 

 

 

 

 

 

 

 

MDC

 

 

 

 

 

 

 

 

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MDC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAC

 

 

 

 

MDC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAC

 

 

 

MDC

 

 

MDC

 

 

 

 

 

 

 

 

 

 

 

Memory Subsystem

 

 

 

 

 

 

 

 

 

 

 

 

 

MDC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAC

 

 

 

 

 

MDC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Expander

 

 

 

 

 

 

 

 

 

 

Buses

 

 

 

 

 

GXB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Graphics

 

 

 

 

PXB

 

Expansion

 

 

 

 

 

Bridge

 

 

 

 

PCI

 

 

 

 

 

 

 

 

Expansion

 

 

 

 

 

 

 

 

 

Bridge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AGP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4X Mode

 

 

 

 

 

 

GART

 

 

 

 

 

 

Slot

 

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WXB

 

 

 

 

 

Wide PCI

 

 

 

 

 

Expansion

 

 

 

 

 

 

Bridge

Memory Subsystem

Memory Data and Control Bus

 

 

 

PID

 

 

USB

 

 

 

 

 

 

 

 

Programmable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Compatibility

 

 

 

 

 

 

 

 

IFB

 

 

 

 

 

IDE HDD

 

 

 

PCI Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O and Firmware

 

 

 

 

IDE CD-ROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bridge

 

 

 

 

 

 

 

 

 

 

 

 

 

Firmware

 

 

 

 

 

 

LPC Interface

 

 

 

 

 

Hub Interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 PCI Buses

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FWH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3V/5.0V,

 

 

 

 

 

 

 

 

 

Super

 

 

 

 

 

 

 

 

32-bit, 33 MHz

 

 

 

Firmware

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

Hub

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 PCI Buses

3.3V, 64-bit, 66 MHz

000346e

Intel® 460GX Chipset Software Developer’s Manual

1-1

Introduction

1.1.1Component Overview

Table 1-1 lists the 460GX chipset components.

Table 1-1. Intel® 460GX Chipset Components

Component

Name

Function

 

 

 

SAC

82461GX

Interfaces the address and control portion of the Itanium™ processor

 

System Address

system bus and the memory bus. Acts as a host bridge interface to

 

peripheral I/O devices through four Expander busses.

 

Controller

 

 

 

 

 

SDC

82462GX

Interfaces the data portion of the Itanium processor system bus and

 

System Data path

the memory bus.

 

 

 

Controller

 

 

 

 

MAC

82463GX

Provides the SDRAM RAS/CAS/WE/CS generation as well as

 

Memory Address

redriving the address to the SDRAMs. It is capable of buffering several

 

commands from the SAC.

 

Controller

 

 

 

 

 

MDC

82464GX

Multiplexes the data from the SDRAM to the SDC. On reads, it latches

 

Memory Data path

data from the SDRAM, then transfers the data to the SDC. On writes, it

 

latches the data from the SDC, then writes the data to the SDRAM.

 

Controller

 

 

 

 

 

GXB

82465GX

Provides the control and data interface for an AGP 4X graphics port.

 

Graphics Expander

This device attaches to the SAC via two Expander busses which utilize

 

a special configuration.

 

Bridge

 

 

 

 

 

WXB

82466GX

Provides the primary control and data interface for two independent

 

Wide and fast PCI

64-bit, 66 MHz PCI interfaces. This device attaches to the SAC via an

 

Expander bus.

 

Expander Bridge

 

 

 

 

 

PXB

82467GX

Provides the primary control and data interface for two independent

 

PCI Expander Bridge

32-bit, 33-MHz PCI interfaces. These two 32-bit interfaces may

 

operate together to produce a single 64-bit, 33-MHz interface via a

 

 

 

 

configuration option. This device attaches to the SAC via an Expander

 

 

bus.

 

 

 

IFB

82468GX

The IFB is a multi-function PCI device implementing a PCI-to-LPC

 

I/O and Firmware

bridge function, a PCI IDE function, a Universal Serial Bus Host/Hub

 

function, an SMBus Interface function, Power Management function

 

Bridge

 

and the Firmware Hub interface.

 

 

 

 

 

FWH

82802AC

The FWH component interfaces to the IFB component and provides

 

Firmware Hub 8Mb

firmware storage and security features. Further FWH information can

 

be found at http://developer.intel.com/design/chipsets/datasheets or by

 

 

 

 

ordering document 290658.

 

 

 

PID

NEC# UPD66566S1-

The PID is an interrupt controller that provides interrupt steering

 

016

functions. The PID contains the logic required to support 8259A mode,

 

Programmable

APIC mode, and SAPIC mode interrupt controller operations. The PID

 

interfaces include a PCI bus interface, an APIC bus interface, a serial

 

Interrupt Device

 

IRQ interface, and an interrupt input interface.

 

 

 

 

 

1-2

Intel® 460GX Chipset Software Developer’s Manual

Introduction

1.2Product Features

High performance hardware based on IA-64 architecture

4.2 GB/s memory bandwidth can simultaneously support both the full system bus and the full I/O bus bandwidths

Architectural support for 64 MB to 64 GB of SDRAM

Support for up to four bridge chips that interface to the 82461GX (SAC) through four Expander channels, each 30 bits wide and providing 533 MB/s peak bandwidth

AGP 4X compatible, via the 82465GX (GXB) and two Expander channels running at 266 MHz totaling 1 GB/s peak bandwidth

Support for two 64-bit, 66-MHz PCI buses using one 82466GX (WXB) component per Expander channel

Support for two independent 32-bit, 33-MHz PCI buses or one 64-bit, 33-MHz PCI bus via the 82467GX (PXB) per Expander channel

Data streaming support between Expanders and DRAM, up to 533 MB/s per Expander channel

Extensive RAS features for mission-critical needs

ECC protection on the system bus data signals

Memory ECC with single-bit error correction, double and nibble error detection

Address and data flows protected by parity throughout chipset

ECC bits in DRAM accessible by diagnostics

Fault recording of multiple errors; sticky through reset

JTAG TAP port for debug and boundary scan capability

I2C slave interface for viewing and modifying specific error and configuration registers

High bandwidth system bus for multiprocessor scalability

— Support of the Intel® Itanium™ processor 64-bit data bus

Full support for 4-way multiprocessing

266 MHz data bus frequency

Cache line size of 64 bytes

Enhanced defer feature for out-of-order data delivery using IDS#

AGTL+ bus driver technology

Features to support flexible platform environments

Hardware compatible with IA-32 binaries

AGP address space up to 32 GB supported

Support for Auto Detection of SDRAM memory type and mixed memory sizes allowed between rows

Supports 16-, 64-, 128and 256-Mbit DRAM devices

Full support for the PCI Configuration Space Enable (CSE) protocol to devices on all Expander channels

WXB supports 3.3 volt PCI bus operation (supports universal and 3.3 volt PCI cards) and has an Integrated Hot-Plug Controller**

PCI Rev. 2.2 compliant on the WXB and PXB

GXB supports fast writes and 1x, 2x and 4x data rates

1 MB or greater of firmware storage provided by the 82802AC (FWH)

Interrupt controller, bus-mastering IDE and Universal Serial Bus supported by the 82468GX (IFB)

Support of 8259A mode, APIC mode and SAPIC mode interrupts via the UPD55566S1-016 (PID) provided by NEC*

Bus, memory and I/O performance counters

Support of ACPI/DMI functions (support is **Based on technology licensed from Compaq Computer Corp.

provided in the IFB)

1.3 Itanium™ Processor System Bus Support

Full support for the Itanium processor system bus.

64-bit data bus.

266 MHz data bus frequency.

Cache line size of 64 bytes.

Supports SAPIC interrupt protocol.

Full support for 4-way multiprocessing.

Parity protection on address and control signals, ECC protection on the data signals.

GTL+ bus driver technology.

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1.4DRAM Interface Support

SDRAM 3.3 volt, 168-pin DIMM’s are the only memory type supported.

Support for 64 MB to 64 GB of DRAM.

Minimum memory size is 64 MB using 16 MB DIMM’s.

Minimum incremental size is 64 MB using 16 MB DIMM’s.

Maximum memory size is 16 GB using 128 MB DIMM’s.

Maximum memory size is 64 GB using 1 GB DIMM’s.

Only 3.3 volt memory is supported.

Support for Auto Detection of SDRAM Memory Type.

Supports 16, 64, 128 and 256 Mbit DRAM devices.

Mixed memory sizes allowed between rows.

Staggered CAS-before-RAS refresh (standard SDRAM refresh).

ECC with single-bit error correction, double and nibble error detection.

Extensive processor-to-Memory and PCI-to-Memory write data buffering, thus minimizing the interference of writes on read latency.

1.5I/O Support

4 Expander ports, each 30 bits wide and providing 533 MB/s peak bandwidth.

Each Expander bus supports a single PXB or WXB. Two Expander busses can be configured to support a GXB.

Full support for the PCI Configuration Space Enable (CSE) protocol to devices on all Expander ports.

Data streaming support between Expanders and DRAM, up to 533 MB/s per Expander port.

All outbound memory and I/O reads (except locked reads) are deferred.

All outbound memory space writes are posted. Outbound I/O space writes are optionally posted (unless targeting an address with side effects, in which case they are deferred).

All inbound memory reads are delayed.

All inbound memory space writes are posted.

Supports concurrent processor and I/O initiated transactions to main memory.

Maintains coherency with processors by snooping all inbound transactions to the system bus.

Supports non-coherent traffic (for AGP), with a direct path to memory bypassing the system bus.

1.5.1PXB Features

Can be configured to provide two independent 32 bit, 33 MHz PCI buses or one 64 bit, 33 MHz PCI bus.

PCI Rev. 2.2, 5V tolerant (PXB drives 3.3 volts, but is 5.0 volt tolerant).

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Parity protection on all PCI signals.

Data collection & write assembly.

Combines back-to-back sequential processor-to-PCI memory writes to PCI burst writes.

Processor to PCI write assembly of full/partial line writes.

Two outbound read requests containing a total of two cache lines of read data for each PCI bus.

Supports six outbound write requests containing a total of three cache lines of write data for each 32 bit PCI bus. Supports 12 outbound write requests containing a total of six cache lines of write data for a 64 bit PCI bus.

Supports two delayed inbound read requests.

Supports the I/O and Firmware Bridge (IFB).

Supports either internal or external arbitration, allowing additional bus masters, on the PCI bus.

1.5.2WXB Features

Support for two 64 bit, 66 MHz PCI busses.

3.3 Volt PCI bus operation (supports Universal and 3.3 Volt PCI cards).

PCI Specification, Revision 2.2.

Integrated Hot-Plug controller.

1.5.3GXB Features

The GXB is AGP and AGP 4X mode compatible, nominal 66 MHz, 266 MHz, 1 GB/s peak bandwidth.

The GXB supports pipelined operation or sideband signals on AGP 4X mode bus.

AGP address space of 1 GB or 256 MB supported. Also supports 32 GB of GART window, if 4 MB pages are used.

Supports Fast Writes and 1x, 2x and 4x data rates.

1.6RAS Features

ECC coverage of system data bus using the Itanium™ processor SEC/DED ECC code. Memory is protected using a SEC/DED code which also provides nibble detection capabilities of 4 bits. All control and address signals are parity protected. Local control buses are parity protected. The Expander is covered by parity.

Data flows protected by parity throughout chipset.

ECC bits in DRAM accessible by diagnostics.

Fault recording of multiple errors; sticky through reset, but NOT through power-down.

Memory scrubbing implemented in hardware.

Boundary test capability through JTAG.

JTAG TAP port for debug.

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I2C Slave Interface will allow viewing and modifying of specific error and configuration registers.

1.7Other Platform Components

These 460GX devices provide access to flash space, interrupt collection and legacy features.

1.7.1I/O & Firmware Bridge (IFB)

The 460GX chipset is designed to work with the IFB south bridge. As part of this support, the PXB includes an internal PCI arbiter as well as support for an external PCI arbiter. The IFB consists of an 8259C Interrupt controller, a bus-mastering IDE interface, and a Universal Serial Bus interface. Devices using IFB are limited to a 32 bit addressing space available for DMA, not the full 44 bits supported by the Itanium™ processor.

1.7.2Programmable Interrupt Device (PID)

The PID is a PCI device that gathers interrupts and delivers them from the PCI bus to the system bus using the SAPIC interrupt protocol. The interrupt will be presented to one of the processors on the bus for servicing. A 460GX chipset based platform requires at least one PID located on the compatibility PCI bus. The compatibility PID will handshake with the IFB before delivering a south bridge/compatibility device interrupt. The same PID may also be used to deliver some portion of the PCI based interrupts.

The system implementor can choose how many PIDs are used in the platform. If enough interrupt lines are shared, there need be only one PID in the system; all interrupts in the system would then be routed to that PID. Each PID has enough interrupt inputs to handle dedicated interrupts from the cards on two PCI buses. Therefore, using one PID per PXB provides a high performance solution with minimum routing between PCI buses.

1.8Reference Documents

In addition to this document, the reader should be familiar with the following reference documents:

Intel® 460GX Chipset Datasheet

(Document Number: 248703)

Intel® Itanium™ Processor Hardware Developer’s Manual

(Document Number: 248701)

Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet

(Document Number: 245481)

Intel® 82460GX Chipset OLGA1 Package, Manufacturing, Mechanical, and Thermal Design Guide

PCI Local Bus Specification, Rev 2.2 (http://www.pcisig.com/)

Accelerated Graphics Port Interface Specification

(http://www.intel.com/technology/agp/agp_index.htm)

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JTAG IEEE 1149.1 Specification

(http://www.ieee.com)

Universal Serial Bus Specification

(http://www.usb.org)

System Management Bus Specification, Rev. 1.0

Low Pin Count (LPC) Interface Specification, Rev 1.0

Note: Contact your Intel representative for the latest revision of the documents without document numbers.

1.9Revision History

Date

Description

 

 

June 2001

Initial release.

 

 

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2

The 460GX chipset has both memory mapped and PCI configuration space mapped registers. The 460GX chipset supports access mechanism #1 as defined in the PCI specification. Two 32-bit register locations (CONFIG_ADDRESS and CONFIG_DATA) are defined in the Itanium processor’s I/O space; I/O accesses to these registers are translated by the 460GX chipset into appropriate PCI configuration cycles.

To access a configuration register in the 460GX chipset (or any other I/O device), software first writes a value to the CONFIG_ADDRESS location consisting of the bus number, Device Number, function number and register number. These writes are claimed and saved by the 460GX chipset. Subsequent reads or writes to the CONFIG_DATA location result in the 460GX chipset using the information stored in CONFIG_ADDRESS to deliver a PCI configuration read or write cycle to the appropriate address on the appropriate PCI bus.

Upon reset, the 460GX chipset sets its internal configuration registers to predetermined default states, representing the minimum feature set required to successfully bring up the system. It is expected that the firmware will properly determine and program the optimal configuration settings. The 460GX chipset implements a PCI-compatible configuration space for each PCI bus under the PXBs, for each AGP bus under the GXB, and for each 460GX chipset component. Each configuration space provides hardwired device identification, address range registers, operation control registers, status and error registers. This chapter describes how the configuration spaces are accessed, then provides detailed descriptions of each register.

2.1Access Mechanism

The PCI specification defines two bus cycles to access PCI configuration space: Configuration Read and Configuration Write. While memory and I/O spaces are supported by the microprocessor, configuration space is not directly supported. The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The 460GX chipset supports only Mechanism #1.

Mechanism #1 defines two I/O-space locations: an address register (CONFIG_ADDRESS) at location 0CF8h, and a data register (CONFIG_DATA) at location 0CFCh. Dword I/O Writes to the configuration address are latched and held; they specify the PCI Bus Number, Device Number within the bus, and Register Number within the device. Subsequent I/O reads and writes to the configuration data location cause a configuration space access the register specified by the address stored in the configuration address location.

Note: The AGP bus under the GXB looks like a standard PCI bus for configuration purposes. The term xXB refers to the PXB, WXB, or GXB. In general, any reference to an access to PCI bus includes accesses to an AGP bus.

Configuration space accesses are processed as follows:

If the SAC detects that the I/O request is a configuration access to its own configuration space, it will service that request entirely within the SAC or the other chipset components. Reads result in data being returned to the system bus.

If the SAC detects that the I/O request is a configuration access to a xXB configuration space, it will forward the request to the appropriate xXB for servicing. The request is not forwarded

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to a PCI bus. Reads result in data being returned by the xXB through the SAC to the system bus.

Otherwise, the access is forwarded to the xXB to be placed on the PCI bus (or AGP bus) as a Configuration Read or Configuration Write cycle. Reads will result in data being returned through the xXB and SAC back to the system bus, just as in normal Outbound Read operations.

2.2Access Restrictions

The 460GX chipset supports PCI configuration space access using the mechanism denoted as Configuration Mechanism #1 in the PCI specification.

The 460GX chipset internal registers (both I/O Mapped and Configuration registers) are accessible by the Host CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS which can only be accessed as a Dword. All multi-byte numeric fields use “little-endian” ordering (i.e. lower addresses contain the least significant parts of the field).

2.2.1Partitioning

Each SAC, SDC, MAC, PXB, WXB, GXB, each AGP bus below an GXB, and each PCI bus below an PXB or WXB, has an independent configuration space. None of the registers are shared between the spaces; that is, the SAC, and each PCI bus in the PXB, have separate control and status registers.

Configuration registers are accessed using an “address” comprised of the PCI Bus Number, the Device Number within the bus, and the Register Number within the Device.

Accesses to devices on Bus #0 and Bus #(CBN) are serviced by the 460GX chipset depending on their device number. Device 10h on Bus #0 is mapped to the SAC; it contains the programmable Chipset Bus Number. All other chipset devices reside on bus CBN.

The DEVNPRES register is used to determine which chipset devices are present; see Table 2-1 for mapping information.

Table 2-1. Device Mapping on Bus CBN

No.

Device

 

No.

Device

 

 

 

 

 

00h

SAC

 

10h

Expander 0, Bus aa

01h

SAC

 

11h

Expander 0, Bus b

 

 

 

 

 

02h

reserved

 

12h

Expander 1, Bus a

 

 

 

 

 

03h

reserved

 

13h

Expander 1, Bus b

 

 

 

 

 

04h

SDC

 

14h

Expander 2, Bus a

 

 

 

 

 

05h

Memory Card A

 

15h

Expander 2, Bus b

 

 

 

 

 

06h

Memory Card B

 

16h

Expander 3, Bus a

 

 

 

 

 

07h

reserved

 

17h

Expander 3, Bus b

 

 

 

 

 

08h-0Fh

reserved

 

18h-1Fh

reserved

 

 

 

 

 

a. This is the compatibility bus (where the boot vector is always directed).

Configuration registers located in the SDC are accessed over the private data bus. The SAC translates CF8/CFC accesses to SDC registers into configuration commands over the PDB. Configuration registers located on the memory boards are accessed over the I2C port. The SAC

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translates CF8/CFC accesses to the MAC registers into read/write commands over the I2C port. The SAC also contains an IIADR pointer register that can be used in conjunction with a CF8/CFC access to generate I2C commands to generic I2C devices on the memory boards.

2.2.2Register Attributes

Registers have designated “access attributes”, with the following definitions:

Read Only

Writes to this register have no effect.

Read/Write

Data may be read from and written to this register. Selected bits in the register may

 

be designated as “hardwired” or “read-only”; such bits are not affected by data writes

 

to the register.

Read/Clear

Data may be read from the register. A data write operates strictly as a clear: a “1”-bit

 

in the data field clears the corresponding bit in the register, while a “0”-bit in the data

 

field has no effect on the corresponding bit in the register. Selected bits in the register

 

may be designated as “hardwired” or “read-only”; such bits are not affected by data

 

writes to the register.

Sticky

Data in this register remains valid and unchanged, during and following a hard reset.

 

Typically, these registers contain special configuration information or error logs.

2.2.3Reserved Bits Defined in Registers

Most 460GX chipset registers described in this section contain reserved bits. The PCI specification requires that software correctly handle reserved fields, as follows. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, write operation for the CONFIG_ADDRESS register.

2.2.4Reserved or Undefined Register Locations

In addition to reserved bits within a register, the 460GX chipset contains address locations in the PCI configuration space that are marked “Reserved” or are simply undefined. Several of the 460GX chipset devices are multi-function devices; all registers in the unused functions are considered “Reserved”. Reserved registers can be 8-, 16-, or 32-bit in size. The PCI specification requires that the 460GX chipset respond to accesses to these address locations by completing the host cycle. Reserved register locations must be treated by software the same as reserved fields are treated: software can not rely on reads returning any particular value, and must not attempt to change the value returned when read.

2.2.5Default Upon Reset

Upon reset, the 460GX chipset sets its internal configuration registers to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (firmware) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the 460GX chipset registers accordingly.

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2.2.6Consistency

There are a number of registers that are repeated in both the SAC and xXB/PCI spaces. It is software’s responsibility to insure that these registers are programmed in a consistent fashion. Failure to insure consistency can produce indeterminate results. See the Initialization Chapter for an overview on initializing all chipset components.

When the address decode ranges of 460GX chipset devices are being updated, no other bus traffic is allowed over the address ranges being affected by the update. This means that the code that updates initial configuration must be executing from a location that will not be affected by the update. Furthermore in a multiprocessor system, precautions should be taken to assure that only one CPU is accessing configuration space at a time.

2.2.7GART Programming Region

The region starting at FE20_0000h is used for programming the GARTs. This region is accessible either by the processor or PCI. See Section 7.2.1 for GART programming details

2.3I/O Mapped Registers

The 460GX chipset contains two registers that reside in the CPU I/O address space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window. The following sections define the fields within the CONFIG_ADDRESS and CONFIG_DATA registers. The 460GX chipset’s device ID mapping into the CONFIG_ADDRESS definition is shown in Table 2-1.

2.3.1CONFIG_ADDRESS: Configuration Address Register

I/O Address:

CF8h [Dword]

Size:

32 bits

Default Value:

00000000h

Attribute:

Read/Write

Sticky:

No

Locked:

No

CONFIG_ADDRESS is a 32 bit register accessed only when referenced as a Dword. A Byte or Word reference will “pass through” the Configuration Address Register onto the PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended.

Bits Description

31Configuration Enable(CFGE).

When this bit is set to 1 accesses to PCI configuration space are enabled. If this bit is reset to 0 accesses to PCI configuration space are disabled.

30:24 reserved (0)

23:16 Bus Number.

When the Bus Number is programmed to match the Chipset Bus Number (CBN), the target of the Configuration Cycle is the 460GX chipset. If the Bus Number is not CBN, the destination and type of access is determined by the Bus Number and Subordinate Bus Number of each PCI port in each PXB. A type 0 access is generated on the appropriate PCI bus if one of the PXB port’s bus number is matched. Otherwise, a type 1 configuration cycle is generated on the appropriate PCI bus below the PXB port whose

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subordinate bus number is in that range. For a type 1 cycle, the Bus Number is mapped to AD[23:16] during the address phase.

15:11 Device Number.

This field selects one agent on the PCI bus selected by the Bus Number. Device 16 (10h) on Bus #0 is always reserved for programming the CBN. On the bus that the chipset is mapped into (determined by the CBN register), Device Numbers 0-31 are reserved for the 460GX chipset components as shown in Table 2-1. All other devices numbers are forwarded to the selected bus.

1 0:8 Function Number.

This field is mapped to AD[10:8] during PCI configuration cycles. This allows the configuration registers of a particular function in a multi-function device to be accessed.

7:2 Register Number.

This field selects one register within a particular Bus, Device, and Function as specified by the other fields in the Configuration Address Register. This field is mapped to AD[7:2] during PCI configuration cycles.

1:0 reserved (0)

2.3.2CONFIG_DATA: Configuration Data Register

I/O Address:

CFCh

Size:

32 bits

Default Value:

00000000h

Attribute:

Read/Write

Sticky:

No

Locked:

No

CONFIG_DATA is a 32 bit read/write window into configuration space. The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS.

Bits Description

31:0 Configuration Data Window (CDW).

If bit 31 of CONFIG_ADDRESS is 1 any I/O reference that falls in the CONFIG_DATA I/O space will be mapped to configuration space using the contents of CONFIG_ADDRESS.

2.4Error Handling Registers

2.4.1SAC

2.4.1.1

SECTID: SEC ITID

 

 

 

 

Bus CBN, Device Number:

00h

Function:

0

 

Address Offset:

80h

Size:

8 bits

 

Default Value:

00h

Attribute:

Read Only/Write

 

 

 

 

Clear, Read/Write

 

Sticky:

Yes

Locked:

No

This register is used to capture the ITID for a single bit memory ECC error. The ITID can then be used to determine the address of the failure. To force the ITID to be cleared and re-used, write a 1 to bit 6. This register is set anytime that the SEC bit is sent from the SDC to the SAC on a ’Retire ITID’ command.

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Bits Description

7Disable

This bit can be written by software. When set, the ITID is retired immediately and not captured. Therefore there can be no checking of the address. See Section 6 for the usage of this bit.

6Valid

If set then the ITID in bits 5:0 is valid and shows the address of a single-bit memory error. Writing a 1 to this bit will clear the ITID and reset the valid bit.

5:0 ITID

The ITID of the SEC error. These bits are read-only.

2.4.1.2

DEDTID: DED ITID

 

 

 

 

Bus CBN, Device Number:

00h

Function:

0

 

Address Offset:

81h

Size:

8 bits

 

Default Value:

00h

Attribute:

Read Only/Write

 

 

 

 

Clear, Read/Write

 

Sticky:

Yes

Locked:

No

This register is used to capture the ITID for a double bit memory ECC error. The ITID can then be used to determine the address of the failure. To force the ITID to be cleared and re-used, write a 1 to bit 6. This register is set anytime that the DED bit is sent from the SDC to the SAC on a ‘Retire ITID’ command.

Bits Description

7Disable

This bit can be written by software. When set, the ITID is retired immediately and not captured. Therefore there can be no checking of the address. See Section 6 for the usage of this bit.

6Valid

If set then the ITID in bits 5:0 is valid and shows the address of a double-bit memory error. Writing a 1 to this bit will clear the ITID and reset the valid bit.

5:0 ITID

The ITID of the double-bit error. These bits are read-only.

2.4.1.3

FSETID: FSE ITID

 

 

 

 

Bus CBN, Device Number:

00h

Function:

0

 

Address Offset:

82h

Size:

8 bits

 

Default Value:

00h

Attribute:

Read Only/Write

 

 

 

 

Clear, Read/Write

 

Sticky:

Yes

Locked:

No

This register is used to capture the ITID for a system bus data error. The ITID can then be used to determine the address of the failure. To force the ITID to be cleared and re-used, write a 1 to bit 6. This register is set anytime that the ADE bit is asserted and both SEC and DED are deasserted on a ’Retire ITID’ command from the SDC to the SAC. NOTE: this register is set for both processorbus errors and errors on the SAC-to-SDC data bus.

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Bits Description

7Disable

This bit can be written by software. When set, the ITID is retired immediately and not captured. Therefore there can be no checking of the address. See Section 6 for the usage of this bit.

6Valid

If set then the ITID in bits 5:0 is valid and shows the address of a system bus data error. Writing a 1 to this bit will clear the ITID and reset the valid bit.

5:0 ITID

The ITID of the system bus error. These bits are read-only.

2.4.1.4FERR_SAC: First Error Status Register

Bus CBN, Device Number:

00h

Function:

1

Address Offset:

40h

Size:

32 bits

Default Value:

000000h

Attribute:

Read/Write Clear

Sticky:

Yes

Locked:

No

This register records the first error condition detected in the SAC/SDC.

Bits Description

31Memory Card B Error (MBE)

Set when the memory card B signals a fatal error.

30Memory Card A Error (MAE)

Set when the memory card A signals a fatal error.

29XSERR# Asserted (XSA)

Set when the SAC sees the signal XSERR# active.

28 ‘Store-Write’ Command Underflow, card A, Stack L (SCAL)

27 ‘Store-Write’ Command Underflow, card A, Stack R (SCAR)

26 ‘Store-Write’ Command Underflow, card B, Stack L (SCBL)

25‘Store-Write’ Command Underflow, card B, Stack R (SCBR)

One of these 4 is asserted when a signal is sent from the SDC to the SAC indicating write data was sent to the MDC, and there is no outstanding write in the SAC.

24SDC Correctable Memory Error (SCME)

Reports correctable DRAM errors (single-bit ECC errors). This bit does not mask other bits in the FERR register from being set. It is the one exception to the rule that only one bit in FERR may be set at a time.

23SDC Non-Fatal Error (SNE)

Reports non-fatal errors that are uncorrectable such as double-bit ECC error, or parity errors. This also reports a single-bit correctable error on the system bus. This bit will also be set if there is a second correctable error from memory in the SDC, and the first one has not been cleared by the time the second one occurs. The first correctable memory error would have set the SCME bit, and all later correctable memory errors (until the SDC’s error registers are cleared) are reported as SNE in the FERR or NERR.

22SDC Fatal Error (SFE)

Fatal error in SDC.

21 ‘Completion’ Command Underflow; MAC A, Stack L (CCAL)

20 ‘Completion’ Command Underflow; MAC A, Stack R (CCAR)

19 ‘Completion’ Command Underflow; MAC B, Stack L (CCBL)

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18‘Completion’ Command Underflow; MAC B, Stack R (CCBR)

One of these 4 bits is set when the SAC receives a completion from the MAC and the SAC has no outstanding transaction.

17BERR# Observed (BER)

BERR# seen on the system bus. Set whenever BERR# is observed active.

16IOQ Underflow/Overflow (IUE)

Set when the IOQ is empty and the SDC sends out a signal saying it popped something from the top of the queue. Or set when the IOQ is 8 (or 1 when the IOQ depth is set to 1) and an ADS# is seen on the bus.

15 reserved(0)

14External XBINIT# Active. (XBE)

Set when XBINIT# is seen active. This signal is from an Expander port or other external agent.

13False Retirement (FRE)

Retirement from SDC that doesn’t match an outstanding ITID in the SAC.

12Address above TOM (TE)

Asserted when an address on the system bus is above TOM and not inside the I/O gap below 4 GB.

11Illegal HITM# (IHS)

HITM# on non-memory access.

10Unsupported ASZ[1:0]# (ASE)

Processor access to an address above 64 GB, so that ASZ# = 10b or 11b.

9System Bus Address Parity Error (AE)

Parity error on A[36:3]#.

8System Bus Request Parity Error (RQE)

Parity error on REQ[4:0]#.

7PDB ITID Parity Error (IPE)

Parity error on the ITID bus from SDC to SAC.

6Retirement Bus Parity Error (RPE)

Parity error on the retirement bus from the SDC to the SAC.

5Lock# Transaction With No Resources Available (LTE)

Set when a LOCK# transaction occurs and there are no outbound resources available in which to place the lock.

4:1 reserved(0)

0Resource Counter Overflow/Underflow (RCE)

Set if the resource counter has an underflow or overflow.

2.4.1.5NERR_SAC: All Error Status Register

Bus CBN, Device Number:

00h

Function:

1

Address Offset:

44h

Size:

32 bits

Default Value:

000000h

Attribute:

Read/Write Clear

Sticky:

Yes

Locked:

No

This register records all error conditions detected in the SAC/SDC.

Bits Description

31:0 See FERR_SAC for bit definitions.

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Intel® 460GX Chipset Software Developer’s Manual

Register Descriptions

2.4.1.6SA_FERR: System Address on First Error

Bus CBN, Device Number:

00h

Function:

1

Address Offset:

60h

Size:

128 bits

Default Value:

undefined after

Attribute:

Read Only

Sticky:

Yes

Locked:

No

This register records and latches the address for the first system bus error detected.

Bits Description

127:107 Reserved (0)

106 LOCK, ’b’ phase.

105 ADS, ’b’ phase.

104 RP#, ’b’ phase. 103:99 REQ, ’b’ phase. 98 AP1; ’b’ phase.

97 AP0; ’b’ phase.

96:64 A[35:3]#, ’b’ phase. 63:43 Reserved (0)

42 LOCK#, ’a’ phase.

41 ADS#, ’a’ phase.

40RP# for REQa#.

Parity on REQa# signals.

39:35 REQa#.

REQa signals on error.

34:33 AP[1:0]#, ’a’ phase.

Address parity for failing address.

32:0 Aa[35:3]#, ’a’ phase.

System Bus - System Address of Error.

2.4.1.7BIUITID: BIU ITID Register

Bus CBN, Device Number:

00h

Function:

1

Address Offset:

80h

Size:

8 bits

Default Value:

0

Attribute:

Read/Write

Sticky:

No

Locked:

No

A write to this register causes the SAC to update the BIUDATA register with the contents of the CAM and RAM associated with the ITID that is written into this register.

Bits Description

7:6 reserved (0)

5:0 ITID

This is the ITID that is used to address the CAM/RAM structure.

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Register Descriptions

2.4.1.8BIUDATA: BIU Data Register

Bus CBN, Device Number:

00h

Function:

1

Address Offset:

90h

Size:

128 bits

Default Value:

undefined

Attribute:

Read Only

Sticky:

No

Locked:

No

This is the contents of the CAM concatenated with the contents of the RAM associated with the ITID in BIUITID.

Bits

Description

127:116

reserved(0)

115:82

Address bits [35:2].

 

This is the contents of the CAM with address bits [5:2] from the RAM (bit 2 is only of

 

interest if the transaction came from an Expander bus).

81:76

reserved(0)

75:71

Reqa. Request phase a[4:0].

70:63

DID. The DID for the transaction.

62:55

BE. The byte enables for the transaction.

54

reserved (0)

53

OWN. OWN# active.

52

DPS. DPS# active.

51:49

Reqb. Request phase b bits [4:2].

48

Lock. The transaction.had LOCK# asserted.

47

LockLoad. The transaction is the first occurrence of an OB lock sequence.

46:43

Dst. The destination of the transaction.

42

ORetry. A retry due to HITO.

41:36

CMD. The command for the transaction.

35

P2P. Set for peer-to-peer transactions.

34

FEorR. The end-of-request bit from the Expander port.

33:30

FRoute. The Expander bus route.

29:22

FLEN. The length on the Expander bus.

21:12

FTID. The Expander id.

11:9

Len. The length of the transaction.

8

System Bus Retry. The transaction was retried on the bus.

7

Dfr. The transaction is deferred.

6

MEM. The target for the transaction if memory.

5

System Bus. The target for the transaction is the system bus.

4

CLINE. The transaction is for a full line.

3

Zero. If set then this is a 0-length transaction.

2:0

RS. The Response generated for the transaction by the BIU. This may not match the

 

system bus response sent, since the BIU’s response may be changed by the MIU. This

 

may be for a HITM# or other reasons.

Note: Note: if the P2P bit is not set, then bits [34:12] and [76] are not defined, since the transaction originated on the system bus and not the Expander bus.

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Intel® 460GX Chipset Software Developer’s Manual

Register Descriptions

2.4.2SDC

2.4.2.1SEC0_D_FERR: Data on First Memory Card B SEC

Bus CBN, Device Number:

04h

 

 

Address Offset:

40-47h

Size:

64 bits

Default Value:

0

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the data corresponding to the first SEC detected by memory interface 0 in the SDC.

Bits Description

63:0 DE - System Data of Error.

2.4.2.2SEC0_ECC_FERR: ECC on First Memory Card B SEC

Bus CBN, Device Number:

04h

 

 

Address Offset:

48h

Size:

8 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the ECC checkbits corresponding to the first SEC detected by memory interface 0 in the SDC

Bits Description

7:0 ECC - ECC of Error.

2.4.2.3SEC0_TXINFO_FERR: TXINFO on First Memory Card B SEC

Bus CBN, Device Number:

04h

 

 

Address Offset:

49-4Ah

Size:

16 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records the ITID and failing chunk corresponding to the first SEC detected by memory interface 0 in the SDC.

Bits Description

15:9 reserved(0)

8:6 DC - Data Chunk of ITID.

5:0 ITID - ITID of error.

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Register Descriptions

2.4.2.4DED0_D_FERR: Data on First Memory Card B DED

Bus CBN, Device Number:

04h

 

 

Address Offset:

50-57h

Size:

64 bits

Default Value:

0

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the data corresponding to the first DED detected by memory interface 0 in the SDC.

Bits Description

63:0 DE - System Data of Error.

2.4.2.5DED0_ECC_FERR: ECC on First Memory Card B DED

Bus CBN, Device Number:

04h

 

 

Address Offset:

58h

Size:

8 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the ECC checkbits corresponding to the first SEC detected by memory interface 0 in the SDC

Bits Description

7:0 ECC - ECC of Error.

2.4.2.6DED0_TXINFO_FERR: TXINFO on First Memory Card B DED

Bus CBN, Device Number:

04h

 

 

Address Offset:

59-5Ah

Size:

16 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records the ITID and failing chunk corresponding to the first DED detected by memory interface 0 in the SDC.

Bits Description

15:9 reserved(0)

8:6 DC - Data Chunk of ITID.

5:0 ITID - ITID of error.

2.4.2.7SEC1_D_FERR: Data on First Memory Card A SEC

Bus CBN, Device Number:

04h

 

 

Address Offset:

60-67h

Size:

64 bits

Default Value:

0

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

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Intel® 460GX Chipset Software Developer’s Manual

Register Descriptions

This register records and latches the data corresponding to the first SEC detected by memory interface 1 in the SDC.

Bits Description

63:0 DE - System Data of Error.

2.4.2.8SEC1_ECC_FERR: ECC on First Memory Card A SEC

Bus CBN, Device Number:

04h

 

 

Address Offset:

68h

Size:

8 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the ECC checkbits corresponding to the first SEC detected by memory interface 1 in the SDC.

Bits Description

7:0 ECC - ECC of Error.

2.4.2.9SEC1_TXINFO_FERR: TXINFO on First Memory Card A SEC

Bus CBN, Device Number:

04h

 

 

Address Offset:

69-6Ah

Size:

16 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records the ITID and failing chunk corresponding to the first SEC detected by memory interface 1 in the SDC.

Bits Description

15:9 reserved(0)

8:6 DC - Data Chunk of error.

5:0 ITID - ITID of error.

2.4.2.10DED1_D_FERR: Data on First Memory Card A DED

Bus CBN, Device Number:

04h

 

 

Address Offset:

70-77h

Size:

64 bits

Default Value:

0

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the data corresponding to the first DED detected by memory interface 1 in the SDC.

Bits Description

63:0 DE - System Data of Error.

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2-13

Register Descriptions

2.4.2.11DED1_ECC_FERR: ECC on First Memory Card A DED

Bus CBN, Device Number:

04h

 

 

Address Offset:

78h

Size:

8 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the ECC checkbits corresponding to the first DED detected by memory interface 0 in the SDC.

Bits Description

7:0 ECC - ECC of Error.

2.4.2.12DED1_TXINFO_FERR: TXINFO on First Memory Card A DED

Bus CBN, Device Number:

04h

 

 

Address Offset:

79-7Ah

Size:

16 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records the ITID and failing chunk corresponding to the first DED detected by memory interface 1 in the SDC.

Bits Description

15:9 reserved(0)

8:6 DC - Data Chunk of ITID.

5:0 ITID - ITID of error.

2.4.2.13SDC_FERR: First Error Status Register

Bus CBN, Device Number: 04h

 

 

Address Offset:

80-83h

Size:

32 bits

Default Value:

0000h

Attribute:

Read/Write to Clear

This register records the first error condition detected in the SDC. Writing a ’1’ to this register will clear the bit in both SDC_FERR and the same bit in SDC_NERR.

Bits Description

31Simultaneous S/W write-one-to-clear and H/W error detected in the same cycle. This bit will only be set if another bit is also set. This implies that the ERROR>_<TYPE>_FERR data registers associated with the other asserted bit contain stale data.

30PDB Receive Length Error (RLE)

Private Bus receive length error

29DRDY# Protocol Error (FS2)

Asserted when a protocol error is found involving DRDY#, SBUSY# and DBUSY#.

28Write Data Protocol Error (FS1)

Asserted on write protocol errors.

27LEN# Protocol Error (FS0)

Asserted on mismatches of LEN# field and actual data transmitted.

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Register Descriptions

26’Forward’ Overlapping ’Forward’; Card A (FWMDI1)

Indicates FWMDI sampled asserted while a store transaction is in progress

25’Load’ Overlapping ’Load’; Card A (LRMDI1)

Indicates LRMDI sampled asserted while a store transaction is in progress

24’Load’ Overlapping ’Forward’; Card A (WrRd1)

Memory interface 1 detected simultaneous read and write operation. Write and Read collision.

23’Forward’ Overlapping ’Load’; Card A (RdWr1)

Memory interface 1 detected simultaneous read and write operation. Read and write collision.

22’Forward’ Underflow; Card A Right Stack Error (FR1)

Memory interface 0 received Forward right Bank without corresponding Store command

21’Forward’ Underflow; Card A Left Stack Error (FL1)

Memory interface received Forward left Bank without corresponding Store command

20’Accept Underflow’; Card A (AE1)

Memory interface 0 received data without corresponding Accept command

19’Forward’ Overlapping ’Forward’; Card B (FWMDI0)

Indicates FWMDI sampled asserted while a store transaction is in progress

18’Load’ Overlapping ’Load’; Card B (LRMDI0)

Indicates LRMDI sampled asserted while a store transaction is in progress

17’Load’ Overlapping ’Forward’; Card B (WrRd0)

Memory interface 1 detected simultaneous read and write operation. Write and Read collision.

16’Forward’ Overlapping ’Load’; Card B (RdWr0)

Memory interface 1 detected simultaneous read and write operation. Read and write collision.

15’Forward’ Underflow; Card B Right Stack Error (FR0)

Memory interface 0 received Forward right Bank without corresponding Store command

14’Forward’ Underflow; Card B Left Stack Error (FL0)

Memory interface received Forward left Bank without corresponding Store command

13’Accept’ Underflow; Card B (AE0)

Memory interface 0 received data without corresponding Accept command

12Configuration Information Parity Error (CIE)

Data buffer detected data parity while reading config address or data from SDC RAM.

11Response Bus Transmission Error (RTE)

Indicates that the SDCRSP bus detected a transmission error.

10PDB - ITID Parity Error (IPE)

Look in ITID_FERR Register to isolate.

9PDB - Command Parity Error (CPE)

Look in CMD_FERR Register to isolate.

8PDB Byte Enable Parity Error (BPE)

Parity error on the Byte-enables from the SAC.

7SDC Data Buffer RAM Parity Error (RPE)

SDC detected bad parity on good data stored in its data buffer. Indicates potential RAM cell disturbance due to alpha or cosmic hit. All four data port map to this bit.

6PDB - Data Parity Error (DPE)

Parity Error Detected on transfer of Data from SAC to SDC.

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2-15

Register Descriptions

5System Bus Double Bit Error (DEDF)

ECC Double Bit Error Detected on system bus.

4System Bus Single Bit Error (SECF)

ECC Single Bit Error Detected on system bus.

3SDC Card A Double Bit Error (DED1)

ECC Double Bit Error Detected from Memory Card A.

2SDC Card A Single Bit Error (SEC1)

ECC Single Bit Error Detected from Memory Card A.

1SDC Card B Double Bit Error (DED0)

ECC Double Bit Error Detected from Memory Card B.

0SDC Card B Single Bit Error (SEC0)

ECC Single Bit Error Detected from Memory Card B.

2.4.2.14SDC_NERR: SDC Next Error Status Register

Bus CBN, Device Number: 04h

 

 

Address Offset:

84-87h

Size:

32 bits

Default Value:

0000h

Attribute:

Read/Write to Clear

This register records the next error status within the SDC. Writing a ’1’ to this register will clear the bit in both SDC_NERR and the same bit in SDC_FERR.

Bits Description

31:0 See SDC_FERR for bit definitions.

2.4.2.15PCMD_FERR: Command on First PCMD Parity Error

Bus CBN, Device Number:

04h

 

 

Address Offset:

88-8Bh

Size:

32 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the data associated with the first parity error detected on the PCMD bus.

Bits Description

31:19 reserved(0)

18If set then the error was detected on the 1st half of the double–pumped transfer. Otherwise, these fields contain the information from the 2nd half of the double-pumped transfer.

17

Parity of Error

16:0 PCMD - Private Data Command value of Error.

2.4.2.16PITID_FERR: Data on First PITID Parity Error

Bus CBN, Device Number:

04h

 

 

Address Offset:

8Ch

Size:

8 bits

Default Value:

0h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

2-16

 

Intel® 460GX Chipset Software Developer’s Manual

Register Descriptions

This register records and latches the data associated with the first parity error detected on the PITID bus.

Bits Description

7If set then the error was detected on the 1st half of the double-pumped transfer. Otherwise, these fields contain the information from the 2nd half of the double-pumped transfer.

6

Parity of Error

5:0 PITID - Private ITID bus value of Error.

2.4.2.17SDCRSP_FERR: Response on First SDCRSP Error

Bus CBN, Device Number:

04h

 

 

Address Offset:

8Dh

Size:

8 bits

Default Value:

0h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the data and inverted data associated with the first transmission error detected on the SDCRSP bus.

Bits Description

7:4 Response Bus for 2nd half of double–pumped transfer. 3:0 Response Bus for 1st half of double–pumped transfer.

2.4.2.18DPBRLE_FERR: Private Data Bus Receive Length Error

Bus CBN, Device Number:

04h

 

 

Address Offset:

8Eh

Size:

8 bits

Default Value:

0h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register indicates that the amount of data transferred from the SAC to the SDC for a given transfer did not match the expected transfer length.

Bits

Description

7:3

reserved(0)

2

Data packet longer than expected (LDP)

1

Data packet shorter than expected (SDP)

0 No data packet shipped as expected (NDP)

2.4.2.19ECCMSK0: ECC Mask Register - Card B

Bus CBN, Device Number:

04h

 

 

Address Offset:

C8h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write

This register is used to test the ECC error detection logic in the memory subsystem for memory card 0. To test, this register is written with a masking function. All subsequent writes into memory will store a masked version of the computed ECC. Subsequent reads of memory locations written

Intel® 460GX Chipset Software Developer’s Manual

2-17

Register Descriptions

while masked will return an invalid ECC code. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR with the computed ECC.

Bits Description

7:0 ECC Generation Mask - For 64 bits of data.

2.4.2.20ECCMSK1: ECC Mask Register - Card A

Bus CBN, Device Number:

04h

 

 

Address Offset:

C9h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write

This register is used to test the ECC error detection logic in the memory subsystem for memory card 1. To test, this register is written with a masking function. All subsequent writes into memory will store a masked version of the computed ECC. Subsequent reads of memory locations written while masked will return an invalid ECC code. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR with the computed ECC.

Bits Description

7:0 ECC Generation Mask - For 64 bits of data.

2.4.2.21ECCMSKF: ECC Mask Register

Bus CBN, Device Number:

04h

 

 

Address Offset:

CAh

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write

This register is used to test the ECC error detection logic of the host processor bus. To test, this register is written with a masking function. All subsequent processor reads will received a masked version of ECC code. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR with the computed ECC.

Bits Description

7:0 ECC Generation Mask - For 64 bits of data.

2.4.2.22ParMskP: PB Parity Mask and IB Correction Enable Register

Bus CBN, Device Number:

04h

 

 

Address Offset:

CBh

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write

The first 4 bits of this register are used to test the data parity error detection logic of the private bus. To test, bits 3:0 are written with a masking function. All subsequent private bus reads will receive a masked version of double byte parity. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR with the computed parity.

Bits 7:4 are used to enable ECC or parity checking for the different busses. Note that the SDC defaults to no parity or ECC checking at power-on.

Bits

Description

7

Private Bus parity detection enable.

6

Front Side Bus ECC correction/detection enable.

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Intel® 460GX Chipset Software Developer’s Manual

Register Descriptions

5

Memory Bus A ECC correction/detection enable.

4

Memory Bus B ECC correction/detection enable.

3:0

Double byte parity mask for 128 bits of data.

2.4.2.23PVD_D_FERR: Data on First PVD Parity Error

Bus CBN, Device Number:

04h

 

 

Address Offset:

D0-D7h

Size:

64 bits

Default Value:

0

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the data associated with the first parity error detected on the PVD bus.

Bits Description

63:0 PVD - Private Data Bus data.

2.4.2.24PVD_PAR_FERR: Parity on First PVD Parity Error

Bus CBN, Device Number:

04h

 

 

Address Offset:

D8h

Size:

8 bits

Default Value:

0

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the data associated with the first parity error detected on the PVD bus.

Bits Description

7:4 reserved(0)

3:0 Double–byte parity of error

2.4.2.25PVD_TXINFO_FERR: TXINFO on First PVD Parity Error

Bus CBN, Device Number:

04h

 

 

Address Offset:

D9-DAh

Size:

16 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records the ITID and failing chunk corresponding to the first double-byte parity detected by private bus interface in the SDC.

Bits Description

15:9 reserved(0)

8:6 DC - Data Chunk of ITID.

5:0 ITID - ITID of error.

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2-19

Register Descriptions

2.4.2.26SECF_D_FERR: Data on First System Bus SEC

Bus CBN, Device Number:

04h

 

 

Address Offset:

E0-E7h

Size:

64 bits

Default Value:

0

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the data corresponding to the first SEC detected by system bus interface in the SDC.

Bits Description

63:0 DE - System Data of Error.

2.4.2.27SECF_ECC_FERR: ECC on First System Bus SEC

Bus CBN, Device Number:

04h

 

 

Address Offset:

E8h

Size:

8 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the ECC checkbits corresponding to the first SEC detected by system bus interface in the SDC.

Bits Description

7:0 ECC - ECC of Error.

2.4.2.28SECF_TXINFO_FERR: TXINFO on First System Bus SEC

Bus CBN, Device Number:

04h

 

 

Address Offset:

E9-EAh

Size:

16 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records the ITID and failing chunk corresponding to the first SEC detected by system bus interface in the SDC.

Bits Description

15:9 reserved(0)

8:6 DC - Data Chunk of error.

5:0 ITID - ITID of error.

2.4.2.29DEDF_D_FERR: Data on First System Bus DED

Bus CBN, Device Number:

04h

 

 

Address Offset:

F0-F7h

Size:

64 bits

Default Value:

0

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

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Intel® 460GX Chipset Software Developer’s Manual

Register Descriptions

This register records and latches the data corresponding to the first DED detected by system bus interface in the SDC.

Bits Description

63:0 DE - System Data of Error.

2.4.2.30DEDF_ECC_FERR: ECC on First System Bus DED

Bus CBN, Device Number:

04h

 

 

Address Offset:

F8h

Size:

8 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the ECC checkbits corresponding to the first DED detected by system bus interface in the SDC.

Bits Description

7:0 ECC - ECC of Error.

2.4.2.31DEDF_TXINFO_FERR: TXINFO on First System Bus DED

Bus CBN, Device Number:

04h

 

 

Address Offset:

F9-FAh

Size:

16 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records the ITID and failing chunk corresponding to the first DED detected by system bus interface in the SDC.

Bits Description

15:9 reserved(0)

8:6 DC - Data Chunk of ITID.

5:0 ITID - ITID of error.

2.4.3MAC

2.4.3.1FERR_MAC: First Error Status Register

Bus CBN, Device Number:

05h,06h

Function Number:

00h,01h

Address Offset:

98h

Size:

8 bits

Default Value:

00h

Attribute:

Read

This register records the first error condition detected in the MAC.

Bits Description

7:2 reserved(0)

1Que-Overflow Error

Signals that the MAC received too many commands from the SAC.

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Register Descriptions

0Parity Error - CMND

Parity Error Detected on SAC-MAC CMND Bus. Look in CMND_FERR Register to isolate. When the error is detected, the MAC will complete those operations which have a RAS pending, and stop. No new RAS cycles will be issued after the parity error and that card is effectively dead.

2.4.3.2CMND_FERR: Command on First Error

Bus CBN, Device Number:

05h,06h

Function Number:

00h,01h

Address Offset:

9Ch

Size:

24 bits

Default Value:

0000h

Attribute:

Read

This register records and latches the data on the SAC-MAC Command Bus for the first error detected.

Bits Description

23:22 reserved (0)

21:19 Row address [2:0]

18:17 Command [1:0]

16:0 MA[16:0]

2.4.4PXB

2.4.4.1ERRSTS: Error Status Register

Address Offset:

44h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write Clear, Sticky

This register records error conditions detected from the PCI bus (not already covered in PCISTS), from the Expander Bus, and performance monitoring events.

The register is sticky through reset; that is, the contents of the register remain unchanged during and following the assertion of X(0,1)RST#. This allows system recovery software invoked following a forced reset to examine the flags to determine the cause of an error. Once set, the flags remain set until explicitly cleared by software or a power-good reset.

Bits Description

7 reserved(0).

6PERR# observed on PCI Bus

This flag is set if the PXB detects the PERR# input asserted, and the PXB was not the asserting agent. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. This bit remains set until explicitly cleared by software writing a 1 to this bit.

5Parity Error on Received PCI Data

This flag is set if the PXB detects a parity error on data being read from the PCI bus. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. This bit remains set until explicitly cleared by software writing a 1 to this bit.

4Parity Error on PCI Address

This flag is set if the PXB detects a parity error on the PCI address. This flag may be configured to assert SERR# in the ERRCMD register. This bit remains set until explicitly cleared by software writing a 1 to this bit.

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3Inbound Delayed Read Time-out Flag

Each inbound read request that is accepted and serviced as a delayed read (i.e. the PXB retries the request) will initiate a watchdog timer (215 cycles, per the PCI spec). If the data has been returned and the timer expires before the requesting master initiates its repeat request, this flag will be set. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. This bit remains set until explicitly cleared by software writing a 1 to this bit.

2 reserved(0)

1Performance Monitor #1 Event Flag

This flag is set when the Performance Monitor #1 requests that an interrupt request be asserted. The PME and PMR registers (Section 2.5.3.3, Section 2.5.3.2) describe the conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will be asserted. This bit remains set until explicitly cleared by software writing a 1 to this bit.

0Performance Monitor #0 Event Flag

This flag is set when the Performance Monitor #0 requests that an interrupt request be asserted. The PME and PMR registers (Section 2.5.3.3, Section 2.5.3.2) describe the conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will be asserted. This bit remains set until explicitly cleared by software writing a 1 to this bit.

2.4.4.2ERRCMD: Error Command Register

Address Offset:

46h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write

This register provides extended control over the assertion of SERR# beyond the basic controls specified in the PCI-standard PCICMD register.

Bits Description

7 reserved(0)

6Assert SERR# on Observed Parity Error

If set, the PXB asserts SERR# if PERR# is observed asserted, and the PXB was not the asserting agent.

5Assert SERR# on Received Data with Parity Error

If set, the PXB asserts SERR# upon receiving PCI data (i.e. an inbound write or outbound read) with a parity error. This occurs regardless of whether PXB asserts it’s PERR# pin.

4Assert SERR# on Address Parity Error

If set, the PXB asserts SERR# on detecting a PCI address parity error.

3Assert PERR# on Data Parity Error

If set, and the PERRE bit is set in the PCICMD register, the PXB asserts PERR# upon receiving PCI data with parity errors.

2Assert SERR# on Inbound Delayed Read Time-out

Each inbound read request that is accepted and serviced as a delayed read (i.e. the PXB retries the request) will initiate a watchdog timer (215 cycles, per the PCI spec). If this enable is set, the PXB will assert SERR# if the data has been returned and the timer expires before the requesting master initiates its repeat request. Default=0.

1 reserved(0)

0Return Hard Fail Upon Generating Master Abort

If set, the PXB will return a Hard Fail response through the SAC to the system bus after generating a master abort time-out for an outbound transaction placed on the PCI bus. If cleared, the PXB will return a normal response (with data of all 1’s for a read). In either case, an error flag is set in the PCISTS register. Default=0.

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Register Descriptions

2.4.5GXB

2.4.5.1

FERR_GXB

 

 

 

 

Function Number:

BFN+1

 

 

 

Address Offset:

80h

Size:

8 bits

 

Default Value:

00h

Attribute:

Read/Write Clear

 

Sticky:

Yes

Locked:

No

These registers record the first error detected by the GXB. For the order to clear this register with respect to the other GXB error registers.

Bits

Description

7:3

reserved (0)

2

FERR_PCI bit asserted

1

FERR_AGP bit asserted

0 FERR_GART bit asserted

2.4.5.2FERR_PCI

Function Number:

BFN+1

 

 

Address Offset:

84h

Size:

8 bits

Default Value:

00h each

Attribute:

Read/Write Clear

Sticky:

Yes

Locked:

No

These registers record the first error detected in GPI.

Bits Description

7PCISTS Error Logged

This bit is asserted when an error, except for a master abort, has been logged in the PCI Status register.

6Non-Configuration Master Abort

This bit is asserted when a master abort occurs on any transaction other than a configuration read or configuration write.

reported the same as a master abort - see PCISTS register

5Discard Timer Expiration

This is the 215 clock timeout.

4

SERR# Observed

3

PERR# Observed

2PCI Inbound Read Que Data Parity Error

Parity error detected as read data is retrieved from buffer.

1PCI Outbound Write Que Data Parity Error

Parity error detected as write data is retrieved from buffer.

0Illegal OB GART Access

Access may continue or abort, results undefined.

2.4.5.3FERR_AGP: First Error Status Register for AGP

Function Number:

BFN+1

 

 

Address Offset:

85h

Size:

8 bits

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Default Value:

00h

Attribute:

Read/Write Clear

Sticky:

Yes

Locked:

No

These registers record and latch the first error detected in the AGP interface.

Bits Description

7:6 reserved (0)

5Lo-priority Read Data Que Parity Error

This is data returned to the graphics card out of the Low-priority buffer.

4Hi-priority Read Data Que Parity Error

This is data returned to the graphics card out of the Hi-priority buffer.

3

Use of Pipe with Sideband Enabled

2

AGP address from graphics card [63:40] not equal to 0

1AGP Request Queue Overflow

The GXB supports 16 outstanding requests. This bit is set if a new request is sent by the AGP card when the GXB already has 16 requests.

0 Illegal AGP Command

2.4.5.4FERR_GART: First Error Status Register for GART

Function Number:

BFN+1

 

 

Address Offset:

86h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write Clear

Sticky:

Yes

Locked:

No

These registers record and latch the first error detected in the AGP interface.

Bits

Description

7:4

reserved (0)

3

GART Parity Error.

2

GART Entry Invalid

1Illegal Address (after GART translation) in range between GAPBAS and GAPTOP, or in VGA range and VGAGE is asserted, or directed by MARG to PCI instead of memory, or above TOM.

0 reserved (0)

2.4.5.5NERR_AGP: Next Errors Status Register for AGP

Function Number:

BFN+1

 

 

Address Offset:

8Dh

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write Clear

Sticky:

Yes

Locked:

No

This register records all error conditions detected in the AGP interface after the first error. Errors recorded in FERR_AGP are not recorded here.

Bits Description

7:0 See FERR_AGP for definition of these bits.

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Register Descriptions

2.4.5.6NERR_GART

Function Number:

BFN+1

 

 

Address Offset:

8Eh

Size:

8 bits

Default Value:

00h each

Attribute:

Read/Write Clear

Sticky:

Yes

Locked:

No

This register records all error conditions detected in the GART logic after the first error. Errors recorded in FERR_GART are not recorded here.

Bits Description

7:0 See FERR_GART for definitions of these bits.

2.4.5.7PAC_ERR: PCI Address & Cmd First Error

Function Number:

BFN+1

 

 

Address Offset:

A0h

Size:

64 bits

Default Value:

0000000000h each

Attribute:

Read/Write

Sticky:

Yes

Locked:

No

These registers record and latch the Address and Command information on the PCI Bus for the first error detected.

Bits

Description

63:46

reserved(0)

45

PCI Parity (2nd phase of DAC, not defined for non-DAC address).

44

PCI Parity (if DAC, this is the parity of the first half of the address).

43:40

PCI Command - Command of Error.

39:0

PCI Address - Address Received on Error. (possible DAC address).

2.4.5.8PD_ERR: PCI Data First Error

Function Number:

BFN+1

 

 

Address Offset:

A8h

Size:

64 bits

Default Value:

00h each

Attribute:

Read/Write

Sticky:

Yes

Locked:

No

These registers record and latch the Data and Byte Enable information on the PCI Bus for the first error detected.

Bits Description

63:37 reserved(0)

36

PCI Parity.

35:32 PCI Byte Enable [3:0] - Byte Enable of Error.

31:0 PCI Data - Data of Error.

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Register Descriptions

2.4.6WXB

2.4.6.1ERRSTS: Error Status Register

Address Offset:

44h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write Clear,

Sticky

 

 

 

This register records certain error conditions detected from the PCI bus. This register is sticky through reset; that is, the contents of the register remain unchanged during and following the assertion of XRST#. This allows system recovery software invoked following a forced reset to examine the flags to determine the cause of an error. Once set, the flags remain set until explicitly cleared by software or a power-good reset.

Note: Bits 6, 4, and 2 are Reserved on side-b and records a zero value only!

Bits Description

7INTRQ Asserted Flag

This flag is set if the WXB has initiated an INTRQ interrupt event. This bit remains set, and the event signaled, until explicitly cleared by software writing a 1 to this bit. Default = 0.

6XBINIT Asserted Flag

This flag is set if the WXB has asserted XBINIT#. This bit remains set, and the event signaled, until explicitly cleared by software writing a 1 to this bit. Default = 0.

Note: This bit is Reserved on side-b and records a zero value only!

5NEPCI Register Records an PCI Bus Error Flag

This flag is set when the PCI bus reports an error (e.g. data parity error) on transactions to/from other PCI bus agents. This bit remains set until explicitly cleared by software writing a 1 to this bit. This bit is only set when the error is reported through the NEPCI Next Error register, indicating that the error is not the first error occurrence since the First Error register was last cleared. Default = 0.

4

reserved (0)

3FEPCI Register Records an PCI Bus Error Flag

This flag is set when the PCI bus reports an error (e.g. data parity error) on transactions to/from other PCI bus agents. This bit remains set until explicitly cleared by software writing a 1 to this bit. This bit is only set when the error is reported through the FEPCI register, indicating that the error is the first error occurrence since the FEPCI register was last cleared. Default = 0.

2

reserved (0)

1Performance Monitor #1 Event Flag

This flag is set when the Performance Monitor #1 detects an event. The PCI_WXB_PMC1 registers describes the conditions that can cause this to occur. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default = 0.

0Performance Monitor #0 Event Flag

This flag is set when the Performance Monitor #0 detects an event. The PCI_WXB_PMC0 registers describes the conditions that can cause this to occur. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default = 0.

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Register Descriptions

2.4.6.2ERRCMD: Error Command Register

Address Offset:

45h– 46h

Size:

16 bits

Default Value:

8040h

Attribute:

Read/Write

This register provides extended control over the signalling of errors through SERR_OUT#, XBINIT#, and INTRQ#. These controls are in addition to the defined controls specified in the PCIstandard PCICMD register for SERR# assertion.

Bits Description

15XBINITO: XBinit Override Enable

This bit should always be initially set to 0 by software. If set to 0, XBINIT# may be asserted by the WXB. The WXB will automatically set this bit after an XBINIT# is signaled. Default = 1

Note: Software should verify that there are no errors pending (by evaluating the ERRSTS register) before clearing this bit.

Note: This bit is Reserved on side-b and records a value of one only! 14 reserved(0)

Note: This bit is Reserved on side-b and records a value of zero only!

13IRQE: INTRQ Enable

Controls the reporting of WXB transmitted data errors. If set, the WXB will assert an INTRQ interrupt for observed PERR# (including IHPC-driven parity errors) and data parity errors detected in outbound transactions (e.g. Internal Queue Error detected during read by PCI interface). Default = 0.

12ASAPE: Assert SERR# on Address Parity Error

This bit should always be set to 1. When the WXB detects a PCI Address Parity Error and both SERRE and PERRE are set, SERR# (and SERR_OUT#) will be signaled. Default = 0.

11ASDPE: Assert SERR# on any Data Parity Error

If set, the WXB will assert SERR# (and SERR_OUT#) whenever a data parity error is detected in an inbound transaction. The SERRE bit in the PCICMD register must also be set for SERR# (and SERR_OUT#) to be signaled. Default = 0.

10ASDTE: Assert SERR# on Discard Timer Expiration

This bit should always be set to 1. When an inbound read Discard Timer Expiration occurs and SERRE is set, SERR# (and SERR_OUT#) will be signaled. Default = 0.

9:7 reserved(0)

6 reserved(1)

5:0 reserved (0)

2.4.6.3FEPCI: PCI Bus First Error Status Register

Address Offset:

83h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write Clear,

 

 

 

Sticky

This register records and latches the first error observed on the PCI bus. Once an error has been noted in this register, no further updates are allowed. This register is a write-1-to-clear register, meaning that software must write a 1 to the specific bit location it wishes cleared. The response to

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Register Descriptions

each of these errors varies and is (generally) controlled through a combination of the PCICMD and ERRCMD registers. Refer to Section 6.12 for information on the conditional reporting of these errors via the SERR#, XBINIT#, or INTRQ# outputs.

Note, if multiple errors are observed very close in time multiple errors may be signaled as a first error.

Bits Description

7PCILV: PCI Error Logs Valid

This flag is set when an error has been logged in the FEPCIAL and FEPCIDL log registers. The FEPCI status bit that lead to the logging must be cleared prior to clearing the PCILV flag. Default = 0.

6UMATA: Unexpected Master or Target Abort

This flag is set when an unexpected master abort or any target abort occurs. Master aborts are reported as described for the RMA bit in the PCISTS register. Target aborts through the RTA bit. Default = 0.

5DTE: Discard Timer Expiration

This flag is set when the 215 clock timeout timer expires. This flag may be configured to assert SERR#, XBINIT#, or an INTRQ interrupt through the ERRCMD register. Default = 0.

4SES: System Error Signaled

This flag is set when the a PCI agent other than the WXB asserts SERR#. This flag may be configured to assert XBINIT#, or an INTRQ interrupt through the ERRCMD register. Default = 0

3PODT: PERR# Observed on PCI Data Transfer

This flag is set if the WXB detects the PERR# input asserted, and the WXB was not the asserting agent. This flag may be configured to assert SERR#, XBINIT#, or an INTRQ interrupt through the ERRCMD register. Default = 0.

2

reserved (0)

1PEOD: Parity Error on Received PCI Data

This flag is set if the WXB detects an parity error (i.e. calculates a parity different from what is provided with the data) on data being sent to the WXB on the PCI bus (from a master read or target write). Default = 0.

0PEPA: Parity Error on PCI Address

This flag is set if the WXB detects a parity error on the PCI address. Default = 0.

2.4.6.4NEPCI: PCI Bus Next Error Status Register

Address Offset:

87h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write Clear,

Sticky

 

 

 

This register records any PCI bus errors detected after the first error is observed and recorded in the FEPCI register. This register is a write-1-to-clear register, meaning that software must write a 1 to the specific bit location it wishes cleared. The response to each of these errors varies and is (generally) controlled through a combination of the PCICMD and ERRCMD registers. Error logging is not performed for Next Error occurrences.

Bits Description

7:0 See the FEPCI register description for definitions. Error logging is not performed for Next Error occurrences.

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Register Descriptions

2.4.6.5FEPCIAL: PCI First Error Address/Command Log

Address Offset:

A5h–ADh

Size:

72 bits

Default Value:

000000000000000000h

Attribute:

Read/Write Clear,

Sticky

 

 

 

These registers record and latch the address/command information, sent or received, associated with a PCI Bus error for the first error detected.

Bits Description

71:68 reserved (0)

67:64 C/BE[3:0]

63:32 AD[63:32]

31:0 AD[31:0]

2.4.6.6FEPCIDL: PCI First Error Data Log

Address Offset:

AFh – B3h

Size:

40 bits

Default Value:

0000000000h

Attribute:

Read/Write Clear,

Sticky

 

 

 

These registers record and latch the PCI information, sent or received, specifically associated with the PCI bus error for the first error detected. The recorded data contains the upper or lower AD and C/BE and PAR signals.

Bits Description

39:37 reserved (0)

36 PAR

35:32 C/BE

31:0 AD

2.5Performance Monitor Registers

2.5.1SAC

2.5.1.1IT_MON_PMD_[0 to 5]: Internal Transaction Performance Monitor Data Register

Bus CBN, Device Number:

00h

Function:

2

Address Offset:

90-97h, 98-9Fh,

Size:

64 bits each

 

A0-A7h, A8-AFh,

 

 

 

B0-B7h, B8-BFh

 

 

Default Value:

0 each

Attribute:

Read/Write

Sticky:

No

Locked:

No

The value written to this address, loads the counter and is also saved in a reload register. Each counter can be configured to reload the data when it overflows.

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