Intel® 460GX Chipset System
Software Developer’s Manual
June 2001
Document Number: 248704 -001
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Copyright © 2002, Intel Corporation
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ii Intel® 460GX Chipset System Software Developer’s Manual
Contents
1 Introduction......................................................................................................................1-1
1.1 System Overview ...............................................................................................1-1
1.1.1 Component Overview............................................................................1-2
1.2 Product Features................................................................................................1-3
1.3 Itanium™ Processor System Bus Support.........................................................1-3
1.4 DRAM Interface Support .... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ................1-4
1.5 I/O Support.........................................................................................................1-4
1.5.1 PXB Features........................................................................................1-4
1.5.2 WXB Features.......................................................................................1-6
1.5.3 GXB Features........................................................................................1-6
1.6 RAS Features........................... .................................................... ...... ....... .........1-6
1.7 Other Platform Components .................................................. ............................. 1- 6
1.7.1 I/O & Firmware Bridge (IFB)..................................................................1-6
1.7.2 Programmable Interrupt Device (PID)...................................................1-7
1.8 Reference Documents . ....... ...... .................................................... ...... ................1-7
1.9 Revision History .................................... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...1-7
2 Register Descriptions ......................................................................................................2-1
2.1 Access Mechanism ............................................................................................2-1
2.2 Access Restrictions............................................................................................2-2
2.2.1 Partitioning ............................................................................................2-2
2.2.2 Register Attributes.................................................................................2-3
2.2.3 Reserved Bits Defined in Registers.......................................................2-3
2.2.4 Reserved or Undefined Register Locations...........................................2-3
2.2.5 Default Upon Reset...............................................................................2-3
2.2.6 Consistency...........................................................................................2-4
2.2.7 GART Programming Region .................................................................2-4
2.3 I/O Mapped Registers ........................................................................................2-4
2.3.1 CONFIG_ADDRESS: Configuration Address Register.........................2-4
2.3.2 CONFIG_DATA: Configuration Data Register ......................................2-5
2.4 Error Handling Registers....................................................................................2-5
2.4.1 SAC.......................................................................................................2-5
2.4.2 SDC.....................................................................................................2-11
2.4.3 MAC ....................................................................................................2-21
2.4.4 PXB.....................................................................................................2-22
2.4.5 GXB.....................................................................................................2-24
2.4.6 WXB....................................................................................................2-27
2.5 Performance Monitor Registers........................................................................2-30
2.5.1 SAC.....................................................................................................2-30
2.5.2 SDC.....................................................................................................2-34
2.5.3 PXB.....................................................................................................2-36
2.5.4 GXB.....................................................................................................2-38
2.5.5 WXB....................................................................................................2-43
2.6 Interrupt Related Registers ..............................................................................2-44
2.6.1 SAC.....................................................................................................2-44
2.6.2 PID PCI Memory-mapped Registers...................................................2-45
2.6.3 PID Indirect Access Registers.............................................................2-46
Intel® 460GX Chipset System Software Developer’s Manual iii
3 System Architecture........................................................................................................3-1
3.1 Coherency..........................................................................................................3-1
3.1.1 Processor Coherency..................................... .......................................3-1
3.1.2 PCI Coherency......................................................................................3-2
3.1.3 AGP Coherency .......................................................... ....... ...... ....... ......3-2
3.2 Ordering .............................................................................................................3-2
3.3 Processor to PCI Traffic and PCI to PCI (Peer-to-Peer) Traffic.........................3-3
3.4 WXB Arbitration..................................................................................................3-3
3.5 Big-endian Support ............................................................................................3-4
3.6 Indivisible Operations.........................................................................................3-4
3.6.1 Processor Locks....................................... ...... ....... ...... ....... ...... ....... ......3-4
3.6.2 Inbound PCI Locks................................................................................3-5
3.6.3 Atomic Writes........................................................................................3-5
3.6.4 Atomic Reads........................................................................................3-5
3.6.5 Locks with AGP Non-coherent Traffic...................................................3-5
3.7 Interrupt Delivery................................................................................................3-6
3.8 WXB PCI Hot-Plug Support ...............................................................................3-6
3.8.1 Slot Power-up and Enable ....................................................................3-7
3.8.2 Slot Power-down and Disable..............................................................3-7
4 System Address Map......................................................................................................4-1
4.1 Memory Map ......................................................................................................4-1
4.1.1 Compatibility Region .............................................................................4-1
4.1.2 Low Extended Memory Region.............................................................4-3
4.1.3 Medium Extended Memory Region.......................................................4-3
4.1.4 High Extended Memory (above 4G)......................................................4-4
4.1.5 Re-mapped Memory Areas...................................................................4-4
4.2 I/O Address Map ................................................................................................4-5
4.3 Devices View of the System Memory Map.........................................................4-7
4.4 Legal and Illegal Address Disposition ................................................................4-8
5 Memory Subsystem ........................................................................................................5-1
5.1 Organization.......................................................................................................5-1
5.1.1 DIMM Types..........................................................................................5-3
5.2 Interleaving/Configurations ................................................................................5-4
5.2.1 Summary of Configuration Rules ..........................................................5-5
5.2.2 Non-uniform Memory Configurations ....................................................5-5
5.3 Bandwidth ..........................................................................................................5-5
5.4 Memory Subsystem Clocking.............................................................................5-6
5.5 Supporting Features...........................................................................................5-6
5.5.1 Auto Detection.......................................................................................5-6
5.5.2 Removing a Bad Row ...........................................................................5-6
5.5.3 Hardware Initialization........................................... ................................5-7
5.5.4 Memory Scrubbing................................................................................5-7
6 Data Integrity and Error Handling...................................................................................6-1
6.1 Integrity ..............................................................................................................6-1
6.1.1 System Bus...........................................................................................6-1
6.1.2 DRAM....................................................................................................6-2
6.1.3 Expander Buses....................................................................................6-2
6.1.4 PCI Buses .............................................................................................6-2
6.1.5 AGP.......................................................................................................6-2
iv Intel® 460GX Chipset System Software Developer’s Manual
6.1.6 Private Bus between SAC and SDC .....................................................6-2
6.2 Memory ECC Routing ........................................................................................6-3
6.3 Data Poisoning...................................................................................................6-3
6.4 Usage of First-error and Next-error....................................................................6-3
6.4.1 Masked Bits...........................................................................................6-4
6.4.2 BERR#/BINIT# Generation ...................................................................6-4
6.4.3 INTREQ#...............................................................................................6-4
6.4.4 XBINIT#.................................................................................................6-5
6.4.5 XSERR#................................................................................................6-5
6.5 SAC/SDC Errors.......... ....... ...... ....... ................................................... ....... ...... ...6-5
6.5.1 Data ECC or Parity Errors.....................................................................6-5
6.5.2 System Bus Errors ................................................................................6-6
6.5.3 SAC to SDC Interface Errors.................................................................6-6
6.5.4 SAC to MAC Interface Errors................................................................6-7
6.5.5 SDC/Memory Card Interface Errors......................................................6-7
6.5.6 SDC/System Bus Errors........................................................................6-8
6.5.7 SDC Internal Errors...............................................................................6-8
6.6 Error Determination............................................................................................6-8
6.6.1 SAC Address on an Error......................................................................6-9
6.6.2 SDC Logging Registers.......................................................................6-10
6.7 Clearing Errors .................................................................................................6-11
6.7.1 SAC/SDC Error Clearing............................. ....... ...... ...........................6 -1 1
6.8 Multiple Errors ..................................................................................................6-11
6.8.1 SDC Multiple Errors.............................................................................6-12
6.8.2 SAC Multiple Errors............ ...... ...... ....... ..............................................6-13
6.8.3 Single Errors with Multiple Reporting ..................................................6-13
6.8.4 Error Anomalies...................................................................................6-13
6.9 Data Flow Errors ..............................................................................................6-14
6.10 Error Conditions ...............................................................................................6-15
6.10.1 Table of Errors....... ...... ....... ...... ...... ....... ...... ....... ................................. 6 -1 5
6.11 PCI Integrity......................................................................................................6-20
6.11.1 PCI Bus Monitoring .............................................................................6-20
6.11.2 PXB as Master ....................................................................................6-20
6.11.3 PXB as Target.....................................................................................6-21
6.11.4 GXB Error Flow ...................................................................................6-22
6.12 WXB Data Integrity and Error Handling............................................................6-26
6.12.1 Integrity................................................................................................6-26
6.12.2 Data Parity Poisoning..........................................................................6-26
6.12.3 Usage of First Error and Next Error Registers ....................................6-26
6.12.4 Error Mask Bits....................................................................................6-27
6.12.5 Error Steering/Signaling......................................................................6-27
6.12.6 INTRQ# Interrupt.................................................................................6-29
6.12.7 Error Determination and Logging........................................................6-29
6.12.8 Error Conditions ..................................................................................6-30
7 AGP Subsystem..............................................................................................................7-1
7.1 Graphics Address Relocation Table (GART) .....................................................7-1
7.1.1 GART Implementation...........................................................................7-3
7.1.2 Programming GART..............................................................................7-4
7.1.3 GART Implementation...........................................................................7-5
7.1.4 Coherency.............................................................................................7-5
7.1.5 Interrupt Handling..................................................................................7-6
Intel® 460GX Chipset System Software Developer’s Manual v
7.2 AGP Traffic........ ....... ................................................... ....... ................................7-6
7.2.1 Addresses Used by the Graphics Card.................................................7-6
7.2.2 Traffic Priority........................................................................................7-7
7.2.3 Coherency, Translation and Types of AGP Traffic................................7-7
7.2.4 Ordering Rules............................ ...... ....... ...... ....... ...... ....... ...... ....... ......7-8
7.2.5 Processor Locks and AGP Traffic.........................................................7-8
7.2.6 Address Alignment and Transfer Sizes.................................................7-9
7.2.7 PCI Semantics Traffic ...........................................................................7-9
7.3 Bandwidth ........................................................................................................7-13
7.3.1 Inbound Read Prefetching ..................................................................7-14
7.4 Latency.............................................................................................................7-14
7.5 GXB Address Map ................................... ...... ....... ...... ....... ...... ....... ...... ....... ....7-14
8 WXB Hot-Plug.................................................................................................................8-1
8.1 IHPC Configuration Registers ............ ...... ...... ....... ...... ....... ...... ....... ...... ....... ......8- 1
8.1.1 Page Number List for the IHPC PCI Register Descriptions...... ....... ......8-3
8.1.2 VID: Vendor Identification Register.......................................................8-3
8.1.3 DID: Device Identification Register........................................................8-3
8.1.4 PCICMD: PCI Command Register........................................................8-4
8.1.5 PCISTS: PCI Status Register................................ ...... ....... ...... ....... ......8-5
8.1.6 RID: Revision Identification Register.....................................................8-5
8.1.7 CLASS: Class Register .........................................................................8-6
8.1.8 CLS: Cache Line Size ...........................................................................8-6
8.1.9 MLT: Master Latency Timer Register....................................................8-6
8.1.10 HDR: Header Register ..........................................................................8-6
8.1.11 Base Address........................................................................................8-7
8.1.12 SVID: Subsystem Vendor Identification ................................................8-7
8.1.13 SID: Subsystem ID................ ...... ...... ....... .............................................8-7
8.1.14 Interrupt Line.........................................................................................8-7
8.1.15 Interrupt Pin...........................................................................................8-8
8.1.16 Hot-Plug Slot Identifier ................................................ ..........................8-8
8.1.17 Miscellaneous Hot-Plug Configuration..................................................8-8
8.1.18 Hot-Plug Features....................... ...... ....... ...... ....... ...... ....... ...... ....... ......8- 9
8.1.19 Switch Change SERR Status................................................................8-9
8.1.20 Power Fault SERR Status.....................................................................8-9
8.1.21 Arbiter SERR Status ...........................................................................8-10
8.1.22 Memory Access Index.........................................................................8-10
8.1.23 Memory Mapped Register Access Port...............................................8-10
8.2 IHPC Memory Mapped Registers ......................... ...........................................8-10
8.2.1 Page Number List for IHPC Memory Mapped Register Descriptions..8-12
8.2.2 Slot Enable..........................................................................................8-12
8.2.3 Hot-Plug Miscellaneous ........ ...... .................................................... ....8-13
8.2.4 LED Control . ...... ....... ...... ....... ...... .................................................... ....8-13
8.2.5 Hot-Plug Interrupt Input and Clear ......................................................8-14
8.2.6 Hot-Plug Interrupt Mask .............................................. ....... ...... ....... ....8-15
8.2.7 Serial Input Byte Data .........................................................................8-16
8.2.8 Serial Input Byte Pointer .....................................................................8-17
8.2.9 General Purpose Output.....................................................................8-17
8.2.10 Hot-Plug Non-interrupt Inputs ........... ....... ...... ....... ...... ....... .................8-17
8.2.11 Hot-Plug Slot Identifier ................................................ ........................8-17
8.2.12 Hot-Plug Switch Interrupt Redirect Enable..........................................8-18
8.2.13 Slot Power Control ..............................................................................8-18
vi Intel® 460GX Chipset System Software Developer’s Manual
8.2.14 Extended Hot-Plug Miscellaneous ......................................................8-18
9 IFB Register Mapping......................................................................................................9-1
9.1 PCI / LPC / FWH Configuration..........................................................................9-1
9.1.1 PCI Configuration Registers (Function 0)..............................................9-1
9.2 IDE Configuration...............................................................................................9-3
9.2.1 PCI Configuration Registers (Function 1)..............................................9-3
9.3 Universal Serial Bus (USB) Configuration..........................................................9-4
9.3.1 PCI Configuration Registers (Function 2)..............................................9-4
9.4 SMBus Controller Configuration.........................................................................9-5
9.4.1 SMBus Configuration Registers (Function 3)........................................9-5
10 IFB Usage Considerations ............................................................................................10-1
10.1 Usage of 1MIN Timer in Power Management ..................................................10-1
10.2 Usage of the SW SMI# Timer...........................................................................10-1
10.3 CD-ROM AUTO RUN Feature of the OS.........................................................10-1
10.4 ACPI, SMBus, GPIO Base Address Reporting to the OS................................10-1
10.5 Ultra DMA Configuration ..................................................................................10-2
10.5.1 UDMAC–Ultra DMA Control Register (IFB Function 1 PCI
Configuration Offset 48h) ....................................................................10-2
10.5.2 UDMATIM–Ultra DMA Timing Register (IFB Function 1 PCI
Configuration Offsets 4A-4Bh) .............. ...... ....... ...... ...........................10- 2
10.5.3 Determining a Drive’s Transfer Rate Capabilities ...............................10-3
10.5.4 Determining a Drive’s Best Ultra DMA Capability ...............................10-5
10.5.5 Determining a Drive’s Best Multi Word DMA/Single Word DMA
(Non-ultra DMA) Capability ................... ...... ....... ...... ....... ...... ....... ...... .10-5
10.5.6 IFB Timing Settings.............................................................................10-9
10.5.7 Drive Configuration for Selected Timings..........................................10-11
10.5.8 Settings Checklist..............................................................................10-13
10.5.9 Example Configurations....................................................................10-14
10.5.10 Ultra DMA System Software Considerations.....................................10-16
10.5.11 Additional Ultra DMA/PCI Bus Master IDE Device Driver
Considerations ..................................................................................10-17
10.6 USB Resume Enable Bit ................................................................................10-19
11 LPC/FWH Interface Configuration.................................................................................11-1
11.1 PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0) ..11-1
11.1.1 VID–Vendor Identification Register (Function 0).................................11-1
11.1.2 DID–Device Identification Registe r (Funct ion 0) ................... ....... ...... .11-1
11.1.3 PCICMD–PCI Command Register (Function 0)..................................11-2
11.1.4 PCISTS–PCI Device Status Register (Function 0)..............................11-2
11.1.5 RID–Revision Identification Register (Function 0)...............................11-3
11.1.6 CLASSC–Class Code Register (Function 0).......................................11-3
11.1.7 HEDT–Header Type Register (Function 0) .........................................11-3
11.1.8 ACPI Base Address (Function 0) ........................................................11-4
11.1.9 ACPI Enable (Function 0)....................................................................11-4
11.1.10 SCI IRQ Routing Control.....................................................................11-4
11.1.11 BIOSEN–BIOS Enable Register (Function 0) .....................................11-5
11.1.12 PIRQRC[A:D]–PIRQx Route Control Registers (Function 0) ..............11-5
11.1.13 SerIRQC–Serial IRQ Control Register (Function 0) ............................11-6
11.1.14 TOM–Top of Memory Register (Function 0)........................................11-6
11.1.15 MSTAT–Miscellaneous Status Register (Function 0)..........................11-7
Intel® 460GX Chipset System Software Developer’s Manual vii
11.1.16 Deterministic Latency Control Register (Function 0)...........................11-7
11.1.17 MGPIOC–Muxed GPIO Control (Function 0)......................................11-8
11.1.18 PDMACFG–PCI DMA Configuration Resister (Function O)................11-8
11.1.19 DDMABP–Distributed DMA Slave Base Pointer
Registers (Function 0).........................................................................11-8
11.1.20 RTCCFG–Real Time Clock Configuration Register (Function 0)........11-9
11.1.21 GPIO Base Address (Function 0)......................................................11-10
11.1.22 GPIO Enable (Function 0).................................................................11-10
11.1.23 LPC COM Decode Ranges (Function 0)...........................................11-10
11.1.24 LPC FDD/LPT Decode Ranges (Function 0) ....................................11-11
11.1.25 LPC Sound Decode Ranges (Function 0).........................................11-12
11.1.26 LPC Generic Decode Range (Function 0).........................................11-12
11.1.27 LPC Enables (Function 0).................................................................11-13
11.2 PCI to LPC I/O Space Registers....................................................................11-15
11.2.1 DMA Registers..................................................................................11-15
11.2.2 Interrupt Controller Registers............................................................11-20
11.2.3 Counter/Timer Registers ...................................................................11-25
11.2.4 NMI Registers ...................................................................................11-28
11.2.5 Real Time Clock Registers................................................................11-29
11.2.6 Advanced Power Management (APM) Registers..............................11-30
11.2.7 ACPI Registers..................................................................................11-31
11.2.8 SMI Registers....................................................................................11-35
11.2.9 General Purpose I/O Registers.........................................................11-37
12 IDE Configuration..........................................................................................................12-1
12.1 PCI Configuration Registers (Function 1) ........................................................12-1
12.2 IDE Controller Register Descriptions (PCI Function 1) ....................................12-1
12.2.1 VID–Vendor Identification Register (Function 1).................................12-2
12.2.2 DID–Device Identification Register (Function 1) .................................12-2
12.2.3 PCICMD–PCI Command Register (Function 1)..................................12-2
12.2.4 PCISTS–PCI Device Status Register (Function 1)..............................12-3
12.2.5 CLASSC–Class Code Register (Function 1).......................................12-3
12.2.6 MLT–Master Latency Timer Register (Function 1)..............................12-4
12.2.7 BMIBA–Bus Master Interfa ce Base Address Regi ster
(Function 1).........................................................................................12-4
12.2.8 SVID–Subsystem Vendor ID (Function 1)...........................................12-5
12.2.9 SID–Subsystem ID (Function 1)..........................................................12-5
12.2.10 IDETIM–IDE Timing Register (Function 1)..........................................12-5
12.2.11 SIDETIM–Slave IDE Timing Register (Function 1) .............................12-6
12.2.12 DMACTL–Synchronous DMA Control Register (Function 1)..............12-7
12.2.13 SDMATIM–Synchronous DMA Timing Register (Function 1).............12-8
12.3 IDE Controller I/O Space Registers .................................................................12-9
12.3.1 BMICx–Bus Master IDE Command Register (I/O)..............................12-9
12.3.2 BMISx–Bus Master IDE Status Register (I/O)...................................12-10
12.3.3 BMIDTPx–Bus Master IDE Descriptor Table Pointer Register (I/O) .12-11
13 Universal Serial Bus (USB) Configuration.....................................................................13-1
13.1 PCI Configuration Registers (Function 2) ........................................................13-1
13.2 USB Host Controller Register Descriptions (PCI Function 2) ..........................13-2
13.2.1 VID–Vendor Identification Register (Function 2).................................13-2
13.2.2 DID–Device Identification Register (Function 2) .................................13-2
13.2.3 PCICMD–PCI Command Register (Function 2)..................................13-2
viii Intel® 460GX Chipset System Software Developer’s Manual
13.2.4 PCISTS–PCI Device Status Register (Function 2)..............................13-3
13.2.5 RID–Revision Identification Register (Function 2)...............................13-3
13.2.6 CLASSC–Class Code Register (Function 2).......................................13-4
13.2.7 MLT–Master Latency Timer Register (Function 2)..............................13-4
13.2.8 HEDT–Header Type Register (Function 2) .........................................13-4
13.2.9 USBBA–USB I/O Space Base Address (Function 2) ..........................13-5
13.2.10 SVID–Subsystem Vendor ID (Function 2)...........................................13-5
13.2.11 SID–Subsystem ID (Function 2)..........................................................13-5
13.2.12 INTLN–Interrupt Line Register (Function 2) ........................................13-5
13.2.13 INTPN–Interrupt Pin (Function 2)........................................................13-6
13.2.14 Miscellaneous Control (Function 2).....................................................13-6
13.2.15 SBRNUM–Serial Bus Release Number (Function 2) ..........................13-6
13.2.16 LEGSUP–Legacy Support Register (Function 2)................................13-6
13.2.17 USBREN–USB Resume Enable .........................................................13-8
13.3 USB Host Controller I/O Space Registers........................................................13-8
13.3.1 USBCMD–USB Command Register (I/O) ...........................................13-8
13.3.2 USBSTS–USB Status Register (I/O).................................................13-10
13.3.3 USBINTR–USB Interrupt Enable Register (I/O)................................13-10
13.3.4 FRNUM–Frame Number Register (I/O).............................................13-11
13.3.5 FLBASEADD–Frame List Base Address Register (I/O)....................13-11
13.3.6 SOFMOD–Start of Frame (SOF) Modify Register (I/O).....................13-11
13.3.7 PORTSC–Port Status and Control Register (I/O) .............................13-12
14 SM Bus Controller Configuration...................................................................................14-1
14.1 SM Bus Configuration Registers (Function 3)..................................................14-1
14.2 System Management Register Descriptions ....................................................14-2
14.2.1 VID–Vendor Identification Register (Function 3).................................14-2
14.2.2 DID–Device Identification Registe r (Funct ion 3) ................... ....... ...... .14-2
14.2.3 PCICMD–PCI Command Register (Function 3)..................................14-2
14.2.4 PCISTS–PCI Device Status Register (Function 3)..............................14-3
14.2.5 RID–Revision Identification Register (Function 3)...............................14-3
14.2.6 CLASSC–Class Code Register (Function 3).......................................14-4
14.2.7 SMBBA–SMBus Base Address (Function 3).......................................14-4
14.2.8 SVID–Subsystem Vendor ID (Function 3)...........................................14-4
14.2.9 SID–Subsystem ID (Function 3)..........................................................14-5
14.2.10 INTLN–Interrupt Line Register (Function 3) ........................................14-5
14.2.11 INTPN–Interrupt Pin (Function 3)........................................................14-5
14.2.12 Host Configuration....................................... ....... .................................1 4- 5
14.2.13 smbslvc–SMBus Slave Command (Function 3) ..................................14-6
14.2.14 smbshdw1–SMBus Slave Shadow Port 1 (Function 3).......................14-6
14.2.15 smbshdw2–SMBus Slave Shadow Port 2 (Function 3).......................14-6
14.3 SMBus I/O Space Registers.............................................................................14-6
14.3.1 smbhststs–SMBus Host Status Register (I/O) ....................................14-7
14.3.2 smbslvsts–SMBus Slave Status Register (I/O) ...................................14-7
14.3.3 smbhstcnt–SMBus Host Control Regis ter (I/O)...................................14-8
14.3.4 smbhstcmd–SMBus Host Command Register (I/O)............................14-9
14.3.5 smbhstadd–SMBus Host Address Register (I/O)................................14-9
14.3.6 smbhstdat0–SMBus Host Data 0 Register (I/O)..................................14-9
14.3.7 smbhstdat1–SMBus Host Data 1 Register (I/O)................................14-10
14.3.8 smbblkdat–SMBus Block Data Register (I/O) ...................................14-10
14.3.9 smbslvcnt–SMBus Slave Control Register (I/O)................................14-10
14.3.10 smbslvdat–SMBus Slave Data Register (I/O) ...................................14-11
Intel® 460GX Chipset System Software Developer’s Manual ix
15 PCI/LPC Bridge Descrip tio n........ ....... ...... ....... ...... ...... ....... ...... .....................................15-1
15.1 PCI Interface ....................................................................................................15-1
15.1.1 Transaction Termination .....................................................................15-1
15.1.2 Parity Support ............................. ...... ....... ...... ....... ...... ....... ...... ........... 15- 1
15.1.3 PCI Arbitration.....................................................................................15-1
15.2 Interrupt Controller ...........................................................................................15-1
15.2.1 Programming the Interrupt Controller..................................................15-2
15.2.2 End of Interrupt Operation...................................................................15-3
15.2.3 Modes of Operation .. ...... ....... ...... ...... ..................................................15- 4
15.2.4 Cascade Mode....................................................................................15-5
15.2.5 Edge and Level Triggered Mode.........................................................15-6
15.2.6 Interrupt Masks ...................................................................................15-6
15.2.7 Reading the Interrupt Controller Status...............................................15-7
15.2.8 Interrupt Steering ................................................................................15-7
15.3 Serial Interrupts........ ...... ....... ...... ....... ...... ...... ....... ...... .....................................15-8
15.3.1 Protocol...............................................................................................15-8
15.4 Timer/Counters ..............................................................................................15-10
15.4.1 Programming the Interval Timer........................................................15-10
15.5 Real Time Clock.............................................................................................15-13
15.5.1 RTC Registers and RAM...................................................................15-14
15.5.2 RTC Update Cycle ............................................................................15-17
15.5.3 RTC Interrupts...................................................................................15-17
15.5.4 Lockable RAM Ranges .....................................................................15-17
16 IFB Power Management ...............................................................................................16-1
16.1 Overview ..........................................................................................................16-1
16.2 IFB Power Planes ............................................................................................16-2
16.2.1 Power Plane Descriptions ...................................................................16-2
16.2.2 SMI# Generation.................................................................................16-2
16.2.3 SCI Generation ...................................................................................16-3
16.2.4 Sleep States................... .................................................... ...... ........... 16- 3
16.2.5 ACPI Bits Not Implemented by IFB.....................................................16-4
16.2.6 Entry/Exit for the S4 and S5 States.....................................................16-4
16.3 Handling of Power Failures in IFB....................................................................16-5
Figures
1-1 Diagram of a Typical Intel® 460GX Chipset-based System with AGP ..............1-1
4-1 System Memory Address Space........................................................................4-2
4-2 Itanium™ Processor and Chipset-specific Memory Space................................4-5
4-3 System I/O Address Space................................................................................4-6
4-4 System Memory Address Space as Viewed from an Expander
Bridge (PXB/GXB)..............................................................................................4-7
5-1 Maximum Memory Configuration Using Two Cards...........................................5-2
5-2 Address Interleaving ..........................................................................................5-4
6-1 SAC Error Flow on Data...................................................................................6-14
6-2 SDC Error Data Flow .......................................................................................6-15
6-3 GXB Error Flow.............. ....... ...... ....... ...... ...... ....... ...... .....................................6-25
7-1 GART Table Usage for 4k Pages.......................................................................7-2
7-2 GART Table Usage for 4 MB Pages..................................................................7-2
7-3 GART Entry Format for 4kB Pag es.... ...... ...... ....... ...... ....... ...... ..........................7-3
x Intel® 460GX Chipset System Software Developer’s Manual
Tables
7-4 GART Entry Format for 4 MB Pages..................................................................7-3
7-5 GART SRAM Timings ........................................................................................7-5
1-1 Intel® 460GX Chipset Components ...................................................................1-2
2-1 Device Mapping on Bus CBN.............................................................................2-2
2-2 Memory-Mapped Register Summary ...............................................................2-45
2-3 I/O Select Register Format...............................................................................2-45
2-4 I/O Window Register Format............................................................................2-46
2-5 (x)APIC EOI Register Format...........................................................................2-46
2-6 Memory-mapped Register Summary ...............................................................2-47
2-7 I/O APIC ID Register Format............................................................................2-49
2-8 I/O (x)APIC Version Register Format...............................................................2-49
2-9 I/O (x)APIC Arbitration ID Register Format ......................................................2-50
2-10 I/O (x)APIC RTE Format ..................................................................................2-50
4-1 Address Disposition............................................................................................4-8
5-1 General Mem ory Charac ter isti cs..... ...... ...... ....... ...... ....... ...... ....... ...... ....... .........5-1
5-2 Minimum/Maximum Memory Size per Configuration..........................................5-3
5-3 Required DRAM Parameters..............................................................................5-6
5-4 Scrubbing Time..................................................................................................5-7
6-1 Error Cases ......................................................................................................6-16
6-2 List of WXB Error Sources Selectively Routable to XBINIT#, SERR_OUT#,
and P(A/B)INTRQ#...........................................................................................6-27
6-3 Supported Error Escalation to XBINIT#............................................................6-27
6-4 Supported Error Escalation to SERR_OUT#....................................................6-28
6-5 Supported Error Escalation to P(A/B)INTRQ# .................................................6-28
7-1 Coherency for AGP/PCI Streams.......................................................................7-8
7-2 Delayed Read Matching Criteria ......................................................................7-11
7-3 Burst Write Combining Modes..........................................................................7-13
7-4 Burst Write Combining Examples with 3 Writes in 1X Transfer Mode .............7-13
7-5 Bandwidth Estimates for Various Request Sizes.............................................7-14
8-1 IHPC Configuration Register Space...................................................................8-2
8-2 IHPC Memor Mapped Regis ter Space..................... ....... ...... ....... ...... ....... .......8-11
9-1 PCI Configuration Registers–Function 0(PCI to LPC/FWH Interface Bridge)....9-1
9-2 PCI Configuration Registers–Function 1 (IDE Interface)....................................9-3
9-3 PCI Configuration Registers–Function 2 (USB Interface) ..................................9-4
9-4 PCI Configuration Registers–Function 3 (SMBus Controller Interface) .............9-5
10-1 Identify Device Information Used for Determining Drive Capabilities...............10-3
10-2 Identify Device Information Used for Determining Ultra DMA
Drive Capabilities .................................. ...... ....... ...... ....... ...... ....... ...... ....... ...... .10-5
10-3 Identify Device Information Used for Determining Multi/Single Word DMA
Drive Capabilities .................................. ...... ....... ...... ....... ...... ....... ...... ....... ...... .10-6
10-4 Drive Multi Word DMA/Single Word DMA Capability as a Function
of Cycle Time ...................................................................................................10-7
10-5 Identify Device Information Used for Determining PIO Drive Capabilities........10-8
10-6 Drive PIO Capability as a Function of Cycle Time ...........................................10-8
10-7 IFB Drive Mode Based on DMA/PIO Capabilities ............................................10-9
10-8 IDE Mode/Drive Feature Settings for Optimal DMA/PIO Operation...............10-10
10-9 DMA/PIO Timing Values Based on PIIX Cable Mode/System Speed............10-11
Intel® 460GX Chipset System Software Developer’s Manual xi
10-10 Ultra DMA Timing Value Based on Drive Mode.............................................10-11
10-11 Ultra DMA/Multi Word DMA/Single Word Transfer/Mode Values ..................10-12
10-12 PIO Transfer/Mode Values.............................................................................10-12
10-13 Drive Capabilities Checklist............................................................................10-13
10-14 IFB Settings Checklist....................................................................................10-14
12-1 PCI Configuration Regist ers–Function 1 (IDE Interface) .................................12-1
12-2 Ultra DMA/33 Timing Mode Settings................................................................12-9
12-3 DMA/PIO Timing Values Based on IFB Cable Mode and System Speed........12-9
12-4 Interrupt/Activity Status Combinations...........................................................12-11
13-1 PCI Configuration Regist ers–Function 2............................ ...... ....... ...... ........... 13- 1
13-2 Run/Stop, Debug Bit Interaction.......................................................................13-9
15-1 SERIRQ Frames..............................................................................................15-9
15-2 RTC (Standard) RAM Bank............................................................................15-14
16-1 IFB Power States and Consumption................................................................16-1
16-2 Causes of SMI#................................................................................................16-2
16-3 Causes of SCI#................................................................................................16-3
16-4 ACPI Bits Not Implemented in IFB...................................................................16-4
xii Intel® 460GX Chipset System Software Developer’s Manual
Introduction 1
This document provides information about the Intel® 460GX chipset compon e nts. The 460GX
chipset is a high performance memory and I/O chipset for the Intel Itanium™ processor, targeted
for multiprocessor server and high-end workstation designs.
This document describes the software programmer's interface to the 460GX chipset. It provides a
brief summary of the system architecture supported by the 460GX chipset, a list of features within
the chipset and a detailed description of software or other externally visible segments.
1.1 System Overview
The Intel 460GX chipset is a high performance chipset for Intel Itanium processor-based systems,
targeted for multiprocessor servers and high-performance workstations. It provides the memory
controller interface and appropriate bridges to PCI, AGP 4X, and other standard I/O buses.
Figure 1-1 illustrates the basic system configuration of a four-processor platform.
Figure 1-1. Diagram of a Typical Intel® 460GX Chipset-based Sy stem with AGP
Expansion
GART
SRAM
GXB
Graphics
Bridge
4X Mode
SAC
System Address
Controller
Expander
Buses
AGP
Slot
WXB
Wide PCI
Expansion
Bridge
Cache
Processor
PXB
PCI
Expansion
Bridge
2 PCI Buses
3.3V, 64 -b it, 6 6 MH z
Cache
Processor
Itan i um™ Processor System Bus
MAC
MAC
Memory Subsystem
Memory Data and Control Bus
Progr ammable
Inter ru p t Devic e
Com patibility
PCI Bus
2 PCI Buses
3.3V/5.0 V ,
32-bit, 33 MHz
Private Bus
MAC
MAC
Memo ry Subsystem
PID
Firmware
Hub Interf ace
Cache
Processor
MDC
MDC
MDC
MDC
FWH
Firmware
Hub
Processor
MDC
MDC
MDC
MDC
USB
IFB
I/O and Firmware
Bridge
Cache
Super
I/O
SDC
System Data
Controller
LPC Interface
IDE HD D
IDE CD- R OM
000346e
Intel® 460GX Chipset Software Developer’s Manual 1-1
Introduction
1.1.1 Component Overview
Table 1-1 lists th e 460GX chipset components.
T able 1-1. Intel® 460GX Chipset Components
Component Name Function
SAC 82461GX
System Address
Controller
SDC 82462GX
System Data path
Controller
MAC 82463GX
Memory Address
Controller
MDC 82464GX
Memory Data path
Controller
GXB 82465GX
Graphics Expander
Bridge
WXB 82466GX
Wide and fast PCI
Expander Bridge
PXB 82467GX
PCI Expander Bridge
IFB 82468G X
I/O and Firmware
Bridge
FWH 82802AC
Firmware Hub 8Mb
PID NEC# UPD66566S1-
016
Programmable
Interrupt Device
Interfaces the address and control portion of the Itanium™ processor
system bus and the memory bus. Acts as a host bridge interface to
peripheral I/O devices through four Expander busses.
Interfaces the data portion of the Itanium processor system bus and
the memory bus.
Provides the SDRAM RAS/CAS/WE/CS generation as well as
redriving the address to the SDRAMs. It is capable of buffering several
commands from the SAC.
Multiplexes the data from the SDRAM to the SDC. On reads, it latches
data from the SDRAM, then transfers the data to the SDC. On writes, it
latches the data from the SDC, then writes the data to the SDRAM.
Provides the control and data interface for an AGP 4X graphics port.
This device attaches to the SAC via two Expander busses which utilize
a special configuration.
Provides the primary control and data interface for two independent
64-bit, 66 MHz PCI interfaces. This device attaches to the SAC via an
Expander bus.
Provides the primary control and data interface for two independent
32-bit, 33-MHz PCI interfaces. These two 32-bit interfaces may
operate together to produce a single 64-bit, 33-MHz interface via a
configuration option. This device attaches to the SAC via an Expander
bus.
The IFB is a multi-function PCI device implementing a PCI-to-LPC
bridge function, a PCI IDE function, a Universal Serial Bus Host/Hub
function, an SMBus Interface function, Power Management function
and the Firmware Hub interface.
The FWH component interfaces to the IFB component and provides
firmware storage and security features. Further FWH information can
be found at http://developer.intel.com/design/chip sets/datasheets or by
ordering document 290658.
The PID is an interrupt controller that provides interrupt steering
functions. The PID contains the logic required to support 8259A mode,
APIC mode, and SAPIC mode interrupt controller operations. The PID
interfaces include a PCI bus interface, an APIC bus interface, a serial
IRQ interface, and an interrupt input interface.
1-2 Intel® 460GX Chipset Software Develop er ’s Manual
1.2 Product Features
Introduction
• High performance hardware base d on IA-64
architecture
—4.2 GB/s memory bandwidth can
simultaneously support both the full system
bus and the full I/O bus bandwidths
—Architectural support for 64 MB to 64 GB of
SDRAM
—Support for up to four bridge chips that
interface to the 82461GX (SAC) through
four Expander channels, each 30 bits wide
and providing 533 MB /s peak bandwidth
—AGP 4X compatible, via the 82465GX
(GXB) and two Expander channels running
at 266 MHz totaling 1 GB/s peak bandwidth
—Support for two 64-bit, 66-MHz PCI buses
using one 82466GX (WXB) component per
Expander channel
—Support for two independent 32-bit, 33-MHz
PCI buses or one 64-bit, 33-MHz PCI bus via
the 82467GX (PXB) pe r Expander channel
—Data streaming support between Expanders
and DRAM, up to 533 MB/s per Expander
channel
• Extensi ve RAS features for mission-critical
needs
—ECC protection on the system bus data
signals
—Memory ECC with single-bit error
correction, double and nibble error detect ion
—Address and data flows protected by parity
throughout ch ipset
—ECC bits in DRAM accessible by diagnostics
—Fault recording of multiple errors; sticky
through reset
—JT AG TAP port for debug and boundary scan
capability
—I2C slave interface for viewing and
modifying specific error and configurati on
registers
—Bus, memory and I/O performance counters
—Support of ACPI/DMI functions (support is
provided in the IFB)
• High bandwidth system bus for multiprocessor
scalability
—Support of the Intel® Itanium™ processor
64-bit dat a bus
—Full support for 4-way multiprocessing
—266 MHz data bus frequency
—Cache lin e size of 64 bytes
—Enhanced defer feature for out-of-order data
delivery using IDS#
—AGTL+ bus driver technology
• Features to support flexible platform
environments
—Hardware compatible with IA-32 binaries
—AGP address space up to 32 GB supported
—Support for Auto Detection of SDRAM
memory type and mixed memory sizes
allowed between r ows
—Supports 16-, 64- , 128- and 256-Mbit
DRAM devices
—Full support for the PCI Configuration Space
Enable (CSE) protocol to devices on all
Expander channels
—WXB supports 3.3 volt PCI bus operation
(supports universal and 3.3 volt PCI cards)
and has an Integrated Hot-Plug Controller**
—PCI Rev. 2.2 compliant on the WXB and
PXB
—GXB supports fast write s a nd 1x, 2x and 4x
data rates
—1 MB or greater of firmware storage
provided by the 8280 2 AC ( FWH)
—Interrupt controller, bus-mastering IDE and
Universal Serial Bus supported by the
82468GX (IFB)
—Support of 8259 A mod e , APIC mo d e an d
SAPIC mode interru pts via the
UPD55566S1-016 (PI D ) provided by NEC*
**Based on technology licensed from Compaq Computer Corp.
1.3 Itanium™ Processor System Bus Support
• Full support for the Itanium processor system bus.
— 64-bit data bus.
— 266 MHz data bus frequency.
— Cache line size of 64 bytes.
— Supports SAPIC interrupt protocol.
• Full support for 4-way multiprocessing.
• Parity protection on address and control signals, ECC protection on the data signals.
• GTL+ bus driver technology.
Intel® 460GX Chipset Software Developer’s Manual 1-3
Introduction
1.4 DRAM Interface Support
• SDRAM 3.3 volt, 168-pin DIMM’s are the only memory type supported.
• Support for 64 MB to 64 GB of DRAM.
• Minimum memory size is 64 MB using 16 MB DIMM’s.
• Minimum incremental size is 64 MB using 16 MB DIMM’s.
• Maximum memory size is 16 GB using 128 MB DIMM’s.
• Maximum memory size is 64 GB using 1 GB DIMM’s.
• Only 3.3 volt memory is supported.
• Support for Auto Detection of SDRAM Memory Type.
• Supports 16, 64, 128 and 256 Mbit DRAM devices.
• Mixed memory sizes allowed between rows.
• Staggered CAS-before-RAS refresh (standard SDRAM refresh).
• ECC with single-bit error correction, double and nibble error detection.
• Extensive processor-to-Memory and PCI-to-Memory write data buffering, thus minimizing
the interference of writes on read latency.
1.5 I/O Support
• 4 Expander ports, each 30 bits wide and providing 533 MB/s peak bandwidth.
• Each Expander bus supports a single PXB or WXB. Two Expander busses can be configured
to support a GXB.
• Full support for the PCI Configuration Space Enable (CSE) protocol to devices on all
Expander ports.
• Data streaming support between Expanders and DRAM, up to 533 MB/s per Expander port.
• All outbound memory and I/O reads (except locked reads) are deferred.
• All outbound memory space writes are posted. Outbound I/O space writes are optionally
posted (unless targeting an address with side effects, in which case they are deferred).
• All inbound memory reads are delayed.
• All inbound memory space writes are posted.
• Supports concurrent processor and I/O initiated transactions to main memory.
• Maintains coherency with processors by snooping all inbound transactions to the system bus.
• Supports non-coherent traffic (for AGP), with a direct path to memory bypassing the system
bus.
1.5.1 PXB Features
• Can be configured to provide two independent 32 bit, 33 MHz PCI buses or one 64 bit, 33
MHz PCI bus.
• PCI Rev. 2.2, 5V tolerant (PXB drives 3.3 volts, but is 5.0 volt tolerant).
1-4 Intel® 460GX Chipset Software Develop er ’s Manual
• Parity protection on all PCI signals.
• Data collection & write assembly.
— Combines back-to-back sequential processor-to-PCI memory writes to PCI burst writes.
— Processor to PCI write assembly of full/partial line writes.
• T wo outbo und read requ ests containing a total of two cach e lines of read data fo r each PCI bus.
• Supports six outbound write requests containing a total of three cache lines of write data for
each 32 bit PCI bus. Supports 12 outbound write requests containing a total of six cache lines
of write data for a 64 bit PCI bus.
• Supports two delayed inbound read requests.
• Supports the I/O and Firmware Bridge (IFB).
• Supports either internal or external arbitration, allowing additional bus masters, on the PCI
bus.
1.5.2 WXB Features
• Support for two 64 bit, 66 MHz PCI busses.
Introduction
• 3.3 Volt PCI bus operation (supports Universal and 3.3 Volt PCI cards).
• PCI Specification, Revision 2.2.
• Integrated Hot-Plug controller.
1.5.3 GXB Features
• The GXB is AGP and AGP 4X mode compatible, nominal 66 MHz, 266 MHz, 1 GB/s peak
bandwidth.
• The GXB supports pipelined operation or sideband signals on AGP 4X mode bus.
• AGP address space of 1 GB or 256 MB supported. Also supports 32 GB of GART window, if
4 MB pages are used.
• Supports Fast Writes and 1x, 2x and 4x data rates.
1.6 RAS Features
• ECC coverage of system data bus using the Itanium™ processor SEC/DED ECC code.
Memory is protected using a SEC/DED code which also provides nibble detection capabilities
of 4 bits. All control and address signals are parity protected. Local control buses are parity
protected. The Expander is covered by parity.
• Data flows protected by parity throughout chipset.
• ECC bits in DRAM accessible by diagnostics.
• Fault recording of multiple errors; sticky through reset, but NOT through power-down.
• Memory scrubbing implemented in hardware.
• Boundary test capability through JTAG.
• JTAG TAP port for debug.
Intel® 460GX Chipset Software Developer’s Manual 1-5
Introduction
• I2C Slave Interface will allow viewing and modifying of specific error and configuration
registers.
1.7 Other Platform Components
These 460GX devices provide access to flash space, interrupt collection and legacy features.
1.7.1 I/O & Firmware Bridge (IFB)
The 460GX chipset is designed to work with the IFB south bridge. As part of this support, the PXB
includes an internal PCI arbiter as well as support for an external PCI arbiter. The IFB consists of
an 8259C Interrupt controller, a bus-mastering IDE interface, and a Universal Serial Bus interface.
Devices using IFB are limited to a 32 bit addressing space available for DMA, not the full 44 bits
supported by the Itanium™ processor.
1.7.2 Programmable Interrupt Device (PID)
The PID is a PCI device that gathers interrupts and delivers them from the PCI bus to the system
bus using the SAPIC inte rr upt p rotocol. The interrupt will be presen te d t o o ne o f the p roces s ors on
the bus for servicing. A 460GX chipset based platform requires at least one PID located on the
compatibility PCI bus. The compatibility PID will hands hake with the IFB befo re delivering a
south bridge/compatibility device interrupt. The same PID may als o be used to deliver some
portion of the PCI based interrupts.
The system implementor can choose how many PIDs are used in the platform. If enough interrupt
lines are shared, there need be only one PID in the system; all interrupts in the system would then
be routed to that PID. Each P ID has en ough i nte rrupt i nputs to handl e dedicated interr upts fr om the
cards on two PCI buses. Therefore, using one PID per PXB provides a high performance solution
with minimum routing between PCI buses.
1.8 Reference Documents
In addition to this document, the reader should be familiar with the following reference do cuments:
• Intel® 460GX Chipset Datasheet
(Document Number: 248703)
• Intel® Itanium™ Processor Hardware Developer’s Manual
(Document Number: 248701)
• Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
(Document Number: 245481)
• Intel® 82460GX Chipset OLGA1 Package, Manufacturing, Mechanical, and Thermal Design
Guide
• PCI Local Bus Specification, Rev 2.2
(http://www.pcisig.com/)
• Accelerated Graphics Port Interface Specification
(http://www.intel.com/technology/agp/agp_index.htm)
1-6 Intel® 460GX Chipset Software Develop er ’s Manual
• JTAG IEEE 1149.1 Specification
(http://www.ieee.com)
• Universal Serial Bus Specification
(http://www.usb.org)
• System Management Bus Specification, Rev. 1.0
• Low Pin Count (LPC) Interface Specification, Rev 1.0
Note: Contact your Intel representative for the latest revision of the documents without document
numbers.
1.9 Revision History
Date Description
June 2001 Initial release.
Introduction
Intel® 460GX Chipset Software Developer’s Manual 1-7
Introduction
1-8 Intel® 460GX Chipset Software Develop er ’s Manual
Register Descriptions 2
The 460GX chipset has both memory mapped and PCI configuration space mapped registers. The
460GX chipset supports access mechanism #1 as defined in the PCI specification. Two 32-bit
register locations (CONFIG_ADDRESS and CONFIG_DATA) are defined in the Itanium
processor’s I/O space; I/O accesses to these registers are translated by the 460GX chipset into
appropriate PCI configuration cycles.
To access a configuration register in the 460GX chipset (or any other I/O device), software first
writes a value to the CONFIG_ADDRESS location consisting of the bus number, Device Number,
function number and register number. These writes are claimed and saved by the 460GX chipset.
Subsequent reads or writes to the CONFIG_DATA location result in the 460GX chipset using the
information stored in CONFIG_ADDRESS to deliver a PCI configuration read or write cycle to
the appropriate address on the appropriate PCI bus.
Upon reset, the 460GX chipset sets its internal configuration regist ers to predetermined default
states, representing the minimum feature set required to successfully bring up the system. It is
expected that the firmware will properly determine and program the optimal configuration settings.
The 460GX chipset implements a PCI-compatible configuration space for each PCI bus under the
PXBs, for each AGP bus under the GXB, and for each 460GX chipset component. Each
configuration space provides hardwired device identification, address range registers, operation
control registers, status and error regis ters. This chap ter describe s how the con figuration sp aces are
accessed, then provides detailed descriptions of each register.
2.1 Access Mechanism
The PCI specification defines two bus cycles to access PCI configuration space: Configuration
Read and Configuration W rite. While memory and I/O spaces are supp orted by the micro processor ,
configuration space is not directly supported. The PCI specification defines two mechanisms to
access configuration space, Mechanism #1 and Mechanism #2. The 460GX chipset supports only
Mechanism #1.
Mechanism #1 defines two I/O-space locations: an address register (CONFIG_ADDRESS) at
location 0CF8h, and a data register (CONFIG_DATA) at location 0CFCh. Dword I/O W rites to the
configuration address are latched and held; they specify the PCI Bus Number, Device Number
within the bus, and Register Number within the device. Subsequent I/O reads and writes to the
configuration data location cause a configuration space access th e register specified by the add ress
stored in the configuration address location.
Note: The AGP bus under the GXB looks like a standard PCI bus for configuration purposes. The term
xXB refers to the PXB, WXB, or GXB. In general, any reference to an access to PCI bus includes
accesses to an AGP bus.
Configuration space accesses are processed as follows:
• If the SAC detects that the I/O request is a configuration acces s to its own con figuration space,
it will service that request entirely within the SAC or the other chipset comp onents. Reads
result in data being returned to the system bus.
• If the SAC detects that the I/O request is a configuration access to a xXB configuration space,
it will forward the request to the appropriate xXB for servicing. The request is not f orwar ded
Intel® 460GX Chipset Software Developer’s Manual 2-1
Register Descriptions
to a PCI bus. Reads result in data being returned by the xXB through the SAC to the system
bus.
• Otherwise, the access is forwarded to the xXB to be placed on the PCI bus (or AGP bus) as a
Configuration Read or Configuration Write cycle. Reads will result in data being returned
through the xXB and SAC back to the system bus, just as in normal Outbound Read
operations.
2.2 Access Restrictions
The 460GX chipset supports PCI configuration space access using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification.
The 460GX chipset internal registers (both I/O Mapped and Configu ration registers) ar e accessible
by the Host CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit)
quantities, with the exception of CONFIG_ADDRESS which can only be accessed as a Dword. All
multi-byte numeric fields use “little-endian” ordering (i.e. lower addresses contain the least
significant parts of the field).
2.2.1 Partitioning
Each SAC, SDC, MAC, PXB, WXB, GXB, each AGP bus below an GXB, and each PCI bus below
an PXB or WXB, has an independent configuration space. None of the regis ters are shared between
the spaces; that is, the SAC, and each PCI bus in the PXB, have separate control and status
registers.
Configuration registers are accessed using an “address” comprised of the PCI Bus Number, the
Device Number within the bus, and the Register Number within the Device.
Accesses to devices on Bus #0 and Bus #(CBN) are serviced by the 460GX chipset depending on
their device number. Device 10h on Bus #0 is mapped to the SAC; it contains the programmable
Chipset Bus Number. All other chipset devices reside on bus CBN.
The DEVNPRES register is used to determine which chipset devices are present; see Table 2-1 for
mapping information.
Table 2-1. Device Mapping on Bus CBN
No. Device No. Device
00h SAC 10h Expander 0, Bus a
01h SAC 11h Expander 0, Bus b
02h reserved 12h Expander 1, Bus a
03h reserved 13h Expander 1, Bus b
04h SDC 14h Expander 2, Bus a
05h Memory Card A 15h Expander 2, Bus b
06h Memory Card B 16h Expander 3, Bus a
07h reserved 17h Expander 3, Bus b
08h-0Fh reserved 18h-1Fh reserved
a. This is the compatibility bus (where the boot vector is always directed).
a
Configuration registers located in the SDC are accessed over the private data bus. The SAC
translates CF8/CFC accesses to SDC registers into configuration commands over the PDB.
Configuration registers located on the memory boards are accessed over the I2C port. The SAC
2-2 Intel® 460GX Chipset Software Develop er ’s Manual
translates CF8/CFC accesses to the MAC registers into read/write commands over the I2C port.
The SAC also contains an IIADR pointer register that can be used in conjunction with a CF8/CFC
access to generate I2C commands to generic I2C devices on the memory boards.
2.2.2 Register Attributes
Registers have designated “access attributes”, with the following definitions:
Read Only Writes to this register have no effect.
Read/Write Data may be read from and written to this register. Selected bits in the register may
be designated as “hardwired” or “read-only”; such bits are not affected by data writes
to the register.
Read/Clear Data may be read from the register. A data write operates strictly as a clear: a “1”-bit
in the data field clears the corresponding bit in the register , while a “0”-bit in the data
field has no effect on the corresponding bit in the register . Selected bits in the register
may be designated as “hardwired” or “read-only”; such bits are not af fected by data
writes to the register.
Sticky Data in this register remains valid and unchanged, du ring and following a hard reset.
Typically, these registers contain special configuration information or error logs.
Register Descriptions
2.2.3 Reserved Bits Defined in Registers
Most 460GX chipset registers described in this s ection contain r eserved bits. Th e PCI specifica tion
requires that software correctly handle reserved fields, as follows. On reads, software must use
appropriate masks to extract the defined bits and not rely on reserved bits being any particular
value. On writes, software must ensure that the values of reserved bit pos itions are p rese rved. That
is, the values of reserved bit positions must first be read, merged with the new values for other bit
positions and then written back. Note the software does not need to perform read, merge, write
operation for the CONFIG_ADDRESS register.
2.2.4 Reserved or Undefined Register Locations
In addition to reserved bits within a register, the 460GX chipset contains address locations in the
PCI configuration space that are marked “Reserved” or are simply undefined. Several of the
460GX chipset devices are multi-function devices; all registers in the unused functions are
considered “Reserved”. Reserved registers can be 8-, 16-, or 32-bit in size. The PCI specification
requires that the 460GX chipset respond to accesses to these address locations by completing the
host cycle. Reserved register locations must be treated by software the same as reserved fields are
treated: software can not rely on reads returning any particular value, and must not attempt to
change the value returned when read.
2.2.5 Default Upon Reset
Upon reset, the 460GX chipset sets its internal configuration registers to pr edeterm in e d default
states. The default state represents the minimum functionality feature set required to successfully
bring up the system. Hence, it does not represent the optimal system configuration. It is the
responsibility of the system initialization software (firmware) to properly deter m ine the DRAM
configurations, operating parameters and optional system features that are applicable, and to
program the 460GX chipset registers accordingly.
Intel® 460GX Chipset Software Developer’s Manual 2-3
Register Descriptions
2.2.6 Consistency
There are a number of registers that are repeated in both the SAC and xXB/PCI spaces. It is
software’s responsibility to insure that these regis ters are progr a mmed in a consistent fashion.
Failure to insure consistency can produce indeterminate resu lts. See the Initialization Chapter for
an overview on initializing all chipset components.
When the address decode ranges of 460GX chipset devices are being updated, no other bus traffic
is allowed over the address ranges being affected by the update. This means that the code that
updates initial configuration must be executing from a location that will not be affected by the
update. Furthermore in a multiprocessor system, precautions should be taken to assure that only
one CPU is accessing configuration space at a time.
2.2.7 GART Programming Region
The region starting at FE20_0000h is used for programming the GARTs. This region is accessible
either by the processor or PCI. See Section 7.2.1 for GART programming details
2.3 I/O Mapped Registers
The 460GX chipset contains two registers that reside in the CPU I/O address space: the
Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible through the
Configuration Data window. The following sections define the fields within the
CONFIG_ADDRESS and CONFIG_DATA registers. The 460GX chipset’s device ID mapping
into the CONFIG_ADDRESS definition is shown in Table 2-1.
2.3.1 CONFIG_ADDRESS: Configuration Address Register
I/O Address: CF8h [Dword] Size: 32 bits
Default Value: 00000000h Attribute: Read/Write
Sticky: No Locked: No
CONFIG_ADDRESS is a 32 bit register accessed only when referenced as a Dword. A Byte or
Word reference will “pass through” the Configuration Add ress R egi st er ont o t h e PC I b us as an I/ O
cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function
Number, and Register Number for which a subsequent configuration access is intended.
Bits
31 Configuration Enable(CFGE).
30:24 reserved (0)
23:16 Bus Number.
Description
When this bit is set to 1 accesses to PCI configuration space are enabled. If this bit is reset
to 0 accesses to PCI configuration space are disabled.
When the Bus Number is programmed to match the Chipset Bus Numb er (CBN), the
target of the Configuration Cycle is the 460GX chipset. If the Bus Number is not CBN,
the destination and type of acce ss is determined by the Bus Numb er and Subordinate Bus
Number of each PCI port in each PXB. A type 0 access is generated on the appropriate
PCI bus if one of the PXB port’s bus number is matched. Otherwise, a type 1
configuration cycle is generated on the appropriate PCI bus below the PXB port whose
2-4 Intel® 460GX Chipset Software Develop er ’s Manual
subordinate bus number is in that range. For a type 1 cycle, the Bus Number is mapped
to AD[23:16] during the address phase.
15:11 Device Number.
This field selects one agent on the PCI bus selected by the Bus Number. Device 16 (10h)
on Bus #0 is always reserved for programming the CBN. On the bus that the chipset is
mapped into (determined by the CBN register), Device Numbers 0-31 are reserved for
the 460GX chipset components as shown in Table 2-1. All other devices numbers are
forwarded to the selected bus.
1 0:8 Function Number.
This field is mapped to AD[10:8] during PCI configuration cycles. This allows the
configuration registers of a particular function in a multi-function device to be accessed.
7:2 Register Number.
This field selects one register within a particular Bus, Device, and Function as sp ecified
by the other fields in the Confi guration Address Register . This fi eld is mapped to AD[7:2]
during PCI configuration cycles.
1:0 reserved (0)
2.3.2 CONFIG_DATA: Configuration Data Register
I/O Address: CFCh Size: 32 bit s
Default Value: 00000000h Attribute: Read/Write
Sticky: No Locked: No
Register Descriptions
CONFIG_DATA is a 32 bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents of
CONFIG_ADDRESS.
Bits
31:0 Configuration Data Window (CDW).
Description
If bit 31 of CONFIG_ADDRESS is 1 any I/O reference that falls in the CONFIG_DATA
I/O space will be mapped to configuration space using the contents of
CONFIG_ADDRESS.
2.4 Error Handling Registers
2.4.1 SAC
2.4.1.1 SECTID: SEC ITID
Bus CBN, Device Number: 00h Function: 0
Address Offset: 80h Size: 8 bits
Default Value: 00h Attribute: Read Only/Write
Sticky: Yes Locked: No
This register is used to capture the ITID for a single bit memory ECC error. The ITID can then be
used to determine the address of the failure. To force the ITID to be cleared and re-used, write a 1
to bit 6. This register is set anytime that the SEC bit is sent from the SDC to the SAC on a ’Retire
ITID’ command.
Clear, Read/Write
Intel® 460GX Chipset Software Developer’s Manual 2-5
Register Descriptions
Bits Description
7 Disable
This bit can be written by software. When set, the ITID is retired immediately and not
captured. Therefore there can be no checking of the address. See Section 6 for the usage
of this bit.
6 Valid
If set then the ITID in bits 5:0 is valid and shows the address of a single-bit memory error.
Writing a 1 to this bit will clear the ITID and reset the valid bit.
5:0 ITID
The ITID of the SEC error. These bits are read-only.
2.4.1.2 DEDTID: DED ITID
Bus CBN, Device Number: 00h Function: 0
Address Offset: 81h Size: 8 bits
Default Value: 00h Attribute: Read Only/Write
Sticky: Yes Locked: No
Clear, Read/Write
This register is used to capture the ITID for a double bit memory ECC error. The ITID can then be
used to determine the address of the failure. To force the ITID to be cleared and re-used, write a 1
to bit 6. This register is set anytime that the DED bit is sent from the SDC to the SAC on a ‘Retire
ITID’ command.
Bits
7 Disable
6 Valid
5:0 ITID
Description
This bit can be written by software. When set, the ITID is retired immediately and not
captured. Therefore there can be no checking of the address. See Section 6 for the usage
of this bit.
If set then the ITID in bits 5:0 is valid and shows the address of a double-bit memory
error. Writing a 1 to this bit will clear the ITID and reset the valid bit.
The ITID of the double-bit error. These bits are read-only.
2.4.1.3 FSETID: FSE ITID
Bus CBN, Device Number: 00h Function: 0
Address Offset: 82h Size: 8 bits
Default Value: 00h Attribute: Read Only/Write
Sticky: Yes Locked: No
Clear, Read/Write
This register is used to capture the ITID for a system bus data error. The ITID can then be used to
determine the address of the failure. To force the ITID to be cleared and re-used, write a 1 to bit 6.
This register is set anytime that the ADE bit is asserted and both SEC and DED are deasserted on a
’Retire ITID’ command from the SDC to the SAC. NOTE: this reg ister is set for both processorbus errors and errors on the SAC-to-SDC data bus.
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Bits Description
7 Disable
This bit can be written by software. When set, the ITID is retired immediately and not
captured. Therefore there can be no checking of the address. See Section 6 for the usage
of this bit.
6 Valid
If set then the ITID in bits 5:0 is valid and shows the address of a system bus data error.
Writing a 1 to this bit will clear the ITID and reset the valid bit.
5:0 ITID
The ITID of the system bus error. These bits are read-only.
2.4.1.4 FERR_SAC: First Error Status Register
Bus CBN, Device Number: 00h Function: 1
Address Offset: 40h Size: 32 bits
Default Value: 000000h Attribute: Read/Write Clear
Sticky: Yes Locked: No
This register records the first error condition detected in the SAC/SDC.
Register Descriptions
Bits
31 Memory Card B Error (MBE)
30 Memory Card A Error (MAE)
29 XSERR# Asserted (XSA)
28 ‘Store-Write’ Command Underflow, card A, Stack L (SCAL)
27 ‘Store-Write’ Command Underflow, card A, Stack R (SCAR)
26 ‘Store-Write’ Command Underflow, card B, Stack L (SCBL)
25 ‘Store-Write’ Command Underflow, card B, Stack R (SCBR)
24 SDC Correctable Memory Error (SCME)
23 SDC Non-Fatal Error (SNE)
22 SDC Fatal Error (SFE)
21 ‘Completion’ Command Underflow; MAC A, Stack L (CCAL)
20 ‘Completion’ Command Underflow; MAC A, Stack R (CCAR)
19 ‘Completion’ Command Underflow; MAC B, Stack L (CCBL)
Description
Set when the memory card B signals a fatal error.
Set when the memory card A signals a fatal error.
Set when the SAC sees the signal XSERR# active.
One of these 4 is asserted when a signal is sent from the SDC to the SAC indicating write
data was sent to the MDC, and there is no outstanding write in the SAC.
Reports correctable DRAM errors (single-bit ECC errors). This bit does not mask other
bits in the FERR register from being set. It is the one exception to the rule that only one
bit in FERR may be set at a time.
Reports non-fatal errors that are uncorrectable such as double-bit ECC error, or parity
errors. This also reports a single-bit correctable error on the system bus. This bit will also
be set if there is a second cor rectable error from memo ry in the SDC, and the first one has
not been cleared by the time the second one occurs. The first correctable memory error
would have set the SCME bit, and all later correctable memory errors (until the SDC’s
error registers are cleared) are reported as SNE in the FERR or NERR.
Fatal error in SDC.
Intel® 460GX Chipset Software Developer’s Manual 2-7
Register Descriptions
18 ‘Completion’ Command Underflow; MAC B, Stack R (CCBR)
17 BERR# Observed (BER)
16 IOQ Underflow/Overflow (IUE)
15 reserved(0)
14 External XBINIT# Active. (XBE)
13 False Retirement (FRE)
12 Address above TOM (TE)
11 Illegal HITM# (IHS)
10 Unsupported ASZ[1:0]# (ASE)
9 System Bus Address Parity Error (AE)
8 System Bus Request Parity Error (RQE)
7 PDB ITID Parity Error (IPE)
6 Retirement Bus Parity Erro r (RPE)
5 Lock# Transaction With No Resources Available (LTE)
4:1 reserved(0)
0 Resource Counter Overflow/Underflow (RCE)
One of these 4 bits is set when the SAC receives a completion from the MAC and the
SAC has no outstanding transaction.
BERR# seen on the system bus. Set whenever BERR# is observed active.
Set when the IOQ is empty and the SDC sends out a signal saying it popped something
from the top of the queu e. Or set when the I OQ is 8 (or 1 when the IOQ d epth is s et to 1)
and an ADS# is seen on the bus.
Set when XBINIT# is seen active. This signal is from an Expander port or other external
agent.
Retirement from SDC that doesn’t match an outstanding ITID in the SAC.
Asserted when an address on the system bus is above TOM and not inside the I/O gap
below 4 GB.
HITM# on non-memory access.
Processor access to an address above 64 GB, so that ASZ# = 10b or 11b.
Parity error on A[36:3]#.
Parity error on REQ[4:0]#.
Parity error on the ITID bus from SDC to SAC.
Parity error on the retirement bus from the SDC to the SAC.
Set when a LOCK# transaction occurs and there are no outbound resources available in
which to place the lock.
Set if the resource counter has an underflow or overflow.
2.4.1.5 NERR_SAC: All Error Status Register
Bus CBN, Device Number: 00h Function: 1
Address Offset: 44h Size: 32 bits
Default Value: 000000h Attribute: Read/Write Clear
Sticky: Yes Locked: No
This register records all error conditions detected in the SAC/SDC.
Bits
31:0 See FERR_SAC for bit definitions.
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Description
2.4.1.6 SA_FERR: System Address on First Error
Bus CBN, Device Number: 00h Function: 1
Address Offset: 60h Size: 128 bits
Default Value: undefined after Attribute: Read Only
Sticky: Yes Locked: No
This register records and latches the address for the first system bus error detected.
Register Descriptions
Bits
127:107 Reserved (0)
106 LOCK, ’b’ phase.
105 ADS, ’b’ phase.
104 RP#, ’b’ phas e.
103:99 REQ, ’b’ phase.
98 AP1; ’b’ phase.
97 AP0; ’b’ phase.
96:64 A[35:3]#, ’b’ phase.
63:43 Reserved (0)
42 LOCK#, ’a’ phase.
41 ADS#, ’a’ phase.
40 RP# for REQa#.
39:35 REQa#.
34:33 AP[1:0]#, ’a’ phase.
32:0 Aa[35:3]#, ’a’ phase.
Description
Parity on REQa# signals.
REQa signals on error.
Address parity for failing address.
System Bus - System Address of Error.
2.4.1.7 BIUITID: BIU ITID Register
Bus CBN, Device Number: 00h Function: 1
Address Offset: 80h Size: 8 bits
Default Value: 0 Attribute: Read/Write
Sticky: No Locked: No
A write to this register causes the SAC to update the BIUDATA register with the contents of the
CAM and RAM associated with the ITID that is written into this register.
Bits
7:6 reserved (0)
5:0 ITID
Intel® 460GX Chipset Software Developer’s Manual 2-9
Description
This is the ITID that is used to address the CAM/RAM structure.
Register Descriptions
2.4.1.8 BIUDATA: BI U D ata Register
Bus CBN, Device Number: 00h Function: 1
Address Offset: 90h Size: 128 bits
Default Value: undefined Attribute: Read Only
Sticky: No Locked: No
This is the contents of the CAM concatenated with the contents of the RAM associated with the
ITID in BIUITID.
Bits
127:116 reserved(0)
115:82 Address bits [35:2].
81:76 reserved(0)
75:71 Reqa. Request phase a[4:0].
70:63 DID. The DID for the transaction.
62:55 BE. The byte enables for the transaction.
54 rese rve d (0)
53 OWN. OWN# active.
52 DPS. DPS# active.
51:49 Reqb. Request phase b bits [4:2].
48 Lock. The transaction.had LOCK# asserted.
47 LockLoad. The transaction is the first occurrence of an OB lock sequence.
46:43 Dst. The destination of the transaction.
42 ORetry. A retry due to HITO.
41:36 CMD. The command for the transaction.
35 P2P. Set for peer-to-peer transactions.
34 FEorR. The end-of-request bit from the Expander port.
33:30 FRoute. The Expander bus route.
29:22 FLEN. The length on the Expander bus.
21:12 FTID. The Expander id.
11:9 Len. The length of the transaction.
8 System Bus Retry. The transaction was retried on the bus.
7 Dfr. The transaction is deferred.
6 MEM. The target for the transaction if memory.
5 System Bus. The target for the transaction is the system bus.
4 CLINE. The transaction is for a full line.
3 Zero. If set then this is a 0-length transaction.
2:0 RS. The Response generated for the transaction by the BIU. This may not match the
Description
This is the contents of the CAM with address bits [5:2] from the RAM (bit 2 is only of
interest if the transaction came from an Expander bus).
system bus response sent, since the BIU’s response may be changed by the MIU. This
may be for a HITM# or other reasons.
Note: Note: if the P2P bit is not set, then bits [34:12] and [76] are not defined, since the transaction
originated on the system bus and not the Expander bus.
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2.4.2 SDC
2.4.2.1 SEC0_D_ FERR: Data on First Memory Card B SEC
Bus CBN, Device Number: 04h
Address Offset: 40-47h Size: 64 bits
Default Value: 0 Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the data corresponding to the first SEC detected by memory
interface 0 in the SDC.
Register Descriptions
Bits
63:0 DE - System Data of Error.
Description
2.4.2.2 SEC0_ECC_FERR: ECC on First Memory Card B SEC
Bus CBN, Device Number: 04h
Address Offset: 48h Size: 8 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the ECC checkbits corresponding to the first SEC detected by
memory interface 0 in the SDC
Bits
7:0 ECC - ECC of Error.
Description
2.4.2.3 SEC0_TXINFO_FERR: TXINFO on First Memory Card B SEC
Bus CBN, Device Number: 04h
Address Offset: 49-4Ah Size: 16 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records the ITID and failing chunk corresponding to the first SEC detected by
memory interface 0 in the SDC.
Bits
15:9 reserved(0)
8:6 DC - Data Chunk of ITID.
5:0 ITID - ITID of error.
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Description
Register Descriptions
2.4.2.4 DED0_D_FERR: Data on First Memory Card B DED
Bus CBN, Device Number: 04h
Address Offset: 50-57h Size: 64 bits
Default Value: 0 Attr ibute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the data corresponding to the first DED detected by memory
interface 0 in the SDC.
Bits
63:0 DE - System Data of Error.
Description
2.4.2.5 DED0_ECC _FERR: ECC on First Memory Card B DED
Bus CBN, Device Number: 04h
Address Offset: 58h Size: 8 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the ECC checkbits corresponding to the first SEC detected by
memory interface 0 in the SDC
Bits
7:0 ECC - ECC of Error.
Description
2.4.2.6 DED0_TXINFO_FERR: TXINFO on First Memory Card B DED
Bus CBN, Device Number: 04h
Address Offset: 59-5Ah Size: 16 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records the ITID and failing chunk corresponding to the first DED detected by
memory interface 0 in the SDC.
Bits
15:9 reserved(0)
8:6 DC - Data Chunk of ITID.
5:0 ITID - ITID of error.
Description
2.4.2.7 SEC1_D_FERR: Data on First Memory Card A SEC
Bus CBN, Device Number: 04h
Address Offset: 60-67h Size: 64 bits
Default Value: 0 Attr ibute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
2-12 Intel® 460GX Chipset Software Develop er ’s Manual
Register Descriptions
This register records and latches the data corresponding to the first SEC detected by memory
interface 1 in the SDC.
Bits
63:0 DE - System Data of Error.
Description
2.4.2.8 SEC1_ECC_FERR: ECC on First Memory Card A SEC
Bus CBN, Device Number: 04h
Address Offset: 68h Size: 8 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the ECC checkbits corresponding to the first SEC detected by
memory interface 1 in the SDC.
Bits
7:0 ECC - ECC of Error.
Description
2.4.2.9 SEC1_TXINFO_FERR: TXINFO on First Memory Card A SEC
Bus CBN, Device Number: 04h
Address Offset: 69-6Ah Size: 16 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records the ITID and failing chunk corresponding to the first SEC detected by
memory interface 1 in the SDC.
Bits
15:9 reserved(0)
8:6 DC - Data Chunk of error.
5:0 ITID - ITID of error.
Description
2.4.2.10 DED1_D_FERR: Data on First Memory Card A DED
Bus CBN, Device Number: 04h
Address Offset: 70-77h Size: 64 bits
Default Value: 0 Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the data corresponding to the first DED detected by memory
interface 1 in the SDC.
Bits
63:0 DE - System Data of Error.
Description
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Register Descriptions
2.4.2.11 DED1_ECC _FERR: ECC on First Memory Card A DED
Bus CBN, Device Number: 04h
Address Offset: 78h Size: 8 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the ECC checkbits corresponding to the first DED detected by
memory interface 0 in the SDC.
Bits
7:0 ECC - ECC of Error.
Description
2.4.2.12 DED1_TXINFO_FERR: TXINFO on First Memory Card A DED
Bus CBN, Device Number: 04h
Address Offset: 79-7Ah Size: 16 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records the ITID and failing chunk corresponding to the first DED detected by
memory interface 1 in the SDC.
Bits
15:9 reserved(0)
8:6 DC - Data Chunk of ITID.
5:0 ITID - ITID of error.
Description
2.4.2.13 SDC_FERR: First Error Status Register
Bus CBN, Device Number: 04h
Address Offset: 80-83h Size: 32 bits
Default Value: 0000h Attribute: Read/Write to Clear
This register records the first error condition detected in the SDC. Writing a ’1’ to this register will
clear the bit in both SDC_FERR and the same bit in SDC_NERR.
Bits
31 Simultaneous S/W write-one-to-clear and H/W error detected in the same cycle. This bit
30 PDB Receive Length Error (RLE)
29 DRDY# Protocol Error (FS2)
28 Write Data Protocol Error (FS1)
27 LEN# Protocol Error (FS0)
2-14 Intel® 460GX Chipset Software Develop er ’s Manual
Description
will only be set if another bit is also set. This implies that the ERROR>_<TYPE>_FERR
data registers associated with the other asserted bit contain stale data.
Private Bus receive length error
Asserted when a protocol error is found involving DRDY#, SBUSY# and DBUSY#.
Asserted on write protocol errors.
Asserted on mismatches of LEN# field and actual data transmitted.
26 ’Forward’ Overlapping ’Forward’; Card A (FWMDI1)
Indicates FWMDI sampled asserted while a store transaction is in progress
25 ’Load’ Overlapping ’Load’; Card A (LRMDI1)
Indicates LRMDI sampled asserted while a store transaction is in progress
24 ’Load’ Overlapping ’Forward’; Card A (WrRd1)
Memory interface 1 detected simultaneous read and write operation. Write and Read
collision.
23 ’Forward’ Overlapping ’Load’; Card A (RdWr1)
Memory interface 1 detected simultaneous read and write operation. Read and write
collision.
22 ’Forward’ Underflow; Card A Right Stack Error (FR1)
Memory interface 0 received Forward right Bank without corresponding S tore command
21 ’Forward’ Underflow; Card A Left Stack Error (FL1)
Memory interface received Forward left Bank without corresponding Store command
20 ’Accept Underflow’; Card A (AE1)
Memory interface 0 received data without corresponding Accept command
19 ’Forward’ Overlapping ’Forward’; Card B (FWMDI0)
Indicates FWMDI sampled asserted while a store transaction is in progress
18 ’Load’ Overlapping ’Load’; Card B (LRMDI0)
Indicates LRMDI sampled asserted while a store transaction is in progress
17 ’Load’ Overlapping ’Forward’; Card B (WrRd0)
Memory interface 1 detected simultaneous read and write operation. Write and Read
collision.
16 ’Forward’ Overlapping ’Load’; Card B (RdWr0)
Memory interface 1 detected simultaneous read and write operation. Read and write
collision.
15 ’Forward’ Underflow; Card B Right Stack Error (FR0)
Memory interface 0 received Forward right Bank without corresponding S tore command
14 ’Forward’ Underflow; Card B Left Stack Error (FL0)
Memory interface received Forward left Bank without corresponding Store command
13 ’Accept’ Underflow; Card B (AE0)
Memory interface 0 received data without corresponding Accept command
12 Configuration Information Parity Error (CIE)
Data buffer detected data parity while reading config address or data from SDC RAM.
11 Response Bus Transmission Error (RTE)
Indicates that the SDCRSP bus detected a transmission error.
10 PDB - ITID Parity Error (IPE)
Look in ITID_FERR Register to isolate.
9 PDB - Command Parity Error (CPE)
Look in CMD_FERR Register to isolate.
8 PDB Byte Enable Parity Error (BPE)
Parity error on the Byte-enables from the SAC.
7 SDC Data Buffer RAM Parity Error (RPE)
SDC detected bad parity on good data stored in its data buffer. Indicates potential RAM
cell disturbance due to alpha or cosmic hit. All four data port map to this bit.
6 PDB - Data Parity Error (DPE)
Parity Error Detected on transfer of Data from SAC to SDC.
Register Descriptions
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Register Descriptions
5 System Bus Double Bit Error (DEDF)
ECC Double Bit Error Detected on system bus.
4 System Bus Single Bit Error (SECF)
ECC Single Bit Error Detected on system bus.
3 SDC Card A Double Bit Error (DED1)
ECC Double Bit Error Detected from Memory Card A.
2 SDC Card A Single Bit Error (SEC1)
ECC Single Bit Error Detected from Memory Card A.
1 SDC Card B Double Bit Error (DED0)
ECC Double Bit Error Detected from Memory Card B.
0 SDC Card B Single Bit Error (SEC0)
ECC Single Bit Error Detected from Memory Card B.
2.4.2.14 SDC_NERR: SDC Next Error Status Register
Bus CBN, Device Number: 04h
Address Offset: 84-87h Size: 32 bits
Default Value: 0000h Attribute: Read/Write to Clear
This register records the next error status within the SDC. Writing a ’1’ to this register will clear
the bit in both SDC_NERR and the same bit in SDC_FERR.
Bits
31:0 See SDC_FERR for bit definitions.
Description
2.4.2.15 PCMD_FERR: Command on First PCMD Parity Error
Bus CBN, Device Number: 04h
Address Offset: 88-8Bh Size: 32 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the data associated with the first parity error detected on the
PCMD bus.
Bits
31:19 reserved(0)
18 If set then the error was detected on the 1
17 Parity of Error
16:0 PCMD - Private Data Command value of Error.
Description
st
half of the double–pumped transfer.
Otherwise, these fields contain the information from the 2
transfer.
nd
half of the double-pumped
2.4.2.16 PITID_FERR: Data on First PITID Parity Error
Bus CBN, Device Number: 04h
Address Offset: 8Ch Size: 8 bits
Default Value: 0h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
2-16 Intel® 460GX Chipset Software Develop er ’s Manual
Register Descriptions
This register records and latches the data associated with the first parity error detected on the
PITID bus.
Bits
7 If set then the error was detected on the 1st half of the double-pumped transf er. Otherwise,
6 Parity of Error
5:0 PITID - Private ITID bus value of Error.
Description
these fields contain the information from the 2
nd
half of the double-pumped transfer.
2.4.2.17 SDCRSP_FERR: Response on First SDCRSP Error
Bus CBN, Device Number: 04h
Address Offset: 8Dh Size: 8 bits
Default Value: 0h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the data and inverted data associated with the first transmission
error detected on the SDCRSP bus.
Bits
7:4 Response Bus for 2nd half of double–pumped transfer.
3:0 Response Bus for 1
Description
st
half of double–pumped transfer.
2.4.2.18 DPBRLE_FERR: Private Data Bus Receive Length Error
Bus CBN, Device Number: 04h
Address Offset: 8Eh Size: 8 bits
Default Value: 0h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register indicates that the amount of data transferred from the SAC to the SDC for a given
transfer did not match the expected transfer length.
Bits
7:3 reserved(0)
2 Data packet longer than expected (LDP)
1 Data packet shorter than expected (SDP)
0 No data packet shipped as expected (NDP)
Description
2.4.2.19 ECCMSK0: ECC Mask Register - Card B
Bus CBN, Device Number: 04h
Address Offset: C8h Size: 8 bits
Default Value: 00h Attribute: Read/Write
This register is used to test the ECC error detection logic in the memory subsystem for memory
card 0. To test, this register is w rit ten with a masking function. All subsequent writes into memory
will store a masked version of the computed ECC . Subsequent reads of memory lo cations written
Intel® 460GX Chipset Software Developer’s Manual 2-17
Register Descriptions
while masked will return an invalid ECC code. To disable testing, the mask value is left at 0h (the
default). The mask is a bit-wise XOR with the computed ECC.
Bits
7:0 ECC Generation Mask - For 64 bits of dat a.
Description
2.4.2.20 ECCMSK1: ECC Mask Register - Card A
Bus CBN, Device Number: 04h
Address Offset: C9h Size: 8 bits
Default Value: 00h Attribute: Read/Write
This register is used to test the ECC error detection logic in the memory subsystem for memory
card 1. To test, this register is written with a masking function. All subsequent writes into memory
will store a masked version of the computed EC C. Subsequent reads of memor y locations written
while masked will return an invalid ECC code. To disable testing, the mask value is left at 0h (the
default). The mask is a bit-wise XOR with the computed ECC.
Bits
7:0 ECC Generation Mask - For 64 bits of dat a.
Description
2.4.2.21 ECCMSKF: ECC Mask Regi ster
Bus CBN, Device Number: 04h
Address Offset: CAh Size: 8 bits
Default Value: 00h Attribute: Read/Write
This register is used to test the ECC error detection logic of the host processor bu s. To test, this
register is written with a masking function. All subsequent processo r reads will received a mask ed
version of ECC code. To disable testing, the mask value is left at 0h (the default). The mask is a
bit-wise XOR with the computed ECC.
Bits
7:0 ECC Generation Mask - For 64 bits of dat a.
Description
2.4.2.22 ParMskP: PB Pari ty Mask and IB Correction Enabl e Register
Bus CBN, Device Number: 04h
Address Offset: CBh Size: 8 bits
Default Value: 00h Attribute: Read/Write
The first 4 bits of this register are used to test the data parity error detection logic of the private bus.
To test, bits 3:0 are written with a masking function. All subsequent private bus reads will receive a
masked version of double byte parity. To disable testing, the mask value is left at 0h (the default).
The mask is a bit-wise XOR with the computed parity.
Bits 7:4 are used to enable ECC or parity checking for the different busses. Note that the SDC
defaults to no parity or ECC checking at power-on.
Bits
7 Private Bus parity detection enable.
6 Front Side Bus ECC correction/detection enable.
2-18 Intel® 460GX Chipset Software Develop er ’s Manual
Description
5 Memory Bus A ECC correction/detection enable.
4 Memory Bus B ECC correction/detection enable.
3:0 Double byte parity mask for 128 bits of data.
2.4.2.23 PVD_D_FERR: Data on First PVD Parity Error
Bus CBN, Device Number: 04h
Address Offset: D0-D7h Size: 64 bits
Default Value: 0 Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the data associated with the first parity error detected on the PVD
bus.
Register Descriptions
Bits
63:0 PVD - Private Data Bus data.
Description
2.4.2.24 PVD_PAR_FERR: Parity on First PVD Parity Error
Bus CBN, Device Number: 04h
Address Offset: D8h Size: 8 bits
Default Value: 0 Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the data associated with the first parity error detected on the PVD
bus.
Bits
7:4 reserved(0)
3:0 Double–byte parity of error
Description
2.4.2.25 PVD_TXINFO_FERR: TXINFO on First PVD Parity Error
Bus CBN, Device Number: 04h
Address Offset: D9-DAh Size: 16 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records the ITID and failing chunk corresponding to the first double-byte parity
detected by private bus interface in the SDC.
Bits
15:9 reserved(0)
8:6 DC - Data Chunk of ITID.
5:0 ITID - ITID of error.
Intel® 460GX Chipset Software Developer’s Manual 2-19
Description
Register Descriptions
2.4.2.26 SECF_D_FERR: Data on First System Bus SEC
Bus CBN, Device Number: 04h
Address Offset: E0-E7h Size: 64 bits
Default Value: 0 Attr ibute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the data corresponding to the first SEC detected by system bus
interface in the SDC.
Bits
63:0 DE - System Data of Error.
Description
2.4.2.27 SECF_ECC_FERR: ECC on First System Bus SEC
Bus CBN, Device Number: 04h
Address Offset: E8h Size: 8 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the ECC checkbits corresponding to the first SEC detected by
system bus interface in the SDC.
Bits
7:0 ECC - ECC of Error.
Description
2.4.2.28 SECF_TXINFO_FERR: TXINFO on First System Bus SEC
Bus CBN, Device Number: 04h
Address Offset: E9-EAh Size: 16 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records the ITID and failing chunk corresponding to the first SEC detected by system
bus interface in the SDC.
Bits
15:9 reserved(0)
8:6 DC - Data Chunk of error.
5:0 ITID - ITID of error.
Description
2.4.2.29 DEDF_D_FERR: Data on First System Bus DED
Bus CBN, Device Number: 04h
Address Offset: F0-F7h Size: 64 bits
Default Value: 0 Attr ibute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
2-20 Intel® 460GX Chipset Software Develop er ’s Manual
Register Descriptions
This register records and latches the data corresponding to the first DED detected by system bus
interface in the SDC.
Bits
63:0 DE - System Data of Error.
Description
2.4.2.30 DEDF_ECC_FERR: ECC on First System Bus DED
Bus CBN, Device Number: 04h
Address Offset: F8h Size: 8 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the ECC checkbits corresponding to the first DED detected by
system bus interface in the SDC.
Bits
7:0 ECC - ECC of Error.
Description
2.4.2.31 DEDF_TXINFO_FERR: TXINFO on First System Bus DED
Bus CBN, Device Number: 04h
Address Offset: F9-FAh Size: 16 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records the ITID and failing chun k cor res pon ding to the fir st DED detected by sys tem
bus interface in the SDC.
Bits
15:9 reserved(0)
8:6 DC - Data Chunk of ITID.
5:0 ITID - ITID of error.
Description
2.4.3 MAC
2.4.3.1 FERR_MAC: First Error Status Register
Bus CBN, Device Number: 05h,06h Function Number: 00h,01h
Address Offset: 98h Size: 8 bits
Default Value: 00h Attribute: Read
This register records the first error condition detected in the MAC.
Bits
7:2 reserved(0)
1 Que-Overflow Error
Description
Signals that the MAC received too many commands from the SAC.
Intel® 460GX Chipset Software Developer’s Manual 2-21
Register Descriptions
0 Parity Error - CMND
Parity Error Detected on SAC-MAC CMND Bus. Look in CMND_FERR Register to
isolate. When the error is detected, the MAC will complete those operations which have
a RAS pending, and stop. No new RAS cycles will be issued after the parity error and that
card is effectively dead.
2.4.3.2 CMND_FERR: Command on First Error
Bus CBN, Device Number: 05h,06h Functi on Number: 00h,01h
Address Offset: 9Ch Size: 24 bits
Default Value: 0000h Attribute: Read
This register records and latches the data on the SAC-MAC Command Bus for the first error
detected.
Bits
23:22 reserved (0)
21:19 Row address [2:0]
18:17 Command [1:0]
16:0 MA[16:0]
Description
2.4.4 PXB
2.4.4.1 ERRSTS: Error Status Register
Address Offset: 44h Size: 8 bits
Default Value: 00h Attribute: Read/Write Clear, Sticky
This register records error conditions detected from the PCI bus (not already covered in PCISTS),
from the Expander Bus, and performance monitoring events.
The register is sticky through reset; that is, the contents of the register remain unchanged during
and following the assertion of X(0,1)RST#. This allows system recovery software in vok e d
following a forced reset to examine the flags to determine the cause of an error. Once set, the flags
remain set until explicitly cleared by software or a power-good reset.
Bits
7 reserved(0).
6 PERR# observed on PCI Bus
5 Parity Error on Received PCI Data
4 Parity Error on PCI Address
Description
This flag is set if the PXB detects the PERR# input asserted, and the PXB was not the
asserting agent. This flag may be configured to assert SE RR# or PERR# in the ERRCMD
register. This bit remains set until explicitly cleared by software writing a 1 to this bit.
This flag is set if the PXB detects a parity error on data being read from the PCI bus. This
flag may be configured to assert SERR# or PERR# in the ERRCMD register. This bit
remains set until explicitly cleared by software writing a 1 to this bit.
This flag is set if the PXB detects a parity error on the PCI address. This flag may be
configured to assert SERR# in the ERRCMD register. This bit remains set until explicitly
cleared by software writing a 1 to this bit.
2-22 Intel® 460GX Chipset Software Develop er ’s Manual
3 Inbound Delayed Read Time-out Flag
Each inbound read request that is accepted and serviced as a delayed read (i.e. the PXB
retries the request) will initiate a watchdog timer (2
has been returned and the timer expires before the requesting master initiates its repeat
request, this flag will be set. This flag may be configured to assert SERR# or PERR# in
the ERRCMD register. This bit remains set until explicitly cleared by software writing
a 1 to this bit.
2 reserved(0)
1 Performance Monitor #1 Event Flag
This flag is set when the Performance Monitor #1 requests that an interrupt request be
asserted. The PME and PMR registers (Section 2.5.3.3, Section 2.5.3.2) describe the
conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will
be asserted. This bit remains set until explicitly cleared by software writing a 1 to this bit.
0 Performance Monitor #0 Event Flag
This flag is set when the Performance Monitor #0 requests that an interrupt request be
asserted. The PME and PMR registers (Section 2.5.3.3, Section 2.5.3.2) describe the
conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will
be asserted. This bit remains set until explicitly cleared by software writing a 1 to this bit.
Register Descriptions
15
cycles, per the PCI spec). If th e data
2.4.4.2 ERRCMD: Error Command Register
Address Offset: 46h Size: 8 bits
Default Value: 00h Attribute: Read/Write
This register provides extended control over the assertion of SERR# beyond the basic controls
specified in the PCI-standard PCICMD register.
Bits
7 reserved(0)
6 Assert SERR# on Observed Parity Error
5 Assert SERR# on Received Data with Parity Error
4 Assert SERR# on Address Parity Error
3 Assert PERR# on Data Parity Error
2 Assert SERR# on Inbound Dela yed Read Time-out
1 reserved(0)
0 Return Hard Fail Upon Generating Master Abort
Description
If set, the PXB asserts SERR# if PERR# is observed asserted, and the PXB was not the
asserting agent.
If set, the PXB asserts SERR# upon receiving PCI data (i.e. an inbound write or outbound
read) with a parity error. This occurs regardless of whether PXB asserts it’s PERR# pin.
If set, the PXB asserts SERR# on detecting a PCI address parity error.
If set, and the PERRE bit is set in the PCICMD register, the PXB asserts PERR# upon
receiving PCI data with parity errors.
Each inbound read request that is accepted and serviced as a delayed read (i.e. the PXB
retries the request) will initiate a watchdog timer (2
enable is set, the PXB will assert SERR# if the data has been returned and the timer
expires before the requesting master initiates its r epeat request. Default=0.
If set, the PXB will return a Hard Fail response through the SAC to the system bus after
generating a master abort time-out for an outbound trans action placed on the PCI bus. If
cleared, the PXB will return a normal response (with data of all 1’s for a read). In either
case, an error flag is set in the PCISTS register. Default=0.
15
cycles, per the PCI spec). If this
Intel® 460GX Chipset Software Developer’s Manual 2-23
Register Descriptions
2.4.5 GXB
2.4.5.1 FERR_GXB
Function Number: BFN+1
Address Offset: 80h Size: 8 bits
Default Value: 00h Attribute: Read/Write Clear
Sticky: Yes Locked: No
These registers record the first error detected by the GXB. For the order to clear this register with
respect to the other GXB error registers.
Bits
7:3 reserved (0)
2 FERR_PCI bit asserted
1 FERR_AGP bit asserted
0 FERR_GART bit asserted
Description
2.4.5.2 FERR_PCI
Function Number: BFN+1
Address Offset: 84h Size: 8 bits
Default Value: 00h each Attribute: Read/Write Clear
Sticky: Yes Locked: No
These registers record the first error detected in GPI.
Bits
7 PCISTS Error Logged
6 Non-Configuration Master Abort
5 Discard Timer Expiration
4 SERR# Observed
3 PERR# Observed
2 PCI Inbound Read Que Data Pa rit y Error
1 PCI Outbound Write Que Data Parity Error
0 Illegal OB GART Access
Description
This bit is asserted when an error, except for a master abor t, has been logged in the PCI
Status register.
This bit is asserted when a master abort occurs on any transaction other than a
configuration read or configuration write.
reported the same as a master abort - see PCISTS register
This is the 2
Parity error detected as read data is retrieved from buffer.
Parity error detected as write data is retrieved from buffer.
Access may continue or abort, results undefined.
15
clock timeout.
2.4.5.3 FERR_AGP: First Error Status Register for AGP
Function Number: BFN+1
Address Offset: 85h Size: 8 bits
2-24 Intel® 460GX Chipset Software Develop er ’s Manual
Register Descriptions
Default Value: 00h Attribute: Read/Write Clear
Sticky: Yes Locked: No
These registers record and latch the first error detected in the AGP interface.
Bits
7:6 reserved (0)
5 Lo-priority Read Data Que Parity Error
4 Hi-priority Read Data Que Parity Error
3 Use of Pipe with Sideband Enabled
2 AGP address from graphics card [63:40 ] not equal to 0
1 AGP Request Queue Overflow
0 Illegal AGP Command
Description
This is data returned to the graphics card out of the Low-priority buffer.
This is data returned to the graphics card out of the Hi-priority buffer.
The GXB supports 16 ou t standing requests. This bit i s set i f a new request is sent by the
AGP card when the GXB already has 16 requests.
2.4.5.4 FERR_GART: First Error Status Register for GART
Function Number: BFN+1
Address Offset: 86h Size: 8 bits
Default Value: 00h Attribute: Read/Write Clear
Sticky: Yes Locked: No
These registers record and latch the first error detected in the AGP interface.
Bits
7:4 reserved (0)
3 GART Parity Error.
2 GART Entry Invalid
1 Illegal Address (after GART translation) in range between GAPBAS and GAPTOP, or
0 reserved (0)
Description
in VGA range and VGAGE is asserted, or directed by MARG to PCI instead of memory,
or above TOM.
2.4.5.5 NERR_AGP: Next Errors Status Register for AGP
Function Number: BFN+1
Address Offset: 8Dh Size: 8 bits
Default Value: 00h Attribute: Read/Write Clear
Sticky: Yes Locked: No
This register records all error conditions detected in the AGP interface after the first error. Errors
recorded in FERR_AGP are not recorded here.
Bits
7:0 See FERR_AGP for definition of these bits.
Intel® 460GX Chipset Software Developer’s Manual 2-25
Description
Register Descriptions
2.4.5.6 NERR_GART
Function Number: BFN+1
Address Offset: 8Eh Size: 8 bits
Default Value: 00h each Attribute: Read/Write Clear
Sticky: Yes Locked: No
This register records all error conditions detected in the GART logic after the first error. Errors
recorded in FERR_GART are not recorded here.
Bits
7:0 See FERR_GART for definitions of these bits.
Description
2.4.5.7 PAC_ERR: PCI Address & Cmd First Error
Function Number: BFN+1
Address Offset: A0h Size: 64 bits
Default Value: 0000000000h each Attribute: Read/Write
Sticky: Yes Locked: No
These registers record and latch the Address and Co mmand information on the PCI Bus for the first
error detected.
Bits
63:46 reserved(0)
45 PCI Parity (2nd phase of DAC, not defined for non-DAC address).
44 PCI Parity (if DAC, this is the parity of the first half of the address).
43:40 PCI Command - Command of Error.
39:0 PCI Address - Address Received on Error. (possible DAC address).
Description
2.4.5.8 PD_ERR: PCI Data First Error
Function Number: BFN+1
Address Offset: A8h Size: 64 bits
Default Value: 00h each Attribute: Read/Write
Sticky: Yes Locked: No
These registers record and latch the Data and Byte Enable information on the PCI Bus for the first
error detected.
Bits
63:37 reserved(0)
36 PCI Parity.
35:32 PCI Byte Enable [3:0] - Byte Enable of Error.
31:0 PCI Data - Data of Error.
2-26 Intel® 460GX Chipset Software Develop er ’s Manual
Description
2.4.6 WXB
2.4.6.1 ERRSTS: Error Status Register
Address Offset: 44h Size: 8 bits
Default Value: 00h Attribute: Read/Write Clear,
Sticky
This register records certain error conditions detected from the PCI bus. This register is sticky
through reset; that is, the contents of the register remain unchanged during and foll owing the
assertion of XRST#. This allows system recovery software invoked following a forced reset to
examine the flags to determine the cause of an error. Once set, the flags remain set until explicitly
cleared by software or a power-good reset.
Note: Bits 6, 4, and 2 are Reserved on side-b and records a zero value only!
Register Descriptions
Bits
7 INTRQ Asserted Flag
6 XBINIT Asserted Flag
Note: This bit is Reserved on side-b and records a zero value only!
5 NEPCI Register Records an PCI Bus Error Flag
4 reserved (0)
3 FEPCI Register Records an PCI Bus Error Flag
2 reserved (0)
1 Performance Monitor #1 Event Flag
0 Performance Monitor #0 Event Flag
Description
This flag is set if the WXB has initiated an INTRQ interrupt event. This bit remains set,
and the event signaled, until explicitly cleared by software writing a 1 to this bit.
Default = 0.
This flag is set if the WXB has asserted XBINIT#. This bit remains set, and th e event
signaled, until explicitly cleared by software writing a 1 to this bit. Default = 0.
This flag is set when the PCI bus reports an error (e.g. data parity error) on transactions
to/from other PCI bus agents. This bit remains set u ntil explicitly cleared by software
writing a 1 to this bit. This bit is only set when the error is reported through the NEPCI
Next Error register, indicating that the error is not the first error occurrence since the
First Error register was last cleared. Default = 0.
This flag is set when the PCI bus reports an error (e.g. data parity error) on transactions
to/from other PCI bus agents. This bit remains set u ntil explicitly cleared by software
writing a 1 to this bit. This bit is only set when the error is reported through the FEPCI
register, indicating that the error is the first error occurrence since the FEPCI register
was last cleared. Default = 0.
This flag is set when the Performance Monitor #1 detects an event. The
PCI_WXB_PMC1 registers describes the conditions that can cause this to occur. This
bit remains set until explicitly cleared by software writi ng a 1 to this bit. Default = 0.
This flag is set when the Performance Monitor #0 detects an event. The
PCI_WXB_PMC0 registers describes the conditions that can cause this to occur. This
bit remains set until explicitly cleared by software writi ng a 1 to this bit. Default = 0.
Intel® 460GX Chipset Software Developer’s Manual 2-27
Register Descriptions
2.4.6.2 ERRCMD: Error Command Register
Address Offset: 45h– 46h Size: 16 bits
Default Value: 8040h Attribute: Read/Write
This register provides extended control over the signalling of errors through SERR_OUT#,
XBINIT#, and INTRQ#. These controls are in add ition to the defined controls specified in the PCIstandard PCICMD register for SERR# assertion.
Bits
15 XBINITO: XBinit Override Enable
Note: Software should verify that there are no errors pending (by evaluating the ERRSTS register) before
clearing this bit.
Note: This bit is Reserved on side-b and records a value of one only!
14 reserved(0)
Note: This bit is Reserved on side-b and records a value of zero only!
13 IRQE: INTRQ Enable
12 ASAPE: Assert SERR# on Address Parity Error
11 ASDPE: Assert SERR# on any Data Parity Error
10 ASDTE: Assert SERR# on Discard Timer Expiration
9:7 reserved(0)
6 reserved(1)
5:0 reserved (0)
Description
This bit should always be initially set to 0 by software. If set to 0, XBINIT# may be
asserted by the WXB. The WXB will automatically set this bit af ter an XB INIT# is
signaled. Default = 1
Controls the reporting of WXB transmitted data errors. If set, the WX B will assert an
INTRQ interrupt for observed PERR# (including IHPC-driven parity errors) and data
parity errors detected in outbound transactions (e.g. Internal Queue Error detected
during read by PCI interface). Default = 0.
This bit should always be set to 1. When the WXB detects a PCI Address Parity Error
and both SERRE and PERRE are set, SERR# (and SERR_OUT#) will be signaled.
Default = 0.
If set, the WXB will assert SERR# (and SERR_OUT#) whenever a data parity error is
detected in an inbound transaction. The SERRE bit in the PCICMD r egister must also be
set for SERR# (and SERR_OUT#) t o be signaled. Def ault = 0.
This bit should always be set to 1. When an inbound read Discard Timer Expiration
occurs and SERRE is set, SERR# (and SERR_OUT#) will be signaled. Default = 0.
2.4.6.3 FEPCI: PCI Bus First Error Status Register
Address Offset: 83h Size: 8 bits
Default Value: 00h Attrib ute: Read/Write Clear,
Sticky
This register records and latches the first error observed on the PCI bus. Once an error has been
noted in this register, no further updates are allowed. This register is a write-1-to-clear register,
meaning that software must write a 1 to the specific bit location it wishes cleared. The response to
2-28 Intel® 460GX Chipset Software Develop er ’s Manual
Register Descriptions
each of these errors varies and is (generally) contr olled throug h a combination of th e PCICMD and
ERRCMD registers. Refer to Section 6.12 fo r inform ation on the conditional reporting of these
errors via the SERR#, XBINIT#, or INTRQ# outputs.
Note, if multiple errors are observed very close in time multiple errors may be signaled as a first
error.
Bits
Description
7 PCILV: PCI Error Logs Valid
This flag is set when an error has been logged in the FEPCIAL and FEPCIDL log
registers. The FEPCI status bit that lead to the logging must be cleared prior to clearing
the PCILV flag. Default = 0.
6 UMATA: Unexpected Master or Target Abort
This flag is set when an unexpected master abort or any target abort occurs. Master
aborts are reported as described for the RMA bit in the PCISTS register. Target aborts
through the RTA bit. Default = 0.
5 DTE: Discard Timer Expiration
This flag is set when the 2
15
clock timeout timer expires . This f lag may be co nfigured to
assert SERR#, XBINIT#, or an INTRQ interrupt through the ERRCMD register.
Default = 0.
4 SES: System Error Signaled
This flag is set when the a PCI agent other than the W XB asse rts SERR#. Th is flag may
be configured to assert XBINIT#, or an INTRQ interrupt through the ERRCMD
register. Default = 0
3 PODT: PERR# Observed on PCI Data Transfer
This flag is set if the WXB detects the PERR# input asserted, and the WXB was not the
asserting agent. This flag may be configured to assert SERR#, XBINIT#, or an INTRQ
interrupt through the ERRCMD register. Default = 0.
2 reserved (0)
1 PEOD: Parity Error on Received PCI Data
This flag is set if the WXB detects an parity error (i.e. calculates a parity different from
what is provided with the data) on data being sent to the WXB on the PCI bus (from a
master read or target write). Default = 0.
0 PEPA: Parity Error on PCI Address
This flag is set if the WXB detects a parity error on the PCI address. Default = 0.
2.4.6.4 NEPCI: PCI Bus Next Error Status Register
Address Offset: 87h Size: 8 bits
Default Value: 00h Attribute: Read/Write Clear,
Sticky
This register records any PCI bus errors detected after the first error is observ ed and recorded in the
FEPCI register. This register is a write-1-to-clear register, meaning that software must write a 1 to
the specific bit location it wishes cleared. The response to each of these errors varies and is
(generally) controlled through a combination of the PCICMD and ERRCMD registers. Error
logging is not performed for Next Error occurrences.
Bits
7:0 See the FEPCI register description for definitions. Error logging is not performed for
Intel® 460GX Chipset Software Developer’s Manual 2-29
Description
Next Error occurrences.
Register Descriptions
2.4.6.5 FEPCIAL: PCI First Error Address/Command Log
Address Offset: A5h–ADh Size: 72 bits
Default Value: 000000000000000000h Attribute: Read/Write Clear,
Sticky
These registers record and latch the address/command information, sent or received, associated
with a PCI Bus error for the first error detected.
Bits
71:68 reserved (0)
67:64 C/BE[3:0]
63:32 AD[63:32]
31:0 AD[31:0]
Description
2.4.6.6 FEPCIDL: PCI First Error Data Log
Address Offset: AFh – B3h Size: 40 bits
Default Value: 0000000000h Attribute: Read/Write Clear,
Sticky
These registers record and latch the PCI information, sent or received, specifically associated with
the PCI bus error for the first error detected. The recor ded data contains the upper or lower AD and
C/BE and PAR signals.
Bits
39:37 reserved (0)
36 PAR
35:32 C/BE
31:0 AD
Description
2.5 Performance Monitor Registers
2.5.1 SAC
2.5.1.1 IT_MON_PMD_[0 to 5]: Internal Transaction Performance Monitor
Data Register
Bus CBN, Device Number: 00h Function: 2
Address Offset: 9 0-97h, 98-9Fh, Size: 64 bits each
A0-A7h, A8-AFh,
B0-B7h, B8-BFh
Default Value: 0 each Attribute: Read/Write
Sticky: No Locked: No
The value written to this address, loads the counter and is also saved in a reload register. Each
counter can be configured to reload the data when it overflows.
2-30 Intel® 460GX Chipset Software Develop er ’s Manual
Register Descriptions
The IT_MON_PMD_[0 to 5] registers hold the performance monitoring count values. 39-bits of
the counter are used for event counting, the 40th-bit is used as a overflow detection bit. The 39-bit
count value allows up to 70 minutes of event collection at 133 MHz. Event selection is controlled
by the PMC registers (Section 2.5.1.2).
Each counter may be stopped/started independently, using the controls available in the associated
PMC register.
Bits
63:40 reserved(0)
39 Overflow
38:0 Count Value
Description
This bit is asserted when the Event Count bit 38 carries into bit 39.
This register contains the Performance Monitor Data Register. You may pr eset the value
of the performance counter by writing to this register . You may read back the value of the
performance counter by reading this register.
2.5.1.2 IT_MON_PMC_[0 to 5]: Internal Transaction Performance Monitor
Config. Register
Bus CBN, Device Number: 00h Function: 2
Address Offset: D0-D7h, D8-DFh, Size: 64 bits each
E0-E7h, E8-EFh,
F0-F7h, F8-FFh
Default Value: 0h each Attribute: Read/Write
Sticky: No Locked: No
The IT_MON_PMC_[0 to 5] Registers specify the configuration of the Internal Transaction
Performance Monitors. This includes specifying Event Selection, Unit Mask, Enable & Disable
Source and Reload Control.
Bits
63:41 reserved(0)
40:33 Length Encodings
Description
0000 0000b Any Length Transaction
0111 0000b 0 - 8 Bytes
0111 0001b 16 Bytes
0111 0010b 32 Bytes
0111 0111b 48 Bytes
0111 0011b 64 Bytes
0110 0000b < 32 Bytes
1000 0011b < 64 Bytes
Note: Length Encodings only used during the following Performance Monitor Setting:
Mem Read - Delayed
Mem Read - Deferred Reply
Memory Write
32:24 DMASK Encodings
0 0001 1010 - Configuration Space - Monitor transactions Destined for Config Block
0 0000 1100 - Memory - Monitor transactions Destined for Memory
0 0001 1110 - Broadcasts - Monitor Broadcasts
1 0000 0000 - All Destinations - Monitor all Destinations
Intel® 460GX Chipset Software Developer’s Manual 2-31
Register Descriptions
23:15 UMASK Encodings
14:8 Event Select
Note: In the fields below bit 13 sometimes has an ’R’. This stands for retry. If ’R’ is set to a 1 then the
count is the number of occurrences of the event that were retried. If ’R’ is set to a 0, then the count
is for non-retried occurrences of the even t. For example 110_0000b would be retried Interrupt Acks
and 100_0000b is for non-retried Interrupt Acks.
0 0000 0000 - Processor 0 - Monitor transactions originating from Processor 0
0 0000 0010 - Processor 1 - Monitor transactions originating from Processor 1
0 0000 0100 - Processor 2 - Monitor transactions originating from Processor 2
0 0000 0110 - Processor 3 - Monitor transactions originating from Processor 3
0 1000 0000 - All Processors - Monitor transactions originating from all Processors
0 0001 1010 - Conf iguration Space - Monitor transactions originating fro m Config Block
1 0000 0000 - All Initiators - Monitor all transactions
Selects the event to be monitored.
000 0000b Monitoring Disabled.
011 1111b All Clocks.
1R0 0000b Interrupt Ack
1R1 0001b Special Transaction and Defer Reply to Write.
1R0 0010b I/O Read
1R0 0011b I/O Write - Deferred Reply
1R1 0011b I/O Write - Posted.
1R0 0101b Purge TC and reserved and Branch Trace Messages
1R1 0101b Outbound Interrupt or Hard Fail Write Completion
1R0 0110b Mem Read
1R1 0111b Memory Write
110 1000b Check Connection
1R0 1010b Cfg Read
1R0 1011b Cfg Write - Deferred Reply
1R1 1011b Cfg Write - Posted
000 1100b Inbound Interrupt
1R0 1110b Locked Read - In Order
1R1 1110b Locked Read - Delayed
1R1 1111b Mem Write-Line
1R1 0000b Normal Read Completion
1R1 0100b Memory Scrub
1R0 1100b SS BR
1R1 1101b RS BR
000 0001b Snoop events
000 0010b Snoop Stall events caused by 460GX chipset
000 0011b Snoop Stall events caused by processors
000 0100b Snoop Stall events by either CPU’s or GX
000 0101b Hit events from CPU
000 0110b BNR events from GX
000 0111b BNR events from CPU
000 1000b BNR events from GX or CPU
000 1001b BPRI Clocks from GX
000 1010b BPRI Events from GX
000 1011b BPRI ADS’s from GX
001 0001b Speculative reads that are not used because of HITW
001 0010b Speculative reads that are not used because of HITM
001 0011b Speculative reads that are not used because of retry
001 0100b Speculative reads that are not used because read was restarted
001 0101b Speculative reads that were successful
001 0110b Speculative reads that were not done speculatively
2-32 Intel® 460GX Chipset Software Develop er ’s Manual
001 0111b Memory Read that was to be retried and received a HITM
001 1000b Memory Read with active OWN# and received a HITM
001 1001b Memory Read from a CPU that received a HITW
001 1010b Memory Read from a CPU that received a HITM
001 1011b Memory Read from PCI that received a HITW
001 1100b Memory Read from PCI that received a HITM
001 1101b Memory Write from PCI that received a HITM
010 0001b EV0 Events
010 0010b EV0 Clocks
010 0011b EV1 Events
010 0100b EV1 Clocks
7 reserved(0).
6:5 Disable Source
Selects event that will disable the performance monitor.
00b Never Disable.
01b Disable when this counter is overflowed (Note that if this setting is used, and bits
[4:3] are set to ’Enable Always’, then when this counter is overflowed, counting
will not resume until the counter is loaded with a non-overflow value).
10b Disable on falling edge of SAC Event 0.
11b Disable on falling edge of SAC Event 1.
4:3 Enable Source
Selects event that will enable the performance monitor.
Register Descriptions
00b Never Enable.
01b Enable Always (Disable events overrides this setting and will disable counting).
10b Enable on rising edge of SAC Event 0.
11b Enable on rising edge of SAC Event 1.
2:0 Reload Control
Selects event that will control the Reloading of the performance monitor with the value
written into the associated PMD2 register.
000b Never Reload.
001b Reload when counter overflows.
010b Reload on SAC Event 0 Asserted.
011b Reload on SAC Event 1 Asserted.
100b Reload on SAC Event 0 Asserting edge.
101b Reload on SAC Event 1 Asserting edge.
Note: When counting retried reads (code of 110_01 10b) the logic will count reads that were to be retried,
but got a HITM# and therefore the HITM# overrides the retry. For an exact count of reads that are
truly retried, count retried reads (110_0110b) and subtract out the number of reads that were to be
retried but got a HITM# (code of 001_ 01 1 1b). Thi s give the exact numb er of reads that were retried
on the bus.
Intel® 460GX Chipset Software Developer’s Manual 2-33
Register Descriptions
2.5.2 SDC
2.5.2.1 FSB_D_PMC_[1,0]: System Bus Performance Monitor Configuration
Register
Bus CBN, Device Number: 04h
Address Offset: 9 8-9Ah, 9C-9Eh Size: 24 bits each
Default Value: 000000h each Attribute: Read/Write
The FSB_D_PMC_[1,0] Registers specify the configuration of the SDC system bus performance
monitors. This includes specifying Event Selection, Unit Mask, Enable & Divisible Source &
Reload Control.
Bits
23:17 reserved(0).
16:15 Mask.
14:8 Event Select.
7 reserved(0).
6:5 Disable Source.
Description
This field contains the Event Specific Mask Bits. This allows qualifying event collection
by the issuing agent of the transaction.
00b reserved.
01b Monitor only if 460GX chipset initiated the transaction.
10b Monitor only if 460GX chipset did not initiate the transaction.
11b Monitor all transactions regardless of issuing agent.
Selects the event to be monitored.
000 0000b Monitoring Disabled.
000 0001b System Bus Clocks.
000 0010b DBSY# Clocks.
100 0010b DBSY# Events.
000 0011b DRDY# Clocks.
100 0011b DRDY# Events.
100 0100b DBSY# and not(DRDY#) Events.
000 0101b TRDY# Clocks.
100 0101b TRDY# Events.
000 0110b TRDY# asserted when DBUSY# asserted (clocks)
100 0110b TRDY# asserted when DBUSY# asserted (events)
000 0111b Read from SDC waiting on processor write (clocks)
100 0111b Read from SDC waiting on processor write (events)
000 1000b Read from SDC waiting on an SDC read to complete (clocks)
100 1000b Read from SDC waiting on an SDC read to complete (events)
100 1001b reserved
100 1010b reserved
000 1011bEvent Logic 0 Active Clocks
100 1011b Event Logic 0 Events
000 1100b Event Logic 1 Active Clocks
100 1100b Event Logic 1 Events
Selects event that will disable the performance monitor. Note that the disable and enable
sources are edge-triggered for Event 0 or 1.
00b Never Di sable.
2-34 Intel® 460GX Chipset Software Develop er ’s Manual
01b Disable when counter overflows.
10b Disable on falling edge (Deassertion) of SDC Event 0.
11b Disable on falling edge (Deassertion) of SDC Event 1.
4:3 Enable Source.
Selects event that will enable the performance monitor.
00b Never Enable (in this mode the counter will never count).
01b Enable Always (note that if this setting is used, the disable events in bits [6:5] will
only disable counting for one clock, and then the counter resumes. When bits [4:3]
are set to ’Enable Always’, the only meaningful setting for bits [6:5] is
’Never Disable’.
10b Enable on rising edge (Assertion) of SDC Event 0.
11b Enable on rising edge (Assertion) of SDC Event 1.
2:0 Reload Control.
Selects event that will control the Reloading of the performance monitor with the value
written into the associated PMD1 register.
000b Never Reload.
001b Reload when counter overflows.
010b Reload on SDC Event 0 Asserted.
011b Reload on SDC Event 1 Asserted.
100b Reload on SDC Event 0 Asserting edge.
101b Reload on SDC Event 1 Asserting edge.
Register Descriptions
2.5.2.2 FSB _D_PMD_[1,0]: System Bus Performance Monitor Data Registers
Bus CBN, Device Number: 04h
Address Offset: A0-A7h, A8-AFh Size: 64 bits each
Default Value: 0 each Attribute: Read/Write
Two performance monitoring counters, with associated event selection and control registers, is
provided in the SDC component. These counters may be configured to track system bus events.
Event detection may be configured to incr ement a counter , affect per formance monitor ing pins, and
issue an interrupt request on counter overflow.
The value written to this address, loads the counter and is also saved in a reload register. Each
counter can be configured to reload the data when it overflows.
The FSB_D_PMD_[1,0] registers hold the performance monitoring count values. 39-bits of the
counter are used for event counting, the 40th-bit is used as a overflow detection bit. The 39-bit
count value allows up to 70 minutes of event collection at 133 MHz. Event selection is controlled
by the PMC registers.
Each counter may be stopped/started independently, using the controls available in the associated
PMD register.
Bits
63:40 reserved(0)
39 Overflow
38:0 Count Value
Description
This bit is asserted when the Event Count bit 38 carries into bit 39.
This register contains the Performance Monitor Data Register. You may pr eset the value
of the performance counter by writing to this register . You may read back the value of the
performance counter by reading this register.
Intel® 460GX Chipset Software Developer’s Manual 2-35
Register Descriptions
2.5.3 PXB
2.5.3.1 PMD[1:0]: Performance Monitoring Data Register
Address Offset: D8-DBh, E0-E3h Size: 32 bits each
Default Value: 0000_0000h each Attribute: Read/Write
Two performance monitoring counters, with associated event selection and control registers, are
provided for each PCI bus in the PXB. Each counter may be configured to track PCI bus events.
Event detection may be configured to increment a counter, toggle a pin on event or counter
overflow, and issue an interrupt request on counter overflow.
The PMD registers hold the performance monitoring count values. These registers are 32-bit
counters. Event selection is controlled by the PME registers, and the action performed on event
detection is controlled by the PMR registers.
Each counter may be stopped/started independently, using the controls available in the associated
PMR register.
Bits
31:0 Count Value
Description
2.5.3.2 PMR[1:0]: Performance Monitoring Response
Address Offset: DDh, E5h Size: 8 bits each
Default Value: 0000h each Attribute: Read/Write
There are two PMR registers for each PCI bus, one for each PMD counter. Each PMR register
specifies how the event selected by the corresponding PME register affects the associated PMD
register, P(A,B)MON# pins, and the INT(A,B)RQ# pins.
Bits
7:6 Interrupt Assertion
5:4 Performance Monitoring pin assertion
3:2 Count Mode
Description
Defines how selected event affects INTRQ# assertion. Whenever INTRQ# is asserted, a
flag for this counter is set in the Error Status Register, so that software can determine the
cause of the interrupt. This flag is reset by writing the Error Status Register.
0 Selected event does not assert INTRQ #
1 reserved
2Assert INTRQ# pin when event occurs
3Assert INTRQ# pin when counter overflows
Defines how the selected event affects the PMON# pin for this counter.
0 PMON# pin is tristated. Selected event has no effect.
1 reserved
2 Assert this counter’s PMON# pin when event occurs
3 Assert this counter’s PMON# pin when counter overflows
Selects when the counter is updated for the detected event.
0 Stop counting.
1 Count each cycle selected event is active.
2 Count on each rising edge of the selected event.
3 Trigger. Start counting on the first rising edge of the selected event, and
continue counting each clock cycle.
2-36 Intel® 460GX Chipset Software Develop er ’s Manual
Once configured to count, all counters in the SAC and each PXB can be (nearly)
simultaneously started and stopped using a separate enable.
1:0 Reload Mode
Reload has priority over increment. That is, if a Reload event and a count event happen
simultaneously, the count event has no effect.
0 Never Reload
1 Reload when this counter overflows.
2 Reload when the other counter overflows.
3 Reload unless the other counter increments.
2.5.3.3 PME[1:0] : Performance Monitoring Event Selection
Address Offset: E8 - EBh Size: 16 bits each
Default Value: 0000h each Attribute: Read/Write
The PME registers specify the particular event to track in the performance monitoring counters.
The PXB supports tracking o f PCI b us t rans acti ons (b oth s peci fic an d gen e ric), an d P CI bus s ignal
assertion. Bus transactions may be qualified by th e orig inating agent and transaction destination.
Accumulated event counts are held in the PMD registers, while the PMR registers specify the
action to performed on event detection.
Register Descriptions
Bits
15 reserved (0)
14 Count Data Cycles
13:10 Initiating Agent Selection
Note: This field is applicable only if the PCI bus is operated in internal-arbiter mode. If the bus is
operated using an external arbiter, this field must be set to Any Agent to trigger any events.
9:8 Transaction Destinat ion Selection
7:6 reserved
Description
1: Count data cycles associated with selected event
0: Count the selected event
This field qualifies the tracking of bus transactions by limiting event detection to those
transactions issued by specific agents. That is, unless otherwise noted for the specific
event selected (below), the agent initiating the bus transaction must match the selection
specified here for the transaction to be tracked.
0000 Agent 0 1000 reserved
0001 Agent 1 1001 reserved
0010 Agent 2 1010 reserved
0011 Agent 3 1011 reserved
0100 Agent 4 1100 reserved
0101 Ag ent 5 1101 South bridge
0110 reserved 1110 460GX chipset agent (i.e.
outbound)
0111 reserved 1111 Any agent
This field qualifies the tracking of bus transactions by limiting event detection to those
transactions directed to a specific resource. That is, unless otherwise noted for the
specific event selected (below), the source or destination of the data must match the
selection specified here for the transaction to be tracked.
00 any 10 PCI Target
01 Main Memory 11 Parallel Segment Peer
Intel® 460GX Chipset Software Developer’s Manual 2-37
Register Descriptions
5:0 Event Selection
This field specifies the basic PCI bus transaction or PCI bus signal to be monitored.
Individual Bus Transactions
00 0000 reserved 00 1000 reserved
00 0001 reserved 00 1001 reserved
00 0010 I/O Read 00 1010 reserved
00 0011 I/O Write 00 1011 reserved
00 0100 reserved 00 1100 Memory Read Multiple
00 0101 reserved 00 1101 Dual Address Cycle
00 0110 Memory Read 00 1110 Memory Read Line
00 0111 Memory Write 00 1111 Memory Write & Invalidate
Generic (Grouped) Bus Transactions
010 000 Any bus transaction 010 100 Any I/O transaction
010 001 Any memory transaction 010 101 Any I/O or memory
transactions
010 010 Any memory read 010 110 Any I/O or memory read
010 011 Any memory write 010 111 Any I/O or memory write
Bus Signal As sertions
011 000 reserved 011 100 reserved
011 001 reserved 011 101 reserved
011 010 RETRY
011 011 reserved 011 111 ACK64
All other encodings are reserved.
1
011 110 LOCK
NOTE:1. Counting data cycles is undefined for this selection.
2.5.4 GXB
2.5.4.1 AGP_PMD_0,1: AGP Performance Monitor Data Registers
Function Number: BFN+1
Address Offset: 50h, 58h Size: 64 bits
Default Value: 0 Attribute: Read/Write
Sticky: No Locked: No
This counter may be configured to track AGP bus events as well as events internal to the GXB.
Event detection may be configured to increm ent a counter , af fect performance monitoring pins, and
issue an interrupt request on counter overflow.
The value written to this address, loads the counter and is also saved in a reload register. Each
counter can be configured to reload the data.
The AGP_G_PMD register holds the performance monitoring count value. 39-bits of the counter
are used for event counting, the 40th-bit is used as a ov erflow d etection bit. T he 39 -bit cou nt value
allows up to 70 minutes of event collection at 133 MHz. Event selection is controlled by the PMC
registers.
Each counter may be stopped/started independently, using the controls available in the associated
PMD register.
Bits
63:40 reserved(0)
39 Overflow
2-38 Intel® 460GX Chipset Software Develop er ’s Manual
Description
This bit is asserted when the Event Count bit 38 carries into bit 39.
38:0 Count Value
This register contains the Performance Monitor Data Register. You may pr eset the value
of the performance counter by writing to this register . You may read back the value of the
performance counter by reading this register.
2.5.4.2 PCI_PMD: PCI Performance Monitor Data Registers
Function Number: BFN+1
Address Offset: 60h Size: 64 bits
Default Value: 0 Attribute: Read/Write
Sticky: No Locked: No
This counter may be configured to track PCI bus events as well as events internal to the GXB.
Event detection may be configured to incr ement a counter , affect per formance monitor ing pins, and
issue an interrupt request on counter overflow.
The value written to this address, loads the counter and is also saved in a reload register. Each
counter can be configured to reload the data.
The PCI_PMD register holds the performance monitoring count value. 39-bits of the counter are
used for event counting, the 40th-bit is used as a overflow detection bit. The 39-bit count value
allows up to 70 minutes of event collection at 133 MHz. Event selection is controlled by the PMC
registers.
Register Descriptions
Each counter may be stopped/started independently, using the controls available in the associated
PMD register.
Bits
63:40 reserved(0)
39 Overflow
38:0 Count Value
Description
This bit is asserted when the Event Count bit 38 carries into bit 39.
This register contains the Performance Monitor Data Register. You may pr eset the value
of the performance counter by writing to this register . You may read back the value of the
performance counter by reading this register.
2.5.4.3 PERCON: Performance Monitor Control Register
Function Number: BFN+1
Address Offset: E0h Size: 8 bits
Default Value: 00h Attribute: Read/Write
Sticky: No Locked: No
The PERCON Register allows one software write to start a nd stop the performance mo nitors. The 2
bits are fed into the Event Logic generation. Bit 0 feeds Event 0 and bit 1 feeds Event 1. Since the
counters can be enabled and disabled by Events 0 or 1, then one write can start or stop all the
counters together.
Bits
7:2 reserved (0)
1 Event 1 Input
Description
This bit is fed as an input into Event 1 logic. This bit is OR’ed with any other logic
generating Event 1, guaranteeing that if this bit is set, then Event 1 will be asserted.
Intel® 460GX Chipset Software Developer’s Manual 2-39
Register Descriptions
0 Event 0 Input
This bit is fed an input into Event 0 logic. This bit is OR’ed with any other logic
generating Event 0, guaranteeing that if this bit is set, then Event 0 will be asserted.
2.5.4.4 AGP_PMC_[0,1]: AGP Performance Monito r Configuration Register
Function Number: BFN+1
Address Offset: ECh, F0h Size: 32 bits
Default Value: 000000h Attrib ute: Read/Write
Sticky: No Locked: No
The AGP_G_PMC Register specifies the configuration of the GXB AGP Performance Monitor.
This includes specifying Event Selection, Unit Mask, Enable & Disable Source and Reload
Control.
Bits
31:24 ’n’ for threshold Monitoring
23:20 reserved(0).
19:18 Events to monitor, when Event Select Code points to events. Data Transfer is one
17:16 Pipe or Sideband Request Mask
15:14 reserved(0).
13:8 Event Select
Description
QW (8 bytes). Used also for code 11 0000
00 - All events
01 - Events with ’n’ Data Transfer Cycles
02 - Events with < ’n’ Data Transfer Cycles
03 - Events with > ’n’ Data Transfer Cycles
00b reserved.
01b Selects Low Priority.
10b Selects High Priority.
11b Selects Both.
Selects the event to be monitored.
00 0000b Monitoring Disabled.
00 0001b AGP Read Request Events.
00 0010b AGP Write Request Events.
00 0011b All AGP Request Events (does not include Flush or Fence requests).
00 0101b Singe Read that splits 4k page boundary.
00 0110b Single Write that splits line boundary.
01 0000b Flushes (events)
01 0001b Fences (events)
01 0010b RBF# active events.
01 0011b Events of write wait states inserted by AGP card
01 0100b Events of LPTT timeout with another request active.
01 0101b Events of MTT timeout with another request active.
01 0111b GART Aperture Misses
10 0000b AGP Clocks.
10 0100b Count AGP clocks that RBF# is stalled
10 0101b Count AGP clocks that low-priority read buffer is physically empty.
10 0110b Count AGP clocks that high-priority read buffer is physically empty.
10 0111b Count AGP clocks that both the low and high priority buffers are empty.
11 0000b C ount AGP clocks that there ar e <=> ’n’ reques ts queued; using b its 31:24 and
19:18.
2-40 Intel® 460GX Chipset Software Develop er ’s Manual
7 EVENT1 Count Enable
If set, then this bit over-rides bits 13:8. If set, then AGP_PMD_0 will count the number
of occurrences of EVENT1 and AGP_PMD_1 will count the number of clocks that
EVENT1 is active. When this bit is not set, then the 2 counters are controlled by bits 13:8.
6:5 Disable Source
Selects event that will disable the performance monitor.
00b Never Disable.
01b Disable when counter overflows.
10b Disable on falling edge of GXB Event 0.
11b Disable on falling edge of GXB Event 1.
4:3 Enable Source
Selects event that will enable the performance monitor.
00b Never Enable.
01b Enable Always (with this setting, the only meaningful setting for bits 6:5 is 00b).
10b Enable on rising edge of GXB Event 0.
11b Enable on rising edge of GXB Event 1.
2:0 Reload Control.
Selects event that will control the Reloading of the performance monitor with the value
written into the associated PMD register.
Register Descriptions
000b Never Reload.
001b Reload when counter overflows.
010b Reload when GXB Event 0 Asserted.
011b Reload when GXB Event 1 Asserted.
100b Reload on GXB Event 0 Asserting edge.
101b Reload on GXB Event 1 Asserting edge.
2.5.4.5 PCI_PMC: PCI Performance Monitor Configuration Register
Function Number: BFN+1
Address Offset: F4h Size: 24 bits
Default Value: 000000h Attribute: Read/Write
Sticky: No Locked: No
The PCI_PMC Register specifies the configuration of the GXB PCI Performance Monitor. This
includes specifying Event Selection, Unit Mask, Enable & Disable Source and Reload Control.
NOTE: the Event Select field determines whether clocks or events are counted. In the case of
events, then all events are counted. In the case of clocks, all clocks in which the selection is active
are counted.
Bits
23:18 reserved(0).
17:16 Initiating Agent
15:14 reserved(0).
13:8 Event Select
Description
00b reserved.
01b Outbound.
10b Inbound.
11b Selects Both.
Selects the event to be monitored.
00 0000b
Monitoring Disabled
Intel® 460GX Chipset Software Developer’s Manual 2-41
Register Descriptions
7 reserved(0).
6:5 Disable Source
00 0010b All PCI Clocks
00 0100b Idle Bus Cycles
00 0111b All Disconnect Events
00 1000b Lock Asserted Clocks
00 1001b Lock Asserted Events
00 1011b I/O Reads - Events
00 1101b I/O Writes - Events
00 1111b Memory Read Events
01 0001b Memory Write Events
01 0011b SRAM Read Events
01 0101b SRAM Write Events
01 0111b Write Combining Events
01 1000b WBF# Active - Clocks
01 1001b WBF# Active - Events
01 1011b Retry Read that’s not Delayed - Events
01 1101b Retry Write because no Write Slot available - Events
01 1110b Count PCI clocks waiting (Devsel and !IRDY and TRDY)
10 0000b Count PCI clocks waiting (Devsel and IRDY and !TRDY)
10 0010b Count PCI clocks data is transferring
Selects event that will disable the performance monitor.
00b Never Di sable.
01b Disable when counter overflows.
10b Disable on falling edge of GXB Event 0.
11b Disable on falling edge of GXB Event 1.
4:3 Enable Source
Selects event that will enable the performance monitor.
00b Never Enable.
01b Enable Always (with this setting, the only meaningful setting for bits 6:5 is 00b).
10b Enable on rising edge of GXB Event 0.
11b Enable on rising edge of GXB Event 1.
2:0 Reload Control
Selects event that will control the Reloading of the performance monitor with the value
written into the associated PMD register.
000b Never Reload.
001b Reload when counter overflows.
010b Reload on GXB Event 0 Asserted.
011b Reload on GXB Event 1 Asserted.
100b Reload on GXB Event 0 Asserting edge.
101b Reload on GXB Event 1 Asserting edge.
2-42 Intel® 460GX Chipset Software Develop er ’s Manual
Register Descriptions
2.5.5 WXB
2.5.5.1 PCI_WXB_PMC0: PCI Performance Monitor Configuration Register
Address Offset: DCh – DFh Size: 32bits
Default Value: 00000000h Attribute: Read/Write
This register controls the PCI performance monitors. There are two performance monitors for each
PCI bus. This register defines the events to be monitored, and when monitoring should start and
stop. The selected event can be qualified by data transferred, and issuing agent.
Bits
31:24 reserved (0)
23:21 Data Transfer and Transaction Qualifier
20:19 reserved (0)
18:17 Issuing Agent Qualifier
16:11 Event Select
10:4 reserved (0)
3 Enable Source
2:0 reserved (0)
Description
Qualifies a selected “Packet Type” by the presence or absence of data transferred.
000bAll events
001bRetry - for any reason
010bRetry - no buffers available (inbound read or write transactions only)
011bRetry - no data available (inbound read transactions only)
101bLocked
110bDual Address Cycles
Monitor only those selected events issued by the following agent:
00breserved
01bOutbound: Issued by WXB
10bInbound: Not issued by WXB
11bAll: Issued by any agent
Selects the event(s) to be monitored.
Measurement
00 0000b Monitoring Disabled
Tra nsact ion Types
01 0001bI/O Reads
01 0010bMemory Reads
01 0100bMem Read Lines
01 1000bMem Read Multiples
01 1111 bAny Read
10 0001bI/O Writes
10 0010bMemory Writes
10 0100bMem Wr & Invalidates
10 1111bAny Write
11 1111bAny Transaction
When this bit is set to 1, the performance monitoring logic is enabled. Default=0.
Intel® 460GX Chipset Software Developer’s Manual 2-43
Register Descriptions
2.5.5.2 PCI_WXB_PMC1: PCI Performance Monitor Configuration Register
Address Offset: E8h – EBh Size: 32bits
Default Value: 00000000h Attribute: Read/Write
This register controls the PCI performance monitors. There are two performance monitors for each
PCI bus. This register defines the events to be monitored and when monitoring starts and stops.
The selected event can be qualified by data transferred, and issuing agent.
Bits
31:0 See PCI_WXB_PMC0 definitions.
Description
2.6 Interrupt Related Registers
2.6.1 SAC
2.6.1.1 XTPRS: External Task Priority Registers
Bus CBN, Device Number: 00h Function: 0
Address Offset: C0-C7h Size: 64 bits
Default Value: 80h Attribute: Read Only
Sticky: No Locked: No
The XTPRS are used to support redirectable interrupts. These registers are made observable to
software primarily for test and debug purposes. These registers will be updated by XTPR Update
Special Cycle on the system bus. The second cycle of the XTPR Update Special Cycle’s address
determines the value to load into the register. Ab[27:24]# is the 4 bit XTPR value. Ab[23:20]#
determines which register to update. Since the high priority agent reserves the uppermost agent ID
bit, only Ab[22:20]# are used. Th ese 3 bits decode to one of the 8 registers . Ab[31] is the enable b it
for the register.
All registers default to 1000_0000b, which is the disabled state.
Each register is defined as:
Bit 7 - enable (1=disable, 0=enable)
Bits 6:4 - reserved (0)
Bits 3:0 - value of XTPR
Bits
63:56 XTPR 7
55:48 XTPR 6
47:40 XTPR 5
39:32 XTPR 4
31:24 XTPR 3
23:16 XTPR 2
2-44 Intel® 460GX Chipset Software Develop er ’s Manual
Description
These bits represent the external task priority for symmetric agent ID 07h.
These bits represent the external task priority for symmetric agent ID 06h.
These bits represent the external task priority for symmetric agent ID 05h.
These bits represent the external task priority for symmetric agent ID 04h.
These bits represent the external task priority for symmetric agent ID 03h.
These bits represent the external task priority for symmetric agent ID 02h.
15:8 XTPR 1
These bits represent the external task priority for symmetric agent ID 01h.
7:0 XTPR 0
These bits represent the external task priority for symmetric agent ID 00h.
2.6.2 PID PCI Memory-mapped Registers
The PID uses two 32-bit memory-mapped registers to provide the indirect addressing access to its
(x)APIC interrupt r edirection registers as w ell as to i ts ID, versio n, and arbit ration ID re gisters. The
memory-mapped registers are placed at default addresses of FEC0_0000h, FEC0_0010h, and
FEC0_0040h for (x)APIC compatibility.
The I/O select register is used to provide the index of the internal register being accessed. The
register being accessed is determined by bits 7 throug h 0 of this regis ter. The I/O window register is
used to provide/receive data associated with the access.
Table 2-2 summarizes the memory-mapped registers. Detailed descriptions of each register follow.
Note: The default base address FEC00 which is mapped to A[31:12] can be changed by reprogramming
the (x)APIC base address register via PCI configuration space access.
Register Descriptions
Table 2-2. Memory-Mapped Register Summary
Address Name Access Default Value
FEC00000h I/O Register Select Register R/W 00000000h
FEC00010h I/O Window Register R/W 00000000h
FEC00040h (x)APIC EOI Register R/W 00000000h
2.6.2.1 I/O Register Select Register (FEC00000h)
The I/O register select register selects which indirect access register appears in the I/O window
register where it can be manipulated by software. The selector values for the indirect access
registers are listed in Section 2.6.3. Software programs bits 7 through 0 of this register to select the
desired internal register. The conten ts of the selected 32-bit register can be manipulated via the I/O
window register . Th e I/O regis ter s elect reg ister is read/write by software and its default is listed in
Section 2.6.2.2. This startin g address, where the I /O register select regis ter and I/O window register
reside, can be relocated to a differ ent ad dres s via the APIC bas e ad dres s regist er. The format of the
I/O register select register is shown in Table 2-3.
Note: This register is defined as a 32-bit reg ister, but only the lower eight bits are used. This register must
be accessed using 32-bit memory reads or writes. Bits 31 through 8 should be set to 0s.
T able 2-3. I/O Select Register Format
Register Offset: FEC00000hDefault Value: [00000000h]Attribute: Read/Write
Bit(s) Name Description
31:8 Reserved These 24 bits are reserved.
7:0 REGISTER
ADDRESS
Intel® 460GX Chipset Software Developer’s Manual 2-45
These eight bits provide the address offset of the internal 32-bit register. This
number is used to select consecutive 32-bit internal registers via the I/O
window register. Described in Section 2.6.2.2 is 64-bit register access.
Register Descriptions
2.6.2.2 I/O Window Register (FEC00010h)
This register is mapped onto the PID’s internal register that is selected by the I/O register select
register. Readability/writeability by software is determined by the characteristics of the internal
register that is currently selected. The format of the I/O window register is shown in Table 2-4
below. This register must be accessed using 32-bit read or write operations.
Table 2-4. I/O Window Register Format
Register Offset: FEC00010hDefault Value: [00000000h]Attribute: Read/Write
Bit(s) Name Description
31:0 IOWIN[31:0] This 32-bit register contains the 32-bit write or read data value.
2.6.2.3 (x)APIC EOI Register (FEC00040h)
The (x)APIC EOI register provides a means of informing the PID that interrupt service has been
completed by the processor for a given inter rupt vector (mapped to 1 of 64 interrupt inputs received
by the PID). The PID will compare this vector value with the vector field of each entry in the RT.
When a match is found, the RIRR bit for that entry will be cleared. In the case of level-triggered
interrupts, clearing the remote IRR bit will initiate a resampling of the corresp onding interrupt
input signal. If the interrupt input is still asserted, the PID will issue a new level-triggered interrupt
message. The PID will therefore issue a sing le new inter rupt message up on receiving an EOI wr ite,
corresponding to the still asserted interrupt input pin. The PID only uses the (x)APIC EOI register
in SAPIC mode.
Note: If multiple redirection entries assign the same vector for more than one interrupt pin, each of those
pins will be resampled and new interrupt messages issued for those that are still asserted. This
register must be accessed using 32-bit read or write operations.
Table 2-5. (x)APIC EOI Register Format
Register Offset: FEC00040hDefault Value: [00000000h]Attribute: Read/Write
Bit(s) Name Description
31:8 Reserved Reserved
7:0 SAPICEOI[7:0] Interrupt vector
2.6.3 PID Indirect Access Registers
The PID provides several indirect access registers. These registers are accessed via the I/O select
and I/O window registers described above. The indirect access registers include the (x)APIC ID,
version, and arbitration ID registers, and 64 RTEs for each of the 64 interrupt inputs to the PID.
Registers at offsets 03h-0Fh are reserved and will return a 00h value when read.
Table 2-6 summarizes the indirect access registers. Detailed descriptions of each register follow.
2-46 Intel® 460GX Chipset Software Develop er ’s Manual
2.6.3.1 I/O (x)APIC ID Register (00h)
T a ble 2-6. Memory-mapped Register Summary
Offset Name Access Default Value
00h I/O (x)APIC ID Register R/W 00000000h
01h I/O (x)APIC Version Register R/O 003F00vvh
02h I/O (x)APIC Arbitration ID Register R/O 00000000h
03h-0Fh Reserved R/O 00000000h
10h RTE 0 R/W 00000000_00010000h
12h RTE 1 R/W 00000000_00010000h
14h RTE 2 R/W 00000000_00010000h
16h RTE 3 R/W 00000000_00010000h
18h RTE 4 R/W 00000000_00010000h
1Ah RTE 5 R/W 00000000_00010000h
1Ch RTE 6 R/W 00000000_00010000h
1Eh RTE 7 R/W 00000000_00010000h
20h RTE 8 R/W 00000000_00010000h
22h RTE 9 R/W 00000000_00010000h
24h RTE 10 R/W 00000000_00010000h
26h RTE 11 R/W 00000000_00010000h
28h RTE 12 R/W 00000000_00010000h
2Ah RTE 13 R/W 00000000_00010000h
2Ch RTE 14 R/W 00000000_00010000h
2Eh RTE 15 R/W 00000000_00010000h
30h RTE 16 R/W 00000000_00010000h
32h RTE 17 R/W 00000000_00010000h
34h RTE 18 R/W 00000000_00010000h
36h RTE 19 R/W 00000000_00010000h
38h RTE 20 R/W 00000000_00010000h
3Ah RTE 21 R/W 00000000_00010000h
3Ch RTE 22 R/W 00000000_00010000h
3Eh RTE 23 R/W 00000000_00010000h
40h RTE 24 R/W 00000000_00010000h
42h RTE 25 R/W 00000000_00010000h
44h RTE 26 R/W 00000000_00010000h
46h RTE 27 R/W 00000000_00010000h
48h RTE 28 R/W 00000000_00010000h
4Ah RTE 29 R/W 00000000_00010000h
4Ch RTE 30 R/W 00000000_00010000h
4Eh RTE 31 R/W 00000000_00010000h
50h RTE 32 R/W 00000000_00010000h
Register Descriptions
a
Intel® 460GX Chipset Software Developer’s Manual 2-47
Register Descriptions
Table 2-6. Memory-mapped Register Summary (Cont’d)
Offset Name Access Default Valu e
52h RTE 33 R/W 00000000_00010000h
54h RTE 34 R/W 00000000_00010000h
56h RTE 35 R/W 00000000_00010000h
58h RTE 36 R/W 00000000_00010000h
5Ah RTE 37 R/W 00000000_00010000h
5Ch RTE 38 R/W 00000000_00010000h
5Eh RTE 39 R/W 00000000_00010000h
60h RTE 40 R/W 00000000_00010000h
62h RTE 41 R/W 00000000_00010000h
64h RTE 42 R/W 00000000_00010000h
66h RTE 43 R/W 00000000_00010000h
68h RTE 44 R/W 00000000_00010000h
6Ah RTE 45 R/W 00000000_00010000h
6Ch RTE 46 R/W 00000000_00010000h
6Eh RTE 47 R/W 00000000_00010000h
70h RTE 48 R/W 00000000_00010000h
72h RTE 49 R/W 00000000_00010000h
74h RTE 50 R/W 00000000_00010000h
76h RTE 51 R/W 00000000_00010000h
78h RTE 52 R/W 00000000_00010000h
7Ah RTE 53 R/W 00000000_00010000h
7Ch RTE 54 R/W 00000000_00010000h
7Eh RTE 55 R/W 00000000_00010000h
80h RTE 56 R/W 00000000_00010000h
82h RTE 57 R/W 00000000_00010000h
84h RTE 58 R/W 00000000_00010000h
86h RTE 59 R/W 00000000_00010000h
88h RTE 60 R/W 00000000_00010000h
8Ah RTE 61 R/W 00000000_00010000h
8Ch RTE 62 R/W 00000000_00010000h
8Eh RTE 63 R/W 00000000_00010000h
a. vv is 13h in APIC mode of operation, 21h in SAPIC mode of operation.
The I/O (x)APIC ID register is read/write by software. On reset, this register’s contents are res et to
zero. This register is provided for APIC compatibility only and it does not serve any other purpose.
The PID’s (x)APIC ID register has a default value of 00000000h. This register should be
programmed with the correct (x)APIC ID value before using the PID in APIC mode. The (x)APIC
ARBID register is also written during a write to this regi ster.
2-48 Intel® 460GX Chipset Software Develop er ’s Manual
Table 2-7. I/O APIC ID Register Format
Register Offset: 00h Default Value: [00000000h]Attribute: Read/Write
Bit(s) Name Description
31:28 Reserved These four bits are reserved.
27:24 ID[3:0] These four bits provide the APIC ID. This field is used by the I/O APIC unit of
the PID. In SAPIC or compatibility mode of operation, these bits are ignored.
23:16 Reserved These 24 bits are reserved.
15 DT This bit defines the delivery type. A ‘0’ in this field indicates APIC delivery
mechanism. A ‘1’ indicates SAPIC delivery mechanism. This bit reflects the
PICMODE strap pin.
14 LTS Level deassert message support. This bit is always ‘0’ since the PID does not
support “level deassert” messages.
13:0 Reserved Reserved.
2.6.3.2 I/O (x)APIC Version Register (01h)
The PID contains an I/O (x)APIC version register that identifies the type of I/O (x)APIC it
implements. Software can use this to provide compatibility between different I/O (x)APIC
implementations and their versions. The version register also contains the maximum RTE
Register Descriptions
.
Table 2-8. I/O (x)APIC Version Register Format
Register Offset: 01h Default Value: [003F00vvh]Attribute: Read-Only
Bit(s) Name Description
31:24 Reserved These eight bits are reserved
23:16 MAX REDIR This is the entry number (0 being the lowest entry) of the highest entry in the I/
15:8 Reserved These eight bits are reserved.
7:0 VERSION This is a version number that identifies the implementation version of the APIC
O RT. It is equal to the number of interrupt input pins minus one that the PID
supports. This field is hardwired and is read-only. The PID sets this field to
3FH, indicating that it supports 64 RTEs.
or SAPIC units in the PID. This field is hardwired and is read-only. When the
PID powers-up in APIC mode this field will return a value of 13H. When the
PID powers-up in SAPIC mode this field will return a value of 21H.
2.6.3.3 I/O (x)APIC Arbitration ID Register (02h)
This register contains the APIC bus arbitration priority for the PID. This register is loaded
whenever the PID’s (x)APIC ID register is loaded. A rotating priority scheme is used for APIC bus
arbitration. The winner of the arbitration becomes the lowest-priority agent and assumes an
arbitration ID of 0. All other agents except the agent whose ARBID is 15, increment their ARBID
by 1. The agent whose ARBID is 15 will take the winner’s ARBID and will increment it by 1.
ARBIDs are changed (incremented or assumed) only for messages that are successfully
transmitted. A message transmitted successfully means that no CS error or acceptance error was
reported for that message. The PID APIC ARBID is always loaded with the PID APIC ID during a
“INIT-level deassert” message.
Note: Only four bits are required for the APIC ARBID. Bits 27:24 are used for this ID.
Intel® 460GX Chipset Software Developer’s Manual 2-49
Register Descriptions
Table 2-9. I/O (x)APIC Arbitration ID Register Format
Register Offset: 02h Default Value: [00000000h]Attribute: Read-Only
Bit(s) Name Description
31:28 Reserved These four bits are reserved.
27:24 ARBID APIC Arbitration ID.
23:0 Reserved These 24 bits are reserved.
2.6.3.4 I/O (x)APIC RTE (10h-8Fh)
The interrupt RT has a dedicated entry for each interrupt input pin. Software can individually
choose the interrupt vector number for input pins. For each individual pin, the oper ating system can
also specify the signal polarity (low-active or high-active), whether the interrupt is signaled as
edges or levels, as well as the destination and delivery mode of the interrupt. The information in the
RT is used to generate the inter-(x)APIC message upon assertion/deassertion of the interrupt pin.
The PID’s version register contains the number of entries in the interrupt RT. Offsets 10h through
8Fh are used for the interrupt RT. Each entry in the table is 64-bits. The format of each entry is
described in Table 2-10.
Note: The interrupt RT is shared between SAPIC and APIC modes. Some of the fields have different
meanings in the two modes as indicated in Columns 2 and 3. The PID implements only those bits
that have valid functional fields associated with them. Reserved bits cannot be written and will
return 0s when read.
Since each RTE is 64 bits wide, it must be accessed using two 32-bit memory read or write
operations to consecutive dword-aligned addresses. The lower half of the entry, bits 31 through 0,
is located at the even offset (such as 10h) and the upper half of the entry, bits 63 through 32, is
located at the odd offset (such as 11h). While programming the RTEs, it is recommended that the
lower half be programmed first, followed by the upper half.
Table 2-10. I/O (x)APIC RTE Format
Register Offset: 10-8Fh Default Value: Undefined except mask bit is 1Attribute: Read/Write
Bit(s)
63:56 DEST ID DEST ID This field contains an (x)APIC ID. Local (x)APIC units receiving an interrupt
55:48 DEST EID Reserved This field contains the extended (x)APIC ID. Local (x)APIC units receiving an
47:32 Reserved Reserved These 16 bits are reserved
31:18 Reserved Reserved These 14 bits are reserved
SAPIC Mode
Name
17 FLUSHEN FLUSHEN This bit controls the flushing of the I/O buffer on a per-interrupt basis.
APIC Mode
Name
Description
message compare the DEST ID and DEST EID fields to the corresponding
fields in their LID registers to determine if the interrupt is to be serviced by
them.
interrupt message will use this field along with the DEST ID field to determine if
the interrupt is to be accepted by them. This field is not used during APIC
mode.
A 0 indicates that the buffer must be flushed before the interrupt is sent to the
local (x)APIC. This setting will cause the hardware flush control signals to be
used.
A 1 indicates that the buffer does not need to be flushed before the interrupt is
sent out to the local (x)APIC. This setting will cause the hardware flush control
signals to be ignored.
2-50 Intel® 460GX Chipset Software Develop er ’s Manual
Table 2-10. I/O (x)APIC RTE Format (Cont’d)
Register Offset: 10-8Fh Default Value: Undefined except mask bit is 1Attribute: Read/Write
Register Descriptions
Bit(s)
SAPIC Mode
Name
16 MASK MASK This bit masks the (x)APIC delivery of this interrupt.
15 TRIGGER
MODE
14 RIRR RIRR This bit is read-only. During (x)APIC mode, this bit is used for level-triggered
13 POLARITY POLARITY This bit specifies the polarity of each interrupt signal connected to the interrupt
12 DELIVERY
STATUS
APIC Mode
Name
TRIGGER
MODE
DELIVERY
STATUS
Description
A 0 indicates that delivery of this interrupt is not masked. An edge or level on
an interrupt pin that is not masked results in the delivery of the interrupt to the
destination.
A 1 indicates that delivery of this interrupt is masked. It is the software’s
responsibility to deal with the case where the mask bit is set after the interrupt
message has been accepted by a local (x)APIC unit but before the interrupt is
dispensed to the processor.
When the mask bit is 1, interrupts coming into the PID are routed to the INTIO,
I2O_INT#, or I2B pins, provided they are correctly mapped. No delivery status
bit latching is performed in this mode.
When the mask bit is a 0, interrupts are latched in the delivery status bit. If the
mask bit is set to a 1 after the interrupt is latched but before it is delivered, the
latched value will be held until the interrupt is unmasked and delivered.
The trigger mode field indicates the type of signal on the interrupt pin that
triggers an interrupt.
A 0 indicates edge sensitive.
A 1 indicates level sensitive.
interrupts. Its meaning is undefined for edge-triggered interrupts. For leveltriggered interrupts, this bit is set when the local (x)APIC(s) accepts the level
interrupt sent by the PID. The RIRR bit is reset when an EOI message is
received from the local (x)APIC.
pins of the PID. A value of 0 means the signal is high-active and a value of 1
means the signal is low-active. In the case of level, high-active means if the pin
is sampled high, it is considered active. In the case of an edge, high-active
means the low-to-high edge is considered active.
This bit is read-only. It holds the current status of interrupt delivery to the
processor. This bit functions differently depending on the Trigger Mode bit.
When the Trigger Mode bit indicates edge sensitive:
The Delivery Status bit is set when an active edge is detected on the interrupt
pin.
The Delivery Status bit is reset when the int errupt message is successfully sent
to the processor.
When the Trigger Mode bit indicates level sensitive:
The Delivery Status bit reflects the assertion of the pin. i.e. If the pin is at its
active level, according to its Polarity bit, the Delivery Status bit is set; If the pin
is at its inactive level, according to its Polarity bit, the Delivery status bit is
reset.
To accurately determine the delivery status of an interrupt in level mode the
RIRR bit must be considered as well as the Delivery Status bit.
Intel® 460GX Chipset Software Developer’s Manual 2-51
Register Descriptions
Table 2-10. I/O (x)APIC RTE Format (Cont’d)
Register Offset: 10-8Fh Default Value: Undefined except mask bit is 1Attribute: Read/Write
Bit(s)
10:8 DELIVERY
SAPIC Mode
Name
11 DESTINATION
MODE
MODE
7:0 VECTOR VECTOR This is the vector number identifying the interrupt being sent.
APIC Mode
Name
DESTINATION
MODE
DELIVERY
MODE
Description
This bit determines the interpretation of the destination field.
A 0 indicates physical mode. In physical APIC mode, a destination APIC is
identified by its ID. Bits 56 through 59 of the destination field specify the 4-bit
APIC ID. In physical SAPIC mode, the destination ID is defined by bit 63
through 48 of the destination field.
A 1 indicates logical mode. In logical APIC mode, destinations are identified by
matching on logical destination under the control of the destination format
register and logical destination register in each local APIC. Bits 56 through 63
(8 MSB) of the destination field specify the 8-bit APIC ID. In logical SAPIC
mode, the destination field bits 63 through 56 make up 8 bits of the destination
ID. The remaining 8 bits are bits 55 through 48 of the destination field and must
always be programmed to 0.
The delivery mode is a 3-bit field that specifies how the local (x)APIC units
listed in the destination field should act upon reception of this signal. Note that
certain delivery modes will only operate as intended when used in conjunction
with a specific trigger mode. These restrictions are indicated in the table below
for each delivery mode. Delivery mode encodings are shown below. Modes
001 and 010&Vector Field apply to APIC mode only:
00x (Fixed SAPIC Mode): This means deliver the interrupt on the INTR signal
of the processor listed in the destination. Trigger mode can be edge or level.
The least significant bit of this delivery mode is a HINT bit that is
communicated to the platform to allow it to redirect the interrupt to another
processor on the same processor system bus as the destination. The way this
redirection occurs is independent of platform implementation. Otherwise, the
processor can ignore the least significant bit.
000 (Fixed APIC Mode): This means deliver the signal on the INTR signal of
all processor cores listed in the destination field. Trigger mode for “fixed”
delivery mode can be edge or level.
001 (Lowest-Priority APIC Mode): This means deliver the interrupt on the
INTR signal of the processor core that is executing at the lowest-priority among
all the processors listed in the specified destination. Trigger mode for lowestpriority delivery mode can be edge or level.
010 (PMI or SMI): Delivery mode is edge only. For systems that rely on SMI
semantics, the vector is ignored but must be all zeros for future upgrades. For
systems that rely on PMI semantics, the vector number has meaning and is not
ignored.
011 (Reserved).
100 (NMI): This means deliver the interrupt on the NMI signal of the processor
listed in the destination. Vector information is ignored. The NMI is always
delivered as an edge-triggered interrupt. The trigger mode field is ignored.
101 (INIT): This means deliver the interrupt on the INIT signal of the processor
listed in the destination. Vector information is ignored.
110 (Reserved).
111 (ExtINT): This means deliver the interrupt to the processor listed in the
destination as an interrupt that originated in an externally connected (8259Acompatible) interrupt controller. The INT A cycle that corresponds to this ExtINT
delivery will be routed to the external controller that is expected to supply the
vector. A delivery mode of ExtINT requires an edge-triggered mode. ExtINT
should be targeted for only one processor.
2-52 Intel® 460GX Chipset Software Develop er ’s Manual
System Architecture 3
This chapter provides an explanation of the 460GX chipset’s handling of various aspects of the
system architecture. It covers coherency, ordering, interrupts and related issues.
3.1 Coherency
For any computer system, data coherency between processor caches and other elements within the
system is one of the main concerns of the system designer. In a Symmetric Multiprocessor (SMP)
system, hardware is usually required to maintain this coherency. In some instances, though,
software may assume responsibility for coherency. The use of WC (write-combining) memory
requires software to manage coherency. Coherency applies to the processor caches, the I/O subsystem and graphics traffic. The programming model for a particular architecture determines
precisely how the hardware must behave. A loosely coupled system may require that software
guarantee that different processors which need to use the same piece of data are able to do so. For
most SMP systems, the hardware in the system guarantees that a piece of data is updated to all
processors if it is shared. For coherent data or code, there can exist only one valid version. There
may be shared copies of this da ta or code, bu t all elements in the system have the same v alue. If th e
data is not coherent, then different elements may h ave differ ent values for the identical address . For
example, non-coherent AGP traffic is not kept coherent with processor caches, since non-coherent
AGP addresses are not snooped on the bus. Coherency is related to, but different than cacheability.
3.1.1 Processor Coherency
Intel processors do not have a specific bit to specify co heren cy fo r each trans action. Data and co de
are usually considered fully coherent with respect to other processors and to each other. There are
exceptions to this - such as the WC (write combining) memory type. Data that is marked as WC in
the page table will not be coherent between processors. The Itanium processor uses the standard
MESI (Modified/Exclusive/Shared/Invalid) protocol for its caches. As well, the Itan ium processor,
when in EM mode, does not guarantee in hardware that the instruction caches are coherent with
data transfers. Software must flush the i-cache and reload it when self-modifying code is running.
Processors maintain coherency with each o ther by p lacing th e ad dress es fo r r eferen ced memory on
the common system bus. Each of the other processors snoops this addres s to see if it has the data in
any of its own caches. If one has the data unmodified, then it signals this using the HIT# pin, and
memory, since it has the latest version of that address, provides the data. Both the responding and
the requesting processors will then go to the shared state in the cache. If the snooping processor has
the data modified, it asserts the HITM pin and provides the data, since it owns the most up-to-date
copy of that address. The memory system will also take the data provided and update the copy in
SDRAM, unless the OWN# signal is active, in which case the memory is not updated.
For WB memory space the MESI protocol requires that only one p roces sor h as a copy o f mod i fied
data. Therefore if processor A is writing the data, it was required to gain ownership of the line
before updating it, and as it gained ownership the other processors in the system would have gone
to the invalid state for that line.
Intel® 460GX Chipset Software Developer’s Manual 3-1
System Architecture
For WC memory, one processor may write to an address that is marked WC in its page table and
hold the write in its own data buffer, while waiting to write to the bus. If a different processor were
to read this address, the first processor does not snoop the WC holding registers and therefore
would not provide the newly written data. So the 2nd processor would get the data from memory
which is stale or un-updated with respect to the first processor.
Processor caches use physical addresses for indexing into the cache. The memory attributes are
marked in the page tables which are based on the virtual address. If the O/S points two virtual
addresses to the same physical page and provides different attributes for each, then coherency may
not be maintained between processors, since one may have used the virtual address that pointed to
the page as WB and the other one used a different virtual address that pointed to the sam e phy sical
page, but was marked WC. This is usually considered a programming error. It may be useful in
some applications, but software takes full respon sib ility for the results.
3.1.2 PCI Coherency
As well as processor to processor coherency, the I/O subsystem maintains coherency between
processor caches and transactions initiated on PCI or other I/O devices that are directed to memory .
This is done in hardware and therefore software is not required to flush caches before I/O
operations (as long as that page is not marked WC).
Reads originating from the I/O sub-system are presented to the system bus for snooping. If a
processor has the modified (dirty) data, then it provides it on the data bus and the SAC presents this
data back to I/O. If no cache has the data modified, then the data is provided by the SDRAMs.
Writes are presented to the system bus as well. This allows a new code or data page to be brought
in and the old page to be invalidated as the write is being done for each line. Writes may get a
HITM# snoop which causes the processor to write back the entire line and then having the I/O
write to overwrite the particular bytes it wishes to update.
3.1.3 AGP Coherency
AGP transactions originate from a graphics (or other) device resid ing in the one AGP slot provided
when using the GXB. There are 2 different types of transactions originating from a device in this
slot. The graphics card may do coherent or non-coherent transactions.
Non-coherent transactions are not required to be placed on the system bus (although they could be,
with some loss of bus ban dw idt h). The 460GX chipset implementati on do es not pass non-coherent
AGP traffic to the system bus. These addresses are sent directly to the memory queue. The
processor could still have these addresses cached. If the application wishes to do this, then it must
handle coherency itself. Software must flush the processor’s cache.
Coherent traffic from the graphics card is treated like coh erent PCI traf fic. Addresses are sent to the
system bus before being serviced by the memory system.
3.2 Ordering
Intel processors prior to the Itanium processor have used processor consistency for their ordering
model. The Itanium processor allows both a strongly ordered and a weakly ordered programming
model to be implemented.
3-2 Intel® 460GX Chipset Software Develop er ’s Manual
System Architecture
New EM code may be weakly ordered. To allow the processor to take advantage of this, the 460GX
chipset defers all reads and returns the data out-of-order to the processor. By returning data in an
out-of-order fashion, the DRAM’s may be accessed in an optimal manner. Accesses are sen t out o f
the memory queue to free banks of SDRAM’s. Thus, if consecutive addresses ar e to th e same bank,
instead of holding up all later accesses while doing the first 2 in order, later accesses may move
around the second access and allow data to move continuously from SDRAM to the system bus.
T o maintain ordering in the system, the processor issues an address and must wait until that address
has been accepted by the system, or in other words become g lobally visible. If the o peration is kept
in the in-order queue, then visibility occurs at the snoop phase with no defer. This means that
operation is not retried and visibility has been met. A read becomes visible when no later store can
change the value seen by the reading processor. A write becomes visible when all later reads will
see the result of that write. With this definition, the 460GX chipset is able to guarantee visibility is
met when the access is deferred, since it prevents any later access from affecting that read. Any
coherent write to that line would be retried until the read is complete. Writes to memory are posted
and so are immediately visible and complete from the system perspective.
There is no ordering relationship between the PCI command streams of an AGP card and its AGP
command streams. The AGP spec mandates certain ordering rules within each stream that are
visible by the graphics card, but the order in which the system does the transactions is not
specified. Therefore, the typical producer-consumer model can not be guaranteed by doing simple
reads and writes across command streams. The AGP card must first issue a “flush” command in
order to guarantee the AGP low-priority stream is observable in memory before sending a flag
(which indicates all the writes are visible to the processor) up the PCI stream.
3.3 Processor to PCI Traffic and PCI to PCI (Peer-toPeer) Traffic
Due to the limited number of resources for transactions directed to PCI, a transaction may be
retried if all the resources are utilized. It is possible for one processor or one PCI agent to keep
taking all the resources and preventing a different processor or PCI agent from making any forward
progress.
3.4 WXB Arbitration
The following topics highlight a few of the methods employed within the WXB for starvation
prevention.
3.4.0.1 WXB Arbitration at the PCI Bus
Arbitration for Inbound Transactions
The WXB implements a simple two-level PCI arbitration scheme in the same vein as th at of th e
PXB-C0. Access to inbound resources is subject to the PCI arbitration scheme and to inbound
resource management algorithms. Inbound Write Request (IWR) acceptance is subject to an IWR
starvation prevention mechanism while Inbound Read Request acceptance is subject to the
availability of either an invalid stream slot or to space in the Delayed Transaction Reservation
Buffer.
Intel® 460GX Chipset Software Developer’s Manual 3-3
System Architecture
Arbitration for Outbound Transactions
The WXB relies heavily on the PCIset core and the PCI Specification regarding transaction
ordering for dealing with starvation on outbound transactions. Once the WXB has won PCI
arbitration for an outbound transaction, the WXB will initiate the req ues t at the top of the
Outbound Transaction Queue (OTQ) unless there is a read within the Outbound Read Request
FIFO (ORRF). In this case, if the read at the top of the ORRF has already received some data, and
the transaction at the top of the OTQ is a read, it will be moved behind the read in the ORRF. The
read at the head of the ORRF will then be initiated on the PCI bus. The read at the head of the
ORRF will be moved to the back if it hasn’t already received some data. If, however, the
transaction at the top of the OTQ is a write, then the arbitration policy will be to choose, on a
round-robin basis, between the read at the head of the ORRF and the write. The write will attempt
to burst to the end of a cache line; if there are no reads in the ORRF at the end of the cache line
burst, the write will continue to burst to the end of the next cache line unless the MLT causes the
WXB to disconnect.
The IHPC will also participate in arbitration with the purpose of idling the PC I bus. Wh en the
IHPC has won grant, and FRAME# has deasserted, there will b e moments of inactivity as the IHPC
alters the state of various external signal and power control registers for one or more PCI slots.
3.5 Big-endian Support
The Itanium processor supports both little-endian and big-endian accesses. The chipset does not
need to know which mode the processor is in. The chipset provides data in the same manner in both
cases. There is no indication on the system bus which mode the processor is using.
3.6 Indivisible Operations
3.6.1 Processor Locks
The 460GX chipset supports locks on the system bus, done by the processor. These locked
transactions are either a series of atomic R ead-Write or Read-Read-Write-Write transactions. They
may be targeted to I/O devices or to SDRAM. See ‘Transactions’ Chapter for the flow for locks.
During the sequence, the system bus is locked and no other traffic can occur on that bus. Traffic
may be flowing throughout t he rest of the system, s uch as AGP to memory o r transact ions t hat stay
within the non-locked PCI buses.
The 460GX chipset does not sup por t lock s that cro ss devi ce bou nd ari es. In ot her wor ds , if the fir st
read in a locked sequence targets device X, then the remaining transactions in the lock (either R-WW or W) must also target device X. The only exception to this rule is when device firmware has
been “in-line shadowed” using the MAR registers. In this case the Read(s) in a locked sequence
can be mapped to the compatibility PCI bus, and the Writes(s) could be map ped to memory. When
a MAR has been mapped to write protect memory, a locked sequence to that MAR region is
completely redirected to PCI, in order to avoid the resource allocation problems associated with
crossing memory/PCI device boundaries. The 460GX chipset does not provide any special checks
to detect locks that cross device boundaries outside of the MARs. If software attempts to establish
such a lock, indeterminate results will occur: either the lock will appear to work, even thought the
access was not performed atomically, or a deadlock will result.
3-4 Intel® 460GX Chipset Software Develop er ’s Manual
AGP LOCKS
There is no LOCK signal on the AGP bus. However, legacy code that issues read-modify-write
(RMW) transactions could still be converted for use with an AGP device. The GXB will attempt to
establish a “pseudo-lock” to cover such an event. However, there is still a deadlock case within the
AGP controller that the GXB can not address. This case is covered in a “special design
considerations” section of the AGP specification.
The deadlock occurs when the device internally posts an inbound write after the first read
completes in a “R-R-W-W” locked sequence. The specification requires that the AGP master
resolve the problem in either software or hardware:
• Software must prevent the device driver from accessing internal registers with misaligned
reads while there are posted writes in the PCI interface. This works if the device never posts
writes, implements a unified interface (i.e.: no “internally posted” writes), or disallo ws
misaligned read access (no multi-word registers).
• Hardware allows the read to proceed even in the presence of the po sted write. Technically this
is a violation of protocol, but the master is at liberty to insure that internal status doesn’t get
updated on behalf of the “posted” write until that data actually leaves the part.
3.6.2 Inbound PCI Locks
System Architecture
The 460GX chipset does not support inbound locks.
3.6.3 Atomic Writes
Some system bus operations such as Write 8 bytes, Write 16 bytes and Write 32 bytes, are
indivisible operations on the system bus. However, since the PCI protocol allows target device to
disconnect at any point in a transfer sequence, these operations are not indivisible on the PCI bus.
Furthermore, these accesses cannot be locked because PCI specification allows use of locked
cycles only if the first transaction of the locked operation is a read. Therefore software must not
rely upon atomicity of system bus write transactions which are greater than 32 bits or Dword
misaligned once they are translated to the PCI bus.
3.6.4 Atomic Reads
The system bus memory read operations to PCI can request more than 32-bits of data (i.e. 8 byte,
16 byte and 32 byte). The problem of indivisibility of operations is very critical for this type of
transaction. The PXB does NOT Lock multi-cycle reads to guarantee atomicity. Note that
ATOMICITY of Host-PCI reads which are greater than 32 bits or are Dword misaligned is NOT
GUARANTEED.
The PXB can accept inbound reads and writes while an outbound read or write is in a partially
completed state.
3.6.5 Locks with AGP Non-coherent Traffic
AGP has a non-coherent stream that does not go over the system bus. Therefore processor locks,
whether established to memory or I/O, do not prevent the non-coherent AGP accesses from
occurring. If a processor reads a location in memory with a locked read, and then writes the same
Intel® 460GX Chipset Software Developer’s Manual 3-5
System Architecture
location, there is no guarantee that AGP has not written the location while the lock was activ e on
the system bus. AGP may read or w r ite thos e l ocati on s or any ot h er memo ry location, independent
of the processor lock.
3.7 Interrupt Delivery
Interrupts may be delivered to the processors over the system bus. The interrupts may come from
an I/O device or from another processor. The new system bus delivery method for interrupts to
Itanium processor is referred to as SAPIC.
For SAPIC, the interrupts appear on the bus with a specific encoding on the REQa/REQb signals.
The address used is 0x000FEEzzzzy. The 16 bits ZZZZ determine the target to which the interrupt
is being sent. Both I/O interrupts and inter-processor interrupts are delivered in this man ner. The
data field contains the interrupt vector.
Devices may send their interrupts to one specific processor, or have the system choose the
processor to which to deliver the interrupt. The algorithm used by the system to deliver interrupts
depends on the software. The chipset will have a register for each processor. This register, called
the XTPR (eXternal Task Priority Register), is programmable and may be set as software wishes.
One could use this feature for lowest-priority delivery, as one example. The processor updates its
XTPR when it updates its own internal priority register. An interrupt which is received by the
chipset with the redirectable hint bit set, will be sent to the processor with the lowest v a lue in th e
XTPR. If 2 or more processors tie for the lowest value, the processor with the lowest processor ID
will be selected.
The 4 XTPR registers in the 460GX chipset are updated when the processor does a special cycle on
the bus. When the special cycle is decoded, the low order 3 bits of the DID are used to determine
which register to update. Each XTPR register is disabled at reset, and requires a special cycle
XPTR-update to be enabled.
3.8 WXB PCI Hot-Plug Support
“Hot-Plug” is the term given to describe the capability to insert and remove PCI add-in cards into a
computer while the PCI bus itself and other subsystems in the computer are fully operational. HotPlug logic in the WXB supports system hot-plug capability by providing the state machines and
programming interface to individually power up and po wer down PCI slots in a contr olled fashion.
An Integrated Hot-Plug Controller (IHPC) comprises the hot-plug logic for one PCI bus.
Hot-Plug functionality in a complete system which includes the WXB requires three subsystems to
work together: (1) the software subsystem, including firmware and drivers, (2) the hardware logic
subsystem in the WXB, including hot-plug registers and memory and state machines, and (3) the
external hardware subsystem, including interlock s witches, shift registers , FETs, and LEDs on each
PCI bus.
The PCI hot-plug logic performs three sets of operations: reset, slot enable (power-up and connect
to bus), and slot disable (disconnect from bus and power-down). In normal operation, slot enable
and slot disable occur only un der software direction. Slot disa bl e may o ccur au t omati call y if a PCI
card generates a power fault or if the user opens an interlock switch to remove a powered-up PCI
card. The slot enable and disable sequences are briefly described below.
3-6 Intel® 460GX Chipset Software Develop er ’s Manual
3.8.1 Slot Power-up and Enable
T o power -up a PCI s lot, softw are sets a command bit in a regist er . Then t he hot-pl ug logic perf orms
the following steps:
1. Set PWREN active to the slot and clock the parallel latch.
2. Set CLKEN# active to the slot but do not clock the parallel latch.
3. Wa it 200 msec for slot power to stabilize, except in test mode.
4. Gain ownership of the PCI bus through arbitration.
5. Clock the parallel latch.
6. Release owne rship of the bus after 480 nsec.
7. Set RESET# inactive to the slot but do not clock the parallel latch.
8. Wait 200 msec for slot clock to stabilize, except in test mode.
9. Gain ownership of the PCI bus through arbitration.
10. Clock the parallel latch.
11. Release ownership of the bus after 480 nsec.
System Architecture
12. Set BUSEN# active to the slot but do not clock the parallel latch.
13. Wait 1000 msec for PCI card initialization, except in test mode.
14. Gain ownership of the PCI bus through arbitration.
15. Clock the parallel latch.
16. Release ownership of the bus after 480 nsec.
3.8.2 Slot Power-down and Disable
To power-down a PCI slot, software sets a command bit in a register. Then the hot-plug logic
performs the following steps:
1. Set BUSEN# inactive to the slot but do not clock the parallel latch.
2. Gain ownership of the PCI bus through arbitration.
3. Clock the parallel latch.
4. Release owne rship of the bus after 480 nsec.
5. Set RESET# active to the slot but do not clock the parallel latch.
6. Gain ownership of the PCI bus through arbitration.
7. Clock the parallel latch.
8. Release owne rship of the bus after 480 nsec.
9. Set CLKEN# inactive to the slot but do not clock the parallel latch.
10. Gain ownership of the PCI bus through arbitration.
11. Clock the parallel latch.
12. Release ownership of the bus after 480 nsec.
13. Set PWREN inactive to the slot and clock the parallel latch.
Intel® 460GX Chipset Software Developer’s Manual 3-7
System Architecture
3-8 Intel® 460GX Chipset Software Develop er ’s Manual
System Address Map 4
4.1 Memory Map
The Itanium™ processor supports a 44 bit addr ess s pace. Th e 46 0GX ch ips et supp orts o nly 36 bits
of the address bus for a 64 GB of physical memory and must address up to several GB of memory
mapped I/O space. The 460GX chipset attaches to A#[35:3].
The memory address space is divided into four regions: the 1 MB Compatibility Area, the 15 MB
Low Extended Memory region, the (4 GB minus 16 MB) Medium Extended Memory region, and
the (16 TB minus 4 GB) High Extended Memory region. The first three regions are divided into
multiple subregions, with dedicated purpose and semantics. The memory address map is illustrated
in Figure 4-1.
4.1.1 Compatibility Region
This is the range from 0-1 MB (0_0000 to F_FFFF). Addresses here may be directed to a PCI bus
(the compatibility bus) or main memory. Any DRAM located in this area that is not used as main
memory is not recovered. This region is divided into four subregions, some of which are further
subdivided. Regions below 1M that are mapped to memory ar e accessible by the processors an d by
any PCI bus.
Regions below 1M that are mapped to PCI are accessible by the processor, and by PCI devices on
the targeted PCI bus (in the case of the regions mapped by the MAR this means the compatibility
PCI bus; for the VGA region this means the PCI bus to which VGA is mapped). Parallel segment
peer-to-peer accesses are not supported below 1M; a PXB will either forward the access to memory
or let it be claimed/master abort on the PCI bus below it.
4.1.1.1 DOS Region
The DOS Region is the lowest 640 KB, in the address range 0h to 9_FFFFh. DOS applications
execute here. The lower 512K of this region is always mapped to main memory, and is accessible
by the processors and by any PCI bus. The upper 128K of this region can be mapped to either PCI
or main memory, and is mapped using one of the MAR registers. The range defaults to memory.
4.1.1.2 VGA Memory
The 128 KB Video Graphics Adapter Memory subregion (A_0000h to B_FFFFh) is normally
mapped to a video device on the compatibility PCI bus. Typically, this is a VGA controller. The
460GX chipset supports mapping this region to any of its logical PCI segments. At power-on this
space is mapped to the compatibility PCI bus.
4.1.1.3 C, D, and E Segments
The 192 KB C, D, and E Segments are divided into smaller blocks that can be independently
programmed as Mapped to Memory, Memory Write Protect, In-line Shadowed, or Mapped to PCI.
These regions are used to provide memory to PCI devices requiring memory space below 1 MB.
The MAR registers determine how each range is used. The default for these segments at power-on
is that they are mapped read/write to the PCI compatibility bus.
Intel® 460GX Chipset Software Developer’s Manual 4-1
System Address Map
Figure 4-1. System Memory Address Space
(16 TB-4GB)
(4 GB-16MB )
15 MB
1 MB
High
Extended
Memory
Medium
Extended
memory
Low
Extended
Memory
Compatibility
Area
FFF_FFFF_FFFF
1_0000_0000
10_0000
F_0000
System
Memory
Firmware,
Processor &
Chipset
Specific
System
Memory
System
Firmware
32
MB
64K
FFFF_FFFF
FF00_0000
FEC0_0000
FE00_0000
FE00_0000 -
(n x 32M)
High
System
Firmware
Processor
Specific
Chipset
Specific
n x 32M
PCI Gaps
16 MB
4 MB
12 MB
Areas are not
C, D, and E
Segments
192K
drawn to scale.
C_0000
VGA
128K
Memory
A_0000
512K-640K
DOS
Region
0
640K
4.1.1.4 System Firmware
The 64 KB region from F_0000h to F_FFFFh is treated as a single block. Read/Write attribute
enables defined in the MAR registers may be used to direct accesses to the compatibility PCI bus
or main memory. At power-on, this area is mapped by default to the PCI compatibility bus.
4-2 Intel® 460GX Chipset Software Develop er ’s Manual
4.1.2 Low Extended Memory Region
The 15 MB Low Extended Memory region is always mapped to main memory. Since the 460GX
chipset does not support ISA cards, there is no gap provided in this region.
4.1.3 Medium Extended Memory Region
The Medium Extended Memory region is divided into two primary regions: A fixed gap containing
the firmware area along with gaps for Itanium processor and chipset specific functions, and a
variable gap to support memory mapped I/O.
The fixed gap is between 4 GB and (4 GB minus 32 MB) and is always enabled. This region must
not be defined as WB. DRAM supported by the 460GX chipset that is masked by this hole is
remapped to an area over 4 GB. The fixed gap is further divided into three regions:
• The 4 GB to (4 GB minus 16 MB) region is reserved for system firmware. Addresses directed
to this area are always directed to the compatibility PCI bus.
• The (4 GB minus 16 MB) to (4 GB minus 20 MB) region is reserved for processor specific
functions. This region can be thought of as four 1 MB segments:
— FEF0_0000 - FEFF_FFFF: This segment is used for Local APIC messages. Neither
inbound nor outbound accesses to this region should be seen by the chipset. The chipset
claims outbound accesses to this region, and will forward reads to PCI 0a to be master
aborted and drops the writes. Inbound accesses to this region can only occur due to a
programming error or address parity error; firmware programs the Expander bridges to
prevent programming errors from reaching the SAC; address parity errors are protected
against at each of the major bus interfaces. Therefore the SAC does not require a defined
response for inbound requests that reach this area; the results are unpredictable.
System Address Map
— FEE0_0000 - FEEF_FFFF: This segment is used to deliver interrupts. The chipset claims
outbound accesses to this region, and will forward reads to PCI 0a to be master aborted
and drops the writes. Inbound writes to this region are translated to an interrupt command
encoding, forwarded to the system bus, and then claimed by the chipset. Reads to this area
are illegal.
— FED0_0000 - FEDF_FFFF: This segment is reserved. The chipset claims outbound
accesses to this region, and will forward reads to PCI 0a to be master aborted and drops
the writes. Inbound accesses to this region are illegal.
— FEC0_0000 - FECF_FFFF: This segment is used f or SAPIC messages. Th e chipset claims
outbound accesses to this region and forward them to the appropriate PCI bus. The
processors use this region to program the SAPIC or IOAPIC registers and for targeted
EOI writes. Inbound accesses to this region are illegal.
• The (4G minus 20M) to (4G minus 32M) region is reserved for chipset specific functions.
Inbound accesses to this region are expected only from the compatibility PCI bus from either a
server management or a validation card. IB accesses are directed to the system bus and then
forwarded to the appropriate PCI segment. This region is segmented as follows (unlisted
regions are reserved):
— FE20_0000 - FE3F_FFFF: This range is for programming the GART. Reads and writes
are sent to Expander port-2 to be forwarded to the GXB. If the DEVNPRES bit for Device
14 is set (meaning that there is no xXB attached to the Expander bus), then accesses to this
region will be forwarded to the compatibility bus for termination .
— FEB0_0CB0: This address is for a memory-mapped register in the SAC.
Intel® 460GX Chipset Software Developer’s Manual 4-3
System Address Map
— FEB0_0CC0: This address is used for BSP selection. It is a write once register in the
SAC.
Figure 4-1 shows how the SAPIC and GART spaces are allocated. There may be up to 255 I/O
SAPICs in the system. There is one region defined for the GART space.
4.1.3.1 Variable GAP
The variable gap starts at 4 G-32M, and can gr ow downwa rd in 32M incremen ts. This gap i s used to
provide memory mapped I/O spaces to all of the lo gical PCI buses (th is includes AGP bu ses) in the
system. Each logical PCI bus is allowed n x 32M of contiguous space. PCI bus #0 is allowed the
first a*32M below (4G-32M), PCI bus #1 is allowed the next b*32M, PCI bus #2 is allowed the
next c*32M, etc. The total gap size, n, is equal to a + b + c and so on. The combined size of the
variable and the fixed gaps must equal a multiple of 64 MB. Since the variable gap starts on a
32 MB boundary, the variable gap must total to an odd multiple of 32 MB. This limit is set up by
firmware and is a function of the memory controller design.
4.1.4 High Extended Memory (above 4G)
The entire address space above 4 GB is treated by the 460GX chipset as ordinary memory. The top
of system memory is calculated by firmware. Processor accesses above the top of system memory
are still claimed by the chipset, but are not forwarded to memory or PCI; instead they cause a
BINIT#. Inbound accesses to this region can only occur due to a programming or address parity
error. Firmware programs both the PXBs and GXBs with the Top of Memory value. A
programming error that results in a PXB access ab ov e the Top of Memory causes the PXB to route
the request as if it were to a peer PCI bus. Therefore the request goes throu gh the SAC decod er and
causes a BINIT#. A programming error that results in a GXB access above the Top of Memory
(detected after GART translation) causes the GXB to force a BINIT#. Address parity errors are
detected at each of the major bus interfaces.
4.1.5 Re-mapped Memory Areas
Any DRAM that lies behind an address that is mapped to PCI or is reserved in the region below
4 GB and above 1 MB is recovered. The memory that lies in the Medium Extended Memory
Region is moved so that it is addressed above 4 GB. This covers all addresses in the Medium
Extended Memory Region. For example, if there is 3 GB of memory and the Medium Extended
Memory Region is 2 GB total (covering PCI, AGP and the reserved area), then the first 2 GB of
addresses are directed to DRAM, the next 2 GB of addresses are directed to PCI or are AGP
addresses or reserved, and the address rang e between 4 GB and 5 GB would be d irected to DRAM.
In other words, to access the 2 GB+1 byte of memory, the processor would use address 4 GB+1,
since the physical address of 2 GB+1 is now mapped to PCI.
Any DRAM not used in the Low Extended Memory Region, i.e. the region below 1 MB is not
recovered. The DRAM in this region which has its address directed to PCI is simply lost to the
system.
4-4 Intel® 460GX Chipset Software Develop er ’s Manual
Figure 4-2. Itanium™ Processor and Chipset-specific Memory Space
System Address Map
FFFF_FFFF
FF00_0000
FEC0_0000
FE00_0000
System
Firmware
16 MB
Processor
Specific
4 MB
Chipset
Specific
12 MB
I/O reserved
1 MB
Interrupt Delivery
On system bus - 1MB
I/O reserved
1 MB
I/O SAPIC #255
I/O SAPIC
#3 to # 254
4KB each
I/O SAPIC #2
I/O SAPIC #1
I/O SAPIC #0
Chipset
Reserved
FEFF_FFFF
FEF0_0000
FEE0_0000
FED0_0000
FECF_F000
FEC0_3000
FEC0_2000
FEC0_1000
FEC0_0000
FEBF_FFFF
FE60_0000
PCI Bus mapping
of SAPIC addresses.
PCI Bus 2A
PCI Bus 1A
PCI Bus 0B
PCI Bus 0A
4.2 I/O Address Map
The 460GX chipset allows I/O addresses to be mapped to resources supported on the I/O buses
underneath the 460GX chipset controller. This I/O space is partitioned into sixteen 4K byte
segments. Each of the segmen ts can be indivi dually confi gured to any I/O bus. S egment 0 is al ways
assigned to the compatibility I/O bus (of which there is only one per system).
There are four classes of I/O addresses that are specifically decoded by the 460GX chipset:
• All I/O addresses less than 100h: These addresses are specifically decoded as “defer-only”
addresses. The SAC does not post any I/O accesses to this range, regardless of the state of the
I/O posting enable bit. This is necessary because I/O accesses below 100h have historically
had ordering side effects: e.g. accesses to the 8259 Interrupt Masks.
8 MB
GART Table
2 MB
Chipset
Reserved
2 MB
FE40_0000
FE20_0000
FE00_0000
Intel® 460GX Chipset Software Developer’s Manual 4-5
System Address Map
• I/O addresses used for VGA controllers: 03B0h-03BBh and 03C0h-03DFh. These addresses
are specifically decoded so they can be mapped to the PCI bus specified by the VGA Space
Register. An I/O access must be contained fully within the VGA I/O range to be remapped
(e.g. an I/O read spanning 03BBh and 03BCh would not be remapped because it crosses the
VGA I/O range). Posting of this range for writes is controlled by the state of the I/O pos ting
enable bit in the Software-Defined Configuration Register.
• I/O addresses used for the PCI Configuration Space Enable (CSE) protocol. The I/O add resses
0CF8h and 0CFCh are specifically decoded as part of the CSE protocol. These addresses, like
the I/O addresses less than 100h, are treated as “defer only” addresses.
• Posting for all other I/O addresses is controlled by the state of the I/O posting enable bit in the
Software-Defined Configuration Register. If this bit is set, I/O writes are posted. If this bit is
not set, all I/O writes are deferred. I/O reads are always deferred.
Note, the 460GX chipset does not support ISA expansion aliasing. The IFB supports a full I/O
space decode, so the compatibility issue will be drivers that rely o n the I/O aliasin g behavior.
Historically, the 64k I/O space actually was 64k+3 bytes. For the extra 3 bytes, A#[16] is asserted.
The 460GX chipset decodes only A#[15:3] when the request encoding indicates an I/O cycle.
Therefore accesses with A#[16] asserted are d ecod ed as if they were accesses to address 0 and will
be forwarded to the compatibility bus. Since they look like accesses less than 100h, they are always
deferred rather than posted. The full address is sent to the PXB and on to the compatibility PCI bus,
which therefore has PCI address bit A#[16] active.
At power-on, all I/O accesses are mapped to the compatibility bus. An I/O access is never
forwarded inbound by the chipset. The I/O address map is shown in Figure 4-3.
Figure 4-3. System I/O Address Space
1_0003
FFFF
F000
4000
3000
2000
1000
0000
+3 bytes
(Decoded
as 0_000X)
Segment 15
Segment 3
Segment 2
Segment 1
Segment 0
Compatibility
Bus Only
4-6 Intel® 460GX Chipset Software Develop er ’s Manual
System Address Map
4.3 Devices View of the System Memory Map
Figure 4-1 shows an Expander Bridge device’s view of system memory. The goal is to prevent
invalid accesses at the expander bridge level, since different expander bridge devices are allowed
to access different regions. For example, PXBs are allowed to access other logical PCI segments
and GXBs are not. The SAC does not perform special checking to prevent this, and therefore the
expander bridges must be set up by firmware accord ingly. An exception to this rule can be made if
the request is being routed to the system bus rather than d irectly to memo ry. For instance, accesses
above the T op of Memory are not b locked at the PXB level, but inst ead cause a BINIT# in the SAC
because they are guaranteed to go through the SAC’s decode logic since the PXB routes these
accesses to the system bus
Note: Figure 4-1 shows that parallel segment peer-to-peer accesses are only supported when initiat ed by
a PXB (GXBs are only allowed to initiate accesses directed to system memory) and directed to one
of the nx32M logical PCI segments (this segment can be anywhere except below the compatibility
PCI bus). Parallel segment peer accesses are not permitted anywhere below 1 MB, not even to the
VGA region. This means that if VGA is relocated below a GXB, a server management card on one
of the PCI buses in the system can no longer access the VGA range.
Figure 4-4. System Memory Address Space as Viewed from an Expander Bridge (PXB/GXB)
FFF_FFFF_FFFF
1_0000_0000
10_0000
F_0000
C_0000
A_0000
Processor &
System
Firmware
C, D, and E
512K-640K
0
System
Memory
Firmware,
Chipset
Specific
System
Memory
Segments
VGA
Memory
DOS
Region
Top of Memory
FFFF_FFFF
FF00_0000
FEC0_0000
32
MB
FE00_0000
FE00_0000 -
(n x 32M)
if enabled as memor y GAP (directed to a logical P CI segment),
all PXB’s must ignore and all GXBs must BINIT# after GART
if enabled as memory GAP (directed to the compatibility PCI bus),
all PXB’s mus t ignore and all GXBs must B INIT# after GART
if enabled as memory GA P (d irected to a log ical PCI segment),
all PXB’s must ignore and all GXBs must ignore in the PCI stream
but BINIT# after G A RT (allows AGP card to “talk to itself” in that region)
if enabled as a memory GAP (directed to the c ompatibility PCI bus),
all PXB’s must ignore and all GXB’s mu st BINIT# after GART
The term “ignore” from a PCI perspective means do not assert DEVSEL#;
instead allow request to master abort
All remaining regions are mapped to main memo ry and are always forwarded inbound
Notes:
using the “memory” route encoding
High
System Firmware
4G-16M to 4G-17M
4G-17M to 4G-18M
4G-18M to 4G-19M
4G-19M to 4G-20M
Chipset
Specific
n x 32M
PCI Gaps
PXB accesses above the Top of Memory
are routed as if to peer and therefore
go through the SAC decode and cause
a BINIT#; GXB must cause a BINIT#
after the GART
PXB must ignore
GXB must BINIT# after GART
PXB must ignore; GXB must BINIT# after GART
PXB/GXB allo w to interrupt delivery area
PXB defaults to memory so SAC must trap;
GXB must BINIT# after GART
PXB must ignore; GXB must BINIT# after GART
PXB allows (only recommended to use
from compatibility bus for server management)
GXB must BINIT# after GART
PXBs may support peer-to-peer; access es
to the PXB’s own PCI bus must be ignored;
accesses to other PCI buses can be directed
to the system bus so the SA C forwards
them to the targeted peer bus
GXBs can not allow peer-to-peer; accesses
to the GXB’s own PCI bus must be ignored
(allows AGP card to “talk to itself” in that)
region); accesses to any PCI bus that are found
after the GART must cause a BINIT #
Intel® 460GX Chipset Software Developer’s Manual 4-7
System Address Map
4.4 Legal and Illegal Address Disposition
Below is the disposition of addresses done by the Bus Interface Unit (BIU).
Table 4-1. Address Disposition
Address Range Outbound Inbound Dest. Decision
0-07FFFFh DRAM DRAM
080000h-09FFFFh DRAM DRAM MAR=11 or (Read and MAR= 01 and
PCI0a unclaimed MAR=00 or (Read and MAR=01 and
0A0000h-0BFFFFh DRAM DRAM VGASE=0
PCIx unclaimed VGASE=1
0C0000h-0EFFFFh
(divided into 12 regions of 4k
bytes)
0F_0000h-0F_FFFFh DRAM DRAM MAR=11 or (Read and MAR= 01 and
10_0000h - PCIS[7] DRA M DRAM PX B uses LXGB instead of PCIS[7]
PCIS[7] - FDFF_FFFFh PCIx PCIx PCIS register determines target PCI
FE00_0000h-FE1F_FFFFh undefined undefined This region is reserved.
FE20_0000h-FE3F_FFFFh Expander port-
FE40_0000h-FE5F_FFFFh undefined
FE60_0000h to FEBF_FFFFh Config unit or
FEC0_0000 to FECF_FFFFh PCI x unclaimed SAR, IOABASE (PXB)
FED0_0000h to FEDF_FFFFh PCI 0a or
FEE0_0000h to FEEF_FFFFh Interrupt
DRAM DRAM MAR=11 or (Read and MAR= 01 and
PCI0a unclaimed MAR=00 or (Read and MAR=01 and
PCI0a unclaimed MAR=00 or (Read and MAR=01 and
2 or PCI0A
Expander port
2 or PCI0A
undefined This region is reserved.
PCI-0a
dropped
Transaction;
Reads sent to
PCI 0a, writes
dropped
Config unit or
PCI-0a
PXB will
forward IB and
mark it to
memory.
interrupt fo r IB
write, PCI-0a
for read
no system bus LOCK#) or (Write and
MAR = 10)
system bus LOCK#) or (Read and
MAR=10) or (Write and MAR=01)
no LOCK#) or (Write and MAR = 10)
LOCK#) or (Read and MAR=10) or
(Write and MAR=01)
no LOCK#) or (Write and MAR = 10)
LOCK#) or (Read and MAR=10) or
(Write and MAR=01)
bus
On PCI if
MMBASE<=address<=MMT, then not
claimed. GXB: unclaimed
If DEVNPRES[14]=0, send to
Expander port 2, else send to PCI-0a
If <=8B then: if one of defined
registers read or write value, if not
then return all 1’s or terminate writes.
If >8B, then send to PCI-0a. NOTE:
Locks to this range are forbidden and
will hang the system
Reads are sent to PCI-0a for master
abort. Writes get No-Data response
and are dropped
Reads are sent to PCI-0a for master
abort. IB writes are turned to
interrupts. OB writes get No-Data
response and are dropped
4-8 Intel® 460GX Chipset Software Develop er ’s Manual
System Address Map
T a ble 4-1. Address Disposition (Cont’d)
Address Range Outbound Inbound Dest. Decision
FEF0_0000h to FEFF_FFFFh PCI0a unclaimed Reads are sent to PCI-0a for master
FF00_0000h to FFFF_FFFFh PCI0a unclaimed Firmware region always enabled
1_0000_0000h to TOM DRAM DRAM main memory (if present) above 4 GB
Above TOM na na BI NIT
abort. Writes get No-Data response
and are dropped. PXB never claims
this range
Note: Accesses listed as “unclaimed” in the table for inbound transactions assume the PXB is
programmed correctly . I f an access were received up the Expander b us that hits in the listed addr ess
range, then its behavior is the same as outbound transactions to the same range.
Note: The PXB will never respond to an access that it is the master for . This means that an OB access will
not be claimed by the PXB, even if that access hits a range to which the PXB would normally
respond with DEVSEL#.
Note: The only ranges the PXB doesn’t claim are MMBASE to MMT, FEF0_0000h to FEFF_FFFFh, and
4G-16M to 4G. If the PCI card initiates a request to any other address, it will be sent up as TPA o r
memory.
Intel® 460GX Chipset Software Developer’s Manual 4-9
System Address Map
4-10 Intel® 460GX Chipset Software Develop er ’s Manual
Memory Subsystem 5
The Intel 460GX chipset’s memory subsystem consists of the SAC’s DRAM controller, the SDC’s
buffering and datapath access, the MAC and MDC components, and the DRAMs themselves.
Table 5-1 summarizes the 460GX chipset’s general memory characteristics.
T able 5-1. General Memory Characteristics
DRAM Types Synchronous DRAM (SDRAM)
Maximum Memory Size Up to 4 GB using 16MB DIMM’s, up to 16 GB using 128 MB DIMM’s, or 64 GB
Minimum Memory 64 MB using 16MB DIMM’s, 256 MB using 1 GB DIMM’s
Memory Increment 64 MB is the smallest increment
Memory Modules 168 pin (x72) 3.3 volt DIMMs
DRAM Sizes 16 Mbit, 64 Mbit, 128Mbit, 256 Mbit
DIMMs/Row 4 DIMMs per row which must be populated as a unit
Rows/Stack Up to 4 rows per stack; may populate any number of rows
Stacks/Card 2 stacks per card; may populate either 1 or 2 stacks
Cards/System 2 cards per system; 1 card per memory port, may have either one or two cards
DRAM Types Synchronous DRAM (SDRAM)
using 1 GB DIMM’s
in the system
The SAC’s DRAM controller provides addresses and commands to the 2 MAC’s on each memory
card. The MAC generates row and column addresses for the DRAM array and controls the data
flow through the MDC. For proces sor- memory cycles, the addres s is received from the system b us,
and data flows through the SDC to/from the memory cards. For PCI-DRAM cycles, the address is
presented on the bus. The data moves between PCI and DRAM within the SAC/SDC, without
appearing on the system bus. AGP-DRAM cycles are done non-coheren tly (unless coher ent AGP is
being used) and therefore do not have their addresses placed on the bus. The data for AGP
transactions, like PCI cycles, flows to/from the DRAM within the SAC/SDC.
5.1 Organization
The 460GX chipset supports 1 or 2 memory cards. Each card supports up to 8 GB of memory using
128 MB DIMM’s (32 GB with 1 GB DIMM’s); 2 cards provide up to 16 GB of memory (64 GB
with 1 GB DIMM’s). There are 2 independent interfaces to the SAC/SDC from the memory
subsystem, running simultaneously. Each memory interface supports 1 card and has a 72-bit
datapath and a separate control path. Running at 266 MHz, each interface allows a 2.13 GB/s peak
transfer rate, for a total of 4.27 GB/s of Bandwidth. Figure 5-1 illustrates this maximum
configuration. platform.
Intel® 460GX Chipset Software Developer’s Manual 5-1
Memory Subsystem
Figure 5-1. Maximum Memory Configuration Using Two Cards
processor address bus
processor data bus
SAC
to PCI via expander bridge
MAa[24:0]
PB[71:0]
controls
MAb[24:0]
row 1 of 4
x 72
row 4 of 4
Stack L
x 72
MDC
x 72
288 bits
x 72 x 72
Stack A
MDa[71:0]
MDC
x 72
MDC MDC
288 bits
MDC MDC
x 72 x 72
MAC
SDC
MDb[71:0]
x 72
MDC MDC
288 bits
MAC
x 72
MAC
Stack R
x 72
row 1 of 4
x 72 x 72
row 4 of 4
288 bits
x 72
Stack B
x 72 x 72
memory card A
Each card is organized as 2 stacks of up to 4 rows each. A stack consists of 1 to 4 rows of DRAM
which share a common data bus. A row consists of the 4 DIMM sockets which have a common
address/control bus. A row is the minimum atomic unit that can be accessed. Each stack has a
separate data path from the MDC to the DRAMs. Data may be transferring on both stacks
simultaneously. For instance, on the same card, stack L could be doing a read while stack R is
doing a write, or both could be doing a read.
Each row represents a set of memory devices simultaneously selected by a RAS signal and having
a common address bus. Each ro w generates 2 88 bits (256 data, 32 E CC) of data. Each ro w uses 4 of
the x72 (168 pin) DIMMs. There may be multiple banks per row. For instance, SDRAMs have 2, 4
or 8 banks internal to the chip. Or the DIMM may be organized such that there are 2 groups of
memory on the DIMM itself (double-sided DIMMs), with 2 chips dotted together on the data pin.
Since a row provides 256 bits (32 bytes) of data, the 64 byte line transfers of the processor will
access a row twice to read or write the entire line. Data is interl eaved by the MDCs to exch ange 72
bits of data per transfer with the SDCs at the rate of one cache line every 30ns (2.13 GB/s) per
interface.
There is a separate address and control bus for each memory port, with 1 card on each port. These
are independent and may be driving address es at the same time. While one bus is dr iving a read, the
other could be driving a write from the write queue. This allows greater bandwidth and allows
writes to be done without interfering with read traffic.
A system may be built with only one card, and provide only half the possible bandwidth, or have
the memory on the motherboard itself. If there are 2 memory cards, then one is placed on each
interface. Average memory latency is a function of how many interleaves are available and
bandwidth. The present structure interleaves across cards first, then across stacks, and then rows.
With 2 cards, each having 2 stacks of memory, Line 0 would be on cardB/stackR, Line 1 would be
on cardA/stackR, Line 2 would be on card B/stackL, and Line 3 would be on cardA/stackL. See
5-2 Intel® 460GX Chipset Software Develop er ’s Manual
Figure 5-2 for an illustration. In theory all 4 of these lines co uld b e transferring data at the same
time. It would then be muxed by the MDC to the SDC and then by the SDC to the bus. This allows
data to be moved with no dead cycles on consecutive reads. Another possibility is that the data
from cardA is going to the system bu s, while the data from cardB is go ing to a PCI port. Since each
memory interface can support the transfer rate of 266 MT/s, data transfers to PCI are completely
overlapping transfers to the system bus such that there are no holes in the data traffic.
Table 5-2 gives a summary of the characteristics of memory configurations supported by the
460GX chipset.
Table 5-2. Minimum/Maximum Memory Size per Configuration
Memory Subsystem
Technology & Configuration
DRAM
16 Mb 2M x 8 2M x 72 No 9 64 MB 1 GB
2M x 8 2Mx72x2 Yes 18 128 MB 2 GB
4M x 4 4M x 72 No 18 128 MB 2 GB
4M x 4 4M x 72 x 2 Yes 36 256 MB 4 GB
64 Mb 8M x 8 8M x 72 No 9 256 MB 4 GB
8M x 8 8M x 72 x 2 Yes 18 512 MB 8 GB
16M x 4 16M x 72 No 18 512 MB 8 GB
16M x 4 16M x 72 x 2 Yes 36 1 GB 16 GB
128Mb 16M x 8 16M x 72 No 9 512 MB 8GB
16M x 8 16M x 72 x 2 Yes 18 1 GB 16 GB
32M x 4 32M x 72 No 18 1 GB 16 GB
32M x 4 32M x 72 x 2 Yes 36 2 GB 32 GB
256 Mb 32M x 8 32M x 72 No 9 1 GB 16 GB
32M x 8 32M x 72 x 2 Yes 18 2 GB 32 GB
64M x 4 64Mx72 No 18 2 GB 32 GB
64M x 4 64M x72 x 2 Yes 36 4 GB 64 GB
DIMM
Size
Double
Sided?
(Yes/no)
Number of
Chips/
DIMM
Memory Size
Min Max
5.1.1 DIMM Types
The 460GX will support PC-100 DIMM’s that meet the requirements defined in Table 5-3.
The only DIMMs supported are 3.3 volt 168 pin (x72) parts. These may be composed of 16Mb,
64Mb or 256Mb DRAMs. The 256Mb DRAMs must have a supply voltage of 3.3 volts.
The DIMMs used must have the serial presence detect (SPD) feature, since this is used to program
the chipset configuration registers. DIMMs not having SPD will be con sidered as not-present in the
system, since they are not visible to firmware.
DIMMs may have a buffer on the DIMM itself. The buffer can be used in a registered mode or a
pass-through mode. The 460GX will support both buffered and unbuffered DIMMs. It will support
the buffered DIMM in the pass-through mode, not the registered mode. Thus the timings of the
state machines in the MAC will be the same for both types of DIMM. DIMMs with 36 components
will be buffered. DIMMs with 9 or 18 components may be buffered.
Intel® 460GX Chipset Software Developer’s Manual 5-3
Memory Subsystem
5.2 Interleaving/Configurations
Maximum system bandwidth is obtaina ble in several ways. If the address pat terns are well-behaved
then one can use the page mode of the DRAM i tsel f to obt ain hi gh band widths. G enerally page hi ts
can sustain about 5 times the bandwidth of page misses with a one-bank memory system. In
systems with only several memory banks, designs tend to try and optimize the page hit rate to
increase bandwidth.
A second approach is to have as many parallel operations within the memory system as possible.
One can spread the addresses out across multiple DRAMs and have the data transfers in parallel.
This lends itself well to designs which require a large memory system of many gigabytes.
The 460GX will implement the second approach. It will attempt to increase the amount of
parallelization. Addresses will be spread out across mu ltiple rows and cards. Figure 5-2 shows the
address layout. It assumes that 2Mx72 DIMMs are used, so that each row is 64 MB. With all the
rows populated evenly we have 16 x 64 MB or 1 GB total memory space.
For sequential accesses, the addresses are laid out so that lines 0 and 1 can be accessed
simultaneously , and can be transferred in parallel up to th e final data transfer on the system bus. As
0 and 1 are being transferred, 2 and 3 can be started to the left stacks of each card and their data
transfer will be done immediately following that of 0 and 1. The SDC buffers the data and sends it
to the system bus with no dead cycles.
SDRAMs have at least two internal banks; 64Mb chips will generally have 4, and 256 Mb chips
may have 8 internal banks. The 460GX takes advantage of these banks as well. In Figure 5-2, the
rows are split into 2 halves. Since there are at least 2 banks in all SDRAMs, the system will
interleave assuming all DRAMs have only 2 banks, and be split as shown. So with 16 rows, each
split in 2, there is a 32 way interleaving scheme in a totally populated system.
The first 256 MB lies in the bottom 4 rows. The next 256 MB lies above that and so on up. This
allows multiple processes, which may be spread throughout memory, to also be interleaved.
Figure 5-2. Address Interleaving
768M+7,768M+15,...
768M+3,768M+11,...
512M+7,512M+15,...
512M+3,512M+11,...
256M+7,256M+15,...
256M+3,256M+11,...
Line 7,15,...
Line 3,11,...
768M+5,768M+13,...
768M+1,768M+9,...
512M+5,512M+13,...
512M+1,512M+9,...
256M+5, 256M+13,...
256M+1, 256M+9,...
Line 5,13,...
Line 1,9,...
768M+6,768M+14,...
768M+2,768M+10,...
512M+6,512M+14,...
512M+2,512M+10,...
256M+6,256M+14,...
256M+2,256M+10,...
Line 6,14,...
Line 2,10,...
768M+4,768M+12,...
768M,768M+8,...
512M+4,512M+12,...
512M,512M+8,...
256M+4, 256M+12,...
256M,256M+8,...
Line 4,12,...
Line 0,8,...
Card A
Card B
5-4 Intel® 460GX Chipset Software Develop er ’s Manual
5.2.1 Summary of Configuration Rules
The memory system may populate any row in any order. There are preferred ways of populating
the memory subsystem for performance, but all configurations will work.
The following rules summarize the way the memory system may be built up. The one hard rule is
that a given row must be popul ated with 4 of the same DIMMs. There is no mi xing allowed within
a row. If the 4 DIMMs within a row are not the same, there is no guarantee as to system behavior,
or that the system will even work.
• For each memory row, 4 DIMMs must be populated as a unit.
• The entire row must be populated with the exact same type of DIMM i.e. the same size,
number of sides, technology (16Mb vs. 64 Mb), etc.
• Different rows may use different size DIMMs (2Mx72 in row 1 and 4Mx72 in row 2).
• Different rows may mix x4 and x8 DRAMs.
• Different rows may mix double sided and single sided DIMMs.
• Any combination of rows may be populated in any order, though performance will be affected
by how the rows are populated.
• For highest performance, the total amount of memory in each stack should be the same.
Memory Subsystem
• Either one or both memory cards can be populated in the system.
• Any number from 0 to 8 memory rows on a card can be populated in the system.
5.2.2 Non-uniform Memory Configurations
The example in Figure 5-2 has all the memory rows populated and all rows have the same size
DIMMs. There is no requirement that memory be populated evenly. Some stacks may have fewer
populated rows than others and the sizes within each stack may differ. Performance will be optimal
with evenly populated rows. Knowing that users may not populate the card optimally, the 460GX
will attempt to spread addresses out as best it can in an unevenly populated system.
For an easy example, use the example above, and assume that there are 4 rows of memo ry such that
the first row of the first 3 stacks are populated with 4Mx72 DIMMs and the last stack has only
2Mx72 DIMMs; for a total of 448 MB. The addres ses are bro ken u p such that the firs t 25 6 MB are
interleaved on a 4 way basis. The remaining 192 MB is interleaved on a 3 way basis; since all the
addresses to the last (2Mx72 row) row have been used.
This algorithm is extended for multiple sizes and arrangements of populated rows. Each row is
broken into multiple chunks and the least common denominator is found across stacks. Whatever
the system configuration, there will be some level of interleaving between cards to increase
parallelism.
5.3 Bandwidth
Sustained bandwidth is a fun ction of tr affic pat terns as well as the system d esign and conf iguratio n.
Each memory port can transfer 16 bytes per clock. This is a peak of 2.13 GB/s per port.
Intel® 460GX Chipset Software Developer’s Manual 5-5
Memory Subsystem
5.4 Memory Subsystem Clocking
The DIMMs are clocked at half the system bus frequency. For the Itanium processor, this means
the DRAMs are clocked at 15 ns. Data is clocked out at the rate of 32B per 15 ns.
The following table lists the DRAM parameters used for the 460GX chipset.
Table 5-3. Required DRAM Parameters
Parameter Symbol
Clock cycle time at CL=2 Tck 15 ns.
Access time from CLK Tac 6 ns.
CAS Latency TCL 2
RAS latency 4
RAS cycle time Trc 6
RAS to CAS delay Trcd 2
RAS precharge Trp 2
Data to precharge Tdpl
a. The sum of Tdpl and Trp are equal to Tdal as defined in the PC SDRAM Specification.
5.5 Supporting Features
5.5.1 Auto Detection
The memory controller provides capability for auto-detection of SDRAM type installed in the
system during the system configuration and initialization, providing a Plug-and-Play DRAM
interface to the user. This is done through the Ser ial Presence Detect logic on the DIMM. Firmware
will read the Serial Presence Detect (SPD) for each row to determine the size of the memory in that
row. Firmware will then write the size and interleaving information into the SAC and MAC
through configuration cycles. Firmware will not have to go write data and see if it is ther e and do
any addressing schemes to understand the system configuration. It will simply read a configuration
register and then write a different configuration register with the chipset mapping. At the same time
Firmware can calculate total system memory.
Min.
(clocks)
a
Max.
(clocks)
1
5.5.2 Removing a Bad Row
A row of memory may have a chip or DIMM fail. If an un-correctable error occurs, the system will
machine-check, usually resulting in a reset. The 460GX will report which row failed. During the
next re-boot or at power on, if the memory test fails, firmware may map the failing row as if it
didn’t exist. Since firmware goes through and reads the SPD on each row to determine its size,
firmware can just set that particular row to a size of 0, as if it weren’t there. No addresses will then
be sent to that row . The entire ro w is remove d, even if on ly one side of a d ouble -sided DIMM w ere
bad. But only the failing row is disabled. All other rows are still present, and the interleavin g
scheme will make the maximum use of the remaining rows. For example, a system with 8 rows
populated that has one go bad will be restarted with 7 rows available.
5-6 Intel® 460GX Chipset Software Develop er ’s Manual
5.5.3 Hardware Initi alization
In order to decrease boot time of systems with large amounts of DRAM installed, hardware
initialization of memory will be supported. Since multi ple ro ws will be initialized simultaneously,
the memory system will be able to initialize to 0 about 8 times faster than having the processor
looping through memory with writes. The MDC will force all zeroes on the data lines, with good
ECC, and the MAC will cycle through the memory addresses generating writes. The main limiter
to the number of rows being simultaneously initialized is current draw on the DRAM. One row
from each of the 4 stacks across the 2 cards will be initialized concurrently.
5.5.4 Memory Scrubbing
Scrubbing is the operation of walking through all installed DRAM and looking for errors. Each line
is read and then written back, whether there is an error or not. Within the SAC there is an engine to
generate addresses to be placed in the memory queue. These addresses are placed directly into the
SAC memory queue and are not snooped on the system bus, nor are they checked for address
conflicts, since the read-modify-write is treated as an atomic operation.
A scrub address is generated every 65K (65536) clocks. For a system with 32 GB of memory, this
would walk through all memory every 3.2 days. The follow ing table s hows the approximate time to
scrub memory based on memory size. Scrub bing may be disabl ed through a con figuration bi t.
Memory Subsystem
Table 5-4. Scrubbing Time
Memory Size Time to Scrub
64 MB 10 minutes
128 MB 20 minutes
256 MB 40 minutes
512 MB 1.2 hours
1 GB 3 hours
2 GB 5 hours
4 GB 10 hours
8 GB 20 hours
16 GB 1.6 days
32 GB 3.2 days
64 GB 6.4 days
Intel® 460GX Chipset Software Developer’s Manual 5-7
Memory Subsystem
5-8 Intel® 460GX Chipset Software Develop er ’s Manual
Data Integrity and Error Handling 6
6.1 Integrity
This chapter explains the various errors in the chipset. Error handling requires catching the error,
containing it, notifying the system, and recovery or system restart. Different platforms have
different requirements for error handling. A server is most interested in containment. It wants bad
data to be stopped before it reaches the network or the disk. On the other hand workstations with
graphics may be less interested in containment. If the screen blips for one frame and the blip is
gone in the next frame, the error is transient, and may not even be noticed.
The 460GX chipset will attempt to accommodate both philosophies. It will allow certain errors to
be masked off, or will turn them into simple interrupts instead of fatal errors. Fatal errors are those
which require a re-boot, e.g. BINIT#. Some errors will always be fatal, such as protocol errors or
when the chipset has lost synchronization of queues or events. The user (OEM, O.S.) can decide
the behavior for data errors. These may be considered as fatal, for maximum containment, or they
may simply be reported as an interrupt while the system continues as best it can . If the data is
moving to graphics, then an error may be unn oticed. It is possib le that data entering memory as bad
is never used, and therefore never shows up as an error to any user.
Each error will not be individually maskable. In general there are only 2 modes - aggressive and
non-aggressive. In aggressive mode, every error - parity, protocol, queue management - will be
considered fatal and lead to a BINIT#. In the non-aggres sive mo de, many errors will be reported as
interrupts and not cause BINIT#. Even in non-aggressive mode, when the chipset has certain errors
and doesn’t know what to do with a transaction or seems out of sync across the chips, it will
BINIT#.
The chipset will report errors at their use, instead of their generation. Both the processor and the
chipset may ‘poison’ data. If the processor has an internal cache error, it may write out the data
with bad ECC. If the chipset has bad parity on I/O data, it will corrupt the data as it is passed along.
In both cases the data will be put in memory with bad ECC. If it isn’t used, then no error is
reported. If it is used, then the error is found at that point.
The 460GX chipset will isolate the error reporting as close to the error itself as possible. In some
cases this can be to a failing DRAM or PCI card. In others it will be for a PCI bus or Expander port.
6.1.1 System Bus
• The 460GX chipset provides ECC generation on data delivered to the system bus, and ECC
checking of data accepted from the system bus. Single-bit errors are cor rected; multi-bit error s
will write the data with bad ECC into the DRAM’s (poisoned data) or to I/O with bad parity.
• Parity bits are generated and checked independently for the system bus address lines, the
system bus request group, and the system bus response group. Errors typically result in the
assertion of BINIT#.
• A variety of system bus protocol errors are also detected, and will result in assertion of
BINIT#.
• The first instance of a bus error is logged with the address and error type. Additional status
flags indicate subsequent errors occurred.
• For I/O accesses, good ECC is always generated for data with no parity errors. For data with
bad parity, the data is poisoned with bad ECC as it’s returned to the processor.
Intel® 460GX Chipset Software Developer’s Manual 6-1
Data Integrity and Error Handling
6.1.2 DRAM
• The 460GX chipset provides ECC generation on all writes into the DRAM, and ECC checking
on all reads from the DRAM. Single-bit errors are corrected. Multi-bit errors will return
poisoned data. Both types of errors are logged, with the address and ECC bits for the data
being recorded. The row which failed, as well as the bit for single-bit errors, can be identified
by softwa re.
• The first instance of a single-bit error is logged. After the first error, additional status flags
indicate subsequent errors occurred. The first multi-bit error is logged, with a status bit
indicating there were more uncorrectable errors. In both cases, software can clear the error
register and reset the error capture logic.
• Single-bit errors are corrected as they are received.
• To facilitate component debug and diagnostics, the ECC code generated on writes into the
DRAM can be forced incorrect. A configuration bit, when set, will force the ECC bits that are
written into memory to be XOR’ed with the correct value. This will allow either single or
double bit failures to be generated in memory. When the data is read, the system should correct
the data and report the error for single-bit errors, or report the error for double bit errors while
passing bad ECC to the processor.
6.1.3 Expander Buses
• Parity bits are generated and checked inde pendently fo r each Ex pander bus. For error behavior
see Table 6-1.
• Hard Fail responses are supported.
• A mechanism for elevating fatal errors to BINIT# (XBINIT#) and non-fatal errors to BERR#
(XBERR#) is provided.
6.1.4 PCI Buses
• Parity bits are generated and checked independently for each PCI bus.
• Standard PCI checking for aborts, PERR# and SERR# are also done.
6.1.5 AGP
• There is no parity on the bus between the graphics card and the GXB when using AGP
protocol. Transactions using PCI protocol have parity as defined for the standard PCI bus.
• The GXB checks for illegal or unknown operations, Expander bus parity errors, or internal
parity errors.
• There is parity on the GART table.
6.1.6 Private Bus between SAC and SDC
• There will be parity on the 64 bit data bus. Errors on data into the SDC will poison the data in
the DB. Errors on data into the SAC will always be passed on without correction, with an
option to BINIT#.
• The command bus and ITID bus are parity protected. Parity erro rs on this bu s cause a BINIT# .
6-2 Intel® 460GX Chipset Software Develop er ’s Manual
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