Intel 440GX User Manual
Intel® 440GX AGPset
Design Guide
March 1999
Order Number: 290651-001
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Intel may make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order .
®
The Intel
440GX AGPset may contain design defects or errors which may cause the products to deviate from published specifications. Current
characterized errata are available on request.
2
I
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
Implementations of the I
North American Philips Corporation.
2
C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by:
calling 1-800-548-4725 or
by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1999
*Third-party brands and names are the property of their respective owners.
Intel® 440GX AGPset Design Guide
Contents
1 Introduction................................................................................................................1-1
1.1 About This Design Guide..............................................................................1-1
1.2 References....................................................................................................1-2
1.3 Intel
1.4 Design Recommendations............................................................................1-8
2 Motherboard Layout and Routing Guidel ine s ...... ....... ...... .........................................2-1
2.1 BGA Quadrant Assignment...........................................................................2-1
2.2 Board Description .........................................................................................2-3
2.3 Routing Guidelines........................................................................................2-5
2.4 Placement & Layout....................................................................................2-14
2.5 Post-Layout Simulation.............. ....... ...... ....... ...... ...... ....... ...... ....... ...... .......2-14
®
Pentium® II Processor / Intel® 440GX AGPset Overview ...................1-3
1.3.1 Intel
1.3.2 Intel
1.3.3 PCI-to-ISA/IDE Xcelerator (PIIX4E).................................................1-6
1.4.1 Voltage Definitions...........................................................................1-8
1.4.2 General Design Recommendations.................................................1-9
1.4.3 Transitioning from Intel
2.3.1 GTL+ Description.............................................................................2-6
2.3.2 GTL+ Layout Recommendations.....................................................2-6
2.3.3 Single Processor Design..................................................................2-6
2.3.4 Dual Processor Systems..................................................................2-8
2.3.5 Single Processor Systems—Single-End Termination (SET) ...........2-8
2.3.6 Additional Guidelines .....................................................................2-10
2.3.7 Design Methodology ......................................................................2-11
2.3.8 Performance Requirements...........................................................2-12
2.3.9 Topology Definition ........................................................................2-13
2.3.10 Pre-Layout Simulation (Sens i tivity Analysis). ....... ..........................2-13
2.5.1 Crosstalk and the Multi-Bit Adjustment Factor...............................2-15
®
Pentium® II Processor................... ...... ....... ...... ......................1 - 3
®
440GX AGPset ......................................................................1-4
1.3.2.1 System Bus Interface......................................................1-5
1.3.2.2 DRAM Interface..............................................................1-5
1.3.2.3 Accelerated Graphics Port Interface...............................1-5
1.3.2.4 PCI Interface...................................................................1-6
1.3.2.5 System Clocking.............................................................1-6
1.3.3.1 Instrumentation...............................................................1-7
1.3.3.2 Remote Service Boot......................................................1-7
1.3.3.3 Remote Wake-Up ...........................................................1-8
1.3.3.4 Power Management........................................................1-8
“
440BX AGPset to Intel“ 440GX
AGPset Design ................................................................................1-9
2.3.3.1 Single Processor Network Topology and Conditions......2-6
2.3.3.2 Single Processor Recommended Trace Lengths ...........2-7
2.3.4.1 Dual Processor Network Topology and Conditions........2-8
2.3.4.2 Dual Processor Recommended Trace Lengths..............2-8
2.3.5.1 Set Network Topology and Conditions ...........................2-8
2.3.5.2 SET Trace Length Requirements...................................2-9
2.3.6.1 Minimizing Crosstalk.....................................................2-10
2.3.6.2 Practical Considerations.............. ....... ...... ....... ...... .......2-10
Intel® 440GX AGPset Design Guide
iii
2.6 Validation....................................................................................................2-15
2.6.1 Flight Time Measurement ..............................................................2-15
2.6.2 Signal Quality Measurement..........................................................2-16
2.7 Timing Analysis...........................................................................................2-17
2.8 AGP Layout and Routing Guidelines..........................................................2-19
2.8.1 AGP Connector (“Up Option) Layout Guidelines ...........................2-19
2.8.2 On-board AGP Compliant Device (“Down” Option)
Layout Guidelines ...... ...... ....... ...... ............................................. ....2 - 20
2.9 82443GX Memory Subsystem Layout and Routing Guidelines..................2-22
2.9.1 100 MHz 82443GX Memory Array Considerations........................2-22
2.9.1.1 Matching the Reference Planes ...................................2-23
2.9.1.2 Adding Additional Decoupling Capacitor ......................2-23
2.9.1.3 Trace Width vs. Trace Spacing ....................................2-24
2.9.2 Memory Layout & Routing Guidelines ...........................................2-24
2.9.3 4 DIMM Routing Guidelines [NO FET]...........................................2-30
2.9.4 PCI Bus Routing Guidelines ..........................................................2-30
2.9.5 Decoupling Guidelines: Intel
2.9.6 Intel
®
440GX AGPset Clock Layout Recommendations................2-32
®
440GX AGPset Platform...............2-31
2.9.6.1 Clock Routing Spacing.................................................2-32
2.9.6.2 System Bus Clock Layout.............................................2-32
2.9.6.3 PCI Clock Layout..........................................................2-33
2.9.6.4 SDRAM Clock Layout...................................................2-33
2.9.6.5 AGP Clock Layout ........................................................2-34
3 Design Checklist........................................................................................................3-1
3.1 Overview.......................................................................................................3-1
3.2 Pull-up and Pull-down Resistor Values.........................................................3-1
3.3 Intel
®
Pentium® II Processor Checklist.........................................................3-2
3.3.1 Intel
3.3.2 Intel
3.3.3 Intel
®
Pentium® II Processor ...........................................................3-2
®
Pentium® II Processor Clocks................................................3-5
®
Pentium® II Processor Signals...............................................3-5
3.3.4 Uni-Processor (UP) Slot 1 Checklist................................................3-7
3.3.5 Dual-Processor (DP) Slot 1 Checklist..............................................3-7
3.3.6 Slot 1 Decoupling Capacitors ..........................................................3-7
3.3.7 Voltage Regulator Module, VRM 8.2 ...............................................3-7
3.4 Intel
®
440GX AGPset Clocks........................................................................3-8
3.4.1 CK100 - 100 MHz Clock Synthesizer...............................................3-8
3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer...............................................3-9
3.4.3 GCKE and DCLKWR Connection....................................................3-9
3.5 82443GX Host Bridge.................................................................................3-10
3.5.1 82443GX Interface.........................................................................3-10
3.5.2 82443GX GTL+ Bus Interface .......................................................3-12
3.5.3 82443GX PCI Interface..................................................................3-12
3.5.4 82443GX AGP Interface ................................................................3-13
3.6 Intel
®
440GX AGPset Memory Interface ....................................................3-14
3.6.1 SDRAM Connections.....................................................................3-14
3.6.2 DIMM Solution With FET Switches................................................3-15
3.6.3 Registered SDRAM .......................................................................3-15
iv
Intel® 440GX AGPset Design Guide
3.7 82371EB (PIIX4E).......................................................................................3-16
3.7.1 PIIX4E Connections...... ....... ...... ....... ...... ...... .................................3-16
3.7.2 IDE Routing Guidelines..................................................................3-20
3.7.2.1 Cabling..........................................................................3-20
3.7.2.2 Motherboard .................................................................3-20
3.7.3 PIIX4E Power And Ground Pins ....................................................3-22
3.8 PCI Bus Signals..........................................................................................3-22
3.9 ISA Signals .................................................................................................3-23
3.10 ISA and X-Bus Signals.. ....... ...... ....... ...... ....... .............................................3-23
3.11 USB Interface..............................................................................................3-24
3.12 IDE Interface...............................................................................................3-24
3.13 Flash Design...............................................................................................3-25
3.13.1 Dual-Footprint Flash Design ..........................................................3-25
3.13.2 Flash Design Considerations.........................................................3-25
3.14 System and Test Signals ............................................................................3-28
3.15 Power Management Signals.......................................................................3-28
3.15.1 Power Button Implementation........................................................3-30
3.16 Miscellaneous .............................................................................................3-31
3.17 82093AA (IOAPIC)......................................................................................3-32
3.18 Manageability Devices................................................................................3-33
3.18.1 Max1617 Temperature Sensor......................................................3-33
3.18.2 LM79 Microprocessor System Hardware Monitor..........................3-33
3.18.3 82558B LOM Checklist ..................................................................3-34
3.18.4 Wake On LAN (WOL) Header........................................................3-35
3.19 Software/BIOS ............................................................................................3-35
3.19.1 USB and Multi-processor BIOS .....................................................3-35
3.19.2 Design Considerations...................................................................3-36
3.20 Thermals / Cooling Solutions......................................................................3-36
3.20.1 Design Considerations...................................................................3-36
3.21 Mechanicals................................................................................................3-36
3.21.1 Design Considerations...................................................................3-37
3.22 Electricals....................................................................................................3-37
3.22.1 Design Considerations...................................................................3-37
3.23 Layout Checklist..........................................................................................3-38
3.23.1 Routing and Board Fabrication......................................................3-38
3.23.2 Design Consideration.....................................................................3-38
3.24 Applications and Add-in Hardware..............................................................3-38
3.24.1 Design Consideration.....................................................................3-38
4 Debug Recommendations ......... ............................................. ....... ...... ....... ...............4- 1
4.1 Slot 1 Test Tools...........................................................................................4-1
4.2 Debug/Simulation Tools....... ...... ............................................. ....... ...... ....... ..4-1
4.2.1 Logic Analyzer Interface (LAI)..........................................................4-1
4.2.2 In-Target Probe (ITP).......................................................................4-1
4.2.3 Bus Functional Model (BFM) ...........................................................4-2
4.2.4 I/O Buffer Models.............................................................................4-2
4.2.5 FLOTHERM* Model.........................................................................4-2
Intel® 440GX AGPset Design Guide
v
4.3 Debug Features............................................................................................4-2
4.3.1 Intel
®
Pentium® II Processor LAI Issue ...........................................4-2
4.3.2 Debug Logic Recommendations......................................................4-4
4.3.2.1 Debug Considerations....................................................4-5
4.3.3 Debug Layout ..................................................................................4-5
4.3.3.1 Design Considerations ...................................................4-5
4.3.4 Debug Procedures...........................................................................4-5
5 Third-Party Vendor Information .................................................................................5-1
5.1 Processors....................................................................................................5-1
5.1.1 Voltage Regulator Modules .............................................................5-2
5.1.2 Voltage Regulator Control Silicon....................................................5-2
5.2 Intel
®
440GX AGPset ...................................................................................5-3
5.2.1 Clock Drivers ...................................................................................5-3
5.2.2 Power Management Components ....... ...... ...... ....... ...... ....... ...... ......5-3
5.2.3 FET Switches(4 DIMM/FET Design)................................................5-3
5.3 Other Processor Components ......................................................................5-4
5.3.1 Slot 1 Connector..............................................................................5-4
5.3.2 Mechanical Support .........................................................................5-4
5.3.3 Heat sinks........................................................................................5-4
5.3.4 Heat sink attachment: Rivscrews* and associated tools..................5-4
5.3.5 Thermal interface materials .............................................................5-4
A Intel
®
440GX AGPset Platform Reference Design................................................... A-1
vi
Intel® 440GX AGPset Design Guide
Figures
1-1 Intel® Pentium® II Processor / Intel® 440GX AGPset
System Block Diagram..................................................................................1-4
2-1 Major Signal Sections (82443GX Top View).................................................2-1
2-2 Example ATX Placement for a UP Pentium
2-3 Example NLX Placement for a UP Intel
®
Intel
440GX AGPset Design .......................................................................2-2
®
Intel
440GX Design.....................................................................................2-3
®
II processor/
®
Pentium® II processor /
2-4 Four Layer Board Stack-up...........................................................................2-4
2-5 Six Layer Board Stack-up With 4 Signal Planes and 2 Power Planes..........2-4
2-6 Six Layer Board Stack-up With 3 Signal Planes and 3 Power Planes..........2-5
2-7 Recommended Topology for Single Processor Design ................................2-6
2-8 Solution Space for Single Processor Design (Based on Results
of Parametric Sweeps)..................................................................................2-7
2-9 Recommended Topology for Dual Processor Design...................................2-8
2-10 Topology for Single Processor Designs With Single-End
Termination (SET).........................................................................................2-9
2-11 Solution Space for Single Processor Designs With Single-End
Termination (SET).........................................................................................2-9
2-12 GTL+ Design Process.................................................................................2-12
2-13 Pre-layout simulation process.....................................................................2-14
2-14 AGP Connector Layout Guidelines.............................................................2-19
2-15 On-board AGP Compliant Device Layout Guidelines.................................2-21
2-16 FET Switch Example............................................ ...... ....... ...... ....... .............2-22
2-17 Registered SDRAM DIMM Example...........................................................2-23
2-18 Matching the Reference Planes and Adding Decoupling Capacitor..........2-24
2-19 4 DIMMs (Single or Double-Sided) .............................................................2-24
2-20 Motherboard Model—Data (MDxx), 4 DIMMs.............................................2-25
2-21 Motherboard Model—DQMA[0,2:4,6:7], 4 DIMMs......................................2-26
2-22 Motherboard Model—DQM_A[1,5], 4 DIMMs.............................................2-26
2-23 Motherboard Model—DQM_A[1,5], 4 DIMMs.............................................2-26
2-24 Motherboard Model—DQM_B[1,5], 4 DIMMs.............................................2-27
2-25 Motherboard Model—CS_A#/CS_B#, 4 DIMMs.........................................2-27
2-26 Motherboard Model—SRAS_A#, 4 DIMMs.................................................2-27
2-27 Motherboard Model—Data (MDxx) Lines, 4 DIMMs (No FET) ...................2-30
2-28 PCI Bus Layout Example............................................................................2-31
2-29 82443GX Decoupling..................................................................................2-31
2-30 Clock Trace Spacing Guidelines.................................................................2-32
2-31 AGP Clock Layout.......................................................................................2-34
3-1 Pull-up Resistor Example..............................................................................3-2
3-2 GCKE & DCLKWR Connections...................................................................3-9
3-3 Current Solution With Existing FET Switches.............................................3-15
3-4 Series Resistor Placement for Primary IDE Connectors.............................3-21
3-5 Dual Footprint Flash Layouts......................................................................3-25
3-6 nterfacing Intel’s Flash with PIIX4E in Desktop ..........................................3-26
3-7 Interfacing Intel’s Flash with PIIX4E in Desktop .........................................3-28
3-8 PWRGOOD & PWROK Logic.....................................................................3-29
4-1 LAI Probe Input Circuit..................................................................................4-3
Intel® 440GX AGPset Design Guide
vii
Tables
2-1 Recommended Trace Lengths for Single Processor Design........................2-7
2-2 Recommended Trace Lengths for Dual Processor Designs2.......................2-8
2-3 SET Trace Length Requirements.............................................. ....... ...... ......2-9
2-4 Recommended 100 MHz System Flight Time Specs .................................2-13
2-5 System Timing Requirements for Validating Setup/Hold Windows ............2-16
2-6 Ringback Guidelines at the Intel
2-7 Intel
®
Pentium® II Processor and Inte®l 440GX AGPset
®
Pentium® II Processor Edge Fingers...2-16
System Timing Equations...........................................................................2-17
2-8 Intel
®
Pentium® II Processor and Intel® 440GX AGPset
System Timing Terms.................................................................................2-17
2-9 Intel
®
Pentium® II Processor and Intel® 440GX AGPset 100 MHz
Timing Specifications..................................................................................2-18
2-10 Recommended 100 MHz System Timing Parameters................................2-18
2-11 Recommended 100 MHz System Flight Time Specs .................................2-18
2-12 Data and Associated Strobe.......................................................................2-19
2-13 Source Synchronous Motherboard Recommendations..............................2-20
2-14 Control Signal Line Length Recommendations ..........................................2-20
2-15 Source Synchronous Motherboard Recommendations..............................2-21
2-16 Control Signal Line Length Recommendations ..........................................2-21
2-17 MDx lines Reference Planes Routing.........................................................2-23
2-18 FET Switch DQ Route Example .................................................................2-25
2-19 Motherboard Model: SRAS_B#, 4 DIMMs..................................................2-28
2-20 Motherboard Model: SCAS_A#, 4 DIMMs..................................................2-28
2-21 Motherboard Model: SCAS_B#, 4 DIMMs..................................................2-28
2-22 Motherboard Model: WE_A#, 4 DIMMs......................................................2-29
2-23 Motherboard Model: WE_B#, 4 DIMMs......................................................2-29
2-24 Motherboard Model: MA_A[14:0], 4 DIMMs ...............................................2-29
2-25 Motherboard Model: MA_B[12,11,9:0]#, MA_B[14,13,10], 4 DIMMs..........2-30
3-1 Slot Connectivity...........................................................................................3-2
3-2 GND & Power Pin Definition......... ....... ...... ............................................. ......3-4
3-3 Processor Frequency Select.........................................................................3-8
3-4 82443GX Connectivity................................................................................3-10
3-5 Strapping Options.......................................................................................3-13
3-6 SDRAM Connectivity ..................................................................................3-14
3-7 PIIX4E Connectivity....................................................................................3-16
3-8 IDE Series Termination...............................................................................3-20
3-9 PIIX4E PWR & GND...................................................................................3-22
3-10 Non-PIIX4E PCI Signals.............................................................................3-23
3-11 Non-PIIX4E ISA Signals .............................................................................3-23
3-12 Non-PIIX4E IDE..........................................................................................3-24
3-13 Flash Vpp Recommendations....................................................................3-27
5-1 Slot 1 Connector...........................................................................................5-1
5-2 Retention Mechanism, Retention Mechanism Module
Attach Sink Suppor.......................................................................................5-1
5-3 GTL+ Bus Slot 1 Terminator Cards ..............................................................5-1
5-4 Voltage Regulator Modules ..........................................................................5-2
5-5 Voltage Regulator Control Silicon Vendors ..................................................5-2
5-6 Clock Driver Vendors....................................................................................5-3
5-7 Power Management Component Vendors. ....... ...... ...... ....... ...... ....... ...... ......5-3
5-8 FET Switch Vendors.....................................................................................5-3
viii
Intel® 440GX AGPset Design Guide
Revision History
Date Revision Description
3/99 -001 Initial Release.
Intel® 440GX AGPset Design Guide
ix
x
Intel® 440GX AGPset Design Guide
Introduction
1
Introduction
Introduction
This document provides design guidelines for developing Intel® Pentium® II processor / Intel®
440GX AGPset based systems. Motherboard and memory subsystem design guidelines are
covered. Special design recommendations and concerns are presented. Likely design issues have
been identified and included here in a checklist format to alleviate problems during the debug
phase. One reference board design is presented:
Dual Processor (DP), 4 DIMM design
•
These designs use the Intel
82443GX Host Bridge and the 82371EB PIIX4E.
Note: The Intel
processor will also be offered as an Intel boxed processor, intended for system integrators who
build systems from motherboards and other components. Some hints for early debug problems are
also included.
®
Pentium® II processor may be installed in a Slot 1 connector. The Intel® Pentium® II
1.1 About This Design Guide
This document is intended for hardware design engineers who are experienced in the design of PC
motherboards or memory subsystem. This document is organized as follows:
®
Pentium® II processor and Intel® 440GX AGPset consisting of the
1
Chapter 1, Introduction. This chapter provides an overview of the features on reference design.
Chapter 1 also provides a general component overview of the Intel
Intel 440GX AGPset. The Wired for Management Initiative is also discussed which is an Intel
initiative to improve the manageability of desktop, mobile, and server systems. This chapter also
provides design recommendations which Intel feels will provide flexibility to cover a broader range
of products within a market segment.
Chapter 2, Motherboard Layout and Routing Guidelines. This Chapter provides detailed
layout, routing, and placement guidelines for the motherboard and memory subsystem. Design
guidelines for each bus (Host GTL+, PCI, DRAM, and AGP) are covered. This chapter provides
details on design methodology, Timing analysis, simulation, and design validation.
Chapter 3, Design Checklist. This chapter provides a design checklist that is intended to be used
when reviewing your Intel
AGPset reference design provided in this Design Guide. Items which have been found to be
incorrect on previous design s are p rovided as a tool to allow the quick debug of In tel
processor based systems.
Chapter 4, Debug Recommendations. This chapter presents debug recommendations that may
assist in the development of the Intel
utilizing them. This chapter also provides tool information, logic suggestions, technical support
options, and a summary of the problems which have been found to be associated with system
debug.
Chapter 5, Third Party Vendor Information. This chapter includes information regarding
various third-party vendors who provide products to support the Intel
Appendix A, Intel
schematics used in the single processor and dual processor reference designs.
®
440GX AGPset design. The checklist is based on the Intel® 440GX
®
Pentium® II processor, Intel® 440GX AGPset, and prod ucts
®
440GX AGPset Reference Design Schematics. This appendix provides the
®
Pentium® II processor and
®
Pentium® II
®
440GX AGPset.
®
Intel® 440GX AGPset Design Guide
1-1
1.2 References
Introduction
•
Intel® Pentium® II Processor Datas
•
Intel® 440GX AGPset
•
Intel 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4)
•
Intel Architecture Software Developer’s Manual
(order number 243190)
•
Intel Architecture Software Developer’s Manual
(order number 243191)
•
Intel Architecture Software Developer’s Manual
(order number 243192)
•
Intel Architecture MMX™ Technology Developer’s Guide
•
AP-485 CPUID Application Note
•
AP-585 Layout Application Note
•
AP-586 Thermal Application Note
•
AP-587 Power Application Note
•
AP-589 EMI
•
AP-524 Intel® Pentium® Pro Processor GTL+ Layout Guidelines
•
AP-525 Intel® Pentium® Pro Processor Thermal Design Guidelines
•
Multi-Processor Specification 1.4
•
+ Processor Fan/Heat Sink Target Specification
•
+ Slot 1 Test Kit User’s Guide
•
+ Slot 1 Processor Enabling Technologies Supplier Guide
•
PCI Local Bus Specification
•
Universal Serial Bus Specification
(WWW; order number 243334)
Datasheet (WWW; order number 290638)
heet
Datasheet (WWW; order number 290562)
, Volume 1; Basic Architecture
, Volume 2; Instruction Set Reference
, Volume 3; System Programming Guide
(order number 243006)
(WWW; order number 41618)
(WWW; order number 243330)
(WWW; order number 243331)
(WWW; order number 243332)
(order number 242016)
, Revision 1.0 or later
, Revision 1.0 or later
, Revision 3.0
, Revision 2.1
, Revision 1.0
(order number 242765)
(order number 242766)
Intel® 440GX AGPset Design Guide
1-2
Introduction
1.3 Intel® Pentium
Overview
The following is a list of features that a Intel® Pentium® II processor / Intel® 440GX System will
provide:
Full Support for up to two Intel® Pentium® II processors, with system bus frequencies of
•
100 MHz
Intel® 440GX AGPset
•
— 82443GX Host Bridge Controller (GX)
— 82371EB PCI ISA IDE Accelerator (PIIX4E)
100 MHz Memory Interface: A wide range of DRAM support including
•
— 64-bit memory data interface plus 8 ECC bits and hardware scrubbing
— SDRAM (Synchronous) DRAM Support
— 16Mbit, 64Mbit, 128Mbit, and 256Mbit DRAM Technologies
4 PCI Add-in Slots
•
— PCI Specification Rev 2.1 Compliant
1 AGP Slot:
•
— AGP Interface Specification Rev 1.0 Compliant
®
II Processor / Intel
®
440GX AGPset
— AGP 66/133 MHz, 3.3V device support
Integrated IDE Controller with Ultra DMA/33 support
•
— PIO Mode 4 transfers
— PCI IDE Bus Master support
Integrated Universal Serial Bus (USB) Controller with 2 USB ports
•
Integrated System Power Management Support
•
On-board Floppy, Serial, Parallel Ports, ISA Add-in slots
•
I/O APIC device support for MP interrupt support
•
1.3.1 Intel® Pentiu m®
The Intel® Pentium® II processor is a follow-on to the Intel® Pentium® Pro processor. This high
performance Intel Architecture processor offers features that can be designed into products for the
following market segments:
Desktop Home Market Segment
Desktop Corporate Market Segment
Workstation Market Segment
Server Market Segment
New applications and hardware add-ins from third party vendors are being developed that take
advantage of the MMX™ technology incorporated into the Intel
contact your local Intel field sales representative for information on IHVs and ISVs utilizing Intel’s
MMX™ technology.
Processor
II
®
Pentium® processor. Please
Intel® 440GX AGPset Design Guide
1-3
Intel introduced the Intel® Pentium® II processor as 350/100 and 400/100 speeds with 512 KB L2
cache versions.
1.3.2 Intel® 440GX AGPset
The Intel® 440GX AGPset is the fourth generation chipset based on the Inte l® Pentium® Pro
•
processor architecture. It has been designed to interface with the Intel
processor’ s system bu s at 100 MHz. Along with its Host-to-PCI bridg e interface, the 8 2443GX
host bridge controller has been optimized with a 100 MHz SDRAM memory controller and
data path. The 82443GX also features the Accelerated Graphics Port (AGP) interface. The
82443GX component includes the following functions and capabilities:
Support for single and dual Intel® Pentium® II processor configurations
•
64-bit GTL+ based system data bus Interface
•
32-bit system address bus support
•
64/72-bit main memory interface with optimized support for SDRAM
•
32-bit PCI bus interface with integrated PCI arbiter
•
AGP interface with up to 133 MHz data transfer rate
•
Extensive data buffering between all interfaces for high throughput and concurrent operations
•
Figure 1-1.
®
Pentium® II Processor / Intel® 440GX AGPset System Block Diagram
Intel
®
Pentium® II
Introduction
Video
- DVD
- Camera
- VCR
Display
TV
Video BIOS
- VMI
- Video Capture
Graphics
Encoder
2 IDE Ports
(Ultra DMA/33)
Device
Local Memory
2 USB
Ports
System BIOS
2X AGP Bus
Graphics
USB
USB
Pentium®
Processor
82443GX
Host Bridge
II
Host Bus
82371EB
(PIIX4E)
(PCI-to-ISA
Bridge)
Pentium®
Processor
72 Bit
w/ECO
100 MHz
SDRAM Support
Primary PCI Bus
(PCI Bus #0)
System Mgnt (SM) Bus
ISA Bus
II
Main
Memory
PCI Slots
IO
APIC
ISA Slots
sys_blk.vsd
Intel® 440GX AGPset Design Guide
1-4
Introduction
Figure 1-1 shows a block diagram of a typical platform based on the Intel® 440GX AGPset. The
82443GX system bus interface supports up to two Intel
bus frequency of 100 MHz. The physical interf ace design is based on the GTL+ specif ication and is
compatible with the Intel
DRAM interface (64-bit Data plus ECC). This interface supports 3.3V DRAM technologies.
The 82443GX is designed to support the PIIX4E I/O bridge. The PIIX4E is a highly integrated
multifunctional component that s up ports the following functions and capabilities:
PCI Rev 2.1 compliant PCI-to-ISA Bridge with support for 33 MHz PCI operations
•
ACPI Desktop Power Management Support
•
Enhanced DMA controller and standard interrupt controller and timer functions
•
Integrated IDE controller with Ultra DMA/33 support
•
USB host interface with support for 2 USB ports
•
System Management Bus (SMB) with support for DIMM Serial Presence Detect
•
Support for an external I/O APIC component
•
®
440GX AGPset solution. The 82443GX provides an optimized 72-bit
1.3.2.1 System Bus Interface
The Intel® Pentium® II processor supports a second level cache size of 512 KB with ECC. All
cache control logic is provided on the processor. The 82443GX supports a maximum of 32 bit
address or 4 GB memory address space from the processor p erspecti ve. The 8244 3GX provi des bus
control signals and address paths for transfers between the processors bus, PCI bus, Accelerated
Graphics Port and main memory. The 82443GX supports a 4-deep in-order queue (i.e., it provides
support for pipelining of up to 4 outstanding transaction requests on the system bus).
®
Pentium® II processors at the maximum
For system bus-to-PCI transfers, the addresses are either translated or directly forwarded on the
PCI bus, depending on the PCI address space being accessed. If the access is to a PCI configuration
space, the processor I/O cycle is mapped to a PCI configuration space cycle. If the access is to a
PCI I/O or memory space, the processor address is passed without modification to the PCI bus.
Certain memory address range (later referred in a document as a Graphics Aperture) are dedicated
for a graphics memory address space. If this space or portion of it is mapped to main DRAM, then
the address will be translated via the AGP address remapping mechanism and the request
forwarded to the DRAM subsystem. A portion of the graphi cs aperture can be mapped on A GP and
corresponding system bus cycles that hit that range are forwarded to AGP without any translation.
Other system bus cycles forwarded to AGP are defined by the AGP address map.
1.3.2.2 DRAM Interface
The 82443GX integrates a main memory controller that supports a 64/72-bit DRAM interface
which operates at 100 MHz. The integrated DRAM controller features: supports up to 4 doublesided DIMMs, 8M to 256M using 16Mbit technology, 1 GB using 64Mbit technology, and 2 GB
using 128M or 256M technol ogy, two copies of MAxx are pro vid ed for optimi zed timing, an d ECC
with hardware scrubbing.
1.3.2.3 Accelerated Graphics Port Interface
The 82443GX supports an AGP interface. The AGP interface can reach a maximum theoretical
~532 Mbytes/sec transfer rate.
Intel® 440GX AGPset Design Guide
1-5
1.3.2.4 PCI Interf ac e
The 82443GX PCI interface is 33 MHz Revision 2.1 compliant and supports up to five external
PCI bus masters in addition to the I/O bridge (PIIX4E).
1.3.2.5 System Clocking
The 82443GX operates the system bus interface at 100 MHz, PCI at 33 MHz and AGP at
66/133 MHz. The 443GX clocking scheme uses an external clock synthesizer which produces
reference clocks for the system bus and PCI interfaces. The 82443GX produces a single 100 MHz
SDRAM clock output which is fed to a 1 to 18 clock buffer to support 1 to 4 DIMMs.
1.3.3 PCI-to-ISA/IDE Xcelerator (PIIX4E)
The PCI-to-ISA/IDE Xcelerator (PIIX4E) is a multi-function PCI device implementing a PCI-toISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an
Enhanced Power Management function. As a PCI-to-ISA bridge, the PIIX4E integrates many
common I/O fu nctions found in ISA -based PC systems; a seven channel DMA Controller, two
82C59 Interrupt Controllers, an 8254 Timer/Counter, and a Real Time Clock. In addition to
Compatible transfers, each DMA channel also supports Type F transfers.
Introduction
The PIIX4E contains full support for both PC/PCI and Distributed DMA protocols implementing
PCI based DMA. The Interrupt Controller has Edge or Level sensitive programmable inputs and
fully supports the use of an external I/O Advanced Programmable Interrupt Controller (APIC) and
Serial Interrupts. Chip select decoding is provided for BIOS, Real Time Clock, Keyboard
Controller, second external Microcontroller, as well as 2 Programmable Chip Selects. The PIIX4E
provides full Plug and Play compatibility. The PIIX4E can be configured as a Subtractive Decode
bridge or as a Positive Decode bridge.
The PIIX4E supports two IDE connectors for up to four IDE devices providing an interface for
IDE/EIDE hard disks and CD ROMs. Up to four IDE devices can be supported in Bus Master
mode. The PIIX4E contains support for “Ultra DMA/33” synchronous DMA compatible devices.
The PIIX4E contains a Universal Serial Bus (USB) Host Controller that is Universal Host
Controller Interface (UHCI) compatible. The Host Controller’s root hub has two programmable
USB ports.
The PIIX4E supports Enhanced Power Management, including full Clock Control, Device
Management for up to 14 devices, and Suspend and Resume logic with Power On Suspend,
Suspend to RAM or Suspend to Disk. It fully supports Operating System Directed Power
Management via the Advanced Configuration and Power Interface (ACPI) specification. The
PIIX4E integrates both a System Management Bus (SMBus) Host and Slave interface for serial
communication with other devices.
For more information on the PIIX4E, please refer to thePIIX4 d atasheet.
1.3.4 Wired for Management Initiative
Wired for Management (WfM) is an Intel initiative to improve the manageability of desktop, and
server systems. The goal of WfM is to reduce the Total Cost of Ownership (TCO) through
improved manageability in the following four technology areas:
Instrumentation
•
Remote Service Boot
•
Remote Wake-Up
•
Power Management
•
Intel® 440GX AGPset Design Guide
1-6
Manageability features in each of these four technology areas combine to form the Wired for
Management Baseline Specification. A copy of the Wired for Management Baseline Specification
can be obtained from:
ftp://download.intel.com/ial/wfm/baselin e.pdf
An on-line Design Guide is available at:
http://developer.intel.com/ial/WfM/design/index.htm
Future versions of the specification, which preserve today's investments, will be available at this
site.
1.3.3.1 Instrumentation
A component's instrumentation consists of co de that maintains attributes with up-to-the-minute
values and adjusts the component's operational characteristics based on these values. By provi ding
instrumentation, the platform provides accurate data to management applications, so those
applications can make the best decisions for managing a system or product.
The WfM 1.1a Baseline requires that compliant desktop and mobile platforms utilize the DMI
Version 2.00 Management Interface (MI) and Component Interface (CI) application programming
interfaces and host a DMI v2.00 Service Provider , as def ined by the DMTF. Intel's DMI 2.0 Service
Provider Software Development Kit (SDK) provides a DMI Service Provider and binaries that
support DMI Version 2.00. This kit is available at:
Introduction
http://developer.intel.com/ial/WfM/tools/sdk/index.htm.
Intel's LANDesk© Client Manager product includes the Service Provider and component
instrumentation. Information regarding this product can be found at:
http://developer.intel.com/ial/WfM/tools/ldcm/index.htm
The WfM Baseline Instrumentation specification identifies specific DMI standard groups,
including event generation groups, that must be instrumented for a Baseline-compliant platform.
This reference design provides support for the SMBIOS revision 2.0 specification which along
with appropriate component instrumentation will supply some of the required data in the specified
DMI 2.0 groups. This reference design also provides additional optional instrumentation hardware
support with the LM79 and Maxim MAX1617 components.
1.3.3.2 Remote Service Boot
The WfM Baseline specifies the protocols by which a client requests and do wn loads an executable
image from a server and the minimum requirements on the client execution environment when the
downloaded image is executed. The Baseline specification includes a set of APIs for the particular
network controller used. The code supporting the Preboot eXecution Environment (PXE) and the
network controller is provided on the EtherExpress
T wo implementation option s are a v ailable: 1) NIC with Option ROM and Wak e on LAN Header or
2) a LAN on Motherboard implementation. For the second option, the Preboot execution
environment and the network controller code must be incorporated into the system BIOS.
In addition, the BIOS must provide the _SYSID_ and _UUID_ data structures. The details of the
BIOS requirements can be obtained from the Intel web site.
©
PRO/100 WFM adapters Option ROM.
Intel® 440GX AGPset Design Guide
http://developer.intel.com/ial/WfM/design/pxedt/index.htm
1-7
1.3.3.3 Remote Wake-Up
If a PC supports a reduced power state, it must be possible to bring the system to a fully powered
state in which all management interfaces are available. Typically, the LAN adapter recognizes a
special packet as a signal to wake up the system. This reference design utilizes a Wake on LAN
(WOL) Header to provide standby power to the NIC and the interface for the wake up signal. The
physical connection to the NIC and motherboard is via a WOL Cable provided with the design kit.
See the WOL Header Recommendations document at:
ftp://download.intel.com/ial/wfm/wol_v14.pdf.
The system BIOS must enable the wake event an d pr o v ide wa k e up status. The d etails of the BI OS
requirements can be obtained from the Intel Corporation w eb site:
http://developer.intel.com/ial/WfM/design/rwudt/index.htm
1.3.3.4 Power Management
WfM Baseline compliant systems have four distinct power states: Working, Sleeping, Soft Off, and
Mechanical Off. Soft off is usually provided by a user accessible switch that will send a soft off
request to the system. The PIIX4 provides the power button input for this purpose and
implementation details are described in th e schematics. A second optional “override” switch
located in a less obvious place (or removal of the power cord) stops current flow forcing the
platform into the mechanical off state without OS consent. Note that a second “override” switch is
required for legal reasons in some jurisdictions (for example, some European countries). The BIOS
may support the power management requirement either through the APM revision 1.2 or ACPI
revision 1.0 specifications. This reference design’s BIOS implementation incorporates both
interfaces. The PIIX4 provides hardware level register support for both the APM and ACPI
specifications. See Intel's web site for additional information:
Introduction
http://developer.intel.com/ial/WfM/design/pmdt/index.htm.
1.4 Design Recommendations
1.4.1 Voltage Definitions
For the purposes of this document the following nominal voltage definitions are used:
Vcc 5.0V
Vcc
Vcc
Vcc
V
TT
V
REF
3.3
CORE
2.5
3.3V
Voltage is dependent on the five bit VID setting
2.5V
1.5V
1.0V
Intel® 440GX AGPset Design Guide
1-8
1.4.2 General Design Recommendations
1. Intel recommends using an industry standard programmable Voltage Regulator Module
(VRM) installed in a VRM header o r an onb oard p rogrammab le v olt age re gulator d esign ed for
®
Intel
Pentium® II processors.
Introduction
2. Systems should be capable of varying the system bu s to processor cor e freq uency ratio per the
System Bus to Core Frequency Multiplier Configuration table of the Intel
processor datasheet. The Intel
®
Pentium® II processor uses the following signals to configure
®
Pentium® II
the internal clock multiplier ratio: LINT[0]/INTR, IGNNE#, A20M#, LINT[1]/NMI. Follow
the recommendations in this document to ensure that adequate hold times are met on the
strapping signals. Ensure the output of the strapping logic is a Vcc
logic level for connection
2.5
to the Slot 1 connector. This can be accomplished using an open-drain output driver with pullups to Vcc
2.5
.
3. Please prepare for additional thermal margin for increases of 1-5W for higher performance or
otherwise enhanced processor.
4. Motherboard designs targeted for system integrators should design to the Boxed Intel
Pentium
Pentium
®
II processor electrical, mechanical and thermal specif ications provided in the Intel®
®
II processor datasheet, most notably the required fan power header, fan/heatsink
®
physical clearance on the motherboard.
5. Motherboard designs should incorporate a retention mechanism, retention mechanism attach
mount and heatsink support mounting holes and keep out areas for the Intel
processor and boxed Intel
®
Pentium® II processor.
®
Pentium® II
1.4.3 Transitioning from Intel 440BX AGPset to Intel 440GX
AGPset Design
1. The 82443GX supports 2GB u sing 12 8M or 25 6M memory technol ogy. The design guidelines
for MAA14 and MAB14 are the same as MAA-13 and MAB-13 on the 82443BX.
2. Intel
®
440GX AGPset supports 100 MHz system bus and 100 MHz SDRAM Memory only.
3. There is no 3 DIMM support with the Intel 440GX AGPset.
Intel® 440GX AGPset Design Guide
1-9
Introduction
1-10
Intel® 440GX AGPset Design Guide
Motherboard Design
2
Motherboard Layout and Routing Guidelines
Motherboard Layout and Routing
Guidelines
This chapter describes layout and rou tin g recommendati ons to in sure a rob us t design. Foll o w these
guidelines as closely as possibl e. Any d eviations from the guidelines listed here should be
simulated to insure adequate margin is still maintain ed in the design
2.1 BGA Quadrant Assignment
Intel assigned pins on the 82443GX to simplify routing and keep board fabrication costs down, by
permitting a motherboard to be routed in 4-layers. Figure 2-1 shows the 4 signal quadrants of the
82443GX. The component placement on the motherb oard should be d one with th is general f low in
mind. This simplifies routing and minimizes the number of signals which must cross. The
individual signals within the respective groups have also been optimized to be routed using only 2
PCB layers.
Note: The Intel
Figure 2-1. Major Signal Sections (82443GX Top View)
®
82443GX AGPset Datasheet contains a complete list of signals and Ball assignments.
PCI
Quadrant
Pin #1 Corner
AGP
Quadrant
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
2
GTL+
Quadrant
Intel® 440GX AGPset Design Guide
SDRAM
Quadrant
v001
2-1
Motherboard Layout and Routing Guidelines
Figure 2-2 and Figure 2-3 show the proposed component placement for a single processor f or both
ATX and NLX form factor designs.
ATX Form Factor:
1. The ATX placement and layout below is recommended for single (UP) Intel
processor / Intel
®
440GX AGPset system design.
2. The example placement below shows 4 PCI slots, 2 ISA slots, 4 DIMM sockets, and one AGP
connector.
3. For an ATX form factor design, the AGP compliant graphics device can be either on the
motherboard (device down option), or on an AGP connector (up option).
4. The trace length limitation between critical connections will be addressed later in this
document.
5. The figure below is for reference only and the trade-off between the number of PCI and ISA
slots, number of DIMM socket, and other motherboard peripherals need to be evaluated for
each design.
Figure 2-2. Example ATX Placement for a UP Pentium
Design
®
Pentium® II
®
II processor/Intel® 440GX AGPset
PCI0
PIIX4E
AGP/PCI1
PCI Interface
AGP Interface
CK100
I/O Ports
Pentium® II Slot 1
Host Interface
82443GX
CKBF
SDRAM Interface
SDRAM DIMMs
IDE 0/1
2-2
v002
Intel® 440GX AGPset Design Guide
NLX Form Factor:
1. The NLX placement and layout below is recommended for a single (UP) Intel
processor / Intel
®
440GX AGPset system design.
2. The example placement below shows one Slot 1 connector, 4 DIMM sockets, and an AGP
compliant device down.
3. For an NLX form factor design, the AGP compliant graphics device may readily be integrated
on the motherboard (device down option).
4. The trace length limitation between critical connections will be addressed later in this
document.
5. Figure 2-3 is for reference only and the trade-off between the number of DIMM sockets, and
other motherboard peripherals need to be evaluated for each design.
Figure 2-3. Example NLX Placement for a UP Intel
Design
SDRAM DIMMs
Motherboard Layout and Routing Guidelines
®
Pentium® II
®
Pentium® II processor / Intel® 440GX
AGP
CK100
SDRAM
Interface
CKBF
Host Interface
Pentium® II Slot 1
2.2 Board Description
For a single processor / Intel® 440GX AGPset motherboa rd design, a 4 layer stack-up arrangement
is recommended. The stack up of the board is sho wn in Figure 2-4. The impedance of all the signal
layers are to be between 50 and 80 ohms. Lower trace impedance will reduce signal edge rates,
over & undershoot, and have less cross-talk than higher trace impedance. Higher trace impedance
will increase edge rates and may slightly decrease signal flight times.
82443GX
AGP Interface
PCI Interface
I/O Ports
PIIX4E
PCI0/ISA Riser
v003
Intel® 440GX AGPset Design Guide
2-3
Motherboard Layout and Routing Guidelines
Figure 2-4. Four Layer Board Stack-up
Z = 60 ohms
Z = 60 ohms
5 mils
47 mils
5 mils
PREPREG
CORE
PREPREG
Primary Signal Layer (1/2 oz. cu .)
Ground Plane (1 oz. cu.)
Power Plane (1 oz. cu)
Secondary Signal Layer (1/2 oz. cu)
Total board thickness = 62.6
Note: The top and bottom routing layers specify 1/2 oz. cu. However, by the time the board is plated, the
traces will end about 1 oz. cu. Check with your fabrication vendor on the exact value and insure
that any signal simulation accounts for this value.
Note: A thicker core may help reduce board warpage issues.
For a dual processor / Intel
®
440GX AGPset design, a 6 layer stack-up is recommended. Two
examples are shown below. Figure 2-5 has 4 signal plane layers and 2 power plane layers.
Figure 2-6 shows 3 signal plane layers and 3 po wer plane layers. The secon d option makes it easier
to accommodate all of the power planes required in a Intel
®
440GX AGPset design.
If a 6 layer stack-up is used, then it is recommended to route most of the GTL+ bus signals on the
inner layers. The primary and secondary signal layer can be used for GTL+ signals where needed.
Routes on the two inner layers should be orthogonal to reduce crosstalk between the layers.
Figure 2-5. Six Layer Board Stack-up With 4 Signal Planes and 2 Power Planes
Z = 66 ohms
Z = 73 ohms
Z = 66 ohms
6 mils
18 mils
6 mils
18 mils
6 mils
PREPREG
CORE
PREPREG
CORE
PREPREG
Primary Signal Layer (1/2 oz. cu.)
Ground Plane (1 oz. cu.)
Inner Layer #1 (1 oz. cu.)
Inner Layer #2 (1 oz. cu)
Power Plane (1 oz. cu)
Secondary Signal Layer (1/2 oz. cu)
Total board thickness = 62.4
2-4
Intel® 440GX AGPset Design Guide
Motherboard Layout and Routing Guidelines
Figure 2-6. Six Layer Board Stack-up With 3 Signal Planes and 3 Power Planes
Z = 60 ohms
Z = 59 ohms
Z = 60 ohms
5 mils
18 mils
8 mils
18 mils
5 mils
PREPREG
CORE
PREPREG
CORE
PREPREG
Primary Signal Layer (1/2 oz. cu .)
Ground Plane (1 oz. cu.)
Inner Layer #1 (1 oz. cu.)
Power Plane #1 (1 oz. cu)
Power Plane #2 (1 oz. cu)
Secondary Signal Layer (1/2 oz. cu)
Total board thickness = 62.4
Additional guidelines on board buildup, placement and layout include:
For a 4-layer single processor design, double ended termination is recommended for GTL+
•
signals. One termination resistor is present on the processor substrate, and the other
termination resistor is needed on the motherboard. It may be possible to use single-ended
termination, if the trace lengths can tightly be controlled to 1.5” minimum and 4. 0” maximu m.
For a 6-layer dual processor design, no termination is required on the motherboard for GTL+
•
signals, as each end of the GTL+ bus is terminated on each processor. If a single Slot 1 is
populated in a DP design, the second Slot 1 must be populated with a termination card.
The termination resistors on the GTL+ bus should be 56 ohms.
•
The board impedance (Z) should be between 50 and 80 ohms (65 ohms ±20%)
•
FR-4 material should be used for the board fabrication.
•
The ground plane should not be split on the ground plane layer. If a signal must be routed for a
•
short distance on a power plane, then it should be routed on a VCC plane, not the ground
plane.
Keep vias for decoupling capacitors as close to the capacitor pads as possible.
•
2.3 Routing Guidelines
This section lists guidelines to be followed when routing the signal traces for the board design. The
order of which signals are rou t ed first and last will vary from d esi g ner t o d esi gn er. Some designers
prefer routing all of the clock signals first, while others prefer routing all of the high speed bus
signals first. Either order can be used, as long as the guidelines listed here are followed. If the
guidelines listed here are not followed, it is very important that your design is simulated, especially
on the GTL+ signals. Even when the guidelines are followed, it is still a good idea to simulate as
many signals as possible for proper signal in tegrity, flight time and cross talk.
Intel® 440GX AGPset Design Guide
2-5
Motherboard Layout and Routing Guidelines
V
2.3.1 GTL+ Description
GTL+ is the electrical bus technology used for the Intel® Pentium® Pro processor and Intel®
Pentium
drain bus with external pull-up resistors that provide both the high logic level and termination at the
end of the bus. The complete GTL+ specification is contained in the Pentium II processor
databook. The specification defines:
Refer to the 100 MHz GTL+ layout Guidelines for the Pentium
AGPset for more details.
®
II processor system bus. GTL+ is a low output swing, incident wave switching, open-
Termination voltage, V
•
Termination resistance, R
•
Maximum output low voltage, VOL, and output low current, I
•
Output driver edge rate when driving the GTL+ reference load
•
Receiver high and low voltage level, VIL and V
•
Receiver reference voltage, V
•
Receiver ringback tolerance
•
TT
TT
, as a function of the termination voltage
REF
2.3.2 GTL+ Layout Recommendations
This section contains the layout recommendations for the GTL+ signals. The layout
recommendations are deri v e d from pre-l ayout simul ations that Intel h as run us ing t he method olog y
described in Section 2.3.7, “Design Methodology” on page 2-11. Results from the pre-layout
simulations are included in this section.
IH
OL
®
II Processor and Intel® 440GX
See the Intel
be present on the particular stepping of the processor used.
®
P entium® II Proce ssor Specif ication Upd ate for workar ounds for an y errata that may
2.3.3 Single Processor Design
2.3.3.1 Single Processor Network Topology and Conditions
The recommended topology for single processor systems is shown in Figur e 2-7. In addition to the
termination resistor on the Pentium II processor substrate, a termination resistor is placed on the
system board. The recommended value for the termination resistor is 56Ω ± 5%.
Figure 2-7. Recommended Topology for Single Processor Design
TT
R
L4
L2
Slot 1
L1
TT
L3
®
Intel
440GX
AGPset
2-6
Intel® 440GX AGPset Design Guide
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