Intel 440BX Schematics
A
g
g
g
g
g
g
(
B
C
D
E
Intel 100 MHz Pentium
tm) II processor/440BX AGPset Dual
Processor Customer Reference Schematics
4 4
3 3
2 2
1 1
Revision 1.0
TITLE
COVER SHEET
BLOCK DIAGRAM
SLOT 1 CONNECTOR
CLK SYNTHESIZER 7
82443BX 8,9,10
FET SWITCHES 11,12
DIMM SOCKETS 13,14,15,16
PIIX4E 17.18
IOAPIC 19
ULTRA I/O 20
AGP CONNECTOR 21
PCI CONNECTORS 22,23
ISA CONNECTORS 24
IDE CONNECTORS 25
USB CONNECTORS 26
FLASH BIOS 27
PARALLEL 28
SERIAL/FLOPPY 29
KEYBOARD/MOUSE 30
VRM 31
POWER CONNECTOR 32
PROCESSOR BUS/CORE FREQ. 33
PCI/AGP PULL-UPS & PULL-DOWNS 34
ISA PULL-UPS 35
82443BX/DRAM DECOUPLING 36
BULK DECOUPLING 37
TERMINATION DECOUPLING 38
LM79 39
REVISION HISTORY 40
A
B
PAGE
1
2
3,4,5,6
** Please note that these schematics are subject
to c hange.
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF
MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE,
OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL,
SPECIFICATION OR SAMPLE.
No license, express or implied, by estoppel or otherwise,
to any intellectual property ri
Intel disclaims all liability, includin
any proprietary ri
specification. Intel does not warrant or represent that such
use will not infrin
I2C is a two-wire communications bus/protocol developed
by Philips. SMBus is a subset of the I2C bus/protocol and
was developed by Intel. Implementations of the I2C
bus/protocol or the SMBus bus/protocol may require
licenses from various entities, includin
N.V. and North American Philips Corporation.
*Third-party brands and names are the property
of their respective owners.
ht * Intel Corporation 1997, 1998
Copyri
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
Intel Pentium(tm) II processor/440BX AGPset Dual Processor Cover Sheet
Size Document Number Rev
Custom
C
Date: Sheet of
hts, relating to use of information in this
e such rights.
D
hts is granted herein.
liability for infringement of
Philips Electronics
Intel(R) 440BX AGPset 1.0
140Thursday, April 09, 1998
E
1
2
3
4
5
6
7
8
APIC BUS
VRM
VTT GEN.
A A
B B
PG. 31
IOAPIC
82093A A
PG. 19
MAX1617 ME
PG. 3
SMBus
Interface
PENTIUM(tm) II
Processor
(SLOT 1)
PG. 3,4
ADDR
CNTL
DATA
SY STEM BUS
AGP
CONN.
PG. 21
ADDR/DATA
AGP SIDEBAND
CNTL
CK100
&
ITP CON.
PG. 7
ADDR
CNTL
82443BX
492 BGA
PG. 8-10
ADD/DATA
DATA
CNTL
PENTIUM(tm) II
Processor
(SLOT 1)
PG. 5,6
ADDR
CNTL
DATA
SYSTEM BUS
CNTL
ADDR
CKBF
PG. 8
DATA
MEMORY
4 SDRAM DIMM
MODULES
PG. 13-16
VRM
VTT GEN.
PG. 31
MAX1617 ME
PG. 5
SMBus
Interface
PCI BUS
ADD/DATA
USB
USB
2 USB CONN.
PG. 26
CONTROL
C C
INTERRUPTS
CONTROL
ADDR
CNTL
82371EB
324 BGA
PG. 17-18
CNTL
DATA
CNTL
ADDR/DATA
2 PCI IDE
CONNECTORS
PG. 25
PRIMARY
IDE
SECONDARY
IDE
CNTL
ADDR/DATA
PG. 22-23
PCI CONN
PCI CONN
PCI CONN
PCI CONN
ISA BUS
CNTL
PG.14
DATA
CNTL
ADDR
PG 35
ISA CONN
ISA CONN
ADDR
FLASH
BIOS
PG. 27
DATA
X-BUS
KEYBOARD
PG. 30
ADDR
ULTRA I/O
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT
BEEN VERIFIED FOR MANUFACTURING AN END USER
PRODUCT. iNTEL ISNOT RESPONSIBLE FOR THE MISUSE OF
THIS INFORMATION.
DEVICE TABLE
DEVICE
TYPE
FUSES F1,F2,F3,F4 26,30
Slot 1 Connectors J1A,B J2A,B
ITP Connector J 3
DIMM Sockets J4,J5,J6,J7 13,14,15,16
AGP Connector J8 21
PCI Connector J9,J10,J11,J12
ISA Connector J13, J14 35
IDE Connector J15, J16 25
USB Connector J17,J18
VRM8.2 J25,J26 31
BLM31A700S L1-L13 26,30
CK100 U1 7
82443BX U2 - 1,2,3 8,9,10
CKBF U3
FET SWITCHES
(74CBT16212)
82371EB (PIIX4E) U10A,B 17,18
82093AA (IOAPIC) U12 19
74LVC125 U13A,B,C,D 19,35
FDC37C932FR
(Ultra I/O)
74AS07 U15A,B,C,D,E,F 21,35
74HCT14 U16 A,B,C,D,E,F 27,32,35
E28F002BC-T(FLASH) U17 27
74ALS08 U20 A,B,C,D 32,35
74ALS05 U21 A,B,C,D,E,F 32,33,35
74HC10 U22 A,B,C 18,32
74F07 U23A,B,C,D,E,F 32,33
74FCT3244 U24 33
LM79 U25 39
MAX 1617 ME U28,U29 3,5
74HCT14
74HC112
74F07 U36A,B,C,D,E,F 18, 32, 35
LT1575
REFERENCE
DESIGNATOR
U4,5,6,7,8,9 11,12
3VSB
U11A,B,C,D,E,F74LVC14 18, 32, 33
3VSB
U14 20
5VSB
5VSB
U30
U32
5VSB
PAGE #
3,4,5,6
22,23
26
8
18,35
18
31VR1
31VR2LT1585
LM79
D D
1
PG. 38
2
MOUSE
PG. 30
FLOPPY
CONN.
PG. 29
3
PARA.
CONN.
PG. 28
SER.
CONN.
PG .29
SER.
CONN.
4
DATA
RESET, POWER CONNECTORS
PCI, AGP, & ISA RESISTORS
DECOUPLING CAPACITORS
5
PG. 32
PG. 34-35
PG. 36-37
6
Crystal (14.318 MHz)
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
Size Document Number Rev
Custom
Date: Sheet of
Y1 7
Intel 100MHz Pentium(tm) II processor/440BX AGPset Block Diagram
Intel(R) 440BX AGPset
7
240Thursday, April 09, 1998
8
1.0
A
(R)
(
)
y
]
B
C
D
E
VTT
GND
GND
GND
TDO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VTTVCCCORE1
A03
A04
A05
A06
A07
A08
A09
TDI
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
HD#61
HD#55
HD#60
HD#53
HD#57
HD#46
HD#49
HD#51
HD#42
HD#45
HD#39
HD#43
HD#37
HD#33
HD#35
HD#31
HD#30
HD#27
HD#24
HD#23
HD#21
HD#16
HD#13
HD#11
HD#10
HD#14
HD#9
HD#8
HD#5
HD#3
HD#1
A20M# 5,33,34
FERR# 5,1 8,34
IGNNE# 5,33,34
TDI_1 7
TDO_1 5,7
PWRGOOD 5,27,32
TES THI 5,34
THERMTRIP# 5,34
LINT0 5,33,34
PICD0 5,19,34
ITPREQ#0 7
VCC3
4 4
SM B SLAVE
ADDRESS
= 0011000b
3 3
2 2
VCC3
FLUSH#5,34
HSMI#5,19
HINIT#5,1 8,34
STPCLK#5,1 8,34
TCK_17
SLP#5,1 8,34
TMS_17
TRST#5,7
LINT15,33,34
PICCLK_P17
100/66#5,7,16
PICD15 ,19,34
PRDY#07
THERM# 5, 18,34
C198
2200pF
HD#62
HD#58
HD#63
HD#56
HD#50
HD#54
HD#59
HD#48
HD#52
HD#41
HD#47
HD#44
HD#36
HD#40
HD#34
HD#38
HD#32
HD#28
HD#29
HD#26
HD#25
HD#22
HD#19
HD#18
HD#20
HD#17
HD#15
HD#12
HD#7
HD#6
HD#4
HD#2
HD#0
EMI_PD3
EMI_PD2
6
1
5
9
U28
STBY#
ADD1
ADD0
SM BDATA
SMBCLK
RESV
RESV
RESV
RESV
RESV
C111
0.1 uF
2
V+
MAX1617 ME
16p QSOP
SMB_ALERT#
3
D+
4
D-
11
R281
4.7K
15
10
SM BDATA5,8,15,16,18,34,39
SMBCLK5,8,15,16,18,34,39
12
14
13
16
GND7GND
MAX1617_2
8
HD#[63:0
5,10
J1A
B01 A01
EMI
B02 A02
FLUSH#
B03
SMI#
B04
INIT#
B05
VCC_VTT
B06
STPCLK#
B07
TCK
B08
SLP#
B09
VCC_VTT
B10
TMS
B11
TRST#
B12
RESERVED
B13
VCC_CORE
B14
RESERVED
B15
RESERVED
B16
LINT[1]
B17
VCC_CORE
B18
PICCLK
B19
BP#[2]
B20
RESERVED
B21
100/66#
B22
PICD[1]
B23
PRDY#
B24
BPM#[1]
B25
VCC_CORE
B26
DEP#[2]
B27
DEP#[4]
B28
DEP#[7]
B29
VCC_CORE
B30
D#[62]
B31
D#[58]
B32
D#[63]
B33
VCC_CORE
B34
D#[56]
B35
D#[50]
B36
D#[54]
B37
VCC_CORE
B38
D#[59]
B39
D#[48]
B40
D#[52]
B41
EMI
B42
D#[41]
B43
D#[47]
B44
D#[44]
B45
VCC_CORE
B46
D#[36]
B47
D#[40]
B48
D#[34]
B49
VCC_CORE
B50
D#[38]
B51
D#[32]
B52
D#[28]
B53
VCC_CORE
B54
D#[29]
B55
D#[26]
B56
D#[25]
B57
VCC_CORE
B58
D#[22]
B59
D#[19]
B60
D#[18]
B61
EMI
B62
D#[20]
B63
D#[17]
B64
D#[15]
B65
VCC_CORE
B66
D#[12]
B67
D#[7]
B68
D#[6]
B69
VCC_CORE
B70
D#[4]
B71
D#[2]
B72
D#[0]
B73
VCC_CORE
EMI_PD1
SLOT1_0.8
VCC_VTT
VCC_VTT
A20M#
FERR#
IGNNE#
PWRGOOD
TESTHI1
THERMTRIP#
RESERVED
LINT[0]
PICD[0]
PREQ#
BPM#[0]
BINIT#
DEP#[0]
DEP#[1]
DEP#[3]
DEP#[5]
DEP#[6]
RESERVED
SLOT 1a
IERR#
BP#[3]
D#[61]
D#[55]
D#[60]
D#[53]
D#[57]
D#[46]
D#[49]
D#[51]
D#[42]
D#[45]
D#[39]
D#[43]
D#[37]
D#[33]
D#[35]
D#[31]
D#[30]
D#[27]
D#[24]
D#[23]
D#[21]
D#[16]
D#[13]
D#[11]
D#[10]
D#[14]
D#[9]
D# [8]
D# [5]
D# [3]
D# [1]
1 1
R1
0
R3
0R20
* Please place as close to the connector as possible
A
B
C
D
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
FIRST SLOT 1
Size Document Number Rev
Custom
Date: Sheet of
PART I
Intel
, April 09, 1998
440BX AGPset 1.0
340Thursda
E
A
(
)
y
]
]
]
B
C
D
E
VCCCORE1
VA3
VA0
VCC3
J1B
B74 A74
RESET#
B75 A75
BREQ1#
B76
FRCERR#
B77
VCC_CORE
B78
A#[35]
B79
A#[32]
B80
A#[29]
B81
EMI
B82
A#[26]
B83
A#[24]
B84
A#[28]
B85
VCC_CORE
B86
A#[20]
B87
A#[21]
B88
A#[25]
B89
VCC_CORE
B90
A#[15]
B91
A#[17]
B92
A#[11]
B93
VCC_CORE
B94
A#[12]
B95
A#[8]
B96
A#[7]
B97
VCC_CORE
B98
A#[3]
B99
A#[6]
B100
EMI
B101
SLOTOCC#
B102
REQ#[0]
B103
REQ#[1]
B104
REQ#[4]
B105
VCC_CORE
B106
LOCK#
B107
DRDY#
B108
RS#[0]
B109
VCC_5
B110
HIT#
B111
RS#[2]
B112
RESERVED
B113
VCC_3
B114
RP#
B115
RSP#
B116
AP#[1]
B117
VCC_3
B118
AERR#
B119
VID[3]
B120
VID[0]
B121
VCC_3
BCLK
BREQ0#
BERR#
A#[33]
A#[34]
A#[30]
A#[31]
A#[27]
A#[22]
A#[23]
RESERVED
A#[19]
A#[18]
A#[16]
A#[13]
A#[14]
A#[10]
BNR#
BPRI#
TRDY#
DEFER#
REQ#[2]
REQ#[3]
HITM#
DBSY#
RS#[1]
RESERVED
ADS#
RESERVED
AP#[0]
VID[2]
VID[1]
VID[4]
A#[5]
A#[9]
A#[4]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
A111
A112
A113
A114
A115
A116
A117
A118
A119
A120
A121
VA2
VA1
VA4
R5 0
R7 0
R8 0
HREQ#2
HREQ#3
VID_A2
VID_A1
VID_A4
HA#30
HA#27
HA#22
HA#23
HA#19
HA#18
HA#16
HA#13
HA#14HA#8
HA#10
HA#5
HA#9
HA#4
CPUHCLK1 7
BREQ0# 6,8
BNR# 6,8
BP RI# 6 ,8
HTRDY# 6,8
DEFER# 6,8
HITM# 6,8
DBSY# 6,8
RS#1 6,8
ADS# 6,8
4 4
HRE SET#6,7,8
BREQ1#6
VCC
HA#29
HA#26
HA#24 HA#31
HA#28
HA#20
HA#21
HA#25
HA#15
HA#17
HA#11
HA#12
HA#7
3 3
A_SLOTOCC#32 ,34
HLOCK#6,8
DRDY#6,8
RS#06,8
HIT#6,8
RS#26,8
HA#3
HA#6
HREQ#0
HREQ#1
HREQ#4
VID_A3
VID_A0
R4 0
R6
0
R11
0
SLOT1_0.8
VID_A0
VID_A1
VID_A2
VID_A3
VID_A4
SLOT 1b
JP1
SE L _VID_A0
1
2
3
JP2
SE L _VID_A1
1
2
3
JP3
SE L _VID_A2
1
2
3
JP4
SE L _VID_A3
1
2
3
JP5
SE L _VID_A4
1
2
3
C
R9
8.2K
R12
8.2K
R13
8.2K
R14
8.2K
R15
8.2K
VCC
VRM optional override
jumpers & resistors
Jumper position 1-2 is
stuffed as the default. To
override, R4-R8 must be
removed.
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
FIRST SLOT 1
Size Document Number Rev
Custom
Date: Sheet of
D
PART II
Intel(R) 440BX AGPset 1.0
, April 09, 1998
E
440Thursda
2 2
HA#[31:3
6,8
HREQ#[4:0
6,8
VID_A[4:0
31
* Please place as close to the
connector as possible
1 1
A
B
EMI_PD5
R10
0
EMI_PD4
A
(R)
(
)
y
]
B
C
D
E
VTT
GND
GND
GND
TDO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VTTVCCCORE2
A03
A04
A05
A06
A07
A08
A09
TDI
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
HD#61
HD#55
HD#60
HD#53
HD#57
HD#46
HD#49
HD#51
HD#42
HD#45
HD#39
HD#43
HD#37
HD#33
HD#35
HD#31
HD#30
HD#27
HD#24
HD#23
HD#21
HD#16
HD#13
HD#11
HD#10
HD#14
HD#9
HD#8
HD#5
HD#3
HD#1
A20M# 3,33,34
FERR# 3,18,34
IGNNE# 3,33,34
TDO_1 3,7
TDO_2 7
PW RGOOD 3,27,32
TESTHI 3,34
THERMTRIP# 3,34
LINT0 3 ,3 3,34
PICD0 3,19,34
ITPREQ#1 7
VCC3
SMB SLAVE
ADDRESS
= 0011010b
SM BDATA3,8,15,16,18,34,39
SMBCLK3,8,15,16,18,34,39
VCC3
R282
4.7K
15
6
10
12
14
1
5
9
13
16
U29
STBY#
ADD1
ADD0
SM BDATA
SMBCLK
RESV
RESV
RESV
RESV
RESV
MAX1617_2
C112
0.1 uF
2
V+
MAX1617 ME
16p QSOP
SMB_ALERT#
GND7GND
8
FLUSH#3,34
HSMI#3,19
HINIT#3,18,34
STPCLK#3,18,34
TCK_27
SLP#3,18,34
TMS_27
TRST#3,7
3
D+
4
D-
PICCLK_P27
11
C199
2200pF
LINT13,3 3,34
100/66#3,7,16
PICD13,19,34
PRDY#17
THERM# 3,18,34
HD#62
HD#58
HD#63
HD#56
HD#50
HD#54
HD#59
HD#48
HD#52
HD#41
HD#47
HD#44
HD#36
HD#40
HD#34
HD#38
HD#32
HD#28
HD#29
HD#26
HD#25
HD#22
HD#19
HD#18
HD#20
HD#17
HD#15
HD#12
HD#7
HD#6
HD#4
HD#2
HD#0
EMI_PD8
EMI_PD7
HD#[63:0
3,10
4 4
3 3
2 2
J2A
B01 A01
EMI
B02 A02
FLUSH#
B03
SMI#
B04
INIT#
B05
VCC_VTT
B06
STPCLK#
B07
TCK
B08
SLP#
B09
VCC_VTT
B10
TMS
B11
TRST#
B12
RESERVED
B13
VCC_CORE
B14
RESERVED
B15
RESERVED
B16
LINT[1]
B17
VCC_CORE
B18
PICCLK
B19
BP#[2]
B20
RESERVED
B21
100/66#
B22
PICD[1]
B23
PRDY#
B24
BPM#[1]
B25
VCC_CORE
B26
DEP#[2]
B27
DEP#[4]
B28
DEP#[7]
B29
VCC_CORE
B30
D#[62]
B31
D#[58]
B32
D#[63]
B33
VCC_CORE
B34
D#[56]
B35
D#[50]
B36
D#[54]
B37
VCC_CORE
B38
D#[59]
B39
D#[48]
B40
D#[52]
B41
EMI
B42
D#[41]
B43
D#[47]
B44
D#[44]
B45
VCC_CORE
B46
D#[36]
B47
D#[40]
B48
D#[34]
B49
VCC_CORE
B50
D#[38]
B51
D#[32]
B52
D#[28]
B53
VCC_CORE
B54
D#[29]
B55
D#[26]
B56
D#[25]
B57
VCC_CORE
B58
D#[22]
B59
D#[19]
B60
D#[18]
B61
EMI
B62
D#[20]
B63
D#[17]
B64
D#[15]
B65
VCC_CORE
B66
D#[12]
B67
D# [7]
B68
D# [6]
B69
VCC_CORE
B70
D# [4]
B71
D# [2]
B72
D# [0]
B73
VCC_CORE
EMI_PD6
SLOT1_0.8
VCC_VTT
VCC_VTT
IGNNE#
PWRGOOD
TES THI1
THERMTRIP#
RESERVED
LINT[0]
PICD[0]
PREQ#
BPM#[0]
DEP#[0]
DEP#[1]
DEP#[3]
DEP#[5]
DEP#[6]
RESERVED
SLOT 1a
IERR#
A20M#
FERR#
BP#[3]
BINIT#
D#[61]
D#[55]
D#[60]
D#[53]
D#[57]
D#[46]
D#[49]
D#[51]
D#[42]
D#[45]
D#[39]
D#[43]
D#[37]
D#[33]
D#[35]
D#[31]
D#[30]
D#[27]
D#[24]
D#[23]
D#[21]
D#[16]
D#[13]
D#[11]
D#[10]
D#[14]
D# [9]
D#[8]
D#[5]
D#[3]
D#[1]
1 1
R16
0
R17
0
R18
0
* P lease place as close to the connector as possible
A
B
C
D
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
SECOND SLOT 1
Size Document Number Rev
Custom
Date: Sheet of
Intel
, April 09, 1998
PART I
440BX AGPset 1.0
540Thursda
E
A
(
)
y
]
]
]
B
C
D
E
VCCCORE2
VB3
VB0VID_B0
VCC3
J2B
B74 A74
RESET#
B75 A75
BREQ1#
B76
FRCERR#
B77
VCC_CORE
B78
A#[35]
B79
A#[32]
B80
A#[29]
B81
EMI
B82
A#[26]
B83
A#[24]
B84
A#[28]
B85
VCC_CORE
B86
A#[20]
B87
A#[21]
B88
A#[25]
B89
VCC_CORE
B90
A#[15]
B91
A#[17]
B92
A#[11]
B93
VCC_CORE
B94
A#[12]
B95
A#[8]
B96
A#[7]
B97
VCC_CORE
B98
A#[3]
B99
A#[6]
B100
EMI
B101
SLOTOCC#
B102
REQ#[0]
B103
REQ#[1]
B104
REQ#[4]
B105
VCC_CORE
B106
LOCK#
B107
DRDY#
B108
RS#[0]
B109
VCC_5
B110
HIT#
B111
RS#[2]
B112
RESERVED
B113
VCC_3
B114
RP#
B115
RSP#
B116
AP#[1]
B117
VCC_3
B118
AERR#
B119
VID[3]
B120
VID[0]
B121
VCC_3
BCLK
BREQ0#
BERR#
A#[33]
A#[34]
A#[30]
A#[31]
A#[27]
A#[22]
A#[23]
RESERVED
A#[19]
A#[18]
A#[16]
A#[13]
A#[14]
A#[10]
BNR#
BPRI#
TRDY#
DEFER#
REQ#[2]
REQ#[3]
HITM#
DBSY#
RS#[1]
RESERVED
ADS#
RESERVED
AP#[0]
VID[2]
VID[1]
VID[4]
A#[5]
A#[9]
A#[4]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
A111
A112
A113
A114
A115
A116
A117
A118
A119
A120
A121
VB2
VB1
VB4
R20 0
R22 0
R23 0
HREQ#2
HREQ#3
VID_B2
VID_B1
VID_B4
HA#30
HA#31
HA#27
HA#22
HA#23
HA#19
HA#18
HA#16
HA#13
HA#14
HA#10
HA#5
HA#9
HA#4
CPUHCLK2 7
BREQ1# 4
BNR# 4,8
BP RI# 4 ,8
HTRDY# 4,8
DEFER# 4,8
HITM# 4,8
DBSY# 4,8
RS#1 4,8
ADS# 4,8
4 4
HRE SET#4,7,8
BREQ0#4,8
VCC
HA#29
HA#26
HA#24
HA#28
HA#20
HA#21
HA#25
HA#15
HA#17
HA#11
HA#12
HA#8
HA#7
3 3
B_SLOTOCC#32 ,34
HLOCK#4,8
DRDY#4,8
RS#04,8
HIT#4,8
RS#24,8
HA#3
HA#6
HREQ#0
HREQ#1
HREQ#4
VID_B3
R19 0
R21
0
R26
0
SLOT1_0.8
VID_B0
VID_B1
VID_B2
VID_B3
VID_B4
SLOT 1b
JP6
SE L_VID_B0
1
2
3
JP7
SE L_VID_B1
1
2
3
JP8
SE L_VID_B2
1
2
3
JP9
SE L_VID_B3
1
2
3
JP10
SE L_VID_B4
1
2
3
C
R24
8.2K
R27
8.2K
R28
8.2K
R29
8.2K
R30
8.2K
VCC
VRM optional override
jumpers & resistors
Jumper position 1-2 is
stuffed as the default. To
override, R19-R23 must
be removed.
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
SECOND SLOT 1
Size Document Number Rev
Custom
Date: Sheet of
D
PART II
Intel(R) 440BX AGPset 1.0
, April 09, 1998
E
640Thursda
2 2
HA#[31:3
4,8
HREQ#[4:0
4,8
VID_B[4:0
31
* Please place as close to
the connector as possible
1 1
A
EMI_PD10
B
R25
0
EMI_PD9
A
g
g
L15
FBHS01L
CD85
0.01 uF
16V
4 4
*NOTE* Override to
66MHz only.
JP11
100/66#3,5,16
PCI_STP#18
3 3
CPU_STP#18
SUSA#18
Stuffing option to enable the
of the CPUCLKs,
stoppin
PCICLKs, and the powerdown of
the CK100. Please note that the
resistors are not stuffed.
2 2
1 1
VCC3
R31
200
R38
8.2K
R381
0
R382
0
R383
0
DO NOT STUFF
A
VCC3
R40
R39
8.2K
8.2K
option to enable Spread#
Stuffin
function for possible EMI reduction.
R54
0
R283
10K
HRESET#4,6,8
DBRESET#32
VCC3
TCK_13
TCK_25
TMS_13
TMS_25
CD86
0.01 uF
16V
R284
10K
B
CLOCK SYNTHESIZER
21
CD88
CD89
C2
10pF
R64
R65
47
47
42
28
27
26
25
31
30
29
100pF
16V
U1
4
XTALIN
5
XTALOUT
RESV
RESV
SEL0
SEL1
SEL_100/66#
PCI_STP#
CPU_STP#
PWRDWN#
CK100_05
ITP_RST
47
47
CD90
C168
+
100pF
22uF
16V
9
15
19
33
48
21
VDDPCI0
VDDPCI1
VDD48MHZ
VDDCORE0
VDDCORE1
CK100
VSSREF
VS S PCI0
3
6
12
VCC2.5 VTT
R55
1K
ITPCLK
TDO_JMP TDI_JMP
1 - 2 1 - 2
2 - 3 2 - 3
46
41
37
VDDAPIC
VDDCPU0
VDDQREF
VDDCPU1
APICCLK_0
APICCLK_1
VSSCORE1
VSS48MHZ
VSS CORE0
VSSPCI1
VSSPCI2
VSSCPU0
VSSCPU1
18
38
34
32
24
20
R56
R57
OPTIONAL ITP
1K
1K
TEST
5%
CONNECTOR
ITP_JMP CONFIG
CD87
0.01uF
16V
R285
10K
100pF
16V
Y1
14.318MHz
C1
10pF
R60
240
R66
R69
B
C
CPUCLK0
CPUCLK1
CPUCLK2
CPUCLK3
PCICLK_F
PCICLK_1
PCICLK_2
PCICLK_3
PCICLK_4
PCICLK_5
PCICLK_6
PCICLK_7
48MHZ_0
48MHZ_1
REF0
REF1
REF2
VSSAPIC
43
J3
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
ITP CONN
1 - 22 - 3
C
C172
100pF
16V
40
39
36
35
7
8
10
11
13
14
16
17
R47
22
23
R48 22
45
44
R51
1
R52
2
47
R53
SINGLE CPU1
DUAL CPU
SINGLE CPU2
C173
100pF
16V
R32
R33 22
R34 22
R35 22
R36 22
R37 22
R41 22
R42 22
R43 22
R44 22
R45 22
22
22
22
22
R_PRDY0
R_PRDY1
CPU
CONFIGJP12 JP13
C174
0.01uF
16V
22
R68 240
L14
2 1
FBHS01L
C175
C176
C177
0.01uF
16V
CPUHCLK1 4
CPUHCLK2 6
BXHCLK 8
ITPCLK
PXPCLK 18
PCLK1 22
PCLK2 22
PCLK3 23
PCLK4 23
BXPCLK 9
PCLKAPIC 19
48Mhz_0 18
APICCLK 19
OSC1 24
OSC2 18
OSC3 20
+
0.01uF
16V
22uF
HPICCLK
VCC2.5 VTT VTT
R61
330
R67 240
R70
680
TDO_13,5
TDO_25
D
VCC2.5VCC3
*NOTE* For power managed systems, the PIIX4 must be
connected t PCICLK_F of the CKE100 which is a free
running PCLK not affected by the assertion of
PCISTOP#.
E
STU FFING OPTION
*NOTE* 10-15 pF caps to ground may be
desirable to reduce the effects of EMI.
R58
R59
56
R63
330
D
56
VCC2.5
R71
R72
150
150
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
CLOCK SYNTHESIZER
Size Document Number Rev
Custom
Date: Sheet of
TR ST# 3,5
ITPREQ#0 3
PRDY#0 3
ITPREQ#1 5
PRDY#1 5
JP12
1
2
3
TDO_JMP
Intel(R) 440BX AGPset
R46
10
R50
10
JP13
2
TDI_JMP
PICCLK_P1 3
PICCLK_P2 5
VCC2.5
1
3
E
740Thursday, April 09, 1998
R73
330
TDI_1 3
1.0
A
y
y
g
[
y
]
]
]
HA#[31:3
4,6
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HREQ#0
HREQ#1
HREQ#2
HREQ#3
CRESET#
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
RS#0
RS#1
RS#2
HREQ#4
4 4
HRE SET#4,6,7
ADS#4,6
3 3
VCC3
2 2
1 1
BNR#4,6
BPRI#4,6
DBSY#4,6
DEFER#4,6
DRDY#4,6
HIT#4,6
HITM#4,6
HLOCK#4,6
HTRDY#4,6
BREQ0#4,6
RS#[2:0
4,6
HREQ#[4:0
4,6
R75
8.2K
**TESTIN# pullup ma
removed after validation
has been completed.
BXHCLK7
CR ESET#33
PCI RST#17 ,21,22,23
A
be
G25
H22
G23
H23
G24
F26
G26
G22
F22
F23
F24
F25
E23
E26
E25
D25
D26
B25
C26
A25
C25
A24
D24
C23
B24
C24
A23
E22
D23
B23
K21
H24
H26
L23
J26
K23
L24
L22
K22
H25
B26
K26
L26
L25
J22
J23
K24
K25
J25
N23
M25
M26
AE22
AE23
P22
A3
U2-1
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
CPURST#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HTRDY#
BREQ0#
RS#0
RS#1
RS#2
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HCLKIN
TE S TIN#
CRESET#
PCI RST#
RESVA
RE SVB
RESVC
443 BX_10
B
VCC3
V21
Y21
F18
F20
G21
J21
AA7
VDD
VDD
VDDF7VDDF9VDD
VDD
VDDG6VDD
VDDJ6VDD
VDD
82443BX
492 BGA
SYSTEM INTERFACE
VSSA1VSS
VSS
VSSC5VSSC9VSS
VSS
VSSE3VSS
VSS
VSS
VSSF6VSSF8VSS
A14
A26
C18
C22
B
E12
E15
E24
F19
F21
AA9
VSS
AA18
AA20
VDD
VDD
VSSH6VSS
H21
VDD
CKE2/CSA6#
CKE3/CSA7#
DRAM INTERFACE
CKE4/CSB6#
CKE5/CSB7#
CKE0/FENA
CKE1/GCKE
VSSJ3VSS
J24
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAB0#
MAB1#
MAB2#
MAB3#
MAB4#
MAB5#
MAB6#
MAB7#
MAB8#
MAB9#
MAB10
MAB11#
MAB12#
MAB13
CSA0#
CSA1#
CSA2#
CSA3#
CSA4#
CSA5#
CSB0#
CSB1#
CSB2#
CSB3#
CSB4#
CSB5#
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
DQMB1
DQMB5
SRAS_A#
SRAS_B#
SCAS_A#
SCAS_B#
WE_A#
WE_B#
DCLKO
DCLKWR
DCLKRD
C
AF17
AB16
AE17
AC17
AF18
AE19
AF19
AC18
AC19
AE20
AD20
AF21
AC21
AF25
AD16
AC16
AD17
AB17
AE18
AD19
AB18
AB19
AF20
AC20
AB20
AE21
AD21
AF22
AB14
AF15
AE15
AC15
AD15
AE16
AE24
AD23
AE25
AD24
AD26
AC24
AC26
AB23
AC23
AF24
AD13
AC13
AC25
AB26
AE14
AC14
AA22
AA24
AE13
AD14
AC22
AF23
**On 4-DIMM solutions that don't support
self-refresh mode, GCKE should be N/C.
AF16
AA17
AF12
AB13
AE12
AC12
AB21
AD25
AB22
**Locate R398 close to CKBF and
R399 close to 443BX.
**Locate "T" and cap close to BX.
** Pl ea se make DCLKREF trace length equal to 2.5" more
than the DCLK outputs to the DIMMs. DCLK outputs to
the DIMMs should all be the same recommended len
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAB#0
MAB#1
MAB#2
MAB#3
MAB#4
MAB#5
MAB#6
MAB#7
MAB#8
MAB#9
MAB10
MAB#11
MAB#12
MAB13
CS_A#0
CS_A#1
CS_A#2
CS_A#3
CS_A#4
CS_A#5
CS_A#6
CS_A#7
CS_B#0
CS_B#1
CS_B#2
CS_B#3
CS_B#4
CS_B#5
CS_B#6
CS_B#7
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
DQMB1
DQMB5
R399 22
Example: if DCLK
then DCLKREF = 2.5" + 2.5".
C
SRA S_A# 13,14
SR AS_B# 15,16
SCA S_A# 13,14
SC AS_B# 15,16
WE_A# 13,14
WE_ B# 15,16
DCLKREF
C3
20pF
DQMB1 15,16
DQMB5 15,16
FENA 11,12
GCKE 10
0-11] = 2.5"
R398 47
R74
4.7k
VCC3
38
11
25
24
47
48
1
2
CKBF
U3
OE
BUF_IN
SCLOCK
SD ATA
RESV
RESV
RESV
RESV
D
MAA[13:0]13 ,14
MAB#[13:0]15,16
CS_A#[1:0]13
CS_A#[3:2]14
CS_A#[5:4]15
CS_A#[7:6]16
CS_B#[1:0]13
CS_B#[3:2]14
CS_B#[5:4]15
CS_B#[7:6]16
DQMA[7:0]13 ,14,15,16
3
23
VDD
VDDIIC
CKBF
VSS6VSS10VSS
VSSIIC
26
th.
D
E
L16
2 1
FBHS01L
100pF
.01uF
C184
100pF
.01uF
C186
100pF
.01uF
C188
100pF
.01uF
C190
100pF
.01uF
C192
22uF
46
VDD7VDD12VDD16VDD20VDD29VDD33VDD37VDD42VDD
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
VSS19VSS22VSS27VSS30VSS34VSS39VSS
15
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
Size Document Number Rev
Custom
Date: Sheet of
R76 0
4
R77
5
R78 0
8
R79 0
9
R80 0
13
R81 0
14
R82 0
17
R83 0
18
R84 0
31
R85 0
32
R86 0
35
R87 0
36
R88 0
40
R89 0
41
R90 0
44
R92 0
45
R93 0
21
R385 0
28
43
slave address =
1101001b
82443BX SYSTEM AND DRAM INTERFACES
, April 09, 1998
DCLK10
0
DCLK11
DCLK6
DCLK7
DCLK0
DCLK1
DCLK14
DCLK15
DCLK13
DCLK12
DCLK3
DCLK2
DCLK5
DCLK4
DCLK9
DCLK8
DCLKREF
*The unused SDRAM clocks
ma
SMBus interface.
SMBCLK 3,5,15,16,18,34,39
SM BDATA 3,5,15,16,18,34,39
Intel(R) 440BX AGPset 1.0
VCC3
C183
C185
C187
C189
C191
+
C193
DCLK[15:0]13, 14,15,16
**PLEASE NOTE**
These clock
assignments may
not be optimum.
SRCLK 10
be disabled using the
840Thursda
E
A
y
]
]
]
]
B
VCC3
C
D
E
AD[31:0
17 ,22,23
4 4
3 3
C/BE#[3:0
17 ,22,23
FRAME#17, 22,23,34
DE VSEL#17, 22,23,34
IRDY#17, 22,23,34
TRDY#17, 22,23,34
STOP#17,22,23,34
PAR17,22,23
PHLD#17,34
PHLDA#17,34
17, 22,23,34
22 ,23,34
SERR#17, 22,23,34
PLOCK#22,23,34
WSC#19
PREQ#[3:0
PREQ#434
PGNT#[3:0
VCC3
R95
10K
2 2
SUSTAT#18
R400
0
DO NOT STUFF
Stuffing option to enable and test
the POS state.
1 1
A
PGNT#434
PWROK18,32
VREF5V18
BXPCLK7
R294
100
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3
PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4
U2-2
K6
AD0
K2
AD1
K4
AD2
K3
AD3
K5
AD4
J1
AD5
J2
AD6
H2
AD7
H1
AD8
J5
AD9
H3
AD10
H5
AD11
H4
AD12
G1
AD13
G2
AD14
G4
AD15
D1
AD16
D3
AD17
D2
AD18
C1
AD19
A2
AD20
C3
AD21
B3
AD22
D4
AD23
E5
AD24
A4
AD25
D5
AD26
B4
AD27
B5
AD28
A5
AD29
E6
AD30
C6
AD31
J4
C/BE0#
G3
C/BE1#
E4
C/BE2#
C4
C/BE3#
E2
FRAME#
F3
DEVSEL#
E1
IRDY#
F5
TRDY#
F4
STOP#
G5
PAR
F1
SERR#
F2
PLOCK#
B6
PHOLD#
D6
PHLDA#
AE3
WSC#
A6
PR EQ0#/IOREQ#
C7
PREQ1#
F10
PREQ2#
D8
PREQ3#
D10
PREQ4#
AD4
SUSTAT#
E7
PGNT0#/IOGNT#
D7
PGNT1#
E10
PGNT2#
E8
PGNT3#
E9
PGNT4#
AF3
BX-PWROK
AC4
CLKRUN#
C2
REFVCC5
B2
PCLKIN
443BX
B
M12
L16
L14
L13
L11
VDD
VDD
VDD
VDD
PCI INTERFACE
PCI ARB & PWR MGT
VSSN1VSSM5VSS
VSS
VSS
VSS
VSS
VSS
L12
L15
M11
M13
M14
M16
M22
N11
N16
P11
P16
R12
M15
VDD
VDD
VDD
VDD
VDD
VDD
82443BX
492 BGA
VSS
VSS
VSS
VSS
VSS
VSS
N12
N13
N14
N15
P12
P13
R15
VDD
VSS
P14
T11
VDD
VSS
P15
T13
VDD
VSS
P26
T14
VDD
VSS
T12
T16
VDD
VSS
T15
N26
VDD
VSS
VDD
VSSR5VSS
R11
C
P1
VDD
VSS
R13
AE1
VDD
VSS
R14
V6
VDD
VSS
R16
Y6
VDD
GDEVSEL#
AGP INTERFACE
GADSTB-A
GADSTB-B
VSS
VSSV3VSS
R22
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC/BE0#
GC/BE1#
GC/BE2#
GC/BE3#
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#
GCLKOUT
GCLKIN
PIPE#
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
RBF#
ST0
ST1
ST2
SB-STB
AGPREFV
VSSW6VSS
V24
W21
AB5
AE2
AD3
AD2
AD1
AC3
AC1
AB4
AB1
AA5
AA3
AA4
AA2
AA1
Y5
Y3
W1
V2
W2
U5
V1
U4
U3
U1
T3
T4
T2
T1
U6
R3
R4
R2
AB2
Y4
V4
U2
W3
W5
V5
W4
Y1
Y2
L5
L3
P5
N5
M3
K1
M2
M1
N2
P2
P4
P3
R1
M4
L4
L2
L1
AC2
T5
N3
N4
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GCBE#0
GCBE#1
GCBE#2
GCBE#3
R98
22
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
ST0
ST1
ST2
R97
22
**NOTE** Locate
circuitry close to
443BX.
D
GAD[31:0]21
GC/BE#[3:0]21
GFRAME# 21,34
GD EVSEL# 21 ,34
GIRDY# 21,34
GTRDY# 21,34
GSTOP# 21,34
GPAR 21,34
GR EQ# 21,34
GGNT# 21,34
GC L KOUT 21
** Note** Please make the
GCLKIN trace length 3.3"
PIPE# 21,34
more than the GCLKOUT
recommended trace length.
Stub to tee should be 1"
MAX.
SBA[7:0]21
RB F# 21,34
ST[2:0]21
ADSTB-A 21,34
AD S TB-B 21,34
SBSTB 21,34
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
82443BX PCI AND AGP INTERFACES
Size Document Number Rev
Custom
Date: Sheet of
Intel(R) 440BX AGPset 1.0
, April 09, 1998
C5
0.001uF
VCC3
R99
**NOTE: It is
150
recommended
1%
that the tolerance
on these
resistors be 1%
R101
in order to meet
100
1%
the margins of
this reference
voltage.
940Thursda
E
A
g
g
y
]
]
MD[63:0
11,12
4 4
3 3
2 2
MECC[7:0
12
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7
U2-3
AF4
MD0
AE4
MD1
AF5
MD2
AD6
MD3
AE6
MD4
AB7
MD5
AC7
MD6
AF7
MD7
AB8
MD8
AB9
MD9
AC9
MD10
AE9
MD11
AB10
MD12
AC10
MD13
AF10
MD14
AD11
MD15
Y24
MD16
Y25
MD17
W23
MD18
W24
MD19
W26
MD20
W25
MD21
V26
MD22
U24
MD23
U23
MD24
T22
MD25
T23
MD26
T26
MD27
R24
MD28
R25
MD29
P23
MD30
N25
MD31
AC5
MD32
AE5
MD33
AB6
MD34
AC6
MD35
AF6
MD36
AD7
MD37
AE7
MD38
AC8
MD39
AD8
MD40
AF8
MD41
AE8
MD42
AF9
MD43
AD10
MD44
AE10
MD45
AB11
MD46
AC11
MD47
Y23
MD48
Y26
MD49
W22
MD50
V22
MD51
V23
MD52
V25
MD53
U22
MD54
U25
MD55
U26
MD56
T24
MD57
T25
MD58
U21
MD59
R23
MD60
R26
MD61
P24
MD62
P25
MD63
AE11
MECC0
AA10
MECC1
AA23
MECC2
AA26
MECC3
AF11
MECC4
AD12
MECC5
AA25
MECC6
Y22
MECC7
443BX_10
VTT VTT
B
VCC3
MEMORY DATA BUS
VSS
VSS
VSS
VSS
VSS
AA8
AA6
N24
AA19
AB25
AF2
AE26
N22
AF14
VDDB1VDD
VDD
VDD
82443BX
492 BGA
VSS
VSS
VSS
VSS
VSS
VSS
AB3
AD5
AB12
AB15
AB24
AD9
AA21
VDD
VSS
AD18
VSS
AD22
VSS
AF1
VSS
AF13
VSS
AF26
VSS
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HOST DATA BUS
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
GTLREFA
GTLREFB
VTTA
VTTB
B22
D22
E21
A22
D21
C21
A21
C20
B21
E20
A20
E19
B20
E18
D20
D19
D18
C19
B19
A18
A19
B18
C17
E17
D17
B17
C16
A17
C15
B16
D16
A16
B15
A15
D14
D15
B13
C14
E14
D13
A13
D12
B12
B14
C13
E13
D11
A12
B11
A11
B7
C12
C8
B10
A10
A9
A7
E11
D9
C11
C10
B8
A8
B9
M23
E16
M24
F17
C
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
VTT
D
HD#[63:0]3,5
4.7K
SRCLK8
GCKE8 B_CKE7 16
**NOTE** GCKE trace length
from the 443BX to the shift
register should be between
1" MIN and 4" MAX.
**NOTE** If GCKE is not used
then each CKE requires a 22K
pullup to VCC3.
GTLREF2
GTLREF1
R386
R396
4.7K
C194
27pF
U33
1
1EN
48
C1
24
2EN
25
C2
47
1D1
46
1D2
44
1D3
43
1D4
41
1D5
40
1D6
38
1D7
37
1D8
36
2D1
35
2D2
33
2D3
32
2D4
30
2D5
29
2D6
27
2D7
26
2D8
SN74LVCH16374
**NOTE** The seven
outputs that circle around
to b ec ome inputs on the
SN74LVCH16374 should
have trace len
er than 2".
lon
2
1
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
11
1Q7
12
1Q8
13
2
2Q1
14
2Q2
16
2Q3
17
2Q4
19
2Q5
20
2Q6
22
2Q7
23
2Q8
ths no
E
**NOTE** The trace
lengths of
BCKE[7:0] should
be 3.0"
B_CKE6 16
B_CKE5 15
B_CKE4 15
B_CKE3 14
B_CKE2 14
B_CKE1 13
B_CKE0 13
R102
75
1%
1 1
R103
150
1%
A
C6
0.001uF
B
R104
75
1%
R105
150
1%
C7
0.001uF
GTLREF2GTLREF1
C
D
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
82443BX MD/HD BUS
Size Document Number Rev
Custom
Date: Sheet of
Intel(R) 440BX AGPset 1.0
, April 09, 1998
10 40Thursda
E
A
(
)
y
[
]
]
]
]
]
[
]
]
FET-SWITCHES (MEMORY DATA LINES & ECC)
VCC
4 4
FENA8,12
MD[63:0
10,12 MD_A[63:0]12 ,13,14
R299
500
R301
500
R303
500
R305
500
R307
500
R309
500
R311
500
MD
R320
500
R322
500
R324
500
R326
500
R328
500
R330
500
R313
500
R316
500
R318
500
FENA
63:0
R315
500
R317
500
R319
500
R321
500
R323
500
R325
500
R327
500
R329
500
A
3 3
2 2
1 1
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
VCC
R108
4.7K
R107
4.7K
1
56
55
2
3
4
5
6
7
9
10
11
12
13
14
15
16
18
20
21
22
23
24
25
26
27
28
U6
1
56
55
2
3
4
5
6
7
9
10
11
12
13
14
15
16
18
20
21
22
23
24
25
26
27
28
PI5C16212A
U5
S0
S1
S2
1A1
1A2
2A1
2A2
3A1
3A2
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
8A1
8A2
9A1
9A2
10A1
10A2
11A1
11A2
12A1
12A2
PI5C16212A
S0
S1
S2
1A1
1A2
2A1
2A2
3A1
3A2
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
8A1
8A2
9A1
9A2
10A1
10A2
11A1
11A2
12A1
12A2
10B1
10B2
11B1
11B2
12B1
12B2
VCC
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
GND
GND
GND
GND
VCC
GND
GND
GND
GND
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
8B2
9B1
9B2
B
VCC
17
54
53
MD_B0
52
51
MD_B1
50
48
MD_B2
47
46
MD_B3
45
44
MD_B4
43
42
MD_B5
41
40
MD_B6
39
37
MD_B7
36
35
MD_B8
34
33
MD_B9
32
31
MD_B10
30
29
MD_B11
8
19
38
49
MD_A0
MD_A1
MD_A2
MD_A3
MD_A4
MD_A5
MD_A6
MD_A7
MD_A8
MD_A9
MD_A10
MD_A11
MD_B[63:0]12 ,15,16
C
VCC
R106
4.7K
FENA
63:0
MD
MD12 MD_A12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
R296
500
R298
500
R302
500
R306
500
R310
500
R314
500
R295
500
R297
500
R300
500
R304
500
R308
500
R312
500
U4
1
S0
56
S1
55
S2
2
1A1
3
1A2
4
2A1
5
2A2
6
3A1
7
3A2
9
4A1
10
4A2
11
5A1
12
5A2
13
6A1
14
6A2
15
7A1
16
7A2
18
8A1
20
8A2
21
9A1
22
9A2
23
10A1
24
10A2
25
11A1
26
11A2
27
12A1
28
12A2
PI5C16212A
D
VCC
17
VCC
54
1B1
53
1B2
2B1
2B2
3B1
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
GND
GND
GND
GND
MD_B12
52
51
MD_B13
50
48
MD_B14
47
46
MD_B15
45
44
MD_B16
43
42
MD_B17
41
40
MD_B18
39
37
MD_B19
36
35
MD_B20
34
33
MD_B21
32
31
MD_B22
30
29
MD_B23
8
19
38
49
MD_A13
MD_A14
MD_A15
MD_A16
MD_A17
MD_A18
MD_A19
MD_A20
MD_A21
MD_A22
MD_A23
E
MD_A[63:0
MD_B[63:0
FET ENABLE TRUTH TABLE
VCC
17
54
53
MD_B24
52
51
MD_B25
50
48
MD_B26
47
46
MD_B27
45
44
MD_B28
43
42
MD_B29
41
40
MD_B30
39
37
MD_B31
36
35
MD_B32
34
33
MD_B33
32
31
MD_B34
30
29
MD_B35
8
19
38
49
B
MD_A24
MD_A25
MD_A26
MD_A27
MD_A28
MD_A29
MD_A30
MD_A31
MD_A32
MD_A33
MD_A34
MD_A35
MD_A[63:0
MD_B[63:0
C
FUNCTION S2 S1
A1 TO B1, A2 TO B2
HH
A1 TO B1, A2 TO B2
Title
Size Document Number Rev
Custom
Date: Sheet of
D
S0
A1 A2[FENA]
LB1B2
HHH
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA. 95630
FET SWITCHES
B2 B1
DP/4 DIMM Design
Intel(R) 440BX AGPset 1.0
, April 09, 1998
A1 = D RA M DATA LINES
A2 = GND
B1 = D I MM 0,1 DATA LINES
B2 = D I MM 2,3 DATA LINES
11 40Thursda
E
A
(
)
y
[
]
]
[
]
]
[
]MD[
]
]
]
B
C
D
E
FET-SWITCHES (DRAM DATA LINES & ECC)
VCC
VCC
VCC
17
54
53
MD_B36
52
51
MD_B37
50
48
MD_B38
47
46
MD_B39
45
44
MD_B40
43
42
MD_B41
41
40
MD_B42
39
37
MD_B43
36
35
MD_B44
34
33
MD_B45
32
31
MD_B46
30
29
MD_B47
8
19
38
49
MD_A36
MD_A37
MD_A38
MD_A39
MD_A40
MD_A41
MD_A42
MD_A43
MD_A44
MD_A45
MD_A46
MD_A47
MD_B[63:0]11 ,15,16
FENA
R334
500
R338
500
R342
500
R346
500
R350
500
R354
500
63:0
R332
500
R336
500
R340
500
R344
500
R348
500
R352
500
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
R110
4.7K
U8
1
S0
56
S1
55
S2
2
1A1
3
1A2
4
2A1
5
2A2
6
3A1
7
3A2
9
4A1
10
4A2
11
5A1
12
5A2
13
6A1
14
6A2
15
7A1
16
7A2
18
8A1
20
8A2
21
9A1
22
9A2
23
10A1
24
10A2
25
11A1
26
11A2
27
12A1
28
12A2
PI5C16212A
VCC
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
GND
GND
GND
GND
VCC
17
54
53
MD_B48
52
51
MD_B49
50
48
MD_B50
47
46
MD_B51
45
44
MD_B52
43
42
MD_B53
41
40
MD_B54
39
37
MD_B55
36
35
MD_B56
34
33
MD_B57
32
31
MD_B58
30
29
MD_B59
8
19
38
49
MD_A48
MD_A49
MD_A50
MD_A51
MD_A52
MD_A53
MD_A54
MD_A55
MD_A56
MD_A57
MD_A58
MD_A59
63:0
MD_A
MD_B[63:0
FET ENABLE TRUTH TABLE
VCC
MD_B
63:0
17
54
53
MD_B60
52
51
MD_B61
50
48
MD_B62
47
46
MD_B63
45
44
MECC_B0
43
42
MECC_B1
41
40
MECC_B2
39
37
MECC_B3
36
35
MECC_B4
34
33
MECC_B5
32
31
MECC_B6
30
29
MECC_B7
8
19
38
49
B
MD_A60
MD_A61
MD_A62
MD_A63
ME CC_A0
ME CC_A1
ME CC_A2
ME CC_A3
ME CC_A4
ME CC_A5
ME CC_A6
ME CC_A7
MD_A[63:0
MECC_A[7:0]13 ,14,15,16
MECC_B[7:0]13 ,14,15,16
C
FUNCTION S2 S1
A1 TO B1, A2 TO B2
HH
A1 TO B1, A2 TO B2
D
S0
A1 A2[ FENA]
LB1B2
HHH
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA. 95630
Title
Size Document Number Rev
Custom
Date: Sheet of
B2 B1
FET SWITCHES
, April 09, 1998
DP/4 DIMM Design
Intel(R) 440BX AGPset 1.0
A1 = DRAM DATA LINES
A2 = GND
B1 = D I MM 0,1 DATA LINES
B2 = D I MM 2,3 DATA LINES
12 40Thursda
E
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
VCC
MD60
MD61
MD62
MD63
MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7
R109
4.7K
R111
4.7K
U7
1
S0
56
S1
55
S2
2
1A1
3
1A2
4
2A1
5
2A2
6
3A1
7
3A2
9
4A1
10
4A2
11
5A1
12
5A2
13
6A1
14
6A2
15
7A1
16
7A2
18
8A1
20
8A2
21
9A1
22
9A2
23
10A1
24
10A2
25
11A1
26
11A2
27
12A1
28
12A2
PI5C16212A
U9
1
S0
56
S1
55
S2
2
1A1
3
1A2
4
2A1
5
2A2
6
3A1
7
3A2
9
4A1
10
4A2
11
5A1
12
5A2
13
6A1
14
6A2
15
7A1
16
7A2
18
8A1
20
8A2
21
9A1
22
9A2
23
10A1
24
10A2
25
11A1
26
11A2
27
12A1
28
12A2
PI5C16212A
VCC
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
GND
GND
GND
GND
VCC
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
GND
GND
GND
GND
4 4
FENA8,11
MD[63:0
10,11 MD_A[63:0]11 ,13,14
R331
500
R333
500
R335
500
R337
500
R339
500
R341
500
R343
500
R345
500
3 3
2 2
1 1
10
R349
500
R353
500
FENA
MD
R356
500
R358
500
R360
500
R362
500
R364
500
R366
500
MECC[7:0
R347
500
R351
500
63:0
R355
500
R357
500
R359
500
R361
500
R363
500
R365
500
A
Loading...