ICST AV9341F, ICS9341F Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9341

Block Diagram

133MHz Clock Generator and Integrated Buffer for PowerPC™

9341 Rev A 10/12/99

Pin Configuration

48-pin SSOP

* Internal pull-up resistor of 120K to 3.3V on

indicated inputs

** Internal pull-down resistor of 120K to GND

on indicated inputs.

Generates the following system clocks:

- 4-CPUA (3.3V, up to 133MHz)

- 4-CPUB (3.3V, up to 133MHz)

- 8-PCI (3.3V, 33.3MHz)

- 1-OUT (3.3v, 64MHz)

- 1-OUT/2 (3.3V, OUT/2MHz)

- 2-REF (3.3V, 14.318MHz)

 Up to 133MHz frequency support.
 Stop clocks for power management

 Spread Spectrum for EMI control

±.25% center spread

Skew characteristics:

- CPU - CPU: <350ps

- CPU - PCI: <500ps

- PCI - PCI: <500ps

The ICS9341 generates all clocks required for high speed
PowerPC RISC microprocessor systems. Generating clocks in
phase with an external reference frequency.

Spread Spectrum may be enabled by driving the SS_EN pin
active. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9341
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Power Groups:

VDDREF, GNDREF = REF, X1, X2
GNDPCI, VDDPCI = PCICLK
VDD66, GND66 = 3V66
VDD48, GND48 = 48MHz
VDDCOR, GNDCOR = PLL Core
VDDLCPU/2 , GNDLCPU/2 = CPU/2
VDDLIOAPIC, GNDIOAPIC = IOAPIC

PD#

CPUB_STOP#

OUT_SEL (0:1)

PCI_STOP#

SS_EN

X1
X2

OSC

PLL

Spread

Spectrum

REF (0:1)

2

4

4

OUT

OUT/2

CPUCLKB (1:4)

CPUCLKA (1:4)

STOP

C
o
n

t
r

o

l

/ 2

PLL2

8

PCICLK (1:8)

STOP

/ 8/ 6/ 5/ 4

/ 2

/ 4

/ 5

/ 6

/ 3

GNDREF

X1
X2

VDDPCI
PCICLK1
PCICLK2
PCICLK3
PCICLK4

GNDPCI

GNDCPUB

CPUB1
CPUB2
CPUB3
CPUB4

VDDCPUB

VDDPCI
PCICLK5
PCICLK6
PCICLK7
PCICLK8

FS0
FS1

*OUT_SEL0

GNDPCI

REF1
REF0
VDDREF
CPUA1
CPUA2
SS_EN
GNDCPUA
OUT_SEL1*
PD#
VDDCPUA
CPUA3
CPUA4
CPUB_STOP#**
VDDD
VDDOUT
OUT
OUT/2
GNDOUT
GNDA
GNDD
N/C
N/C
*PCI_STOP#
VDDA

ICS9341

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9341

Pin Descriptions

Pin number Pin name Type Description

1 GNDREF PWR Ground pin for REF clocks.
2 X1 IN X T AL _IN 14 .318MHz c r ys tal input.
3 X2 OUT XTAL_OUT Crystal output.

4, 16 VDDPCI PWR 3.3Volts pow er pin for PCICLKs.

5, 6, 7, 8, 17, 18,

19, 20

PCIC LK (1:8) OUT PCI clock output at 3.3V. Syn chronous to CPU clocks.

9, 24 GNDPCI PWR Ground pin for PCI clocks.

10 GN DC P UB PWR G roun d pin for CP UB clocks.

11, 12, 13, 14 CPUB (1:4) OUT C P U C LK outputs up to 133.3MH z.

15 VD DC P UB PWR P ower pin for the CPU bank B C LK s . 3.3V .

21, 22 FS (0 :1) IN Logic - input for frequency selection.
23, 41 *OUT_SEL (0:1) IN

The se contr o l the o u tpu t func tionality of the OUT an d OUT /2 pins.

Refer to table for details.
24 GNDPC I P W R Gnd pin for P CICLKs.
25 VDDA PW R P ower for analog outputs.
26 *PCI_STOP# IN This active low input s tops PCI clocks.

27, 28 N/C - Not connected

29 GND D PWR Digitial ground
30 GN DA PW R A nalog ground
31 GN DOUT PWR G roun d for output pins.

32 OUT/2 O UT

H alf t he OUT frequ e ncy. Depe nd e nt on O U T _SE L. Refer to ta ble

fo r deta ils.
33 OUT OUT

This o utput fre que n c y is d epen den t o n OUT_SEL. Ref er to table f or

details.
34 VD DOUT PWR P ower for OU T pins 3.3V.
35 VD DD PW R Power for digitial outputs.

36 CPUB_S TO P #* * IN

This ac tive lo w in p ut sto p s the CP UB clock s at a log ic " 0 " level

when in

p

ut low .

45, 44, 38, 37 CPUA (1:4) O UT CP U CLK outputs up to 133.3MH z.

39 VD DC P UA PWR Pow er pin for the CPU bank A CLKs. 3.3V .

40 PD # IN

This asynchronous input powers down the chip when drive

active(Lo w) . T h e in ternal PL L s are d isabled an d all the ou tput clocks

are held at a Low state.
42 GN DC P UA PWR Ground pin for CP UB clocks.

43 SS_ EN IN

Sp r e ad spectr u m is turn ed on by d r iv ing this in p ut high and tur ned

off b

y

driving low.

46 VD DR EF PW R P ower pin for REF clocks.

47, 48 REF OU T 14.318MHz reference clock outputs at 3.3V.

3

ICS9341

Frequency Selection

1SF0SF

BUPC,AUPC

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ICP

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FER

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11 3.3313.33813.41

10 0013.33813.41
01 3.383.33813.41
00 6.663.33813.41

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2/TUO

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