5
D D
4
3
2
1
Laduree 15.6" Intel Crescent Bay
UMA/DIS Co-lay Schematic
C C
Broadwell-U 15W TDP
nVidia N16S-GM 16W
REV:1
B B
2015-02-13
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Cover Page
Cover Page
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, February 13, 2015
Friday, February 13, 2015
Friday, February 13, 2015
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Cover Page
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
1
1 102
1 102
1 102
1
1
5
Laduree 15.6" Block Diagram
LCD
1366x768(LVDS HD)
D D
VRAM*4
128M*16/256M*16
78,79,80,81
DDR3L/1.35V
900MHz
nVidia
27MHz
N16S-GM-S 930M
(15.6" DIS only)
23x23mm
C C
RJ45
CONN
16W
73,74,75,76,77
Lan Controller
31
Realtek
RTL8111HSH-CG (10/100/1000)
IO Board
SD Card
Slot
33
CardReader
Realtek
RTS5237S-GR
Sensor Board (On LCD side)
Touch Control Board
Accelerometer+
e-Compass+
B B
Gyro
HP9DS1
Accelerometer
ST
IO Board
1920x1080(eDP FHD)
4
PCIE x 4 lanes
USB2.0 CONN
67
HP3DC2
Touch CONN.
Touch Control Board
Synaptics
S7501
HDMI 1.4a
54
USB3.0 Ext.Port0
w/ USB Charger
TPS2546
52
USB3.0 Ext.Port1
I2C
Camera module + DMIC
63
4
eDPx1/2/4
eDP to LVDS
LVDS
52
52
HDMI
Parade
PS8625QFN
HDMI Redriver
Parade
30
PCIe
32
USB2.0 USB2.0
34
35
Sensor Hub
ST
STM32F102CBT6
66
52
I2C
PCIe (15" only)
PS8407A
PCIe
63
DMIC
55
54
PCIe
USB2.0 & USB3.0
USB2.0 & USB3.0
USB2.0
USB2.0
DP
Intel CPU
Broadwell-U
BGA1168
15W
8 USB 2.0/1.1 ports
6 USB 3.0 ports
High Definition Audio
4 SATA ports
8 PCIE ports
LPC I/F
ACPI 4.0a
3,4,5,6,7,8,9,10
11,15,16,17,18,19,20
3
DDR3L 1333/1600 Channel A
DDR3L / 1.35V
DDR3L 1333/1600 Channel B
PCIe / USB2.0
SATA/ PCIe
DDR3L-1600
SO-DIMM1
DDR3L-1600
SO-DIMM2
NGFF
WLAN + BT
NGFF
SSD
2
Project code : 4PD048010001
PCB P/N : 14257
Revision : SA
12
13
58
60
1
CHARGER
HPA02224RGRR
OUTPUTS INPUTS
AD+
BT+ DCBATOUT
SYSTEM DC/DC
TPS51225RUKR-GP
INPUTS OUTPUTS
DCBATOUT
5V_AUX_S5
3D3V_AUX_S5
5V_S5
3D3V_S5
CPU DC/DC
TPS51624RSMR
INPUTS
DCBATOUT
OUTPUTS
CPU_CORE
SYSTEM DC/DC
RT8068AZQWID
DCBATOUT 1D5V_S0
OUTPUTS INPUTS
SYSTEM DC/DC
SY8208DQNC
INPUTS
DCBATOUT
OUTPUTS
1D05V_LAN
SYSTEM DC/DC
TPS51716RUKR
INPUTS
DCBATOUT
OUTPUTS
1D35V_PWR
VGA
RT8179CGQW
DCBATOUT
OUTPUTS INPUTS
VGA_CORE
44
45
46,47
51
48
49
80,81
VGA
SATA
2.5" HDD/ SSHD
56
RT8068AZQWID
SY8208DQNC
INPUTS OUTPUTS
3D3V_S5
DCBATOUT 0D95V
1D8V
82
PCB LAYER
SPI
LPC debug port
LPC BUS
TPM 2.0
Infineon
SLB9665TT2.0
SPI Flash
8MB
25
65
88
SPI
KBC
ene
KB9028Q
Touch
PAD
62 62
Int.
KB
24
Int.
BATT
Fan Control
PWM
SMBus
I2C
43
Thermal
NCT7718W
Accelerometer
HP3DC2
ST
26
26
67
L1:
L2:
L3:
L4:
TOP
GND
Signal
Signal
L5:
L6:
GND/PWR
BOTTOM
A A
Combo Jack
Realtek
ALC3227-CG
27
Speaker
29
Audio Codec
5
4
HDA BUS
32.768KHz 24MHz
3
CPU_XDP
96
2
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, January 30, 2015
Friday, January 30, 2015
Friday, January 30, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Block Diagram
Block Diagram
Block Diagram
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
1
2 102
2 102
2 102
1
1
1
SSID = CPU
D
C
5
4
3
2
1
B
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
CPU (Reserved)
CPU (Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 30, 2015
Friday, January 30, 2015
Friday, January 30, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (Reserved)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
1
3 102
3 102
3 102
1
5
SSID = CPU
1D05V_VCCST
4
3
2
1
D
1 2
R401
R401
62R2J-GP
62R2J-GP
C
DDR3_DRAMRST# 12,13
SC100P50V2JN-L-GP
SC100P50V2JN-L-GP
20150205 MV-1 Ita
B
R420
R420
470R2F-GP
470R2F-GP
C403
C403
H_PROCHOT#
1 2
C402
C402
SC47P50V2JN-L1-GP
SC47P50V2JN-L1-GP
1D35V_S3
1 2
1 2
DY
DY
1 2
H_PECI 24
H_PROCHOT# 24,46
R406 200R2F-L1-GP R406 200R2F-L1-GP
1 2
R407 120R2F-GP R407 120R2F-GP
1 2
R408 100R2F-L1-GP-U R408 100R2F-L1-GP-U
1 2
R402
R402
0R0402-PAD
0R0402-PAD
DDR_PG_CTRL 12
Layout Note:
1. SM_RCOMP trace width=12~15mil
2. Isolation Spacing: 20mil
3. Total trace length<500mil
1 2
R413
R413
56R2J-L1-GP
56R2J-L1-GP
R403
R403
10KR2J-L-GP
10KR2J-L-GP
H_PROCHOT#_R
H_CPUPWRGD
1 2
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST#
CPU1B
CPU1B
D61
PROC_DETECT#
K61
CATERR#
N62
PECI
K63
PROCHOT#
C61
PROCPWRGD
AU60
SM_RCOMP0
AV60
SM_RCOMP1
AU61
SM_RCOMP2
AV15
SM_DRAMRST#
AV61
SM_PG_CNTL1
BROADWELL-1-GP
BROADWELL-1-GP
MISC
MISC
THERMAL
THERMAL
PWR
PWR
DDR3L
DDR3L
BROADWELL
BROADWELL
JTAG
JTAG
2 OF 19
2 OF 19
PRDY#
PREQ#
PROC_TCK
PROC_TMS
PROC_TRST#
PROC_TDI
PROC_TDO
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
XDP_TMS
XDP_TDI
XDP_TDO
J62
K62
E60
E61
E59
F63
F62
J60
H60
H61
H62
K59
H63
K60
J61
R404 51R2J-2-GP
R404 51R2J-2-GP
1 2
DY
DY
R405 51R2J-2-GP
R405 51R2J-2-GP
1 2
DY
DY
R409 51R2J-2-GP R409 51R2J-2-GP
1 2
XDP_PRDY# 96
XDP_PREQ# 96
XDP_TCK 96
XDP_TMS 96
XDP_TRST# 19,96
XDP_TDI 96
XDP_TDO 96
XDP_BPM0 96
XDP_BPM1 96
1D05V_VCCST
XDP_TCK
XDP_TRST#
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
A
Title
Title
Title
CPU (THERMAL/CLOCK/PM)
CPU (THERMAL/CLOCK/PM)
CPU (THERMAL/CLOCK/PM)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
R410 51R2J-2-GP R410 51R2J-2-GP
1 2
R411 51R2J-2-GP
R411 51R2J-2-GP
1 2
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
4 102
4 102
4 102
1
1
1
5
4
3
2
1
SSID = CPU
4 OF 19
3 OF 19
CPU1C
CPU1C
M_A_DQ[15:0] 12
D D
M_B_DQ[15:0] 13
M_A_DQ[31:16] 12
C C
M_B_DQ[31:16] 13
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
BROADWELL
BROADWELL
DDR CHANNEL A
DDR CHANNEL A
3 OF 19
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS#
SA_WE#
SA_CAS#
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
AP33
AR32
AP32
AY34
AW34
AU34
AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
AP49
AR51
AP51
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DQS_DN0
M_A_DQS_DN1
M_B_DQS_DN0
M_B_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_B_DQS_DN2
M_B_DQS_DN3
M_A_DQS_DP0
M_A_DQS_DP1
M_B_DQS_DP0
M_B_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_B_DQS_DP2
M_B_DQS_DP3
M_A_CLK#0 12
M_A_CLK0 12
M_A_CLK#1 12
M_A_CLK1 12
M_A_CKE0 12
M_A_CKE1 12
M_A_CS#0 12
M_A_CS#1 12
M_A_RAS# 12
M_A_WE# 12
M_A_CAS# 12
M_A_BS0 12
M_A_BS1 12
M_A_BS2 12
M_A_A[15:0] 12
+V_SM_VREF_CNT 14
DDR_WR_VREF01 14
DDR_WR_VREF02 14
M_A_DQ[47:32] 12
M_B_DQ[47:32] 13
M_A_DQ[63:48] 12
M_A_DQS_DN[7:0] 12
M_A_DQS_DP[7:0] 12
M_B_DQS_DN[7:0] 13
M_B_DQS_DP[7:0] 13
M_B_DQ[63:48] 13
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
CPU1D
CPU1D
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
BROADWELL
BROADWELL
DDR CHANNEL B
DDR CHANNEL B
4 OF 19
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS#
SB_WE#
SB_CAS#
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_A_DQS_DN4
M_A_DQS_DN5
M_B_DQS_DN4
M_B_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
M_B_DQS_DN6
M_B_DQS_DN7
M_A_DQS_DP4
M_A_DQS_DP5
M_B_DQS_DP4
M_B_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
M_B_DQS_DP6
M_B_DQS_DP7
M_B_CLK#0 13
M_B_CLK0 13
M_B_CLK#1 13
M_B_CLK1 13
M_B_CKE0 13
M_B_CKE1 13
M_B_CS#0 13
M_B_CS#1 13
M_B_RAS# 13
M_B_WE# 13
M_B_CAS# 13
M_B_BS0 13
M_B_BS1 13
M_B_BS2 13
M_B_A[15:0] 13
BROADW ELL-1-GP
BROADW ELL-1-GP
BROADW ELL-1-GP
A A
5
4
3
BROADW ELL-1-GP
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
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Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU (DDR)
CPU (DDR)
CPU (DDR)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
5 102
5 102
5 102
1
1
1
1
5
4
3
2
1
SSID = CPU
19 OF 19
CPU1S
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
AA62
U63
AA61
U62
V63
H18
B12
T63
T62
T61
T60
A5
E1
D1
J20
CPU1S
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
RSVD#A5
RSVD#E1
RSVD#D1
RSVD#J20
RSVD#H18
TD_IREF
BROADWELL
BROADWELL
RESERVED
RESERVED
PROC_OPI_RCOMP
CFG[19:0] 96
D D
R607
C C
R607
49D9R2F-GP
49D9R2F-GP
1 2
R606
R606
8K2R2F-1-GP
8K2R2F-1-GP
1 2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
TD_IREF
19 OF 19
RSVD_TP#AV63
RSVD_TP#AU63
RSVD_TP#C63
RSVD_TP#C62
RSVD#B43
RSVD_TP#A51
RSVD_TP#B51
RSVD_TP#L60
RSVD#N60
RSVD#W23
RSVD#Y22
RSVD#AV62
RSVD#D58
VSS
VSS
RSVD#P20
RSVD#R20
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
AV62
D58
P22
N21
P20
R20
RSVDAV63
RSVDAU63
RSVDA51
RSVDB51
OPI_COMP1
TP601 TPAD14-OP-GP TP601 TPAD14-OP-GP
1
TP602 TPAD14-OP-GP TP602 TPAD14-OP-GP
1
20141126 SE - Ita
TP604 TPAD14-OP-GP TP604 TPAD14-OP-GP
1
TP605 TPAD14-OP-GP TP605 TPAD14-OP-GP
1
1 2
R610
R610
49D9R2F-GP
49D9R2F-GP
CFG9
CFG0
B B
1
TP606
TP606
TPAD14-OP-GP
TPAD14-OP-GP
1 2
DY
DY
R605
R605
1KR2J-1-GP
1KR2J-1-GP
NO SVID PROTOCOL CAPABLE VR CONNECTED
0:NO VR SUPPORTING SVID IS PRESENT. THE CHIP
WILL NOTGENERATE (OR RESPOND TO) SVID ACTIVITY
1:VRS SUPPORTING SVID PROTOCOL ARE PRESENT
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
CFG3
1
TP607
TP607
TPAD14-OP-GP
TPAD14-OP-GP
CFG[3]
0 : ENABLED
SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
1 : DISABLED
CFG4
1 2
R603
R603
1KR2J-L2-GP
1KR2J-L2-GP
A A
5
DISPLAY PORT PRESENCE STRAP
0 : ENABLED
CFG[4]
AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT
1 : DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT
4
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
CPU (CFG)
CPU (CFG)
CPU (CFG)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
6 102
6 102
6 102
1
1
1
1
SSID = CPU
5
4
3
2
1
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
CPU_CORE
12 OF 19
CPU1L
CPU1L
L59
J58
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
F59
N58
AC58
E63
AB23
A59
E20
AD23
AA23
AE59
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
AC22
AE22
AE23
AB57
AD57
AG57
C24
C28
C32
BROADW ELL-1-GP
BROADW ELL-1-GP
RSVD#L59
RSVD#J58
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD#N58
RSVD#AC58
VCC_SENSE
RSVD#AB23
VCCIO_OUT
VCOMP_OUT
RSVD#AD23
RSVD#AA23
RSVD#AE59
VIDALERT#
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
VSS
PWR_DEBUG#
VSS
RSVD_TP#P60
RSVD_TP#P61
IVR_ERROR
IST_TRIGGER
RSVD#T59
RSVD#AD60
RSVD#AD59
RSVD#AA59
RSVD#AE60
RSVD#AC59
RSVD#AG58
RSVD#U59
RSVD#V59
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
BROADWELL
BROADWELL
HSW ULT POWER
HSW ULT POWER
DY
DY
CPU_CORE
1D35V_S3
1 2
VCC_SENSE
VCCIO_OUT_R
CPU_SVIDALRT#
VR_READY
D D
1D05V_VCCST
130R2F-1-GP
130R2F-1-GP
R703
R703
1 2
75R2F-2-GP
75R2F-2-GP
R704
R704
1 2
150R2F-4-L-GP
150R2F-4-L-GP
R706
R706
1 2
CPU_CORE
C C
1D05V_VCCST
B B
R701 close to CPU
R701
R701
100R2F-L1-GP-U
100R2F-L1-GP-U
1 2
C703
C703
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
Close to CPU
H_CPU_SVIDDAT
VR_SVID_ALERT#
PWR_DEBUG
Follow Intel CRB
1 2
VCC_SENSE 46
C703,C715 close to CPU
PIN AC22 AE22 AE23
DY
DY
1 2
C715
C715
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
VR_SVID_ALERT# 46
H_CPU_SVIDCLK 46
H_CPU_SVIDDAT 46
VCCST_PWRGD 96
PWR_DEBUG 96
1D05V_S0
20150205 MV-1 Ita
1D05V_VCCST
FC701
FC701
SC10U25V5KX-GP
SC10U25V5KX-GP
1V_VCOMP_OUT
H_VR_EN 46
1 2
R711
R711
0R0402-PAD
0R0402-PAD
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
1 2
DY
DY
DY
DY
1D05V_VCCST
43R2J-GP
43R2J-GP
1D05V_VCCST
C716
C716
1 2
FC702
FC702
SC10U25V5KX-GP
SC10U25V5KX-GP
CPU_CORE
0R2J-L-GP
0R2J-L-GP
R707
R707
1 2
R705
R705
1 2
12 OF 19
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RN702
RN702
1
8
2
7
3
6
1D05V_S0_PWRGD 36,48,51
A A
5
4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
VCCST_PWRGD
IMVP_PWRGD 36,46
4
3
RN703
RN703
1
2
3
4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
8
7
6
VR_READY
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU (VCC_CORE)
CPU (VCC_CORE)
CPU (VCC_CORE)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
7 102
7 102
7 102
1
1
1
1
5
4
3
2
1
SSID = CPU
D D
1 OF 19
CPU1A
CPU1A
BROADWELL
BROADWELL
1 OF 19
HDMI_DATA_CPU_N2 54
HDMI_DATA_CPU_P2 54
HDMI_DATA_CPU_N1 54
HDMI
C C
HDMI_DATA_CPU_P1 54
HDMI_DATA_CPU_N0 54
HDMI_DATA_CPU_P0 54
HDMI_DATA_CPU_N3 54
HDMI_DATA_CPU_P3 54
C54
C55
B58
C58
B55
A55
A57
B57
C51
C50
C53
B54
C49
B50
A53
B53
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP DDI
EDP DDI
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
C45
B46
A47
B47
C47
C46
A49
B49
A45
B45
D20
A43
EDP_RCOMP
eDP_TX_CPU_N0 55
eDP_TX_CPU_P0 55
eDP_TX_CPU_N1 55
eDP_TX_CPU_P1 55
eDP_TX_CPU_N2 52
eDP_TX_CPU_P2 52
eDP_TX_CPU_N3 52
eDP_TX_CPU_P3 52
eDP_AUX_CPU_N 55
eDP_AUX_CPU_P 55
eDP
R801 24D9R2F-L-GP R801 24D9R2F-L-GP
1 2
1V_VCOMP_OUT
Layout Note:
BROADWELL-1-GP
BROADWELL-1-GP
B B
Design Guideline:
EDP_COMP keep routing length max 100 mils.
Trace Width:20 mils.
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
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Wistron Corporation
A A
Title
Title
Title
CPU (DDI/EDP)
CPU (DDI/EDP)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
CPU (DDI/EDP)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
2
Laduree-BDW 15.6"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
1
8 102
8 102
8 102
1
1
5
4
3
2
1
SSID = CPU
D D
16 OF 19
CPU1P
CPU1P
BROADWELL
D33
VSS
D34
VSS
D35
VSS
D37
VSS
D38
VSS
D39
VSS
D41
VSS
D42
VSS
D43
VSS
D45
VSS
D46
VSS
D47
VSS
D49
VSS
D5
VSS
D50
C C
B B
VSS
D51
VSS
D53
VSS
D54
VSS
D55
VSS
D57
VSS
D59
VSS
D62
VSS
D8
VSS
E11
VSS
E17
VSS
F20
VSS
F26
VSS
F30
VSS
F34
VSS
F38
VSS
F42
VSS
F46
VSS
F50
VSS
F54
VSS
F58
VSS
F61
VSS
G18
VSS
G22
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
H13
VSS
BROADWELL-1-GP
BROADWELL-1-GP
BROADWELL
16 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
R901 close to CPU
VSS_SENSE
R901
R901
100R2F-L1-GP-U
100R2F-L1-GP-U
VSS_SENSE 46
1 2
Layout Note:
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
CPU (VSS)
CPU (VSS)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
CPU (VSS)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
2
Laduree-BDW 15.6"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
1
9 102
9 102
9 102
1
1
5
4
3
2
1
SSID = MCP
1D35V_S3
1D35V_S3
D D
2.2uF x 4
10uF x 6
MAX: 9.76A
1D35V_S3
1 2
C1034
C1034
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
1 2
C1033
C1033
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
1 2
C1032
C1032
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
1 2
C1031
C1031
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
1 2
EC1001
EC1001
1 2
EC1002
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
EC1002
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
20141203 SE - Ita
1 2
C C
C1040
C1040
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
1 2
C1039
C1039
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
1 2
C1038
C1038
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
1 2
C1037
C1037
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
1 2
C1036
C1036
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
1 2
C1035
C1035
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
CPU_CORE
CPU_CORE
22uF x 10
DUMMY 22UF*2
C1009
C1010
C1011
C1012
C1012
1 2
DY
B B
DY
C1011
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
DY
DY
C1010
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
C1009
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
C1008
C1008
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
C1007
C1007
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
C1006
C1006
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
C1005
C1005
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
C1004
C1004
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
C1003
C1003
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
1 2
C1002
C1002
CPU_CORE
C1001
C1001
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
1 2
EC1003
EC1003
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1 2
EC1004
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
EC1004
1 2
EC1005
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
EC1005
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
20141204 SE - Ita change back
CPU_CORE
Wistron Confidential document, Anyone can not
1 2
TC1001
TC1001
ST220U2VDM-5-GP
ST220U2VDM-5-GP
79.22719.2BL
79.22719.2BL
A A
5
4
3
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (Power CAP1)
CPU (Power CAP1)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (Power CAP1)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Friday, January 30, 2015
Friday, January 30, 2015
Friday, January 30, 2015
2
Laduree-BDW 15.6"
10 102
10 102
10 102
1
1
1
1
5
4
3
2
1
1D05V_S0 1D05V_MODPHY 1D05V_MODPHY
D D
C1102;C1103
pin K9 L10
1 2
C1102
C1102
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
C1103
C1103
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
Page 21
20141022 SC - Terry 20141022 SC - Terry
0.041A 0.042A
1 2
L1101
L1101
IND-2D2UH-196-GP
IND-2D2UH-196-GP
2nd = 68.2R21G.10Q
2nd = 68.2R21G.10Q
C1108 ;C1109
pin B18
1 2
C1108
C1108
1 2
C1109
C1109
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
C1104 ;C1106
1 2
L1102
L1102
IND-2D2UH-196-GP
IND-2D2UH-196-GP
2nd = 68.2R21G.10Q
2nd = 68.2R21G.10Q
pin B11
1 2
C1104
C1104
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
MAX: 1.92A
1 2
C1106
C1106
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
3D3V_RTC_AUX 1D05V_VCCUSB3PLL_S0 1D05V_VCCSATA3PLL_S0
1 2
1 2
C1135
C1135
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
20141203 SE - Ita
C1135;C1136
pin AG10
C1136
C1136
SCD1U50V3KX-L-GP
SCD1U50V3KX-L-GP
3D3V_SUS
1 2
C1116
C1116
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
20141204 SE - Ita change back
C1116 pin AC9, AA9
MAX: 3.51A
1 2
C1111
C1111
1D05V_VCCCLK_S0 1D05V_VCCACLKPLL_S0 1D05V_S0 1D05V_S0
1 2
C1115
C1115
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
3D3V_S0
MAX: 0.285A
1 2
C C
C1101 pin V8
C1119 pin K14
1 2
C1119
C1119
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
C1101
C1101
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
C1118;C1120
1 2
L1104
L1104
IND-2D2UH-196-GP
IND-2D2UH-196-GP
2nd = 68.2R21G.10Q
2nd = 68.2R21G.10Q
pin A20
1 2
C1118
C1118
1 2
C1120
C1120
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
C1111;C1115
1 2
L1103
L1103
IND-2D2UH-196-GP
IND-2D2UH-196-GP
2nd = 68.2R21G.10Q
2nd = 68.2R21G.10Q
pin J18, K19
20141204 SE - Ita change back
1D05V_S0 1D05V_S0 1D05V_S0
1 2
C1144
C1144
pin AE9
B B
A A
5
C1144
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
C1110 pin J11
C1134 C1141 pin J11, AE8
4
1 2
C1134
C1134
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
1 2
C1141
C1141
C1110
C1110
SC22U6D3V5MX-L3-GP
SC22U6D3V5MX-L3-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
3
C1122;C1123
pin AA21
1 2
C1122
C1122
1 2
C1123
C1123
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU (Power CAP2)
CPU (Power CAP2)
CPU (Power CAP2)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Friday, January 30, 2015
Friday, January 30, 2015
Friday, January 30, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
11 102
11 102
11 102
1
1
1
1
5
SSID = MEMORY
D D
C C
B B
M_VREF_CA_D IMM0
1 2
C1226
C1226
SCD1U16V2KX- L-GP
SCD1U16V2KX- L-GP
1 2
C1225
C1225
SC2D2U10V3KX- L-GP
SC2D2U10V3KX- L-GP
DY
DY
M_A_A[15:0] 5
M_A_BS2 5
M_A_BS0 5
M_A_BS1 5
M_A_DQ[15:0] 5
M_A_DQ[31:16] 5
M_A_DQ[47:32] 5
M_A_DQ[63:48] 5
M_A_DQS_DN[7: 0] 5
M_A_DQS_DP[7:0] 5
M_VREF_CA_D IMM0
DDR3_DR AMRST# 4,13
M_VREF_DQ_D IMM0
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
M_A_DIM0_ODT0
M_A_DIM0_ODT1
0D675V_VREF_S0
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
H = 4mm
Close DIMM1 VREF_CA pin
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
109
108
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
10
27
45
62
135
152
169
186
12
29
47
64
137
154
171
188
116
120
126
1
30
203
204
M_VREF_DQ_D IMM0
1 2
1 2
C1205
C1205
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
DY
DY
DIMM1
DIMM1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
DDR3-204P- 306-GP
DDR3-204P- 306-GP
062.10011.0461
062.10011.0461
C1211
C1211
SC2D2U10V3ZY- 1GP
SC2D2U10V3ZY- 1GP
RAS#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1
NC#2
NC#/TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
4
NP1
NP1
NP2
NP2
110
113
WE#
115
114
121
73
74
101
CK0
103
102
CK1
104
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
200
SDA
202
SCL
SA0
SA1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TS#_DIMM0_1
198
199
SA0_DIM0
197
SA1_DIM0
201
77
122
1D35V_S3
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
0D675V_VREF_S0
1 2
C1214
C1214
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
M_A_RAS# 5
M_A_WE# 5
M_A_CAS# 5
M_A_CS#0 5
M_A_CS#1 5
M_A_CKE0 5
M_A_CKE1 5
M_A_CLK0 5
M_A_CLK#0 5
M_A_CLK1 5
M_A_CLK#1 5
SMB_DATA 13,18,62,96
SMB_CLK 13,18,62,96
3D3V_S0
SA0_DIM0
SA1_DIM0
1 2
1 2
FC1201
FC1201
C1203
C1203
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
Thermal EVENT
R1204
1D35V_S3
1 2
C1215
C1215
R1204
10KR2J-L-GP
10KR2J-L-GP
1 2
1 2
C1206
C1206
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
1 2
C1223
C1223
1 2
C1219
C1219
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
Layout Note:
Place these Caps near
SO-DIMMA.
SODIMM A DECOUPLING
1 2
C1207
C1207
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
TS#_DIMM0_1
1 2
C1222
C1222
C1216
C1216
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
FC1207
FC1207
3D3V_S0
1 2
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC10U 25V5KX-GP
SC10U25V5KX-GP
3
1
2 3
RN1202
RN1202
SRN10KJ-5-G P
SRN10KJ-5-G P
4
1 2
FC1208
FC1208
SC100P50V2JN-3GP
SC100P50V2JN-3GP
RF
RF
RF
RF
1 2
C1208
C1208
C1209
C1209
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
1 2
1 2
C1220
C1220
C1221
C1221
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
Place these caps
close to VTT1 and
VTT2.
0D675V_VREF_S0
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
DDR_PG_CT RL 4
1 2
1 2
C1210
C1210
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
DY
DY
1 2
FC1202
FC1202
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
DY
DY
1 2
1 2
FC1204
FC1204
FC1210
FC1210
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
RF
RF
FC1203
FC1203
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
DY
DY
SC10U25V5KX-GP
SC10U25V5KX-GP
Q1202
Q1202
DMN5L06K-7-G P
DMN5L06K-7-G P
84.05067.031
84.05067.031
1 2
FC1205
FC1205
SC10U 25V5KX-GP
SC10U25V5KX-GP
RF
RF
1 2
FC1209
FC1209
SC100P50V2JN-3GP
SC100P50V2JN-3GP
RF
RF
Q1202 Q1203
Vth1V
1D35V_S3
G
D S
1 2
FC1206
FC1206
SC100P50V2JN-3GP
SC100P50V2JN-3GP
RF
RF
SODIMM Memory Connectivity and Topology
ODT Signal Connectivity and Support
For DDR3L SODIMM designs, Intel recommends ODT signals not to be routed between
CPU and DIMM on platform, leave ODT at CPU as no-connect (open), and tie DIMM
ODT to VDDQ through FET and resistor. The reason for this additional ODT-control
circuitry on the platform is to save power dissipation by turning off VDDQ to VTT path
during low power states, as ODT signal is terminated to VTT through RTT on SODIMM.
The ODT value for DDR3L SODIMM 1-DPC platform will be encoded in the write
command and use RTT_NOM = Off and RTT_WR = (60,120) Ohm.
CPU ODT output would be NOCON
SODIMM ODT input should be tied to VDDQ through a FET and a resistor to
support low power states.
84.05067.031
3D3V_S0
1 2
R1212
R1212
220KR2J-L2-GP
220KR2J-L2-GP
2
1D35V_S3
D S
Q1203
Q1203
DMN5L06K-7-G P
DMN5L06K-7-G P
G
84.05067.031
84.05067.031
ODT resistor must be 66.5 ohm
1 2
R1208 66D5R2F-GP R1208 66D5R2F-GP
M_A_B_DIM_ODT
DDR_PG_OU T 49
1 2
R1209 66D5R2F-GP R1209 66D5R2F-GP
1 2
R1210 66D5R2F-GP R1210 66D5R2F-GP
1 2
R1211 66D5R2F-GP R1211 66D5R2F-GP
M_A_DIM0_ODT0
M_A_DIM0_ODT1
1
M_B_DIM0_ODT0 13
M_B_DIM0_ODT1 13
A A
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Title
Title
Title
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Thursday, Feb ruary 12, 2015
Thursday, Feb ruary 12, 2015
Thursday, Feb ruary 12, 2015
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O.C.
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
1
12 102
12 102
12 102
1
1
1
5
DIMM2
SSID = MEMORY
D D
C C
B B
M_VREF_CA_D IMM0
1 2
1 2
C1330
C1330
SCD1U16V2KX- L-GP
SCD1U16V2KX- L-GP
M_B_DQ[15:0] 5
M_B_DQ[31:16] 5
M_B_DQ[47:32] 5
M_B_DQS_DN[7: 0] 5
M_B_DQS_DP[7:0] 5
M_B_DIM0_ODT0 12
M_B_DIM0_ODT1 12
C1329
C1329
SC2D2U10V3KX- L-GP
SC2D2U10V3KX- L-GP
DY
DY
M_B_A[15:0] 5
M_B_BS2 5
M_B_BS0 5
M_B_BS1 5
M_B_DQ[63:48] 5
M_VREF_CA_D IMM0
M_VREF_DQ_D IMM1
DDR3_DR AMRST# 4,12
M_B_DQ23
M_B_DQ17
M_B_DQ20
M_B_DQ19
M_B_DQ22
M_B_DQ16
M_B_DQ21
M_B_DQ18
M_B_DQ5
M_B_DQ4
M_B_DQ7
M_B_DQ6
M_B_DQ3
M_B_DQ2
M_B_DQ0
M_B_DQ1
M_B_DQ9
M_B_DQ14
M_B_DQ11
M_B_DQ13
M_B_DQ12
M_B_DQ8
M_B_DQ15
M_B_DQ10
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ31
M_B_DQ29
M_B_DQ30
M_B_DQ28
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ38
M_B_DQ32
M_B_DQ33
M_B_DQ37
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQS_DN2
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
M_B_DQS_DP2
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
0D675V_VREF_S0
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
H=4mm
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
DIMM2
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
109
108
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
10
27
45
62
135
152
169
186
12
29
47
64
137
154
171
188
116
120
126
1
30
203
204
DDR3-204P- 327-GP
DDR3-204P- 327-GP
062.10011.0841
062.10011.0841
20141202 SE - Ita
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
SKT_DDR 204P SMD
SKT_DDR 204P SMD
4
RAS#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1
NC#2
NC#/TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
3
NP1
NP1
NP2
NP2
110
M_B_RAS# 5
113
115
114
121
73
74
101
103
102
104
11
28
46
63
136
153
170
187
200
202
198
199
197
201
77
122
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
M_B_WE# 5
M_B_CAS# 5
M_B_CS#0 5
M_B_CS#1 5
M_B_CKE0 5
M_B_CKE1 5
M_B_CLK0 5
M_B_CLK#0 5
M_B_CLK1 5
M_B_CLK#1 5
SMB_DATA 12,18,62,96
SMB_CLK 12,18,62,96
TS#_DIMM1_1
SB0_DIM0
SB1_DIM0
1D35V_S3
0D675V_VREF_S0
1D35V_S3
1 2
C1314
C1314
0D675V_VREF_S0
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
3D3V_S0
1 2
C1303
C1303
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
Layout Note:
Place these Caps near
SO-DIMMB.
SODIMM B DECOUPLING
1 2
1 2
C1320
C1320
EC1305
EC1305
1 2
C1315
C1315
1 2
1 2
C1307
C1307
EC1306
EC1306
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
1 2
1 2
C1318
C1318
C1321
C1321
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
C1316
C1316
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
C1317
C1317
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SB1_DIM0
SB0_DIM0
1 2
FC1301
FC1301
SC100P50V2JN-3GP
SC100P50V2JN-3GP
RF
RF
1 2
1 2
C1308
C1308
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
1 2
C1319
C1319
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
Place these caps
close to VTT1 and
VTT2.
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
WE#
CK0
CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
SA0
SA1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SRN10KJ-5-G P
SRN10KJ-5-G P
1 2
FC1302
FC1302
SC10U 25V5KX-GP
SC10U25V5KX-GP
C1309
C1309
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
RN1302
RN1302
1
2 3
1 2
RF
RF
1 2
C1310
C1310
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
FC1303
FC1303
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
3D3V_S0
4
DY
DY
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
SO-DIMMB is placed farther from
the Processor than SO-DIMMA
Thermal EVENT
TS#_DIMM1_1
1 2
1 2
FC1310
FC1310
RF
RF
1 2
FC1311
FC1311
FC1304
FC1304
SC10U 25V5KX-GP
SC10U25V5KX-GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
R F
RF
DY
DY
R1302
R1302
10KR2J-L-GP
10KR2J-L-GP
1 2
3D3V_S0
2
1
Close DIMM2 VREF_CA pin
1 2
FC1320
FC1320
SCD1U25V2KX-L-GP
M_VREF_DQ_D IMM1
1 2
1 2
C1327
C1327
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
DY
DY
C1328
C1328
SC2D2U10V3ZY- 1GP
A A
SC2D2U10V3ZY- 1GP
5
4
SCD1U25V2KX-L-GP
DY
DY
1 2
1 2
FC1322
FC1322
FC1321
FC1321
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC10U 25V5KX-GP
SC10U25V5KX-GP
R F
RF
RF
RF
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Title
Title
Title
DDR3-SODIMM2
DDR3-SODIMM2
DDR3-SODIMM2
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Thursday, Feb ruary 12, 2015
Thursday, Feb ruary 12, 2015
Thursday, Feb ruary 12, 2015
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O.C.
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
1
13 102
13 102
13 102
1
1
1
5
4
3
VREF circuit -M1 (Voltage Driver Network) & M3 (Driven by Processor) Implementation
2
1
D D
C C
B B
Driven by process (PIN#AR51) Driven by process (PIN#AP51)
DDR_WR_VREF01 5 DDR_WR_VREF02 5
SA_DIMM_VREFDQ SB_DIMM_VREFDQ
DDR_WR_VREF01
1 2
C1401
C1401
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
+V_VREF_PATH1
1 2
R1403
R1403
24D9R2F-L-GP
24D9R2F-L-GP
Close to DIMM
1D35V_S3
1 2
R1406
R1406
1K8R2F-GP
DDR_WR_VREF01
DDR_WR_VREF02
R1408
R1408
1 2
2R2F-GP
2R2F-GP
R1416
R1416
1 2
4D99R2F-GP
4D99R2F-GP
1 2
1D35V_S3
1 2
1 2
1K8R2F-GP
R1412
R1412
1K8R2F-GP
1K8R2F-GP
R1415
R1415
1K8R2F-GP
1K8R2F-GP
R1419
R1419
1K8R2F-GP
1K8R2F-GP
M_VREF_DQ_DIMM0 M_VREF_CA_DIMM0
Close to DM
M_VREF_DQ_DIMM1
SODIMM1
SODIMM2
DDR_WR_VREF02
Close to DIMM
DDR_VREF_S3
1 2
DY
DY
R1405
R1405
0R2J-2-GP
0R2J-2-GP
1 2
C1402
C1402
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
+V_VREF_PATH2
1 2
R1404
R1404
24D9R2F-L-GP
24D9R2F-L-GP
1D35V_S3
1 2
R1407
R1407
1K8R2F-GP
1K8R2F-GP
1 2
R1413
R1413
1K8R2F-GP
1K8R2F-GP
0820-Anthony
R1422
R1422
1 2
2D7R2F-1-GP
2D7R2F-1-GP
+V_SM_VREF_CNT
1 2
C1403
C1403
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
+V_VREF_PATH3
1 2
R1414
R1414
24D9R2F-L-GP
24D9R2F-L-GP
+V_SM_VREF_CNT 5
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
A A
5
4
3
2
application without get Wistron permission
UMA
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Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
M1 & M3 Implementation
M1 & M3 Implementation
M1 & M3 Implementation
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
14 102
14 102
14 102
1
1
1
1
5
SSID = CPU
4
3
2
1
D D
C C
B B
3D3V_S0
RN1503
RN1503
SRN10KJ-L-GP
SRN10KJ-L-GP
1
2 3
RN1504
RN1504
SRN10KJ-6-GP
SRN10KJ-6-GP
1
2
3
4 5
R1523
R1523
10KR2J-L-GP
10KR2J-L-GP
R1524
R1524
10KR2J-L-GP
10KR2J-L-GP
4
8
7
6
1 2
1 2
DY
DY
INT_PIRQC#
ACCEL_INT
WIFI_RST#
DGPU_PWR_EN#
TP608 TPAD14-OP-GP TP608 TPAD14-OP-GP
3D3V_S0
INT_PIRQB#
R1525
R1525
10KR2J-L-GP
10KR2J-L-GP
MCP_GPIO90 20
INT_SERIRQ 20,24,88
SATA_LED# 19,63
eDP_BLCTRL_CPU 52,55
eDP_BLEN_CPU 52
eDP_VDDEN_CPU 52
WIFI_RST# 58
1
ACCEL_INT 67
DGPU_PWR_EN# 83
DGPU_PWROK 24,73,82,83
GPU_EVENT# 76
INT_PIRQD# 20
EC_SCI# 20,24
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
PCH_PME#
1 2
9 OF 19
9 OF 19
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
B9
C9
D9
D11
C5
B6
B5
A6
C8
A8
D6
C6
U6
N4
N2
AD4
U7
R5
CPU1I
CPU1I
B8
A9
P4
L1
L3
L4
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA#/GPIO77
PIRQB#/GPIO78
PIRQC#/GPIO79
PIRQD#/GPIO80
PME#
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
eDP SIDEBAND
eDP SIDEBAND
PCIE
PCIE
BROADWELL
BROADWELL
DISPLAY
DISPLAY
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
3D3V_S0
4
1
2 3
eDP_HPD_CPU
RN1506
RN1506
SRN2K2J-5-GP
SRN2K2J-5-GP
HDMI_CLK_CPU 54
HDMI_DATA_CPU 54
HDMI_DET_CPU 54
BROADWELL-1-GP
BROADWELL-1-GP
DY_LVDS
DY_LVDS
R1521
eDP_HPD_CPU
For Colay
A A
5
4
R1521
0R2J-2-G P
0R2J-2-GP
1 2
1 2
eDP
eDP
R1522 0R2J-2-GP
R1522 0R2J-2-GP
eDP_HPD_CPU_T 55
eDP_HPD_CPU_C 52
3
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
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Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU(EDP SIDEBAND/GPIO/DDI)
CPU(EDP SIDEBAND/GPIO/DDI)
CPU(EDP SIDEBAND/GPIO/DDI)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
15 102
15 102
15 102
1
1
1
1
5
4
3
2
1
SSID = PCH
D D
LAN
C C
WLAN
Cardreader
PCIE_TX_LAN_N3 30
PCIE_TX_LAN_P3 30
PCIE_TX_W LAN_N4 58
PCIE_TX_W LAN_P4 58
PCIE_TX_CARD_N1 63
PCIE_TX_CARD_P1 63
dGPU
PCIE_RX_CPU_N3 30
PCIE_RX_CPU_P3 30
PCIE_RX_CPU_N4 58
PCIE_RX_CPU_P4 58
PCIE_RX_CPU_N1 63
PCIE_RX_CPU_P1 63
PCIE_RXN[5..8] 73
PCIE_RXP[5..8] 73
PCIE_TXP[5..8] 73
PCIE_TXN[5..8] 73
PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5 PCIE_TXP5_C
PCIE_RXN6
PCIE_RXP6
PCIE_TXN6
PCIE_TXP6 PCIE_TXP6_C
PCIE_RXN7
PCIE_RXP7
PCIE_TXN7
PCIE_TXP7 PCIE_TXP7_C
PCIE_RXN8
PCIE_RXP8
PCIE_TXN8
PCIE_TXP8 PCIE_TXP8_C
1D05V_VCCUSB3PLL_S0
C1605 SCD22U10V2KX-L1-GP
C1605 SCD22U10V2KX-L1-GP
1 2
PX
PX
C1606 SCD22U10V2KX-L1-GP
C1606 SCD22U10V2KX-L1-GP
1 2
PX
PX
C1607 SCD22U10V2KX-L1-GP
C1607 SCD22U10V2KX-L1-GP
1 2
PX
PX
C1608 SCD22U10V2KX-L1-GP
C1608 SCD22U10V2KX-L1-GP
1 2
PX
PX
C1613 SCD22U10V2KX-L1-GP
C1613 SCD22U10V2KX-L1-GP
1 2
PX
PX
C1614 SCD22U10V2KX-L1-GP
C1614 SCD22U10V2KX-L1-GP
1 2
PX
PX
C1615 SCD22U10V2KX-L1-GP
C1615 SCD22U10V2KX-L1-GP
1 2
PX
PX
C1616 SCD22U10V2KX-L1-GP
C1616 SCD22U10V2KX-L1-GP
1 2
PX
PX
C1619 SCD1U16V2KX-L-GP C1619 SCD1U16V2KX-L-GP
1 2
C1620 SCD1U16V2KX-L-GP C1620 SCD1U16V2KX-L-GP
1 2
C1621 SCD1U16V2KX-L-GP C1621 SCD1U16V2KX-L-GP
1 2
C1622 SCD1U16V2KX-L-GP C1622 SCD1U16V2KX-L-GP
1 2
C1623 SCD1U16V2KX-L-GP C1623 SCD1U16V2KX-L-GP
1 2
C1624 SCD1U16V2KX-L-GP C1624 SCD1U16V2KX-L-GP
1 2
3K01R2F-3-GP
3K01R2F-3-GP
R1601
R1601
1 2
PCIE_TXN5_C
PCIE_TXN6_C
PCIE_TXN7_C
PCIE_TXN8_C
PCIE_TX_CPU_N3
PCIE_TX_CPU_P3
PCIE_TX_CPU_N4
PCIE_TX_CPU_P4
PCIE_TX_CPU_N1
PCIE_TX_CPU_P1
PCIE_COMP
C23
C22
H10
G10
C21
G11
C29
G13
G17
C30
C31
G15
F10
E10
B23
A23
B21
B22
A21
F11
B30
F13
B29
A29
F17
F15
B31
A31
E15
E13
A27
B27
CPU1K
CPU1K
F8
E8
E6
F6
PERN5_L0
PERP5_L0
PETN5_L0
PETP5_L0
PERN5_L1
PERP5_L1
PETN5_L1
PETP5_L1
PERN5_L2
PERP5_L2
PETN5_L2
PETP5_L2
PERN5_L3
PERP5_L3
PETN5_L3
PETP5_L3
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
RSVD#E15
RSVD#E13
PCIE_RCOMP
PCIE_IREF
BROADWELL
BROADWELL
PCIE USB
PCIE USB
11 OF 19
11 OF 19
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS#
USBRBIAS
RSVD#AN10
RSVD#AM10
OC0#/GPIO40
OC1#/GPIO41
OC2#/GPIO42
OC3#/GPIO43
AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USB_RBIAS
USB_OC#
USB_CPU_PN0 35
USB_CPU_PP0 35
USB_CPU_PN1 34
USB_CPU_PP1 34
USB_CPU_PN2 63
USB_CPU_PP2 63
USB_CPU_PN3 58
USB_CPU_PP3 58
USB_CPU_PN6 52
USB_CPU_PP6 52
USB_CPU_PN7 91
USB_CPU_PP7 91
USB30_RX_CPU_N1 34
USB30_RX_CPU_P1 34
USB30_TX_CPU_N1 34
USB30_TX_CPU_P1 34
USB30_RX_CPU_N2 34
USB30_RX_CPU_P2 34
USB30_TX_CPU_N2 34
USB30_TX_CPU_P2 34
22D6R2F-L1-GP
22D6R2F-L1-GP
R1611
R1611
1 2
1 2
R1602
R1602
10KR2J-L-GP
10KR2J-L-GP
USB Table
Pair
USB3.0 (CHG)
USB3.0
Layout Note:
1. USB_COMP using 50 ohm single-ended impedance
2. Isolation Spacing :15mil
3. Total trace length<500mil
3D3V_SUS
0
USB3.0 Port 1(CHG)
1
USB3.0 Port 2
2
USB2.0 Port 1(IO BD)
3
WLAN(Bluetooth)
4
N/A
5
N/A(Touch screen)
6
CCD
7
Sensor Hub
Device
B B
A A
5
Layout Note:
1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil
2. Isolation Spacing: 12mil
3. Total trace length<500mil
4
BROADW ELL-1-GP
BROADW ELL-1-GP
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
CPU (PCI/USB)
CPU (PCI/USB)
CPU (PCI/USB)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
16 102
16 102
16 102
1
1
1
1
SSID = CPU
5
4
3
2
1
DSWODVREN - On Die DSW VR Enable
HIGH Enabled (DEFAULT)
LOW Disabled
D D
1 2
DSWODVREN
3D3V_S0
R1740
R1740
10KR2J-L-GP
10KR2J-L-GP
3D3V_S5
PM_SYSRST#_R
XDP_DBRESET# 96
S0_PWR_GOOD 24,96
PCH_PW ROK 36,96
PLT_RST# 24,30,36,58,63,65,76,88,96
PM_SUSW ARN# 24
PM_PWRBTN# 24,96
AC_PRESENT 24
RN1703
RN1703
1
2 3
SRN10KJ-L- G P
SRN10KJ-L-GP
4
PCIE_WAKE#
AC_PRESENT
20141103 SE - Ita
PM_SUSW ARN#
R1739 0R0402-PAD-1-GP R1739 0R0402-PAD-1-GP
R1724 0R0402-PAD-1-GP R1724 0R0402-PAD-1-GP
R1729 0R0402-PAD-1-GP R1729 0R0402-PAD-1-GP
20141012 SC - Terry
PM_SUSACK# 24
DY_Non DS3
DY_Non DS3
1 2
1 2
1 2
1 2
PM_RSMRST# 24
PM_SLP_WLAN# 24
PCH_PW ROK
R1738
R1738
0R2J-L-GP
0R2J-L-GP
1 2
DY
DY
R1721
R1721
1KR2J-1-GP
1KR2J-1-GP
PM_SUSACK#
PM_SYSRST#_R
SYS_PWROK_R
PCH_PW ROK_R
PM_RSMRST#
BATLOW #
3D3V_S0
CPU1H
CPU1H
AK2
SUSACK#
AC3
SYS_RESET#
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST#
AW6
RSMRST#
AV4
SUSWARN#/SUSPWRDNACK/GPIO30
AL7
PWRBTN#
AJ8
ACPRESENT/GPIO31
AN4
BATLOW#/GPIO72
AF3
SLP_S0#
AM5
SLP_WLAN#/GPIO29
BROADW ELL-1-GP
BROADW ELL-1-GP
SYSTEM POWER MANAGEMENT
SYSTEM POWER MANAGEMENT
BROADWELL
BROADWELL
8 OF 19
8 OF 19
DSWVRMEN
DPWROK
WAKE#
CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
SLP_LAN#
AW7
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7
DSWODVREN
PCH_DPW ROK
PM_SUS_STAT#
PCH_DPW ROK
DY_Non DS3
DY_Non DS3
R1710
R1710
0R2J-L-GP
0R2J-L-GP
1 2
1
DS3
DS3
AFTP1701
AFTP1701
AFTE14P-GP
AFTE14P-GP
1 2
1 2
C C
1 2
PM_RSMRST#
20141103 SE - Ita
1 2
R1732
R1732
100KR2J-1-GP
100KR2J-1-GP
DY
DY
R1741
R1741
0R0402-PAD-1-GP
0R0402-PAD-1-GP
3D3V_RTC_AUX
R1717 330KR2J-L-GP R1717 330KR2J-L-GP
R1718 330KR2J-L-GP
R1718 330KR2J-L-GP
PCIE_WAKE# 24,30,58,63
PM_CLKRUN#_EC 24
SUS_CLK_CPU 24,58
PM_SLP_S4# 24,49
PM_SLP_S3# 24,26,31,36,48,51
PM_SLP_SUS# 24,38,48
DPWROK_R 24
20141022 SC - Terry
B B
3D3V_S5
R1742 10KR2J-L-GP R1742 10KR2J-L-GP
R1720 8K2R2J-3-GP R1720 8K2R2J-3-GP
20141012 SC - Terry
1 2
1 2
PM_PWRBTN#
BATLOW #
3D3V_AUX_S5
R1716
R1716
DS3
DS3
10KR2J-L-GP
10KR2J-L-GP
1 2
3V_5V_POK_#
DY_Non D S3
DY_Non DS3
R1709 100KR2J-4-GP
R1709 100KR2J-4-GP
1 2
Q1701
Q1701
3 4
2
5
1
6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 75.00601.07C
2nd = 75.00601.07C
3rd = 84.DM601.03F
3rd = 84.DM601.03F
20141124 SE - Ita
PM_RSMRST#_3
3V_5V_POK_C
R1712 1KR2J-L2-GP
R1712 1KR2J-L2-GP
R1730 0R2J-L-GP
R1730 0R2J-L-GP
1 2
DS3
DS3
1 2
DY_Non DS3
DY_Non DS3
1 2
R1722 0R0402-PAD-1-GP R1722 0R0402-PAD-1-GP
20141103 SE - Ita
PM_SLP_SUS#
PM_RSMRST# 24
3V_5V_POK 45
PM_SUSW ARN#
20141012 SC - Terry
PM_CLKRUN#_EC
PM_SUS_STAT#
20141012 SC - Terry
R1702
R1702
10KR2J-L-GP
10KR2J-L-GP
R1719
R1719
8K2R2J- 3 -GP
8K2R2J-3-GP
1 2
R1736
R1736
10KR2J-L-GP
10KR2J-L-GP
1 2
3D3V_SUS
1 2
3D3V_S0
3D3V_SUS
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
A A
5
4
3
2
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (DMI/FDI/PM)
CPU (DMI/FDI/PM)
CPU (DMI/FDI/PM)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
17 102
17 102
17 102
1
1
1
1
5
SSID = CPU
3D3V_S0
RN1808
RN1808
1
8
2
7
3
6
D D
4 5
SRN10KJ-6-G P
SRN10KJ-6-GP
RN1812
RN1812
2 3
1
SRN10KJ-L-GP
SRN10KJ-L-GP
4
Cardreader
LAN
WLAN
C C
B B
A A
GPU PEG BUS
LPC_AD_CPU_P0 24,65,88
LPC_AD_CPU_P1 24,65,88
LPC_AD_CPU_P2 24,65,88
LPC_AD_CPU_P3 24,65,88
LPC_FRAME#_CPU 24,65,88
SPI_CLK_CPU 25
SPI_CS_CPU_N0 25
SPI_SI_CPU 25
SPI_SO_CPU 25
SPI_WP_CPU 25
SPI_HOLD_CPU 25
Close to CPU
CLKREQ_SSD#
CARD_CLKREQ_CPU#
CK_REQ
WLAN_CLKREQ_CPU#
PEG_CLKREQ#
CARD_CLK_CPU# 63
CARD_CLK_CPU 63
CARD_CLKREQ_CPU# 63
LAN_CLK_CPU# 30
LAN_CLK_CPU 30
LAN_CLKREQ_CPU# 20,30
WLAN_CLK_CPU# 58
WLAN_CLK_CPU 58
WLAN_CLKREQ_CPU# 58
CLK_PCIE_VGA# 73
CLK_PCIE_VGA 73
PEG_CLKREQ# 73
20141107 SD - Ita
5
20141107 SD - Ita
H_RCIN# 20,24
20141107 SD - Ita
CK_REQ
CLKREQ_SSD#
CPU1G
CPU1G
AU14
LAD0
AW12
LAD1
AY12
LAD2
AW11
LAD3
AV12
LFRAME#
AA3
SPI_CLK
Y7
SPI_CS0#
Y4
SPI_CS1#
AC2
SPI_CS2#
AA2
SPI_MOSI
AA4
SPI_MISO
Y6
SPI_IO2
AF1
SPI_IO3
BROADW ELL-1-GP
BROADW ELL-1-GP
LPC
LPC
4
CPU1F
CPU1F
C43
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
U2
PCIECLKRQ0#/GPIO18
B41
CLKOUT_PCIE_N1
A41
CLKOUT_PCIE_P1
Y5
PCIECLKRQ1#/GPIO19
C41
CLKOUT_PCIE_N2
B42
CLKOUT_PCIE_P2
AD1
PCIECLKRQ2#/GPIO20
B38
CLKOUT_PCIE_N3
C37
CLKOUT_PCIE_P3
N1
PCIECLKRQ3#/GPIO21
A39
CLKOUT_PCIE_N4
B39
CLKOUT_PCIE_P4
U5
PCIECLKRQ4#/GPIO22
B37
CLKOUT_PCIE_N5
A37
CLKOUT_PCIE_P5
T2
PCIECLKRQ5#/GPIO23
BROADW ELL-1-GP
BROADW ELL-1-GP
BROADWELL
BROADWELL
SMBUS
SMBUS
SML1ALERT#/PCHHOT#/GPIO73
C-LINK SPI
C-LINK SPI
4
7 OF 19
7 OF 19
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST#
BROADWELL
BROADWELL
CLOCK
CLOCK
SIGNALS
SIGNALS
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
AF2
AD2
AF4
DIFFCLK_BIASREF
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
MCP_GPIO11
SMB_CLK_CPU
SMB_DATA_CPU
MCP_GPIO60
SML0_CLK_CPU
SML0_DATA_CPU
MCP_GPIO73
PCH_KBC_CLK
PCH_KBC_DATA
3
6 OF 19
6 OF 19
CPU_XTAL_24M_IN
A25
XTAL24_IN
XTAL24_OUT
RSVD#K21
RSVD#M21
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CPU_XTAL_24M_OUT
B25
K21
M21
DIFFCLK_BIAS
C26
CLK_BUF_CKSSCD_N
C35
CLK_BUF_CKSSCD_P
C34
CLK_BUF_DOT96_P
AK8
CLK_BUF_DOT96_N
AL8
CLK_PCI_LPC_R
AN15
CLK_PCI_TPM_R
AP15
B35
A35
CLK_PCI_LPC
CLK_PCI_KBC
CLK_PCI_TPM
20150130 MV-1 Ita
SMB_DATA 12,13,62,96
SMB_CLK 12,13,62,96
3
LBAV99LT1G-1-GP
LBAV99LT1G-1-GP
75.00099.O7D
75.00099.O7D
3
LBAV99LT1G-1-GP
LBAV99LT1G-1-GP
75.00099.O7D
75.00099.O7D
DIMM1 / DIMM2 / Touchpad / XDP
MCP_GPIO73 20
PCH_KBC_CLK 24,26,76
PCH_KBC_DATA 24,26,76
CL_CLK1 58
CL_DATA1 58
CL_RST#1 58
MCP_GPIO13 20
MCP_GPIO8 20
3
CPU_XTAL_24M_IN
R1807
R1807
1MR2J-L3-GP
1MR2J-L3-GP
CPU_XTAL_24M_OUT
3K01R2F-3-GP
3K01R2F-3-GP
R1801
R1801
PCIE_CLK_XDP_N 96
PCIE_CLK_XDP_P 96
FC1801 SC4D7P50V2BN-GP
FC1801 SC4D7P50V2BN-GP
FC1802 SC4D7P50V2BN-GP
FC1802 SC4D7P50V2BN-GP
FC1803 SC4D7P50V2BN-GP
FC1803 SC4D7P50V2BN-GP
3D3V_S0
ED1801
ED1801
2
1
3D3V_S0
ED1802
ED1802
2
1
1D05V_VCCACLKPLL_S0
1 2
DY
DY
1 2
DY
DY
1 2
DY
DY
1 2
1 2
1 2
1 2
EC / Thermal / GPU
EDP to LVDS / Sensor
MCP_GPIO60
MCP_GPIO11
MCP_GPIO8
2
1 2
22R2J-2-GP
22R2J-2-GP
R1804
R1804
22R2J-2-GP
22R2J-2-GP
R1802
R1802
R1803
R1803
22R2J-2-GP
22R2J-2-GP
RN1804
RN1804
8
7
6
SRN10KJ-6-GP
SRN10KJ-6-GP
2
2 3
SMB_DATA_CPU
SMB_CLK_CPU
3D3V_SUS
1
2
3
4 5
1
C1808
C1808
SC15P50V2JN-L-GP
SC15P50V2JN-L-GP
1 2
X1801
X1801
4 1
XTAL-24MHZ-81-GP
XTAL-24MHZ-81-GP
82.30004.841
82.30004.841
CLK_PCI_LPC 65
CLK_PCI_KBC 24
CLK_PCI_TPM 88
3D3V_S0
RN1807
RN1807
1
2 3
SRN2K2J-5-GP
SRN2K2J-5-GP
Q1801
Q1801
6
5
2 N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 75.00601.07C
2nd = 75.00601.07C
SMB_CLK_CPU
SMB_DATA_CPU
SML0_DATA_CPU
SML0_CLK_CPU
PCH_KBC_CLK
PCH_KBC_DATA
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (PCI-E/SMBUS/CLOCK/CL)
CPU (PCI-E/SMBUS/CLOCK/CL)
CPU (PCI-E/SMBUS/CLOCK/CL)
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
1 2
C1807
C1807
SC15P50V2JN-L-GP
SC15P50V2JN-L-GP
RN1810
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P
CLK_BUF_DOT96_P
CLK_BUF_DOT96_N
RN1810
2 3
1
SRN10KJ-L-GP
SRN10KJ-L-GP
RN1811
RN1811
1
2 3
SRN10KJ-L-GP
SRN10KJ-L-GP
Need very close to CPU
4
1
2
3 4
RN1803
RN1803
4
SRN2K2J-5-GP
SRN2K2J-5-GP
RN1805
RN1805
4
SRN2K2J-5-GP
SRN2K2J-5-GP
RN1806
RN1806
4
SRN2K2J-5-GP
SRN2K2J-5-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
SMB_DATA 12,13,62,96
SMB_CLK 12,13,62,96
1
2 3
1
2 3
1
2 3
18 102
18 102
18 102
1
4
4
3D3V_SUS
1
1
1
5
4
3
2
1
SSID = CPU
3D3V_RTC_AUX
R1928 20KR2F-L3-GP R1928 20KR2F-L3-GP
1 2
R1927 20KR2F-L3-GP R1927 20KR2F-L3-GP
1 2
D D
1 2
C C
20141203 SE - Ita
Flash Descriptor Security Overide
HDA_SDOUT
3D3V_SUS
Low = Default
High = Enable
1 2
DY
DY
R1902
R1902
1KR2J-L2-GP
1KR2J-L2-GP
20141203 SE - Ita
2 1
C1904
C1904
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
HDA_SDOUT_CPU
1 2
C1903
C1903
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
RTC Reset
G1901
G1901
GAP-OPEN
GAP-OPEN
HDA_BITCLK_CODEC 27
HDA_RST#_CODEC 27
HDA_SDIN0_CPU 27
HDA_SDOUT_CODEC 27
HDA_BITCLK_CODEC
3D3V_RTC_AUX
ME_UNLOCK 24
INTVRMEN- Integrated SUS
1.05V VRM Enable
High - Enable internal VRs
Low - Enable external VRs
R1904 1M1R2J-GP R1904 1M1R2J-GP
R1905 330KR2F-L-GP R1905 330KR2F-L-GP
R1908 1KR2J-L2-GP R1908 1KR2J-L2-GP
R1923 33R2J-L1-GP R1923 33R2J-L1-GP
FC1901 SC4D7P50V2BN-GP
FC1901 SC4D7P50V2BN-GP
1 2
1 2
RN1902
RN1902
SRN33J-5-GP-U
SRN33J-5-GP-U
1
2 3
XDP_TRST# 4,96
PCH_JTAG_TCK 96
PCH_JTAG_TDI 96
PCH_JTAG_TDO 96
PCH_JTAG_TMS 96
PCH_JTAGX 96
1 2
4
1 2
1 2
DY
DY
CPU_XTAL_32K_X1
CPU_XTAL_32K_X2
SM_INTRUDER#
PCH_INTVRMEN
SRTC_RST#
RTC_RST#
HDA_BITCLK_CPU
HDA_SYNC_CPU
HDA_RST#_CPU
HDA_SDOUT_CPU
CPU1E
CPU1E
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER#
AV7
INTVRMEN
AV6
SRTCRST#
AU7
RTCRST#
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST#/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN#/I2S1_TXD
AV10
HDA_DOCK_RST#/I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST#
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD#AL11
AC4
RSVD#AC4
AE63
JTAGX
AV2
RSVD#AV2
BROADW ELL-1-GP
BROADW ELL-1-GP
BROADWELL
BROADWELL
RTC
RTC
AUDIO SATA
AUDIO SATA
JTAG
JTAG
5 OF 19
5 OF 19
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_IREF
RSVD#L11
RSVD#K10
SATA_RCOMP
SATALED#
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
A12
L11
K10
C12
U3
20141012 SC - Terry
SATA0GP_GPIO34
SATA3GP_GPIO35
SATA3GP_GPIO36
SATA_RCOMP
SATA_RX_CPU_N0 56
SATA_RX_CPU_P0 56
SATA_TX_CPU_N0 56
SATA_TX_CPU_P0 56
SATA_RX_CPU_N1 60
SATA_RX_CPU_P1 60
SATA_TX_CPU_N1 60
SATA_TX_CPU_P1 60
NMI_SMI_DBG# 20,24
3K01R2F-3-GP
3K01R2F-3-GP
R1926
R1926
SATA_LED# 15,63
1 2
20141012 SC - Terry
SATA3GP_GPIO35
SATA0GP_GPIO34
HDD
M2 SATA SSD
1D05V_VCCSATA3PLL_S0
RN1901
RN1901
1
4
2 3
SRN10KJ-L-GP
SRN10KJ-L-GP
3D3V_S0
B B
1 2
R1901 10MR2J-L-GP R1901 10MR2J-L-GP
X1901
X1901
1 2
C1901
C1901
SC4P50V2CN-GP
SC4P50V2CN-GP
2 3
XTAL-32D768KHZ-67-GP
XTAL-32D768KHZ-67-GP
82.30001.G11
82.30001.G11
20141028_2 SC - Ita
A A
5
4 1
CPU_XTAL_32K_X1
CPU_XTAL_32K_X2
12
C1902
C1902
SC4P50V2CN-GP
SC4P50V2CN-GP
R1929
R1929
10KR2J- L -GP
10KR2J-L-GP
1 2
R1938
SATA3GP_GPIO36
R1938
0R0402-PAD-1-GP
0R0402-PAD-1-GP
20141103 SE - Ita
Q1901
Q1901
RTCRST_ON 24
R1910
R1910
33R2J-L1-GP
33R2J-L1-GP
4
R1906
R1906
100KR2F-L3-GP
100KR2F-L3-GP
1 2
1 2
R1909
R1909
2KR2F-L1-GP
2KR2F-L1-GP
HDA_SYNC_R HDA_SYNC_CPU
1 2
3
5
6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 75.00601.07C
2nd = 75.00601.07C
RTC_RST# RTC_RST#_S
3 4
2
1
3D3V_S0
1 2
5V_S0
HDA_SYNC_CODEC 27
mSATA_DET# 60
2
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (RTC/LPC/SATA/HDA)
CPU (RTC/LPC/SATA/HDA)
CPU (RTC/LPC/SATA/HDA)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
19 102
19 102
19 102
1
1
1
1
5
4
3
2
1
SSID = CPU
RN2006
3D3V_SUS
RN2004
RN2004
SRN10KJ-L-GP
SRN10KJ-L-GP
1
4
2 3
RN2005
3D3V_S5
RN2005
SRN10KJ-6-GP
SRN10KJ-6-GP
1
2
3
4 5
10KR2J-L-GP
10KR2J-L-GP
R2058
R2058
1 2
8K2R2F- 1-GP
8K2R2F-1-GP
R2001
R2001
10KR2J-L-GP
10KR2J-L-GP
R2062
R2062
1 2
10KR2J-L-GP
10KR2J-L-GP
R2063
R2063
1 2
RN2010
RN2010
SRN10KJ-6-GP
SRN10KJ-6-GP
1
2
3
4 5
DY
DY
R2030
R2030
10KR2J-L-GP
10KR2J-L-GP
1 2
R2003
R2003
10KR2J-L-GP
10KR2J-L-GP
1 2
R2059
R2059
10KR2J-L-GP
10KR2J-L-GP
1 2
R2061
R2061
10KR2J-L-GP
10KR2J-L-GP
1 2
R2038
R2038
1KR2J-L2-GP
1KR2J-L2-GP
R2060
R2060
10KR2J-L-GP
10KR2J-L-GP
1 2
D D
C C
3D3V_S0
3D3V_S0
B B
MCP_GPIO45
MCP_GPIO10
8
ROTATION_LOCK
7
MCP_GPIO14
6
PCH_TS_INT#
MCP_GPIO24
MCP_GPIO15
1 2
DY
DY
WIFI_RF_KILL_SLATEMODE#
PCH_BT_RF_KILL_N
MCP_GPIO27
8
LANLINK_STATUS
7
MCP_GPIO25
6
HOME_BTN_R
MCP_GPIO76
KBL_DET#
LAN_DIS#
DY
DY
1 2
WIFI_RF_KILL_SLATEMODE# 58
PCH_BT_RF_KILL_N 58
HDA_SPKR
DGPU_HOLD_RST#
No Reboot Strap
Low = Default
High = No Reboot
MCP_GPIO46
1 2
3D3V_SUS
HDA_SPKR
R2004
R2004
10KR2J-L-GP
10KR2J-L-GP
MCP_GPIO73 18
HOME_BTN# 24,61
PCH_TS_INT# 52
LAN_CLKREQ_CPU# 18,30
NMI_SMI_DBG# 19,24
EC_SCI# 15,24
10 OF 19
CPU1J
CPU1J
BROADWELL
BROADWELL
MCP_GPIO8 18
LANLINK_STATUS 31
KBL_DET# 62
THERM_SCI# 26
TP2002 TPAD14-OP-GP TP2002 TPAD14-OP-GP
TP2003 TPAD14-OP-GP TP2003 TPAD14-OP-GP
R2022 0R2J-L-GP
R2022 0R2J-L-GP
1 2
DGPU_HOLD_RST# 76
HDD_HALTLED 63
DY
DY
MCP_GPIO13 18
20150205 MV-1 Ita
R2014
HDD_DEVSLP0 60
HDA_SPKR 27
WLAN_WIFI_PW REN 58
3D3V_S0
0R0402-PAD
0R0402-PAD
R2021
R2021
100KR2J-4-GP
100KR2J-4-GP
1 2
R2014
R2020
R2020
100KR2J-4-GP
100KR2J-4-GP
1 2
MCP_GPIO76
LANLINK_STATUS
MCP_GPIO15
KBL_DET#
MCP_GPIO24
MCP_GPIO27
MCP_GPIO26
ROTATION_LOCK
1
RTC_DET#
1
HOME_BTN_R
DGPU_PRSNT#
UMA_DIS#
HSIOPC
MCP_GPIO13
MCP_GPIO14
MCP_GPIO25
MCP_GPIO45
MCP_GPIO46
MCP_GPIO10
LAN_DIS#
MCP_GPIO70
HDD_DEVSLP0_R
1 2
SSD_PW REN
R2015
R2015
0R2J-L-G P
0R2J-L-GP
1 2
SSD_PW REN
DY
DY
MCP_GPIO70
P1
BMBUSY#/GPIO76
AU2
GPIO8
AM7
LAN_PHY_PWR_CTRL/GPIO12
AD6
GPIO15
Y1
GPIO16
T3
GPIO17
AD5
GPIO24
AN5
GPIO27
AD7
GPIO28
AN3
GPIO26
AG6
GPIO56
AP1
GPIO57
AL4
GPIO58
AT5
GPIO59
AK4
GPIO44
AB6
GPIO47
U4
GPIO48
Y3
GPIO49
P3
GPIO50
Y2
HSIOPC/GPIO71
AT3
GPIO13
AH4
GPIO14
AM4
GPIO25
AG5
GPIO45
AG3
GPIO46
AM3
GPIO9
AM2
GPIO10
P2
DEVSLP0/GPIO33
C4
SDIO_POWER_EN/GPIO70
L2
DEVSLP1/GPIO38
N5
DEVSLP2/GPIO39
V2
SPKR/GPIO81
BROADW ELL-1-GP
BROADW ELL-1-GP
MCP_GPIO86
PU
PD
CPU/
CPU/
MISC
MISC
GPIO
GPIO
SERIAL IO
SERIAL IO
R2040
R2040
1KR2J-L2-GP
1KR2J-L2-GP
1 2
GSPI0_MOSI_BBS0_R(SSD_PWR)
RESERVED
SPI BUS
GSPI0_CS#/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS#/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS#/GPIO93
UART0_CTS#/GPIO94
UART1_RXD/GPIO0
UART1_RST#/GPIO2
UART1_CTS#/GPIO3
10 OF 19
THERMTRIP#
RCIN#/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD#AF20
RSVD#AB21
UART1_TXD/GPIO1
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
PCH_THERMTRIP_R
D60
V4
T4
OPI_COMP2
AW15
AF20
AB21
MCP_GPIO83
R6
MCP_GPIO84
L6
N6
MCP_GPIO86
L8
TS_RESET#
R7
MCP_GPIO88
L5
N7
MCP_GPIO90
K2
MCP_GPIO91
J1
MCP_GPIO92
K3
MCP_GPIO93
J2
MCP_GPIO94
G1
UART1_RXD
K4
UART1_TXD
G2
UART1_RTS#
J3
MCP_GPIO3
J4
I2C0_DATA_CPU
F2
I2C0_CLK_CPU
F3
G4
F1
E3
F4
D3
E4
C3
E2
20150205 MV-1 Ita
R2039 0R0402-PAD R2039 0R0402-PAD
1 2
TS_RESET# 52
TS_PWREN 52
MCP_GPIO90 15
1
TP2004 TPAD14-OP-GP TP2004 TPAD14-OP-GP
I2C1_DATA_CPU 52
I2C1_CLK_CPU 52
GC6_FB_EN_PCH 76
H_THERMTRIP# 36
H_RCIN# 18,24
INT_SERIRQ 15,24,88
INT_PIRQD# 15
MCP_GPIO84
TS_RESET#
TS_PWREN
MCP_GPIO88
HDD_DEVSLP0_R
OPI_COMP2
MCP_GPIO83
UART1_RXD
UART1_TXD
UART1_RTS#
MCP_GPIO3
MCP_GPIO93
MCP_GPIO94
MCP_GPIO92
MCP_GPIO91
I2C0_CLK_CPU
I2C0_DATA_CPU
I2C1_DATA_CPU
I2C1_CLK_CPU MCP_GPIO26
8
7
6
1 2
1 2
1 2
1 2
R2010
R2010
49K9R2F - L-GP
49K9R2F-L-GP
1 2
R2016
R2016
49K9R2F - L-GP
49K9R2F-L-GP
1 2
R2018
R2018
49K9R2F - L-GP
49K9R2F-L-GP
1 2
R2019
R2019
49K9R2F - L-GP
49K9R2F-L-GP
1 2
1
2 3
1
2 3
8
7
6
1
2 3
RN2006
SRN10KJ-6-GP
SRN10KJ-6-GP
R2066
R2066
10KR2J-L-GP
10KR2J-L-GP
R2067
R2067
10KR2J-L-GP
10KR2J-L-GP
R2065
R2065
10KR2J-L-GP
10KR2J-L-GP
R2011
R2011
49D9R2F-GP
49D9R2F-GP
R2041
R2041
1KR2J-L2-GP
1KR2J-L2-GP
RN2012
RN2012
SRN10KJ-L- G P
SRN10KJ-L-GP
DY
DY
RN2009
RN2009
SRN10KJ-L- G P
SRN10KJ-L-GP
RN2008
RN2008
SRN2K2J-4-GP
SRN2K2J-4-GP
RN2011
RN2011
SRN4K7J-8 - G P
SRN4K7J-8-GP
DY
DY
DY
DY
1 2
3D3V_S0
1
2
3
4 5
3D3V_S0
3D3V_S0
4
4
1
2
3
4 5
4
3D3V_S0 3D3V_S0
1 2
R2012
R2012
10KR2J-L-GP
10KR2J-L-GP
A A
5
1 2
R2013
R2013
10KR2J-L-GP
10KR2J-L-GP
UMA
UMA
DGPU_PRSNT# UMA_DIS#
1 2
R2023
R2023
10KR2J-L-GP
10KR2J-L-GP
PX
PX
4
3D3V_S0
1 2
R2017
R2017
100KR2J-4-GP
100KR2J-4-GP
HSIOPC
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
CPU (GPIO/MISC)
CPU (GPIO/MISC)
CPU (GPIO/MISC)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
20 102
20 102
20 102
1
1
1
1
5
4
3
2
1
SSID = CPU
D D
13 OF 19
CPU1M
1D05V_S0
0.041A
1 2
C2101
C2101
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
C C
B B
3D3V_SUS
3D3V_S0
20150205 MV-1 Ita
0R0402-PAD
0R0402-PAD
R2104
R2104
1 2
R2105
R2105
0R2J-2-G P
0R2J-2-GP
1 2
DY
DY
1D05V_VCCCLK_S0
1 2
C2103
C2103
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
C2104
C2104
0.042A
1D05V_MODPHY
1D05V_VCCUSB3PLL_S0
1D05V_VCCSATA3PLL_S0
1D05V_S0
TP2101 TPAD14-OP-GP TP2101 TPAD14-OP-GP
TP2102 TPAD14-OP-GP TP2102 TPAD14-OP-GP
1D05V_VCCACLKPLL_S0
1 2
C2107
C2107
1
1
3D3V_SUS
3D3V_S5
3D3V_S0
1D05V_VCCCLK_S0
3D3V_SUS
1.838A
DCPSUS3
VCCHDA
DCPSUS2
CPU1M
K9
L10
M9
N8
P9
B18
B11
Y20
AA21
W21
J13
AH14
AH13
AC9
AA9
AH10
V8
W9
J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21
BROADW ELL-1-GP
BROADW ELL-1-GP
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD#Y20
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD#K18
RSVD#M20
RSVD#V21
VCCSUS3_3
VCCSUS3_3
HSIO
HSIO
USB3
USB3
HDA
HDA
VRM
VRM
GPIO/LPC
GPIO/LPC
LPT LP POWER
LPT LP POWER
BROADWELL
BROADWELL
RTC
RTC
SPI
OPI
OPI
SPI
CORE
CORE
THERMAL SENSOR
THERMAL SENSOR
SERIAL IO
SERIAL IO
SUS OSCILLATOR
SUS OSCILLATOR
USB2
USB2
13 OF 19
VCCSUS3_3
VCCRTC
DCPRTC
VCCSPI
VCCASW
VCCASW
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP#AG19
DCPSUSBYP#AG20
VCCASW
VCCASW
VCCASW
DCPSUS1#AD10
DCPSUS1#AD8
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD#AC20
VCC1_05
VCC1_05
AH11
AG10
AE7
Y8
AG14
AG13
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16
U8
T9
AB8
AC20
AG16
AG17
3D3V_SUS
3D3V_DCPRTC
3D3V_VCCSPI_S5
1D05V_S0
1D05V_S0
DCPSUSYP
1D05V_S0
DCPSUS1
DCPSUS4
R2102 0R2J-2-GP
R2102 0R2J-2-GP
VCCAPLL_AC20
C2108
C2108
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
C2109
C2109
1 2
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
R2103 0R0402-PAD R2103 0R0402-PAD
1 2
1 2
DY
DY
R2101
R2101
0R2J-2-G P
0R2J-2-GP
1 2
3D3V_S0
1 2
DY
DY
1
20150205 MV-1 Ita
C2110
C2110
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
C2111
C2111
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
1D5V_S0
1D5V_S0
1D5V_S0
TP2103 TPAD14-OP-GP TP2103 TPAD14-OP-GP
3D3V_RTC_AUX
3D3V_S5
12
C2116
C2116
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
1D05V_S0
12
C2105
C2105
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
1 2
C2102
C2102
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
3D3V_S0
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
A A
5
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
CPU (POWER1)
CPU (POWER1)
CPU (POWER1)
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Friday, February 06, 2015
Friday, February 06, 2015
Friday, February 06, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
21 102
21 102
21 102
1
1
1
1
5
4
3
2
1
SSID = CPU
D D
17 OF 19
CPU1Q
CPU1Q
BROADWELL
DC_AY2_AW2
DC_AY3_AW3
DC_AY60
TP2212 TP2212
TP2213 TP2213
C C
1
1
DC_AY61_AW61
DC_AY62_AW62
DC_B2
DC_A3_B3
DC_A61_B61
DC_B62_B63
DC_C1_C2
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
BROADWELL-1-GP
BROADWELL-1-GP
CPU1R
CPU1R
BROADWELL
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
17 OF 19
18 OF 19
18 OF 19
A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
DC_A3_B3
DC_A4
DC_A60
DC_A61_B61
DC_A62
DC_AV1
DC_AW1
DC_AY2_AW2
DC_AY3_AW3
DC_AY61_AW61
DC_AY62_AW62
DC_AW63
1
TP2219 TP2219
1
TP2218 TP2218
1
TP2217 TP2217
1
TP2215 TP2215
1
TP2216 TP2216
1
TP2214 TP2214
BROADWELL
BROADWELL
AT2
RSVD#AT2
AU44
RSVD#AU44
AV44
RSVD#AV44
D15
RSVD#D15
F22
RSVD#F22
B B
A A
5
H22
RSVD#H22
J21
RSVD#J21
BROADWELL-1-GP
BROADWELL-1-GP
4
3
RSVD#N23
RSVD#R23
RSVD#T23
RSVD#U10
RSVD#AL1
RSVD#AM11
RSVD#AP7
RSVD#AU10
RSVD#AU15
RSVD#AW14
RSVD#AY14
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (RSVD)
CPU (RSVD)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (RSVD)
Friday, January 30, 2015
Friday, January 30, 2015
Friday, January 30, 2015
2
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
22 102
22 102
22 102
1
1
1
1
5
4
3
2
1
SSID = CPU
14 OF 19
CPU1N
CPU1N
A11
D D
C C
B B
A A
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
AB22
VSS
AB7
VSS
AC61
VSS
AD21
VSS
AD3
VSS
AD63
VSS
AE10
VSS
AE5
VSS
AE58
VSS
AF11
VSS
AF12
VSS
AF14
VSS
AF15
VSS
AF17
VSS
AF18
VSS
AG1
VSS
AG11
VSS
AG21
VSS
AG23
VSS
AG60
VSS
AG61
VSS
AG62
VSS
AG63
VSS
AH17
VSS
AH19
VSS
AH20
VSS
AH22
VSS
AH24
VSS
AH28
VSS
AH30
VSS
AH32
VSS
AH34
VSS
AH36
VSS
AH38
VSS
AH40
VSS
AH42
VSS
AH44
VSS
AH49
VSS
AH51
VSS
AH53
VSS
AH55
VSS
AH57
VSS
AJ13
VSS
AJ14
VSS
AJ23
VSS
AJ25
VSS
AJ27
VSS
AJ29
VSS
BROADWELL-1-GP
BROADWELL-1-GP
5
BROADWELL
BROADWELL
14 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
CPU1O
CPU1O
BROADWELL
AP22
VSS
AP23
VSS
AP26
VSS
AP29
VSS
AP3
VSS
AP31
VSS
AP38
VSS
AP39
VSS
AP48
VSS
AP52
VSS
AP54
VSS
AP57
VSS
AR11
VSS
AR15
VSS
AR17
VSS
AR23
VSS
AR31
VSS
AR33
VSS
AR39
VSS
AR43
VSS
AR49
VSS
AR5
VSS
AR52
VSS
AT13
VSS
AT35
VSS
AT37
VSS
AT40
VSS
AT42
VSS
AT43
VSS
AT46
VSS
AT49
VSS
AT61
VSS
AT62
VSS
AT63
VSS
AU1
VSS
AU16
VSS
AU18
VSS
AU20
VSS
AU22
VSS
AU24
VSS
AU26
VSS
AU28
VSS
AU30
VSS
AU33
VSS
AU51
VSS
AU53
VSS
AU55
VSS
AU57
VSS
AU59
VSS
AV14
VSS
AV16
VSS
AV20
VSS
AV24
VSS
AV28
VSS
AV33
VSS
AV34
VSS
AV36
VSS
AV39
VSS
AV41
VSS
AV43
VSS
AV46
VSS
AV49
VSS
AV51
VSS
AV55
VSS
BROADWELL-1-GP
BROADWELL-1-GP
4
BROADWELL
15 OF 19
15 OF 19
AV59
VSS
AV8
VSS
AW16
VSS
AW24
VSS
AW33
VSS
AW35
VSS
AW37
VSS
AW4
VSS
AW40
VSS
AW42
VSS
AW44
VSS
AW47
VSS
AW50
VSS
AW51
VSS
AW59
VSS
AW60
VSS
AY11
VSS
AY16
VSS
AY18
VSS
AY22
VSS
AY24
VSS
AY26
VSS
AY30
VSS
AY33
VSS
AY4
VSS
AY51
VSS
AY53
VSS
AY57
VSS
AY59
VSS
AY6
VSS
B20
VSS
B24
VSS
B26
VSS
B28
VSS
B32
VSS
B36
VSS
B4
VSS
B40
VSS
B44
VSS
B48
VSS
B52
VSS
B56
VSS
B60
VSS
C11
VSS
C14
VSS
C18
VSS
C20
VSS
C25
VSS
C27
VSS
C38
VSS
C39
VSS
C57
VSS
D12
VSS
D14
VSS
D18
VSS
D2
VSS
D21
VSS
D23
VSS
D25
VSS
D26
VSS
D27
VSS
D29
VSS
D30
VSS
D31
VSS
3
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
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Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (VSS)
CPU (VSS)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (VSS)
Friday, January 30, 2015
Friday, January 30, 2015
Friday, January 30, 2015
2
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
23 102
23 102
23 102
1
1
1
1
SSID = KBC
SENSOR_HUB_STATUS 91
D D
KSI8 35
3D3V_AUX_KBC
PCH_KBC_DATA 18,26,76
PCH_KBC_CLK 18,26,76
C C
BAT_SDA 43,44
BAT_SCL 43,44
SENSOR_HUB_EN 91
DY
DY
R2407
R2407
10KR2F-2-GP
10KR2F-2-GP
1 2
DY_LVDS
DY_LVDS
R2413
R2413
10KR2F-2-GP
10KR2F-2-GP
1 2
KEYBOARD_DISABLE# 91
LID_SW# 43,52,64
GPIO8_OVERT#_EC
5
CLK_PCI_KBC 18
LPC_FRAME#_CPU 18,65,88
LPC_AD_CPU_P0 18,65,88
LPC_AD_CPU_P1 18,65,88
LPC_AD_CPU_P2 18,65,88
LPC_AD_CPU_P3 18,65,88
INT_SERIRQ 15,20,88
H_RCIN# 18,20
PLT_RST# 17,30,36,58,63,65,76,88,96
EC_SCI# 15,20
PM_CLKRUN#_EC 17
ECRST# 90
KB_BL_LED# 62
EC_CAP_LED 62
DC_BATFULL 42
FAN1_PWM 26
FAN_TACH1 26
CPPWR_EN 35
KSO[17..0] 62
KSI8
KSI8
KSI[7..0] 62
20150205 MV-1 Ita
R2401 0R0402-PAD R2401 0R0402-PAD
1 2
R2409 0R0402-PAD R2409 0R0402-PAD
1 2
SEN_MODE_GPIO0 91
SEN_MODE_GPIO1 91
DGPU_PWROK 15,73,82,83
IMCLK 62
IMDAT 62
AD_DETECT 42
WLAN_PW R_EN# 58
VOL_DN# 63
E51_TXD 58
E51_RXD 58
ME_UNLOCK 19
CHARGE_LED 42
WIFI_RF_EN 58
TP2403 TPAD14-OP-GP TP2403 TPAD14-OP-GP
TP2404 TPAD14-OP-GP TP2404 TPAD14-OP-GP
R2411
R2411
10KR2F-2-GP
10KR2F-2-GP
ECRST#
KSI8
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
BAT_SDA_EC
BAT_SCL_EC
1
1
3D3V_S0
1 2
B B
ENE EDI
KSI4
KSI5
KSI6
KSI7
1
TP2405
TP2405
TPAD14-OP-GP
TPAD14-OP-GP
1
TP2406
TP2406
TPAD14-OP-GP
TPAD14-OP-GP
1
TP2407
TP2407
TPAD14-OP-GP
TPAD14-OP-GP
1
TP2408
TP2408
TPAD14-OP-GP
TPAD14-OP-GP
PLT_RST#
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
EC2401
EC2401
U2401
U2401
12
4
10
8
7
5
3
1
2
13
20
38
37
21
23
25
26
27
28
29
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
55
56
57
58
59
60
61
62
78
77
80
79
83
84
85
86
87
88
17
18
16
19
34
30
31
90
92
95
KB9028Q-C-GP
KB9028Q-C-GP
071.09028.000G
071.09028.000G
12
DY
DY
PCICLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
GA20
KBRST#
PCIRST#
SCI#
CLKRUN#
ECRST#
PWM0
PWM1
PWM2
FANPWM0
FANPWM1
FANFB0
FANFB1
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KBC9028Q
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
SDA0
SCL0
SDA1
SCL1
PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3
GPIO0B
GPIO0C
GPIO0A
GPIO0D
GPIO19
GPIO16
GPIO17
GPIO52
GPIO54
GPIO56
68.00084.921
68.00084.921
L2401
L2401
BLM15AG121SN-1GP
BLM15AG121SN-1GP
1 2
ene 20140326
SUSCLK32_KBC_5E
PLT_RST#
GPXIOD03
EC_AGND
R2425 47KR2J-L2-GP R2425 47KR2J-L2-GP
GPXIOD01
GPXIOD02
GPIO7F
GPIO5A
GPIO5C
GPIO5B
GPIO58
1 2
4
VCC
VCC
VCC
VCC0
VCC
VCC_LPC
AVCC
GND
GND
GND
GND
GND
AGND
VCC_IO2
DA0
DA1
DA2
DA3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GPXIOA00
GPXIOA01
GPXIOA02
GPXIOA03
GPXIOA04
GPXIOA05
GPXIOA06
GPXIOA07
GPXIOA08
GPXIOA09
GPXIOA10
GPXIOA11
GPXIOD00
AC_IN#
EC_EN#
PWRBTN#
GPXIOD04
GPXIOD05
GPIOD06
PECI
GPIO1A
GPIO53
GPIO55
GPIO5D
GPIO5E
GPIO59
GPIO57
GPIO50
GPIO18
GPIO08
GPIO07
GPIO04
SPICS#
MOSI
MISO
SPICLK
100KR2F-L1-GP
100KR2F-L1-GP
R2423
R2423
1 2
DY
DY
1 2
DY
DY
125
22
33
111
96
9
67
11
24
35
94
113
69
124
68
70
71
72
63
PCB_VER_AD
64
ADT_TYPE
65
66
75
MODEL_ID
76
73
74
97
98
99
100
101
102
103
104
105
106
107
108
109
110
112
KBC_PWRBTN#_R
114
115
116
117
H_PECI_R1
118
36
91
93
122
SUSCLK32_KBC_5E
123
127
121
KBC_ECWP#
89
32
PROCHOT_EC
15
14
6
EC_SPI_CS#_C1
128
EC_SPI_DO_C1
120
EC_SPI_DI_C1
119
EC_SPI_CLK_C1
126
C2410
C2410
SC20P50V2JN-1GP
SC20P50V2JN-1GP
RSMRST#_KBC
3D3V_AUX_KBC
1 2
C2407
1 2
R2408
R2408
43R2J-GP
43R2J-GP
1 2
1 2
1 2
1 2
1 2
20150204 MV-1 Ita
KBC_ECWP#
CLK_PCI_KBC
C2407
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
33R2J-2-GP R2418 33R2J-2-GP R2418
33R2J-2-GPR2419 33R2J-2-GPR2419
33R2J-2-GP R2421 33R2J-2-GP R2421
EC_AGND
R2416
R2416
0R0402-PAD
0R0402-PAD
20150204 MV-1 Ita
R2420 0R0402-PAD R2420 0R0402-PAD
C2401
C2401
C2402
C2402
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
12
A_SD# 27,28
LID_EC_CTRL# 52
GPIO8_OVERT#_EC 76
VOL_UP# 63
AD_IA 44
DPWROK_R 17
PCIE_WAKE#_W LAN_EC 58
HOME_BTN# 20,6 1
GPU_PROTECT# 76
PCIE_WAKE# 17,30,58,63
TOUCH_OFF# 35,52
CAM_OFF 52
USB_PWR_EN# 3 4,63
3V_S5_EN 36
PM_PWRBTN# 17,96
AD_OFF 44
NMI_SMI_DBG# 19,20
S0_PWR_GOOD 17,96
RTCRST_ON 19
AC_PRESENT 17
PM_SLP_WLAN# 17
AC_IN# 4 3,44
ALL_SYS_PWRGD 36
PM_SLP_SUS# 17,38,48
PM_SUSWARN# 17
H_PECI 4
MUTE_LED 62
5V_S5_EN 36
PWR_LED 61
PM_SUSACK# 17
SUS_CLK_CPU 17,5 8
CHG_ON# 44
BLUETOOTH_EN 58
TOUCH_RST# 35
PM_SLP_S4# 17,49
PM_SLP_S3# 17,26 ,31,36,48,51
KBC_SPI_CS0#_R 25
KBC_SPI_SI0_R 25
KBC_SPI_SO_R 25
KBC_SPI_CLK_R 25
3D3V_AUX_S5
R2424
R2424
10KR2F-2-GP
10KR2F-2-GP
1 2
83.00355.F1F
83.00355.F1F
FC2401 SC4D7P50V2BN-GP
FC2401 SC4D7P50V2BN-GP
C2403
C2403
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
12
D2401
D2401
1SS355GP-GP
1SS355GP-GP
1 2
C2404
C2404
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
12
A K
3
3D3V_AUX_KBC
C2405
C2405
C2406
C2406
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
12
C2408
C2408
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
12
EC_AGND
3D3V_AUX_KBC_AVCC
12
1 2
C2409
C2409
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
L2402
L2402
BLM15AG121SN-1GP
BLM15AG121SN-1GP
12
20150204 MV-1 Ita
CONFIRM EC THIS PIN PM_PWRBTN# PIN HI OUPUT
S0_PWR_GOOD ==DELAY 99ms
H_PROCHOT# 4,46
KBC_SPI0_WP# 25
DY
DY
For EC power consumption reserver
3D3V_AUX_KBC
3D3V_AUX_KBC
1 2
RSMRST#_KBC
PCB VERSION
PCB_VER_AD
-1
MODEL ID
MODEL_ID
Q2401
Q2401
D
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
G
S
PROCHOT_EC
2
R2402
R2402
1 2
R2403
R2403
0R0402-PAD
0R0402-PAD
R2404
R2404
47KR2J-L2-GP
47KR2J-L2-GP
3D3V_AUX_KBC
R2405
R2405
76K8R2F-GP
76K8R2F-GP
1 2
1 2
R2406
R2406
100KR2F-L1-GP
100KR2F-L1-GP
EC_AGND
3D3V_AUX_KBC
1 2
R2422
R2422
100KR2J-1-GP
100KR2J-1-GP
3D3V_AUX_S5
0R0603-PAD-1-GP-U
0R0603-PAD-1-GP-U
20150205 MV-1 Ita
1 2
1 2
1 2
R2410
R2410
100KR2F-L1-GP
100KR2F-L1-GP
1 2
R2414
R2414
100KR2F-L1-GP
100KR2F-L1-GP
EC_AGND
PM_RSMRST# 17
SE
-1
-2
-3
-4
1
HP Limit Signal Detect
3D3V_AUX_KBC
1
2
D2402
D2402
BAV99T-7F-GP
BAV99T-7F-GP
83.00099.U11
83.00099.U11
3
1 2
LIMIT_SIGNAL
A A
R2430
R2430
1KR2F-3-GP
1KR2F-3-GP
EC_AGND
1 2
R2432
R2432
12K4R2F-GP
12K4R2F-GP
ADT_TYPE
FAN_TACH1
3V_S5_EN
5V_S5_EN
R2427
R2427
10KR2J-3 - GP
10KR2J-3-GP
1 2
1 2
1 2
3D3V_S0
2 1
1 2
R2431
R2431
470R2J-2-GP
470R2J-2-GP
G2401
G2401
GAP-OPEN
GAP-OPEN
3D3V_AUX_KBC
R2429
R2429
10KR2J-3-GP
10KR2J-3-GP
1 2
1 2
C2411
C2411
SC100P50V2JN-L-GP
SC100P50V2JN-L-GP
DY
DY
KBC_PWRBTN# 61,90
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
KBC_NPCE285PA0DX-GP
KBC_NPCE285PA0DX-GP
KBC_NPCE285PA0DX-GP
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
24 102
24 102
24 102
1
1
1
3D3V_AUX_KBC
RN2403
12
C2412
C2412
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
RN2403
4
SRN2K2J-5-GP
SRN2K2J-5-GP
1 2
DY
DY
1
2 3
R2433
R2433
10KR2J-3-GP
10KR2J-3-GP
KBC_PWRBTN#_R
BAT_SCL
BAT_SDA
ECRST#
R2434 10KR2J-3-GP R2 434 10KR2J-3-GP
R2435 10KR2J-3-GP R2 435 10KR2J-3-GP
5
4
3
2
1
SSID = Flash.ROM
SPI FLASH ROM (8M byte) for PCH
SPI ROM Equal length need to less than 500mil
20150213 MV-1 Ita
D D
3D3V_S5 3D3V_S5
1 2
SPI_CS_CPU_N0 18
SPI_SO_CPU 18
C C
SPI_WP_CPU 18
KBC_SPI0_WP# 24
SSID = RBAT
B B
No RTC battery for Macaron
1 2
C2502
C2501
C2501
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
C2502
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
DY
DY
R2506 20R2J-3-GP R2506 20R2J-3-GP
R2505 33R2J-L1-GP R2505 33R2J-L1-GP
R2513 0R2J-2-GP
R2513 0R2J-2-GP
R2514 0R0402-PAD R2514 0R0402-PAD
20150205 MV-1 Ita
3K3R2J-3-GP
3K3R2J-3-GP
1 2
1 2
1 2
DY
DY
1 2
20150130 MV-1 Ita
3D3V_RTC_PWR
12
1 2
R2503
R2502
R2502
R2503
4K7R2J-L-GP
4K7R2J-L-GP
SPI_CS0#
SPI_SO_0
SPI0_WP_0
20150204 MV-1 Ita
1 2
R2518 470R2F-GP R2518 470R2F-GP
BIOS1
BIOS1
1
CS#
2
DO/IO1
3
4
HOLD#/IO3
WP#/IO2
GND
W25Q64FVSSIG-GP
W25Q64FVSSIG-GP
72.25Q64.F01
72.25Q64.F01
2nd = 72.25640.D01
2nd = 72.25640.D01
BATT_RTC
VCC
CLK
DI/IO0
8
7
6
5
3D3V_S5
SPI0_HOLD_0
SPI_CLK_0
SPI_SI_R_0
1 2
R2504
R2504
3K3R2J-3-GP
3K3R2J-3-GP
R2501 33R2J-L1-GP R2501 33R2J-L1-GP
1 2
R2507 33R2J-L1-GP R2507 33R2J-L1-GP
1 2
R2508 33R2J-L1-GP R2508 33R2J-L1-GP
1 2
R2509 0R0402-PAD R2509 0R0402-PAD
1 2
R2512 0R0402-PAD R2512 0R0402-PAD
1 2
R2511 0R0402-PAD R2511 0R0402-PAD
1 2
R2510 0R0402-PAD R2510 0R0402-PAD
1 2
20150205 MV-1 Ita
SPI_HOLD_CPU 18
SPI_CLK_CPU 18
SPI_SI_CPU 18
KBC_SPI_CS0#_R 24
KBC_SPI_CLK_R 24
KBC_SPI_SO_R 24
KBC_SPI_SI0_R 24
3D3V_RTC_AUX
C2503
C2503
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
1 2
DY
DY
Q2501
Q2501
2
3
1
BAS40CW -GP
BAS40CW -GP
83.00040.E81
83.00040.E81
2nd = 83.00040.T81
2nd = 83.00040.T81
3rd = 83.00040.K81
3rd = 83.00040.K81
Width=20mils
3D3V_AUX_S5
3D3V_RTC_VCC
RTC1
RTC1
DY
DY
3
1
2
4
ACES-CON2-20-GP-U
ACES-CON2-20-GP-U
20.F1639.002
20.F1639.002
20150204 MV-1 Ita
D2502
D2502
CH551H-30PT-GP
A A
5
CH551H-30PT-GP
2 1
DY
DY
4
DY
DY
1 2
R2515 1KR2J-L2-GP
R2515 1KR2J-L2-GP
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Flash(KBC+PCH)/RTC
Flash(KBC+PCH)/RTC
Flash(KBC+PCH)/RTC
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Friday, February 13, 2015
Friday, February 13, 2015
Friday, February 13, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
25 102
25 102
25 102
1
1
1
1
5
4
3
2
1
SSID = Thermal
Thermal sensor NCT 7718W
D D
Layout notice :
Both DXN and DXP routing 10 mil
trace width and 10 mil spacing.
Q2601
Q2601
PMBS3904-1-GP
PMBS3904-1-GP
84.03904.L06
84.03904.L06
2nd = 84.03904.E11
2nd = 84.03904.E11
1 2
R2604
R2604
NTC-100K-8-GP
NTC-100K-8-GP
DY
DY
C C
2.System Sensor, Put on palm rest
3
1
2
P2800_DXP
12
C2604
C2604
SC470P50V3JN-2GP
SC470P50V3JN-2GP
DY
DY
P2800_DXN
NCT7718W I2C/ SMBusTM address is 1001100xb (x is R/W bit).
3D3V_S0
R2601
R2601
10R2F-L-GP
10R2F-L-GP
1 2
1 2
C2601
C2601
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
1 2
C2605
C2605
THERM_VDD
SC2K2P50V2KX-L-GP
SC2K2P50V2KX-L-GP
NCT_DATA 55,67
U2601
U2601
1
VDD
2
D+
3
DT_CRIT#4GND
NCT7718W-GP
NCT7718W-GP
74.07718.0B9
74.07718.0B9
SCL
SDA
ALERT#
NCT_CLK
8
NCT_DATA
7
THERM_SCI#
6
5
1.H/W T8 Shutdown
3D3V_S0
1
2 3
RN2601
RN2601
SRN2K2J-5-GP
SRN2K2J-5-GP
4
3D3V_S0
1 2
R2611
R2611
R5
18K7R2F-GP
18K7R2F-GP
PURE_HW _SHUTDOWN#
Q2602
Q2602
1
2
3 4
2N7002KDW-GP
2N7002KDW-GP
3D3V_S0
R7
THERM_SCI# 20
6
5
1 2
R2612
R2612
2KR2F-L1-GP
2KR2F-L1-GP
84.2N702.A3F
84.2N702.A3F
2nd = 75.00601.07C
2nd = 75.00601.07C
FAN1_PW M 24
FAN_TACH1 24
PCH_KBC_CLK 18,24,76 NCT_CLK 55,67
PCH_KBC_DATA 18,24,76
D2602
D2602
CH551H-30PT-GP
CH551H-30PT-GP
2ND = 83.R5003.H8H
2ND = 83.R5003.H8H
*Layout* 15 mil
2 1
D2601
D2601
CH551H-30PT-GP
CH551H-30PT-GP
83.R5003.C8F
83.R5003.C8F
2ND = 83.R5003.H8H
2ND = 83.R5003.H8H
2 1
83.R5003.C8F
83.R5003.C8F
FAN_TACH1_C
5V_S0
5V_S0
FAN_TACH1_C
FAN1_PW M
5V_S0
1 2
C2603
C2603
SC4D7U25V5KX-L2-GP
SC4D7U25V5KX-L2-GP
4
3
2
1
1
1
1
1
1 2
C2602
C2602
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
6
FAN1
FAN1
ACES-CON4-21-GP
ACES-CON4-21-GP
5
AFTP2601 AFTE14P-GP AFTP2601 AFTE14P-GP
AFTP2602 AFTE14P-GP AFTP2602 AFTE14P-GP
AFTP2603 AFTE14P-GP AFTP2603 AFTE14P-GP
AFTP2604 AFTE14P-GP AFTP2604 AFTE14P-GP
98 / 4C
B B
PURE_HW _SHUTDOWN#_R 36
T8=85 degree
PM_SLP_S3# 17,24,31,36,48,51
A A
5
4
PURE_HW _SHUTDOWN#_R
3
D
G
Q2604
Q2604
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
PURE_HW _SHUTDOWN# PM_SLP_S3#
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
G788P81/Fan Controllor P2793
G788P81/Fan Controllor P2793
G788P81/Fan Controllor P2793
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
26 102
26 102
26 102
1
1
1
1
5
AVDD_CODEC
1D5V_S0
1 2
C2702
C2702
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
3D3V_S0
D D
C C
1 2
1 2
C2705
C2705
C2701
C2701
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
3D3V_S0
C2713
C2713
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
Speaker 4 ohm : 40mil
Speaker 8 ohm : 20mil
5V_S0
12
C2706
C2706
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
C2708
C2708
1 2
MIC_L 29
HPA_OUT_L1 28,29
HPA_OUT_R1 28,29
JACK_DET 29
MIC2_JD 29
1 2
1 2
C2709
C2709
SCD1U16V2KX-L-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
SCD1U16V2KX-L-GP
SPKR_L+ 29
SPKR_L- 29
SPKR_R+ 29
SPKR_R- 29
AMP
AMP
1 2
12
AUD_AGND
C2711
C2711
C2710
C2710
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
C2715 SC4D7U6D3V3KX-L-GP C2715 SC4D7U6D3V3KX-L-GP
1 2
C2747 SC4D7U6D3V3KX-L-GP C2747 SC4D7U6D3V3KX-L-GP
1 2
HPA_OUT_L1_R 28
HPA_OUT_R1_R 28
R2714 0R2J-L-GP
R2714 0R2J-L-GP
1 2
R2715 0R2J-L-GP
R2715 0R2J-L-GP
1 2
R2701 39K2R2F-L-GP R2701 39K2R2F-L-GP
1 2
R2720 20KR2F-L3-GP
R2720 20KR2F-L3-GP
1 2
1 2
AUD_AGND
SLATE_MICL
SLATE_MICR
DY_Non AMP
DY_Non AMP
DY_Non AMP
DY_Non AMP
JACK_DET_C
MIC2_JD_C
AUO_BEEP
4
C2703
C2703
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
1 2
C2704
C2704
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
AUDIO CODEC
ALC3227
U2701
U2701
26
AVDD1
40
AVDD2
41
PVDD1
46
PVDD2
1
DVDD
9
DVDD-IO
36
CPVDD
19
MIC1-L/PORT-B-L
20
MIC1-R/PORT-B-R
17
MIC2-L/PORT-F-L
18
MIC2-R/PORT-F-R
22
LINE1-L/PORT-C-L
21
LINE1-R/PORT-C-R
24
LINE2-L/PORT-E-L
23
LINE2-R/PORT-E-R
32
HPOUT-L/PORT-I-L
33
HPOUT-R/PORT-I-R
42
SPK-OUT-L+
43
SPK-OUT-L-
45
SPK-OUT-R+
44
SPK-OUT-R-
13
SENSE_A
14
SENSE_B
12
PCBEEP
16
MONO-OUT
ALC3227-CG-GP
ALC3227-CG-GP
071.03227.0003
071.03227.0003
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
SPDIF-OUT/GPIO2
SDATA-OUT
SDATA-IN
BCLK
SYNC
RESET#
PDB
MIC1-VREFO-L
MIC1-VREFO-R
MIC2-VREFO
LDO1-CAP
LDO2-CAP
LDO3-CAP
CBN
CBP
JDREF
VREF
CPVEE
AVSS1
AVSS2
DVSS
GND
1 2
C2735
C2735
DMIC_DATA_R
2
DMIC_CLK_R
3
HP_COMBO_CGI
48
5
HDA_SDIN0_CODEC
8
6
10
11
A_SD#_R
47
31
30
29
LDO1_C
27
LDO2_C
39
LDO3_C
7
CBN
35
CBP
37
JDREV_C
15
VREF_C
28
CPVEE_C
34
25
38
4
49
3
DMIC_DATA_R
DMIC_CLK_R
1 2
C2736
C2736
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
DY
DY
DY
DY
MUTE_LED_CTRL 62
MIC_VREFO 29
R2712 100KR2F-L1-GP R2712 100KR2F-L1-GP
1 2
C2716 SC10U6D3V3MX-L-GP C2716 SC10U6D3V3MX-L-GP
1 2
C2717 SC10U6D3V3MX-L-GP C2717 SC10U6D3V3MX-L-GP
1 2
C2718 SC10U6D3V3MX-L-GP C2718 SC10U6D3V3MX-L-GP
1 2
C2719 SC2D2U10V3KX-L-GP C2719 SC2D2U10V3KX-L-GP
1 2
R2706 20KR2F-L3-GP R2706 20KR2F-L3-GP
1 2
C2721 SC2D2U10V3KX-L-GP C2721 SC2D2U10V3KX-L-GP
1 2
C2722 SC2D2U10V3KX-L-GP C2722 SC2D2U10V3KX-L-GP
1 2
AUD_AGND
HDA_BITCLK_CODEC
20150205 MV-1 Ita
R2710
R2710
1 2
0R0402-PAD
0R0402-PAD
R2713
R2713
1 2
0R0402-PAD
0R0402-PAD
R2703
R2703
1 2
22R2J-2-GP
22R2J-2-GP
HDA_SYNC_CODEC 19
HDA_RST#_CODEC 19
FC2701 SC4D7P50V2BN-GP
FC2701 SC4D7P50V2BN-GP
1 2
DMIC_DATA 52
DMIC_CLK 52
HP_COMBO_CGI 28,29
HDA_SDOUT_CODEC 19
HDA_SDIN0_CPU 19
1 2
C2714
C2714
SC22P50V2JN-4GP
SC22P50V2JN-4GP
AUD_AGND
AUD_AGND
AUD_AGND
DY
DY
2
1 2
D2704
D2704
AZ5125-01H-R7G-GP
AZ5125-01H-R7G-GP
DY
DY
1 2
C2707
C2707
HDA_BITCLK_CODEC 19
HDA_RST#_CODEC 19
3D3V_S0
5V_S0
R2702
R2702
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1 2
AVDD_CODEC_EN
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
DY
DY
A_SD# 24,28
1 2
R2707
R2707
4K7R2J-2-GP
4K7R2J-2-GP
DY
DY
HDA_CODEC_RST#
1 2
C2723
C2723
SCD01U50V2KX-L-GP
SCD01U50V2KX-L-GP
DY
DY
L2701
L2701
BLM18PG60 0SN-2GP
BLM18PG600SN-2GP
1 2
DY
DY
U2702
U2702
EN3NC#4
2
GND
1
IN
HPA01091DBVR-GP
HPA01091DBVR-GP
74.01091.03F
74.01091.03F
D2701
D2701
1SS355GP-GP
1SS355GP-GP
A K
83.00355.F1F
83.00355.F1F
D2703
D2703
1SS355GP-GP
1SS355GP-GP
A K
DY
DY
83.00355.F1F
83.00355.F1F
Port Arrangement
Port A---> x
Port B---> x
Port C---> x
Port D---> Speaker
Port E---> x
Port F---> Mic In
OUT
4
5
AUD_AGND
3D3V_S0
1 2
R2705
R2705
10KR2J-3-GP
10KR2J-3-GP
1 2
C2720
C2720
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
1
Vout = 4.75 V
AVDD_CODEC
1 2
C2712
C2712
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
DY
DY
A_SD#_R
1 2
C2730
C2730
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
Port G---> x
B B
Port H---> x
Port I---> Head Phone
Digital GND & AUD_AGND
Tie Analog GND and Digital GND
under codec by a single point
G2701
G2701
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
G2702
G2702
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
G2703
G2703
1 2
GAP-CLOSE-PWR-3-GP
A A
GAP-CLOSE-PWR-3-GP
AUD_AGND
audio ground must be connect to
digital ground with an 80 mil copper
bridge located directly under codec
to prevent ESD latch up.
5
4
3
HDA_SPKR 20
2
PC BEEP
R2719
R2719
47KR2J-L2-GP
47KR2J-L2-GP
1 2
C2725
C2725
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
AUO_BEEP MONO_L_1
12
R2711
R2711
10KR2J-3-GP
10KR2J-3-GP
1 2
AUD_AGND
UMA
UMA
UMA
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 2
C2728
C2728
SCD01U50V2KX-L-GP
SCD01U50V2KX-L-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Audio Codec_ALC3225
Audio Codec_ALC3225
Audio Codec_ALC3225
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
1
27 102
27 102
27 102
1
1
1
5
D D
C C
20150205 MV-1 Ita
HPA_OUT_L1_R 27
HPA_OUT_R1_R 27
AUD_AGND
R2833
R2833
0R0402-PAD
0R0402-PAD
1 2
R2834
R2834
0R0402-PAD
0R0402-PAD
1 2
4
AVDD_CODEC
1 2
1 2
C2830
C2830
C2831
C2831
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
AMP
AMP
AMP
AMP
AUD_AGND AUD_AGND
AMP
AMP
C2832 SC1U10V2KX-L1-GP
C2832 SC1U10V2KX-L1-GP
1 2
AMP
LEFTINP_R
RIGHTINP_R RIGHTINP
R2835
R2835
0R0402-PAD
0R0402-PAD
1 2
R2836
R2836
0R0402-PAD
0R0402-PAD
1 2
AMP
C2833 SC2D2U10V3KX-L-GP
C2833 SC2D2U10V3KX-L-GP
1 2
AMP
AMP
C2834 SC2D2U10V3KX-L-GP
C2834 SC2D2U10V3KX-L-GP
1 2
HPA_OUT_R1 27,29
HPA_OUT_L1 27,29
20141203 SE - Ita
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
C2835
C2835
1 2
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
C2836
C2836
RIGHTINM RIGHTINM_R
1 2
AMP
AMP
AMP
AMP
LEFTINM_R LEFTINM
LEFTINM_R
LEFTINP
RIGHTINM_R
3
U2801
U2801
AMP
AMP
12
VDD
20
VDD
CPN
17
CPN
CPP
18
CPP
1
LEFTINM
2
LEFTINP
5
RIGHTINM
4
RIGHTINP
11
HPRIGHT
14
HPLEFT
HPA022642RTJR-GP
HPA022642RTJR-GP
074.22642.0013
074.22642.0013
TEST1
TEST2
CPVSS
CPVSS
AMP_TEST1
R2830 2K2R2J-L1-GP
R2830 2K2R2J-L1-GP
AMP_TEST2
AMP_SD#
CPVSS
AUD_AGND
1 2
R2831 2K2R2J-L1-GP
R2831 2K2R2J-L1-GP
1 2
1 2
C2837
C2837
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
AMP
AMP
8
7
6
SD#
3
GND
9
GND
10
GND
13
GND
19
GND
21
GND
15
16
AVDD_CODEC
AMP
AMP
AMP
AMP
2
AMP
AMP
D2801
D2801
A_SD# 24,27
HP_COMBO_CGI 27,29
1
3
2
BAT54A-7-F-2-GP
BAT54A-7-F-2-GP
75.00054.R7D
75.00054.R7D
2nd = 75.00054.I7D
2nd = 75.00054.I7D
AMP_SD#
3D3V_S0
1
1 2
R2832
R2832
10KR2J-L-GP
10KR2J-L-GP
AMP
AMP
R2837
R2837
DY
4
22KR2F-GP
22KR2F-GP
1 2
R2838
R2838
22KR2F-GP
22KR2F-GP
1 2
DY
DY
DY
AUD_AGND
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Audio AMP_HPA0022642RTJR
Audio AMP_HPA0022642RTJR
Audio AMP_HPA0022642RTJR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
28 102
28 102
28 102
1
1
1
1
LEFTINM
RIGHTINM
B B
A A
5
5
4
3
2
1
D D
MIC_VREFO 27
Q2901
Q2901
AMP
AMP
MIC2_JD 27
C C
D
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.07002.I31
2nd = 84.07002.I31
3rd = 84.2N702.W31
3rd = 84.2N702.W31
HP_COMBO_CGI 27,28
S
G
JACK_DET
DY_Non AMP
DY_Non AMP
R2901
R2901
0R2J-L-GP
0R2J-L-GP
1 2
MIC_L 27
HPA_OUT_L1 27,28
HPA_OUT_R1 27,28
JACK_DET 27
MIC_VREFO_G
Combo-Jack (Headphone & MIC)
R2805
R2805
2K2R2J-L1-GP
2K2R2J-L1-GP
1 2
R2801
R2801
1KR2F-L1-GP
1KR2F-L1-GP
HPA_OUT_L1
HPA_OUT_R1
MIC_VREFO_G
1 2
C2809
C2809
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
1 2
R2803 30D1R2F-L-GP R2803 30D1R2F-L-GP
1 2
R2804 30D1R2F-L-GP R2804 30D1R2F-L-GP
1 2
R2807 22KR2J-GP R2807 22KR2J-GP
1 2
22KR2J-GP
22KR2J-GP
R2806
R2806
AUD_AGND AUD_AGND
1 2
1 2
C2820
C2820
SC100P50V2JN-3GP
SC100P50V2JN-3GP
AUD_AGND AUD_AGND AUD_AGND
1 2
C2819
C2819
COMBO1
COMBO1
MIC_L_1 MIC_L
HP_OUTL_2
HP_OUTR_2
JACK_DET
1 2
C2818
C2818
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
HP_OUTL_2
JACK_DET
HP_OUTR_2
MIC_L_1
AUD_AGND
20141020 SC - Ita Change symbol
HP_OUTL_2
MIC_L_1
JACK_DET
HP_OUTR_2
AUD_AGND
3
1
5
6
2
4
MS
AUDIO-JK505-GP
AUDIO-JK505-GP
022.10002.0931
022.10002.0931
1
1
1
1
1
AFTP2905 AFTE14P-GP AFTP2905 AFTE14P-GP
AFTP2906 AFTE14P-GP AFTP2906 AFTE14P-GP
AFTP2907 AFTE14P-GP AFTP2907 AFTE14P-GP
AFTP2908 AFTE14P-GP AFTP2908 AFTE14P-GP
AFTP2909 AFTE14P-GP AFTP2909 AFTE14P-GP
Speaker
1
2
3
4
1
1
1
1
5
SPK1
SPK1
ACES-CON4-21-GP
ACES-CON4-21-GP
6
AFTP2901 AFTE14P-GP AFTP2901 AFTE14P-GP
AFTP2902 AFTE14P-GP AFTP2902 AFTE14P-GP
AFTP2903 AFTE14P-GP AFTP2903 AFTE14P-GP
AFTP2904 AFTE14P-GP AFTP2904 AFTE14P-GP
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Audio Combo Jack / SPK Conn
Audio Combo Jack / SPK Conn
Audio Combo Jack / SPK Conn
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Laduree-BDW 15.6"
Taipei Hsien 221, Taiwan, R.O.C.
29 102
29 102
29 102
1
1
1
1
B B
SPKR_R+ 27
SPKR_R- 27
SPKR_L+ 27
SPKR_L- 27
1 2
1 2
1 2
C2910
C2910
C2907
C2907
SC1KP50V2KX-L-1-GP
SC1KP50V2KX-L-1-GP
SC1KP50V2KX-L-1-GP
SC1KP50V2KX-L-1-GP
A A
5
4
C2909
C2909
SC1KP50V2KX-L-1-GP
SC1KP50V2KX-L-1-GP
1 2
C2908
C2908
SC1KP50V2KX-L-1-GP
SC1KP50V2KX-L-1-GP
SPKR_L+
SPKR_LSPKR_R+
SPKR_R-
3
5
4
3
2
1
EEPROM LED OPTION USE '00'
=> LED0 : ACT (Amber)
=> LED1 : LINK (White)
(BOTH 10/100 & GIGA CHIP)
(Power down => Kept high)
D D
Layout:
For RTL8111G(S)
* Place C3021 to C3024 close to each VDD10 pin--3, 8,
L3001
L3001
IND-2D2UH- 297-GP
REGOUT
IND-2D2UH-297-GP
1 2
68.2R21G.10P
68.2R21G.10P
1 2
C3003
C3003
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
20140802
1V_LAN_VDD10
12
C3027
C3027
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
C3032: colse to Pin8
C3025 close to Pin30
C3026: close to Pin3
C3031: close to Pin22
12
12
C3026
C3026
C3025
C3025
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
12
12
C3031
C3031
C3032
C3032
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
12
12
C3030
C3030
C3024
C3024
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
C3024 / C3030 close to Pin22
RSET
1 2
R3008
R3008
2K49R2F-2-L-GP
2K49R2F-2-L-GP
MDIP0 31
MDIN0 31
MDIP1 31
MDIN1 31
MDIP2 31
MDIN2 31
MDIP3 31
MDIN3 31
PCIE_WAKE#_LAN
ISOLATEB
3D3V_S5
1 2
R3006
R3006
4K02R2F-GP
4K02R2F-GP
PCIE_WAKE#_LAN_B
1 2
R3012
R3012
2KR2J-1-GP
2KR2J-1-GP
1V_LAN_VDD10
1V_LAN_VDD10
3D3V_LAN_VDD33
C C
B B
PCIE_WAKE#_LAN
A A
5
B
4
U3001
U3001
3
AVDD10
8
AVDD10
30
AVDD10
32
AVDD33
11
AVDD33
23
VDDREG
22
DVDD10
1
MDIP0
2
MDIN0
4
MDIP1
5
MDIN1
6
MDIP2
7
MDIN2
9
MDIP3
10
MDIN3
21
LANWAKE#
20
ISOLATE#
RTL8111HSH-CG-GP
RTL8111HSH-CG-GP
071.8111H.M002
071.8111H.M002
C
Q3002
Q3002
LMBT3904LT1G-GP
LMBT3904LT1G-GP
84.T3904.H11
84.T3904.H11
2 n d = 84.03904.X11
2nd = 84.03904.X11
E
3rd = 84.03904.E11
3rd = 84.03904.E11
R3011
R3011
0R2J-2-GP
0R2J-2-GP
DY
DY
CLKREQ#
REFCLK_P
REFCLK_N
LED1/GPO
1 2
PERST#
CKXTAL1
CKXTAL2
REGOUT
13
HSIP
14
HSIN
17
HSOP
18
HSON
19
12
15
16
28
29
27
LED0
26
25
LED2
24
31
RSET
33
GND
0822-Anthony
PCIE_TX_LAN_P3 16
PCIE_RX_LAN_P3
PCIE_RX_LAN_N3
LAN_XTAL_25M_IN
LAN_XTAL_25M_OUT
LAN_LED3#
REGOUT
RSET
PCIE_WAKE# 17,24,58,63
PCIE_TX_LAN_N3 16
LAN_XTAL_25M_IN
LAN_XTAL_25M_OUT
C3028 SCD1U16V2KX-L-GP C3028 SCD1U16V2KX-L-GP
1 2
C3029 SCD1U16V2KX-L-GP C3029 SCD1U16V2KX-L-GP
PLT_RST# 17,24,36,58,63,65,76,88,96
LAN_CLK_CPU 18
LAN_CLK_CPU# 18
1 2
LAN_CLKREQ_CPU# 18,20
AMBER_LED# 31
WHITE_LED# 31
DY
DY
R3009
R3009
1MR2J-L3-GP
1MR2J-L3-GP
1 2
3
1
TP3001 TPAD14-OP-GP TP3001 TPAD14-OP-GP
2 3
PCIE_RX_CPU_P3 16
PCIE_RX_CPU_N3 16
X3001
X3001
4 1
XTAL-25MHZ-181-GP
XTAL-25MHZ-181-GP
82.30020.G71
82.30020.G71
2nd = 82.30020.G61
2nd = 82.30020.G61
20150210 MV-1 Ita
C3022
C3022
SC12P50V2JN-3GP
SC12P50V2JN-3GP
1 2
C3023
C3023
SC15P50V2JN-L-GP
SC15P50V2JN-L-GP
1 2
R3004
R3004
1 2
0R0603-PAD-1-GP-U
0R0603-PAD-1-GP-U
2
1 2
40 mils
C3008: close to Pin32
C3007: close to Pin11 (RTL8111 only)
C3009 and C3011 close pin23
12
1 2
C3009
C3009
C3010
C3010
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
DY
DY
DY
DY
3D3V_S0
ISOLATEB
3D3V_LAN_VDD33 3D3V_S5
C3007
C3007
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
12
C3008
C3008
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
1 2
12
C3012
C3012
C3011
C3011
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
C3011 / C3012 close to Pin23
R3010
R3010
1KR2J-L2-GP
1KR2J-L2-GP
1 2
1 2
R3013
R3013
15K4R2F-GP
15K4R2F-GP
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
LAN(RTL8411)
LAN(RTL8411)
LAN(RTL8411)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Thursday, February 12, 2015
Thursday, February 12, 2015
Thursday, February 12, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Laduree-BDW 15.6"
Laduree-BDW 15.6"
Laduree-BDW 15.6"
1
30 102
30 102
30 102
1
1
1