HP HCTL-1100 Datasheet

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MOTION SENSING

AND CONTROL

General Purpose Motion
Control ICs

Technical Data

HCTL-1100 Series

Description

The HCTL-1100 series is a high
performance, general purpose
motion control IC, fabricated in
HP CMOS technology. It frees the
host processor for other tasks by
performing all the time-intensive
functions of digital motion
control. The programmability of
all control parameters provides
maximum flexibility and quick

Features

• Low Power CMOS

• PDIP and PLCC Versions
Available

• Enhanced Version of the
HCTL-1000

• DC, DC Brushless, and Step
Motor Control

• Position and Velocity
Control

• Programmable Digital Filter
and Commutator

• 8-Bit Parallel, and PWM
Motor Command Ports

• TTL Compatible

• SYNC Pin for Coordinating
Multiple HCTL-1100 ICs

• 100 kHz to 2 MHz Operation

• Encoder Input Port

design of control systems with a
minimum number of components.
In addition to the HCTL-1100, the
complete control system consists
of a host processor to specify
commands, an amplifier, and a
motor with an incremental
encoder (such as the HP HEDS­5XXX, -6XXX, -9XXX series). No
analog compensation or velocity
feedback is necessary.

Pinouts

ESD WARNING: NORMAL HANDLING PRECAUTIONS SHOULD BE TAKEN TO AVOID STATIC DISCHARGE.

H

5965-5893E

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Applications

Typical applications for the
HCTL-1100 include printers,
medical instruments, material
handling machines, and industrial
automation.

HCTL-1100 vs.
HCTL-1000

The HCTL-1100 is designed to
replace the HCTL-1000. Some
differences exist, and some
enhancements have been added.

Comparison of HCTL-1100 and HCTL-1000

Description HCTL-1100 HCTL-1000

Max. Supply Current 30 mA 180 mA
Max. Power Dissipation 165 mW 950 mW
Max. Tri-State Output

Leakage Current 150 nA 10 µA
Operating Frequency 100 kHz-2 MHz 1 MHz-2 MHz
Operating Temperature

Range -20°C to +85°C0°C to 70°C
Storage Temperature Range -55°C to +125°C-40°C to +125°C
Synchronize 2 or More ICs Yes –
Preset Actual Position

Registers Yes –
Read Flag Register Yes –
Limit and Stop Pins Must be pulled Can be left

up to VDD if floating if not

not used. used.
Hard Reset Required Recommended
PLCC Package Available Yes –

System Block Diagram

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Theory of Operation

The HCTL-1100 is a general pur­pose motor controller which
provides position and velocity
control for DC, DC brushless and
stepper motors. The internal
block diagram of the HCTL-1100
is shown in Figure 1. The HCTL­1100 receives its input commands
from a host processor and
position feedback from an
incremental encoder with quadra­ture output. An 8-bit bi-directional
multiplexed address/data bus
interfaces the HCTL-1100 to the
host processor. The encoder

The resident Position Profile
Generator calculates the neces­sary profiles for Trapezoidal Pro­file Control and Integral Velocity
Control. The HCTL-1100 com­pares the desired position (or
velocity) to the actual position (or
velocity) to compute compensated
motor commands using a pro­grammable digital filter D(z). The
motor command is externally
available at the Motor Command
port as an 8-bit byte and at the
PWM port as a Pulse Width
Modulated (PWM) signal.

The HCTL-1100 has the capability
of providing electronic commu­tation for DC brushless and
stepper motors. Using the
encoder position information, the
motor phases are enabled in the
correct sequence. The commu­tator is fully programmable to
encompass most motor/encoder
combinations. In addition, phase
overlap and phase advance can be
programmed to improve torque
ripple and high speed perform­ance. The HCTL-1100 contains a
number of flags including two
externally available flags, Profile
and Initialization, which allow the
user to see or check the status of
the controller. It also has two
emergency inputs, Limit and Stop,
which allow operation of the
HCTL-1100 to be interrupted
under emergency conditions.

The HCTL-1100 controller is a
digitally sampled data system.
While information from the host
processor is accepted asyn­chronously with respect to the
control functions, the motor
command is computed on a
discrete sample time basis. The
sample timer is programmable.

Package Dimensions

feedback is decoded into
quadrature counts and a 24-bit
counter keeps track of position.
The HCTL-1100 executes any one
of four control algorithms
selected by the user. The four
control modes are:

• Position Control

• Proportional Velocity Control

• Trapezoidal Profile Control for
point to point moves

• Integral Velocity Control with
continuous velocity profiling
using linear acceleration

4.83

0.190

1.27

0.050

±

0.15

0.006

0-15°

13.72

0.540

13.72

0.540

0.25

0.010

±

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Figure 1. Internal Block Diagram.

Figure 2. Operating Mode Flowchart.

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MOTION SENSING

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Electrical Specifications

Absolute Maximum Ratings

Operating Temperature, T

A

...................................................................

-20°C to 85°C

Storage Temperature, T

S

......................................................................

-55°C to 125°C

Supply Voltage, V

DD

......................................................................................

-0.3 V to 7 V

Input Voltage, V

IN

.........................................................................

-0.3 V to VDD +0.3 V

Maximum Operating Clock Frequency, f

CLK

...............................................

2 MHz

DC Electrical Characteristics

VDD = 5 V ± 5%; TA = -20°C to +85°C

Parameter Symbol Min. Typ. Max. Units Test Conditions

Supply Voltage V

DD

4.75 5.00 5.25 V

Supply Current I

DD

15 30 mA

Input Leakage Current I

IN

10 100 nA VIN = 0.00 and 5.25 V
Input Pull-Up Current
SYNC PIN I

PU

- 40 ± 150 µAVIN = 0.00 V

Tristate Output Leakage I

OZ

10 -150 nA Sync, LIMIT, STOP
Current pin #35 (PDIP)

V

OUT

= -0.3 to 5.25 V

pin #38 (PLCC)

Input Low Voltage V

IL

-0.3 0.8 V

Input High Voltage V

IH

2.0 V

DD

V

Output Low Voltage V

OL

-0.3 0.4 V IOL = 2.2 mA

Output High Voltage V

OH

2.4 V

DD

VIOH = -200 µA

Power Dissipation P

D

75 165 mW
Input Capacitance C

IN

20 pF

Output Capacitance C

OUT

100 pF

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AC Electrical Characteristics

VDD = 5 V ± 5%; TA = -20°C to +85°C; Units = nsec

Clock Frequency

Formula*

2 MHz 1 MHz

ID

# Signal Symbol Min. Max. Min. Max. Min. Max.

1 Clock Period (clk) t

CPER

500 1000

2 Pulse Width, Clock High t

CPWH

230 300

3 Pulse Width, Clock Low t

CPWL

200 200 200

4 Clock Rise and Fall Time t

CR

50 50 50

5 Input Pulse Width Reset t

IRST

2500 5000 5 clk

6 Input Pulse Width Stop, Limit t

IP

600 1100 1 clk

+ 100 ns

7 Input Pulse Width Index, Index t

IX

1600 3100 3 clk

+ 100 ns

8 Input Pulse Width CHA, CHB t

IAB

1600 3100 3 clk

+ 100 ns

9 Delay CHA to CHB Transition t

AB

600 1100 1 clk

+ 100 ns

10 Input Rise/Fall Time CHA, CHB,

Index t

IABR

450 900 900 (clk

< 1 MHz)

11 Input Rise/Fall Time Reset, ALE,

CS, OE, Stop, Limit t

IR

50 50 50

12 Input Pulse Width ALE, CS t

IPW

80 80 80

13 Delay Time, ALE Fall to CS Fall t

AC

50 50 50

14 Delay Time, ALE Rise to CS Rise t

CA

50 50 50

15 Address Setup Time Before

ALE Rise t

ASR1

20 20 20

16 Address Setup Time Before CS t

ASR

20 20 20

Fall

17 Write Data Setup Time Before

CS Rise t

DSR

20 20 20

18 Address/Data Hold Time t

H

20 20 20

19 Setup Time, R/W Before CS Rise t

WCS

20 20 20

20 Hold Time, R/W After CS Rise t

WH

20 20 20

21 Delay Time, Write Cycle, CS

Rise to ALE Fall t

CSAL

1700 3400 3.4 clk

22 Delay Time, Read/Write, CS

Rise to CS Fall t

CSCS

1500 3000 3 clk

23 Write Cycle, ALE Fall to ALE

Fall For Next Write t

WC

1830 3530 3.7 clk

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MOTION SENSING

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Clock Frequency

Formula*

2 MHz 1 MHz

ID

# Signal Symbol Min. Max. Min. Max. Min. Max.

24 Delay Time, CS Rise to OE Fall t

CSOE

1700 3200 3 clk

+ 200 ns

25 Delay Time, OE Fall to Data

Bus Valid t

OEDB

100 100 100

26 Delay Time, CS Rise to Data

Bus Valid t

CSDB

1800 3300 3 clk

+ 300 ns

27 Input Pulse Width OE t

IPWOE

100 100 100

28 Hold Time, Data Held After

OE Rise t

DOEH

20 20 20

29 Delay Time, Read Cycle, CS

Rise to ALE Fall t

CSALR

1820 3320 3 clk

+ 320 ns

30 Read Cycle, ALE Fall to ALE

Fall For Next Read t

RC

1950 3450 3 clk

+ 450 ns

31 Output Pulse Width, PROF,

INIT, Pulse, Sign, PHA-PHD,
MC Port t

OF

500 1000 1 clk

32 Output Rise/Fall Time, PROF,

INIT, Pulse, Sign, PHA-PHD,
MC Port t

OR

20 150 20 150 20 150

33 Delay Time, Clock Rise to

Output Rise t

EP

20 300 20 300 20 300

34 Delay Time, CS Rising to MC

Port Valid t

CSMC

1600 3200 3.2 clk

35 Hold Time, ALE High After

CS Rise t

ALH

100 100 100

36 Pulse Width, ALE High t

ALPWH

100 100 100

37 Pulse Width, SYNC Low t

SYNC

9000 18000 18 clk

*General formula for determining AC characteristics for other clock frequencies (clk), between 100 kHz and 2 MHz.

AC Electrical Characteristics (continued).

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HCTL-1100 I/O Timing Diagrams

Input logic level values are the TTL Logic levels VIL = 0.8 V and VIH = 2.0 V. Output logic levels
are VOL = 0.4 V and VOH = 2.4 V.

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HCTL-1100 I/O Timing Diagrams

There are three different timing configurations which can be used to give the user flexibility to interface the
HCTL-1100 to most microprocessors. See the I/O interface section for more details.

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HCTL-1100 I/O Timing Diagrams

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HCTL-1100 I/O Timing Diagrams

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Pin Descriptions and Functions

Input/Output Pins

Pin Number

Symbol PDIP PLCC Description

AD0/DB0- 2-7 3-8 Address/Data Bus – Lower 6 bits of 8-bit I/O port which are
AD5/DB5 multiplexed between address and data.

DB6, DB7 8, 9 9, 10 Data bus – Upper 2 bits of 8-bit I/O port used for data only.

Input Signals

Pin Number

Symbol PDIP PLCC Description

CHA/CHB 31, 30 34, 33 Channel A, B – Input pins for position feedback from an incremental

shaft encoder. Two channels, A and B, 90 degrees out of phase are
required.

Index 33 36 Index Pulse – Input from the reference or index pulse of an incre-

mental encoder. Used only in conjunction with the Commutator. Either
a low or high true signal can be used with the Index pin. See Timing

Diagrams and Encoder Interface section for more detail.
R/W 37 41 Read/Write – Determines direction of data exchange for the I/O port.
ALE 38 42 Address Latch Enable – Enables lower 6 bits of external data bus into

internal address latch.
CS 39 43 Chip Select – Performs I/O operation dependent on status of R/W line.

For a Write, the external bus data is written into the internal

addressed location. For Read, data is read from an internal location

into an internal output latch.
OE 40 44 Output Enable – Enables the data in the internal output latch onto the

external data bus to complete a Read operation.
Limit 14 15 Limit Switch – An internal flag which when externally set, triggers an

unconditional branch to the Initialization/Idle mode before the next

control sample is executed. Motor Command is set to zero. Status of

the Limit flag is monitored in the Status register.
Stop 15 16 Stop Flag – An internal flag that is externally set. When flag is set

during Integral Velocity Control mode, the Motor Command is

decelerated to a stop.
Reset 36 40 Reset – A hard reset of internal circuitry and a branch to Reset mode.
ExtClk 34 37 External Clock
V

DD

11, 35 12, 38 Voltage Supply – Both VDD pins must be connected to a 5.0 volt supply.

GND 10, 32 1, 11, Circuit Ground

23, 35
SYNC 1 2 Used to synchronize multiple HCTL-1100 sample timers.
NC – 17, 39 Not connected. These pins should be left floating.