HP AT-38086-BLK, AT-38086-TR1 Datasheet

4.8 V NPN Silicon Bipolar
Common␣ Emitter Transistor

Technical Data

AT-38086

Features

• 4.8 Volt Pulsed

(pulse width = 577 µsec,

duty cycle = 12.5%)/CW
Operation

• +28 dBm Pulsed P
@␣ 900␣ MHz, Typ.

• +23.5 dBm CW P
@␣ 836.5␣ MHz, Typ.

• 60% Pulsed Collector
Efficiency @ 900 MHz, Typ.

• 11 dB Pulsed Power Gain
@␣ 900 MHz, Typ.

• -35 dBc IMD3 @ P
17␣ dBm per tone, 900 MHz,
Typ.

out

out

out

of

Applications

• Driver Amplifier for GSM
and AMPS/ETACS/ 900 MHz
NMT Cellular Phones

• 900 MHz ISM and Special
Mobile Radio

85 mil Plastic Surface Mount Package

Outline 86

Pin Configuration

4

EMITTER

1

BASE

EMITTER

2

3

COLLECTOR

Description

Hewlett Packard’s AT-38086 is a
low cost, NPN silicon bipolar
junction transistor housed in a
surface mount plastic package.
This device is designed for use as
a pre-driver or driver device in
applications for cellular and
wireless communications
markets. At 4.8 volts, the
AT-38086 features +28 dBm pulsed
output power, Class AB operation,
and +23.5␣ dBm CW. Superior
efficiency and gain makes the
AT-38086 an excellent choice for
battery powered systems.

The AT-38086 is fabricated with
Hewlett Packard’s 10 GHz Ft Self­Aligned-Transistor (SAT) process.
The die are nitride passivated for
surface protection. Excellent
device uniformity, performance
and reliability are produced by the
use of ion-implantation, self­alignment techniques, and gold
metalization in the fabrication of
these devices.

4-89

5965-5959E

AT-38086 Absolute Maximum Ratings

Absolute

Symbol Parameter Units Maximum

V

EBO

V

CBO

V

CEO

I

C

I

C

P

T

P

T

T

j

T

STG

Notes:

1. Permanent damage may occur if any of these limits are exceeded.

2. Pulsed operation, pulse width = 577␣ µsec, duty cycle␣ =␣ 12.5%.

3. CW operation.

4. Derate at 57.1 mW/°C for T

collector pin 3, where the lead contacts the circuit board.

5. Derate at 7.1 mW/°C for T

collector pin 3, where the lead contacts the circuit board.

6. Using the liquid crystal technique, V
“hot-spot” resolution.

Emitter-Base Voltage V 1.4
Collector-Base Voltage V 16.0
Collector-Emitter Voltage V 9.5
Collector Current
Collector Current
Peak Power Dissipation
CW Power Dissipation

[2]

[3]

[2, 4]

[3, 5]

m A 250
m A 160

W 3.7

m W 460

Junction Temperature °C 150
Storage Temperature °C -65 to 150

␣>␣85 °C. T

C

␣>␣85 °C. T

C

is defined to be the temperature of the

C

is defined to be the temperature of the

C

= 4.5 V, Ic= 50 mA, T

CE

=150° C, 1-2␣ µm

j

[1]

Thermal Resistance

θjc = 140°C/W

[6]

:

Electrical Specifications, T

= 25° C

C

Symbol Parameters and Test Conditions Units Min. Typ. Max.

P

out

η

C

P

out

IMD

BV

BV

BV

h

FE

I

CEO

Freq. = 900 MHz, VCE = 4.8 V, I
duty cycle = 12.5%, unless otherwise specified

Output Power, Test Circuit A, Pin = +17 dBm dBm +26.5 +28.0
Pulsed Operation

Collector Efficiency, Test Circuit A, Pin = +17 dBm % 50 60
Pulsed Operation

Mismatch Tolerance Test Circuit A, P
No Damage, Pulsed

[1]

[1]

[1]

Output Power , F = 836.5 MHz, ICQ = 1 5 m A d B m +22.0 +23.5
CW Operation

3rd Order Intermodulation Distortion, F1 = 899 MHz, F2 = 901 MHz

3

2-Tone Test, P

[2]

each tone = +17 dBm, CW

out

Mismatch Tolerance, No Damage, F = 836.5 MHz, ICQ = 15 mA 7:1

[2]

CW

Emitter-Base Breakdown Voltage IE = 0.2 mA, open collector V 1.4

EBO

Collector-Base Breakdown Voltage IC = 1.0 mA, open emitter V 16.0

CBO

Collector-Emitter Breakdown Voltage IC = 3.0 mA, open base V 9.5

CEO

Forward Current Transfer Ratio VCE = 3 V, IC = 160 mA — 40 150 330

Collector Leakage Current V

= 20 mA, Pulse width = 577 µsec,

CQ

out

any phase, 2 sec duration

Test Circuit B, Pin = +10 dBm

[2,3]

ICQ = 15 mA, Test Circuit B

Test Circuit B, P

out

any phase, 2 sec duration

= +28 dBm, 7:1

dBc -35

= +23.5 dBm

= 5 V µA15

CEO

Notes:

1. With external matching on input and output, tested in a 50 ohm environment. Refer to Test Circuit A (GSM).

2. With external matching on input and output, tested in a 50 ohm environment. Refer to Test Circuit B (AMPS).

3. Test circuit B re-tuned at 900␣ MHz.

4-90

AT-38086 Typical Performance, T

Frequency = 900 MHz, VCE = 4.8 V, I

= 20 mA, pulsed operation, pulse width␣ =␣ 577␣ µsec, duty cycle␣ =␣ 12.5%,

CQ

= 25° C

C

Test Circuit A (GSM), unless otherwise specified

32

Γ

= 0.75 ∠ -177

source

30

Γ

= 0.48 ∠ +161

load

28
26

(dBm)

24
22
20
18

OUTPUT POWER

16
14
12

21412641081816 242220

P

out

η

c

INPUT POWER (dBm)

100
90
80
70
60
50
40

30
20
10
0

Figure 1. Output Power and Collector
Efficiency vs. Input Power.

32

Γ

source

30

Γ

(%)

COLLECTOR EFFICIENCY

load

28
26

(dBm)

24
22
20
18

OUTPUT POWER

16
14
12

21412641081816 242220

Figure 2. Output Power vs. Input
Power Over Bias Voltage.

= 0.75 ∠ -177

= 0.48 ∠ +161

INPUT POWER (dBm)

3.6 V

4.8 V

6.0 V

90

Γ

= 0.75 ∠ -177

source

80

Γ

= 0.48 ∠ +161

load

(%)

70
60
50
40
30
20

COLLECTOR EFFICIENCY

10

0

21412641081816 242220

INPUT POWER (dBm)

3.6 V

4.8 V

6.0 V

Figure 3. Collector Efficiency vs.
Input Power Over Bias Voltage.

32

Γ

= 0.75 ∠ -177

source

Γ

= 0.48 ∠ +161

load

30

(dBm)

28

26

24

OUTPUT POWER

22

20

10 1612 14 18 242220

INPUT POWER (dBm)

TC = +85°C

= +25°C

T

C

= –40°C

T

C

Figure 4. Output Power vs. Input
Power Over Temperature.

29.0

Γ

28.8

Γ

28.6

28.4

(dBm)

28.2

28.0

27.8

27.6

OUTPUT POWER

27.4

27.2

27.0
880

Pin = +17 dBm

= 0.75 ∠ -177

source

= 0.48 ∠ +161

load

P

out

η

c

FREQUENCY (MHz)

Figure 5. Output Power and
Collector Efficiency vs. Frequency.

Note: Tuned at 900 MHz, then Swept
over Frequency.

75

71

67

63

59

55

0

Γ

-2

(%)

COLLECTOR EFFICIENCY

Γ

-4

(dB)

-6

-8

-10

RETURN LOSS

-12

-14

-16
800 850 950 1000900890 910 920900

Figure 6. Input and Output Return
Loss vs. Frequency.

= 0.75 ∠ -177

source

= 0.48 ∠ +161

load

FREQUENCY (MHz)

Output R.L.

Input R.L.

4-91