Fairchild Semiconductor MM74HC164MTC, MM74HC164MTCX, MM74HC164MX, MM74HC164N, MM74HC164M Datasheet
MM74HC164
8-Bit Serial-in/Parallel-out Shift Register
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
September 1983
Revised February 1999
General Description
The MM74HC164 utilizes advanced silicon-gate CMOS
technology. It has the high noise imm unity and low consumption of standard CMOS integrated circuits. It also
offers speeds comparable to low power Schottky devices.
This 8-Bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip-flop. Inputs A
& B permit complete control over the incoming data. A
LOW at either or b oth i n puts inh i bits en try of new data and
resets the first flip-flop to the low level at the next clock
pulse. A high level on one input enables the other input
which will then determine the state of the first flip-flop. Data
at the serial inputs may be changed while the clock is HIGH
or LOW, but only information meet ing the setup and hold
time requirements will be entered. Data is serially shifted in
and out of the 8-Bit register during the positive going transi-
tion of the clock pulse . Clear is independent of th e clock
and accomplished by a low level at the CLEAR input.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
■ Typical operating frequency: 50 MHz
■ Typical propagation delay: 19 ns (clock to Q)
■ Wide operating supply voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent suppl y current: 80 µA maximum (74HC
Series)
■ Fanout of 10 LS-TTL loads
Ordering Code:
Order Number Package Number Package Description
MM74HC164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC164MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and TSSOP
Truth Table
Inputs Outputs
Q
Clear Clock A B Q
A
LXXXLL L
HLXXQ
AOQBO
H ↑ HH HQ
H ↑ LX LQ
H ↑ XL LQ
H = HIGH Level (steady state), L = LOW Level (steady state)
X = Irrelevant (any input, inc luding transitions)
↑ = Transition from LOW-to-HIGH level.
, QBO, QHO = the lev el of QA, QB, or QH, respectively, before the indi-
Q
AO
cated steady state input conditions were established.
, QGn = The level of QA or QG before the most recent ↑ transition of the
Q
An
clock; indicated a on e-bit shift.
... Q
B
Q
An
An
An
Q
Q
Q
H
HO
Gn
Gn
Gn
Top View
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Logic Diagram
MM74HC164
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Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
or GND Current, per pin (ICC) ±50 mA
DC V
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds ) 260°C
) −1.5 to V
IN
) −0.5 to V
OUT
, IOK) ±20 mA
IK
) ±25 mA
OUT
) −65°C to +150°C
STG
)
D
)
L
CC
CC
Recommended Operating
Conditions
+1.5V
Supply Voltage (V
+0.5V
DC Input or Output Voltage
, V
(V
IN
OUT
Operating Temperature Range (T
Input Rise or Fall Times
, tf) V
(t
r
CC
V
CC
V
Note 1: Absolute Maximum Ra tings are those valu es beyond w hich damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
CC
)26V
CC
)0V
) −40 +85 °C
A
= 2.0V 1000 ns
= 4.5V 500 ns
= 6.0V 400 ns
Min Max Units
CC
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions
V
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
V
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage 4.5V 1.35 1.35 1.35 V
V
Minimum HIGH Level V
OH
Output Voltage |I
V
Maximum LOW Level V
OL
Output Voltage |I
I
Maximum Input V
IN
Current
I
Maximum Quiescent V
CC
Supply Current I
Note 4: For a powe r supply o f 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case V
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be us ed.
rent (I
IN
= VIH or V
IN
OUT
V
IN
|I
OUT
|I
OUT
IN
OUT
V
IN
|I
OUT
|I
OUT
IN
IN
OUT
and VIL occur at V
IH
IL
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
= VIH or V
IL
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
= VIH or V
IL
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
= VIH or V
IL
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
= VCC or GND 6.0V 8.0 80 160 µA
= 0 µA
CC
V
CC
6.0V 4.2 4.2 4.2 V
6.0V 1.8 1.8 1.8 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3 .8 5V.) The worst c as e leakage cur-
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
MM74HC164
V
Units
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