Fairchild Semiconductor MM74HC161MX, MM74HC161MTC, MM74HC161N, MM74HC161MTCX, MM74HC161M Datasheet
...
September 1983
Revised February 1999
MM74HC161 • MM74HC163 Synchronous Binary Counter with Asynchronous Clear • Synchronous Binary
Counter with Synchronous Clear
© 1999 Fairchild Semiconductor Corporation DS005008.prf www.fairchildsemi.com
MM74HC161 • MM74HC163
Synchronous Binary Counter with Asynchronous Clear
• Synchronous Binary Counter with Synchronous Clear
General Description
The MM74HC161 and MM74HC163 synchronous presettable counters utilize advanced silicon-gate CMOS technology and internal look-ahead carry logic for use in high
speed counting applications. They offer the high noise
immunity and low po wer consumption inherent to CMOS
with speeds similar to low power Schottky TTL. The HC161
and the HC163 are 4 bit binary c ounters. All flip-flops are
clocked simultaneously on the LOW-to-HIGH transition
(positive edge) of the CLOCK input waveform.
These counters may be p reset u sing the LO AD inpu t. Pr esetting of all four flip-flops is synchronous to the rising edge
of CLOCK. When LOAD is held LOW cou nting is disabled
and the data on the A, B, C, and D inputs is loaded into the
counter on the rising edge o f CLOCK. If the load input is
taken HIGH before the positive edge of CLOCK the count
operation will be unaffected.
All of these counters may be cleared by utilizing the
CLEAR input. The clear function on the MM74HC163
counter is synchronous t o the clock. That is, the counters
are cleared on the positive edge o f CLO CK while th e cle ar
input is held LOW.
The MM74HC161 counter is cleared asynchronously.
When the CLEAR is taken LOW the counter is cleared
immediately regardless of the CLOCK.
Two active HIGH enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are pr ovid ed to e na ble e asy cascading of counters. Both ENABL E inputs must be HIG H to
count. The ENT input also enables the RC outp ut. When
enabled, the RC outputs a positive pulse wh en t he c oun ter
overflows. This pulse is approximately equal in duration to
the HIGH level portion of the Q
A
output. The RC output is
fed to successive cascaded stages to fa cilitate ea sy im plementation of N-bit counters.
All inputs are protected from damage due to static discharge by diodes to V
CC
and ground.
Features
■ Typical operating frequency: 40 MHz
■ Typical propagation delay; clock to Q: 18 ns
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Low input current: 1 µA maximum
■ Wide power supply range: 2–6V
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Order Number Package Number Package Description
MM74HC161M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC161N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC163 M M16A 16-Lead Small Outli n e Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC163SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC163N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
www.fairchildsemi.com 2
MM74HC161 • MM74HC163
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Tables
MM74HC161
MM74HC163
H = HIGH Level
L = LOW Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
Logic Diagram
CLK CLR ENP ENT Load Function
X L X X X Clear
X H H L H Count & RC disabled
X H L H H Count disabled
X H L L H Count & RC disabled
↑ H X X L Load
↑ H H H H Increment Counter
CLK CLR ENP ENT Load Function
↑ L X X X Clear
X H H L H Count & RC disabled
X H L H H Count disabled
X H L L H Count & RC disabled
↑ H X X L Load
↑ H H H H Increment Counter
3 www.fairchildsemi.com
MM74HC161 • MM74HC163
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ra tings are those valu es beyond w hich dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a powe r supply o f 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case V
IH
and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3. 85V.) The wor st c ase le ak ag e cur ren t
(I
IN
, ICC, and IOZ) occur for CMOS at the higher voltage and s o t he 6.0V values should be used.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to VCC+1.5V
DC Output Voltage (V
OUT
) −0.5 to VCC+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current, per pin (I
OUT
) ±25 mA
DC V
CC
or GND Current, per pin (ICC) ±50 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temper ature
(T
L
) (Solderin g 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
DC Input or Output Voltage 0 V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) V
CC
= 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
V
CC
TA=25°CTA=−40 to 85°CTA=−55 to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum HIGH Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA2.0V00.10.10.1V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN = VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input V
IN
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
I
CC
Maximum Quiescent V
IN
= VCC or GND 6.0V 8.0 80 160 µA
Supply Current I
OUT
= 0 µA
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