Fairchild Semiconductor MM74C73N Datasheet
MM74C73 • MM74C76
Dual J-K Flip-Flops with Clear and Preset
MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset
October 1987
Revised January 1999
General Description
The MM74C73 and MM74C76 dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-cha nnel enhancement transistors.
Each flip-flop has inde pendent J, K, c lock and clear inputs
and Q and Q outputs. The MM74C76 flip flops also inclu de
preset inputs a nd are supplied in 16 pin packages. This
flip-flop is edge sensitive to the clock input and change
state on the negative going transiti on of the clock pulse.
Clear or preset is inde pendent of the clock and i s accomplished by a low level on the respective input.
Features
■ Supply voltage range: 3V to 15V
■ Tenth power TTL compatibl e: Drive 2 LPTTL loads
■ High noise immunity: 0.45 V
■ Low power: 50 nW (typ.)
■ Medium speed operation: 10 MHz (typ.)
CC
(typ.)
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
• Computers
Ordering Code:
Order Number Package Number Package Description
MM74C73N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C76M M1 6A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74C76N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
MM74C73
MM74C76
Note: A logic “0” on clear sets Q to a logic “0”.
Note: A logic “0” on clear set s Q to logic “0”.
Top View
© 1999 Fairchild Semiconductor Corporation DS005884.prf www.fairchildsemi.com
Note: A logic “0” on preset sets Q t o a logic “1”.
Top Vi ew
Truth Tables
JKQ
00Q
010
MM74C73 • MM74C76
101
11Q
tn = bit time before clock puls e
= bit time after clock pulse
t
n+1
Logic Diagrams
t
n
t
n+1
Preset Clear Q
n
Q
n
00 00
n
01 10
10 01
11Qn
n
Note 1: No change in output from previous state
(Note 1)
Q
n
(Note 1)
MM74C73
MM74C76
Transmission Gate
www.fairchildsemi.com 2
Absolute Maximum Ratings(Note 2)
Voltage at Any Pin −0.3V to VCC + 0.3V
Operatin g Temperature Range −40°C to +85°C
Storage Temperature −65°C to +150°C
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature
(Soldering, 10 seconds) 260°C
Operating V
(Max) 18V
V
CC
Range +3V to 15V
CC
Note 2: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed. E x c ept for “ Operating Temperature Range” they are not mea nt to imply that the devices sh ould be operated at these limits. The table of Electrical Characteristics provides
conditions for actual device o peration.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
LOW POWER TTL TO CMOS INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Logical “1” Input Voltage VCC = 5V 3.5 V
VCC = 10V 8 V
Logical “0” Input Voltage VCC = 5V 1.5 V
VCC = 10V 2 V
Logical “1” Output Voltage VCC = 5V 4.5 V
VCC = 10V 9 V
Logical “0” Output Voltage VCC = 5V 0.5 V
VCC = 10V 1 V
Logical “1” Input Current VCC = 15V 1 µA
Logical “0” Input Current VCC = 15V −1 µA
Supply Current VCC = 15V 0.050 60 µA
Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V
Logical “0” Input Voltage VCC = 4.75V 0.8 V
Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V
Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V
Output Source Current VCC = 5V, V
TA = 25°C, V
Output Source Current VCC = 10V, V
TA = 25°C, V
Output Sink Current VCC = 5V, V
TA = 25°C, V
Output Sink Current VCC = 10V, V
TA = 25°C, V
= 0V −1.75 mA
IN(0)
= 0V
OUT
= 0V −8mA
IN(0)
= 0V
OUT
= 5V 1.75 mA
IN(1)
= V
OUT
CC
= 10V 8 mA
IN(1)
= V
OUT
CC
MM74C73 • MM74C76
3 www.fairchildsemi.com
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