Fairchild Semiconductor GTLP18T612MTDX, GTLP18T612MTD, GTLP18T612MEAX, GTLP18T612MEA Datasheet
© 1999 Fairchild Semiconductor Corporation DS500169 www.fairchildsemi.com
May 1999
Revised September 1999
GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
GTLP18T612
18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver
which provides LVTTL to GTLP sign al level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct res ult of GTL P ’s reduced out put sw ing
(< 1V), reduced input threshold levels and output edge rate
control. The edge rate c ontrol min imizes b us settli ng time.
GTLP is a Fairchild Semiconduct or derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has inte rnal ed ge-ra te cont rol and is Process, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP outpu t LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
■ Bidirectional interface between GTLP and LVTTL logic
levels
■ Edge Rate Control to minimize noise on the GTLP port
■ Power up/down high impedance for live insertion
■ External V
REF
pin for receiver threshold
■ BiCMOS technology for low power dissipation
■ Bushold data input s on A Port eliminates the need for
external pull-up resistors for unused inputs
■ LVTTL compatible Driver and Control inputs
■ Flow-through architecture optimizes PCB layout
■ Open drain on GTLP to support wired-or connection
■ A-Port source/sink −24 mA/+24 mA
■ B-Port sink capability +50 mA
■ D-type flip-flop, latch and transparent data paths
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Order Number Package Number Package Description
GTLP18T612MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JE DEC MO-118, 0.300” Wide
GTLP18T612MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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GTLP18T612
Pin Descriptions Connection Diagram
Functional Description
The GTLP18T612 is an 18 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation
for the data path. Data flow in ea ch direction is c ontrolled by the clock enables (CEAB
and CEBA), latch enables ( LEAB
and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB
and OEBA). The clock enables (CEAB and CEBA) and
the output enables (OEAB
and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively.
For A-to-B data flow, when CEAB
is LOW, the device operates o n the LOW-to-HIGH transition of C LKAB for the flip-flop
and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB
is LOW and LEAB is LOW the A data is
latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When
OEAB
is LOW the outputs are active. When OEAB is HIGH the outputs ar e HIGH impedance . The data flow of B-to -A is
similar except that CEBA
, OEBA, LEBA, and CLKBA are used.
Pin Names Description
OEAB
A-to-B Output Enable
(Active LOW) (LVTTL Lev el)
OEBA
B-to-A Output Enable
(Active LOW) (LVTTL Lev el)
CEAB
A-to-B Clock/LE Enable
(Active LOW) (LVTTL Lev el)
CEBA
B-to-A Clock/LE Enable
(Active LOW) (LVTTL Lev el)
LEAB A-to-B Latch Enable
(Transparent HIGH) (LVTTL Level)
LEBA B-to-A Latch Enable
(Transparent HIGH) (LVTTL Level)
V
REF
GTLP Input Threshold
Reference Voltage
CLKAB A-to-B Clock (LVTT L Level)
CLKBA B-to-A Clock (LVTT L Level)
A1–A18 A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B1–B18 B-to-A Data Inputs or
A-to-B Open Drain Outputs
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GTLP18T612
Truth Table (Note 1)
Note 1: A-to-B data flow is s how n. B-to-A data flow is si m ilar but uses OEBA, LEBA , CL KBA, and CEBA.
Note 2: Output level bef ore the indicated stea dy s ta t e input conditions were es t ablished, provided that C LKAB was HIGH before LEAB went LOW.
Note 3: Output level before the indicated steady-state input conditions were established.
Logic Diagram
Inputs Output
B
Mode
CEAB
OEAB LEAB CLKAB A
X H X X X Z Latched
LLLH or LXB
0
(Note 2) storage
LLLH or LXB
0
(Note 3) of A data
X L H X L L Transparent
XLHXHH
LLL↑ L L Clocked
LLL↑ H H storage
of A data
HLLXXB
0
(Note 3) Clock inhibit
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