Fairchild Semiconductor DM74LS194AN, DM74LS194AMX, DM74LS194AM Datasheet
© 2000 Fairchild Semiconductor Corporation DS006407 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS194A 4-Bit Bidirectional Universal Shift Register
DM74LS194A
4-Bit Bidirectional Universal Shift Register
General Description
This bidirectional shift register is designed to incorp orate
virtually all of the features a system designer may want in a
shift register; they feature p arallel inputs, parallel outputs,
right-shift and left-shi ft serial inputs, operating-mode-co ntrol inputs, and a dire ct overriding clear lin e. The register
has four distinct modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction Q
A
toward QD)
Shift left (in the direction Q
D
toward QA)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of da ta and taking both mode control inputs,
S0 and S1, HIGH. T he data is load ed into the associated
flip-flops and appear at the outputs after the positive transition of the clock in put. During loading, seri al data flow is
inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is HIGH a nd S1 is LOW.
Serial data for this mode is entered at the shift-right data
input. When S0 is LOW and S1 is HIGH, data shifts left
synchronously and new data is entered at the shift-left
serial input.
Clocking of the flip-flop is inhibited when both mode control
inputs are LOW.
Features
■ Parallel inputs and outputs
■ Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
■ Positive edge-triggered clocking
■ Direct overriding clear
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Order Number Package Number Package Description
DM74LS194AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS194AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
DM74LS194A
Function Table
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH lev el
a, b, c, d = The level of steady state input at inputs A, B, C or D, re s pec t iv ely.
Q
A0
, QB0, QC0, QD0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established.
Q
An
, QBn, QCn, QDn = The level of QA, QB, QC, respectively, before the most -recent ↑ transition of the clock.
Logic Diagram
Inputs Outputs
Clear
Mode
Clock
Serial Parallel
Q
AQBQCQD
S1 S0 Left Right A B C D
L X X X X X XXXX L L L L
H X X L X X XXXXQ
A0QB0QC0QD0
HHH↑ XXabcdabcd
HLH↑ X H XXXX H Q
AnQBnQCn
HLH↑ X L XXXX L QAnQBnQ
Cn
HHL ↑ H X XXXXQBnQCnQ
Dn
H
HHL ↑ L X XXXXQ
BnQCnQDn
L
H L L X X X XXXXQ
A0QB0QC0QD0
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