Fairchild Semiconductor DM74LS191M, DM74LS191N, DM74LS191MX Datasheet

August 1986
Revised February 1999

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

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DM74LS191
Synchronous 4-Bit Up/Down Counter with Mode Control

General Description

The DM74LS191 circ uit is a synchronous, reversible, up/
down counter. Synchronous operation is provided by hav­ing all flip-flops clocked simultaneou sly, so that the outputs
change simultaneously when so instructed by the steer ing
logic. This mode of operation eliminates the out put count­ing spikes normally associat ed with asynchronous (ripple
clock) counters.

The outputs of the four master-sl ave flip-flops are tr igg er ed
on a LOW-to-HIGH level transition of the clock input , if the
enable input is LOW. A HIGH at the enable input inhibits
counting. Level changes at either the enable input or the
down/up input should be made only when the clock input is
HIGH. The direction of the co unt is determined by the level
of the down/up input. When LOW, the counter counts up
and when HIGH, it counts down.

The counter is fully programmable; that is, the ou tpu ts m ay
be preset to either level by placing a LOW on the load input
and entering the desired data at the data inputs. The output
will change independent of the level of the clock input. This
feature allows the counters to be u sed as modu lo-N divid­ers by simply modifying the coun t length with the preset
inputs.

The clock, down/up, and load inpu ts are buffered to lower
the drive requirement; which significantly reduces the num­ber of clock drivers, etc., required for long parallel words.

Two outputs have been made available to perform the cas­cading function: ripple clock and maximum/minimum count.
The latter output pro duces a hig h-level output pulse w ith a
duration approximately equal to one c omplete cycle of the
clock when the counter overflows or un der flows. The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding co unter if parallel clocking
is used, or to the clock input if parall el enabling is used.
The maximum/minimum count output can be used to
accomplish look-ahead for high-speed operation.

Features

■ Counts binary

■ Single down/up count control line

■ Count enable control input

■ Ripple clock output for cascading

■ Asynchronously presettable with load control

■ Parallel outputs

■ Cascadable for n-bit applications

■ Average propagation delay 20 ns

■ Typical clock frequency 25 MHz

■ Typical power dissipation 100 mW

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number Package Number Package Description

DM74LS191M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
DM74LS191N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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DM74LS191

Connection Diagram

Timing Diagram