Fairchild Semiconductor DM74LS181N, DM74LS181CW Datasheet

© 2000 Fairchild Semiconductor Corporation DS009821 www.fairchildsemi.com

October 1988
Revised April 2000

DM74LS181 4-Bit Arithmetic Logic Unit

DM74LS181
4-Bit Arithmetic Logic Unit

General Description

The DM74LS181 is a 4-bit Arithmetic Logic Unit (ALU)
which can perform all the possible 16 logic o perations on
two variables and a variety of arithmetic operations.

Features

■ Provides 16 arithmetic operat ions: add, subtract, com­pare, double, plus twelve other arithmetic operations

■ Provides all 16 logic operations of two variables:
exclusive-OR, compare, AND, NAND, OR, NOR, plus
ten other logic operations

■ Full lookahead for high speed arithmetic operation on
long words

Ordering Code:

Logic Symbols

Active High Operands

Active Low Operands

VCC = Pin 24
GND = Pin 12

Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

DM74LS181N N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide

Pin Names Description

A

0–A3 Operand In puts (Active LOW)

B

0–B3 Operand In puts (Active LOW)
S0–S3 Function Select Inputs
M Mode Control Input
C

n

Carry Input

F

0–F3 Function Outputs (Active LOW)
A = B Comparator Output
G

Carry Generate Output (Active LOW)

P

Carry Propagate Output (Active LOW)

C

n+4

Carry Output

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DM74LS181

Functional Description

The DM74LS181 is a 4- bit high speed parallel Arithm etic
Logic Unit (ALU). Controlled by the four Fun ction Select

inputs (S0–S3) and the Mode Control input (M), it can per­form all the 16 possible logic operations or 16 different
arithmetic operations o n active HIGH or acti ve LOW oper­ands. The Function Table lists these operations

When the Mode Control input (M) is HIGH, all internal car­ries are inhibited and the device p erforms l ogic oper ations
on the individual bits as listed. When the Mode Control
input is LOW, the carries are enabled and the dev ice per­forms arithmetic operations on the two 4-bit words. The
device incorporates full internal carry l ookahead and pro­vides for either ripple carry between devices using the C

n+4

output, or for carry lookahead between packages using the
signals P

(Carry Propagate) and G (Carry Generate). In the

ADD mode, P

indicates that F is 15 or more, while G indi-

cates that F

is 16 or more. In the SUBTRACT mode, P indi-

cates that F

is zero or less, while G indicates that F is less

than zero. P

and G are not affected by carry in. When
speed requiremen ts are not stringent, it can be used in a
simple ripple carry mode by connecting the Carry output
(C

n+4

) signal to the Carry i nput (Cn) of the next unit. Fo r

high speed operation the device is used in conjunction with
the 9342 or 93 S42 carry lookah ead circuit. One carry loo ­kahead package is required for each group of four

DM74LS181 devices. Carry looka head can be provid ed at
various levels and offers high speed capability over
extremely long word lengths.

The A = B output from the device goes HIGH w hen all four
F

outputs are HIGH and can be used to indicate logic
equivalence over four bits when the uni t is in the subtract
mode. The A = B output is open-collector and can be wired­AND with other A = B outputs to give a comparison for
more than four bits. The A = B signal can also be used with
the C

n+4

signal to indicate A > B and A < B.

The Function Table lists the arithmetic ope rations that are
performed without a carry in. An incoming carry adds a one
to each operation . Thus, select code LHHL gene rates A
minus B minus 1 (2s complem ent no tation) witho ut a ca rry
in and generates A minus B when a carry is applied.
Because subtraction is actual ly performed by co mplemen­tary addition (1s complement), a carry out means borrow;
thus a carry is gener ated when there is no underflow a nd
no carry is generated when there is underflow. As indi­cated, this device can be used with either active LOW
inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outp uts. For either case the
table lists the operatio ns that are performed to the oper­ands labeled inside the logic symbol.

Function Table

Note 1: Each bit is shifted to the next most significant position.
Note 2: Arithmetic operations expresse d in 2s complement notation.

Mode Select Active LOW Operands Active HIGH Operands

Inputs & F

n

Outputs & Fn Outputs

Logic Arithmetic

(Note 2)

Logic Arithmetic

(Note 2)

S3 S2 S1 S0 (M = H) (M = L) (C

n

= L) (M = H) (M = L) (Cn = H)

LLLLA

A minus 1 A A

LLLHAB

AB minus 1 A + B A + B

LLHLA

+ B AB minus 1 A BA + B
L L H H Logic 1 minus 1 Logic 0 minus 1
LHLLA

+ B A plus (A + B)ABA plus AB
LHLHB AB plus (A + B)B (A + B) plus AB
LHHLA ⊕ B A minus B minus 1 A ⊕ B A minus B minus 1
LHHHA + B

A + B AB AB minus 1

HLLLA

B A plus (A + B) A + B A plus AB
HLLHA ⊕ B A plus B A

⊕ B A plus B

HLHLB AB

plus (A + B) B (A + B) plus AB
HLHHA + BA + B AB AB minus 1
H H L L Logic 0 A plus A (Note 1) Logic 1 A plus A (Note 1)
HHLHAB

AB plus A A + B (A + B) plus A

H H H L AB AB

minus A A + B(A + B) plus A
HHHHAA AA minus 1

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DM74LS181

Logic Diagram