Fairchild Semiconductor 74ACT74SJX, 74ACT74SJ, 74ACT74SCX, 74ACT74SC, 74ACT74PC Datasheet

© 1999 Fairchild Semiconductor Corporation DS009920 www.fairchildsemi.com

November 1988
Revised November 1999

74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

74AC74 • 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set in puts and complement ary (Q, Q

) outputs.
Information at the input is tra nsferre d to the output s on t he
positive edge of the clock puls e. Clo ck tri ggering occurs at
a voltage level of the clock pulse and is no t directly related
to the transition ti me of the positiv e-going pulse. After the
Clock Pulse input t hreshold vol tage has be en passed, t he
Data input is locked out and information present will not be
transferred to the outputs u ntil the next rising edg e of the
Clock Pulse input.

Asynchronous Inputs:

LOW input to S

D

(Set) sets Q to HIGH level

LOW input to C

D

(Clear) sets Q to LOW level

Clear and Set are independent of clock
Simultaneous LOW on C

D

and SD makes both Q and Q

HIGH

Features

■ ICC reduced by 50%

■ Output source/sink 24 mA

■ ACT74 has TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Connection Diagram Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74AC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

D

1

, D

2

Data Inputs

CP

1

, CP

2

Clock Pulse Inputs

C

D1

, C

D2

Direct Clear Inputs

S

D1

, S

D2

Direct Set Inputs

Q

1

, Q1, Q2, Q

2

Outputs

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74AC74 • 74ACT74

Logic Symbols

IEEE/IEC

Truth Table

(Each Half)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial



= LOW-to-HIGH Clock Transition

Q

0

(Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Outputs

S

DCD

CP D Q Q

LHXXHL
HLXXLH
LLXXHH
HH



HH L

HH



LLH

HHLXQ

0

Q

0

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74AC74 • 74ACT74

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute max imum ratings are those values beyond w hich damage

to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specif ic at ions.

DC Electrical Characteristics for AC

Note 2: All outputs loaded; thres holds on input associate d w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I

IN

and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source

or Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

J

)

PDIP 140°C

Supply Voltage (V

CC

)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V

Input Voltage (V

I

)0V to V

CC

Output Voltage (VO)0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)

AC Devices
V

IN

from 30% to 70% of V

CC

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

ACT Devices
V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

TA = +25°C

T

A

= −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH 3.0 1.5 2.1 2.1 V

OUT

= 0.1V
Level Input 4.5 2.25 3.15 3.15 V or VCC − 0.1V
Voltage 5.5 2.75 3.85 3.85

V

IL

Maximum LOW 3.0 1.5 0.9 0.9 V

OUT

= 0.1V
Level Input 4.5 2.25 1.35 1.35 V or VCC − 0.1V
Voltage 5.5 2.75 1.65 1.65

V

OH

Minimum HIGH 3.0 2.99 2.9 2.9
Level Output 4.5 4.49 4 .4 4.4 V I

OUT

= −50 µA

Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

IH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V I

OH

= −24 m

5.5 4.86 4.76 I

OH

= −24 m (Note 2)

V

OL

Maximum LOW 3.0 0.002 0.1 0.1
Level Output 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

I

IN

(Note 4) Maximum InputLeakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent

5.5 2.0 20.0 µA

VIN = VCC

(Note 4) Supply Current or GND