Fairchild Semiconductor 74ACT652SPC, 74ACT652SCX, 74ACT652SC, 74ACT652MTCX, 74ACT652MTC Datasheet
© 2000 Fairchild Semiconductor Corporation DS500310 www.fairchildsemi.com
August 1999
Revised September 2000
74ACT652 Transceiver/Register
74ACT652
Transceiver/Register
General Description
The ACT652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers a s the appropr iate clock pin g oes to the
HIGH logic level. Output Enable pins (OEAB, OEBA
) are
provided to control the transceiver function.
Features
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACT652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT652MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
A
0–A7
, B0–B7A and B Inputs/3-STATE Outputs
CPAB, CPBA Clock Inputs
SAB, SBA Select Inputs
OEAB, OEBA
Output Enable Inputs
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74ACT652
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clo c k Transi ti on
Note 1: The data output fu nction s may b e enable d or di sabled b y variou s signa ls at O EAB or O EBA
inputs. Data input functions are always enabled, i.e.,
data at the bus pins w ill be stored on every LOW-to -H I GH t ransition on the clock inp ut s.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Inputs/Outputs (Note 1) Operating Mode
OEAB OEBA
CPAB CPBA SAB SBA A0 thru A7B0 thru B
7
L H H or L H or L X X Input Input Isolation
LH
X X Store A and B Data
XH
H or L X X Input Not Specified Store A, Hold B
HH
X X Input Outp ut Store A in Both Registers
LXH or L
X X Not Specified Input Hold A, Store B
LL
X X Output Input Store B in Both Registers
L L X X X L Output Input Real-Time B Data to A Bus
L L X H or L X H Store B Data to A Bus
H H X X L X Input Output Real-Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
Stored B Data to A Bus
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74ACT652
Functional Description
In the transceiver mode , data present a t the HIGH impe dance port may be sto red in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 de monstr ate the fo ur funda mental bus-management func tions that can be perfor med with
the Octal bus transceivers and receivers.
Data on the A or B data bus, or both can be stored in the
internal D-type flip -flop by LOW to HIGH tr ansitions at the
appropriate Clock Inp uts (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer m od e, it is a lso po ssibl e to sto re d ata
without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA
. In this configuration
each Output reinforces its Input. Thu s when all other data
sources to the two sets of bus lin es are in a HIGH imp edance state, each set of bus lines will remain at its last state.
FIGURE 1.
Note A: Real-Time Note B: Real-Time
Transfer Bus B to Bus A Transfer Bus A to Bus B
OEAB OEBA
CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA
LLXXXL HHXXLX
Note C: Storage Note D: Transfer Storage
Data to A or B
OEAB OEBA
CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA
XH
X X X H L H or L H or L H H
LXX
XX
LH
XX
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