Fairchild Semiconductor 100371SCX, 100371SC, 100371QIX, 100371QI, 100371QCX Datasheet

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© 2000 Fairchild Semiconductor Corporation DS010148 www.fairchildsemi.com
October 1989 Revised August 2000
100371 Low Power Tri p le 4-Input Multiplexer with Enable
100371 Low Power Triple 4-Input Multiplexer with Enable
General Description
The 100371 contains three 4-input multiplexers which share a common decoder (inputs S
0
and S1). Output buffer
gates provide true and complement outputs. A HIGH on the Enable input (E
) forces all true outputs L OW (see Truth
Table). All inputs have 50 k
pull-down resistors.
Features
35% power reduction of the 100171
2000V ESD protection
Pin/function compatible with 100171
Voltage compensated operating range
= −4.2V to 5.7V
Available to industrial grade temperature range
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Order Number Package Number Package Description
100371SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100371PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 10371QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 10371QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
40°C to +85°C)
Pin Names Description
I
0x–I3x
Data Inputs
S
0
, S1Select Inputs E
Enable Input (Active LOW)
Z
a–Zc
Data Outputs
Z
a–Zc
Complementary Data Outputs
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100371
Truth Table
H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care
Logic Diagram
Inputs Outputs
E
S
0
S
1
Z
n
LLLI
0x
LHLI
1x
LLHI
2x
LHHI
3x
HXXL
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100371
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: The Absolute Maximum Ratings are those value s beyond which
the safety of the dev ice cannot b e guaranteed . The device sh ould not be operated at these limit s. The parametric values defi ned in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The Recomm ended O peratin g Cond itions table will defin e the condition s for actual device operation.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version DC Electrical Characteristics
(Note 3)
V
EE
= 4.2V to 5.7V, VCC = V
CCA
= GND, T
C
= 0°C to +85°C
Note 3: The specified limits represent the worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under worst case conditions.
DIP AC Electrical Characteristics
V
EE
= 4.2V to 5.7V, VCC = V
CCA
= GND
Note 4: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s witching.
Storage Temperature (T
STG
) 65°C to +150°C
Maximum Junction Temperature (T
J
) +150°C
V
EE
Pin Potential to Ground Pin 7.0V to +0.5V
Input Voltage (DC) V
EE
to +0.5V
Output current (DC Output HIGH)
50 mA
ESD (Note 2)
2000V
Case Temperature (T
C
)
Commercial 0
°C to +85°C
Industrial
40°C to +85°C
Supply Voltage (V
EE
) 5.7V to 4.2V
Symbol Parameter Min Typ Max Units Conditions
V
OH
Output HIGH Voltage −1025 −955 −870 mV VIN =VIH (Max) Loading with
V
OL
Output LOW Voltage −1830 −1705 1620 mV or VIL (Min) 50 to −2.0V
V
OHC
Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with
V
OLC
Output LOW Voltage 1610 mV or VIL (Max) 50 to −2.0V
V
IH
Input HIGH Voltage −1165 870 mV Guaranteed HIGH Signal
for All Inputs
V
IL
Input LOW Voltage −1830 1475 mV Guaranteed LOW Signal
for All Inputs
I
IL
Input LOW Current 0.50 µAVIN = VIL (Min)
I
IH
Input HIGH Current
I
0X–I3X
340 µAVIN = VIH (Max)
S0, S1, E 300
I
EE
Power Supply Current −75 39 mA Inputs Open
Symbol Parameter
TC = 0°CT
C
= +25°CT
C
= +85°C
Units Conditions
Min Max Min Max Min Max
t
PLH
Propagation Delay
0.45 1.50 0.45 1.50 0.45 1.60 ns
t
PHL
I0x–I3x to Output
t
PLH
Propagation Delay
0.90 2.40 0.90 2.40 1.00 2.60 ns
Figures 1, 2
t
PHL
S0, S1 to Output (Note 4)
t
PLH
Propagation Delay
0.65 2.30 0.65 2.30 0.75 2.40 ns
t
PHL
E to Output
t
TLH
Transition Time
0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1, 2
t
THL
20% to 80%, 80% to 20%
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