Fairchild Semiconductor 100364QIX, 100364QI, 100364QCX, 100364QC, 100364PC Datasheet

© 2000 Fairchild Semiconductor Corporation DS010265 www.fairchildsemi.com

February 1990
Revised August 2000

100364 Low Power 16-Input Multiplexer

100364
Low Power 16-Input Multiplexer

General Description

The 100364 is a 16-inpu t multiplexer. Data paths ar e con­trolled by four Select lines (S

0–S3

). Their decoding is

shown in the Truth Table. Output data polarity is the same
as the selected input data. All inputs have 50 k

Ω pull-down

resistors.

Features

■ 35% power reduction of the 100164

■ 2000V ESD protection

■ Pin/function compatible with 100164

■ Voltage compensated operating range

= −4.2V to −5.7V

■ Available to industrial grade temperature range

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP

28-Pin PLCC

Order Number Package Number Package Description

100364PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100364QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100364QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

I

0–I15

Data Inputs

S

0–S3

Select Inputs

Z Data Output

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100364

Truth Table

H = HIGH Voltage Level
L = LOW Voltage Level

Logic Diagram

Select Inputs Output

S

0

S

1

S

2

S

3

Z

LLLLI

0

HLLLI

1

LHLLI

2

HHL LI

3

LLHLI

4

HLHLI

5

LHHLI

6

HHHLI

7

LLLHI

8

HLLHI

9

LHLHI

10

HHLHI

11

LLHHI

12

HLHHI

13

LHHHI

14

HHHHI

15

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100364

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version
DC Electrical Characteristics

(Note 3)

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

C

= 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operate under “worst case” conditions.

DIP AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

J

) +150°C

Pin Potential to Ground Pin (V

EE

) −7.0V to +0.5V

Input Voltage (DC) V

EE

to +0.5V

Output Current

(DC Output HIGH)

−50 mA

ESD (Note 2)

≥ 2000V

Case Temperature (T

C

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

EE

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

V

OH

Output HIGH Voltage −1025 −955 −870 mV VIN = VIH (Max) Loading with

V

OL

Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V

V

OHC

Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with

V

OLC

Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V

V

IH

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

V

IL

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

I

IL

Input LOW Current 0.5 µAVIN = VIL (Min)

I

IH

Input HIGH Current 300 µAVIN = VIH (Max)

I

EE

Power Supply Current −89 −45 mA Inputs OPEN

Symbol Parameter

TC = 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

0.90 2.00 0.90 2.00 0.90 2.10 ns

t

PHL

I0–I15 to Output

t

PLH

Propagation Delay

1.40 2.80 1.40 2.80 1.50 2.90 ns

t

PHL

S0, S1 to Output Figures 1, 2

t

PLH

Propagation Delay

1.00 2.20 1.00 2.20 1.10 2.40 ns

t

PHL

S2, S3 to Output

t

TLH

Transition Time

0.35 1.20 0.35 1.20 0.35 1.20 ns

t

THL

20% to 80%, 80% to 20%