Fairchild FAN54015UCX, FAN54015UCX Schematic [ru]

October 2013
FAN54015
SW
PGND
C
OUT
L1
VBAT
+
Battery
CSIN
R
SENSE
68m
1H
C
BAT
SYSTEM
LOAD
0.1F
1F
4.7F
SDA SCL
OTG/USB#
C
REG
1F
VREG
STAT
10F
DISABLE
C
BUS
C
MID
VBUS
PMID
All trademarks are the property of their respective owners.
FAN54015 USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Features
Fully Integrated, High-Efficiency Charger for Single-Cell
Li-Ion and Li-Polymer Battery Packs
Faster Charging than Linear Charge Voltage Accuracy: 0.5% at 25°C
1% from 0 to 125°C
5% Input Current Regulation Accuracy 5% Charge Current Regulation Accuracy 20 V Absolute Maximum Input Voltage 6 V Maximum Input Operating Voltage 1.45 A Maximum Charge Rate Programmable through High-Speed I
(3.4 Mb/s) with Fast Mode Plus Compatibility
C Interface
Input Current Fast-Charge / Termination Current Charger Voltage Termination Enable
3 MHz Synchronous Buck PWM Controller with Wide
Duty Cycle Range
Small Footprint 1 H External Inductor Safety Timer with Reset Control 1.8 V Regulated Output from VBUS for Auxiliary Circuits Dynamic Input Voltage Control Low Reverse Leakage to Prevent Battery Drain to VBUS 5 V, 500 mA Boost Mode for USB OTG for 3.0 V to
4.5 V Battery Input
Available in a 1.96 x 1.87 mm, 20-bump, 0.4 mm Pitch
WLCSP Package
Description
The FAN54015 combines a highly integrated switch-mode charger, to minimize single-cell Lithium-ion (Li-ion) charging time from a USB power source, and a boost regulator to power a USB peripheral from the battery.
The charging parameters and operating modes are programmable through an I2C Interface that operates up to
3.4 Mbps. The charger and boost regulator circuits switch at 3 MHz to minimize the size of external passive components.
The FAN54015 provides battery charging in three phases: conditioning, constant current and constant voltage.
To ensure USB compliance and minimize charging time, the input current limit can be changed through the I2C by the host processor. Charge termination is determined by a programmable minimum current level. A safety timer with reset control provides a safety backup for the I2C host. Charge status is reported to the host through the I2C port.
The integrated circuit (IC) automatically restarts the charge cycle when the battery falls below an internal threshold. If the input source is removed, the IC enters a high-impedance mode, preventing leakage from the battery to the input. Charge current is reduced when the die temperature reaches 120°C, protecting the device and PCB from damage.
The FAN54015 can operate as a boost regulator on command from the system. The boost regulator includes a soft-start that limits inrush current from the battery and uses the same external components used for charging the battery.
Applications
Cell Phones, Smart Phones, PDAs Tablet, Portable Media Players Gaming Device, Digital Cameras
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 • Rev. 1.0.2
Figure 1. Typical Application
Part Number
Temperature
Range
Package
PN Bits:
IC_INFO[4:2]
Packing
Method
FAN54015UCX
-40 to 85°C
20-Bump, Wafer-Level Chip-Scale Package (WLCSP),
0.4 mm Pitch, Estimated Size: 1.96 x 1.87 mm
101
Tape and
Reel
FAN54015BUCX
(1)
Part Number
Slave Address
Automatic
Charge
Special
Charger
(2)
Safety Limits
Battery Absent
Behavior
E2 Pin
VREG
(E3 Pin)
FAN54015UCX
1101010
Yes
Yes
Yes
ON
DISABLE
1.8 V
PWM
MODULATOR
PMID
SW
PGND
PMID
L1
VBAT
C
MID
+
Battery
CSIN
1H
4.7F
C
BAT
SYSTEM
LOAD
VREF
SDA SCL
OTG/USB#
VCC
VBUS
C
BUS
1F
STAT
I2C
INTERFACE
LOGIC
AND
CONTROL
PMID
OSC
30mA
C
OUT
0.1F
R
SENSE
Q3
CHARGE
PUMP
VBUS
OVP
I_IN
CONTROL
VREG
C
REG
1F
DAC
DISABLE
1.8V / PMID REG
Q2
Q1B
Q1A
Q1
Component
Description
Vendor
Parameter
Typ.
Unit
L1
1 H ±20%, 1.6 A, DCR=55 m, 2520
Murata: LQM2HPN1R0
L
1.0
H
1 H ±30%, 1.4 A, DCR=85 m, 2016
Murata: LQM2MPN1R0
C
BAT
10 F, 20%, 6.3 V, X5R, 0603
Murata: GRM188R60J106M
TDK: C1608X5R0J106M
C
10
F
C
MID
4.7 F, 10%, 6.3 V, X5R, 0603
Murata: GRM188R60J475K
TDK: C1608X5R0J475K
C
(3)
4.7
F
C
BUS
1.0 F, 10%, 25 V, X5R, 0603
Murata GRM188R61E105K
TDK:C1608X5R1E105M
C
1.0
F
PMID
Q1A
Q1B
Greater than V
BAT
ON
OFF
Less than V
BAT
OFF
ON
Ordering Information
Note:
1. FAN54015BUCX includes backside lamination.
Table 1. Feature Summary
Note:
2. A “special charger is a current-limited charger that is not a USB compliant source.
Block Diagram
Table 2. Recommended External Components
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 2
Note:
3. A 6.3 V rating is sufficient for C
because PMID is protected from over-voltage surges on VBUS by Q3 (Figure 2).
MID
Figure 2. IC and System Block Diagram
Top View
Bottom View
Figure 3. WLCSP-20 Pin Assignments
Pin #
Name
Description
A1, A2
VBUS
Charger Input Voltage and USB-OTG output voltage. Bypass with a 1 F capacitor to PGND.
A3
NC
No Connect. No external connection is made between this pin and the IC’s internal circuitry.
A4
SCL
I2C Interface Serial Clock. This pin should not be left floating.
B1-B3
PMID
Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense, and high-voltage input switch. Bypass with a minimum of 4.7 F, 6.3 V capacitor to PGND.
B4
SDA
I2C Interface Serial Data. This pin should not be left floating.
C1-C3
SW
Switching Node. Connect to output inductor.
C4
STAT
Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charging.
D1-D3
PGND
Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom of C
MID
should be as short as possible.
D4
OTG
On-The-Go. Enables boost regulator in conjunction with OTG_EN and OTG_PL bits (see Table 16). On VBUS Power-On Reset (POR), this pin sets the input current limit for t
15MIN
charging.
E1
CSIN
Current-Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to sense current into the battery. Bypass this pin with a 0.1 F capacitor to PGND.
E2
DISABLE
Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is controlled by the I2C registers. When this pin is HIGH, the 15-minute timer is reset. This pin does not affect the 32-second timer.
E3
VREG
Regulator Output. Connect to a 1 F capacitor to PGND. This pin can supply up to 2mA of DC load current. The output voltage is PMID, which is limited to 1.8 V.
E4
VBAT
Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 0.1 F capacitor to PGND if the battery is connected through long leads.
C1
B1
A1 A2
C3
B3
A3
C2
D1 D3D2
B2
C4
B4
A4
D4
E1 E3E2 E4
C1
B1
A1
C3
B3
A3 A2
C2
D1D3 D2
B2
C4
B4
A4
D4
E1E3 E2E4
Pin Configuration
Pin Definitions
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 3
Symbol
Parameter
Min.
Max.
Unit
V
BUS
VBUS Voltage Continuous
–1.4
20.0
V
Pulsed, 100 ms Maximum Non-Repetitive
–2.0
V
STAT
STAT Voltage
–0.3
16.0
V
VI
PMID Voltage
7.0
V
SW, CSIN, VBAT, DISABLE Voltage
–0.3
7.0
VO
Voltage on Other Pins
–0.3
6.5
(4)
V
dt
dV
BUS
Maximum V
BUS
Slope above 5.5 V when Boost or Charger are Active
4
V/s
ESD
Electrostatic Discharge Protection Level
Human Body Model per JESD22-A114
2000
V
Charged Device Model per JESD22-C101
500
TJ
Junction Temperature
–40
+150
°C
T
STG
Storage Temperature
–65
+150
°C
TL
Lead Soldering Temperature, 10 Seconds
+260
°C
Symbol
Parameter
Min.
Max.
Unit
V
BUS
Supply Voltage
4 6 V
V
BAT(MAX)
Maximum Battery Voltage when Boost enabled
4.5
V
dt
dV
BUS
Negative VBUS Slew Rate during VBUS Short Circuit, C
MID
< 4.7 F (see VBUS Short While Charging)
TA < 60°C
4
V/s
TA > 60°C
2 TA
Ambient Temperature
–30
+85
°C
TJ
Junction Temperature (see Thermal Regulation and Protection section)
–30
+120
°C
Symbol
Parameter
Typical
Unit
JA
Junction-to-Ambient Thermal Resistance
60
°C/W
JB
Junction-to-PCB Thermal Resistance
20
°C/W
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Note:
4. Lesser of 6.5 V or VI + 0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer 2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature T
at a given ambient temperature TA. For measured data, see Table 11.
J(max)
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 4
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; V
BUS
=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power Supplies
I
VBUS
VBUS Current
V
BUS
> V
BUS(min)
, PWM Switching
10 mA
V
BUS
> V
BUS(min)
; PWM Enabled, Not Switching (Battery OVP Condition); I_IN Setting=100 mA
2.5 mA
0°C < TJ < 85°C, HZ_MODE=1 V
BAT
< V
LOWV
, 32S Mode
63
90
A
I
LKG
VBAT to VBUS Leakage Current
0°C < TJ < 85°C, HZ_MODE=1, V
BAT
=4.2 V, V
BUS
=0 V
0.2
5.0
A
I
BAT
Battery Discharge Current in High­Impedance Mode
0°C < TJ < 85°C, HZ_MODE=1, V
BAT
=4.2 V
20
A
DISABLE=1, 0°C < TJ < 85°C, V
BAT
=4.2 V
10
Charger Voltage Regulation
V
OREG
Charge Voltage Range
3.5 4.4
V Charge Voltage Accuracy TA=25°C
–0.5%
+0.5%
TJ=0 to 125°C
–1%
+1%
Charging Current Regulation
I
OCHRG
Output Charge Current Range
V
LOWV
< V
BAT
< V
OREG
, R
SENSE
=68 m
550
1450
mA
Charge Current Accuracy Across R
SENSE
20 mV ≤ V
IREG
40 mV
92
97
102
%
V
IREG
> 40 mV
94
97
100
%
Weak Battery Detection
V
LOWV
Weak Battery Threshold Range
3.4 3.7
V
Weak Battery Threshold Accuracy
–5 +5
%
Weak Battery Deglitch Time
Rising Voltage
30 ms
Logic Levels: DISABLE, SDA, SCL, OTG
VIH
High-Level Input Voltage
1.05 V VIL
Low-Level Input Voltage
0.4
V
IIN
Input Bias Current
Input Tied to GND or VIN
0.01
1.00
A
Charge Termination Detection
I
(TERM)
Termination Current Range
V
BAT
> V
OREG
– V
RCH
, R
SENSE
=68 m
50 400
mA
Termination Current Accuracy [V
CSIN
– V
BAT
] from 3 mV to 20 mV
–25 +25
% [V
CSIN
– V
BAT
] from 20 mV to 40 mV
–5 +5
Termination Current Deglitch Time
2 mV Overdrive
30 ms
1.8V Linear Regulator
V
REG
1.8V Regulator Output
I
REG
from 0 to 2 mA
1.7
1.8
1.9
V
Input Power Source Detection
V
IN(MIN)1
VBUS Input Voltage Rising
To Initiate and Pass VBUS Validation
4.29
4.42
V
V
IN(MIN)2
Minimum VBUS During Charge
During Charging
3.71
3.94
V
t
VBUS_VALID
VBUS Validation Time
30 ms
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 5
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; V
BUS
=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Special Charger (V
BUS
)
VSP
Special Charger Setpoint Accuracy
–3 +3
%
Input Current Limit
I
INLIM
Input Current Limit Threshold IIN Set to 100 mA
88
93
98
mA
IIN Set to 500 mA
450
475
500
V
REF
Bias Generator
V
REF
Bias Regulator Voltage
V
BUS
> V
IN(MIN)
or V
BAT
> V
BAT(MIN)
6.5
V
Short-Circuit Current Limit
20 mA
Battery Recharge Threshold
V
RCH
Recharge Threshold
Below V
(OREG)
100
120
150
mV
Deglitch Time
V
BAT
Falling Below V
RCH
Threshold
130 ms
STAT Output
V
STAT(OL)
STAT Output Low
I
STAT
=10 mA
0.4
V
I
STAT(OH)
STAT High Leakage Current
V
STAT
=5 V
1
A
Battery Detection
I
DETECT
Battery Detection Current before Charge Done (Sink Current)
(5)
Begins after Termination Detected and V
BAT
< V
OREG
–V
RCH
–0.80 mA
t
DETECT
Battery Detection Time
262 ms
Sleep Comparator
V
SLP
Sleep-Mode Entry Threshold, V
BUS
– V
BAT
2.3 V < V
BAT
< V
OREG
, V
BUS
Falling
0
0.04
0.10 V t
SLP_EXIT
Deglitch Time for VBUS Rising Above V
BAT
by V
SLP
Rising Voltage
30 ms
Power Switches (see Figure 2)
R
DS(ON)
Q3 On Resistance (VBUS to PMID)
I
IN(LIMIT)
=500 mA
180
250
mΩ
Q1 On Resistance (PMID to SW)
130
225
Q2 On Resistance (SW to GND)
150
225
Charger PWM Modulator
fSW
Oscillator Frequency
2.7
3.0
3.3
MHz
D
MAX
Maximum Duty Cycle
100
%
D
MIN
Minimum Duty Cycle
0 %
I
SYNC
Synchronous to Non-Synchronous Current Cut-Off Threshold
(6)
Low-Side MOSFET (Q2) Cycle-by­Cycle Current Limit
140 mA
Boost Mode Operation (OPA_MODE=1, HZ_MODE=0)
V
BOOST
Boost Output Voltage at VBUS
2.5 V < V
BAT
< 4.5 V, I
LOAD
from 0 to
200 mA
4.80
5.07
5.17
V
3.0 V < V
BAT
< 4.5 V, I
LOAD
from 0 to
500 mA
4.77
5.07
5.17
I
BAT(BOOST)
Boost Mode Quiescent Current
PFM Mode, V
BAT
=3.6 V, I
OUT
=0
140
300
A
I
LIMPK(BST)
Q2 Peak Current Limit
1272
1590
1908
mA
UVLO
BST
Minimum Battery Voltage for Boost Operation
While Boost Active
2.42
V
To Start Boost Regulator
2.58
2.70
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 6
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; V
BUS
=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VBUS Load Resistance
R
VBUS
VBUS to PGND Resistance Normal Operation
1500
k
Charger Validation
100
Protection and Timers
VBUS
OVP
VBUS Over-Voltage Shutdown
V
BUS
Rising
6.09
6.29
6.49
V
Hysteresis
V
BUS
Falling
100 mV
I
LIMPK(CHG)
Q1 Cycle-by-Cycle Peak Current Limit
Charge Mode
2.3
A
V
SHORT
Battery Short-Circuit Threshold
V
BAT
Rising
1.95
2.00
2.05
V
Hysteresis
V
BAT
Falling
100 mV
I
SHORT
Linear Charging Current
V
BAT
< V
SHORT
20
30
40
mA
T
SHUTDWN
Thermal Shutdown Threshold
(7)
TJ Rising
145
°C
Hysteresis
(7)
TJ Falling
10
TCF
Thermal Regulation Threshold
(7)
Charge Current Reduction Begins
120 °C
t
INT
Detection Interval
2.1 s
t
32S
32-Second Timer
(8)
Charger Enabled
20.5
25.2
28.0
s
Charger Disabled
18.0
25.2
34.0
t
15MIN
15-Minute Timer
15-Minute Mode
12.0
13.5
15.0
min
tLF
Low-Frequency Timer Accuracy
Charger Inactive
–25 25
%
Notes:
5. Negative current is current flowing from the battery to VBUS (discharging the battery).
6. Q2 always turns on for 60 ns, then turns off if current is below I
SYNC
.
7. Guaranteed by design; not tested in production.
8. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers.
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 7
I2C Timing Specifications
Guaranteed by design.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
f
SCL
SCL Clock Frequency
Standard Mode
100
kHz
Fast Mode
400
High-Speed Mode, CB < 100 pF
3400
High-Speed Mode, CB < 400 pF
1700
t
BUF
Bus-Free Time between STOP and START Conditions
Standard Mode
4.7
s
Fast Mode
1.3
t
HD;STA
START or Repeated START Hold Time Standard Mode
4
s
Fast Mode
600 ns
High-Speed Mode
160 ns
t
LOW
SCL LOW Period
Standard Mode
4.7
s
Fast Mode
1.3
s
High-Speed Mode, CB < 100 pF
160 ns
High-Speed Mode, CB < 400 pF
320 ns
t
HIGH
SCL HIGH Period
Standard Mode
4
s
Fast Mode
600 ns
High-Speed Mode, CB < 100 pF
60 ns
High-Speed Mode, CB < 400 pF
120 ns
t
SU;STA
Repeated START Setup Time Standard Mode
4.7
s
Fast Mode
600 ns
High-Speed Mode
160 ns
t
SU;DAT
Data Setup Time Standard Mode
250
ns
Fast Mode
100
High-Speed Mode
10
t
HD;DAT
Data Hold Time
Standard Mode
0 3.45
s
Fast Mode
0 900
ns
High-Speed Mode, CB < 100 pF
0 70
ns
High-Speed Mode, CB < 400 pF
0 150
ns
t
RCL
SCL Rise Time
Standard Mode
20+0.1CB
1000
ns
Fast Mode
20+0.1CB
300
High-Speed Mode, CB < 100 pF
10
80
High-Speed Mode, CB < 400 pF
20
160
t
FCL
SCL Fall Time
Standard Mode
20+0.1CB
300
ns
Fast Mode
20+0.1CB
300
High-Speed Mode, CB < 100 pF
10
40
High-Speed Mode, CB < 400 pF
20
80
t
RDA
t
RCL1
SDA Rise Time Rise Time of SCL after a Repeated START Condition and after ACK Bit
Standard Mode
20+0.1CB
1000
ns
Fast Mode
20+0.1CB
300
High-Speed Mode, CB < 100 pF
10
80
High-Speed Mode, CB < 400 pF
20
160
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 8
I2C Timing Specifications
Guaranteed by design.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
t
FDA
SDA Fall Time
Standard Mode
20+0.1CB
300
ns
Fast Mode
20+0.1CB
300
High-Speed Mode, CB < 100 pF
10
80
High-Speed Mode, CB < 400 pF
20
160
t
SU;STO
Stop Condition Setup Time Standard Mode
4
s
Fast Mode
600 ns
High-Speed Mode
160 ns
CB
Capacitive Load for SDA, SCL
400
pF
START
REPEATED
START
SCL
SDA
t
F
t
HD;STA
t
LOW
t
R
t
HD;DAT
t
HIGH
T
SU;DAT
t
SU;STA
t
HD;STO
t
BUF
START STOP
t
HD;STA
REPEATED START
SCLH
SDAH
t
FDA
t
LOW
t
RCL1
t
HD;DAT
t
HIGH
t
SU;STO
REPEATED
START
t
RDA
t
FCL
t
SU;DAT
t
RCL
STOP
= MCS Current Source Pull-up
= RP Resistor Pull-up
note A
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
t
HD;STA
t
SU;STA
Timing Diagrams
Figure 4. I2C Interface Timing for Fast and Slow Modes
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 9
Figure 5. I2C Interface Timing for High-Speed Mode
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, V
OREG
=4.2 V, V
BUS
=5.0 V, and TA=25°C.
Figure 6. Battery Charge Current vs. V
BUS
with
I
INLIM
=100 mA
Figure 7. Battery Charge Current vs. V
BUS
with
I
INLIM
=500 mA
Figure 8. Charger Efficiency, No I
INLIM
, I
OCHARGE
=1450 mA
Figure 9. Charger Efficiency vs. V
BUS
, I
INLIM
=500 mA
Figure 10. Auto-Charge Startup at VBUS Plug-in,
I
INLIM
=100 mA, OTG=1, V
BAT
=3.4 V
Figure 11. Auto-Charge Startup at VBUS Plug-in,
I
INLIM
=500 mA, OTG=1, V
BAT
=3.4 V
-
20
40
60
80
100
120
140
160
180
2.5 3 3.5 4 4.5
Battery Charge Current (mA)
Battery Voltage, VBAT (V)
5.5VBUS
5.0VBUS
4.5VBUS
-
100
200
300
400
500
600
700
800
900
2.5 3 3.5 4 4.5
Battery Charge Current (mA)
Battery Voltage, VBAT (V)
5.5VBUS
5.0VBUS
4.5VBUS
82%
85%
88%
91%
94%
97%
100 300 500 700 900 1100 1300 1500
Efficiency
Battery Charge Current (mA)
4.20VBAT, 4.5VBUS
4.20VBAT, 5.0VBUS
3.54VBAT, 5.0VBUS
3.54VBAT, 4.5VBUS
84%
86%
88%
90%
92%
94%
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
Efficiency
Battery Voltage, VBAT (V)
4.5VBUS
5.0VBUS
5.5VBUS
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 10
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, V
OREG
=4.2 V, V
BUS
=5.0 V, and TA=25°C.
Figure 12. AutoCharge Startup with 300mA Limited
Charger / Adaptor, I
INLIM
=500 mA, OTG=1, V
BAT
=3.4 V
Figure 13. Charger Startup with HZ_MODE Bit Reset,
I
INLIM
=500 mA, I
OCHARGE
=1050 mA, OREG=4.2 V, V
BAT
=3.6 V
Figure 14. Battery Removal / Insertion During Charging,
V
BAT
=3.9 V, I
OCHARGE
=1050 mA, No I
INLIM,
TE=0
Figure 15. Battery Removal / Insertion During Charging,
V
BAT
=3.9 V, I
OCHARGE
=1050 mA, No I
INLIM,
TE=1
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN54015 Rev. 1.0.2 11
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