Low On Resistance Quad SPDT Wide Bandwidth Video Switch
Page 13
2. 74LVX125
Low Voltage Quad Buffer with 3-STATE Outputs.
Page 14
3. A T49BVO40B
Page 15
Page 16
Page 17
4. LM1117
Page 18
5. FDS9435A
Single P-Channel Enhancement Mode Field Effect Transistor
SO-8 P-Channel enhancement mode power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide superior switching
performance. These devices are particularly suited for low voltage applications such as
notebook computer power management and other battery powered circuits where fast
switching, low in-line power loss, and resistance to transients are needed.
·Features
-5.3 A, -30 V, R
R
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used surface mount package.
= 0.045 Ω @ VGS = -10 V,
DS(ON)
= 0.075 Ω @ VGS = - 4.5 V.
DS(ON)
Page 19
6.FLI8125
The FLI8125 is a cost-effective, highly-integrated, mixed signal solution for TV and Digit al
Video applications. It incorporates a multi-standard video decoder, high-speed triple 8 -bit
Analog-to-Digital Converter(ADC),and front end switching. An integrated VBI Slicer adds
Closed Captioning(CC) and Teletext service support, and the built-in microprocessor enables
full system control without external devices.
Features
Page 20
·PInput
·Pin List
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground
Table 1: Analog Input Port
Pin Name No. I/O Description
VDD18_A
B
NC 159 No Connection. Leave this pin open for normal operation.
GND18_C 160 AG Analog Ground (1.8V Return) for C channel. Must be directly connected to the analog system ground plane
VDD18_C 16 1 AP Analog Power (1.8V) for C Channel. Must be bypassed with 0.1uF capacitor to the analog system ground
ADC_TES
T
AVDD_AD
C
AGND 164 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
AGND 165 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
SV1P 166 AI Positive analog sync input for channel 1.
GNDS 167 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
158 AP Analog Power (1.8V) for A & B Channels. Must be bypassed with 0.1uF capacitor to the analog system
162 O Analog Front End Test O/P. Leave this Pin open. Used for factory testing purpose only.
163 AP Analog Power (3.3V) for ADC. Must be bypassed with 0.1uF capacitor to the analog system ground plane.
ground plane.
on board.
plane.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
Page 21
A1P 168 AI Positive analog input ‘A’ for channel 1.
GNDS 169 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
B1P 170 AI Positive analog input ‘B’ for channel 1.
GNDS 171 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
C1P 172 AI Positive analog input ‘C’ for channel 1.
AVDD_A 173 AP Analog Power (3.3V) for ADC of Channel-A. Must be bypassed with 0.1uF capacitor to the analog system
AN 174 AI Nega t ive analog input ‘A’ for channels 1 through 4.
AGND 175 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
SV2P 176 AI Positive analog sync input for channel 2.
GNDS 177 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
A2P 178 AI Positive analog input ‘A’ for channel 2.
GNDS 179 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
B2P 180 AI Positive analog input ‘B’ for channel 2.
GNDS 181 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
C2P 182 AI Positive analog input ‘C’ for channel 2.
AVDD_B 183 AP Analog Power (3.3V) for ADC of Channel-B. Must be bypassed with 0.1uF capacitor to the analog system
BN 184 AI Nega t ive analog input ‘B’ for channels 1 through 4.
AGND 185 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
SV3P 186 AI Positive analog sync input for channel 3.
VDD18_AB 158 AP Analog Power (1.8V) for A & B Channels. Must be bypassed with 0.1uF capacitor to the analog system
GNDS 187 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
A3P 188 AI Positive analog input ‘A’ for channel 3.
GNDS 189 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
B3P 190 AI Positive analog input ‘B’ for channel 3.
GNDS 191 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
C3P 192 AI Positive an alog input ‘C’ for channel 3.
AVDD_C 193 AP Analog Power (3.3V) for ADC of Channel-C. Must be bypassed with 0.1uF capacitor to the analog system
CN 194 AI Negative analog input ‘C’ for channels 1 through 4.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
ground plane.
This acts as the return Path for the Sources connected to Channel-A Inputs. This has to be AC coupled
using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
ground plane.
This acts as the return Path for the Sources connected to Channel-B Inputs. This has to be AC coupled
using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
ground plane.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
ground plane.
This acts as the return Path for the Sources connected to Channel-C Inputs. This has to be AC coupled
using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board.
AGND 195 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
SV4P 196 AI Positive analog sync input for channel 4.
GNDS 197 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
A4P 198 AI Positive analog input ‘A’ for channel 4.
GNDS 199 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
B4P 200 AI Positive analog input ‘B’ for channel 4.
GNDS 201 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
C4P 202 AI Positive an alog input ‘C’ for channel 4.
AVDD_SC 203 AP Analog Power (3.3V) for ADC of SYNC Channel. Must be bypassed with 0.1uF capacitor to the analog
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
system ground plane.
Page 22
SVN 204 AI Negative analog sync input for channels 1 through 4.
VO_GND 205 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
VOUT2 206 AO Analog VOUT signal
VDD18_SC 207 AP Analog Power (1.8V) for SYNC Channel. Must be bypassed with 0.1uF capacitor to the analog system
GND18_SC 208 AG Analog Ground (1.8V Return) for SYNC channel. Must be directly connected to the analog system ground
This acts as the return Path for the Sources connected to SV Channel Inputs. This has to be AC coupled
using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board.
This is the Analog Video Output from the Decoder in the Composite Video format. This can be amplified
and be fed to any video display device.
ground plane.
plane on board.
Table 2: Low Bandwidth ADC Input Port
Pin Name No I/O Description
VDDA33_LBADC 1 AP Analog Power (3.3V) for Low Bandwidth ADC Block. Must be bypassed with 0.1uF capacitor.
LBADC_IN1 2 AI Low Bandwidth Analog Input-1. The Input signal connected to this Pin, must be bypassed with a 0.1uF
LBADC_IN2 3 AI Low Bandwidth Analog Input-2. The Input signal connected to this Pin, must be bypassed with a 0.1uF
LBADC_IN3 4 AI Low Bandwidth Analog Input-3. The Input signal connected to this Pin, must be bypassed with a 0.1uF
LBADC_IN4 5 AI Low Bandwidth Analog Input-4. The Input signal connected to this Pin, must be bypassed with a 0.1uF
LBADC_IN5 6 AI Low Bandwidth Analog Input-5. The Input signal connected to this Pin, must be bypassed with a 0.1uF
LBADC_IN6 7 AI Low Bandwidth Analog Input-6. The Input signal connected to this Pin, must be bypassed with
LBADC_RTN 8 AG This Pin provides the Return Path for LBADC inputs. Must be directly connected to the analog system
VSSA33_LBADC 9 AG Analog Ground for Low Bandwidth ADC Block. Must be directly connected to the analog system ground
capacitor and could be in the range of 0V to 3.3V (peak to peak).
capacitor and could be in the range of 0V to 3.3V (peak to peak).
capacitor and could be in the range of 0V to 3.3V (peak to peak).
capacitor and could be in the range of 0V to 3.3V (peak to peak).
capacitor and could be in the range of 0V to 3.3V (peak to peak).
ground plane on board.
plane on board.
Table 3: RCLK PLL Pins
Pin Name No I/O Description
GND_RPLL 11 DG Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground plane.
VDD_RPLL_18 12 DP Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to Ground Plane.
VBUFC_RPLL 13 O Test Output. Leave this Pin Open. This is reserved for Factory Testing Purpose.
AGND_RPLL 14 AG Analog ground for the Reference DDS PLL. Must be directly connected to the analog system ground
XTAL 15 AO Crystal oscillator output.
TCLK 16 AI Reference clock (TCLK) from the 14.3MHz crystal oscillator.
AVDD_RPLL_33 17 AP Analog Power (3.3V) for RCLK PLL. Must be bypassed with 0.1uF capacitor.
plane.
Table 4: Digital Video Input Port
Pin Name No I/O Description
VID_CLK_1 153 I Video port data clock input meant for Video Input – 1. Up to 75Mhz
VIDIN_HS 122 I When Video Input – 1 is in BT656 Mode, this Pin acts as Horizontal Sync Input for Video Input – 2.
VIDIN_VS 121 I When Video Input – 1 is in BT656 Mode, this Pin acts as Vertical Sync Input for Video Input – 2.
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Horizontal Sync Input for Video Input – 1.
OR this Pin acts as Horizontal Sync Input for 24 Bit Video Input
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Vertical Sync Input for Video Input – 1.
OR this Pin acts as Vertical Sync Input for 24 Bit Video Input
IO Input YUV data in 8-bit BT656 of Video Input – 1
[Bi-Directional, 5V-tolerant]
OR Input Y Data in case of 16 Bit Video Input (CCIR601) of Video Input – 1
OR Input Red Data in case of 24 Bit Video Input
VID_CLK2 118 I Video port data clock input meant for Video Input – 2. Up to 75Mhz
VID_DE/FLD 115 I Video Active Signal Input or the Field Signal Input from external Digital Video Source.
145
IO Input Pr / Pb Data in case of 16 Bit Video Input (CCIR601) of Video Input – 1
146
147
148
149
150
151
152
123
124
125
128
129
130
131
132
OR Input Green Data in case of 24 Bit Video Input
IO Input Blue Data in case of 24 Bit Video Input
OR Video Input – 2 in 8-bit with Embedded Sync / Separate Sync Sync in which case
VID_DATA_IN_16 acts as the LSB of the 8-bit Video input and VID_DATA_IN_23 acts as the MSB of
the 8-bit Video input.
[Input, 5V-tolerant]
Note: In case of Multiple Digital Video Input Sources, only one source could be in 8-Bit with
embedded Sync (BT656 mode) format.
Table 5: System Interface
Pin Name No I/O Description
RESETn 10 I Hardware Reset (active low) [Schmitt trigger, 5v-tolerant]
TEST 20 I For normal mode of operation connect this Pin to Ground.
GPIO15 21 IO This pin is available as a general-purpose input/output port. Also it is optionally programmable to
Connect to ground with 0.01uF (or larger) capacitor.
give out the external chip select signal meant for external SRAM. Refer to note below.
HSYNC2 22 I Horizontal Sync signal Input-2. Used when Analog RGB component signal carries separate
VSYNC2 23 I Vertical Sync signal Input-2. Used when Analog RGB component signal carries separate VSYNC
HOST_SCLK 24 IO Host input clock or 186 UART Data In or JTAG clock signal.
HOST_SDATA 25 IO Host input data or 186 UART Data Out or JTAG mode signal.
DDC_SCLK 26 IO
DDC_SDATA 27 IO
MSTR_SCLK 30 O Clock signal from Master Serial 2 Wire Interface Controller
MSTR_SDATA 31 IO Data signal meant for Master Serial 2 Wire interface Controller
TCK 34 IO This Pin accepts the Input Clock signal in case of Boundary Scan Mode.
TDI 35 IO This Pin accepts the Input Data signal in case of Boundary Scan Mode.
TMS 36 IO This Pin accepts the Input Test Mode Select signal in case of Boundary Scan Mode.
TRST 37 IO This Pin accepts the Boundary Scan Reset signal in case of Boundary Scan Mode.
GPIO6/IRin 38 IO Input from Infra Red Decoder can be connected to this Pin. When not used, this pin is available
GPIO7/IRQin 41 IO Input Interrupt Request signal can be connected to this Pin. When not used, this pin is available
GPIO8/IRQout 42 IO This Pin will give out the Interrupt Signal to interrupt external Micro. When not used, this pin is
GPIO9/SIPC_SCLK 43 IO This Pin accepts the Clock signal from External Serial 2 Wire interface Bus if FLI8125 is
GPIO10/SIPC_SDATA/
A18
GPIO11/PWM0 47 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use.
GPIO12/PWM1 48 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use.
GPIO13/PWM2 51 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use.
Pin Name No I/O Description
44 IO This Pin acts as the Data I/O signal when used with External Serial 2 Wire interface Bus if
HSYNC signal.
signal.
[Input, Schmitt trigger, 5V-tolerant]
[Bi-directional, Schmitt trigger, slew rate limited, 5V-tolerant]
DDC2Bi clock for VGA Port [internal 10KΩ pull-up resistor]
DDC2Bi data for VGA Port [internal 10KΩ pull-up resistor]
as General Purpose Input/output Port.
as General Purpose Input/output Port.
available as General Purpose Input/output Port.
programmed to be in Slave mode. When not used, this pin is available as General Purpose
Input/output Port.
FLI8125 is programmed to be in Slave mode. Or this Pin is programmable to give out Address #
18 from the Internal Micro when used with 512K External Memory. When not used, this pin is
available as General Purpose Input/output Port.
When not used, this pin is available as General Purpose Input/output Port.
When not used, this pin is available as General Purpose Input/output Port.
When not used, this pin is available as General Purpose Input/output Port.
Page 24
GPIO14/PWM3/
SCART16
TDO 55 O This Pin provides the Output Data in case of Boundary Scan Mode.
HSYNC1 156 I Horizontal Sync signal Input-1. Used when Analog RGB component signal carries separate
VSYNC1 157 I Vertical Sync signal Input-1. Used when Analog RGB component signal carries separate VSYNC
101 O Clock Output meant for External OSD Controller
102 O Horizontal Sync Output meant for External OSD Controller
XOSD_CLK 103 O Vertical Sync Output meant for External OSD Controller
XOSD_HS 104 O Field Signal Output meant for External OSD Controller
PD20/B4/GPIO0
PD21/B5/GPIO1
PD22/B6/GPIO2
PD23/B7/GPIO3
52 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use.
86
87
88
89
Or it can be programmed to sense the Fast Blank Input signal from a SCART I/P source. When
not used, this pin is available as General Purpose Input/output Port.
HSYNC signal.
signal.
IO T hese Pins provide the Panel Data as shown in the TTL Display Interface Table below. These are
available as General Purpose Input / Output Pins when not used as Panel Data.
Table 6: LVDS Display Interface
Pin Name No I/O Description
PBIAS 53 O Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
PPWR 54 O Panel Power Control [Tri-state output, 5V- tolerant]
AVDD_LV_33
VCO_LV
AVSS_LV
AVDD_OUT_LV_33
CH3P_LV_E
CH3N_LV_E
CLKP_LV_E
CLKN_LV_E
CH2P_LV_E
CH2N_LV_E
CH1P_LV_E
CH1N_LV_E
CH0P_LV_E
CH0N_LV_E
AVSS_OUT_LV
AVDD_OUT_LV_33
CH3P_LV_O
CH3N_LV_O
CLKP_LV_O
CLKN_LV_O
CH2P_LV_O
CH2N_LV_O
CH1P_LV_O
CH1N_LV_O
CH0P_LV_O
CH0N_LV_O
AVSS_OUT_LV
AVDD_OUT_LV_33
56 DP Digital Power for LVDS Block. Connect to digital 3.3V supply.
57 O Reserved. Output for Testing Purpose only at Factory.
58 G Ground for LVDS outputs.
59 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
60 O
61 O
62 O
63 O
64 O
65 O
66 O
67 O
68 O
69 O
70 G Ground for LVDS outputs.
71 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
72 O
73 O
74 O
75 O
76 O
77 O
78 O
79 O
80 O
81 O
82 G Ground for LVDS outputs.
83 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
These form the Differential Data Output for Channel – 3 (Even).
These form the Differential Clock Output Even Channel.
These form the Differential Data Output for Channel – 2 (Even).
These form the Differential Data Output for Channel – 1 (Even).
These form the Differential Data Output for Channel – 0 (Even).
These form the Differential Data Output for Channel – 3 (Odd).
These form the Differential Clock Output Odd Channel.
These form the Differential Data Output for Channel – 2 (Odd).
These form the Differential Data Output for Channel – 1 (Odd).
These form the Differential Data Output for Channel – 0 (Odd).
Page 25
Table 7: TTL Display Interface
Pin Name No I/O Description
PBIAS 53 O Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
PPWR 54 O Panel Power Control [Tri-state output, 5V- tolerant]
AVDD_LV_33
VCO_LV
AVSS_LV
AVDD_OUT_LV_33
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
AVSS_OUT_LV
AVDD_OUT_LV_33
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
AVSS_OUT_LV
AVDD_OUT_LV_33
PD20/B4 86 O Blue channel bit 4 (Even) Blue channel bit 2 (Even)
PD21/B5 87 O Blue channel bit 5 (Even) Blue channel bit 3 (Even)
PD22/B6 88 O Blue channel bit 6 (Even) Blue channel bit 4 (Even)
PD23/B7 89 O Blue channel bit 7 (Even) Blue channel bit 5 (Even)
DEN 90 O Display Data Enable
DHS 91 O Display Horizontal Sync.
DVS 92 O Display Vertical Sync.
DCLK 93 O Display Pixel Clock
PD24
56 DP Digital Power for TTL Block. Connect to digital 3.3V supply.
57 O Reserved. Output for Testing Purpose only at Factory.
58 G Ground for TTL outputs.
59 DP Digital Power for TTL outputs. Connect to digital 3.3V supply.
60 O Red channel bit 0 (Even) Not used.
61 O Red channel bit 1 (Even) Not used.
62 O Red channel bit 2 (Even) Red channel bit 0 (Even)
63 O Red channel bit 3 (Even) Red channel bit 1 (Even)
64 O Red channel bit 4 (Even) Red channel bit 2 (Even)
65 O Red channel bit 5 (Even) Red channel bit 3 (Even)
66 O Red channel bit 6 (Even) Red channel bit 4 (Even)
67 O Red channel bit 7 (Even) Red channel bit 5 (Even)
68 O Green channel bit 0 (Even) Not used.
69 O Green channel bit 1 (Even) Not used.
70 G Ground for TTL outputs.
71 DP Digital Power for TTL outputs. Connect to digital 3.3V supply.
72 O Green channel bit 2 (Even) Green channel bit 0 (Even)
73 O Green channel bit 3 (Even) Green channel bit 1 (Even)
74 O Green channel bit 4 (Even) Green channel bit 2 (Even)
75 O Green channel bit 5 (Even) Green channel bit 3 (Even)
76 O Green channel bit 6 (Even) Green channel bit 4 (Even)
77 O Green channel bit 7 (Even) Green channel bit 5 (Even)
78 O Blue channel bit 0 (Even) Not used.
79 O Blue channel bit 1 (Even) Not used.
80 O Blue channel bit 2 (Even) Blue channel bit 0 (Even)
81 O Blue channel bit 3 (Even) Blue channel bit 1 (Even)
82 G Ground for TTL outputs.
83 DP Digital Power for TTL outputs. Connect to digital 3.3V supply.
115 O Red channel bit 0 (Odd) Not used.
114 O Red channel bit 1 (Odd) Not used.
113 O Red channel bit 2 (Odd) Red channel bit 0 (Odd)
112 O Red channel bit 3 (Odd) Red channel bit 1 (Odd)
111 O Red channel bit 4 (Odd) Red channel bit 2 (Odd)
110 O Red channel bit 5 (Odd) Red channel bit 3 (Odd)
109 O Red channel bit 6 (Odd) Red channel bit 4 (Odd)
108 O Red channel bit 7 (Odd) Red channel bit 5 (Odd)
107 O Green channel bit 0 (Odd) Not used.
106 O Green channel bit 1 (Odd) Not used.
105 O Green channel bit 2 (Odd) Green channel bit 0 (Odd)
104 O Green channel bit 3 (Odd) Green channel bit 1 (Odd)
103 O Green channel bit 4 (Odd) Green channel bit 2 (Odd)
102 O Green channel bit 5 (Odd) Green channel bit 3 (Odd)
101 O Green channel bit 6 (Odd) Green channel bit 4 (Odd)
123 O Green channel bit 7 (Odd) Green channel bit 5 (Odd)
124 O Blue channel bit 0 (Odd) Not used.
125 O Blue channel bit 1 (Odd) Not used.
128 O Blue channel bit 2 (Odd) Blue channel bit 0 (Odd)
129 O Blue channel bit 3 (Odd) Blue channel bit 1 (Odd)
130 O Blue channel bit 4 (Odd) Blue channel bit 2 (Odd)
131 O Blue channel bit 5 (Odd) Blue channel bit 3 (Odd)
For 8-bit panels For 6-bit panels
For 8-bit panels For 6-bit panels
24
Page 26
PD46
PD47
132 O Blue channel bit 6 (Odd) Blue channel bit 4 (Odd)
118 O Blue channel bit 7 (Odd) Blue channel bit 5 (Odd)
Note: In case of 24 Bit TTL Panels the RGB Odd Channel Outputs will not be used. In that case they can be
made available for other purposes as Address & Data from On-Chip Micro or Digital Video Input Data.
RVDD_3.3 32 49 98 116 154 P Ring VDD. Connect to digital 3.3V.
95
O 256K x8 PROM Address. These pins also have bootstrap functionality.
96
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
132
131
130
129
128
125
124
123
97 O External PROM data Write Enable (for In-System-Programming of FLASH) or Serial Data Input
94 O External PROM data Chip Select or Serial PROM Chip Select (ROM_SCSN) for SPI ROM
For serial SPI ROM interface:
- ROM_ADDR17 will be Serial Clock (ROM_SCLK)
- ROM_ADDR16 will be Serial Data Output (ROM_SDO)
For 512K X 8 PROM, Address Signal A18 is available thru Pin # 44 which is GPIO10.
IO External PROM data input.
(SDI) for SPI ROM interface.
interface.
CVDD_1.8 18 28 39 45 84 119 126 133 143 P Core VDD. Connect to digital 1.8V.
CRVSS 19 29 33 40 46 50 85 99 117 120
127 134 144 155
G Chip ground for core and ring.
Table 10: JTAG Boundary Scan
Pin Name No I/O Description
TCK 34 I JTAG Boundary Scan TCK signal
TDO 55 O JTAG Boundary Scan TDO signal
TDI 35 I JTAG Boundary Scan TDI signal. Pad has internal 50K pull-up resistor.
TMS 36 I JTAG Boundary Scan RST signal. Pad has internal 50K pull-up resistor.
TRST 37 I JTAG Boundary Scan TMS signal. Pad has internal 50K pull-up resistor.
25
Page 27
7. CD4052B
The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A
and B, and an inhibit input. The two binary signals selec t 1 of 4 pairs of channels to be turned
on and connect the analog inputs to the outputs.
·PInputs
.
26
Page 28
8. A T24C32AN
2-Wire Serial EEPROM 32K (4096 x 8)
27
Page 29
28
Page 30
9. TPA3008D2
10-W STEREO CLASS-D AUDIO POWER AMPLIFIER.
29
Page 31
·Pin Description
30
Page 32
10.TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
31
Page 33
1. BA5954
ICS ON DVD BOARD
32
Page 34
33
Page 35
2. MT1389HD
Abbr. :
SR : Slew Rate
PU : Pull Up
PD : Pull Down
SMT : Schmitt Trigger
2MA~16MA : Output buffer driving strength.
Pin Main Alt. Type Description
231 RFGND18
232 RFVDD18
252 OSP
253 OSN
254 RFGC
Ground Analog ground
Analog output RF Offset cancellation capacitor connecting
Analog output RF Offset cancellation capacitor connecting
Analog output RF AGC loop capacitor connecting for DVD-ROM
255 IREF
Analog Input RF path. Connect an external 15K resistor to this pin and
Ground Analog ground
Analog Input AC coupled input path A
Analog Input AC coupled input path B
Analog Input AC coupled input path C
Analog Input AC coupled input path D
Analog Input AC coupled DVD RF signal input RFIP
Analog Input AC coupled DVD RF signal input RFIN
Analog Input DC coupled main-beam RF signal input A
Analog Input DC coupled main-beam RF signal input B
Analog Input DC coupled main-beam RF signal input C
Analog Input DC coupled main-beam RF signal input D
Analog Input DC coupled sub-beam RF signal input A
Analog Input DC coupled sub-beam RF signal input B
Analog Input DC coupled sub-beam RF signal input C
Analog Input DC coupled sub-beam RF signal input D
Analog Input CD focusing error negative input
Analog Input CD focusing error positive input
Analog Input 3 beam satellite PD signal negative input
Analog Input 3 beam satellite PD signal positive input
Analog output The output terminal of RF jitter meter.
Analog Input The input terminal of RF jitter meter.
Ground Ground pin for data PLL and related analog circuitry.
Analog output Data PLL DAC Low-pass filter
Power Power pin for data PLL and related analog circuitry.
Analog Output The negative output of loop filter amplifier
Analog Input The positive input terminal of loop filter amplifier.
Analog Input The negative input terminal of loop filter amplifier.
Analog Output The positive output of loop filter amplifier
Motor and Actuator Driver Interface ( 10 )
34 OP_OUT
35 OP_INN
36 OP_INP
37 DMO
38 FMO
39
40
41 TRO
42 FOO
50
55,93,
142,160,
174, 213
81,178 DVSS
65,96,11
8,
131,145,
156,
170, 208
90, 148 DVSS
TROPENP
W M
PWMOUT
FG (Digital
pin)
DVDD18
DVDD3
1
V_ADIN9 Analog Output
V_ADIN8
Analog output Op amp output.
Analog input Op amp negative input
Analog input Op amp positive input
Analog Output Disk motor control output. PWM output.
Analog Output Feed motor control. PWM output.
Analog Output Tray PWM output / Tray open output.
Analog Output
Analog Output
LVTTL 3.3V Input,
Schmitt Input, pull
up , with analog
input path for
V_ADIN8
General Power/Ground ( 18 )
Power 1.8V power pin for internal digital circuitry
Ground 1.8V Ground pin for internal digital circuitry
Power 3.3V power pin for internal digital circuitry
Ground 3.3V Ground pin for internal digital circuitry
1)
2)
Tracking servo output. PDM output of tracking servo
compensator.
Focus servo output. PDM output of focus servo
compensator
1)
2)
1st General PWM output, or
Version AD input 9
Motor Hall sensor input, or
Version AD input 8
Micro Controller and Flash Interface (48)
Pin Main Alt. Type Description
36
Page 38
62 HIGHA0
Input
2~16MA, SR
PU
Microcontroller address 8
74 HIGHA1
73HIGHA2
72HIGHA3
71HIGHA4
70HIGHA5
69HIGHA6
68HIGHA7
Input
2~16MA, SR
PU
Input
2~16MA, SR
PU
Input
2~16MA, SR
PU
Input
2~16MA, SR
PU
Input
2~16MA, SR
PU
Input
2~16MA, SR
PU
Input
2~16MA, SR
PU
Microcontroller address 9
Microcontroller address 10
Microcontroller address 11
Microcontroller address 12
Microcontroller address 13
Microcontroller address 14
Microcontroller address 15
89 AD7
86 AD6
85 AD5
84 AD4
83 AD3
82 AD2
80 AD1
79 AD0
92IOA0
Input 2~16MA, SR
Input 2~16MA, SR
Input 2~16MA, SR
Input 2~16MA, SR
Input 2~16MA, SR
Input 2~16MA, SR
Input 2~16MA, SR
Input 2~16MA, SR
Input
2~16MA, SR
PU
Microcontroller address/data 7
Microcontroller address/data 6
Microcontroller address/data 5
Microcontroller address/data 4
Microcontroller address/data 3
Microcontroller address/data 2
Microcontroller address/data 1
Microcontroller address/data 0
Microcontroller address 0 / IO
37
Page 39
PinMainAlt. TypeDescription
77
IOA1
Input
2~16MA, SR
PU
Microcontroller address 1 / IO
56 IOA2
57IOA3
58IOA4
59IOA5
60IOA6
61IOA7
Input
2~16MA, SR
PU
Microcontroller address 2 / IO
Input
2~16MA, SR
PU
Microcontroller address 3 / IO
Input
2~16MA, SR
PU
Microcontroller address 4 / IO
Input
2~16MA, SR
PU
Microcontroller address 5 / IO
Input
2~16MA, SR
PU
Microcontroller address 6 / IO
Input
2~16MA, SR
PU
Microcontroller address 7 / IO
67 A16
91 A17
63IOA18
64IOA19
75IOA20
87IOA21
Output 2~16MA,
SR
Output 2~16MA,
SR
Flash address 16
Flash address 17
Input
2~16MA, SR
SMT
Flash address 18 / IO
Input
2~16MA, SR
SMT
Flash address 19 / IO
Input
2~16MA, SR
SMT
Flash address 20 / IO
Input
2~16MA, SR
SMT
1) Flash address 21 / IO
2) While External FLASH size <= 2MB:
I) GPIO
38
Page 40
88ALE
2~16MA, SR
PU, SMT
Microcontroller address latch enable
Input
Pin Main Alt. TypeDescription
78 IOOE#
Input
2~16MA, SR
SMT
Flash output enable, active low / IO
66 IOWR#
76 IOCS#
94 UWR#
95 URD#
97 UP1_2
98 UP1_3
99 UP1_4
100 UP1_5
Input
2~16MA, SR
SMT
Input
2~16MA, SR
PU, SMT
Input
2~16MA, SR
PU, SMT
Input
2~16MA, SR
PU, SMT
Input
4MA, SR
PU, SMT
Input
4MA, SR
PU, SMT
Input
4MA, SR
PU, SMT
Input
4MA, SR
PU, SMT
Flash write enable, active low / IO
Flash chip select, active low / IO
Microcontroller write strobe, active low
Microcontroller read strobe, active low
Microcontroller port 1-2
Microcontroller port 1-3
Microcontroller port 1-4
Microcontroller port 1-5
101 UP1_6 SCL
102 UP1_7 SDA
103 UP3_0 RXD
104 UP3_1 TXD
Input
4MA, SR
PU, SMT
Input
4MA, SR
PU, SMT
Input
4MA, SR
PU, SMT
Input
4MA, SR
PU, SMT
1) Microcontroller port 1-6
2
2) I
C clock pin
1) Microcontroller port 1-7
2) I2C data pin
1) Microcontroller port 3-0
2) 8032 RS232 RXD
1) Microcontroller port 3-1
2) 8032 RS232 TXD
39
Page 41
105 UP3_4 RXD SCL
Input
4MA, SR
PU, SMT
1) Microcontroller port 3-4
2) Hardwired RD232 RXD
2
3) I
C clock pin
1) Microcontroller port 3-5
2) Hardwired RD232 TXD
2
3) I
C data pin
106 UP3_5 TXD SDA
Input
4MA, SR
PU, SMT
109 IR
110 INTO#
Input
SMT
Input
4MA, SR
PU, SMT
IR control signal input
Microcontroller external interrupt 0, active low
Audio interface ( 28 )
Pin Main Alt. Type Description
1)
2)
1)
2)
204 SPMCLK SCLK0
205 SPDATA SDIN0
Input
Non-pull
Input
Non-pull
Audio DAC master clock of SPDIF input
While SPDIF input is not used:
I) Serial interface port 0 clock pin
II) GPIO
Audio data of SPDIF input
While SPDIF input is not used:
I) Serial interface port 0 data-in
II) GPIO
206 SPLRCK SDO0
207 SPBCK
SDCS0
ASDATA5
209 ALRCK
210 ABCK Fs64
211 ACLK
1)
Audio left/right channel clock of SPDIF input
2)
While SPDIF input is not used:
Input
Non-pull
Input
Non-pull
Input 4MA, PD,
SMT
Output
4MA
Non-pull
Input
4MA Audio DAC master clock
I) Serial interface port 0 data-out
II) GPIO
1)
Audio bit clock of SPDIF input
2)
While SPDIF input is not used:
I) Serial interface port 0 chip select
II) Audio serial data 5 part I : DSD data sub-woofer
channel or Microphone output
III) GPIO
1)
Audio left/right channel clock Trap value in power-on
2)
reset: I) 1 : use external 373 II) 0: use internal 373
1)
Audio bit clock
2)
Phase de-modulation
40
Page 42
197 ASDATA0
202 ASDATA1
203 ASDATA2
212 ASDATA3
Non-pull
Input
4MA
PD SMT
Input
4MA
PD SMT
Input 4MA PD
SMT
Input
4MA
PD SMT
Audio serial data 0 (Front-Left/Front-Right)
1)
DSD data left channel
2)
Trap value in power-on reset :
3)
I) 1 : manufactory test mode
II) 0 : normal operation
While using external channels:
4)
I) GPO_2
Audio serial data 1 (Left-Surround/Right-Surround)
1)
DSD data right channel
2)
Trap value in power-on reset :
3)
I) 1 : manufactory test mode
II) 0 : normal operation
While using external channels:
4)
I) GPO_1
Audio serial data 2 (Center/LFE) DSD data left surround
1)
channel Trap value in power-on reset : I) 1 : manufactory
2)
test mode II) 0 : normal operation While using external
3)
channels: I) GPO_0
4)
Audio serial data 3 (Center-back/
1)
Center-left-back/Center-right-back, in 6.1 or 7.1 mode)
DSD data right surround channel
2)
Trap value in power-on reset :
3)
I) 1 : manufactory test mode
II) 0 : normal operation
While only 2 channels output:
4)
I) GPO_0
214 ASDATA4 INT1#
215 MC_DATA INT2#
216 SPDIF
217 APLLVDD3
218 APLLCAP
Audio serial data 4 (Down-mixed Left/Right)
1)
DSD data center channel
2)
Trap value in power-on reset :
Input
4MA
PD SMT
Input
PD SMT
Output
2~16MA,
SR : ON/OFF
Non-pull
Power 3.3V Power pin for audio clock circuitry
Analog Input APLL External Capacitance connection
3)
I) 1 : manufactory test mode
II) 0 : normal operation
While only 2 channels output:
DRAM data 10
DRAM data 11
DRAM data 12
DRAM data 13
DRAM data 14
DRAM data 15
DRAM data 0
DRAM data 1
DRAM data 2
DRAM data 3
DRAM data 4
DRAM data 5
DRAM data 6
DRAM data 7
GPIO
Data mask 0
JTAG Interface( 4 )
Serial interface port 3 data-out
1)
51 TDI V_ADIN4 Input Non-pull
52 TMS V_ADIN5 Input Non-pull
53 TCK V_ADIN6 Input Non-pull
54 TDO V_ADIN7 Input Non-pull
Version AD input port 4
2)
GPIO
3)
Serial interface port 3 data-in
1)
Version AD input port 5
2)
GPIO
3)
1)
Serial interface port 3 clock pin
2)
Version AD input port 6
3)
GPIO
1)
Serial interface port 3 chip-select
2)
Version AD input port 7
3)
GPO
Note:
1. The Main column is the main function, Alt. Means alternative function.
2. The multi-function GPIO pins are set to green characters.
3. The video input port and external TV encoder mode can not both use CCIR-601 mode, at
least one of them should be in CCIR-656 mode.
4. Following is a summary of modified pins.
(a) Pin 48, 49, 50, 51 are no longer for JTAG functions.
(b) V_ADIN0 and V_ADIN3 is not available.
45
Page 47
3.24C16
2-Wire Serial CMOS E2PROM 16k ( 2048 x 8 )
The AT24C16 provides 16384 bits of serial electrically erasable and program mable read
only memory (EEPROM) organized as 2048 words of 8 bits each. The device is optimized f or
use in many industrial and commercial applications where low power and low voltage
operation are essential. The AT24C16 is available in space saving 8-pin PDIP, 8-pin and
14-pin SOIC packages and is accessed via a 2-wire serial interface. In addition, the entire
family is available in 5.0V(4.5V to 5.5V), 2.7V(2.7V to 5.5V) and 1.8V(1.8V to 5.5V) versions.
46
Page 48
47
Page 49
48
Page 50
4. NJM4558
DUAL OPERATIONAL AMPLIFIER
49
Page 51
5. BA033
Low saturation voltage type 3-pin regulator
50
Page 52
ICS ON HI-VOLTAGE BOARD
1. BIT3193
High Performance PWM Controller
BIT3193 integrated circuit provides the essential features for general purpose PWM
controller in a small low cost 16-pin package. BIT3193 has built-in a low frequency PWM
generator for any specified application. BIT3193 includes latched off protection feature may
make the system more reliable while compare to other similar products.
1 INN I/O The i nve rting input of the error amplifier.
2 CMP O Output of the error amplifier.
3 LOAD I/O A switch that connected to the high frequency triangle wave generator.
4 CTOSC I/O An external capacitor connected here can set the frequency of high
5 TIMER I/O With internal reference current and an external capacitor connected here
6 ONOFF I The control pin of turning on or off the IC.1V threshold with an internal 80K
7 GND I/O The ground pin of the device.
8 NOUT2 O The number 2 output driver for driving the NMOSFET switch.
9 NOUT1 O The number 1 output driver for driving the NMOSFET switch.
10 VDD I The power supplies pin of the device.
11 PWMOUT O The output pin of low frequency PWM generator. A 2.5V or floating two
12 CTPWM I/O With the internal reference current and an external capacitor connected
13 PWMDC I Low frequency PWM controlling input. A PWM output comes out by
14 CLAMP I
15 ISEN I Load current detection pin, the open load situation is detected if a less than
16 MODSEL O To set the output polarity of the low frequency PWM controller.
Symbol I/O Descriptions
This switch is op en while ISEN pin <1.3V. An e xternal resistor conne cted
here may change the operation frequency of CTOSC in open load situation.
frequency PWM controller.
can set the required period of starting and the timing of initialization. The
controller is forced to reset mode while TIMER<0.3V. During reset mode,
a~60uA current will flow into the INN pin to reduce the output level of the
error amplifier CMP to turn off the controller. The latched off protection
function will be enable after this node is charged to>2.5V. System is latched
off if any abnormal operation is detected if pin TIMER>2.5V.
The output current of this pin is 20uA when TIMER<0.3V.
The output current becomes to 1uA when TIMER>0.3V.
±15% ohm pull-low resistor.
state output is provided through this pin.
The internal circuit limits the max. Duty-cycle to ~92%.
here can set the operation frequency of low frequency PWM generator with
1.0V~2.5V triangle wave output.
comparing this DC input and the 1.0~2.5V triangle wave that is generated
by CTPWM.
Over voltage clamping. If a>2.0V voltage is detected. A~60uA current will
flow into the INN pin to reduce the output of the error amplifier pin CMP to
regulate the output voltage.
First check voltage in HI-voltage Board; otherwise check the voltage of MAIN board ,
if abnormal , the problem occurs in 4U1. If the voltage is OK, check the LVDS. At last
the connection between the main board and drive board may be the target for
troubleshooting.
Black screen
This problem often arise from the voltage input to the screen, so the first step is to
check the voltage of invert circuit. Otherwise check if the status is standby. If in TV
mode, check the power for tuner is correct.
No color
Check if the connection with the external device is correct. Otherwise make sure
the saturation is not zero. At last the problem may arise from the FLI8125.
Abnormal picture
Check if the range of the signal input to FLI8125 is correct. If no, the problem may
be in the AFE(Analog Front End). Otherwise make sure the color system is correct.
Then check the LVDS and the LCD Screen.
Pictures with no sound
Firstly, make sure the speakers works well. If so, the trouble mostly occurred in
TPA3008 in 3U6 in main board, then MSP3425G in 3U1.
Sounds with no picture
Check if any signal inputs to FLI8125, if yes, the problem may be in the AFE.
Otherwise check the LVDS.
80
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.