Denon DVD-3910 Service Manual

For U.S.A., Canada, Europe, Asia, China,& Japan model

Ver. 6

SERVICE MANUAL

MODEL DVD-

3910

Please refer to the MODIFICATION NOTICE.

DVD AUDIO-VIDEO / SUPER AUDIO CD PLAYER

注意

サービスをおこなう前に、このサービスマニュアルを必ずお読みください。本機は、火災、感電、けがなどに対する安全性を確保するために、さまざまな配慮をおこなっており、また法的には「電気用品安全法」にもとづき、所定の許可を得て製造されております。従ってサービスをおこなう際は、これらの安全性が維持されるよう、このサービスマニュアルに記載されている注意事項を必ずお守りください。

●

For purposes of improvement, specifications and design are subject to change without notice.

●

Please use this service manual with referring to the operating instructions without fail.

●

Some illustrations using in this service manual are slightly different from the actual set.

Denon Brand Company, D&M Holdings Inc.

●

TOKYO, JAPAN

本機の仕様は性能改良のため、予告なく変更することがあります。補修用性能部品の保有期間は、製造打切後8年です。

修理の際は、必ず取扱説明書を参照の上、作業を行ってください。

本文中に使用しているイラストは、説明の都合上現物と多少異なる場合があります。

X0200V.06 DE/CDM 0707

SAFETY PRECAUTIONS

The following check should be performed for the continued protection of the customer and service technician.

LEAKAGE CURRENT CHECK

Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the power cord is less than 460 kohms, the unit is defective.

LASER RADIATION

Do not stare into beam or view directly with optical instruments, class 3A laser product.

DVD-3910

CAUTION

Please heed the points listed below during servicing and inspection.

◎ Heed the cautions!

Spots requiring particular attention when servicing, such as the cabinet, parts, chassis, etc., have cautions indicated on labels or seals. Be sure to heed these cautions and the cautions indicated in the handling instructions.

◎ Caution concerning electric shock!

(1) An AC voltage is impressed on this set, so touching inter-

nal metal parts when the set is energized could cause electric shock. Take care to avoid electric shock, by for example using an isolating transformer and gloves when servicing while the set is energized, unplugging the power cord when replacing parts, etc.

(2)There are high voltage parts inside. Handle with extra care

when the set is energized.

◎

Caution concerning disassembly and assembly!

Though great care is taken when manufacturing parts from sheet metal, there may in some rare cases be burrs on the edges of parts which could cause injury if fingers are moved across them. Use gloves to protect your hands.

◎ Only use designated parts!

The set's parts have specific safety properties (fire resistance, voltage resistance, etc.). For replacement parts, be sure to use parts which have the same properties. In particular, for the important safety parts that are marked ! on wiring diagrams and parts lists, be sure to use the designated parts.

◎ Be sure to mount parts and arrange the

wires as they were originally!

For safety reasons, some parts use tape, tubes or other insulating materials, and some parts are mounted away from the surface of printed circuit boards. Care is also taken with the positions of the wires inside and clamps are used to keep wires away from heating and high voltage parts, so be sure to set everything back as it was originally.

◎ Inspect for safety after servicing!

Check that all screws, parts and wires removed or disconnected for servicing have been put back in their original positions, inspect that no parts around the area that has been serviced have been negatively affected, conduct an insulation check on the external metal connectors and between the blades of the power plug, and otherwise check that safety is ensured.

(Insulation check procedure) Unplug the power cord from the power outlet, disconnect the antenna, plugs, etc., and turn the power switch on. Using a 500V insulation resistance tester, check that the insulation resistance between the terminals of the power plug and the externally exposed metal parts (antenna terminal, headphones terminal, microphone terminal, input terminal, etc.) is 1MΩ or greater. If it is less, the set must be inspected and repaired.

CAUTION

Many of the electric and structural parts used in the set have special safety properties. In most cases these properties are difficult to distinguish by sight, and using replacement parts with higher ratings (rated power and withstand voltage) does not necessarily guarantee that safety performance will be preserved. Parts with safety properties are indicated as shown below on the wiring diagrams and parts lists is this service manual. Be sure to replace them with parts with the designated part number.

(1) Schematic diagrams ... Indicated by the ! mark.

(2) Parts lists ... Indicated by the ! mark.

Concerning important safety parts

Using parts other than the designated parts could result in electric shock, fires or other dangerous situations.

注意

サービス、点検時にはつぎのことにご注意願います。

◎注意事項をお守りください！

サービスのとき特に注意を必要とする個所についてはキャビネット、部品、シャーシなどにラベルや捺印で注意事項を表示しています。これらの注意書きおよび取扱説明書などの注意事項を必ずお守りください。

◎感電に注意！

(1) このセットは、交流電圧が印加されていますので通電時

に内部金属部に触れると感電することがあります。従って通電サービス時には、絶縁トランスの使用や手袋の着用、部品交換には、電源プラグを抜くなどして感電にご注意ください。

(2) 内部には高電圧の部分がありますので、通電時の取扱に

は十分ご注意ください。

◎分解、組み立て作業時のご注意！

板金部品の端面の『バリ』は、部品製造時に充分管理をしておりますが、板金端面は鋭利となっている箇所が有りますので、部品端面に触れたまま指を動かすとまれに怪我をする場合がありますので十分注意して作業して下さい。手の保護のために手袋を着用してください。

◎指定部品の使用！

セットの部品は難燃性や耐電圧など安全上の特性を持ったものとなっています。従って交換部品は、使用されていたものと同じ特性の部品を使用してください。特に配線図、部品表に!印で指定されている安全上重要な部品は必ず指定のものをご使用ください。

◎部品の取付けや配線の引きまわしは、

元どおりに！

安全上、テープやチューブなどの絶縁材料を使用したり、プリント基板から浮かして取付けた部品があります。また内部配線は引きまわしやクランパーによって発熱部品や高圧部品に接近しないように配慮されていますので、これらは必ず元どおりにしてください。

◎サービス後は安全点検を！

サービスのために取り外したねじ、部品、配線などが元どおりになっているか、またサービスした個所の周辺を劣化させてしまったところがないかなどを点検し、外部金属端子部と、電源プラグの刃の間の絶縁チェックをおこなうなど、安全性が確保されていることを確認してください。

（絶縁チェックの方法）

電源コンセントから電源プラグを抜き、アンテナやプラグなどを外し、電源スイッチを入れます。500V 絶縁抵抗計を用いて、電源プラグのそれぞれの端子と外部露出金属部［アンテナ端子、ヘッドホン端子マイク端子、入力端子など］との間で、絶縁抵抗値が１ MΩ 以上であること、この値以下のときはセットの点検修理が必要です。

注意

本機に使用している多くの電気部品、および機構部品は安全上、特別な特性を持っています。この特性はほとんどの場合、外観では判別つきにくく、またもとの部品より高い定格（定格電力、耐圧）を持ったものを使用しても安全性が維持されるとは、限りません。安全上の特性を持った部品は、このサービスマニュアルの配線図、部品表につぎのように表示していますので必ず指定されている部品番号のものを使用願います。

(1) 配線図…!マークで表示しています。 (2) 部品表…!マークで表示しています。

安全上重要な部品について

指定された部品と異なるものを使用した場合には、感電、火災などの危険を生じる恐れがあります。

2

DVD-3910

WIRE ARRANGEMENT

If wire bundles are untied or moved to perform adjustment or parts replacement etc.,be sure to rearrange them neatly as they were originally bundled or placed afterward. Otherwise, incorrect arrangement can be a cause of noise generation.

Wire arrangement viewed from the top

ワイヤー整形図

調整や部品の交換等により、ワイヤー類の結束をはずしたり移動させた場合には、それらの作業が完了した時点でワイヤーの整形をおこなってください。正しく整形されていないとノイズ発生の原因となることがあります。

上面からみたワイヤー整形

(Europe model only)

3

3 Deletion of latitude line of weight.

DVD-3910

DISASSEMBLY

(Follow the procedure below in reverse order when reas-

各部のはずしかた

（組み立てるときは、逆の順序で行ってください。）

sembling.)

分解と廃棄(Disassembly and abandonment)

(1)Disassembly of a set



It decomposes according to a work procedure1.~11.clause.



(2)Judgment of use parts



It classifies according to the discernment signs in a figure



(c, m, s, p, etc.).



(3)Abandonment of parts



Each part article is discarded according to the specification



abandonment method of each self-governing body. The parts of ◆ mark show that it shall be remove .



(1)セットの分解

作業手順 1.〜11.項に従い分解を実施します。

(2)使用部品の分別

図中の識別記号(c、m、s、p 等)に従い分別する。

(3)部品の廃棄  各部品は、各自治体の指定廃棄方法に従い廃棄する。   ◆記号付き部品は、分離する事。



No. Part Name Q’ty Material No. Part Name Q’ty Material

c · 1䎃

c · 2 DVD mechanism ass’y 1 - m · 2 Front angle 1 SECC

c · 3 Power P.W.B. ass’y 1 - m · 3 Ieee1394 top Shield 1 SPCC

c · 4 Ac inlet 1 - m · 4 Ieee1394 bottom Shield 1 SECC

c · 5 Ferrite core & 3P VH wire 1 - m · 5 Rear panel 1 SECC

c · 6 Video P.W.B. ass’y 1 - m · 6 Mecha base 1 SECC

c · 7 Scart P.W.B. ass’y 1 - m · 7 Bottom cover 1 SECC

c · 8 Audio P.E.B. ass’y 1 - m · 8 Chassis 1 SECC

c · 9 IEEE1394 P.W.B. ass’y 1 - m · 9 Spring 1 SUS304

c · 10 System P.W.B. ass’y 1 - m · 10 Front panel 1 A6063SS

c · 11 D12mm knob ass’y 1 - m (Metals) totals 6,553g

c · 12 Display P.W.B. ass’y 1 -   

c · 13 Power-1 P.W.B. ass’y 1 - No. Part Name Q’ty Material

c · 14 Power knob (MAIN) ass’y 1 - s · 1 Screw 3X6 CBTS(S)-B 48 SW

c · 15 Power-2 P.W.B. ass’y 1 - s · 2 Screw 4X8 3P SWELLING 9 SW

c · 16 Power knob (SUB) ass’y 1 - s · 3 Screw 3X8 CBTS(S)-Z 26 SW

c Wire (the othes) 1 - s · 4 Screw 3X8 CBS-Z 2 SW

   s · 6 Screw 3X8 FIXING 8 SW

p · 1 P.W.B. support 1 PA66 s · 8 P3 nut for RS-232C 2 SW

p · 2 Foot ass’y 4 ABS s · 9 Screw 3X8 CBTS(P)-B 16 SW

p · 3 P.W.B. spacer 6 PA66 s · 10 Screw 3X10 Special 2 SW

p · 4 Lens 1 PMMA s Washer 2 SPCC/SK

p · 5 Blind ass’y 1 PVC+ s (Screws) totals 81g

p · 6 Inner panel ass’y 1 ABS  

p · 7 Part of inner panel 1 ABS Total Weight 9,270g

p · 8 Rubber sheet 2 CR Recycle Weight 6,998g

p · 9 Rubber sheet 1 CR Abandonment Weight 2,272g

The parts of ◆ mark show that it shall be remove at the disassembly and the abandonment

◆ CE04W2G470MC (KMG) ĭ16.0×h31.5mm C-909 c · 3 Power P.W.B. ass’y (GU-3614-2) 1

3

◆ CE04W1A222MC (KY)J30 ĭ10.0×h30.0mm C-918, C-952 c · 3 Power P.W.B. ass’y (GU-3614-2) 2

Loader Panel ass’y 1 - m · 1 Top cover 1 SECC+PVC

c (Complex) totals 2,272g s · 5 Screw 3X8 CFTS(S) 2 SW

No. Part Name Q’ty Material s · 7 P3 nut for DVI 2 SW

p (Plastics) totals 364g   

  

Part Name Dimensions Ref.No. Unit No. Q’ty

4

1. Top cover

締結トルク

(1)Remove 2 screws(s ･1) on the rear side and 9

screws(s･2) on the top and the both sides.

 Remove 2-washer at the front center on the top.

(2)Widen the Top cover a little laterally, then detach it

with sliding.

ｓ･2

DVD-3910

(1)背面側から s･１のねじ2 本と天･側面から s･2 のねじ 9

本をはずします。天前中央のみﾜｯｼｬｰ 2 個共締め。

(2)左右へ少し広げて m･1：Topcover をはずします

m･1：Top cover

㨟㨯1



ｓ･2

2. Front panel sub ass'y & etc.

2-1.When the Disc tray can be ejected electrically. (1)Switch on , and press ｢OPEN/CLOSE｣ button to

open the Disc tray.

(2)Detach the Loader panel ass'y by lifting.

(3)Close the Disc tray.

(4)Disconnect the wire [CX031] [CX025] [CY211]

connecting a･1：From the Front panel sub ass’y.

(5)Remove 4 top screws(s･1) and 4 bottom screws

(s･1) , then detach the Front panel sub ass’y .

(6)Remove 2 top screws(s･3) , then detach the m2 :

Front angle. Use 2 pieces of F.Angle for Japan.

2-2.When the Disc tray cannot be ejected

electrically.

(1)Insert a driver into the left 8mm hole , and push

the Plate Gear of the DVD Mechanism , to open the Disc Tray. (Arrow direction)

(2)The same steps described on 2-1.(2)〜(6).

ｓ：2-washer

s･1：（Tighten-torque）

ｓ･2

2-1.ﾃﾞｨｽｸﾄﾚｲが電動でｵｰﾌﾟﾝ出来る場合 (1)電源を入れ｢OPEN/CLOSE｣ﾎﾞﾀﾝを押して、ﾃﾞｨｽｸﾄﾚｲを

開きます。 (2)ｃ･1：Loaderpanelass'y を持ち上げてはずします。 (3)ﾃﾞｨｽｸﾄﾚｲを閉じます。 (4)a･1：Frontpanelsubass'y からのﾜｲﾔｰ[CX031][CX025]

[CY211] をはずします。 (5)天・底面からｓ･１のねじ各 4 本をはずし、a･1：Front

panelsubass'y をはずします。 (6)天面からｓ･3 のねじ 2 本をはずし、ｍ･2：Frontangle

をはずします。国内モデルのみ 2 個使用。 2-2.ﾃﾞｨｽｸﾄﾚｲが電動でｵｰﾌﾟﾝ出来ない場合 (1)左側面のΦ8mm 孔よりﾄﾞﾗｲﾊﾞｰ等を挿し込みﾒｶﾕﾆｯﾄの

ﾌﾟﾚｰﾄｷﾞｱを押してﾃﾞｨｽｸﾄﾚｲを開きます。(矢印方向) (2)2-1.(2)〜(6)の作業に同じ。 

s･2：締結トルク：1.0Nm （Tighten-torque）

：0.5Nm

m･2：Front angle

(only Japan)

ｓ･3

m･2：Front angle

ｓ･3

ｃ･1：Loader panel ass’y

ｓ･1

㨟㨯1

ａ･１：Front panel sub ass’y

5

s･1：（Tighten-torque） s･3：締結トルク：0.5Nm （Tighten-torque）

：0.5Nm

3. DVD mechanism ass'y

y

r

◆



(1)Remove 4 screws (s · 3) on the top side.䎃



(2)Disconnect [CY251] [CY301] [CY171] [CX331]



[CY101] from the MAIN P.W.B. (GU-3618).



(3)Take the DVD mechanism ass'y (s ·2) off.



c · 2㧦DVD mechanism ass'y



4. Power P.W.B. ass'y etc.



4-1.Power P.W.B. ass'y



(1)Remove 2 side screws (s · 4) and 5 top screws



(s · 3). Screw 1P-3P EH CON.CORD together at near



the [CX131] (only JAPAN).



(2)Disconnect the wire [CX131] [CX051] [CX024]



connecting c · 5 : Power P.W.B. ass'y.



(3)Detach the c · 5 : Power P.W.B. ass'y.

33



Thing to do abandonment based on WEEE directive



detaching E-Capacitor of C909, C918, C952 when



abandoning Power P.W.B. ass’y.



4-2.AC INLET



(1)Remove 2 rear screws (s · 5).



(2)Disconnect the STO terminals from c · 4 : Ac inlet.



(3)Detach the c · 4 : Ac inlet.





4-3.Ferrite core & 3P VH wire



(1)Cut 3 clamper on the left side of the chassis.



(2)Detach the c · 5 : Ferrite core & 3P VH wire.

DVD-3910

(1)天面側から s・3 のねじ 4 本をはずします。 (2)ﾒｲﾝ基板(GU-3618)よりﾜｲﾔｰ[CY251] [CY301] [CY171]

[CX331][CY101]をはずします。

(3)c・2：DVDmechanismass'y をはずします。

s·3

s · 3：締結トルク：0.5Nm （Tighten-torque）

4-1.電源基板 ass'y (1)側面からｓ･4 のねじ 2 本と天面からｓ･3 のねじ 5 本

をはずします。日本向けモデルのみ 1P-3P EH ﾜｲﾔｰが [CX131]横に共締。

(2)ｃ･5：電源基板ass'y からﾜｲﾔｰ[CX131][CX051][CX024]

をはずします。 (3)ｃ･5：電源基板 ass'y をはずします。  電源基板 ass'y の廃棄時は、C909､C918､C952 電解コン

デンサを取外して WEEE 指令に基づく処理をする事。 4-2.ACINLET (1)背面からｓ･5 のねじ 2 本をはずします。 (2)c・4：ACINLET から STO ｺﾈｸﾀｰをはずします。 (3)c・4：ACINLET をはずします。  4-3.ﾌｪﾗｲﾄｺｱ＆3PVH ﾜｲﾔｰ (1)ｼｬｰｼ左側面のｸﾗﾝﾌﾟﾊﾞﾝﾄﾞ 3 箇所をｶｯﾄします。 (2)c・5：ﾌｪﾗｲﾄｺｱと 3PVH ﾜｲﾔｰをはずします。

c · 3 : Power P.W.B. ass'

s · 3

c · 4 : Ac inlet

C952:ĭ10×h30.0mm:2200µF /10V

3

C918:ĭ10×h30.0mm㧦2200µF /10V

c · 5 : Ferrite core & 3P VH wire

s · 5

s · 4

clampe

c : 1P-3P EH CON.CORD (only Japan)

C909:ĭ16×h31.5mm㧦47µF/400V

s · 3 ~䎃5 : 締結トルク:0.5Nm䎃（Tighten-torque）

3

6

5.Video P.W.B. ass'y and Scart P.W.B. ass'y

y y

締結トルク

5-1. Video P.W.B. ass'y (1)Remove 6 screws(s･1) and 2(Japan :3) screws(s･5)

and 2 Nuts(s･6) on the rear side and 2 screws (s･3) on the top side.

(2)Disconnect [CY174] from the Hdmi P.W.B. ass'y

(GU-3613-3).

(3)Take the Video P.W.B. ass'y(c･6) off.

5-2.Scart P.W.B. ass'y (1)Remove 2 screws(s･5) on the rear side.

(2)Disconnect [CX053] from the Audio P.W.B. ass'



(GU-3614-1)and [CX121] from the Video P.W.B.

ass'y(GU-3613-2).

(3)Take the Scart P.W.B. ass'y(c･6) off.

DVD-3910

5-1.Video 基板 (1)背面側から s･1 のねじ 6 本と s･5 のねじ 2(国内:3)本と

s･6 のナット 2 本と天面から s･3 のねじ 2 本をはずします。

(2)ﾋﾞﾃﾞｵ基板 ass'y(GU-3613-3：HDMI 基板 ass'y)より

ﾜｲﾔｰ[CY174] をはずします。 (3)ｃ･6：VideoP.W.B.ass'y をはずします。  5-2.Scart 基板 (1)背面側から s･5 のねじ 2 本をはずします。 (2)ｵｰﾃﾞｨｵ基板 ass'y(GU-3614-1)よりﾜｲﾔｰ[CX053]を、ﾋﾞﾃﾞ

ｵ基板 ass'y(GU-3613-2)より[CX121]をはずします。 (3)c･7：ScartP.W.B.ass'y をはずします。  

c･7：Scart P.W.B. ass'y( only Europe )

c･6：

Video P.W.B. ass'y

ｓ･5( only Europe )

ｓ･6

ｓ･5

ｓ･1

6.Audio P.W.B. ass'y

(1)Remove 2 side screws(s･1) and 4 side screw(s･5)

and 2 top screws(s･3).

(2)Disconnect the wire [CY061][CY072][CY332]

connecting ｃ･8 ：Audio P.W.B. ass'y. Disconnect

1P-3P EH CON.CORD from the EH base (onl

JAPAN).

(3)Detach the c･8 : Audio P.W.B. ass'y.

ｓ･3

ｓ･5( only Japan )

(1)背面からｓ･1 のねじ 2 本とｓ･5 のねじ 4 本と天面か

(2)ｃ･8：ｵｰﾃﾞｨｵ基板 ass'y からﾜｲﾔｰ[CY061] [CY072]

(3)ｃ･8：ｵｰﾃﾞｨｵ基板 ass'y をはずします。

s･1：（Tighten-torque） s･3：締結トルク：0.5Nm （Tighten-torque） s･5：締結トルク：0.35Nm （Tighten-torque） s･6：締結トルク：0.35Nm （Tighten-torque）

らｓ･3 のねじ 2 本をはずします。

[CY332]をはずします。国内モデルのみ 1P-3P EH CON.CORD を EH ﾍﾞｰｽから外します。

：0.5Nm

c：1P-3P EH CON.CORD (only JAPAN)

c･8：Audio P.W.B. ass'y ｓ･3

ｓ･1

ｓ･5

s･1：（Tighten-torque） s･3：締結トルク：0.5Nm （Tighten-torque） s･5：締結トルク：0.35Nm （Tighten-torque）

：0.5Nm

7

7.IEEE1394 sub ass'y

締結トルク

(1)Remove 2 rear screws(s･1) and 1 top screw(s･3).

(2)Disconnect [CY071] [CY173] [CY191]. (3)Remove 2 top screws(s･1) . (4)Take the IEEE1394 P.W.B. ass'y(c･9) off.

DVD-3910

(1)背面の s･1 のねじ 2 本と天面の s･3 のねじ 1 本をはず

します。 (2)ﾜｲﾔｰ [CY071][CY173][CY191] をはずします。 (3)天面から s･1 のねじ 2 本をはずします。 (4)ｃ･9：IEEE1394P.W.B.ass'y をはずします。  

ｓ･3

c･9：IEEE1394

P. W . B . ass'y



ｓ･1

m･4：Ieee1394 bottom Shield

8.System P.W.B. ass'y

(1)Remove 1 screw(s･1) , 2 screw(s･5) and 2 nuts (s･6) on the rear and 6 top screws(s･3).

(2)Disconnect [CY131]. (3)Detach the c･10 : System P.W.B. ass'y.

ｓ･1

ｐ：BASS RUBBER(S) (only JAPAN)

ｍ･3：Ieee1394 top Shield

s･1：（Tighten-torque） s･3：締結トルク：0.5Nm （Tighten-torque）

(1)背面からｓ･1 のねじ 1 本とｓ･5 のねじ 2 本と s･6 の

ナット 2 本と天面からｓ･3 のねじ 6 本をはずします。 (2)ﾜｲﾔｰ[CY131] をはずします。 (3)ｃ･10：ｼｽﾃﾑ基板 ass'y をはずします。

：0.5Nm

c･10：System P.W.B. ass'y

ｓ･6

ｓ･1

ｓ･5

ｓ･3

s･1：（Tighten-torque） s･3：締結トルク：0.5Nm （Tighten-torque） s･5：締結トルク：0.35Nm （Tighten-torque） s･6：締結トルク：0.35Nm （Tighten-torque）

：0.5Nm

8

9.Rear panel and Mecha base

締結トルク

9-1.Rear panel (1)Remove 5 rear screws(s･1) and and 2 top screws

(s･1).

(2)Take the Rear panel(m･5) off.

9-2.Mecha base (1)Remove 6 screws(s･1) on the top side. (2)Detach 1 P.W.B. support(p･1) on the bottom. (3)Take the Mecha base(m･6) off.

p：BASS RUBBER(L) (only JAPAN)



m･5：Rear panel

DVD-3910

9-1.ﾘｱﾊﾟﾈﾙ (1)背面側から s･1 のねじ 5 本と天面から s･1 のねじ 2 本

をはずします。 (2)m･5：Rearpanel をはずします。  9-2.ﾒｶﾍﾞｰｽ (1)天面側から s･1 のねじ 6 本をはずします。 (2)底面から P.W.B.ｻﾎﾟｰﾄをはずします。

(3)ｍ･6：Mechabase をはずします。 

ｓ･1

m･6：Mecha base

ｓ･1

10.Chassis & Bottom cover

10-1.Bottom cover (1)Remove 4 bottom screws(s･3) from the Foot ass'y. (2)Take the Foot ass'y(p･2) off. (3)Remove 12 bottom screws(s･1). (4)Take the Bottom cover(m･7) off.

10-2.Chassis (1)Detach 6 P.W.B. spacer (p･3) on the bottom. (2)Take the Chassis(m･8) off.

ｓ･3

p･2：Foot ass'y

ｓ･3

p･1：P.W.B. support

s･1：（Tighten-torque）

10-1.ﾎﾞﾄﾑｶﾊﾞｰ (1)底面のﾌｯﾄ ass'y からｓ･3 のねじ 4 本をはずします。 (2)p･2：ﾌｯﾄ ass'y4 個をはずします。 (3)底面からｓ･1 のねじ 12 本をはずします。 (4)m･7：ﾎﾞﾄﾑｶﾊﾞｰをはずします。  10-2.ｼｬｰｼ (1)底面から p･3：P.W.B.spacer6 個をはずします。 (2)m･8：ｼｬｰｼをはずします。

m･7：Bottom cover

ｓ･3

：0.5Nm

p･3：P.W.B. spacer

The others screws：s･1

m･8：Chassis

ｓ･3

9

p･2：Foot ass'y

s･3：（Tighten-torque）

p･3：P.W.B. spacer

：0.5Nm

11.Parts on Front panel sub ass'y(a.1)

r

締結トルク

y

11- 1.Display P.W.B. ass'y (1)Remove 7 screws(s･7).

(2)Disconnect [CX052] . (3)Detach D12mm knob ass'y(c･11). (4)Take the Display P.W.B. ass'y(c･12) off.

11-2.Power SW-1 P.W.B. ass'y (1)Remove 2 screws(s･7). (2)Take the Power SW-1 P.W.B. ass'y(c･13) off. (3)Take the Power knob(MAIN) ass'y(c･14) off.

11-3.Power SW-2 P.W.B. ass'y (1)Remove 4 screws(s･7). (2)Take the Power SW-2 P.W.B. ass'y(c･15) off. (3)Take the Power knob(SUB) ass'y(c･16) off. (4)Detach the Lens(p･4).

11-4.Blind ass'y (1)Remove 2 screws(s･8). (2)Take the Spring(m･9) and the Blind ass'y(p･5) off.

11-5.Inner panel

(1)Detach 4 top hooks and 4 rear hooks. (2)Take the Inner panel(p･6) off.

11-6.Front panel (1)Detach the Part of Inner panel(p ･ 7) and rubbe

sheets(p･8,9) by minus(–) driver or etc..

DVD-3910

11-1.ﾃﾞｨｽﾌﾟﾚｲ基板 (1)s･7 のねじ 10 本をはずします。 (2)ﾜｲﾔｰ [CX052] をはずします。 (3)c･11：D12mm ﾉﾌﾞ ass'y をはずします。 (4)c･12：ﾃﾞｨｽﾌﾟﾚｲ基板をはずします。  11-2.電源 SW-1 基板 (1)s･7 のねじ 2 本をはずします。 (2)c･13：電源 SW-1 基板をはずします。 (3)c･14：電源 MAIN ﾎﾞﾀﾝをはずします。  11-3.電源 SW-2 基板 (1)s･7 のねじ 4 本をはずします。 (2)c･15：電源 SW-2 基板をはずします。 (3)c･16：電源 SUB ﾎﾞﾀﾝをはずします。 (4)p･4：ﾚﾝｽﾞをはずします。  11-4.ﾌﾞﾗｲﾝﾄﾞ ass'y (1)s･8 のねじ 2 本をはずします。 (2)m9･：ｽﾌﾟﾘﾝｸﾞと p･5：ﾌﾞﾗｲﾝﾄﾞ ass'y をはずします。  11-5.ｲﾝﾅｰﾊﾟﾈﾙ (1)上下各 4 個のﾌｯｸをはずします。 (2)p･6：ｲﾝﾅｰﾊﾟﾈﾙをはずします。  11-6.ﾌﾛﾝﾄﾊﾟﾈﾙ (1)p･7：ｲﾝﾅｰﾊﾟﾈﾙｶｯﾄ部品や p･8,9：ﾗﾊﾞｰをﾏｲﾅｽﾄﾞﾗｲﾊﾞｰ

等ではずします。



p･5：Blind ass'y

c･11：Display P.W.B. ass'y

p･6：Inner panel

p･7：Part of Inner panel

c･11：D12mm knob ass'y

m･9：Spring

ｓ･7

ｓ･8

ｓ･7

m･10：Front panel

ｓ･7ｓ･8

c13･：Power-1 P.W.B. ass'y

c･14：Power knob(MAIN) ass'

c15･：Power-2 P.W.B. ass'y

c･16：Power knob(SUB) ass'y

p･4：Lens

s･7：（Tighten-torque） s･8：締結トルク：0.35Nm （Tighten-torque）

p･8：Rubber sheet p･9：Rubber sheet

：0.35Nm

10

DVD-3910

DVD laser drive current measuring points

[DVD] Iop silk point

[CD] Iop silk point

GU-3512 P.W.B. (foil side)

CD laser drive current measuring points

Laser current initial value on the rear of mechanism

DVD

mA

CD

mA

Iop Measurement (Judging for Traverse Unit Replacement)

As to deciding whether optical pickup is defect or not (for replacing traverse unit), follow the steps below.

1. Judging Step

(1) Disc play abnormal

Problems such as disc no read, unsteady playback, etc.

(2) Laser drive current (Iop) check

Check Iop according to the measuring method described in step 2 below. If the checked value is 1.5 times or more than the initial Iop indicated on the rear of mechanism unit, the traverse unit should be replaced.

(3) Replacing traverse unit

Referring to “How to Replace Traverse Unit”, replace the traverse unit. No mechanism adjustment is required as the whole unit is replaced with a new one.

DVD

CD

Laser current initial value on the rear of mechanism

2. Iop Measuring Method

DVD laser drive current measuring points

[DVD] Iop silk point

mA mA

󰶚ቯ㧔࠻࡜ࡃ࡯࡙ࠬ࠾࠶࠻឵್ቯ㧕

Iop

光ピックアップの故障（トラバースユニットの交換）判定は、下記の手順で行ってください。

判定手順

1.

ディスク再生不具合

(1)

ディスクを読み込まない、スムーズに再生しない等の不具合発生

レーザー駆動電流（

(2)

下記、2項のメカ背面のレーザー電流初期値のトラバースユニット交換の目安となります。

トラバースユニット交換

(3)

「トラバースユニットのはずしかた」を参照して、トラバースユ

ニットを交換します。トラバースユニット単位での交換となりますので、メカ部の調整は不要です。

の測定方法

2. Iop

Iop

）の確認

Iop

測定方法に従い電流値を確認する。

倍以上になっている場合は、

1.5

CD laser drive current measuring points

[CD] Iop silk point

GU-3512 P.W.B. (foil side)

(1) DVD laser drive current measurement

• Playback the title-1/chapter-1 of DVDT-S01 or commercially available DVD disc.

• Connect an oscilloscope to the test point above and measure the voltage.

• DVD laser drive current is calculated by: Iop = Measured Voltage Value / 14 (Resistance Value)

(2) CD laser drive current measurement

• Playback the track-1 of TCD-784 or commercially available CD disc.

• Connect an oscilloscope to the test point above and measure the voltage.

• CD laser drive current is calculated by:

Iop = Measured Voltage Value / 12 (Resistance Value)

(1) DVD

(2) CD

レーザー駆動電流の測定

・

DVDT-S01

・上記テストポイントをオシロスコープに接続し、電圧値を測定する。・

DVD

レーザー駆動電流の測定

・

TCD-784

・上記テストポイントをオシロスコープに接続し、電圧値を測定する。・CDレーザー駆動電流値＝「測定した電圧値」／

または市販

レーザー駆動電流値＝「測定した電圧値」／

または同等市販CDディスクのトラック1を再生する。

ディスクのタイトル1・チャプター1を再生する。

DVD

「14（合成抵抗値）」

「12（合成抵抗値）」

11

DIAGNOSTICS OF OPTICAL PICKUP AND REPLACING TRAVERSE UNIT

1.

శࡇ࠶ࠢࠕ࠶ࡊߩขᛒᵈᗧ

レーザーダイオードの破壊防止。光素子ユニットを交換するときは、以下を遵守してください。

(1)

光素子ユニットの接続ケーブルをはずすときは、静電対策を行ったデスクの上で作業をしてください。

(2)

作業者はリストストラップを使用してください。

(3)

レーザーダイオードの破壊防止のため、24Ｐ

FFC

ケーブルをはずす前にランドを半田付けショートしてください。

(4)

光素子ユニットのコネクタ部に触れないでください。

2.

࠻࡜ࡃ࡯࡙ࠬ࠾࠶࠻ߩ឵

交換時、以下の手順で故障診断をおこなってください。



レーザー駆動電流の現在値が初期値の

150

％以上なら、ピックアップを交換してください。

ピックアップ交換の場合はトラバースユニットを交換し、調整は不要です。初期値はメカ後部のラベルに表示されています。

శࡇ࠶ࠢࠕ࠶ࡊขᛒᵈᗧߣ឵

"NO DISC"

⴫␜ޔౣ↢⦟╬



࡟࡯ࠩ࡯㚟േ㔚ᵹ࠴ࠚ࠶ࠢ

 HF

ାภ࠴ࠚ࠶ࠢ

࠻࡜ࡃ࡯࡙ࠬ࠾࠶࠻឵

󱂜࿷୯㧦ೋᦼ୯ߩ

150%

એ

឵ᓟޔ࡟࡯ࠩ࡯㚟േ㔚ᵹࠍ࠴ࠚ࠶ࠢߒ߹ߔޕ 󱂜࿷୯߇

80mA

એߥࠄᣂ࡜ࡌ࡞߳ᚻᦠ߈ߒޔ

ᣥ࡜ࡌ࡞ߩߦ⾍ࠅߟߌ߹ߔޕ

󱂜࿷୯߇

80mA

એߥࠄޔౣᐲ࠻࡜ࡃ࡯࡙ࠬ࠾࠶࠻ࠍ឵ߒߡߊߛߐ޿ޕ ޓ ේ࿃㧦឵ᤨޔ㕒㔚⎕უߐࠇߚޕ

1. Note for Handling the Laser Pick-up

The protection for the damage of laser diode. If you want to change the optical device unit from any other units, you must keep the following. (1) It should be done at the desk already took measures the static electricity in care of removing the OPU's

(Optical device unit) connector cable. (2) Workers should be put on the "Earth Band". (3) It shold be done to add the solder to the short land to prevent the broken Laser diode before removing the

24P FFC cable. (4) Don't touch OPU's connector parts carelessly.

2. Optical Pick-up Diagnostics and Replacement

When repairing, carry out failure diagnostics by following the procedure described below. If the present value of the laser drive current is 150% up to initial value, it is the point of the pickup replacement. In case of the pickup replacement, replace the Traverse Unit with no adjustment. The initial value is indicated on the label on back side of Mecha.

NO DISC indicated, Playback not smooth, etc.

DVD-3910



Laser drive current check



HF signal check

Present value: 150% up to initial value

Traverse Unit replacement (refer to page 10)

Laser drive current check after replacement. If the present value is less than 80mA, write on the new label by hand, put on the new label over the old label.

If the present value exceeds 80mA, replace the Traverse Unit with a new one. Cause: Damaged electrostatically when replaced.

12

How to Replace Traverse Unit

࠻࡜ࡃ࡯࡙ࠬ࠾࠶࠻ߩ឵ᣇᴺ

1.

࠻࡜ࡃ࡯࡙ࠬ࠾࠶࠻឵Ḱ஻

(1)

クランプベースダンパーのはずしかた

2.6mm

マシンネジ

(a)4

本をはずして、クランプベー

スダンパーを上へはずします。

(2)

クランプベースのはずしかた

3mmP

タイトネジ

(b)6

本をはずして、クランプベー

スを上へはずします。

(3)

ローダーを開くメカユニットの左側角孔より、スライダーを定規やドライバーでトラバース部が下がってローダーが少し開くまで押します。

(4)

ローダーのはずしかた・ローダー左のホルダー部より

3mmP

タイトネジ

(c)2

本をはずします。

・ローダー右側より

3mmP

タイトネジ

(d)2

本をはずし、ベアリングプレートを上へはずします。・ローダーを前面へ引出し、止まった所で上へはずします。

(5)

ピックアップのショートトラバースユニットのピックアップの静電保護の為、2ヶ所ショートします。

（ショート箇所は、右図参照）

(6)

メイン基板

ASS'Y

のはずしかた

3mmP

タイトネジ

(e)4

本をはずし、基板を下へはず

します。

2.

࠻࡜ࡃ࡯࡙ࠬ࠾࠶࠻ߩ឵

(1)

トラバースユニットのワイヤーをはずす

・

CX241

：ピック用

24P-FFC

・

CX151

：スピンドル用

15P-FFC

・

CX031：PU

スライド用

3P-PH

ワイヤー

(2)

トラバースユニットをはずす特殊ネジ

(f)4

本とダンパー4個をはずし、トラバースユ

ニットを上にはずします。

(3)

トラバースユニットの取付逆の手順で、トラバースユニットを取付けます。

1. Preparing for Replacement

(1) Removing Clamp Base Damper

Remove 4 pcs of 2.6mm machine screw (a), and detach the Clamp Base Damper upward.

(2) Removing Clamp Base

Remove 6 pcs of 3mm P-tight screw (b), and detach the Clamp Base upward.

(3) Ejecting Loader

Through the left rectangular hole of the Mechanism Unit, push the slider with a ruler or driver until the Traverse portion lowers and the Loader comes out a little.

(4) Removing Loader

• Remove 2 pcs of 3mm P-tight screw (c) on the Loader Holder left.

• Remove 2 pcs of 3mm P-tight screw (d) on the Loader Holder right, then pull up the Bearing Plate.

• Fully pull out the Loader forward, and lift up to take it out.

(5) Shorting Pickup

To protect the Pickup from static electricity, short-circuit 2 positions as shown in figure.

(6) Removing Main P.W.B. Ass'y

Remove 4 pcs of 3mm P-tight screw (e), and detach the Main P.W.B. Ass'y downward.

(b)

Holder

A

(e)

(c)

(a)

(3)

DVD-3910

Clamp Base Damper

Clamp Base

(d)

Bearing Plate

Loader

(4)

Main P.W.B. Ass'y

Solder to short-circuit (CD)

Short-circuit with solder (enlarged fig. A)

(1) Removing Wires

• CX241: 24P-FFC for Pickup

• CX151: 15P-FFC for Spindle

• CX031: 3P-PH wire for PU Slide

(2) Removing Traverse Unit

(3) Mounting Traverse Unit

Remove 4 pcs of special screw (f) and dampers, then take out the Traverse Unit upward.

Mount the Traverse Unit following the reverse order.

2. Replacing Traverse Unit

(f)

Traverse Unit

Damper

13

3. Installing Loader

4.

⚵┙

(1)

メイン基板

ASS'Y

の取付

3mmP

タイトネジ

(e)4

本で基板を取付けます。

(2)

ピックアップのショートはずしピックアップの

24PFFC

を基板へ接続後、2ヶ所のショー

トをはずします。

(3)

クランプベースの仮置きレーザーから目を保護する為、クランプベースを仮置きします。

(4)

トラバースユニットをアップする。メカユニットの下記ワイヤーを接続し、メカを動作させます。

・

CX141

：電源用の

14P-PH

ワイヤー接続

・

CX131

：ディスプレイ基板からの

13P-FFC

ワイヤー接続

セットの電源を入れ、ローダー開閉ボタンで、

CLOSE

さ

せます。トラバースユニットがアップします。

（

0h00m00s

：表示）ローダーを前面へ引出し、止まった所で上へはずします。

3.

ࡠ࡯࠳࡯ߩ⚵┙

(1)

ローダーの挿入ローダーを矢印方向へ止まるまで押しこみます。ローダを組込時、プレートギアのボスがトレイ裏面の溝に合う様にプレートギアを右側へ寄せておきます。（右図参照）

(2)

ローダーの取付

(c)、(d)

のネジ各2本を取付ます。

4.

⚵┙

(1)

メイン基板

ASS'Y

の取付

3mmP

タイトネジ

(e)4

本で基板を取付けます。

(2)

ピックアップのショートはずしピックアップの

24PFFC

を基板へ接続後、2ヶ所のショー

トをはずします。

(3)

クランプベースの仮置きレーザーから目を保護する為、クランプベースを仮置きします。

(4)

トラバースユニットをアップする。メカユニットの下記ワイヤーを接続し、メカを動作させます。

・

CX141

：電源用の

14P-PH

ワイヤー接続

・

CX131

：ディスプレイ基板からの

13P-FFC

ワイヤー接続

セットの電源を入れ、ローダー開閉ボタンで、

CLOSE

さ

せます。トラバースユニットがアップします。

（

0h00m00s

：表示）ローダーを前面へ引出し、止まった所で上へはずします。

3.

ࡠ࡯࠳࡯ߩ⚵┙

(1)

ローダーの挿入ローダーを矢印方向へ止まるまで押しこみます。ローダを組込時、プレートギアのボスがトレイ裏面の溝に合う様にプレートギアを右側へ寄せておきます。（右図参照）

(2)

ローダーの取付

(c)、(d)

のネジ各2本を取付ます。

(1) Inserting Loader

(2) Fixing Loader

Set and push the Loader to the arrow direction until it stops. When installing the Loader, move the Plate Gear to right beforehand so as that the boss of the Plate Gear fits in the backside groove of the Loader. (See figure right)

Fix the Loader with each 2 screws (c) and (d).

DVD-3910

Plate Gear

Boss

Groove

(d)

Bearing Plate

(c)

Loader

4. Assembly (1)

(1) Assembling Main P.W.B. Ass'y

Fix the Main P.W.B. Ass'y with 4 pcs of 3mm P-tight screw (e).

(2) Removing Pickup-short Solder

After connecting 24P-FFC of the Pickup with P.W.B., remove solder from 2 shorted positions.

(3) Temporary Positioning Clamp Base

To protect your eyes from laser light, put the Clamp Base temporarily.

(4) Positioning up Traverse Unit

Connect the following wires of the Mechanism Unit, and operate it.

• CX141: 14P-PH wire for power

• CX131: 13P-FFC wire from Display P.W.B. Turn on the power to the unit, and press "OPEN/CLOSE" button to close the Loader. The Traverse Unit rises up. (display: 0h00m00s) Pull out the Loader forward, and lift up to take it out.

Clamp Base

(e)

Main P.W.B. Ass'y

14

5.

⚵┙

(2)

(1)

クランプベースダンパーへのアセクロ貼付クランプベースダンパー裏面の突起3箇所へアセテートクロステープを貼付します。

(2)

クランプベースの取付クランプベースダンパーを挿入し、3箇所の突起でクランパーの位置決めを行います。

3mmP

タイトネジ

(b)6

本

で、クランプベースを取付けます。

6.

⚵┙

(3)

(1)

クランプベースダンパーからアセクロはがしクランプベースダンパー裏面の突起3箇所からアセテートクロステープをはがします。

(2)

クランプダンパーベースの取付クランプベースダンパーを、クランプベースに先程と反対向きに挿入します。

3mmS

タイトネジ

(a)4

本で、ク

ランプベースダンパーを取付けます。

5. Assembly (2)

(1) Attaching Tape to Clamp Base Damper

Attach acetate cloth tape to 3 projections of the Clamp Base Damper backside.

(2) Assembling Clamp Base

Set the Clamp Base Damper with positioning for clamper by 3 projections. Fix the Clamp Base with 6 pcs of 3mm P-tight screw (b).

DVD-3910

Acetate Cloth Tape

Clamp Base Damper

(b)

Clamp Base

6. Assembly (3)

(1) Detaching Tape from Clamp Base Damper

Detach acetate cloth tape from 3 projections of the Clamp Base Damper backside.

(2) Assembling Clamp Base Damper

Set the Clamp Base Damper to the Clamp Base contrary to the direction set in step above. Fix the Clamp Base Damper with 4 pcs of 3mm S-tight screw (a).

(a)

Clamp Base Damper

15

DVD-3910

SERVICE MODE

1. Aging Mode

(1) preparation

(a) Equipment used: Any one of DVD Karaoke Disc (contain-

ing more than 10 titles).

(b) Unit setting : No spec other than the following procedure

(Aging mode). At the tray open status, press the “POWER” button to turn on the power while pressing the “PLAY” and “OPEN/CLOSE” buttons for DVD operation simulta-

neously. mark on the FL lights, and the unit is set to the heat run mode.

(2) procedure

(a) According the above, set to the aging mode. (b) Set a DVD Karaoke disc to the tray and press the “PLAY”

button once. mark on the FL blinks, and aging operation(after playback title-1 and title-10 of the disc, the tray open/close is made automatically, then playback the title-1 again) starts. This aging operation continues automatically until it is stopped or it stops caused by an error. In case of some error in DVD, the following error messages are displayed on the FL.

No Error contents FL display

1 Bad Disc ERROR 02

2 Focus Error ERROR 04

3 Read Error ERROR 03

4 Tracking Error ERROR 04

5Tray Error ERROR 05

6 Navigation Pack Read Error ERROR 06

7 Cmmunication Error ERROR07

サービスモードについて

1.エージングモード

(1) 準備

(a) 使用機器：DVD カラオケディスク（10 タイトル以上

の物）。

(b) 本体設定：下記設定以外規定無。

（エージングモード）

トレイを開けた状態で DVD ユニットの「再生ボタン」 +「開 / 閉ボタン」を同時に押しながら「電源ボタン」

を押してセットの電源を入れると、FL 管のマークが点灯し、ヒートランモードに設定される。

(2) 手順

(a) 上記手順でエージングモードに設定する。 (b) トレイに DVD カラオケディスクを入れ、「再生ボタン」

を 1 回押して、FL 管のマークが点滅になると、

「ディスクのタイトル 1 とタイトル 10 を再生した後、

トレイを自動で開 / 閉し、再度タイトル 1 の再生を行う。」エージング動作になります。停止させるか、エラーにて停止するまでこの動作を自動で繰り返します。 DVD 部にエラーが発生した場合は、FL 管に下表のエラーが表示されます。

No. エラー内容 FL 管表示

1 不良ディスク 2 フォーカスエラー ERROR 04 3 リードエラー 4 トラッキングエラー 5 トレイエラー 6 ナビゲーションパックエラー 7 コマンド通信エラー

ERROR 02

ERROR 03

ERROR 04

ERROR 05

ERROR 06

ERROR 07

2. Initial Setting Mode

(1) Preparation

(a) Equipment used: None (b) Unit setting: No spec other than the following procedure

(2) Procedure

(a) Initialize the DVD player when µcom, peripheral parts of

µcom, or Main P.W.B. has been replaced in servicing.

(b) Carry out the following to restore factory setting mode. At

the player stop condition, press 3 buttons for DVD oper-

ation(“PLAY”,”OPEN/CLOSE”, and “ SKIP”) until “INITIALIZE” appears and disappears in the FL. (“Initialized” appears and disappears on the TV screen.)

(c) All user setting will be lost and its factory setting will be

restored when this initialization is made. Be sure to memorize your setting for restoring again after the initialization.

2.初期設定モード

(1) 準備

(a) 使用機器：無 (b) 本体設定：下記手順以外規定無。

(2) 手順

(a) サービスにて、マイコンやマイコン周辺部分やメイン

基板を交換した場合は、ＤＶＤプレーヤーの初期化を行ってください。

(b) セットの初期化を下記の手順で行い、工場出荷モード

に設定する。セットが停止状態にて、ＤＶＤ操作部の「再生ボタ

ン」+「開 / 閉ボタン」+「 ( スキップ）ボタン」の 3 重押しをＦＬ管に "INITIALIZE" が表示され消える

まで押します。（ＴＶ画面には初期化しましたが表示され消えます。）

(c) 初期化を行うとお客様が設定した内容が工場出荷状態

に戻りますので、あらかじめ設定内容を控えておき初期化後に再設定してください。

16

DVD-3910

3. μ-Com Firm Check Mode

(1) Preparation

(a) Equipment used: None (b) Unit setting: No spec other than the following procedure.

(2) Procedure

(a) Press the “POWER” button to turn on the power while

pressing the “PLAY” and “OPEN/CLOSE” buttons for DVD operation simultaneously.

(b) FL all light mode.

This mode is for detecting FL defects. Press “STILL/

PAUSE ” on the remote control unit once to light all FL segments.

(c) DVD µcom and main unit µcom firm check mode. This

mode is for displaying the status of each µcom employed.

•DVD µcom firm: Press the 3, 2, 6, 5 buttons on the remote Then press the “MENU” button or “PUSH ENTER” button.

• Each time the “MENU” button on the remote control unit or “PUSH ENTER” button is pressed, µcom firm is displayed one after another.

Ex.: [DRV 6334-1, B/E 030825, SYSTEM 0001, DSP1 6332, DSP2 6333]

Set Serial

No.

(lower 5

digits)

1 00001- 030825 6334 6542 6332 6333

2

3

4

Drive

µcom

B/E

µcom

SYSTEM

µcom

DSP1 DSP2

3.マイコンファームチェックモード

(1) 準備

(a) 使用機器：無 (b) 本体設定：下記手順以外規定無。

(2) 手順

(a) ＤＶＤ操作部の「再生ボタン」と「開 / 閉ボタン」を

押しながらセットの「電源ボタン」を押し電源を入れます。

(b) ＦＬ管全点灯モード。

ＦＬ管の故障判別用のモードで、リモコンの「スティル / ポーズボタン」を押すとＦＬ管が全点灯します。

(c) ＤＶＤマイコン及び本体マイコンのファーム確認モー

ド搭載されている各マイコンのファーム状態を表示します。

･ＤＶＤマイコンのファーム：リモコンの「メニューボタ

ン」または、本体の PUSHENTER ボタンを押します。

･リモコンのメニューボタンまたは、本体の PUSHENTER

ボタンを押すたびにマイコンファームを次々と表示します。

表示例：〔DRV6334-1､B/E030825､SYSTEM0001､Dsp1 6332 ､ Dsp26333〕

セットのシリアル番号 ( 下 5 桁)

1 00001 〜 2

3 4

ドライブマイコン

030825 6334 6542 6332 6333

B/E マイコンシステム

マイコン

Dsp1 Dsp2

17

DVD-3910

4. Setting up the test mode

(1) Setting up ※ Firmware Change needs.

• In order to set up the test mode, you press STOP button and REV button simultaneously in the heat-run mode.Fundamentaly, you can set up the test mode at the stop state after disc loading. (Heat-run mode is set up by pressing PLAY button,holding OPEN/CLOSE button. If it becomes heat run mode, PLAY indicator and PAUSE indicator will light up.)

LOADING display

↓

FL display (The display part of 13 digits)

12345678910111213 T

(2) Mode Select

• There are two, servo adjustment value display mode and trace mode (error rate display), in the mode.

(a) If the REV button or the FWD button is pushed in the test

mode, it will become servo adjustment value display mode.

FL display (The display part of 13 digits)

12345678910111213 Ｔ３

(b) If the REV button or the FWD button is pushed again, it

will become the trace mode (error rate display).

FL display (The display part of 13 digits)

12345678910111213 Ｔ７

(3) Mode decision

• The mode will be decided if the PLAY button is pushed in the state where the mode is chosen.

(a) In the case of servo adjustment value display mode, a

focus offset adjustment value is displayed.

FL display (The display part of 13 digits)

12345678910111213 Ｔ３１ｎｎｎｎｎｎｎｎｎｎ

(n:adjustment value)

(b) In the case of trace mode (error rate display), trace of

the circumference in one layer is chosen.

FL display (The display part of 13 digits)

12345678910111213 Ｔ７１ＦＦＦＦＦＦＦＦＦＦ

(F: An address and an error rate display F at the time of undecided.)

(4) Change within the mode

• If the REV button or the FWD button is pushed in the state where the mode is decided, a change within the mode will be made.

(a) In the case of servo adjustment value display mode (re-

fer to table 1 servo adjustment value display mode details)

FL display (The display part of 13 digits)

12345678910111213 ＴＸＸｎｎｎｎｎｎｎｎｎｎ

(XX:selection mode [31--62] n:adjustment value)

4. テストモード

(1) テストモードへの投入※ファーム変更が必要です。

･テストモードへの投入はヒートランモード時に STOP

キーと REV キーを 2 重押しすることで行う。基本的にディスクローディング後の停止状態でテストモードに投入する。( ヒートランモードへの投入は OPEN/CLOSE キーと PLAY キーを 2 重押しすることで行う。ヒートランモードになると PLAY インジケータと PAUSE インジケータが点灯する。）

LOADING 表示

↓

FL 管の表示 (13 桁の表示部 )

12345678910111213 T

(2) モードの選択

･モードには、サーボ調整値表示モードとトレースモード

( エラーレート表示 ) の 2 つがある。

(a) テストモード投入後に REV キー又は FWD キーを押す

と、サーボ調整値表示モードになる。

FL 管の表示 (13 桁の表示部 )

12345678910111213 Ｔ３

(b) 再度 REV キー又は FWD キーを押すとトレースモード

( エラーレート表示 ) になる。

FL 管の表示 (13 桁の表示部 )

12345678910111213 Ｔ７

(3) モードの確定

･モードを選択してある状態で PLAY キーを押すとモード

を確定する。

(a) サーボ調整値表示モードの場合は、フォーカスオフ

セット調整値を表示する。

FL 管の表示 (13 桁の表示部 )

12345678910111213 Ｔ３１ｎｎｎｎｎｎｎｎｎｎ

(n: 調整値 )

(b) トレースモード ( エラーレート表示 ) の場合は、１層

内周のトレースを選択する。

FL 管の表示 (13 桁の表示部 )

12345678910111213 Ｔ７１ＦＦＦＦＦＦＦＦＦＦ

(Ｆ: アドレス及びエラーレートは未確定時、Ｆを表示する。)

(4) モード内での変更

･モードを確定してある状態で REV キー又は FWD キーを

押すとモード内での変更を行う。

(a) サーボ調整値表示モードの場合（表１サーボ調整値表

示モード詳細参照）

FL 管の表示 (13 桁の表示部 )

12345678910111213 ＴＸＸｎｎｎｎｎｎｎｎｎｎ

(ＸＸ: 選択モード [31 〜 62]、n: 調整値 )

18

DVD-3910

(b) In the case of trace mode (error rate display) (refer to ta-

ble 2 trace mode details)

FL display (The display part of 13 digits)

12345678910111213 ＴＹＹＦＦＦＦＦＦＦＦＦＦ

(YY: select mode [71--94] ,F: address and an error rate display F at the time of undecided)

(5) Execution of trace mode (error rate display)

(refer to table 2 trace mode details)

• Trace will be performed if the PLAY button is pushed after choosing operation.

FL display (The display part of 13 digits)

12345678910111213 ＴＹＹｍｍｍｍｍｍｌｌｌｌ

(YY:select mode[71--94],m:address[PBA][HEX], l:error rate[COUNT/SEC][HEX]) (Note) Renewal of data is carried out for every CD:300 frame and

DVD:85ECC block.

• The mode chosen when selection mode was changed into the trace execution and the PLAY button was pushed is performed from the beginning.When the PLAY button is pushed without changing selection mode, the mode under selection is performed from the beginning.(If the PLAY button is pushed, the address corresponding to the chosen mode will be searched again.)

(b) トレースモード ( エラーレート表示 ) の場合（表 2 ト

レースモード詳細参照）

FL 管の表示 (13 桁の表示部 )

12345678910111213 ＴＹＹＦＦＦＦＦＦＦＦＦＦ

(ＹＹ: 選択モード [71 〜 94]、Ｆ: アドレス及びエラーレートは未確定時、Ｆを表示する。)

(5) トレースモード ( エラーレート表示 ) の実行（

表 2 トレースモード詳細参照）

･動作を選択した後、PLAY キーを押すとトレースを実行

する。

FL 管の表示 (13 桁の表示部 )

12345678910111213 ＴＹＹｍｍｍｍｍｍｌｌｌｌ

(ＹＹ: 選択モード [71 〜 94]、ｍ: アドレス [PBA][HEX]、

ｌ: エラーレート [COUNT/SEC][HEX])

( 注 )CD:300 フレーム ,DVD:85ECC ブロック毎にデータ

更新する。

･トレース実行中に選択モードを変更し、PLAY キーを押

すと選択したモードを最初から実行する。選択モードを変更せずに PLAY キーを押した場合も、選択中のモードを最初から実行する。

（PLAY キーを押したら、選択しているモードに対

応したアドレスを再度サーチする。)

(6) Other operation

(a) If the STOP button is pushed into servo adjustment val-

ue display mode and trace mode (error rate display), it will return to the state at the time of a test mode injection.

FL display (The display part of 13 digits)

12345678910111213 Ｔ

(b) Push the OPEN/CLOSE button twice and carry out ser-

vo readjustment in OPEN operation ->CLOSE operation.

(It readjusts with test mode.)

OPEN display

↓

CLOSE display

↓

LOADING display

↓

FL display (The display part of 13 digits)

12345678910111213 Ｔ

(c) By pressing STOP button and REV button simulta-

neously in the test mode, it returns to heat-run mode.

(6) その他の動作

(a) サーボ調整値表示モード、トレースモード ( エラー

レート表示 ) 中に STOP キーを押すとテストモード投入時の状態に戻る。

FL 管の表示 (13 桁の表示部 ) 12345678910111213

Ｔ

(b) OPEN/CLOSE キーを 2 回押して、OPEN 動作→ CLOSE

動作で、サーボ再調整する。

( テストモードのまま再調整する。)

OPEN 表示 ↓ CLOSE 表示 ↓ LOADING 表示 ↓

FL 管の表示 (13 桁の表示部 )

12345678910111213 Ｔ

(c) テストモード中に STOP キーと REV キーの 2 重押し

( 投入時と同じキー ) で、ヒートランモードに戻る。

19

DVD-3910

(7) Test mode detailed table

Table 1: servo adjustment value display mode details

ＸＸ Contents

31 RFPFEOffset layer0 PIofCXD1881ARAnoffset valueand

32 RFP TE Bal

Gain

33 RFPTE Output

Gain

34 RFPTEOffset layer0 TE offset value of CXD1881AR is

35 DSPTEOffset layer0 TE offset value inside CXD1885Q is

36 FcsBias layer0 The focus bias value inside

37 FcsAGC layer0 Theinsidefocusgain(setting0x2000

38 TrkAGC layer0 The inside tracking gain (setting

39 PiOffset layer0 It is the parameter calculated inside

40 FEOffset layer0 It is the parameter calculated inside

41 SEOffset layer0 It is the parameter calculated inside

42 RFPFEOffset layer1 PI ofCXD1881ARAnoffset valueand

Contents supplementContentsexplanation

FEAnoffsetvalueisdisplayed. Pioffsetisshowninhigherrank 1Byte. FEoffsetisshowninlowrank1Byte.

layer0 TEbalancegainvalueofCXD1881AR

layer0 TEoutputgainvalueofCXD1881ARis

isdisplayed.

displayed.

CXD1885Qisdisplayed.

to 1) value of CXD1885Q is displayed.。 Therefore,0x1FF2andinthecaseof 0x2012,itisasfollows.   0x1FF2(8178) / 0x2000(8192) =

0.998291015625(fold)   0x2012(8210) / 0x2000(8192) =

1.002197265625(fold) Notes:Theinsideof()isadecimal systemequivalent.

0x2000 to 1) value of CXD1885Q is displayed.。 Therefore,0x1FF2andinthecaseof 0x2012,itisasfollows.   0x1FF2(8178) / 0x2000(8192) =

0.998291015625(fold)   0x2012(8210) / 0x2000(8192) =

1.002197265625(fold) Notes:Theinsideof()isadecimal systemequivalent

CXD1885Q. Thevaluedisplayedonasetservesas the number of complement of 2 of 2Bytes(es)doubled256. Avoltagevalueis6.25mVperbit.

FEAnoffsetvalueisdisplayed. Pioffsetisshowninhigherrank 1Byte. FEoffsetisshowninlowrank1Byte.

(7) テストモード詳細一覧表

表 1サーボ調整値表示モード詳細

ＸＸ内容内容補足 内容説明

31 RFPFEOffset レイヤ 0 CXD1881AR の PIオフセット値と FE

32 RFP TE Bal

Gain

33 RFPTE Output

Gain

34 RFPTEOffset レイヤ 0 CXD1881AR の TEオフセット値を表

35 DSPTEOffset レイヤ 0 CXD1885Q 内部の TE オフセット値を

36 FcsBias レイヤ 0 CXD1885Q 内部のフォーカスバイア

37 FcsAGC レイヤ 0 CXD1885Q 内部フォーカスゲイン

38 TrkAGC レイヤ 0 CXD1885Q内部トラッキングゲイン(0

39 PiOffset レイヤ0 CXD1885Q 内部で計算されるパラ

40 FEOffset レイヤ0 CXD1885Q 内部で計算されるパラ

41 SEOffset レイヤ0 CXD1885Q 内部で計算されるパラ

42 RFPFEOffset レイヤ 1 CXD1881AR の PIオフセット値と FE

レイヤ 0 CXD1881ARのTEバランスゲイン値を

レイヤ 0 CXD1881ARのTE出力ゲイン値を表示

オフセット値を表示。上位 1Byte に Pi オフセットを示す。下位 1Byte に FEオフセットを示す。

表示す。

す。

示。

表示。

ス値を表示。

(0x2000 を 1 として ) 値を表示。 0x1FF2 や 0x2012 の場合、以下のようになる。   0x1FF2(8178) / 0x2000(8192) =

0.998291015625( 倍 )   0x2012(8210) / 0x2000(8192) =

1.002197265625( 倍 ) 注 :() 内は 10 進換算値

x2000 を 1 として ) 値を表示。 0x1FF2 や 0x2012 の場合、以下のようになる。   0x1FF2(8178) / 0x2000(8192) =

0.998291015625( 倍 )   0x2012(8210) / 0x2000(8192) =

1.002197265625( 倍 ) 注 :() 内は 10 進換算値

メータ。セットに表示される値は、256 倍された 2Bytes の 2 の補数となる。電圧値は 1bit あたり 6.25mV。

オフセット値を表示。上位 1Byte に Pi オフセットを示す。下位 1Byte に FEオフセットを示す。

43 RFP TE Bal

Gain

44 RFPTE Output

Gain

45 RFPTEOffset layer1 TE offset value of CXD1881AR is

46 DSPTEOffset layer1 It is the parameter calculated inside

47 FcsBias layer1 Itistheparametercalculatedinside

layer1 TEbalancegainvalueofCXD1881AR

layer1 TEoutputgainvalueofCXD1881ARis

isdisplayed.

displayed.

CXD1885Q. Thevaluedisplayedonasetservesas the number of complement of 2 of 2Bytes(es)doubled256. Avoltagevalueis6.25mVperbit.

43 RFP TE Bal

Gain

44 RFPTE Output

Gain

45 RFPTEOffset レイヤ 1 CXD1881AR の TEオフセット値を表

46 DSPTEOffset レイヤ 1 CXD1885Q 内部で計算されるパラ

47 FcsBias レイヤ 1 CXD1885Q 内部で計算されるパラ

レイヤ 1 CXD1881ARのTEバランスゲイン値を

レイヤ 1 CXD1881AR の TE出力ゲイン値を表

表示。

示。

メータ。セットに表示される値は、256 倍された 2Bytes の 2 の補数となる。電圧値は 1bit あたり 6.25mV。

20

DVD-3910

48 FcsAGC layer1 Theinsidefocusgain(setting0x2000

49 TrkAGC layer1 The inside tracking gain (setting

50 PiOffset layer1 It is the parameter calculated inside

51 FEOffset layer1 It is the parameter calculated inside

52 SEOffset layer1 It is the parameter calculated inside

53 POerror

detection number

54 POuncorrect-

ableerror number

55 PIerrordetec-

tionnumber

56 PI uncorrect-

able error number

57 MirrCount Disc dis-

58 MirrWidth Disc dis-

59 FZCCount Disc dis-

60 PiLevel Disc dis-

61 DiscType DiscType Theyarethecontentsatthetimeof

62 POerror

detection numberand address

Errorrate It is invalid at the time of CD

ErrorRate ItisinvalidatthetimeofCD

ErrorRate CD:C1errordetectionnumber

ErrorRate CD:C2uncorrectableerrornumber

criminant

Errorrate PO error detection number is invalid

to1)valueofCXD1885Qisdisplayed. Therefore,0x1FF2andinthecaseof 0x2012,itisasfollows.   0x1FF2(8178) / 0x2000(8192) =

0.998291015625(fold)   0x2012(8210) / 0x2000(8192) =

1.002197265625(fold) Notes:Theinsideof()isadecimal systemequivalent.

0x2000 to 1) value of CXD1885Q is displayed. Therefore,0x1FF2andinthecaseof 0x2012,itisasfollows.   0x1FF2(8178) / 0x2000(8192) =

0.998291015625(fold)   0x2012(8210) / 0x2000(8192) =

1.002197265625(fold) Notes:Theinsideof()isadecimal systemequivalent

CXD1885Q. Thevaluedisplayedonasetservesas the number of complement of 2 of 2Bytes(es)doubled256. Avoltagevalueis6.25mVperbit.

operation.

Theyarethecontentsatthetimeof diskdistinction. Pleasereferto"Table3Disc distinction information" about the contentsofavalue.

disktype. Pleasereferto"Table4Disc classificationinformation" about the contentsofavalue.

atthetimeofCDoperation.

48 FcsAGC レイヤ 1 CXD1885Q 内部フォーカスゲイン

49 TrkAGC レイヤ1 CXD1885Q 内部トラッキングゲイン

50 PiOffset レイヤ1 CXD1885Q 内部で計算されるパラ

51 FEOffset レイヤ1 CXD1885Q 内部で計算されるパラ

52 SEOffset レイヤ1 CXD1885Q 内部で計算されるパラ

53 PO 誤り検出数エラー

54 PO 訂正不可数エラー

55 PI 誤り検出数エラー

56 PI 訂正不可数エラー

57 MirrCount ディスク判別ディスク判別時の内容。

58 MirrWidth ディスク判別ディスク判別時の内容。

59 FZCCount ディスク判別ディスク判別時の内容。

60 PiLevel ディスク判別ディスク判別時の内容。

61 DiscType ディスク種別ディスク種別の内容。

62 PO 誤り検出数

とアドレス

レート

エラーレート

(0x2000 を 1 として ) 値を表示。 0x1FF2 や 0x2012 の場合、以下のようになる。   0x1FF2(8178) / 0x2000(8192) =

0.998291015625( 倍 )   0x2012(8210) / 0x2000(8192) =

1.002197265625( 倍 ) 注 :() 内は 10 進換算値

(0x2000 を 1 として ) 値を表示。 0x1FF2 や 0x2012 の場合、以下のようになる。   0x1FF2(8178) / 0x2000(8192) =

0.998291015625( 倍 )   0x2012(8210) / 0x2000(8192) =

1.002197265625( 倍 ) 注 :() 内は 10 進換算値

メータ。セットに表示される値は、256 倍された 2Bytes の 2 の補数となる。電圧値は 1bit あたり 6.25mV。

CD 時は無効。

CD 時は C1 誤り検出数。

CD 時は C2 訂正不可数。

値の内容は「表３ディスク判別情報」を参照。

値の内容は「表３ディスク判別情報」参照。

値の内容は「表４ディスク種別情報」参照。

CD 時は PO 誤り検出数は無効。

21

DVD-3910

Table 2:tracemode details

ＹＹ Contents Contentssupplement

71 A display of PO error detection

number of the inner circumferenceof1-layerandanaddress.

72 A display of PO uncorrectable

number of the inner circumferenceof1-layerandanaddress.

73 A display of PI error detection

number of the inner circumferenceof1-layerandanaddress.

74 A display of PI uncorrectable

number of the inner circumferenceof1-layerandanaddress.

75 A display of PO error detection

numberofthecentralcircumferenceof1-layerandanaddress.

76 A display of PO uncorrectable

numberofthecentralcircumferenceof1-layerandanaddress.

77 A display of PI error detection

numberofthecentralcircumferenceof1-layerandanaddress.

78 A display of PI uncorrectable

numberofthecentralcircumferenceof1-layerandanaddress.

79 A display of PO error detection

number of the outer circumferenceof1-layerandanaddress.

80 A display of PO uncorrectable

number of the outer circumferenceof1-layerandanaddress.

81 A display of PI error detection

number of the outer circumferenceof1-layerandanaddress.

82 A display of PI uncorrectable

number of the outer circumferenceof1-layerandanaddress.

83 A display of PO error detection

number of the inner circumferenceof2-layerandanaddress.

84 A display of PO uncorrectable

number of the inner circumferenceof2-layerandanaddress.

85 A display of PI error detection

number of the inner circumferenceof2-layerandanaddress.

86 A display of PI uncorrectable

number of the inner circumferenceof2-layerandanaddress.

87 A display of PO error detection

numberofthecentralcircumferenceof2-layerandanaddress.

88 A display of PO uncorrectable

numberofthecentralcircumferenceof2-layerandanaddress.

89 A display of PI error detection

numberofthecentralcircumferenceof2-layerandanaddress.

90 A display of PI uncorrectable

numberofthecentralcircumferenceof2-layerandanaddress.

91 A display of PO error detection

number of the outer circumferenceof2-layerandanaddress.

92 A display of PO uncorrectable

number of the outer circumferenceof2-layerandanaddress.

93 A display of PI error detection

number of the outer circumferenceof2-layerandanaddress.

94 A display of PI uncorrectable

number of the outer circumferenceof2-layerandanaddress.

ItisinvalidatthetimeofCD operation.

CD:C1errordetectionnumber

CD : C2 uncorrectable error number

ItisinvalidatthetimeofCD operation.

CD:C1errordetectionnumber

CD : C2 uncorrectable error number

ItisinvalidatthetimeofCD operation.

CD:C1errordetectionnumber

CD : C2 uncorrectable error number

Inthecaseof1-layerdisc,itis invalid.

表 2トレースモード詳細

ＹＹ内容補足説明

71 1 層内周の PO 誤り検出数とアド

レスの表示

72 1 層内周の PO 訂正不可数とアド

レスの表示

73 1層内周のPI誤り検出数とアドレ

スの表示

74 1層内周のPI訂正不可数とアドレ

スの表示

75 1 層中周の PO 誤り検出数とアド

レスの表示

76 1 層中周の PO 訂正不可数とアド

レスの表示

77 1層中周のPI誤り検出数とアドレ

スの表示

78 1層中周のPI訂正不可数とアドレ

スの表示

79 1 層外周の PO 誤り検出数とアド

レスの表示

80 1 層外周の PO 訂正不可数とアド

レスの表示

81 1層外周のPI誤り検出数とアドレ

スの表示

82 1層外周のPI訂正不可数とアドレ

スの表示

83 2 層内周の PO 誤り検出数とアド

レスの表示

84 2 層内周の PO 訂正不可数とアド

レスの表示

85 2層内周のPI誤り検出数とアドレ

スの表示

86 2層内周のPI訂正不可数とアドレ

スの表示

87 2 層中周の PO 誤り検出数とアド

レスの表示

88 2 層中周の PO 訂正不可数とアド

レスの表示

89 2層中周のPI誤り検出数とアドレ

スの表示

90 2層中周のPI訂正不可数とアドレ

スの表示

91 2 層外周の PO 誤り検出数とアド

レスの表示

92 2 層外周の PO 訂正不可数とアド

レスの表示

93 2層外周のPI誤り検出数とアドレ

スの表示

94 2層外周のPI訂正不可数とアドレ

スの表示

CD 時は無効。

CD 時は C1 誤り検出数。

CD 時は C2 訂正不可数。

CD 時は無効。

CD 時は C1 誤り検出数。

CD 時は C2 訂正不可数。

CD 時は無効。

CD 時は C1 誤り検出数。

CD 時は C2 訂正不可数。

1 層ディスクの場合、無効。

22

DVD-3910

Table 3:Discdistinctioninformation

MirrCount MirrWidth FZCCountPILevel

NoDisc Except2

CDHigh reflection

CDLow reflection

DVDHigh reflection

DVDLow reflection

DVD2-layer 2 Lessthan

SACDHybrid 3 - - -

and3

2Morethan

2 Lessthan

---

0x8ED

-Morethan

-Lessthan

1Morethan

1Lessthan

2-

0x99

0x98

0x81

0x80

PIlevelFormula：PIlevel(V)=Measuredvalue × 1.6 ÷ 256 "-":Invalid

Table 4:Discclassificationinformation

DiscType Media

0x00 NoDisc

0x01 UnknownDisc 0x04 DVDSingleLowreflection 0x05 DVDDualParallelLowreflection 0x06 DVDDualOppositeLowreflection 0x08 CDDALowreflection 0x0A VCDLowreflection

0x44 DVDSingleHighreflection 0x48 CDDAHighreflection 0x4A VCDHighreflection 0x8F SACDHybridDisc

表３ディスク判別情報

MirrCount MirrWidth FZCCountPILevel

NoDisc 2 と 3 以外 - - CD 高反射 2 0x8ED 以上 - 0x99 以上 CD 低反射 2 0x8ED 以上 - 0x98 以下 DVD 高反射 2 0x8ED 以下 1 0x81 以上 DVD 低反射 2 0x8ED 以下 1 0x80 以下 DVD2 層 2 0x8ED 以下 2 SACDHybrid 3 - - -

PIlevel計算式：PIlevel(V)=測定値× 1.6 ÷ 256 "-" は無効

表４ディスク種別情報

DiscType Media

0x00 NoDisc

0x01 UnknownDisc 0x04 DVDSingle低反射 0x05 DVDDualParallel低反射 0x06 DVDDualOpposite低反射 0x08 CDDA低反射

0x0A VCD低反射

0x44 DVDSingle高反射 0x48 CDDA高反射

0x4A VCD高反射

0x8F SACDHybridDisc

23

DVD-3910

トラブ

グ

管点灯せず

立ち上がりチェック工程

電源電圧確認

半田付けを確認

発振波形確認

半田付けを確認

電源電圧確認

半田付けを確認

信号の確認

半田付けを確認

データバスの確認

半田付けを確認

不良

次のステップ

立ち上げチェック工程

TROUBLE SHOOTING

ルシューティン

1. GU-3618 (MAIN UNIT) ,GU-3613-1 (SYSTEM UNIT) 1. GU-3618 (MAIN UNIT) ,GU-3613-1 (SYSTEM UNIT)

1.1. FL TUBE dosen't light 1.1. FL

(1) Check the Set-up process of System 㱘-COM (1)システムµ-COM

Check Power Supply Voltages. GU-3613-1(SYSTEM UNIT) GU-3613-1(SYSTEM PWB)

・ [IC202]:D1,D4 N.G Check Soldering. ・ [IC202]:D1,D4 N.G

+3.3V_D1,+3.3V_D4 ・ CY131 on SYSTEM UNIT. +3.3V_D1,+3.3V_D4 ・ SYSTEM UNITのCY131

O.K. O.K.

Check Oscillation waveform. GU-3613-1(SYSTEM UNIT) GU-3613-1(SYSTEM UNIT)

・ [IC202]: N.G Check Soldering. ・ [IC202]: N.G

16MHz at 13pin. ・ X201 on SYSTEM UNIT. 16MHz at 13pin. ・ SYSTEM UNITのX201

O.K. O.K.

Check Power Supply Voltages. GU-3613-1(SYSTEM UNIT) GU-3613-1(SYSTEM UNIT)

・ [IC202]: N.G Check Soldering. ・ [IC202]: N.G

"H"level at 39pin?"L"level at 7pin and ・ IC202 on SYSTEM UNIT. "H"level at 39pin?"L"level at 7pin and ・ SYSTEM UNITのIC202 44pin? 44pin?

O.K. O.K.

Check Reset Signal RESET GU-3613-1(SYSTEM UNIT) GU-3613-1(SYSTEM UNIT)

・ [IC202]: N.G Check Soldering. ・ [IC202]: N.G

"H"level at 10pin? ・ IC201(Reset IC) on SYSTEM UNIT. "H"level at 10pin? ・ SYSTEM UNITのIC201(Reset IC)

O.K. O.K.

Check Data Bus between GU-3614-1(DISPLAY UNIT) GU-3614-1(DISPLAY UNIT)

FLD Driver(GU-3614-4(IC101)] N.G (1) Check soldering of CY211 on SYSTEM UNIT. FLD Driver(GU-3614-4(IC101)] N.G (1) SYSTEM UNITのCY211の

・ [VFD_RST]:"H"level? (2) GU-3614-4 is N.G.(No Good). ・ [VFD_RST]:"H"level? (2) GU-3614-4 の

O.K. O.K.

Continue to next step. Check the Set-up process of B/E 㱘-COM. (2)B/E µ-COM

へ

24

(2) Check the Set-up process of B/E 㱘-COM (2) Check the Set-up process of B/E 㱘-COM

電源電圧確認

出力レベル確認

半田付けを確認

クロックの波形確認

を確認

半田付けを確認

信号の確認

半田付けを確認

２

と

半田付けを確認

アドレス、データバスの確認

次のステップ

立ち上げチェック工程

Check Power Supply Voltages. GU-3618(MAIN UNIT) N.G Check the output level. N.G Check Soldering. GU-3618(MAIN UNIT) N.G

・ [IC108]:D1,D4 [ON/ST]:"H"level? ・ [IC202]:88pin. ・ [IC108]:D1,D4 [ON/ST]:"H"level ・ [IC202]:88pin.

+3.3V_ESS,+2.0V_ESS O.K.? +3.3V_ESS,+2.0V_ESS

O.K. O.K.

DVD-3910

N.G

Check Clock waveform. Check 27MHz(3.3V)at (1) Check Soldering. of X101. GU-3618(MAIN UNIT) N.G 10pin of IC106. N.G (2) Check Soldering. of IC105 GU-3618(MAIN UNIT) ・ [IC106]:10pin (2)

・ [IC108]:49,108,116pin and (SM8701). ・ [IC108]:49,108,116pin and ・ [IC105](SM8701).

117pin. 117pin. 27MHz(3.3V),O.K.? O.K. Check Soldering. Of 27MHz(3.3V) O.K.

R114,R115 and R154. ・ R114,R115 and R154.

O.K. O.K.

Check Reset signal. Check Soldering. RESET GU-3618(MAIN UNIT) GU-3613-1(SYSTEM UNIT) GU-3618(MAIN UNIT) GU-3613-1(SYSTEM UNIT)

・ [IC108]:(RESET)24 pin. N.G ・ [IC202]:8pin. ・ [IC108]:(RESET)24 pin. N.G ・ [IC202]:8pin.

"H"level O.K.? GU-3618(MAIN UNIT) "H"level GU-3618(MAIN UNIT)

O.K. O.K.

Check I GU-3618(MAIN UNIT) GU-3618(MAIN UNIT) GU-3618(MAIN UNIT) GU-3618(MAIN UNIT)

Check Address,Data Bus between Check Soldering at Address,Data Bus,Control Signal. [1C108] GU-3618(MAIN PWB) GU-3618(MAIN UNIT) GU-3618(MAIN UNIT) GU-3618(MAIN UNIT)

[1C108]and[IC104](Flash Rom). N.G ・ [LD0-LD7],[LCS3,LOE]

C Signal. Check Soldering. I２C信号の確認半田付けを確認

・ [IC108]: N.G ・ [IC108] and [IC116] ・ [IC108]: N.G ・ [IC108] and [IC116]

"H"level at 160pin and 161pin. ・ R185,R186,R757,FB173 and FB174. "H"level at 160pin and 161pin. ・ R185,R186,R757,FB173 and FB174.

O.K. O.K.

・ [IC117]:5pin and 6pin. ・ [IC117]:5pin and 6pin. ・ FB127 and R138. ・ FB127 and R138.

[IC104](Flash Rom)間の

N.G

N.G ・ [LD0-LD7],[LCS3,LOE]

N.G (1) [X101]

O.K. O.K.

Continue to next step. Check the Set-up process of F/E 㱘-COM. (3)F/E µ-COM

へ

25

(3) Check the Set-up process of F/E 㱘-COM (3) F/E µ-COM

立ち上げチェック工程

電源電圧確認

半田付けを確認

クロックの波形確認

半田付けを確認

信号の確認

半田付けを確認

終了

映像出力せず。（ブルーバック

壁紙）

映像用デジタル信号出力確認

半田付けを確認

映像用デジタル信号出力確認

半田付けを確認

チェック工程

Check Power Supply Voltages. GU-3618(MAIN UNIT) Check Soldering. GU-3618(MAIN UNIT)

・ [IC507]: N.G ・ [IC951] ・ [IC507]: N.G ・ [IC951]

+3.3V_D2,+1.8V_D2 O.K.? ・ FB953,FB960 and FB967 +3.3V_D2,+1.8V_D2 O.K.? ・ FB953,FB960 and FB967 +3.3V_A2,+1.8V_A2 O.K.? +3.3V_A2,+1.8V_A2 O.K.?

O.K. O.K.

Check Clock waveform. Check Soldering. GU-3618(MAIN UNIT) N.G ・ [IC106]:12pin GU-3618(MAIN UNIT) N.G ・ [IC106]:12pin

・ [IC507]:33pin. ・ R147 ・ [IC507]:33pin. ・ R147

33.87MHz(3.3V),O.K.? ・ [IC404],R440 and R623 33.87MHz(3.3V),O.K.? ・ [IC404],R440 and R623

O.K. O.K.

Check Reset Signal. Check Soldering. RESET GU-3618(MAIN UNIT) N.G ・ [IC108]:145pin GU-3618(MAIN UNIT) N.G ・ [IC108]:145pin

・ [IC507]:(DRVRST)51pin ・ R618 and R628 ・ [IC507]:(DRVRST)51pin ・ R618 and R628

"H"level O.K.? "H"level O.K.?

O.K. O.K.

END

DVD-3910

1.2. Image is not displayed.(Blue-back,DENON wallpaper) 1.2.

Check Digital output signal for Video.[1] GU-3618(MAIN UNIT) Check Soldering. GU-3618(MAIN UNIT)

・ [IC108]:PCLKG N.G ・ [IC108]:117pin,[IC105],R115 and R120 ・ [IC108]:PCLKG N.G ・ [IC108]:117pin,[IC105],R115 and R120 ・ [IC108]:HSYNC,VSYNC ・ [IC108]:118,119pin ・ [IC108]:HSYNC,VSYNC ・ [IC108]:118,119pin ・ [IC108]:YUV(0-7), ・ [IC108]:106-110,113-115pin,RA108,RA109 ・ [IC108]:YUV(0-7), ・ [IC108]:106-110,113-115pin,RA108,RA109

O.K. O.K.

Check Digital output signal for Video.[2] GU-3618(MAIN UNIT) N.G Check Soldering. GU-3618(MAIN UNIT) N.G

・ [CX331]:CLKO(13pin) ・ [CX331]:13pin,R703,FB111 ・ [CX331]:CLKO(13pin) ・ [CX331]:13pin,R703,FB111 ・ [CX331]:HSYNC,VSYNC(23,24pin) ・ [CX331]:23,24pin,FB116,FB117 ・ [CX331]:HSYNC,VSYNC(23,24pin) ・ [CX331]:23,24pin,FB116,FB117 ・ [CX331]:PC2-PC9(4-11pin) ・ [CX331]:4-11pin,FB103-110.RA703,RA704 ・ [CX331]:PC2-PC9(4-11pin) ・ [CX331]:4-11pin,FB103-110.RA703,RA704

O.K. O.K.

Continue to the check process GU-3613-2 VIDEO UNIT of GU-3613-2 VIDEO UNIT.

、 DENON

[1]

[2]

へ

26

1.3. Does not Read Disc 1.3.

ディスク読めず

ク回転せず

発光を確認

半田ショートランドを確認

レーザー発光

半田付けを確認

電流チェック

ネクタ接続を確認

とその周辺回路の半田付けを確認

ピンドルドライブ信号の確認

半田付けを確認

信号ライン周辺

半田付けを確認

周辺回路の半田付けを確認

終

程

ＲＦ信号の確認

周辺回路の半田付けを確認

トポイント

電圧確認

周辺回路の半田付けを確認

バスライン確認

半田付けを確認

アドレス､データ、制御信号

切替

とその周辺回路の半田付けを確認

終了

程

ＶＳＴＥＭ通信確認

半田付けを確認

切替

リクエスト信号の確認

周辺回路の半田付けを確認

ト信号

終了

[No Play],[00 00] displayed etc. [No Play],[00 00] 等の表示

(1) Disc does not Rotate. (1)ディス

DVD-3910

Check the Emission of Pick-up. (1) Check Soldering of P.U. Pick-up の GU-3618(MAIN UNIT) N.G ・ short-circuit? GU-3618(MAIN UNIT) N.G

・ Emission of P.U. laser O.K.? (2) Check the circumference soldering of TR501 ・ P.U. ・ See attached sheet laser current check. and TR502. ・レーザー

(3) Check connector insertion. (3) コ

・ [P.U.] - [GU-3618] FFC(CX241) ・ [P.U.] - [GU-3618] FFC(CX241)

(4) Check the soldering [IC502](CXD1881AR) (4) [IC502]

and circumference soldering of [IC502].

O.K. (5) Check the soldering [IC503](FAN8042) O.K. (5) [IC503]

and circumference soldering of [IC503].

Check Spindle drive signal. (1) Check soldering of [IC507]:111-113pin. ス GU-3618(MAIN UNIT) N.G (2) Check the circumference soldering of GU-3618(MAIN UNIT) N.G (2) [SPWM1],[SPWM2],[FG]

・ [DMO]:"H"level? [SPWM1],[SPWM2] and [FG] signal. ・ [DMO]:"H"level?

(3) Check the soldering [IC501](AN8471SA) (3) [IC501]とその

and circumference soldering of [IC501].

O.K. O.K.

END

(2) CD check process (2) ＣＤチェック工

Check the RF signal. GU-3618(MAIN UNIT) N.G (1) Check the circumference soldering of [IC502] GU-3618(MAIN UNIT) N.G (1) [IC502]とその

・ Check the voltage of Test-Point(TP) (2) Check the circumference soldering of [IC507] ・テス

TP[RFAC]:about 1.0Vp-p TP[RFAC]:約 1.0Vp-p

(1) P.U.の

O.K.? (2) TR501,TR502周辺の

(1) [IC507]:111-113pinの

了

(TP)の

(2) [IC507]とその

の

O.K. O.K.

Check Bus Line. Check Soldering. GU-3618(MAIN UNIT) N.G ・ Address,Data Bus,Control Signal. GU-3618(MAIN UNIT) N.G ・

・ [IC507] ⇔ [IC505](16MDRAM) [BD0-15],[BA0-9],[XLCAS],[XUCAS],[XMOE], ・ [IC507] ⇔ [IC505](16MDRAM) [BD0-15],[BA0-9],[XLCAS],[XUCAS],[XMOE],

"L" ⇔"H" alternate? [XRAS] "L" ⇔"H"

・ Check the circumference soldering of [IC505] ・ [IC505]

O.K. O.K.

END

(3) DVD check process (3) ＤＶＤチェック工

Check VSTEM communication. GU-3618(MAIN UNIT) N.G Check Soldering. GU-3618(MAIN UNIT) N.G

・ [VDT0-7_COR],[XHAC_COR],[XSHD_COR], ・ [IC507]:36-49pin ・ [VDT0-7_COR],[XHAC_COR],[XSHD_COR], ・ [IC507]:36-49pin

[DCK_COR],VEFG_COR] ・ R638-R650 [DCK_COR],VEFG_COR] ・ R638-R650 "L" ⇔"H" alternate? "L" ⇔"H"

O.K. O.K.

Check Request signal. GU-3618(MAIN UNIT) N.G ・ Check the circumference soldering of [IC401] GU-3618(MAIN UNIT) N.G ・ [IC401]とその

・ Request from [B/E] and [F/E] ・ [B/E]と[F/E]のリクエス

[HDRQ_COR]:"L"level? [HDRQ_COR]:"L"level?

.

[XRAS]

O.K. O.K.

END

27

(4) SACD check process (4) SACD チェック工

程

電源電圧確認

半田付けを確認

クロックの波形確認

半田付けを確認

信号の確認

半田付けを確認

バスラインの確認

半田付けを確認

通信の確認

半田付けを確認

ウォータ

ク用ＲＦ信号の確認

周辺と

半田付け

を確認

終了

Check Power Supply Voltages. Check Soldering. GU-3618(MAIN UNIT) N.G ・ [IC950] GU-3618(MAIN UNIT) N.G ・ [IC950]

・ [IC401],[IC403],[IC405]: ・ FB952,FB956 ・ [IC401],[IC403],[IC405]: ・ FB952,FB956

+5V_A2,+3.3V_D2,+2.5V_D2 O.K.? +5V_A2,+3.3V_D2,+2.5V_D2 O.K.?

O.K. O.K.

Check Clock waveform. GU-3618(MAIN UNIT) N.G Check Soldering. GU-3618(MAIN UNIT) N.G

・ [IC401](EPM3128ATC):87pin. ・ [IC401]:87pin,R498,[IC404],R440 ・ [IC401](EPM3128ATC):87pin. ・ [IC401]:87pin,R498,[IC404],R440 ・ [IC405](CXD2753R):11pin. ・ [IC405]:11pin,R439,[IC404] ・ [IC405](CXD2753R):11pin. ・ [IC405]:11pin,R439,[IC404]

33.87MHz(3.3V),O.K.? 33.87MHz(3.3V),O.K.?

O.K. O.K.

Check Reset signal. RESET GU-3618(MAIN UNIT) N.G Check Soldering. GU-3618(MAIN UNIT) N.G

・ [IC401]:(XRST_PLD)89 pin. ・ [IC508],R413 ・ [IC401]:(XRST_PLD)89 pin. ・ [IC508],R413 ・ [IC405]:(RST)9 pin. ・ R463 ・ [IC405]:(RST)9 pin. ・ R463

"H"level O.K.? "H"level O.K.?

O.K. O.K.

DVD-3910

Check Bus Line. Check Soldering. GU-3618(MAIN UNIT) N.G ・ Address,Data Bus,Control Signal. GU-3618(MAIN UNIT) N.G ・ Address,Data Bus,Control Signal.

・ [IC405] ⇔ [IC402](16MSDRAM) [DQ0-7],[D_MA0-11],[DCLK],[DCKE],[DWE], ・ [IC405] ⇔ [IC402](16MSDRAM) [DQ0-7],[D_MA0-11],[DCLK],[DCKE],[DWE],

"L" ⇔"H" alternate? [DCAS],[DRAS] "L" ⇔"H" alternate? [DCAS],[DRAS]

・ RA401-RA405,R445-R449 ・ RA401-RA405,R445-R449

O.K. O.K.

Check VSTEM communication. Check Soldering. VSTEM GU-3618(MAIN UNIT) N.G ・ [IC401]:35-37,44-48,54,63,67-69pin GU-3618(MAIN UNIT) N.G ・ [IC401]:35-37,44-48,54,63,67-69pin

・ [SD0-7],[XSAC],[XSHD2],[SDCK],[SDEF], ・ [IC405]:164-176pin ・ [SD0-7],[XSAC],[XSHD2],[SDCK],[SDEF], ・ [IC405]:164-176pin

[XSRQ] [XSRQ] "L" ⇔"H" alternate? "L" ⇔"H" alternate?

O.K. O.K.

Check RF signal for Water Mark. GU-3618(MAIN UNIT) N.G Check the circumference soldering of [IC403] GU-3618(MAIN UNIT) N.G [IC403](AD8062)

・ TP[WM]:about 1.0Vp-p (AD8062) and [IC405]:126pin ・ TP[WM]:約t 1.0Vp-p

O.K. O.K.

END

ーマー

[IC405]:126pinの

28

1.4. No Sound,Noise generated 1.4. 音声出力せず、ノイズ発生

デジタルオーディオデータ

通信確認

半田付けを確認

出力

切替

デジタルオーディオデータ確認

半田付けを確認

出力

デジタルオーディオデータ確認

半田付けを確認

出力

デジタルオーディオデータ確認

と

周辺回路の半田付け

オセレクタ入出力

を確認

程

(1) CD,DVD-VIDEO/AUDIO (1) CD,DVD-VIDEO/AUDIO

DVD-3910

Check PCM Digital Audio Data(VSTEM data) Check Soldering. PCM and VSTEM communication. N.G ・ [IC401]:75-98pin N.G ・ [IC401]:75-98pin GU-3618(MAIN UNIT) ・ R401-R412,R494 GU-3618(MAIN UNIT) ・ R401-R412,R494

・ [IC401]output and [IC108](ES6138)input: ・ [IC108]:122-128,131,132,142,144,149,150pin ・ [IC401]

[BD0-7],[BSDCLK],[SHAK],[BSDEF],[BSHD], [BD0-7],[BSDCLK],[SHAK],[BSDEF],[BSHD], [BSREQ] [BSREQ] "L" ⇔"H" alternate? "L" ⇔"H"

O.K. O.K.

Check PCM Digital Audio Data output.[1] Check Soldering. PCM GU-3618(MAIN UNIT) N.G ・ [IC108]:33,36,37,40,32pin GU-3618(MAIN UNIT) N.G ・ [IC108]:33,36,37,40,32pin

・ [IC108]output and [IC801](SM5819A)input: ・ R129-R132,R134 ・ [IC108]

[TSD0-2],[TBCK],[TWS],[PMCK] ・ [IC801]:29,31-35pin [TSD0-2],[TBCK],[TWS],[PMCK] ・ [IC801]:29,31-35pin

・ [IC110].R150,R157,R173 ・ [IC110].R150,R157,R173

O.K. O.K.

Check PCM Digital Audio Data output.[2] Check Soldering. PCM GU-3618(MAIN UNIT) N.G ・ [IC801]:17,19-23pin GU-3618(MAIN UNIT) N.G ・ [IC801]:17,19-23pin

・ [IC801]output: ・ R806-R811 ・ [IC801]

[TSD0-2.],[TBCK.],[TWS.],[PMCK.] ・ [IC801]:4pin,[IC115]:12pin [TSD0-2.],[TBCK.],[TWS.],[PMCK.] ・ [IC801]:4pin,[IC115]:12pin

・ [IC801]:4pin(SELEXT)"H"? ・ [IC801]:4pin(SELEXT)"H"?

O.K. O.K.

Check PCM Digital Audio Data output.[3] PCM GU-3618(MAIN UNIT) N.G ・ Check the circumference soldering of [IC124] GU-3618(MAIN UNIT) N.G ・ [IC124]

・ Audio selector input/output: and [IC125] ・オーディ

[PDATA0-2],[PBCK],[PLRCK],[PMCK] [PDATA0-2],[PBCK],[PLRCK],[PMCK]

・ [IC124,IC125]:1pin(DSD_SEL)"L"? ・ [IC124,IC125]:1pin(DSD_SEL)"L"?

/ [IC108](ES6138)入力: ・ [IC108]:122-128,131,132,142,144,149,150pin

?

/ [IC801](SM5819A)入力: ・ R129-R132,R134

: ・ R806-R811

/VSTEM

[1]

[2]

[3]

[IC125]とその

O.K. O.K.

Continue to the check process GU-3613-1/GU-3614-1 AUDIO UNIT of GU-3613-1/GU-3614-1 AUDIO UNIT. のチェック工

へ.

29

(2) SACD : SOURCE DIRECT ON MODE (2) SACD : SOURCE DIRECT ON MODE

時

デジタルオーディオデータ

通信確認

半田付けを確認

出力

データ確認

半田付けを確認

出力

データ確認

と

周辺回路の半田付け

オセレクタ入出力

を確認

データ確認

と

周辺回路の半田付け

オセレクタ入出力

を確認

程

デジタルオーディオデータ

通信確認

半田付けを確認

出力

データ確認

半田付けを確認

データ確認

半田付けを確認

データ確認

と

周辺回路の半田付け

オセレクタ入出力

を確認

程

DVD-3910

Check SACD Digital Audio Data(VSTEM data) Check Soldering. SACD and VSTEM communication. N.G ・ [IC401]:35-37,44-48,54,63,67-69pin N.G ・ [IC401]:35-37,44-48,54,63,67-69pin GU-3618(MAIN UNIT) ・ [IC405]:164-176pin GU-3618(MAIN UNIT) ・ [IC405]:164-176pin

・ [IC401]output and [IC405]input: ・ R414-426 ・ [IC401]

[SD0-7],[SDCK],[XSAK],[SDEF],[XSHD2], [SD0-7],[SDCK],[XSAK],[SDEF],[XSHD2], [XSRQ] [XSRQ]

O.K. O.K.

Check DSD Data.[1] Check Soldering. DSD GU-3618(MAIN UNIT) N.G ・ [IC405]:76,74,71,69,66,64,60,56,55pin GU-3618(MAIN UNIT) N.G ・ [IC405]:76,74,71,69,66,64,60,56,55pin

・ [IC405]output:[DSARS],[DSALS],[DSASW], ・ R464-R473 ・ [IC405]

[DSAC],[DSAR],[DSAL],[BCKAO],[DSAMR], [DSAC],[DSAR],[DSAL],[BCKAO],[DSAMR], [DSADML],[EXCK01] [DSADML],[EXCK01]

O.K. O.K.

Check DSD Data.[2] DSD GU-3618(MAIN UNIT) N.G ・ Check the circumference soldering of [IC119] GU-3618(MAIN UNIT) N.G ・ [IC119]

・ Audio selector input/output: and [IC120] ・オーディ

[DSDFL],[DSDFR],[DSDSW],[DSDC], [DSDFL],[DSDFR],[DSDSW],[DSDC], [DSDSL],[DSDSR],[DSDBCK] [DSDSL],[DSDSR],[DSDBCK]

・ [IC119,IC120]:1pin(SEL_1394)"L"? ・ [IC119,IC120]:1pin(SEL_1394)"L"?

O.K. O.K.

Check DSD Data.[3] DSD GU-3618(MAIN UNIT) N.G ・ Check the circumference soldering of [IC124] GU-3618(MAIN UNIT) N.G ・ [IC124]

・ Audio selector input/output: and [IC125] ・オーディ

[DSDFL],[DSDFR],[DSDSW],[DSDC], [DSDFL],[DSDFR],[DSDSW],[DSDC], [DSDSL],[DSDSR],[DSDBCK] [DSDSL],[DSDSR],[DSDBCK]

・ [IC124,IC125]:1pin(DSD_SEL)"H"? ・ [IC124,IC125]:1pin(DSD_SEL)"H"?

/ [IC405]入力: ・ R414-426

[1]

:[DSARS],[DSALS],[DSASW], ・ R464-R473

[2]

[3]

/VSTEM

[IC120]とその

[IC125]とその

O.K. O.K.

Continue to the check process GU-3613-1/GU-3614-1 AUDIO UNIT of GU-3613-1/GU-3614-1 AUDIO UNIT. のチェック工

(3) SACD : SOURCE DIRECT OFF MODE (3) SACD : SOURCE DIRECT OFF MODE

Check SACD Digital Audio Data(VSTEM data) Check Soldering. SACD and VSTEM communication. N.G ・ [IC401]:35-37,44-48,54,63,67-69pin N.G ・ [IC401]:35-37,44-48,54,63,67-69pin GU-3618(MAIN UNIT) ・ [IC405]:164-176pin GU-3618(MAIN UNIT) ・ [IC405]:164-176pin

・ [IC401]output and [IC405]input: ・ R414-426 ・ [IC401]

[SD0-7],[SDCK],[XSAK],[SDEF],[XSHD2], [SD0-7],[SDCK],[XSAK],[SDEF],[XSHD2], [XSRQ] [XSRQ]

O.K. O.K.

Check DSD Data.[1] Check Soldering. DSD GU-3618(MAIN UNIT) N.G ・ [IC405]:76,74,71,69,66,64,60,56,55,13pin GU-3618(MAIN UNIT) N.G ・ [IC405]:76,74,71,69,66,64,60,56,55,13pin

・ [IC405]output/[IC801]input: ・ R486-R493 ・ [IC405]output/[IC801]input: ・ R486-R493

[DSARS.],[DSALS.],[DSASW.],[DSAC.], ・ [IC801]:27,38-44pin [DSARS.],[DSALS.],[DSASW.],[DSAC.], ・ [IC801]:27,38-44pin [DSAR.],[DSAL.],[BCKAO.],[EXCK01.] [DSAR.],[DSAL.],[BCKAO.],[EXCK01.]

O.K. O.K.

Check DSD Data.[2] Check Soldering. DSD GU-3618(MAIN UNIT) N.G ・ [IC801]:17,19-23pin GU-3618(MAIN UNIT) N.G ・ [IC801]:17,19-23pin

・ [IC801]output: ・ R806-R811 ・ [IC801]output: ・ R806-R811

[TSD0-2.],[TWS.],[TBCK.],[PMCK.] ・ [IC801]:4pin,[IC115]:12pin [TSD0-2.],[TWS.],[TBCK.],[PMCK.] ・ [IC801]:4pin,[IC115]:12pin

・ [IC801]:4pin(SELEXT)"L"? ・ [IC801]:4pin(SELEXT)"L"?

O.K. O.K.

Check DSD Data.[3] DSD GU-3618(MAIN UNIT) N.G ・ Check the circumference soldering of [IC124] GU-3618(MAIN UNIT) N.G ・ [IC124]

・ Audio selector input/output: and [IC125] ・オーディ

[PDATA0-2],[PBCK],[PLRCK],[PMCK] [PDATA0-2],[PBCK],[PLRCK],[PMCK]

・ [IC124,IC125]:1pin(DSD_SEL)"L"? ・ [IC124,IC125]:1pin(DSD_SEL)"L"?

へ.

/ [IC405]入力: ・ R414-426

[1]

[2]

[3]

/VSTEM

[IC125]とその

O.K. O.K.

Continue to the check process GU-3613-1/GU-3614-1 AUDIO UNIT of GU-3613-1/GU-3614-1 AUDIO UNIT. のチェック工

へ.

30

DVD-3910

(1)

)

(1)

)

ブ

(

)

(

)

75（256f

79(512fs),90(BCK),92

75（256f

79(512fs),90(BCK),92

（

LRCK

）

93(TSD0

：

FL/FR),94(TSD1

：

SL/SR)

（

LRCK

）

93(TSD0

：

FL/FR),94(TSD1

：

SL/SR)

(

)

(

)

21（BCK

）

22(LRCK),10(FL/FR),12(C/SW)

21（BCK

）

22(LRCK),10(FL/FR),12(C/SW)

13(SL/SR),14(MIXL/MIXR

：

ithout SACD)

13(SL/SR),14(MIXL/MIXR

：

ithout SACD)

(

)

CheckFi

DSP

N.G

(

マイコンファームチェックモードで

DSP

のバージョンを確認

N.G

(

デ

(

)

が

デ

(

)

(

)

GU-3613-1(SYSTEM UNIT)/GU-3614

（

AUDIO UNIT)

N.G

GU-3613-1(SYSTEM UNIT)/GU-3614

（

AUDIO UNIT)

N.G

GU-3613-1(SYSTEM UNIT)/GU-3614

（

AUDIO UNIT)

N.G.CheckP

GU-3613-1(SYSTEM UNIT)/GU-3614

（

AUDIO UNIT)

N.G

GU-3613-1(SYSTEM UNIT)/GU-3614

（

AUDIO UNIT)

N.G

GU-3613-1(SYSTEM UNIT)/GU-3614

（

AUDIO UNIT)

N.G

g

2. GU-3613-1 (SYSTEM UNIT)/GU-3614 (AUDIO UNIT) 2. GU-3613-1 (SYSTEM UNIT)/GU-3614 (AUDIO UNIT)

CD,DVD-VIDEO/AUDIO,(SACD-SOURCE DIRECT OFF

Check connection Mecha UNIT Check Soldering.、FFC cable メカユニットとの接続確認半田付け、FFCケーブルを確認

GU-3613-1(SYSTEM UNIT) ・ [CY302]:GU-3618 GU-3613-1(SYSTEM UNIT) ・ [CY302]:GU-3618 ・ [CX301]output signal ・ FFC cable、insert condition ・ [CX301]出力信号の確認・ FFCケー

O.K. O.K.

Check input signal : IC203 IC203の入力信号の確認 GU-3613-1(SYSTEM UNIT) N.G. Check Soldering. GU-3613-1(SYSTEM UNIT) N.G. 半田付けを確認

・

[IC203]

EPM3128ATC

s）,

,

96（TSD2：C/SW）, 96（TSD2：C/SW）, 97(TSD3：MIXL/MIXR：without SACD)pin check 97(TSD3：MIXL/MIXR：without SACD)pin check

O.K. O.K.

Check output signal : IC203 Check Soldering. IC203の出力信号の確認半田付けを確認 GU-3613-1(SYSTEM UNIT) N.G. ・

・

EPM3128ATC

[IC203]

,

Check DSP operation Check Soldering. DSP動作の確認半田付けを確認

rm version on

・ ”００００”indicate is N.G. "H" Level OK? "H"⇔"L"：N.G. ・ ”００００”表示はN.G. "H" Level OK? "H"⇔"L"：N.G.

（refer page 17.）・

Check DATA Signal -1 GU-3613-1(SYSTEM UNIT) N.G. Check Soldering. GU-3613-1(SYSTEM UNIT) N.G. 半田付けを確認

・

[IC203](EPM3128ATC)：output Ｒ226,234,231,230,236,229

・

[IC209](DSP)：input

w

O.K. O.K.

,

, ・

N.G. ・ [CX301] N.G. ・ [CX301]

・

FB211〜217、IC205

84pin：1394-Ｈ

・

85pin：Fs=192/176.4-H other Fs-Ｌ 87pin：Ｌ

・

8８pin：D.L.-Ｈ

GU-3613-1

. ・

SYSTEM UNIT

[IC209]:

DSP RESET)121pin

[IC209] to [IC210] Signal

・

[IC202] to [IC209] Signal

・ [IC210]:(FLASH ROM for DSP) ・ [IC210]:(FLASH ROM for DSP)の確認

CD,DVD-VIDEO/AUDIO,(SACD-SOURCE DIRECT OFF

・

[IC203]

EPM3128ATC

s）,

,

GU-3613-1(SYSTEM UNIT) N.G. ・

・

[IC203]

EPM3128ATC

,

（page 17 参照）・

ータ確認 -1

・

[IC203](EPM3128ATC)：output Ｒ226,234,231,230,236,229の確認

・

[IC209](DSP)：input

w

,

, ・

・

GU-3613-1(SYSTEM UNIT

. ・

・

ル、挿入状態の確認

FB211〜217、IC205確認

84pin：1394-Ｈ 85pin：Fs=192/176.4-H other Fs-Ｌ 87pin：Ｌ 8８pin：D.L.-Ｈ

[IC209]:

DSP RESET)121pin

[IC209],[IC210]の接続確認 [IC202],[IC209]の接続確認

O.K. O.K.

Check DATA Signal -2 GU-3613-1

SYSTEM UNIT

・

[IC209](DSP)：output 86(FL/FR),82(C/SW）,81(SL/SR), 86(FL/FR),82(C/SW）,81(SL/SR),80(MIXL/MIXR）pinの確認 80(MIXL/MIXR）pin Each output pin Level "H": NG

O.K. O.K.

Check DATA Signal -3 GU-3613-1(SYSTEM UNIT) N.G. Check Soldering. GU-3613-1(SYSTEM UNIT) N.G. 半田付けを確認

・

[IC209](DSP)：output Ｒ378,384,385,386

・

[IC203](EPM3128ATC)：input

O.K. O.K.

Check DATA Signal -4 GU-3613-1(SYSTEM UNIT) N.G. Check Soldering. GU-3613-1(SYSTEM UNIT) N.G. 半田付けを確認

・

[IC203](EPM3128ATC)：output to DAC 44〜55pin

・

[IC221](DAC for S/SW),[IC222](DAC for SL/SR) : input

・

4〜7pin(LRCK=1fs,DATA,BCK=64fs,MCK=256fs）

GU-3614

AUDIO UNIT

・

[IC311](DAC for MIXL/MIXR),[IC312](DAC for FL/FR) : input

・

4〜7pin(LRCK=1fs,DATA,BCK=64fs,MCK=256fs）

O.K. O.K.

Check DAC output Check Soldering. / Check Supply Voltages. DAC出力確認半田付けを確認

・

[IC223][IC224][IC301][IC307]:output

O.K. O.K.

Check OP AMP output Check Soldering. OP AMP出力確認半田付けを確認

・

[IC227]〜[IC230]:output:7pin

・

[IC303][IC304][IC304][IC304]:output:7pin

N.G. GU-3613-1(SYSTEM UNIT

・

CX332,CY332

・ CX173,CX191（Connection to 1394 PWB）

. ・

[IC203][IC221][IC311][IC312]

・

[IC223][IC224][IC301][IC307]

・

[IC203][IC221][IC311][IC312]：10〜14pin（control line）

・

[IC227]〜[IC230]

・

[IC303][IC304][IC304][IC304]

Connection to AUDIO UNIT

owerSupplyVoltages.

ータ確認 -2

・

[IC209](DSP)：output

各出力信号

ータ確認 -3

・

[IC209](DSP)：output Ｒ378,384,385,386の確認

・

[IC203](EPM3128ATC)：input

ータ確認 -4

・

[IC203](EPM3128ATC)：output to DAC 44〜55pin

・

[IC221](DAC for S/SW),[IC222](DAC for SL/SR) : input

・

4〜7pin(LRCK=1fs,DATA,BCK=64fs,MCK=256fs）

GU-3614(AUDIO UNIT

・

[IC311](DAC for MIXL/MIXR),[IC312](DAC for FL/FR) : input

・

4〜7pin(LRCK=1fs,DATA,BCK=64fs,MCK=256fs）

・

[IC223][IC224][IC301][IC307]:output

・

[IC227]〜[IC230]:output:7pin

・

[IC303][IC304][IC304][IC304]:output:7pin

"H"になっていないか

N.G.

. ・

・

CX332,CY332の確認(AUDIO UNITとの接続)

・ CX173,CX191の確認（1394 PWBとの接続）

[IC203][IC221][IC311][IC312]電源確認

・

[IC223][IC224][IC301][IC307]電源確認

・

[IC203][IC221][IC311][IC312]：10〜14pin確認（制御信号）

[IC227]〜[IC230]電源、周辺回路確認

・

[IC303][IC304][IC304][IC304]電源、周辺回路確認

O.K. O.K.

Check AUDIO OUT Check Soldering. 出力端子の確認半田付けを確認

・

Check OUTPUT terminal (Each channels)

O.K. O.K.

END 終了

. ・

CX061、CY061

・

MUTE circuit：MUTE TR(TR303〜308、TR311〜322) TR-BASE terminal：about -9V (at MUTE off) BASE端子：約-9V (MUTE off 時)

・

Check Solderin

. Output Jack

・

各chのOUTPUT端子からの出力信号を確認する

. ・

CX061、CY061の接続確認

・

MUTE回路の確認：MUTE ＴＲ(TR303〜308、TR311〜322)

・

出力端子の半田付け確認

31

(2) SACD-SOURCE DIRECT ON (2) SACD-SOURCE DIRECT ON

接続確

半田付

出力信号の確

力信号の確

半田付けを確

（

出力信号の確

半田付けを確

[

)

[

)

（

13(SL/SR),14(MIXL/MIXR

：

ithout SACD)

13(SL/SR),14(MIXL/MIXR

：

ithout SACD)

動作の確

参

データ確

半田付けを確

データ確

半田付けを確

（

）

確認（

接続）

(

)

出力確

参

終

DVD-3910

Check connection Mecha UNIT Check Soldering.、FFC cable メカユニットとの

GU-3613-1(SYSTEM UNIT) ・ [CY302]:GU-3618 GU-3613-1(SYSTEM UNIT) ・ [CY302]:GU-3618 ・ [CX301]output signal ・ FFC cable、insert condition ・ [CX301]

O.K. O.K.

Check input signal : IC203 IC203の入 GU-3613-1(SYSTEM UNIT) N.G. Check Soldering. GU-3613-1(SYSTEM UNIT) N.G.

・

[IC203](EPM3128ATC) 75

256fs）,79(512fs),90(BCK),92 75（512fs:fs=44.1kHz）,79(1024fs),90(BCK),

LRCK）,93(TSD0：FL/FR),94(TSD1：SL/SR), 92（FL）,93(FR),94(C),96（SW）,97(SL),98(SR),

96（TSD2：C/SW）, 99(MIXL),100(MIXR)pinの確認

O.K. O.K.

Check output signal : IC203 IC203の GU-3613-1(SYSTEM UNIT) N.G. Check Soldering. GU-3613-1(SYSTEM UNIT) N.G. ・

・

IC203](EPM3128ATC

21

BCK）,22(LRCK),10(FL/FR),12(C/SW), 21（BCK）,22(LRCK),10(FL/FR),12(C/SW), ・

Check DSP operation DSP Ｒefer

(1) CD,DVD-VIDEO/AUDIO,(SACD-SOURCE DIRECT OFF) N.G. (1) CD,DVD-VIDEO/AUDIO,(SACD-SOURCE DIRECT OFF)

w

O.K. O.K.

N.G. ・ [CX301] N.G. ・ [CX301]

・

FB211〜217、IC205

・

FB211〜217、IC205

・

[IC203](EPM3128ATC)

・

IC203](EPM3128ATC

認

照

認

認・FFCケーブル、挿入状態の確認

認

w

け、FFCケーブルを確認

・

FB211〜217、IC205確認

84pin：1394-Ｈ

・

85pin：Fs=192/176.4-H 87pin：Ｈ

・

88pin：D.L.-Ｈ

認

O.K. O.K.

Check DATA Signal -1 GU-3613-1(SYSTEM UNIT) N.G. Check Soldering. GU-3613-1(SYSTEM UNIT) N.G.

・

[IC209](DSP)：output Ｒ378,384,385,409,398,666 86(FL),82(C）,81(SL),57(FR),62(SW),70(SR) 86(FL),82(C）,81(SL),57(FR),62(SW),70(SR)

・

[IC203](EPM3128ATC)：input

O.K. O.K.

Check DATA Signal -2 GU-3613-1(SYSTEM UNIT) N.G. Check Soldering. GU-3613-1(SYSTEM UNIT) N.G.

・

[IC203](EPM3128ATC)：output to DAC 44〜55pin

・

[IC221](DAC for S/SW),[IC222](DAC for SL/SR) : input

・

4〜7pin(DATA-1,DATA-2,BCK="L",MCK=64fs）

GU-3614

・・

Check DAC output 〜 DAC Ｒefer

(1) CD,DVD-VIDEO/AUDIO,(SACD-SOURCE DIRECT OFF)

AUDIO UNIT

[IC311](DAC for MIXL/MIXR),[IC312](DAC for FL/FR) : input 4〜7pin(DATA-1,DATA-2,BCK="L",MCK=64fs）

O.K. O.K.

END

・

CX332,CY332(Connection to AUDIO UNIT)

・ CX173,CX191

Connection to 1394 PWB

・

・・

GU-3614(AUDIO UNIT

・・

(1) CD,DVD-VIDEO/AUDIO,(SACD-SOURCE DIRECT OFF)

認 -1

[IC209](DSP)：output Ｒ378,384,385,409,398,666の確認

[IC203](EPM3128ATC)：input

認 -2

[IC203](EPM3128ATC)：output to DAC 44〜55pin [IC221](DAC for S/SW),[IC222](DAC for SL/SR) : input 4〜7pin(DATA-1,DATA-2,BCK="L",MCK=64fs）

[IC311](DAC for MIXL/MIXR),[IC312](DAC for FL/FR) : input 4〜7pin(DATA-1,DATA-2,BCK="L",MCK=64fs）

認〜

照

了

認

・

CX332,CY332の確認(AUDIO UNITとの接続)

・ CX173,CX191の

認

1394 PWBとの

32

3. GU-3613-2 (VIDEO UNIT) 3. GU-3613-2 (VIDEO UNIT)

プログレッシブ映像

出力せず

電源電圧確認

半田付けを確認

周辺回路

映像用デジタル信号の確認

半田付けを確認

入力

映像用デジタル信号の確認

半田付けを確認

出力

発振波形確認

半田付けを確認

周辺回路

制御用

確認

半田付けを確認

周辺回路

制御信号の確認

半田付けを確認

と

制御信号の確認

半田付けを確認

映像用デジタル信号の確認

半田付けを確認

出力

周辺回路

ビデオ

確認

周辺回路の半田付けを確認

(1) Progressive output [Y,Pb,Pr] does not outputed. (1)

Check Power Supply Voltages. GU-3613-2(VIDEO UNIT) N.G Check Soldering. GU-3613-2(VIDEO UNIT) N.G

・ +3.3V_D3, +5V_V1, +2.5V_V1, +1.8V_V1 ・ [CY051],[IC715],[IC716] ・ +3.3V_D3, +5V_V1, +2.5V_V1, +1.8V_V1 ・ [CY051],[IC715],[IC716] ・ [IC704](FN4321DEN):(VccINT) +1.5V ・ Circumference of [IC705](BA15BCOFP) ・ [IC704](FN4321DEN):(VccINT) +1.5V ・ [IC705](BA15BCOFP)

O.K. O.K.

[Y,Pb,Pr]

DVD-3910

Check Digital signal for Video[1]. Check Soldering. GU-3613-2(VIDEO UNIT) N.G ・ [CY331]:23-30,11,10,21pin GU-3613-2(VIDEO UNIT) N.G ・ [CY331]:23-30,11,10,21pin

・ [IC704]input: ・ [IC704]:125,128-134,140,139,16pin ・ [IC704]

[PC2.-9.],[VSIN],[HSIN],[CLK1] ・ RA751,RA752,R701,R702,R753 [PC2.-9.],[VSIN],[HSIN],[CLK1] ・ RA751,RA752,R701,R702,R753

O.K. O.K.

Check Digital signal for Video[2]. Check Soldering. GU-3613-2(VIDEO UNIT) N.G ・ [IC704]:74-85,100pin GU-3613-2(VIDEO UNIT) N.G ・ [IC704]:74-85,100pin

・ [IC704]output / [IC718](FLI2310)input: ・ [IC718]:195,196,199-205,207,208pin ・ [IC704]

[PC2-9],[HSYNC],[VSYNC],[CLK0] ・ RA723,RA724,R930,R931 [PC2-9],[HSYNC],[VSYNC],[CLK0] ・ RA723,RA724,R930,R931

O.K. O.K.

Check oscillation waveform. Check Soldering. GU-3613-2(VIDEO UNIT) N.G ・ Circumference of [X731](13.5MXTAL) GU-3613-2(VIDEO UNIT) N.G ・ [X731](13.5MXTAL)

・ [IC718]:[XTAL_IN]191pin ・ [IC718]:[XTAL_IN]191pin

13.5MHz(3.3V) O.K.? 13.5MHz(3.3V) O.K.?

O.K. O.K.

Check PROM for [IC704]controled. N.G Check Soldering. [IC704] GU-3613-2(VIDEO UNIT) ・ Circumference of [IC703] GU-3613-2(VIDEO UNIT) ・ [IC703]

・ [IC703](EPCS1SI8) ・ [IC703](EPCS1SI8)

O.K. O.K.

: ・ [IC704]:125,128-134,140,139,16pin

/ [IC718](FLI2310)入力: ・ [IC718]:195,196,199-205,207,208pin

PROMの

[1]

[2]

N.G

Check control signal for [IC704]. N.G Check Soldering. [IC704] GU-3613-2(VIDEO UNIT) ・ [CY331]:1-3,9pin,R701-R703 GU-3613-2(VIDEO UNIT) ・ [CY331]:1-3,9pin,R701-R703

・ [IC704]:[MD],[MC],[ML],[RST_V] ・ [IC704]:4-6,2pin,R752,R755,R757,R758 ・ [IC704]:[MD],[MC],[ML],[RST_V] ・ [IC704]:4-6,2pin,R752,R755,R757,R758

O.K. O.K.

Check control signal for [IC718] and [IC701]. N.G Check Soldering. [IC708] GU-3613-2(VIDEO UNIT) ・ [CY331]:9,14,15pin GU-3613-2(VIDEO UNIT) ・ [CY331]:9,14,15pin

・ [SDA],[SCK],[RST_V] ・ [IC718]:45-47pin,R915-R917 ・ [SDA],[SCK],[RST_V] ・ [IC718]:45-47pin,R915-R917

・ [IC701]:21,22,33pin,R718,R719,R737 ・ [IC701]:21,22,33pin,R718,R719,R737

O.K. O.K.

Check Digital signal for Video[3]. Check Soldering. GU-3613-2(VIDEO UNIT) N.G ・ [IC718]:144-155,126-137,125,118,119pin GU-3613-2(VIDEO UNIT) N.G ・ [IC718]:144-155,126-137,125,118,119pin

・ [IC718]output / [IC701](ADV7310)input: ・ R945,R947,R948 ・ [IC718]

[YO0-9],[CO0-9],[P_HSYNC],[P_VSYNC] ・ [IC701]:2-13,14-18,23,24,26-30,32pin [YO0-9],[CO0-9],[P_HSYNC],[P_VSYNC] ・ [IC701]:2-13,14-18,23,24,26-30,32pin [CLK_P/I],[PS_CLK] ・ RA701-RA704,RA707,R723,R729 [CLK_P/I],[PS_CLK] ・ RA701-RA704,RA707,R723,R729

・ Circumference of [IC702](SN74LVC157APW) ・ [IC702](SN74LVC157APW)

O.K. O.K.

Check Video Encoder[1] circuit. GU-3613-2(VIDEO UNIT) N.G Check the soldering [IC701] GU-3613-2(VIDEO UNIT) N.G [IC701]とその

・ [IC701]: and circumference soldering of [IC701]. ・ [IC701]:

O.K. O.K.

[IC701]

[3]

/ [IC701](ADV7310)入力: ・ R945,R947,R948

エンコーダー[1]回路の

N.G

33

DVD-3910

ビデオバ

確認

とその周辺回路の半田付けを確認

ビデオドライバー回路の確認

周辺回路の半田付けを確認

終

映像

ず

映像用デジタル信号の確認

半田付けを確認

終了

出力せず

制御信号の確認

半田付けを確認

映像用デジタル信号の確認

半田付けを確認

ビデオ

確認

とその周辺回路の半田付けを確認

ビデオバ

確認

周辺回路の半田付けを確認

ビデオドライバー回路の確認

周辺回路の半田付けを確認

終

Check Video Buffer circuit. GU-3613-2(VIDEO UNIT) N.G Check the soldering [TR701-TR703] GU-3613-2(VIDEO UNIT) N.G [TR701-TR703]

・ [TR701-TR703] and circumference soldering of [TR701-TR703]. ・ [TR701-TR703] ・ [VR702-VR704] ・ [VR702-VR704]

O.K. O.K.

Check Video Driver circuit. GU-3613-2(VIDEO UNIT) N.G Check the soldering [IC708] GU-3613-2(VIDEO UNIT) N.G [IC708]とその

・ [IC708](BH7862F) and circumference soldering of [IC708]. ・ [IC708](BH7862F)

O.K. O.K.

END

(2) Interlace output [Y,Cb,Cr] does not outputed. (2) インターレース

Check Digital signal for Video[4]. Check Soldering. GU-3613-2(VIDEO UNIT) N.G ・ [IC701]:53-55,58-62,49,50pin GU-3613-2(VIDEO UNIT) N.G ・ [IC701]:53-55,58-62,49,50pin

・ [IC701]input: ・ RA705,RA706,R726,R728 ・ [IC701]input: ・ RA705,RA706,R726,R728

[PC2-9],[HSYNC],[VSYNC],[CLK0] [PC2-9],[HSYNC],[VSYNC],[CLK0]

O.K. O.K.

END

ッファー回路の

了

[Y,Cb,Cr] 出力せ

[4]

(3) Interlace output [V-OUT,S-OUT] does not outputed. (3)インターレース映像 [V-OUT,S-OUT]

Check control signal for [IC710](ADV7310). N.G Check Soldering. [IC710](ADV7310) GU-3613-2(VIDEO UNIT) ・ [IC701]:21,22,33pin,R839,R840,R858 GU-3613-2(VIDEO UNIT) ・ [IC701]:21,22,33pin,R839,R840,R858

・ [SDA],[SCK],[RST_V] ・ [SDA],[SCK],[RST_V]

O.K. O.K.

Check Digital signal for Video[5]. Check Soldering. GU-3613-2(VIDEO UNIT) N.G ・ [IC710]:53-55,58-62,49,50pin GU-3613-2(VIDEO UNIT) N.G ・ [IC710]:53-55,58-62,49,50pin

・ [IC710]input: ・ RA714,RA715,R847,R852,R853 ・ [IC710]input: ・ RA714,RA715,R847,R852,R853

[PC2-9],[HSYNC],[VSYNC],[CLK0] [PC2-9],[HSYNC],[VSYNC],[CLK0]

O.K. O.K.

Check Video Encoder[2] circuit. N.G GU-3613-2(VIDEO UNIT) Check the soldering [IC710] GU-3613-2(VIDEO UNIT) [IC710]

・ [IC710]: and circumference soldering of [IC710]. ・ [IC710]:

O.K. O.K.

Check Video Buffer circuit. GU-3613-2(VIDEO UNIT) N.G Check the soldering [TR713],[TR714] GU-3613-2(VIDEO UNIT) N.G [TR713-TR714]とその

・ [TR713],[TR714] and circumference soldering of [TR713],[TR714]. ・ [TR713],[TR714] ・ [VR709],[VR710] ・ [VR709],[VR710]

O.K. O.K.

エンコーダー[2]回路の

ッファー回路の

[5]

N.G

Check Video Driver circuit. GU-3613-2(VIDEO UNIT) N.G Check the soldering [IC708] GU-3613-2(VIDEO UNIT) N.G [IC708]とその

・ [IC708](BH7862F) and circumference soldering of [IC708]. ・ [IC708](BH7862F)

END

O.K. O.K.

了

34

DVD-3910

ELECTRICAL ADJUSTMENT FOR VIDEO

ビデオ回路の調整

1. SETTING

(1) Connect the monitor TV to the video output terminal. (2) Connect the oscilloscope to the Y-signal and C-signal of

S-VIDEO output terminal and each terminate at 75 Ohms.

(3) Connect the oscilloscope to the Y-signal, P

PR-signal of Component video output terminal and each terminate at 75 Ohms.

※ Use the 75 Ohms resistance must be 1%

(4) DVD test disc : DVDT-S01

B-signal and

2. BEFORE ADJUSTMENT

2.1. Setting the Oscilloscope as below.

(1) PB/PR

(a) TIME/DIV : 20μS (b) VOLT/DIV : 100mV

(Use the probe : x10 )

(2) Y/C

(a) TIME/DIV : 20μS (b) VOLT/DIV : 50mV

(Use the probe : x10 )

Power on. Power Supply USA & Canada : 120V Europe : 230V Japan : 100V

1. セッティング手順

(1) セットの VIDEOOUT端子にテレビモニターを接続す

る。

(2) セットの S2VIDEOOUT端子から Y信号と C信号をそれ

ぞれオシロスコープ（終端抵抗：75Ω）に接続する。

(3) セットの COMPONENTVIDEOOUTの端子（Y/P

をそれぞれオシロスコープ（終端抵抗：75Ω）に接続する。

※ 75Ω 抵抗は 1％品を使用する事。

(4) DVD テストディスク：DVDT-S01 を用意する。

B/PR）

2. 調整のまえに

2.1. オシロスコープを下記に設定する。

(1) PB/PR

(a) TIME/DIV : 20μS (b) VOLT/DIV : 100mV

（プローブ x10 使用）

(2) Y/C

(a) TIME/DIV : 20μS (b) VOLT/DIV : 50mV

（プローブ x10 使用）

電源電圧：100V

2.2. Preparation

(1) power on. (2) Push [OPEN/CLOSE] button, then open the Disc Tray. (3) Set DVD test disc (DVDT-S01) on the Disc Tray, and

then push [CLOSE] button.

(4) FL display appear “STOP”, push [PLAY] button to play-

back DVD.

(5) Push the [DISPLAY] button of remote control unit and

then appear the ON-Screen Display (GUI) on the monitor

TV. (6) Push the [+10] and [2] button, select title 12 of DVD. (7) Push the [ENTER] button, playback title 12. (color bar

75%)

2.2. 準備手順

(1) セットの AC コードをコンセントへ挿入し、セットの

電源を ON する。

(2) セットの「OPEN/CLOSE」ボタンを押しトレイを開き、

トレイ上に DVD テストディスク（DVDT-S1）をセット後、「CLOSE」ボタンを押す。

(3) セット表示管上に "STOP" が表示されてから、PLAY ボ

タンを押し、ディスクを再生する。

(4) リモコンの DISPLAY ボタンを押しグラフィカル・ユー

ザー・インターフェイス (GUI) 画面を出す。

(5) 番号ボタンの [+10][2] ボタンを押し、Title12 を選択す

る。

(6) 「ENTER」ボタンを押し、Title12 を再生する（75％カ

ラーバー信号）。

35

DVD-3910

2.3. Procedure

(1) Adjust the signal of S-VIDEO out by the wave of oscillo-

scope.

(a) Target, Y-signal

Point : VR709 Adjustment Value : 1000 ± 20mV Waveform

Y

Y-signal of S-VIDEO out

(b) Target, C-signal

Point : VR710 Adjustment Value : 286 ± 5mV Waveform

C

2.3. 手順

(1) セットの S2VIDEOOUT の信号レベルをオシロスコープ

上の波高値で調整する。

(a) Y 信号レベル

調整個所：VR709 調整値：1000 ± 20mV 波形

Y

S2VIDEO OUT の Y 信号レベル

(b) C 信号レベル

調整個所：VR710 調整値：286 ± 5ｍV 波形

C

C-signal of S-VIDEO out

(2) Adjust the signal of COMPONENT OUT by the wave of

oscilloscope.

(a) Target, Y-signal

Point : VR702 Adjustment Value : 1000 ± 20mV

Waveform

Y

Y-signal

(b) Target, PB-signal

Point : VR703 Adjustment Value : *525 ± 10mV Waveform

S2VIDEO OUT の C 信号レベル

(2) COMPONENTOUTの信号レベルをオシロスコープ上の

波高値で調整する。

(a) Y 信号レベル

調整個所：VR702 調整値：1000 ± 20ｍV 波形

Y

プログレッシブの Y 信号レベル

(b) P

B/CB 信号レベル

調整個所：VR703 調整値：525 ± 10ｍV 波形

PB-signal

PB

PB信号レベル

36

DVD-3910

(c) Target, PR-signal

Point : VR704 Adjustment Value : *525 ± 10mV Waveform

P

R

PR-signal

* : 486 ± 10mV for U.S.A. & Canada model

(c) PR 信号レベル

調整個所：VR704 調整値：525 ± 10ｍV 波形

PR

信号レベル

PR

37

BLOCK DIAGRAM

6

DVD-3910

38

SEMICONDUCTORS / 半導体一覧表

()

Only major IC's are shown, general IC's etc. are omitted to list.

主な半導体を記載しています。汎用の半導体等は記載を省略しています。

●IC's

Note: Abbreviation ahead of IC No. indicates the name of P.W.B., etc.

注 ):ICNo.の前の記号は、基板の名称を表します。

MA: Main P.W.B. IE : IEEE1394 P.W.B. SY: System P.W.B. AP: Audio/Power P.W.B.

CXD1885Q(MA:IC507)

Top View

DRAM I/F PWM.FG D/A

DVD-3910

DV

DD33

RD8

TEST0

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

TEST7

TEST8

TEST9

TEST10

TEST11

TEST12

TEST13

TEST14

TEST15

MODSEL0

MODSEL1

DV

MODSEL2

GIO0

GIO1

GIO2

GIO3

DD33

DV

GIO4

GIO5

GIO6

GIO7

DV

DD18

GIO8

GIO9

GIO10

General Port

GIO11

GIO12

DV

GIO13

GIO14

GIO15

GIO16

GIO17

GIO18

GIO19

TRST

TMS

JTAG Test/Monitor Pin

TCK

TDO

VMCHG

DVDD18

18

DD

DV

RD9

RD10

RD11

RD12

RD13

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

SS

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

SS

195

196

197

198

199

200

201

202

203

204

TDI

205

206

207

208

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

33

MA0

ALCR

MSEL0

MSEL1

MA1

DD

DV

RD14

MA2

RD15

MA3

RD0

MA4

RD1

MA5

RD2

MA6

RD3

MA7

RD4

MA8

SS

RD5

DV

MD0

TESTSEL

RD6

MD1

RD7

MD2

XMWR

MD3

XRAS

MD4

RA0

MD5

18

DD

DV

SS

DV

RA1

MD6

RA2

MD7

RA3

MALE

RA4

MCS

33

DD

DV

MWR

RA5

SS

RA10

RA11

XMOE

XUCAS

XLCAS

GPWM5

GPWM4

GPWM3

GPWM2

GPWM1

GPWM0

SPWM2

VDT3

VDT2

VDT1

SPWM1FGAVSSDA3 (SLED2_TILT)

VDT0

HDRQ

VSTEM I/FClockB/E MCU I/F

VEFG

XHAC

RA6

RA7

RA8

RA9

DV

XI

SS

33

DD

DV

MRD

18

DD

MINT

MRDY

SYSCK

DV

SS

XO

DV

VDT7

VDT6

VDT5

VDT4

DA2 (FSCON)

DCK

XSHD

DA1 (SLED)

DA0 (TSCON)

105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156

DRVIRQ

DRVRST

33

DD

AV

DD18

104

VREFL

103

VREFH

102

AD9

101

AD8

100

AD7

99

AD6

98

AD5

97

AD4

96

AD3

95

AV

94

AD2

93

AD1

92

AD0

91

AVSS

90

AV

89

RC

88

LPF2

87

LPF1

86

VCOI

85

AV

84

VFBC

83

CHG

82

JMOUT

81

JMREF

80

AV

79

IREF

78

TLC1

77

TLC0

76

HF

75

ATC

74

AV

73

DTC

72

MIRRORH

71

HFD

70

RFOKGH

69

SCLKH

68

SO

67

SI

66

CSL

65

EXPLDT

64

EXVCO

63

BCK

62

LRCK

61

DOTK

60

DADT

59

C2PO

58

DRVRDY

57

DRVCLK

56

DRVRX

55

DRVTX

54

DV

53

18

DD

DV

A/DData PLL/Data SlicerASP S-I/O, Defect etcAudio D/AVSTEM I/F

DD33

SS

DD18

DD33

SS

DD33

39

Block Diagram

DVD-3910

16/4M DRAM

HFD

HF

ASP

PWM

AT C

JTAG

Mecha control

Servo singnal

Data Slicer

Data-PLL

ASP Serial I/F

TZC

GIO

A/D

TC

Direction

ROM/RAM

ICU Timer

BCA

DVD Demodulation

CD-DSP (DDCD)

VSTEM Serial I/F

Spindle

DSP

Data

RAM

D/A PWM

CMD/ RSP reg.

Memory manager

CD-ROM Header Dec.

Peri. CLK

Audio I/F

ECC Core

EDC

MPEG I/F

DSP CLK/Mode

MCU I/F

ICU

Video

Serial Command

Audio

MCU

Servo control

X'tal

VSTEM

Functions (A/D : Analog/Digital, PU : Pull-up, PD : Pull-down, SMT=Schumitt )

No. Terminal Name I/O A/D Classification Function PU PD SMT

DD33 P VDD & GND Digital 3.3V Power for I/O.

1DV

2 ALCR I D MCU I/F Chip select input. (L: Reset) * *

3 MSEL0 I D MCU I/F MCU I/F mode select 0. *

4 MSEL1 I D MCU I/F MCU I/F mode select 1. *

5 MA0 I/O D MCU I/F MCU Adress input 0 / data I/O 0 <LSB>. *

6 MA1 I/O D MCU I/F MCU Adress input 1 / data I/O 1. *

7 MA2 I/O D MCU I/F MCU Adress input 2 / data I/O 2. *

8 MA3 I/O D MCU I/F MCU Adress input 3 / data I/O 3. *

9 MA4 I/O D MCU I/F MCU Adress input 4 / data I/O 4. *

10 MA5 I/O D MCU I/F MCU Adress input 5 / data I/O 5. *

11 MA6 I/O D MCU I/F MCU Adress input 6 / data I/O 6. *

12 MA7 I/O D MCU I/F MCU Adress input 7 / data I/O 7. *

13 MA8 I D MCU I/F MCU Adress input 8 <MSB>. *

14 TESTSEL I D MCU I/F TEST Select input. *

15 MD0 I/O D MCU I/F MCU data I/O 0 <LSB>. *

16 MD1 I/O D MCU I/F MCU data I/O 1. *

17 MD2 I/O D MCU I/F MCU data I/O 2. *

18 MD3 I/O D MCU I/F MCU data I/O 3. *

19 MD4 I/O D MCU I/F MCU data I/O 4. *

20 MD5 I/O D MCU I/F MCU data I/O 5. *

SS PVDD & GND Digital Ground.

21 DV

22 MD6 I/O D MCU I/F MCU data I/O 6. *

23 MD7 I/O D MCU I/F MCU data I/O 7 <MSB>. *

24 MALE I D MCU I/F MCU Adress latch signal input. *

25 MCS I D MCU I/F MCU Chip Select signal input. *

26 MWR I D MCU I/F MCU Write strobe signal. *

DD

27 DV

28 MRD I D MCU I/F MCU Read Strobe signal. *

29 MRDY O D MCU I/F MCU Ready signal. (L: Wait)

30 MINT O D MCU I/F MCU Interrupt signal. (L: Interrupt request)

33 P VDD & GND digital 3.3V Power. (for I/O )

40

DVD-3910

No. Terminal Name I/O A/D Classification Function PU PD SMT

31 SYSCK O D Clock Clock Monitor output.

DD

32 DV

33 XI I D Clock Crystal oscillation input.

34 XO O D Clock Crystal oscillation output.

35 DV

36 VDT7 O D VSTEM A/V MPEG data output 7.

37 VTD6 O D VSTEM A/V MPEG data output 6.

38 DV

39 VDT5 O D VSTEM A/V MPEG data output 5.

40 VDT4 O D VSTEM A/V MPEG data output 4.

41 VDT3 O D VSTEM A/V MPEG data output 3.

42 VDT2 O D VSTEM A/V MPEG data output 2.

43 VDT1 O D VSTEM A/V MPEG data output 1.

44 VDT0 O D VSTEM A/V MPEG data output 0.

45 HDRQ I D VSTEM A/V MPEG data Request input. *

46 XHAC O D VSTEM A/V Data Valid output.

47 VEFG O D VSTEM A/V ECC Error-sector Flag output. (L: error sector)

48 XSHD O D VSTEM A/V DVD Sector Head Flag output.

49 DCK O D VSTEM A/V Data Strobe output.

50 DRVIRQ O D VSTEM Command Interrupt Request output for Host. (L: interruption is demanded)

51 DRVRST I D VSTEM Command Drive H/W Reset input. (L: reset) * *

52 DV

53 DV

54 DRVTX O D VSTEM Command Transmitting serial data output to Host.

55 DRVRX I D VSTEM Command Reception serial data input from Host.

56 DRVCLK I D VSTEM Command Clock input from Host. *

57 DRVRDY O D VSTEM Command Drive Ready signal output. (L: ready)

58 C2PO O D Audio I/F CD-DSP C2 Pointer output.

59 DADT O D Audio I/F Audio serial data output.

60 DOTX O D Audio I/F Digital audio output.

61 LRCK O D Audio I/F L/R Clock output.

62 BCK O D Audio I/F Audio Bit Clock output.

63 EXVCO I D TEST/Monitor External Channel clock input.

64 EXPLDT I D TEST/Monitor External RF data input. (Logic level)

65 CSL O D ASP I/F SIO for RF signal processing LSI control. Latch signal output.

66 SI I D ASP I/F SIO for RF signal processing LSI control. Serial data input.

67 SO O D ASP I/F SIO for RF signal processing LSI control. Serial data output.

68 SCLKH O D ASP I/F SIO for RF signal processing LSI control. Serial clock output.

69 RFOKGH I D ASP I/F RF O.K. Signal input. *

70 HFD I D ASP I/F RF lack Signal input. *

71 MIRRORH I D ASP I/F Mirror detected signal input.(H: Mirror detected) *

72 DTC I D ASP I/F Track cross signal input. (Logic level input) *

73 AV

74 ATC I A Data PLL Track Cross signal input. (Analog level input)

75 HF I A Data PLL RF signal input.

76 TLC0 O A Data PLL Asymmetry Charge-pump output 0.

77 TLC1 O A Data PLL Asymmetry Charge-pump output 1

78 IREF I A Data PLL Reference current setting terminal for Asymmetry Circuit.

79 AV

80 JMREF I A Data PLL Reference current setting terminal for Jitter Monitor

81 JMOUT O A Data PLL Jitter Monitor output.

82 CHG I A Data PLL Reference current setting terminal for data PLL.

83 VFBC I A Data PLL VCO offset frequency setting terminal for data PLL.

84 AV

85 VCOI I A Data PLL VCO Control voltage input terminal for data PLL.

86 LPF1 O A Data PLL VCO Loop-filter connection terminal 1 for data PLL.

87 LPF2 O A Data PLL VCO Loop-filter connection terminal 2 for data PLL

88 RC I A Data PLL VCO gain setting terminal for data PLL.

89 AV

90 AV

91 AD0 I A ADC AD0 Input.

18 P VDD & GND Digital 1.8V Power. (Internal logic system power)

SS

DD

18 P VDD & GND Digital 1.8V power for Internal logic system.

DD

33 P VDD & GND Digital 3.3V Power for I/O.

SS

DD33 P VDD & GND Analog 3.3V Power.

DD18 P VDD & GND Analog 1.8V Power.

SS

PV

DD

& GND Digital Ground.

DD

& GND Digital Ground.

DD

& GND Analog Ground.

DD

& GND Analog Ground.

DD

& GND Analog Ground.

41

DVD-3910

No. Terminal Name I/O A/D Classification Function PU PD SMT

92 AD1 I A ADC AD1 Input.

93 AD2 I A ADC AD2 Input.

DD

94 AV

95 AD3 I A ADC AD3 Input.

96 AD4 I A ADC AD4 Input.

97 AD5 I A ADC AD5 Input.

98 AD6 I A ADC AD6 Input.

99 AD7 I A ADC AD7 Input.

100 AD8 I A ADC AD8 Input.

101 AD9 I A ADC AD9 Input.

102 VREFH I/O A ADC Max Reference Voltage input for ADC.

103 VREFL I/O A ADC Min Reference Voltage input for ADC.

104 AV

105 AV

106 DA0 (TSCON) O A DAC DA0 output. (Track Servo output)

107 DA1 (SLED) O A DAC DA1 output. (Sled Servo output)

108 DA2 (FSCON) O A DAC DA2 output. (Forcus Servo output)

109 DA3 (SLED2_

110 AV

111 FG I D SPM FG signal input. *

112 SPWM1 O D SPM Spindle motor PWM output 1.

113 SPWM2 O D SPM Spindle motor PWM output 2.

114 GPWM0 O D General PWM Multi-purpose PWM output 0.

115 GPWM1 O D General PWM Multi-purpose PWM output 1.

116 GPWM2 O D General PWM Multi-purpose PWM output 2.

117 GPWM3 O D General PWM Multi-purpose PWM output 3.

118 GPWM4 O D General PWM Multi-purpose PWM output 4.

119 GPWM5 O D General PWM Multi-purpose PWM output 5.

120 XLCAS O D DRAM I/F DRAM LCAS output. (Low-Byte row address strobe output)

121 XUCAS O D DRAM I/F DRAM UCAS output. (Upper-Byte row address strobe output)

122 XMOE O D DRAM I/F DRAM output enable.

123 RA11 O D DRAM I/F DRAM address output terminal 11.

124 RA10 O D DRAM I/F DRAM address output terminal 10.

125 DV

126 RA9 O D DRAM I/F DRAM address output terminal 9.

127 RA8 O D DRAM I/F DRAM address output terminal 8.

128 RA7 O D DRAM I/F DRAM address output terminal 7.

129 RA6 O D DRAM I/F DRAM address output terminal 6.

130 RA5 O D DRAM I/F DRAM address output terminal 5.

131 DV

132 RA4 O D DRAM I/F DRAM address output terminal 4.

133 RA3 O D DRAM I/F DRAM address output terminal 3.

134 RA2 O D DRAM I/F DRAM address output terminal 2.

135 RA1 O D DRAM I/F DRAM address output terminal 1.

136 DV

137 RA0 O D DRAM I/F DRAM address output terminal 0.

138 XRAS O D DRAM I/F DRAM RAS output. (Column address strobe output)

139 XMWR O D DRAM I/F DRAM Write enable.

140 RD7 I/O D DRAM I/F DRAM data input/output terminal 7. *

141 RD6 I/O D DRAM I/F DRAM data input/output terminal 6. *

142 DV

143 RD5 I/O D DRAM I/F DRAM data input/output terminal 5. *

144 RD4 I/O D DRAM I/F DRAM data input/output terminal 4. *

145 RD3 I/O D DRAM I/F DRAM data input/output terminal 3. *

146 RD2 I/O D DRAM I/F DRAM data input/output terminal 2. *

147 RD1 I/O D DRAM I/F DRAM data input/output terminal 1. *

148 RD0 I/O D DRAM I/F DRAM data input/output terminal 0. *

149 RD15 I/O D DRAM I/F DRAM data input/output terminal 15. *

33 P VDD & GND Analog 3.3V Power.

(Internal Reference Voltage mode, it will be an output state)

DD18 P VDD & GND Analog 1.8V Power.

DD33 P VDD & GND Analog 3.3V Power.

O A DAC DA3 output. (Sled Servo / Tilt Servo output)

TILT)

SS

DD

33 P VDD & GND Digital 3.3V Power. (for I/O)

DD18 P VDD & GND Digital 1.8V Power. (for Internal Logic power)

SS PVDD & GND Digital Ground.

PV

DD

& GND Analog Ground

DD

& GND Digital Ground.

42

DVD-3910

No. Terminal Name I/O A/D Classification Function PU PD SMT

150 RD14 I/O D DRAM I/F DRAM data input/output terminal 14. *

151 RD13 I/O D DRAM I/F DRAM data input/output terminal 13. *

152 RD12 I/O D DRAM I/F DRAM data input/output terminal 12. *

153 RD11 I/O D DRAM I/F DRAM data input/output terminal 11. *

154 RD10 I/O D DRAM I/F DRAM data input/output terminal 10. *

155 RD9 I/O D DRAM I/F DRAM data input/output terminal 9. *

DD

156 DV

157 DV

158 RD8 I/O D DRAM I/F DRAM data input/output terminal 8. *

159 TEST0 O D TEST/Monitor TEST I/O 0.

160 TEST1 O D TEST/Monitor TEST I/O 1.

161 TEST2 O D TEST/Monitor TEST I/O 2.

162 TEST3 O D TEST/Monitor TEST I/O 3.

163 TEST4 O D TEST/Monitor TEST I/O 4.

164 TEST5 O D TEST/Monitor TEST I/O 5.

165 TEST6 O D TEST/Monitor TEST I/O 6.

166 TEST7 O D TEST/Monitor TEST I/O 7.

167 TEST8 O D TEST/Monitor TEST I/O 8.

168 TEST9 O D TEST/Monitor TEST I/O 9.

169 TEST10 O D TEST/Monitor TEST I/O 10.

170 TEST11 O D TEST/Monitor TEST I/O 11.

171 TEST12 O D TEST/Monitor TEST I/O 12.

172 TEST13 O D TEST/Monitor TEST I/O 13.

173 TEST14 O D TEST/Monitor TEST I/O 14.

174 TEST15 O D TEST/Monitor TEST I/O 15.

175 MODSEL0 I D TEST/Monitor TEST mode select 0. (GND, under normal conditions)

176 MODSEL1 I D TEST/Monitor TEST mode select 1. (GND, under normal conditions)

177 DV

178 MODSEL2 I D TEST/Monitor TEST mode select 2. (GND, under normal conditions)

179 GIO0 I/O D Multi-purpose Multi-purpose port 0. * *

180 GIO1 I/O D Multi-purpose Multi-purpose port 1. * *

181 GIO2 I/O D Multi-purpose Multi-purpose port 2. * *

182 GIO3 I/O D Multi-purpose Multi-purpose port 3. * *

183 DV

184 GIO4 I/O D General Port Multi-purpose port 4. * *

185 GIO5 I/O D General Port Multi-purpose port 5. * *

186 GIO6 I/O D General Port Multi-purpose port 6. * *

187 GIO7 I/O D General Port Multi-purpose port 7. * *

188 DV

189 GIO8 I/O D General Port Multi-purpose port 8. * *

190 GIO9 I/O D General Port Multi-purpose port 9. * * *

191 GIO10 I/O D General Port Multi-purpose port 10. * *

192 GIO11 I/O D General Port Multi-purpose port 11. * *

193 GIO12 I/O D General Port Multi-purpose port 12. * * *

194 DV

195 GIO13 I/O D Multi-purpose Multi-purpose port 13. * * *

196 GIO14 I/O D General Port Multi-purpose port 14. * * *

197 GIO15 I/O D General Port Multi-purpose port 15. * * *

198 GIO16 I/O D General Port Multi-purpose port 16. * *

199 GIO17 I/O D General Port Multi-purpose port 17. * *

200 GIO18 I/O D General Port Multi-purpose port 18. * *

201 GIO19 I/O D General Port Multi-purpose port 19. * *

202 TRST I D JTAG I/F JTAG Reset input. * *

203 TMS I D JTAG I/F JTAG Mode Select input. * *

204 TDI I D JTAG I/F JTAG Data Input. * *

205 TCK I D JTAG I/F JTAG Clock input. *

206 TDO O D JTAG I/F JTAG Data output.

207 VMCHG I D MCU I/F VSTEM / external MCU access selection terminal of system set-

208 DV

18 P VDD & GND Digital 1.8V Power. (for internal Logic system)

DD

33 P VDD & GND Digital 3.3V power for I/O.

SS

DD

33 P VDD & GND Digital 3.3V Power for I/O.

DD

18 P VDD & GND Digital 1.8V Power for I/O. (for internal Logic system)

SS PVDD & GND Digital Ground.

PV

DD

& GND Digital Ground.

ting register for DSP. (L: VSTEM, H: external MCU)

DD

18 P VDD & GND Digital 1.8V power for internal Logic system.

43

ES6138F (MA: IC108)

PINOUT DIAGRAM

HA1/AUX4[3]

VSS

155

156

LA0 LA1 LA2 LA3

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

1

2 3 4 5 6 7 8 910111213141516171819202122232425262728293031323334353637383940414243444546474849505152

VEE

/AUX4[4]

HA2

I2CDATA/AUX[0] I2C_CLK/AUX[1]

VEE

AUX[2]/IOW#

VSS VEE

AUX[3]/IOR#

AUX[4] AUX[5] AUX[6] AUX[7]

LOE#

VSS

VCC LCS0# LCS1# LCS2# LCS3#

VSS LD0 LD1 LD2 LD3 LD4 VEE VSS LD5 LD6 LD7 LD8 LD9

LD10

LD11

VSS

VEE LD12 LD13 LD14 LD15

LWRLL#

LWR HL#

VSS

VEE

CAMIN0 CAMIN1

VSS

HA0/AUX4[2]

HCS3FX#/AUX3[6]

HCS1FX#/AUX3[7]

152

153

154

HIOCS16#/CAMCLK/AUX3[4]

151

HWR#/DCI_CLK/AUX4[5]

HRD#/DCI_ACK#/AUX4[6]

VEE

VSS

HIORDY/AUX3[3]

HIRQ/DCI_ERR#/AUX4[7]

HRST#/AUX3[5]

HRRQ#/AUX4[0]

143

144

145

146

147

148

149

150

HWRQ#/DCI_REQ#/AUX4[1]

142

HD15/AUX2[7]/IR

HD14/AUX2[6]

VCC

139

140

141

VSS

HD13/AUX2[5]/SP

HD12/AUX2[4]/C2PO

HD11/AUX2[3]//IRQ

135

136

137

138

ES6138F

HD10/AUX2[2]

HD9/AUX2[1]

HD8/DCI_FDS#/AUX2[0]/VFD_CLK

HD7/DCI7/AUX1[7]/VFD_DIN

131

132

133

134

VEE

130

VSS

129

HD6/DCI6/AUX1[6]/VFD_DOUT

128

HD5/DCI5/AUX1[5]

127

HD4/DCI4/AUX1[4]

126

HD3/DCI3/AUX1[3]

125

HD2/DCI2/AUX1[2]

124

HD1/DCI1/AUX1[1]

123

HD0/DCI0/AUX1[0]

122

VCC

121

VSS

120

HSYNC#/CAMIN7/AUX3[0]

119

VSYNC#/CAMIN6/AUX3[1]

118

PCLKQSCN/CAMIN5/AUX3[2]

117

PCLK2XSCN/CAMIN4

116

YUV7/FDAC/CAMIN3

YUV6/VDAC

YUV5/YDAC

113

114

115

ADVSS

ADVEE

111

112

YUV4/RSET

YUV3/COMP

YUV2/CDAC

YUV1/VREF

107

108

109

110

YUV0/CAMIN2/UDAC

DCLK

105

106

104

VEE

103

VSS

102

DSCK

101

DQM

100

DCS0#

99

VEE

98

VSS

97

DCS1#

96

DB15

95

DB14

94

DB13

93

DB12

92

VEE

91

VSS

90

DB11

89

DB10

88

DB9

87

DB8

86

DB7

85

DB6

84

VSS

83

VCC

82

DB5

81

DB4

80

DB3

79

DB2

78

DB1

77

DB0

76

VSS

75

VEE

74

DMBS1

73

DMBS0

72

DRAS#

71

DWE#

70

DOE#/DSCK_EN

69

DCAS#

68

VEE

67

VSS

66

DMA11

65

DMA10

64

DMA9

63

DMA8

62

DMA7

61

DMA6

60

VSS

59

VEE

58

DMA5

57

DMA4

56

DMA3

55

DMA2

54

DMA1

53

DMA0

DVD-3910

NC

LA4

LA5

LA6

LA7

LA8

VEE

LA9

VSS

VCC

LA11

LA10

LA12

VSS

LA13

VEE

LA14

LA15

LA16

LA17

LA18

LA19

VSS

VEE

LA21

LA20

RESET#

TDMDX/RSEL

TDMDR

TDMCLK

VSS

VCC

TSD2

TDMFS

TDMTSC#

TWS/SEL_PLL2

TSD0/SEL_PLL0

TSD3

TSD1/SEL_PLL1

TBCK

MCLK

SPDIF_IN

SEL_PLL3/SPDIF_OUT

VSS

VCC

RSD

RWS

RBCK

XIN

AVE E

XOUT

AVS S

44

ES6138F Pin Description

Name Pin Numbers I/O Definition

VEE 1,18, 27, 59, 68, 75,

92, 99, 104, 130,

148, 157, 159, 164,

183, 193, 201

P I/O power supply.

DVD-3910

LA[21:0]

VSS 8, 17, 26, 34, 43,

VCC

RESET# 24 I Reset input (active-low).

TDMDX

RSEL I LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ

TDMDR 28 I TDM receive data input.

TDMCLK 29 I TDM clock input.

TDMFS 30 I TDM frame sync input.

2:7, 10:16, 19:23,

204:207

60, 67, 76, 84, 91,

98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192,

200, 208

9, 35, 44, 83, 121,

139, 172

25

O RISC port address bus.

G Ground.

P Core power supply.

O TDM transmit data output.

resistor; read only during reset.

RSEL Selection

0 16-bit ROM

1 8-bit ROM

TDMTSC# 31 O TDM output enable (active-low).

TWS

SEL_PLL2 I System and DSCK output clock frequency selection is made at the rising edge of

32

O Audio transmit frame sync output.

RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Strapped to VCC or ground via 4.7-kΩ resistor; read only during reset.

SEL_PLL2 SEL_PLL1 SEL_PLL0 PLL Settings

0 0 0 DCLK × 4.5

001DCLK × 5.0

0 1 0 Bypass

011DCLK × 4.0

1 0 0 DCLK × 4.25

1 0 1 DCLK × 4.75

110DCLK × 5.5

111DCLK × 6.0

45

ES6138F Pin Description (Continued)

Name Pin Numbers I/O Definition

DVD-3910

TSD0

33

SEL_PLL0 I Refer to the description and matrix for SEL_PLL2 pin 32.

TSD1

36

SEL_PLL1 I Refer to the description and matrix for SEL_PLL2 pin 32.

TSD2 37 O Audio transmit serial data output 2.

TSD3 38 O Audio transmit serial data output 3.

NC 48 — No connect pins. Leave open.

MCLK 39 I/O Audio master clock for audio DAC.

TBCK 40 O Audio transmit bit clock.

SEL_PLL3

41

SPDIF_OUT O S/PDIF output.

SPDIF_IN 42 I S/PDIF input.

O Audio transmit serial data port 0.

O Audio transmit serial data port 1.

I Clock source select. Strapped to VCC or ground via 4.7-kΩ resistor; read only

during reset.

SEL_PLL3 Clock Source

0 Crystal oscillator

1 DCLK input

RSD 45 I Audio receive serial data.

RWS 46 I Audio receive frame sync.

RBCK 47 I Audio receive bit clock.

XIN 49 I 27-MHz crystal input.

XOUT 50 O 27-MHz crystal output.

AVEE 51 P Analog power for PLL.

AVSS 52 G Analog ground for PLL.

DMA[11:0] 53:58, 61:66 O DRAM address bus.

DCAS# 69 O DRAM column address strobe.

DOE#

70

DSCK_EN O DRAM clock enable.

DWE# 71 O DRAM write enable (active-low).

DRAS# 72 O DRAM row address strobe (active-low).

DMBS0 73 O DRAM bank select 0.

DMBS1 74 O DRAM bank select 1.

DB[15:0] 77:82, 85:90, 93:96 I/O DRAM data bus.

DCS[1:0]# 97,100 O DRAM chip select (active-low).

O DRAM output enable (active-low).

DQM 101 O Data input/output mask.

46

ES6138F Pin Description (Continued)

Name Pin Numbers I/O Definition

DSCK 102 O Output clock to DRAM.

DCLK 105 I Clock input to PLL.

DVD-3910

YUV0

CAMIN2 I Camera YUV 2.

UDAC O Video DAC output.

106

O YUV pixel 2 output data.

Pin 115 114 113 108 106

Value F DAC V DAC Y DAC C DAC U DAC

0 CVBS/Chroma CVBS1 Y C N/A

1 CVBS/Chroma CVBS1 Y C CVBS2

2 CVBS/Chroma N/A Y C N/A

3 CVBS/Chroma CVBS1 N/A N/A CVBS2

4 CVBS/Chroma CVBS1 N/A N/A N/A

5 CVBS/Chroma CVBS1 Y Pb Pr

6 CVBS/Chroma N/A Y Pb Pr

7 N/A SYNC G B R

8 CVBS/Chroma Chroma Y Pb Pr

9 CVBS CVBS1 G B R

10 CVBS CVBS1 G R B

11 N/A SYNC G R B

12 CVBS/Chroma N/A Y Pr Pb

13 CVBS/Chroma CVBS1 Y Pr Pb

14 Chroma Y G R B

F: CVBS/chroma signal for simultaneous mode. Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal for YUV mode.

YUV1

107

VREF I Internal voltage reference to video DAC. Bypass to ground with 0.1-µF capacitor.

YUV2

108

CDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.

YUV3

109

COMP I Compensation input. Bypass to ADVEE with 0.1-µF capacitor.

YUV4

110

RSET I DAC current adjustment resistor input.

ADVEE 111 P Analog power for video DAC.

O YUV pixel 1 output data.

O YUV pixel 2 output data.

O YUV pixel 3 output data.

O YUV pixel 4 output data.

47

ES6138F Pin Description (Continued)

Name Pin Numbers I/O Definition

ADVSS 112 G Analog ground for video DAC.

DVD-3910

YUV5

YDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.

YUV6

VDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.

YUV7

FDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.

CAMIN3 I Camera YUV 3.

PCLK2XSCN

CAMIN4 I Camera YUV 4.

PCLKQSCN

CAMIN5 I Camera YUV 5.

AUX3[2] I/O Aux3 data I/O.

VSYNC#

CAMIN6 I Camera YUV 6.

AUX3[1] I/O Aux3 data I/O.

HSYNC#

CAMIN7 I Camera YUV 7.

113

114

115

116

117

118

119

O YUV pixel 5 output data.

O YUV pixel 6 output data.

O YUV pixel 7 output data.

I/O 27-MHz video output pixel clock.

O 13.5-MHz video output pixel clock.

I/O Vertical sync (active-low).

I/O Horizontal sync (active-low).

AUX3[0] I/O Aux3 data I/O.

HD[5:0]

DCI[5:0] I/O DVD channel data I/O.

AUX1[5:0] I/O Aux1 data I/O.

HD6

DCI6 I/O DVD channel data I/O.

AUX1[6] I/O Aux1 data I/O.

VFD_DOUT I VFD data output.

HD7

DCI7 I/O DVD channel data I/O.

AUX1[7] I/O Aux1 data I/O.

VFD_DIN I VFD data input.

HD8

DCI_FDS# I/O DVD input sector start (active-low).

AUX2[0] I/O Aux2 data I/O.

VFD_CLK I VFD clock input.

122:127

128

131

132

I/O Host data bus lines 5:0.

I/O Host data bus line 6.

I/O Host data bus line 7.

I/O Host data bus line 8.

48

ES6138F Pin Description (Continued)

Name Pin Numbers I/O Definition

DVD-3910

HD9

AUX2[1] I/O Aux2 data I/O.

HD10

AUX2[2] I/O Aux2 data I/O.

HD11

AUX2[3] I/O Aux2 data I/O.

IRQ O IRQ.

HD12

AUX2[4] I/O Aux2 data I/O.

C2PO I C2PO error correction flag from CD-ROM.

HD13

AUX2[5] I/O Aux2 data I/O.

SP I 16550 UART serial port input.

HD14

AUX2[6] I/O Aux2 data I/O.

HD15

AUX2[7] I/O Aux2 data I/O.

133

134

135

136

137

140

141

I/O Host data bus line 9.

I/O Host data bus line 10.

I/O Host data bus line 11.

I/O Host data bus line 12.

I/O Host data bus line 13.

I/O Host data bus line 14.

I/O Host data bus line 15.

IR I IR remote control input.

HWRQ#

DCI_REQ# O DVD control interface request (active-low).

AUX4[1] I/O Aux4 data I/O.

HRRQ#

AUX4[0] I/O Aux4 data I/O.

HIRQ

DCI_ERR# I/O DVD channel data error (active-low).

AUX4[7] I/O Aux4 data I/O.

HRST#

AUX3[5] I/O Aux3 data I/O.

HIORDY

AUX3[3] I/O Aux3 data I/O.

HWR#

DCI_CLK I/O DVD channel data clock.

AUX4[5] I/O Aux4 data I/O.

142

143

144

145

146

149

O Host write request (active-low).

O Host read request (active-low).

I/O Host interrupt.

O Host reset (active-low).

I Host I/O ready.

I/O Host write (active-low).

49

ES6138F Pin Description (Continued)

Name Pin Numbers I/O Definition

DVD-3910

HRD#

DCI_ACK# O DVD channel data valid (active-low).

150

O Host read (active-low).

AUX4[6] I/O Aux4 data I/O.

HIOCS16#

CAMCLK I Camera port pixel clock input.

151

I Device 16-bit data transfer (active-low).

AUX3[4] I/O Aux3 data I/O.

HCS1FX#

O Host select 1 (active-low).

152

AUX3[7] I/O Aux3 data I/O.

HCS3FX#

O Host select 3 (active-low).

153

AUX3[6] I/O Aux3 data I/O.

HA[2:0]

I/O Host address bus.

154, 155, 158

AUX4[4:2] I/O Aux4 data I/Os.

AUX[0]

160

I2CDATA I/O I

AUX[1]

161

I2C_CLK I/O I

AUX[2]

I/O Auxiliary port 0 (open collector).

2

C data I/O.

I/O Auxiliary port 1 (open collector).

2

C clock I/O.

I/O Auxiliary port.

162

IOW# O I/O write strobe (LCS1) (active-low).

AUX[3]

I/O Auxiliary port.

165

IOR# O I/O read strobe (LCS1) (active-low).

AUX[6:4] 166:168 I/O Auxiliary ports.

AUX[7] 169 I/O Auxiliary port.

LOE# 170 O RISC port output enable (active-low).

LCS[3:0]# 173:176 O RISC port chip select (active-low).

LD[15:0]

178:182,

185:191,194:197

I/O RISC port data bus.

LWRLL# 198 O RISC port low-byte write enable (active-low).

LWRHL# 199 O RISC port high-byte write enable (active-low).

CAMIN0 202 I Camera YUV 0.

CAMIN1 203 I Camera YUV 1.

50

FLI2310 (SY: IC718)

t

Block Diagrams

DVD-3910

Port 2 8-bit 656 Input

Port 1 8/16/24-bit RGB/YCrCb Input

Pin Diagram

HSYNC1_PORT1

VSYNC1_PORT1

FIELD ID1_PORT1

IN_CLK1_PORT1

HSYNC2_PORT1

VSYNC2_PORT1

FIELD ID2_PORT1

VDD1

VSS

IN_CLK2_PORT1

B/Cb/D1_0

B/Cb/D1_1

B/Cb/D1_2

B/Cb/D1_3

B/Cb/D1_4

VDDcore1

VSScore

B/Cb/D1_5

B/Cb/D1_6

B/Cb/D1_7 R/Cr/Cb Cr_0

R/Cr/Cb Cr_1

R/Cr/Cb Cr_2

R/Cr/Cb Cr_3

R/Cr/Cb Cr_4

R/Cr/Cb Cr_5 R/Cr/Cb Cr_6

R/Cr/Cb Cr_7

G/Y/Y_0

VDD2

VSS

G/Y/Y_1 G/Y/Y_2

G/Y/Y_3

G/Y/Y_4

VDDcore2

VSScore

G/Y/Y_5

G/Y/Y_6 G/Y/Y_7

IN_SEL

TEST DEV_ADDR1

DEV_ADDR0

SCLK

SDATA

RESET_N

VDD3

VSS

SDRAM DATA(0)

SDRAM DATA(1) SDRAM DATA(2)

Input Processor with Auto Sync and auto Adjust

Clock

Generation

PLLs

FIELD ID_PORT2

HSYNC_PORT2

VSYNC_PORT2

D1_IN_7

D1_IN_6

D1_IN_5

2 0 5

1

5

1 0

1 5

2 0

2 5

3 0

3 5

4 0

4 5

5 0

5 5

Noise Reducer,

Deinterlacer, Frame

Rate Converter and

SDRAM interface

Vertical and

Horizontal

Scalers

Output

Processor

16/20/24-bi

RBG/YCrCb

Digital Outputs

2Mx32

SDRAM

(external)

IN_CLK_PORT2

XTAL IN

XTAL OUT

VDD9

VSS

D1_IN_4

D1_IN_0

D1_IN_3

D1_IN_2

D1_IN_1

VDDcore8

VSScore

1 9 5

2 0 0

6 0

6 5

TEST2

1 9 0

7 0

R_VSS

R_VDD

TEST0

TEST1

R_VDD

R_VSS

R_VDD

1 8 5

7 5

R_VSS

Reserved

1 8 0

8 0

R_VDD

Reserved

8 5

Vertical and

Horizontal Enhancers

R_VDD

R_VSS

R_VDD

Reserved

1 7 5

9 0

Reserved

1 7 0

R_VSS

R_VDD1.8

AVSS_PLL_FE

AVDD_PLL_FE

AVDD_PLL_SDI

AVSS_PLL_BE2

AVSS_PLL_SDI

1 6 5

9 5

AVDD_PLL_BE2

1 0 0

AVDD_PLL_BE1

1 6 0

PLL_PVDD

PLL_PVSS

AVSS_PLL_BE1

OE

G/Y/Y_OUT_7

1 5 5

G/Y/Y_OUT_6

G/Y/Y_OUT_5

G/Y/Y_OUT_4

G/Y/Y_OUT_3

G/Y/Y_OUT_2

1 5 0

G/Y/Y_OUT_1

G/Y/Y_OUT_0

VSS

VDD8

1 4 5

1 4 0

1 3 5

1 3 0

1 2 5

1 2 0

1 1 5

1 1 0

1 0 5

R/V/Pr_OUT_7

R/V/Pr_OUT_6

R/V/Pr_OUT_5

R/V/Pr_OUT_4

R/V/Pr_OUT_3

R/V/Pr_OUT_2

VSScore

VDDcore7 R/V/Pr_OUT_1

R/V/Pr_OUT_0

B/U/Pb_OUT_7

B/U/Pb_OUT_6

B/U/Pb_OUT_5

B/U/Pb_OUT_4

B/U/Pb_OUT_3

B/U/Pb_OUT_2

VSS VDD7

B/U/Pb_OUT_1

B/U/Pb_OUT_0

CLKOUT

VSScore

VDDcore6

CTLOUT4

CTLOUT3

CTLOUT2

CTLOUT1

CTLOUT0 TEST OUT1

TEST OUT0

TEST3 SDRAM CLKIN

VSS

VDD6

SDRAM CLKOUT

SDRAM DQM SDRAM CSN

SDRAM BA0 SDRAM BA1

SDRAM CASN SDRAM RASN

VSS

VDD4

SDRAM DATA(3)

SDRAM DATA(5)

SDRAM DATA(4)

SDRAM DATA(8)

SDRAM DATA(7)

SDRAM DATA(6)

SDRAM DATA(9)

SDRAM DATA(10)

SDRAM DATA(12)

SDRAM DATA(11)

VSScore

VDDcore3

SDRAM DATA(17)

SDRAM DATA(16)

SDRAM DATA(14)

SDRAM DATA(13)

SDRAM DATA(15)

SDRAM DATA(18)

SDRAM DATA(21)

SDRAM DATA(20)

SDRAM DATA(19)

SDRAM DATA(22)

SDRAM DATA(24)

SDRAM DATA(23)

SDRAM DATA(25)

VSScore

VDDcore4

SDRAM DATA(28)

SDRAM DATA(26)

SDRAM DATA(27)

VSS

VDD5

TEST IN

SDRAM DATA(31)

SDRAM DATA(30)

SDRAM DATA(29)

SDRAM ADDR(9)

SDRAM ADDR(10)

SDRAM ADDR(7)

SDRAM ADDR(8)

SDRAM ADDR(6)

VSScore

VDDcore5

SDRAM ADDR(5)

SDRAM ADDR(4)

SDRAM ADDR(3)

SDRAM ADDR(2)

SDRAM ADDR(0)

SDRAM ADDR(1)

SDRAM WEN

51

Pin details

DVD-3910

Pin No Pin Name I/O Type

1

HSYNC1_PORT1 Input 5v

2

VSYNC1_PORT1 Input 5v FIELD ID1_PORT1

3

IN_CLK1_PORT1

4 5

HSYNC2_PORT1 Input 5v

6

VSYNC2_PORT1 Input 5v FIELD ID2_PORT1

7

VDD1

8

VSS

9

IN_CLK2_PORT1

10

B/Cb/D1_0

11

B/Cb/D1_1

12

B/Cb/D1_2

13

B/Cb/D1_3

14

B/Cb/D1_4

15

VDDcore1

16

VSScore

17

B/Cb/D1_5

18

B/Cb/D1_6

19

B/Cb/D1_7

20

R/Cr/Cb Cr_0

21

R/Cr/Cb Cr_1

22

R/Cr/Cb Cr_2

23

R/Cr/Cb Cr_3

24

R/Cr/Cb Cr_4

25

R/Cr/Cb Cr_5

26

R/Cr/Cb Cr_6

27

R/Cr/Cb Cr_7

28

G/Y/Y_0

29

VDD2

30

VSS

31

G/Y/Y_1

32

G/Y/Y_2

33

G/Y/Y_3

34

G/Y/Y_4

35

VDDcore2

36

VSScore

37

G/Y/Y_5

38

G/Y/Y_6

39

G/Y/Y_7

40 41

IN_SEL Output 5v 8 mA 42 TEST Input 5v 43

DEV_ADDR1 Input 5v 44

DEV_ADDR0 Input 5v

Input 5v Input 5v

Input 5v

Power 3.3 V - Power pin for IO

Ground Ground

Input 5v Input 5v Input 5v Input 5v Input 5v Input 5v

Power 1.8 V - Power pin for core

Ground Ground

Input 5v Input 5v Input 5v Input 5v Input 5v Input 5v Input 5v Input 5v Input 5v Input 5v Input 5v Input 5v

Power 3.3 V - Power pin for IO

Ground Ground

Input 5v Input 5v Input 5v Input 5v

Power 1.8 V - Power pin for core

Ground Ground

Input 5v Input 5v Input 5v

Voltage

Tolerance Drive

Pull up/

Pulldown Description

Horizontal sync or reference -CTL1 of Port 1 Vertical sync or reference -CTL1 of Port 1 Odd/Even Field identification -CTL1 of Port 1 Data Clock input -CTL1 of Port 1 Horizontal sync or reference –CTL2 of Port 1 Vertical sync or reference –CTL2 of Port 1 Odd/Even Field identification –CTL2 of Port 1

Data Clock input –CTL2 of Port 1 Port 1 – Digital video input (Blue/Cb/D1) Port 1 – Digital video input (Blue/Cb/D1) Port 1 – Digital video input (Blue/Cb/D1) Port 1 – Digital video input (Blue/Cb/D1) Port 1 – Digital video input (Blue/Cb/D1)

Port 1 – Digital video input (Blue/Cb/D1) Port 1 – Digital video input (Blue/Cb/D1) Port 1 – Digital video input (Blue/Cb/D1) Port 1 – Digital video input (Red/Cr/CrCb) Port 1 – Digital video input (Red/Cr/CrCb) Port 1 – Digital video input (Red/Cr/CrCb) Port 1 – Digital video input (Red/Cr/CrCb) Port 1 – Digital video input (Red/Cr/CrCb) Port 1 – Digital video input (Red/Cr/CrCb) Port 1 – Digital video input (Red/Cr/CrCb) Port 1 – Digital video input (Red/Cr/CrCb) Port 1 – Digital video input (Green/Y)

Port 1 – Digital video input (Green/Y) Port 1 – Digital video input (Green/Y) Port 1 – Digital video input (Green/Y) Port 1 – Digital video input (Green/Y)

Port 1 – Digital video input (Green/Y) Port 1 – Digital video input (Green/Y) Port 1 – Digital video input (Green/Y) Output to select external video mux Connect to Ground

Device address setting 1

Device address setting 0

52

DVD-3910

No Pin Name I/O Type

45 SCLK 46 SDATA 47 RESET_N 48 VDD3 49 VSScore 50 SDRAM DATA(0) 51 SDRAM DATA(1) 52 SDRAM DATA(2) 53 SDRAM DATA(3) 54 SDRAM DATA(4) 55 SDRAM DATA(5) 56 SDRAM DATA(6) 57 SDRAM DATA(7) 58 SDRAM DATA(8) 59 SDRAM DATA(9) 60 SDRAM DATA(10) 61 SDRAM DATA(11) 62 VDD4 63 VSS 64 SDRAM DATA(12) 65 SDRAM DATA(13) 66 SDRAM DATA(14) 67 SDRAM DATA(15) 68 VDDcore3 69 VSScore 70 SDRAM DATA(16) 71 SDRAM DATA(17) 72 SDRAM DATA(18) 73 SDRAM DATA(19) 74 SDRAM DATA(20) 75 SDRAM DATA(21) 76 SDRAM DATA(22) 77 SDRAM DATA(23) 78 SDRAM DATA(24) 79 SDRAM DATA(25) 80 VDDcore4 81 VSScore 82 SDRAM DATA(26) 83 SDRAM DATA(27) 84 SDRAM DATA(28) 85 SDRAM DATA(29) 86 SDRAM DATA(30) 87 SDRAM DATA(31) 88 VDD5

I/O I/O

Input

Power

Ground Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O

Power

Ground Tristate I/O Tristate I/O Tristate I/O Tristate I/O

Power

Ground Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O

Power

Ground Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O Tristate I/O

Power

Voltage

Tolerance Drive

5v 8 mA 2-wire serial control bus clock 5v 8 mA 2-wire serial control bus data 5v PU Reset

3.3 V – Power pin for IO

Ground 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD

3.3 V – Power pin for IO

Ground 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD

1.8 V - Power pin for core

Ground 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD

1.8 V – Power pin for core

Ground 5v 4 mA PD SDRAM data bus * 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD 5v 4 mA PD

3.3 V – Power pin for IO

Pull up/

Pulldown Description

SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus *

SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus *

SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus *

SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus * SDRAM data bus *

53

DVD-3910

No Pin Name I/O Type

89 VSS 90 TEST IN 91 SDRAM ADDR(10) 92 SDRAM ADDR(9) 93 SDRAM ADDR(8) 94 SDRAM ADDR(7) 95 SDRAM ADDR(6) 96 VDDcore5 97 VSScore 98 SDRAM ADDR(5)

99 SDRAM ADDR(4) 100 SDRAM ADDR(3) 101 SDRAM ADDR(2) 102 SDRAM ADDR(1) 103 SDRAM ADDR(0) 104 SDRAM WEN 105 SDRAM RASN 106 SDRAM CASN 107 SDRAM BA1 108 SDRAM BA0 109 SDRAM CSN 110 SDRAM DQM 111 SDRAM CLKOUT 112 VDD6 113 VSS 114 SDRAM CLKIN 115 TEST3 116 TEST OUT0

TEST OUT1 / Interrupt

117

Out Output

118 CTLOUT0

119 CTLOUT1

120 CTLOUT2

121 CTLOUT3

122 CTLOUT4

123 VDDcore6 124 VSScore 125 CLKOUT 126 B/U/Pb_OUT_0 127 B/U/Pb_OUT_1

Ground

Input Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P

Power

Ground Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P

Output

Power

Ground

Input Input

Output

Tristate O/P

Power

Ground Tristate O/P Tristate O/P Tristate O/P

Voltage

Tolerance Drive

Ground

5V Test input-Connect to ground

5v 8 mA SDRAM address bus * 5v 8 mA SDRAM address bus * 5v 8 mA SDRAM address bus * 5v 8 mA SDRAM address bus * 5v 8 mA SDRAM address bus *

1.8 V – Power pin for core

Ground 5v 8 mA SDRAM address bus * 5v 8 mA SDRAM address bus * 5v 8 mA SDRAM address bus * 5v 8 mA SDRAM address bus * 5v 8 mA SDRAM address bus * 5v 8 mA SDRAM address bus * 5v 8 mA SDRAM write enable * 5v 8 mA SDRAM row address select * 5v 8 mA SDRAM column address select * 5v 8 mA SDRAM bank select 1* 5v 8 mA SDRAM bank select 0* 5v 4 mA SDRAM CS * 5v 8 mA SDRAM DQM * 5v 12 mA Clock out to SDRAM *

3.3 V - Power pin for IO

Ground 5v Trace delayed SDRAM Clock in

Test input – Connect to ground

Test output – leave open

Interrupt Output

5v 8 mA

1.8 V - Power pin for core

Ground 5v 12 mA Output data rate clock 5v 8 mA 5v 8 mA

Pull up/

Pulldown Description

Control signal output selectable as HSync1/ CSync/HRef/Monitor coast

Control signal output selectable as VSync1/CRef/VRef/Film Indicator

Control signal output selectable as Monitor coast/HRef/VDD_en / HSync2

Control signal output selectable as Film Indicator/VRef/backlight_en/VSync2

Control signal output selectable as CRef/Field ID/CSync/Monitor coast

Digital video output – Blue/U/Pb Digital video output – Blue/U/Pb

54

DVD-3910

No

Pin Name I/O Type

128 VDD7 129 VSS 130 B/U/Pb_OUT_2 131 B/U/Pb_OUT_3 132 B/U/Pb_OUT_4 133 B/U/Pb_OUT_5 134 B/U/Pb_OUT_6 135 B/U/Pb_OUT_7 136 R/V/Pr_OUT_0 137 R/V/Pr_OUT_1 138 VDDcore7 139 VSScore 140 R/V/Pr_OUT_2 141 R/V/Pr_OUT_3 142 R/V/Pr_OUT_4 143 R/V/Pr_OUT_5 144 R/V/Pr_OUT_6 145 R/V/Pr_OUT_7 146 VDD8 147 VSS 148 G/Y/Y_OUT_0

G/Y/Y_OUT_1

149

G/Y/Y_OUT_2

150

G/Y/Y_OUT_3

151

G/Y/Y_OUT_4

152

G/Y/Y_OUT_5

153

G/Y/Y_OUT_6

154

G/Y/Y_OUT_7

155 156 OE 157 PLL_PVDD 158 PLL_PVSS 159 AVSS_PLL_BE1 160 AVDD_PLL_BE1 161 AVDD_PLL_BE2 162 AVSS_PLL_BE2 163 AVSS_PLL_SDI 164 AVDD_PLL_SDI 165 AVDD_PLL_FE 166 AVSS_PLL_FE 167 DAC_PVSS 168 DAC_VDD 169 DAC_VSS 170 DAC_BOUT 171

DAC_AVDDB

Power

Ground Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P

Power

Ground Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P

Power

Ground Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P

Input

Power Ground Ground

Power

Power Ground Ground

Power

Power Ground Ground

Power Ground

Output

Power

Voltage

Tolerance

3.3 V – Power pin for IO

Ground 5v 8 mA Digital video output – Blue/U/Pb 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA Digital video output – Red/V/Pr 5v 8 mA Digital video output – Red/V/Pr

1.8 V – Power pin for core

Ground 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA

3.3 V – Power pin for IO

Ground 5v 8 mA Digital video output – Green/Y 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA 5v 8 mA 5v Output data enable for Digital video output

1.8 V – Power pin for PLL pads

Ground for PLL pads

PLL Ground

1.8 V – Power pin for PLL

PLL Ground

1.8 V – Power pin for PLL

PLL Ground

Ground for DAC pads

1.8 V – Digital power pin for DAC

DAC digital Ground

34 mA Analog B/U output

3.3 V – Analog power pin for B channel

Drive

Pull up/

Pulldown

Description

Digital video output – Blue/U/Pb Digital video output – Blue/U/Pb Digital video output – Blue/U/Pb Digital video output – Blue/U/Pb Digital video output – Blue/U/Pb

Digital video output – Red/V/Pr Digital video output – Red/V/Pr Digital video output – Red/V/Pr Digital video output – Red/V/Pr Digital video output – Red/V/Pr Digital video output – Red/V/Pr

Digital video output – Green/Y Digital video output – Green/Y Digital video output – Green/Y Digital video output – Green/Y Digital video output – Green/Y Digital video output – Green/Y Digital video output – Green/Y

55

DVD-3910

No

Pin Name I/O Type

172 DAC_AVSSB 173 DAC_GOUT 174 DAC_AVDDG 175 DAC_AVSSG 176 DAC_ROUT 177 DAC_AVDDR 178 DAC_AVSSR 179 DAC_COMP 180 DAC_RSET

181 DAC_VREFOUT

182 DAC_VREFIN 183 DAC_AVDD 184 DAC_AVSS 185 DAC_GR_AVSS 186 DAC_GR_AVDD 187 DAC_PVDD 188 TEST0 189 TEST1 190 TEST2 191 XTAL IN 192 XTAL OUT 193 VDD9 194 VSS 195 IN_CLK_PORT 2 196 D1_IN_0 197 VDDcore8 198 VSScore Ground Ground 199 D1_IN_1 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input 200 D1_IN_2 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input 201 D1_IN_3 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input 202 D1_IN_4 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input 203 D1_IN_5 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input 204 D1_IN_6 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input 205 D1_IN_7 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input 206 FIELD ID_PORT 2 207 VSYNC_ PORT 2 208 HSYNC_PORT 2

Ground

Output

Power

Ground

Output

Power

Ground

Output Output Output

Input

Power Ground Ground

Power

Input Input Input Input

Output

Power Ground

Input Input

Power

Input Input Input

Voltage

Tolerance

Analog Ground for B channel 34 mA Analog G/Y output

3.3 V – Analog power pin for G channel Analog Ground for G channel 34 mA Analog R/V output

3.3 V – Analog power pin for R channel Analog Ground for R channel Compensation for video DACs Current setting resistor for video DACs

External Voltage reference for video DACs

3.3 V – Analog power pin for DAC Analog Ground for DAC Ground for DAC Guard ring

3.3 V – Power pin for DAC Guard ring

3.3 V –Power pin for DAC pads 5v Test pin – connect to ground 5v Test pin – connect to ground 5v Test pin – connect to ground

External parallel crystal oscillator External parallel crystal oscillator

3.3 V - Power pin for IO

Ground 5v 4 mA Port 2 - Data Clock input 5v 4 mA Port 2 - ITU-R BT656 digital data input

1.8 V – Power pin for core

5v 4 mA Port 2 - Odd/Even Field identification 5v 4 mA Port 2 - Vertical sync or reference 5v 4 mA Port 2 - Horizontal sync or reference

Drive

Pull up/

Pulldown

Description

1.28 V Internally generated voltage reference for video DACs

Note: * - The connection of these pins depends on the type of external SDRAM used.

56

CXD2753R (MA: IC405)

Pin Assignment

DVD-3910

Block Diagram

57

DVD-3910

Pin Name I/O Functions

1 VSC - It fixed to ground.( for Core)

2 XMSLAT I Latch input for µCOM serial communication.

3 MSCK I Shift clock input for µCOM serial communication.

4 MSDATI I Data input for µCOM serial communication.

5 VDC - +2.5V Power for Core.

6 MSDATO O Data output for µCOM serial communication. “Hi-Z” potential except the output mode.

7 MSREADY O Completion flag of output preparation for µCOM serial communication. “L” is outputted at the time of

8 XMSDOE O Output enable pin for µCOM serial communication. “L” is outputted at the time of MSDATO mode.

9 XRST I Reset pin. The whole IC is reset by at the time of “L” potential.

10 SMUTE Ipd Soft Mute. Soft mute of the audio output is carried out at the time of “H” potential.

11 MCKI I Master Clock input.

12 VSIO - It fixed to Ground. Ground for I/O.

13 EXCKO1 O External output Clock 1.

14 EXCKO2 O External output Clock 2.

15 LRCK O 44.1kHz, 1Fs Clock output.

16 FRAME O Frame signal output.

17 VDIO - +3.3V Power for I/O.

18 MNT0 O Monitor output.

19 MNT1 O Monitor output.

20 MNT2 O Monitor output.

21 MNT3 O Monitor output.

22 TESTO O Output terminal for a Test. (open)

23 TESTO O Output terminal for a Test.(open)

24 TESTO O Output terminal for a Test.(open)

25 TESTO O Output terminal for a Test.(open)

26 TCK I Clock input for a Test. It fixed to “L” potential.

27 TDI Ipu Input pin(pull-up) for a Test.(open)

28 VSC - It fixed to Ground. Ground for CORE.

29 TDO O Output for a Test.(open).

30 TMS Ipu Input pin(pull-up) for a Test.(open)

31 TRST Ipu Reset pin(pull-up) for a Test. Input the Power-on reset signal or fixed to “L” potential.

32 TEST1 I Test input pin. It fixed to “L” potential.

33 TEST2 I Test input pin. It fixed to “L” potential.

34 TEST3 I Test input pin. It fixed to “L” potential.

35 VDC - +2.5V Power for CORE.

36 TESTO O Out put for TEST. It fixed to open.

37 XBIT O DST monitor.

38 SUPDT0 O Supplementary data output. (LSB)

39 SUPDT1 O Supplementary data output.

40 SUPDT2 O Supplementary data output.

41 SUPDT3 O Supplementary data output.

42 VSIO - Ground for I/O.

43 SUPDT4 O Supplementary data output.

44 SUPDT5 O Supplementary data output.

45 VDIO - +3.3V Power for I/O.

46 SUPDT6 O Supplementary data output.

47 SUPDT7 O Supplementary data output. (MSB)

48 XSUPAK O Supplementary data Acknowledge output terminal.

49 VSC - Ground for CORE.

completion.

It releases at the time of “L” potential.

58

Pin Name I/O Functions

50 TESTO O Output for TEST. (open)

51 TESTI I Input for TEST. It fixed to “L” potential.

52 TESTI I Input for TEST. It fixed to “L” potential.

53 TESTO O Output for TEST. (open)

54 VDC - +2.5V Power for CORE.

55 DSADML O DSD Data output terminal for Lch Down Mix.

56 DSADMR O DSD Data output terminal for Rch Down Mix.

57 BCKASL I I/O selection terminal of the Bit clock for DSD data output. L=input (Slave), H=output (Master)

58 VSDSD - Ground terminal for DSD data output.

59 BCKAI I Bit clock input terminal for DSD data output.

60 BCKAO O Bit clock output terminal for DSD data output.

61 PHREFI I Reference phase signal input terminal for DSD output phase modulation.

62 PHREFO O Reference phase signal output terminal for DSD output phase modulation.

63 ZDFL O Lch zero-data detection flag (at the time of µcom setup).

64 DSAL O DSD data output terminal for Lch speaker.

65 ZDFR O Rch zero-data detection flag (at the time of µcom setup).

66 DSAR O DSD data output terminal for Rch speaker.

67 V

DDSD - +3.3V Power for DSD data output.

68 ZDFC O Cch zero-data detection flag (at the time of µcom setup).

69 DSAC O DSD data output terminal for Cch speaker.

70 ZDFLFE O LFEch zero-data detection flag (at the time of µcom setup).

71 DSASW O DSD data output terminal for SWch speaker.

72 VSDSD - Ground for DSD data output.

73 ZDFLS O LSch zero-data detection flag (at the time of µcom setup).

74 DSALS O DSD data output terminal for LSch speaker.

75 ZDFRS O RSch zero-data detection flag (at the time of µcom setup).

76 DSARS O DSD data output terminal for RSch speaker.

77 V

DDSD O +3.3V Power for DSD data output.

78 IOUT0 O Data output terminal 0 for IEEE1394 link chip I/F.

79 IOUT1 O Data output terminal 1 for IEEE1394 link chip I/F.

80 VSC - Ground for CORE.

81 IOUT2 O Data output terminal 2 for IEEE1394 link chip I/F.

82 IOUT3 O Data output terminal 3 for IEEE1394 link chip I/F.

83 VDC - +2.5V Power for CORE.

84 IOUT4 O Data output terminal 4 for IEEE1394 link chip I/F.

85 IOUT5 O Data output terminal 5 for IEEE1394 link chip I/F.

86 VSIO - Ground for I/O.

87 IANCO O Transmission information data output terminal for IEEE1394 link chip I/F.

88 IFULL I Data transmission hold request signal input terminal for IEEE1394 link chip I/F.

89 IEMPTY I High speed transmission request signal input terminal for IEEE1394 link chip I/F.

90 VDIO - +3.3V Power for I/O.

91 IFRM O Frame reference signal output terminal for IEEE1394 link chip I/F.

92 IOUTE O Enable signal output terminal for IEEE1394 link chip I/F.

93 IBCK O Data transmission clock output terminal for IEEE1394 link chip I/F.

94 VSC - Ground for CORE.

95 TESTI I TEST input terminal. It fixed to “H” potential.

Input a Bit clock into this terminal at the time of BCKASL=”L” potential.

Bit clock output from this terminal at the time of BCKASL=”H” potential.

It will be set to “H” if non-sound data continues 300 msecs.

DVD-3910

59

Pin Name I/O Functions

96 TESTI I TEST input terminal. It fixed to “L” potential.

97 TESTI Ipu TEST input terminal. It fixed to “H” potential.

98 TESTO O TEST output terminal. (open)

99 VDC - +2.5V Power for CORE.

100 TESTI I TEST input terminal. It fixed to “L” potential.

101 TESTI I TEST input terminal. It fixed to “L” potential.

102 TESTI I TEST input terminal. It fixed to “L” potential.

103 TESTI I TEST input terminal. It fixed to “L” potential.

104 TESTI I TEST input terminal. It fixed to “L” potential.

105 TESTI I TEST input terminal. It fixed to “L” potential.

106 VSIO - Ground for I/O.

107 TESTI I TEST input terminal. It fixed to “L” potential.

108 TESTI I TEST input terminal. It fixed to “L” potential.

109 TESTI I TEST input terminal. It fixed to “L” potential.

110 VDIO - +3.3V Power for I/O.

111 WAD0 I External A/D data input terminal(LSB) for PSP physical disc mark detection.

112 WAD1 I External A/D data input terminal for PSP physical disc mark detection.

113 WAD2 I External A/D data input terminal for PSP physical disc mark detection.

114 WAD3 I External A/D data input terminal for PSP physical disc mark detection.

115 VSIO - Ground for I/O.

116 VSC - Ground for CORE.

117 WAD4 I External A/D data input terminal for PSP physical disc mark detection.

118 WAD5 I External A/D data input terminal for PSP physical disc mark detection.

119 WAD6 I External A/D data input terminal for PSP physical disc mark detection.

120 WAD7 I External A/D data input terminal(MSB) for PSP physical disc mark detection.

121 VDC - +2.5V Powe for CORE.

122 TESTI I TEST input terminal. It fixed to “L” potential.

123 WCK I Operation clock for PSP physical disc mark detection.

124 WAV

125 WAV

DD - +2.5V Power. A/D Power supply for PSP physical disc mark detection.

DD

- +2.5V Power. A/D Power supply for PSP physical disc mark detection.

126 WARFI Ai Analog RF signal input terminal for PSP physical disc mark detection.

127 WAVRB Ai A/D bottom reference terminal for PSP physical disc mark detection.

128 WAV

129 WAV

SS

- A/D Ground terminal for PSP physical disc mark detection.

130 VSIO - Ground for I/O.

131 DQ7 I/O SDRAM data input/output terminal. (MSB)

132 DQ6 I/O SDRAM data input/output terminal.

133 DQ5 I/O SDRAM data input/output terminal.

134 DQ4 I/O SDRAM data input/output terminal.

135 VDIO - +3.3V Power for I/O.

136 DQ3 I/O SDRAM data input/output terminal.

137 DQ2 I/O SDRAM data input/output terminal.

138 DQ1 I/O SDRAM data input/output terminal.

139 DQ0 I/O SDRAM data input/output terminal. (LSB)

140 VSIO - Ground for I/O.

141 DCLK O Clock output terminal for SDRAM.

142 DCKE O Clock enable output terminal for SDRAM.

143 XWE O Write enable output terminal for SDRAM.

144 XCAS O Colomn address strobe output terminal for SDRAM.

145 XRAS O Row address strobe output terminal for SDRAM.

146 VDIO - +3.3V Power for I/O.

147 TESTO O Output terminal for TEST. (open)

DVD-3910

60

Pin Name I/O Functions

148 A11 O Address output terminal for SDRAM. (MSB)

149 A10 O Address output terminal for SDRAM.

150 VSC - Ground for CORE.

151 A9 O Address output terminal for SDRAM.

152 A8 O Address output terminal for SDRAM.

153 VDC - +2.5V Power for CORE.

154 A7 O Address output terminal for SDRAM.

155 A6 O Address output terminal for SDRAM.

156 A5 O Address output terminal for SDRAM.

157 A4 O Address output terminal for SDRAM.

158 VSIO - Ground for I/O.

159 A3 O Address output terminal for SDRAM.

160 A2 O Address output terminal for SDRAM.

161 A1 O Address output terminal for SDRAM.

162 A0 O Address output terminal for SDRAM. (LSB)

163 VDIO - +3.3V Power for I/O.

164 XSRQ O Output terminal of the Data Request signal inputted a front-end processor.

165 XSHD I Input terminal of the header Flag outputted from a front-end processor.

166 SDCK I Input terminal of the data conveyance Clock outputted from a front-end processor.

167 XASK I Input terminal of the data valid Flag outputted from a front-end processor.

168 SDEF I Input terminal of the error Flag outputted from a front-end processor.

169 SD0 I Input terminal of the stream Data outputted from a front-end processor.

170 SD1 I Input terminal of the stream Data outputted from a front-end processor.

171 SD2 I Input terminal of the stream Data outputted from a front-end processor.

172 SD3 I Input terminal of the stream Data outputted from a front-end processor.

173 SD4 I Input terminal of the stream Data outputted from a front-end processor.

174 SD5 I Input terminal of the stream Data outputted from a front-end processor.

175 SD6 I Input terminal of the stream Data outputted from a front-end processor.

176 SD7 I Input terminal of the stream Data outputted from a front-end processor.

DVD-3910

Ipu: Pull-up input Ipd: Pull-down input Ai: Analog input

61

ADSP-21266SKSTZ1B-DVD (SY: IC209)

DVD-3910

144

1

PIN 1 INDICATOR

109

108

TOP VIEW

36

37

73

72

Terminal Function

LQFP

Pin Name

V

DDINT

Pin # Pin Name

1V

DDINT

CLKCFG0 2 GND 38 GND 74 V CLKCFG1 3 RD 39 V BOOTCFG0 4 ALE 40 GND 76 V

LQFP Pin # Pin Name

37 V

DDEXT

DDINT

LQFP Pin # Pin Name

73 GND 109

DDINT

75 GND 111

DDINT

BOOTCFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113 GND 6 AD14 42 DAI_P11 (SD3A) 78 V V

DDEXT

7 AD13 43 DAI_P12 (SD3B) 79 GND 115 GND 8 GND 44 DAI_P13 (SCLK23) 80 V V

DDINT

9V

DDEXT

45 DAI_P14 (SFS23) 81 GND 117 GND 10 AD12 46 DAI_P15 (SD4A) 82 V V

DDINT

11 V

DDINT

47 V

DDINT

83 GND 119 GND 12 GND 48 GND 84 V V

DDINT

13 AD11 49 GND 85 RESET 121

DDINT

DDEXT

DDINT

GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS 122 FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123 FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 V

DDINT

AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK45) 89 SPICLK 125 GND 18 V V

DDINT

19 GND 55 GND 91 MOSI 127

DDINT

54 V

DDINT

90 MISO 126

GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128 V

DDEXT

GND 22 GND 58 DAI_P20 (SFS45) 94 V V

DDINT

AD6 24 V

21 DAI_P3 (SCLK0) 57 V

23 V

DDEXT

DDINT

59 GND 95 A 60 V

DDEXT

DDINT

93 V

96 A

DDINT

DDEXT

VDD

VSS

AD5 25 GND 61 FLAG2 97 GND 133 AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 CLKOUT 134 V

DDINT

27 DAI_P5 (SD1A) 63 V

DDINT

99 EMU 135 GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136 AD3 29 DAI_P7 (SCLK1) 65 V AD2 30 V V

DDEXT

31 GND 67 V

GND 32 V

DDINT

66 GND 102 TRST 138

68 GND 104 TMS 140

AD1 33 GND 69 V

DDINT

101 TDI 137

103 TCK 139

105 GND 141 AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142 WR 35 DAI_P9 (SD2A) 71 V V

DDINT

36 V

DDINT

72 V

DDINT

107 XTAL 143

108 V

DDEXT

LQFP Pin #

110

112

114

116

118

120

124

129 130 131 132

144

62

M30620FCPGP(3910) (SY: IC202)

p

PIN CONFIGURATION (top view)

DVD-3910

P0 P0 P0 P0 P0 P02/AN P0 P0

P10 P10 P10 P10

P9

7

/AD

P9

6

/ANEX1/S

P9

5

/ANEX0/CLK4

7

/AN

6

/AN

5

/AN

4

/AN

3

/AN

1

/AN

0

/AN

7

/AN

6

/AN

5

4

P10 P10 P10

P10

TRG

P1

/AN /AN

P1 P1

3

2

1

2

/D

1

0

07

06

05

04

03

02

01

00

7

/KI

6

/KI

5

/KI

4/

/AN /AN /AN

AV

0

/AN

V

REF

AVcc

/S

OUT

)

3

/D

4

(/D

4

/A

4

P2

)

4

/D

5

(/D

5

/A

5

P2

)

5

/D

6

(/D

6

/A

6

P2

)

6

/D

7

(/D

7

/A

7

P2

Vss

)

7

(/-/D

8

/A

0

P3

Vcc

13

16

14

9

10

11

/A

1

2

3

P3

15

12

/A

5

4

P3

17

/A

0

6

7

1

P4

P3

P4

525354555657585960616263646566676869707172737475

51

P4

2

/A

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31 30 29

28

27 26

18

P4

3

/A

19

P4

4

/CS0

P4

5

/CS1

P4

6

/CS2

P4

7

/CS3

P5

0

/WRL/WR

P5

1

/WRH/BHE

2

/RD

P5 P53/BCLK P5

4

/HLDA

P5

5

/HOLD

P5

6

/ALE

P5

7

/RDY/CLK

P6

0

/CTS

P6

1

/CLK

P6

2

/RxD

P6

3

/T

X

P6

4

/CTS

P6

5

/CLK

P6

6

/RxD

P6

7/TX

0/TX

P7

1

/RxD

P7 P7

2

/CLK

0

/RTS

0

D

0

1

/RTS

1

D

1

D

2

/SDA/TA0

2

/SCL/TA0

2

/TA1

OUT

0

1

OUT

/CLKS

/V

OUT

IN

1

(Note)

/TB5

IN

(Note)

)

1

0

3

4

5

/INT

11

/D

3

P1

10

/D /D

/D /D /D /D /D /D /D /D

KI

SS

IN

76

9

77

8

78

7

79

6

80

5

81

4

82

3

83

2

84

1

85

0

86

3

87

2

88

1

89

0

90

3

91

2

92

1

93

94

0

95

96

97

4

98

4

99

00

1

1 2 3 4 5 6 7 8 9 10111213141516171819202122 23 24 25

/INT

13

12

14

15

/D

5

4

6

7

P1

2

/D

/-)

2

1

3

0

(/D

2

1

3

0

/A

2

1

3

0

P2

M16C/62N Group

IN

/TB4

/TB3

1

0

/DA

4

3

P9

Note: P7

3

IN

OUT

/S

IN

/S

IN

/TB1

1

/TB2

2

P9

0

and P7

BYTE

/CLK3

IN

/TB0

0

P9

CIN

/X

7

CNVss

P8

SS

OUT

V

COUT

X

/X

RESET

6

P8

1

are N channel o

1

2

/NMI

5

P8

/INT

4

P8

/INT

3

P8

0

IN

/U

OUT

IN

/INT

OUT

2

/TA3

7

/TA3

/TA4

P8

6

1

P7

/TA4

0

P7

P8

en-drain out

/W

IN

/TA2

5

P7

/W

OUT

/TA2

4

P7

/V

IN

/TA1

2

/RTS

2

/CTS

3

P7

ut

in.

IN

CC

X

V

63

PIN Description

PIN No

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

PIN NAME SYMBOL

1

TB4IN DSPSPICS

2

3

4

5

6

7

SOUT3 V-DATA

SIN3 ROM CONT 1

CLK3 V -CLK

BYTE

CNVss CNVss

8

9

RESET- RESET

XOUT CLOCK OUT

VSS GND

VCC VCC

INT2- OP_CS

INT1- W.REM

INT0- REMO

TA4OUT OPN_DRV

TA3OUT CLS_DRV

TA2IN

RTS2- PANEL_REQ

CLK2 OP_CLK

RXD2 OP_DI

TXD2 OP_DO

TXD1 SYSTXD

RXD1 SYSRXD

CLK1 CLK1

RTS1 1394_RST

TXD0 TXD1394

RXD0 RXD1394

CLK0 CLK1394

FRASH_EPM FRASH_EPM

FRASH_HCE FRASH_HCE

FUNCTION

P93 V-CS

BUS WIDTH

SEL

P87 NCS_1394

P86 48_96

XIN CLOCK IN

NMI MN TERMINAL

P81 OPEN 19

P77 LD CONT

DFRESET

P74 +1.8V_ON/OFF

P60 SEL_1394

P57 EXTMIXIN

P56 192_OTHER

P54 D.L.ON

P53 DSD_SEL

P52 FILM_ON

P51 EMUTE

P47 DIR_CLK

P46 DIR_DI

P45 DIR_DO

P44 DIR_CS

P43 ERROR

P42 CFLUG

I/O

DESCRIPTION

O DSP CONTROL SIGNAL

VFD CONTROL SIGNAL(CS) / H=NEGATE , L=ASSERT

I/O

VFD CONTROL SIGNAL(DATA)

I/O

NOT USED

I/O

VFD CONTROL SIGNAL(CLK)

I/O

I EXT DATA BUS WIDTH SELECT L=16bit (width) H=8bit (width)

I MODE SELECT SIGNAL

SINGLE CHIP MODE=Vss CONNECTION, MICRO PROSECER MODE=Vcc CONNECTION

1394 CONTROL SIGNAL(CS) / H=NEGATE , L=ASSERT

I/O

AUDIO STATUS SELECT SIGNAL1

I/O

I RESET INPUT/ H=NEGATE , L=ASSERT *RESET IC OUT = OPEN DRAIN

O X'TAL CONNECTION

I IMPRESS: 0V

I X'TAL CONNECTION

I IMPRESS: 2.4-3.6V

NON USABLE

I/O

BE CONTROL SIGNAL(CS) / H=NEGATE , L=ASSERT

I/O

WIRED REMOTE INPUT

I/O

REMOTE INPUT

I/O

NOT USED

I/O

TRAY CONTROL SIGNAL1

PICK UP LASER ON/OFF CONTROL OUTPUT H=DVD L=CD

I/O

TRAY CONTROL SIGNAL2

I/O

INTERRUPT INPUT FOR BE / H=NEGATE , L=ASSERT

I/O

+1.8V POWER CONTROL SIGNAL FOR DSP / H=ON , L=OFF

I/O

BE CONTROL SIGNAL(REQ) / H=ASSERT , L=NEGATE

I/O

BE CONTROL SIGNAL(CLK)

I/O

BE CONTROL SIGNAL(DI)

I/O

BE CONTROL SIGNAL(DO)

I/O I/O

TXD

RXD

I/O

CLOCK MODE SELECT

I/O

RESET OUTPUT FOR 1394 / H=NEGATE , L=ASSERT

I/O

1394 CONTROL SIGNAL(DO)

I/O

1394 CONTROL SIGNAL(DI)

1394 CONTROL SIGNAL(CLK)

I/O

AUDIO STATUS SELECT SIGNAL2

AUDIO STATUS SELECT SIGNAL3

I/O

AUDIO STATUS SELECT SIGNAL4

I/O

INTERNAL FLASH CONTROL SIGNAL1 / H=NOMAL , L=BOOT

I/O

AUDIO STATUS SELECT SIGNAL5

I/O

AUDIO STATUS SELECT SIGNAL6

I/O

VIDEO STATUS SELECT SIGNAL

I/O I/O

MUTE CONTROL SIGNAL / H=MUTE ON , L=MUTE OFF

INTERNAL FLASH CONTROL SIGNAL1 / H=BOOT , L=NOMAL

I/O

DIR CONTROL SIGNAL(CLK)

I/O

DIR CONTROL SIGNAL(DI)

I/O

DIR CONTROL SIGNAL(DO)

I/O

DIR CONTROL SIGNAL(CS)

I/O

ERROR DETECT SIGNAL

I/O

CH STATUS DETECT SIGNAL

I/O

DVD-3910

64

DVD-3910

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

P41 EXT_INT

P40 SW_HGAIN

P37 BUSYEPROM

P36 VPP

P35 DSP_RST

P34 ROMRST

P33 DSPOSCON

P32 FLUG 0A

P31 FLUG 1A

VCC POWER INPUT 3

P30 FLUG 2A

VSS

P27

P26 +3.3V_ON/OFF

P25 232CONT1

P24

P23 HD_2ch/Mch

P22

P21 LED1

P20 LED2

P17 P_DED2

P16 ROM_CONT2

INT3 INTERRUPT

P14 LED3

P13

P12 G_LED

P11 HD_HOKEN1

P10

P07 PLL_RST

P06 PDET

P05 RST

P04 BE_ON

P03 1394_ON/OFF

P02 1394_YOBI

P01 CL_SW

P00 OP_SW

P107 R_LED

P106 ON/ST

AN5 JOG1

AN4 JOG2

AN3 REG

AN2 KEY2

AN1 KEY1

AVSS ANA POWER

AN0 KEY0

VREF REFERENCE

AVCC ANA POWER

SIN4 DSPMISO

SOUT4 DSPMOSI

CLK4 DSPSPICLK

POWER INPUT 4

FLUG 3A

232CONT2

HD_ON/OFF

LED4

HD_HOKEN2

SPDIF OUTPUT CONTROL H=EXT IN, L=INT

I/O

SUB WOOFER HGAIN

I/O

DSP CONTROL (SPARE)

I/O

NORMAL: "H" FLASH WRITING FOR DSP: "L"

I/O

DSP RESET OUTPUT TERMINAL (RESET: "L")

I/O

MEMORY RESET FOR DSP (RESET: "L")

I/O

XTAL CONTROL PORT FOR DSP H=ON, L=OFF

I/O

E2ROM CHIP SELECT CONTROL FOR DSP

I/O

NOT USED

I IMPRESS: 2.4-3.6V

DSP CHECK FLAG (FLAG 2A) Normal="L"

I/O

IMPRESS: 0V

I/O

I/O Special Flag for ROM update (ADSP 21061L-A: FLAG 3A)

I/O

H=ON, L=OFF

I/O 232C/1394 COMMUNICATION PATHWAY SWITCHING OUTPUT 1

I/O

232C/1394 COMMUNICATION PATHWAY SWITCHING OUTPUT 2

I/O HDMI CONTROL 2ch (Low)/Mch (High)

I/O HDMI CONTROL ON (Low)/OFF (High)

I/O LED CONTROL (AL24)

I/O

LED CONTROL (D.L.)

POWER CHECK SPARE TERMINAL

I/O

NOT USED

I/O

IEEE 1394 INTERRUPT DETECTION PORT

I/O

LED CONTROL (DVD)

I/O

LED CONTROL (SACD)

POWER INDICATOR LED (Green) CONTROL L: ON/H: OFF

I/O

HDMI CONTROL

I/O

HDMI CONTROL

I/O

RESET OUTPUT FOR PLL_IC / H=NEGATE , L=ASSERT

I/O

POWER DETECT SIGNAL / H=ON , L=OFF

I/O

RESET OUTPUT FOR PERIPHERAL DEVICE / H=NEGATE , L=ASSERT

I/O

BE STATUS DETECT SIGNAL / H=ACTIVE , L=STANBY

I/O

+3.3V' POWER ON/OFF CONTROL SIGNAL FOR 1394 / H=ON , L=OFF

I/O

1394 SPARE TERMINAL

I/O

CLOSE_SW DETECT SIGNAL / H=NOT CLOSE , L=CLOSE

I/O

OPEN_SW DETECT SIGNAL / H=NOT OPEN , L=OPEN

I/O

POWER INDICATOR LED (Red) CONTROL L: ON/H: OFF

I/O

POWER ON/OFF CONTROL SIGNAL / H=POWER_ON , L=STANBY

I/O

JOG SELECT

I/O

JOG SELECT

REGION DETECT SIGNAL

I/O

KEY SCAN 2

I/O

KEY SCAN 1

I/O

I POWER INPUT TERMINAL FOR A-D CONVERTER Vss CONNECTION

KEY SCAN 0

I/O

I REFERENCE VOLTAGE INPUT TERMINAL FOR A-D CONVERTER

I

POWER INPUT TERMINAL FOR A-D CONVERTER Vcc CONNECTION

DSP CONTROL TERMINAL

I/O

DSP CONTROL TERMINAL

I/O

DSP CONTROL TERMINAL

I/O

65

W986432DH-6 (SY: IC717)

BLOCK DIAGRAM

Bank Select

Data Input Register

512K x 32

Sense AMP

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Address Register

Row Buffe r

Refresh Counter

Row Decoder Col. Buffer

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

CLK CKE CS

RAS CAS WE DQM

LWE

LDQM

DQi

CLK

ADD

LCAS LWCBR

512K x 32

Timing Register

PIN CONFIGURATION

VDD

1 2

DQ0

3

DDQ

V

4

DQ1

5

DQ2

6

V

SSQ

7

DQ3

8

DQ4

9

V

DDQ

10

DQ5

11

DQ6

12

V

SSQ

13

DQ7

14

N.C

15

V

DD

16

DQM0

17

WE

18

CAS

19

RAS

20

CS

21

N.C

22

BA0

23

BA1

24

A10/AP

25

A0

26

A1

27

A2

28

DQM2

29

V

DD

30

N.C

31

DQ16

32

V

SSQ

33

DQ17

34

DQ18

35

V

DDQ

36

DQ19

37

DQ20

38

V

SSQ

39

DQ21

40

DQ22

41

V

DDQ

42

DQ23

43

V

DD

DVD-3910

VSS

86

DQ15

85

SSQ

V

84

DQ14

83

DQ13

82

V

DDQ

81

DQ12

80

DQ11

79

V

SSQ

78

DQ10

77

DQ9

76

V

DDQ

75

DQ8

74

N.C

73

V

SS

72

DQM1

71

N.C

70

N.C

69

CLK

68

CKE

67

A9

66

A8

65

A7

64

A6

63

A5

62

A4

61

A3

60

DQM3

59

V

SS

58

N.C

57

DQ31

56

V

DDQ

55

DQ30

54

DQ29

53

V

SSQ

52

DQ28

51

DQ27

50

V

DDQ

49

DQ26

48

DQ25

47

V

SSQ

46

DQ24

45

V

SS

44

PIN FUNCTION DESCRIPTION

Pin Name Input Function

CLK System clock Active on the positive going edge to sample all inputs.

CS

Chip select

Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM.

Masks system clock to freeze operation from the next clock cycle.

CKE Clock enable

CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down mode.

0 ~ A10 Address

A

BA0,1 Bank select address

RAS

CAS

WE

Row address strobe

Column address strobe

Write enable

DQM0 ~ 3 Data input/output mask

DQ

0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins.

V

DD/VSS Power supply/ground Power and ground for the input buffers and the core logic.

DDQ/VSSQ Data output power/ground

V

NC No Connection This pin is recommended to be left No connection on the device.

Row/column addresses are multiplexed on the same pins. Row address : RA

Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.

0 ~ RA10, Column address : CA0 ~ CA7

Latches row addresses on the positive going edge of the CLK with RAS Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS Enables column access.

Enables write operation and row precharge. Latches data in starting from CAS

Makes data output Hi-Z, t

,WE active.

SHZ after the clock and masks the output.

Blocks data input when DQM active.

Isolated power supply and ground for the output buffers to provide improved noise immunity.

low.

66

ADV7310 (SY: IC701,710)

ADV7300 (MA: IC706)

ADV7310 Terminal Function

VDD_IO

VDD

DGND

GND_IO

CLKIN_BS9S8S7S6S5DGND

646362616059585756555453525150

1

Y0

2

Y1

3

Y2

4

Y3

5 6

Y4

7

Y5 Y6

8 9

Y7

10 11 12

Y8 Y9

13 14

C0

15

C1

16

C2

171819202122232425262728293031

C3

TOP VIEW

C4

SPI/I2C

ALSB_SO

SDA_CLKSP

SCLK_SI

P_HSYNC

VDDS4S3S2S1

C5C6C7C8C9

P_BLANK

P_VSYNC

S0

S_VSYNC

S_HSYNC

49

32

CLKIN_A

RTC_SCR_TR

48

S_BLANK

47

R

46

VREF COMP1

45 44

DAC A

43

DAC B

42

DAC C

41

VAA

40

AGND

39

DAC D DAC E

38 37

DAC F COMP2

36 35

R EXT_LF

34 33

RESET

DVD-3910

SET 1

SET 2

Pin No. Pin Name

FunctionI/O

1VDD_IO P Digital power supply. 2~9, 12, 13 Y9-0 I 10-Bit Progressive scan/ HDTV input port for Y data. 10, 56 VDD P Digital power supply. 11, 57 DGND G Digital Ground 14~18, 26~30 C9-0 I 10-Bit Progressive scan/ HDTV input port for CrCb color data in 4:2:2 input mode.

When this input pin is brought low, the ADV7300 interfaces over the SPI port and uses this

19 SPI/I2C I input as part of the 4 wire SPI interface. When this input pin is tied high [VDD_IO], the ADV7300

interfaces over the I2C port. 20 ALSB_SO I/O Multifunctional pin. 21 SDA_CLKSP I/O Multifunctional pin. 22 SCLK_SI I Multifunctional input.

23 P_HSYNC I

24 P_VSYNC I

Video Horizontal Sync Control Signal for HD sync in simultaneous SD/HD mode

and HD only mode.

Video Vertical Sync Control Signal for HD sync in simultaneous SD/HD mode

and HD only mode. 25 P_BLANK I Video Blanking Control Signal for HD sync in simultaneous SD/HD mode and HD only mode. 31 RTC_SCR_TR I Multifunctional input. 32 CLKIN_A I Pixel Clock Input for HD only or SD only modes.

33 RESET I

This input resets the on-chip timing generator and sets the ADV7300 into Default Register

setting. Reset is an active low signal. 34 EXT_LF I External Loop filter for the internal PLL.

35, 47 R

SET1,2 I

A1520 Ohms resistor must be connected from this pin to AGND and is used to control the

amplitudes of the DAC outputs. 36,45 COMP O Compensation Pin for DACs.

37 DAC F O

38 DAC E O

39 DAC D O

In SD only mode: Chroma/RED/V analog output.

In HD only mode and simultaneus HD/SD: Pb/ BLUE (HD) analog output.

In SD only mode: Luma/BLUE/U analog output.

In HD only mode and simultaneus HD/SD: Pr/ RED (HD) analog output.

In SD only mode: CVBS/GREEN/Y analog output.

In HD only mode and simultaneus HD/SD:Y/ GREEN (HD) analog output. 40 AGND G Analog Ground 41 VAA P Analog power supply. 42 DAC C O Chroma/ RED/ V SD analog output. 43 DAC B O Luma/ BLUE/ U SD analog output. 44 DAC A O CVBS/ GREEN/ Y SD analog output. 46 VREF I/O Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235V). 48 S_BLANK I/O Video Blanking Control Signal for SD. 49 S_VSYNC I/O Video Vertical Sync Control Signal for SD. 50 S_HSYNC I/O Video Horizontal Control Signal for SD.

51~55, 58~62 S9-S0 I

10-Bit Standard Definition input port. Or Progressive Scan/ HDTV input port for

Cr [Red/V] color data in 4:4:4 input mode. 63 CLKIN_B I Pixel Clock Input. 64 GND_IO G Digital Ground

67

SiI 170B (SY: IC721)

Pin Diagram

RESERVED

PGND2

VCC

GND

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

DVD-3910

PGND1

PVCC1

EXT_SWING

AGND

TXC -

TXC +

AVCC

TX0-

TX0+

AGND

TX1-

TX1+

AVCC

TX2-

TX2+

AG N D

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SiI 170B

64-Pin LQFP

(Top View)

49

50

51

54

52

53

55

56

58

57

59

60

62

61

63

64

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

SCLS

SDAS

ISEL/RST#

VCC

MSEN

PD#

HTPLG

NC

CTL3

VSYNC

HSYNC

VREF

DE

VCC

D5

D4

D3

D2

D1

D9

D8

D7

D11

PVCC2

D10

D6

IDCK-

IDCK+

D0

GND

Pin Diagram

68

Pin Descriptions

Input Pins

Pin Name Pin # Type Description

D23-D12 See Pin

Diagram

In Upper 12 bits of 24-bit pixel bus. Mode controlled by configuration register bit:

When BSEL = HIGH, this bus inputs the top half of the 24-bit pixel bus. When BSEL = LOW, these bits are not used to input pixel data.

DVD-3910

D11–D0 See Pin

Diagram

IDCK+ 57 In Input Data Clock +. This clock is used for all input modes.

IDCK- 56 In Input Data Clock –. This clock is only used in 12-bit mode when dual edge

DE 2 In Data enable. This signal is high when input pixel data is valid to the transmitter

HSYNC 4 In Horizontal Sync input control signal.

VSYNC 5 In Vertical Sync input control signal.

In Bottom half of 24-bit pixel bus / 12-bit pixel bus input. Mode controlled by

configuration register bit: When BSEL = HIGH, this bus inputs the bottom half of the 24-bit pixel bus. When BSEL = LOW, this bus inputs ½ a pixel (12-bits) at every latch edge (both

falling and/or rising) of the clock.

clocking is turned off (DSEL = LOW). It is used to provide the ODD latching edges for multi-phased clocking. If (BSEL = HIGH) or (DSEL = HIGH) this pin is unused and should be tied to GND.

and low otherwise.

Input Voltage Reference Pin

Pin Name Pin # Type Description

VREF 3 AnalogInMust be tied to 3.3V.

Power Management Pin

Pin Name Pin # Type Description

PD# 10 In Power Down (active LOW). A HIGH level (3.3V) indicates normal operation and a

LOW level (GND) indicates power down mode.

69

Differential Signal Data Pins

Pin Name Pin # Type Description

TX0+

TX0-

TX1+

TX1-

TX2+

TX2-

TXC+

TXC-

EXT_SWING 19 Analog Voltage Swing Adjust. A resistor should tie this pin to AVCC. This resistor

25 24 28 27 31 30

22 21

Analog Analog Analog Analog Analog Analog

Analog Analog

TMDS Low Voltage Differential Signal output data pairs. These pins are tri-stated when PD# is asserted.

TMDS Low Voltage Differential Signal output clock pairs. These pins are tri-stated when PD# is asserted.

determines the amplitude of the voltage swing. A 510 ohm resistor is recommended for remote display applications. For notebook computers, 680 ohm is recommended.

Configuration/Programming Pins

Pin Name Pin # Type Description

MSEN 11 Out Monitor Sense. This pin is an open collector output. The output is programmable

through the I resistor is required on this pin.

RESERVED 34 In This pin is reserved.

2

C interface (see I2C register definitions). An external 5K pull-up

DVD-3910

NC 7,8 NC These pins are not electrically connected inside the package.

Control Pins

These control pins allow configuration of the transmitter through the slave I2C port, which is required by HDCP.

Pin Name Pin # Type Description

ISEL/RST# 13 In I2C Interface Select. If HIGH, then the I2C interface is active.

SCLS 15 In DDC I2C Clock.

SDAS 14 In/Out DDC I2C Data.

CTL3 6 In External CTL3.

HTPLG 9 In Monitor Charge Input. This pin is used to connect to the DVI Hot Plug pin to detect

the presence of an attached monitor.

Power and Ground Pins

Pin Name Pin # Type Description

VCC 1,12,33 Power Digital VCC. Connect to 3.3V supply.

GND 16,35,64 Ground Digital GND.

AVCC 23,29 Power Analog VCC. Connect to 3.3V supply.

AGND 20,26,32 Ground Analog GND.

PVCC1 18 Power Primary PLL Analog VCC. Connect to regulated 3.3V supply.

PVCC2 49 Power Filter PLL Analog VCC. Connect to regulated 3.3V supply.

PGND1 17 Ground PLL Analog GND.

PGND2 48 Ground PLL Analog GND.

70

TSB41AB2 (IE: IC111))

AGND AGND

AV

DD

AV

DD

RESET FILTER0 FILTER1

PLLV

DD

PLLGND PLLGND

XI

XO

DV

DD

DV

DD

DGND DGND

TPA1+

AGND

TPBIAS1

47 46 45 44 4348 42

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

12 3

TPA1–

TPB1+

5678

4

PAP PACKAGE

(TOP VIEW)

DD

TPB1–AVR1

R0

40 39 3841

TSB41AB2

910111213

TPBIAS0

AGND

37 36

TPA0+

TPA0–

TPB0+

35 34 33

14 15 16

TPB0–

AGND

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

AGND AV

DD

AV

DD

SM SE TESTM DV

DD

DV

DD

CPS ISO PC2 PC1 PC0 C/LKON DGND DGND

DVD-3910

block diagram

CPS

LPS

ISO

CNA

SYSCLK

LREQ

CTL0 CTL1

PC0 PC1 PC2

C/LKON

D0 D1 D2 D3 D4 D5 D6 D7

Link

Interface

I/O

LREQ

SYSCLK

CNA

CTL0

CTL1

D0D1D2

D3

D4D5D6

Received Data

Decoder/Retimer

Arbitration

and Control

State Machine

Logic

D7

PD

LPS

NC

TPA0+

TPA0–

Cable Port 0

TPB0+

TPB0–

TPA1+

TPA1–

Cable Port 1

TPB1+

TPB1–

R0 R1

TPBIAS0 TPBIAS1

PD

RESET

Bias Voltage

and

Current

Generator

Transmit Data

Encoder

71

Crystal

Oscillator,

PLL System,

and Clock Generator

XI XO

FILTER0 FILTER1

CXD1881AR (MA: IC502)

SDEN

S D ATA

SCLK

V33

LCP

LCN

MNTRCEFE

TE

DVD-3910

PI

V25

V125

TPH

DFT

LINK

33343536373839404142434445464748

RX

MEV

VNA

FNN

FNP

DIP

DIN

BYP

RFAC

VPA

AIP

AIN

ATO N

ATO P

RFSIN

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

CXD1881AR

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

MEVO

MIN

MLPF

MB

MP

MIRR

LDON

VNB

CDPD

DVDPD

COLD

DVDLD

VC

VPB

CD_E

RFDC

64

1 2 3 4 5 6 7 8 9

A2

B2

C2

DVDRFP

DVDRFN

D2

CP

CN

CD_F

17

10

11 12 13 14 15 16

B

D

C

A

CD_B

CD_D

CD_C

CD_A

72

DVDRFP

DVDRFN

RFSIN

CD_A

CD_B

CD_C

CD_D

CD_E

CD_F

DVDPD

CDPD

DVD-3910

ATO P

ATO N

AIN

62 61 60 59

1

MUX

2

63

SIGR b3 INPUT SEL

A

12

16

B

11

15

MUX

C

10

14

D

9

13

PDCR b3

CD/DVD

6dB is added @ high gain mode

18

17

RFCR b2-0

12dB is added @ high gain mode

(CDR b5=1)

A2

3

B2

4

C2

5

D2

6

RFCR b2-0

CDR b4 LD H/L

2

RFCR b7-6 INPUT IMP SEL

A

B

C

D

(CDR b5=1)

GCA

3

GCA

3

TRCR2 b6-4

DPD EQ

CCR b5 APC SEL DVD/CD

ATT

GCA

SUM

EQ

3

SIGR b7-4 ATT

4D

W/LPF

SIGR b2-0

12dB is added

@ high gain mode

4

(CDR b5=1)

3

SIGR b2-0 12dB is added @ high gain mode

(CDR b5=1)

+/-4dB

TRCR2 b3-0

Comp.

VC

TRCR b6 DPD COMP HYS ON

AGCO

GCA

4

3B

Btm Env

INPUT

BIAS

RFCR b5-4 INPUT IMP SEL

CAR b1-0 Env/Clamp

B+D

SUM Amp.

A+C

A+D

B+C

PHASE

DETECTOR

PHASE

DETECTOR

2

SSOUT

2

RESUM

FCCR b7-0 FBCR b6-0

AGC

Clamp &Env

TENV

TOPHLD

+3dB

CDR b5

High Gain

CTCR b5-4 MEVO SEL

CAR b3-2 SIGDET

GCA +/-4dB

MRCR b7-0

2

AIP

23

24

Dual APC

AGC BTM ENV

BENV

MUX

32

50

21

22

26

DVDLD

MEV

MEVO

LDON

CDLD

MUX

Pll

Btm clamp

& clip

31

MIN

FNP

53 52

PROGRAMMABLE

EQUALIZER

FILTER

DIFFERENTIATOR

AGCO

2

Level DAC

4

FOCR b7-4

FS Gain

70kHz

LPF

CER b4-0 CE offset

CFR b2-0

CE-ATT

CFR b3 CEPOL

PDCR b3

CD/DVD

MRCR b6-4

control

Mirr Comp

ATT L e v e l

droop rate

TOP HLD

TOP ENV

BTM HLD

BTM ENV

FNN

Offset

cancel

Offset

cancel

4

3

MUX

29MP28

PIOR b4-0

5

BCA DET

CTCR b3-0

TRCR2 b7

CHR b7-6

Mirr Defect

Comp ATT

ATT

Vref

MB

FULL WAVE RECTIFIER

PI offset

CTCR b7

CO Gain

LPF ATT Pol sel. buff (Ð12dB)

CP/CN

Low lmp

CONTROL Signals

2

To each block

DIN

DIP

55 54 57

OUTPUT INHIBIT

CCR b4-0

FE offset

70kHz +/-6dB, 4bit

LPF GCA

TOPHLD

CBR b3-2

Buff

CGR b0 OUTPUT INHIBIT

CGR b1

5

Offset

cancel

2

RFAC

AGC

CHARGE

PUMP

FOCR b3-0

FO Gain

DAC

AGC HOLD RFCR b3

4

COMP

4

GCA

0-+8dB, 4bit

FE TE CE

V25

V125

V25/3

PIOR b7-5

SUBMUX

LPF GCA

Offset cancel

6

CEFDB

TRCR b5-0

TR offset

for PI output ref.

V25/3

V25/2

VCI for servo input

VC

SERIAL PORT REGISTER

MUX

Offset

30

MLPF

GCA

CGR b5-4 Gain

CDR b7 LINKEN

MUXMUX

27

LINK

V33 for output buff

58

VPA

MIRR

HOLDEN CDR b6

Pll

SEL

2

CBR b1-0

SEL

2

CAR b7-4

TE MASK SEL

PI

MON SEL

3

TE

RST

3

CFR b7-5 TR Gain

for TE, FE & CE output ref.

CDR b2

CDR b3

CCR b7 DISK DET

19

2533

VPB

VNA51VNB

56

BYP

49

RX

40

FE

38

PI

35

TPH

34

DFT

61

RFDC

41

CE

42

MNTR

44

LCP

43

LCN

7

CP

8

CN

39

TE

36

V125

37

V25

20

VC

48

SDEN

47

SD ATA

46

SCLK

45

V33

73

Terminal Function

Power Supply Pins

Name I/O Function

VPA - Power for RF and serial port

VPB - Power for servo

VNA - GND for RF and serial port

VNB - GND for servo

V33 - Power for output buffer

V25 - Reference Power for servo output

Input Pins

Name I/O Function

DVDRFP,DVDRFN I RF signal input

RFSIN I RF signal input

AIP,AIN I AGC amp. input

DIP,DIN I Analog input for RF single buffer

A,B,C,D I Photo detector interface input

A2,B2,C2,D2 I Photo detector interface input

CD_A,B,C,D I CD photo detector interface input

CD_E,F I CD photo detector interface input

MIN I RF signal input for mirror

DVDPD I APC input

CDPD I APC input

LDON I APC input ON/OFF (L:Open)

LINK

I Link signal input (L:Open)

O Mirror monitor output

DVD-3910

Output Pins

Name I/O Function

ATOP,ATON O Differential attenuator output

FNP,FNN O Differential normal output

RFAC O Single end normal output

RFDC O RF signal output

FE O Focus error signal output

TE O Tracking error signal output

CE O Center error signal output

MEVO O RFDDC bottom envelope output

DFT O Defect output

MIRR O Mirror detected output

PI O Pull-in signal output

DVDLD O APC output

CDLD O APC output

MNTR O Monitor output

74

Analog Pins

Name I/O Function

BYP - RF AGC integration capacitor connecting terminal

CP - Differential phase tracking LPF terminal

CN - Differential phase tracking LPF terminal

LCP - Lens shift offset cancel LPF terminal

LCN - Lens shift offset cancel LPF terminal

MP - MIRR top hold terminal

MB - MIRR bottom hold terminal

MEV - RFDC bottom envelope terminal

MLPF - Mirror LPF terminal

TPH - PI top hold terminal

VC - Reference voltage output

V125 - Reference voltage output

RX - Reference resistor input

DVD-3910

Serial Port Pins

Name I/O Function

SDEN I Serial data enable

SDATA I/O Serial data

SCLK I Serial clock

75

K4S641632 (MA: IC114)

W986416DH (MA: IC103)

DVD-3910

V

DQ0

VCCQ

DQ1

DQ2

SS

V

DQ3

DQ4

CC

V

DQ5

DQ6

V

SS

DQ7

V

LDQM

WE

CAS

RAS

CS

BS0

BS1

A10/AP

A0

A1

A2

A3

Vcc

1

CC

2

3

4

5

6

Q

7

8

Q

9

10

11

Q

12

13

14

CC

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

V

SS

DQ15 VssQ

DQ14

DQ13

CC

Q

V

DQ12

DQ11

SS

Q

V

DQ10

DQ9

Q

V

CC

DQ8

SS

V

NC

UDQM

CLK

CKE

NC

A11

A9

A8

A7

A6

A5

A4

Vss

Terminal Function

Pin No. Pin Name

1, 14, 27 VCC Power (+3.3V) Power for input buffers and logic circuit inside DRAM. 2, 4, 5, 7, 8, 10,

11, 13, 42, 44, 45, 47, 48, 50,

DQ0-DQ15 Data Input/Output Multiplexed pins for data output and input.

51, 53 3, 9, 43, 49 VCCQ Power (+3.3V) for I/O buffer Separated power from VCC, to improve DQ noise immunity. 6, 12, 46, 52 VSSQ Ground for I/O buffer Separated ground from VSS, to improve DQ noise immunity. 16 WE Write Enable Referred to RAS. 17 CAS Column Address Strobe Referred to RAS.

18 RAS Row Address Strobe

19 CS Chip Select

20, 21 BS0, BS1 Bank Select

23~26, 22 29~35

A0-A11 Address Column address: A0-A7. A10 is sampled during a precharge command to

Command input. When sampled at the rising edge of the clock RAS, CAS and WE define the operation to be executed.

Disable or enable the command decoder.When command decoder is disabled, new command is ignored and previous operation continues.

Select bank to activate during row address latch time, or bank to read/write during address latch time.

Multiplexed pins for row and column address. Row address: A0-A11.

determine if all banks are to be precharged or bank selected by BS0, BS1. 28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM. 36, 40 NC No Connection No Connection

37 CKE Clock Enable

CKE controls the clock activation and deactivation. When CKE is low,

Power Down mode, Suspend mode, or Self Refresh mode is entered. 38 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock.

The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled 39, 15 UDQM, LDQM Input/Output mask high in read cycle. In write cycle, sampling DQM high will block the write

operation with zero latency.

DescriptionFunction

76

16M SDRAM (MA: IC402)

16M SDRAM (TSOP)-8 (DM: IC103, 104)

K4S161622D-TC80 W981616AH-8

15

SS

V

50

SSQ

V

DQ14DQ

DQ13DQ

46

47

48

49

DVD-3910

12

45

10DQ11

DDQ

V

DQ

43

44

4241403938373635343332313029282726

SSQ

V

8

DQ9DQ

DDQ

V

UDQM

N.C/RFU

CLK

CKE

N.C

9

A

A8A7A6A5A

SS

4

V

123456789

1

2

SSQ

V

DQ

3

DQ

DDQ

V

4

DQ

0

DD

DQ

V

DQ

1011121314151617181920

6

5

DQ

SSQ

V

DQ7DQ

DDQ

V

WE

LDQM

CAS

RAS

CS

BA

/AP

10

A

21

A0A

23

25

24

22

1

2

3

A

DD

V

Terminal Function

Pin Name FunctionPin No. Symbol

1VDD Power Supply/Ground Power and ground for the input buffer and the core logic 2DQ0 Data Input/Output Data input/output are mutiplexed on the same pin 3DQ1 Data Input/Output Data input/output are mutiplexed on the same pin 4VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffer 5DQ2 Data Input/Output Data input/output are mutiplexed on the same pin 6DQ3 Data Input/Output Data input/output are mutiplexed on the same pin 7VDDQ Data Output Power/Ground Isolated power supply and ground for the output buffer 8DQ4 Data Input/Output Data input/output are mutiplexed on the same pin

9DQ5 Data Input/Output Data input/output are mutiplexed on the same pin 10 VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffer 11 DQ6 Data Input/Output Data input/output are multiplexed on the same pin 12 DQ7 Data Input/Output Data input/output are multiplexed on the same pin 13 VDDQ Data Output Power/Ground Isolated power supply and ground for the output buffer 14 L DQM Data Input/Output Mask Blocks data input when active 15 WE Write Enable Enables write operation and row precharge 16 CAS Column Address Strobe Latches column address on the positive going edge of the CLK at low 17 RAS Row Address Strobe Latches row address on the positive going edge of the CLK at low

18 CS Chip Select

19 BA Bank Select Address Selects bank to be activated during row address latch time 20 A10/AP Address Row/column addresses are multiplexed on the same pin 21 A0 Address Row/column addresses are multiplexed on the same pin 22 A1 Address Row/column addresses are multiplexed on the same pin 23 A2 Address Row/column addresses are multiplexed on the same pin 24 A3 Address Row/column addresses are multiplexed on the same pin 25 VDD Power Supply/Ground Power and ground for the input buffer and the core logic 26 VSS Power Supply/Ground Power and ground for the input buffer and the core logic 27 A4 Address Row/column addresses are multiplexed on the same pin 28 A5 Address Row/column addresses are multiplexed on the same pin 29 A6 Address Row/column addresses are multiplexed on the same pin 30 A7 Address Row/column addresses are multiplexed on the same pin 31 A8 Address Row/column addresses are multiplexed on the same pin 32 A9 Address Row/column addresses are multiplexed on the same pin 33 N. C No Connection No connect pin 34 CKE Clock Enable Masks system clock to freeze operation from the next clock cycle 35 CLK System Clock Active on the positive going edge to sample all inputs 36 U DQM Data Input/Output Mask Blocks data input when active 37 N. C/RFU NC/Reserved No connect pin 38 VDDQ Data Output Power/Ground Isolated power supply and ground for the output buffer 39 DQ8 Data Input/Output Data input/output are multiplexed on the same pin 40 DQ9 Data Input/Output Data input/output are multiplexed on the same pin 41 VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffer 42 DQ10 Data Input/Output Data input/output are multiplexed on the same pin 43 DQ11 Data Input/Output Data input/output are multiplexed on the same pin 44 VDDQ Data Output Power/Ground Isolated power supply and ground for the output buffer 45 DQ12 Data Input/Output Data input/output are multiplexed on the same pin 46 DQ13 Data Input/Output Data input/output are multiplexed on the same pin 47 VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffer 48 DQ14 Data Input/Output Data input/output are multiplexed on the same pin 49 DQ15 Data Input/Output Data input/output are multiplexed on the same pin 50 VSS Power Supply/Ground Power and ground for the input buffer and the core logic

Disables or enables device operation by masking or enabling all inputs except CLK, CKE, and LDQM

77

FAN8042 (MA: IC503)

Pin Assignments

DVD-3910

IN1+

IN1-

OUT1

IN2+

IN2-

GND

OUT2

IN3+

IN3-

VREF

OPIN1-

OPIN1+

48 47 46 45 44 43 42 41 40 39 38 37

1

2

3

4

5

6

7

8

9

10

SVCC

OPOUT1

GND

FAN8042

OPIN2+

OPIN2-

PS

OPOUT2

PVCC1

36

35

34

33

32

31

30

29

28

27

DO1+

DO1-

DO2+

DO2-

DO3+

GND

DO3-

DO4+

DO4-

OUT3

IN4+

11

12

13 14 15 16 17 18 19 20 21 22 23 24

IN4-

OUT4

CTL

FWD

REV

GND

SGND

MUTE123

MUTE4

TSD-M

26

25

PVCC2

DO5+

DO5-

78

Block Diagram

DVD-3910

IN1+

IN1-

OUT1

IN2+

IN2-

GND

OUT2

IN3+

10K

10

K

OPOUT2

40K

40K 40K

40K

PS PVCC1

3738394041434445464748

POWER

SAVE

36

35

34

33

32

31

DO1+

DO1-

DO2+

DO2-

DO3+

GND

OPIN1+

OPIN1-

OPOUT1

SVCC

VREF OPIN2-

GND GND

OPIN2+

42

1

2

3

10K

10K 10K

4

10K

40K

40K 40K

40K

5

6

10K

10K 10K

40K

40K 40K

10K

40K

7

30

GND

40K

8

9

10K

10K 10K

40K 40K

29

28

DO3-

DO4+

10

IN3-

OUT3

11

12

IN4+

OUT4IN4-

Note.

Detail ed circuit of the output power amp

From input opamp

Vref

10K

40K

M

C

W

+S

S

-

MUTE123

19

CTL FWD REV GND TSD-M PVCC2

GND SGND MUTE4

D

MUTE4 TSD-M

2423222120181716151413

MUTE123

40 K

10 K

DO+

DO-

10K

Pref

10K

+

40 K

+

10K

40K

Pref1 is almost PVCC1 / 2 Pref2 is almost PVCC2 / 2

27

26

25

DO4-

DO5+

DO5-

79

Pin Definitions

Pin Number Pin Name I/O Pin Function Descrition

1 IN1+ I CH1 op-amp input (+)

2 IN1- I CH1 op-amp input (-)

3 OUT1 O CH1 op-amp output

4 IN2+ I CH2 op-amp input (+)

5 IN2- I CH2 op-amp input (-)

6 GND - Ground

7 GND - Ground

8 OUT2 O CH2 op-amp output

9 IN3+ I CH3 op-amp input (+)

10 IN3- I CH3 op-amp input (-)

11 OUT3 O CH3 op-amp output

12 IN4+ I CH4 op-amp input (+)

13 IN4- I CH4 op-amp input (-)

14 OUT4 O CH4 op-amp output

15 CTL I CH5 motor speed control

16 FWD I CH5 forward input

17 REV I CH5 reverse input

18 GND - Ground

19 GND - Ground

20 SGND - Signal Ground

21 MUTE123 I Mute for CH1,2,3

22 MUTE4 I Mute for CH4

23 TSD-M O TSD monitor

24 PVCC2 - Power supply voltage 2 (For CH4,CH5)

25 DO5- O CH5 drive output (-)

26 DO5+ O CH5 drive output (+)

27 DO4- O CH4 drive output (-)

28 DO4+ O CH4 drive output (+)

29 DO3- O CH3 drive output (-)

30 GND - Ground

31 GND - Ground

32 DO3+ O CH3 drive output (+)

33 DO2- O CH2 drive output (-)

34 DO2+ O CH2 drive output (+)

35 DO1- O CH1 drive output (-)

36 DO1+ O CH1 drive output (+)

37 PVCC1 - Power supply voltage 1 (FOR CH1 CH2,CH3)

38 PS I Power save

39 OPOUT2 O Normal op-amp2 output

40 OPIN2- I Normal op-amp2 input (-)

41 OPIN2+ I Normal op-amp2 input (+)

42 GND - Ground

43 GND - Ground

44 VREF I Bias voltage input

45 SVCC - Signal & OPAMPs supply voltage

46 OPOUT1 O Normal op-amp1 output

47 OPIN1- I Normal op-amp1 input (-)

48 OPIN1+ I Normal op-amp1 input (+)

DVD-3910

80

M29W160EB70N6 (MA: IC104 IE: IC401)

DVD-3910

A15 A14 A13 A12 A11

1

48

A16 BYTE V

SS

DQ15A–1 DQ7

A10 DQ14

37 36

DQ6 DQ13 DQ5 DQ12 DQ4 V

CC

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

SS

E A0

A9 A8

A19

NC

W RP NC NC RB

A18 A17

A7 A6 A5 A4 A3 A2 A1

12

M29W160ET M29W160EB

13

24 25

AI06850

A0-A19 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

E

G

W

RP

RB

BYTE

V

CC

V

SS

NC Not Connected Internally

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply Voltage

Ground

LH28F160BJE-BTL90 (SY: IC210)

A0-A19 Address Inputs DQ0-DQ15 Data Inputs/Outpus DE# Chip Enable RP# Reset OE# Output Enable WE# Write Enable WP# Wraite Protect BYTE# Byte Enable BY/BY# Ready/Busy

CCW

V

CC

V GND Ground NC Not Connected

Block Erase, Full chip Erase, Word/Byte Write & Lock Bit set up Voltage Supply Vootage

81

LC89057W (SY: IC213)

DVD-3910

RXOUT

RX0 RX1 RX2 RX3

RX4 RX5/VI RX6/UI

LPF

TMCK/PIO0

TBCK/PIO1

TLRCK/PIO2

TDATA/PIO3

TXO/PIOEN

1

2 3 4 5 8 9

10

13

44 45 46 47

48

EMPHA/UO33AUDIO/VO35INT40CL39CE38DI

32

Clock

Selector

27

Microcontroller

Input

Selector

Modulation

or

Parallel Port

XIN

29

C bit, U bit

Demodulation

&

Lock Detect

PLL

28

XOUT

XMCK34CKST

I/F

Data

Selector

I/N

XMODE 41

37

36

21

24

16 17 20 22 23

DO

RERR

RD ATA

SDIN

RMCK RBCK RLRCK SBCK SLRCK

36 RERR1RXOUT

35 INT2RX0

34 CKST3RX1

TOP VIEW

33 AUDIO/VO4RX2

32 EMPHA/UO5RX3

31 DGND6DGND

30 DVDD7DVDD

29 XIN8RX4

28 XOUT9RX5/VI

27 XMCK10RX6/UI

26 DVDD11DVDD

25 DGND12DGND

24 SDIN37DO 23 SLRCK38DI 22 SBCK39CE 21 RDATA40CL 20 RLRCK41XMODE 19 DVDD42DGND 18 DGND43DVDD 17 RBCK44TMCK/PIO0 16 RMCK45TBCK/PIO1 15 AGND46TLRCK/PIO2 14 AVDD47TDATA/PIO3 13 LPF48TXO/PIOEN

LC89057W Terminal Function

Pin No.

1 RXOUT O Input bi-phase select data output terminal

2 RX0 I TTL compatible digital data input terminal

3 RX1 I Coaxial compatible amp built-in digital data input terminal

4 RX2 I TTL compatible digital data input terminal

5 RX3 I TTL compatible digital data input terminal

6 DGND — Digital GND

7 DVDD — Digital power

8 RX4 I TTL compatible digital data input terminal

9 RX5/VI I TTL compatible digital data/Validity flag input terminal for modulation

10 RX6/UI I TTL compatible digital data/User data input terminal for modulation

11 DVDD — Digital power for PLL

12 DGND — Digital GND for PLL

13 LPF O PLL loop filter connecting terminal

14 AVDD — Analog power for PLL

15 AGND — Analog GND for PLL

16 RMCK O RMCK clock output terminal (256fs, 512fs, XIN, VCO)

17 RBCK O/I RBCK clock in/output terminal (64fs)

18 DGND — Digital GND

19 DVDD — Digital power

20 RLRCK O/I RLRCK clock in/output terminal (fs)

21 RDATA O Serial audio data output terminal

22 SBCK O SBCK clock output terminal (32fs, 64fs, 128fs)

23 SLRCK O SLRCK clock output terminal (fs/2, fs, 2fs)

24 SDIN I Serial audio data input terminal

25 DGND — Digital GND

26 DVDD — Digital power

27 XMCK O Osc. amp output terminal

Pin Name

I/O

Function

82

DVD-3910

Pin No.

28 XOUT O X’tal osc. connecting output terminal

29 XIN I X’tal osc. connection, external clock input terminal (24.576MHz or 12.288MHz)

30 DVDD — Digital power

31 DGND — Digital GND

32 EMPHA/UO I/O Emphasis information/U-data output/Chip address setting terminal

33 AUDIO/VO I/O Non-PCM detect/V-flag output/ Chip address setting terminal

34 CKST I/O Clock switch transition period output/Demodulation master or slave function switching terminal

35 INT I/O Interrupt output for ∝com (Interrupt factor selectable)/Modulation or general I/O switching terminal

36 RERR O PLL lock error, data error flag output

37 DO O ∝com I/F, read out data output terminal (3-state)

38 DI I ∝com I/F, write data input terminal

39 CE I ∝com I/F, chip enable input terminal

40 CL I ∝com I/F, clock input terminal

41 XMODE I System reset input terminal

42 DGND — Digital GND

43 DVDD — Digital power

44 TMCK/PIO0 I/O 256fs system clock input for modulation/General I/O in/output terminal

45 TBCK/PIO1 I/O 64fs bit clock input for modulation/General I/O in/output terminal

46 TLRCK/PIO2 I/O fs clock input for modulation/General I/O in/output terminal

47 TDATA/PIO3 I/O Serial audio data input for modulation/General I/O in/output terminal

48 TXO/PIOEN O/I Modulation data output/ General I/O enable input terminal

* For latch-up countermeasure, perform each power supply ON/OFF in the same timing.

Pin Name I/O

Function

83

SM5819A (MA: IC801)

Pin Assignment

BLOCK DIAGRAM

VDDL

DSBCK

DSIFL

DSIFR

DSICT

DSISW

DSISL

DSISR

DIRDSCK

SYNC

INIT

VSS

EXISLR

EXICSW

EXIFLR

VSS

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

123456789

VDDL

SEL1FS

SEL4FS

SELEXT

EXIBCK

EXILRCK

31

32

DSGAIN

XMTPCM

VDDH

30

VDDH

VSS

EXIMCK

28

29

TEST1

TEST2

MCK

TOUT2

26

27

101112

TEST3

TOUT1

VDDL

25

VSS

24

23

22

21

20

19

18

17

16

15

14

13

DVD-3910

VSS

POFLR

POCSW

POSLR

PLRCK

PBCK

VDDH

MCKOUT

VSS

FMTPCM

DIRPCK

VDDL

DSIFL

DSIFR

DSICT

DSISL

DSISR

DSISW

DSGAIN

SEL1FS

SEL4FS

XMTPCM

EXIFLR EXISLR

EXICSW

EXILRCK

EXIBCK

EXIMCK

SYNC

INIT

DIRDSCK

DSBCK

MCK

FIR FILTER

and

DOWN SAMPLING

UNIT

ROM

24bit 720word

(fs 240w) (2fs 240w) (4fs 240w)

GENERATOR

CONTROL

CLOCK

and

TIMING

PCM

MUTE

PCM

I/F

(Internal Clocks)

INT/EXT.

DATA

SELECT

INT/EXT.

CLOCK

SELECT

FMTPCM

POFLR

POSLR

POCSW

SELEXT

PLRCK

PBCK

MCKOUT

DIRPCK

TEST1 TEST2 TEST3

84

TEST

CONTROL

TOUT1

TOUT2

PIN DESCRIPTION

Input

No. Name I/O Property

1 VDDL −− 2.5V Core power supply

2 SEL1FS I PD 3.3V

3 SEL4FS I PD 3.3V

4 SELEXT I PD 3.3V

5 DSGAIN I PD 3.3V

6 XMTPCM I PD 3.3V

7 VDDH −− 3.3V I/O power supply

8 TEST1 I PD 3.3V Test input 1 (must be open or tie LOW for normal operation)

9 TEST2 I PD 3.3V Test input 2 (must be open or tie LOW for normal operation)

10 TEST3 I PD 3.3V Test input 3 (must be open or tie LOW for normal operation)

11 TOUT1 O −−Test output 1

12 VSS −− −Ground

13 VDDL −− 2.5V Core power supply

14 DIRPCK I PD 3.3V

15 FMTPCM I PD 3.3V

16 VSS −− −Ground

17 MCKOUT O 12mA − System clock output (selected by SELEXT)

18 VDDH −− 3.3V I/O power supply

19 PBCK I/O S, 6mA 3.3V PCM output BCK bit clock

20 PLRCK I/O S, 6mA 3.3V PCM output LRCK word clock

21 POSLR O 2mA − PCM data output: surround left/right-channel

22 POCSW O 2mA − PCM data output: center/subwoofer channel

23 POFLR O 2mA − PCM data output: front left/right-channel

24 VSS −− −Ground

25 VDDL −− 2.5V Core power supply

26 TOUT2 O −−Test output 2

27 MCK I − 3.3V Master clock input: 512fs (22.5792MHz, fs = 44.1kHz)

28 VSS −− −Ground

29 EXIMCK I − 3.3V External system clock input

30 VDDH −− 3.3V I/O power supply

31 EXIBCK I S 3.3V Exter nal PCM data BCK bit clock input

32 EXILRCK I S 3.3V External PCM data LRCK word clock input

33 EXISLR I − 3.3V External PCM data input: surround left/right-channel

34 EXICSW I − 3.3V External PCM data input: center/subwoofer channel

35 EXIFLR I − 3.3V External PCM data input: front left/right-channel

36 VSS −− −Ground

37 VDDL −− 2.5V Core power supply

38 DSBCK I/O S, 6mA 3.3V DSD data input bit clock. Controlled by DIRDSCK

1

voltage

PCM output rate select 1 L: 2fs/4fs, H: fs

PCM output rate select 2 L: 2fs, H: 4fs

fs/2fs/4fs output and external data output select L: fs/2fs/4fs data, H: external data (EXI**)

DSD signal gain setting L: 100% modulation = 0dB, H: 50% modulation = 0dB

PCM output mute control input L: Mute ON, H: Mute OFF

PCM output PBCK/PLRCK I/O select L: Output (master mode), H: Input (slave mode)

PCM output format select L: MSB-ﬁrst left-justiﬁed 32-bit, H: IIS 32-bit

Description

DVD-3910

85

Input

No. Name I/O Property

39 DSIFL I − 3.3V DSD data input: front left-channel

40 DSIFR I − 3.3V DSD data input: front right-channel

41 DSICT I − 3.3V DSD data input: center channel

42 DSISW I − 3.3V DSD data input: subwoofer channel

43 DSISL I − 3.3V DSD data input: surround left-channel

44 DSISR I − 3.3V DSD data input: surround right-channel

45 DIRDSCK I PD 3.3V

46 SYNC I S, PU 3.3V Forced synchronization input (active-HIGH edge)

47 INIT I S, PU 3.3V Initialization input: Active-LOW, Resync on “L” → “H”

48 VSS −− −Ground

1. S = Schmitt, PU = pull-up resistor, PD = pull-down resistor, mA = output current

1

voltage

DSBCK I/O select L: input (slave), H: output (master)

Description

DVD-3910

86

IC61LV25616 (IE: IC402)

DVD-3910

I/O0

I/O1

I/O2

I/O3

V

GND

I/O4

I/O5

I/O6

I/O7

WE

1

A0

2

A1

3

A2

4

A3

5

A4

6

CE

7

8

9

10

11

CC

12

13

14

15

16

17

18

A5

19

A6

20

A7

21

A8

A9

22

44

A17

43

A16 A15

42

41

OE

UB

40

39

LB

I/O15

38

I/O14

37

I/O13

36

I/O12

35

GND

34

V

CC

33

I/O11

32

I/O10

31

I/O9

30

I/O8

29

28

NC

A14

27

A13

26

A12

25

A11

24

A10

23

Pin Description

Pin NameSymbol

A0~A17 Address Inputs

I/O0-I/O15 Data Inputs/Outputs

Chip Enable Input

CE

OE

V

GND Ground

Output Enable Input

Write Enable Input

WE

LB Lower-byte Control (I/O0-I/O7)

UB Upper-byte Control (I/O8-I/O15)

No Connection

NC

Power

CC

Block Diagram

A0-A17

DECODER

256K × 16

MEMORY ARRAY

VCC

GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

CE

OE

WE

UB

LB

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

COLUMN I/O

87

M11L16161SA (MA: IC505)

㪊㪉㪛㪚㪛㪄㪪㪘㪈㪇

44 I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 NC

NC NC WE RAS NC NC A0 A1 A2 A3 Vcc

1Vcc 2 3 4 5 6 7 8 9 10 11

12 13 14 15 16 17 18 19 20 21 22

Vss

43

I/O15

42

I/O14

41

I/O13

40

I/O12

39

Vss

38

I/O11

37

I/O10

36

I/O9

35

I/O8

34

NC

33

NC

32

CASL

31

CASH

30

OE A9

29

A8

28

A7

27

A6

26

A5

25

A4

24

Vss

23

PIN DESCRIPTIONS

PIN NO.

〜

21,24

18

29

15

31

32

14

30

2~5,7~10,

〜

38,40

35 43

1,6,22

23,39,44

11,12,13,16,17,

33,34

PIN NAME TYPE DESCRIPTION

Address Input

A0~A9

Input

Row Address:A0~A9 Column Address:A0~A9

RAS

CASH

CASL

WE

OE

I/O0~I/O15

Vcc

Vss

NC

Input/Output

Row Address StrobeInput

Column Address Strobe/Upper Byte ControlInput

Column Address Strobe/Lower Byte ControlInput

Write EnableInput

Output EnableInput

Data Input/Output

Power,(5V or 3.3V)Supply

GroundGround

No Connect-

DVD-3910

AN8471SA (MA: IC501)

32

116

VDD

18 16 15 14 13 12 32 31

Hall

Hall Amp

Matrix

Direction

VCL

SW

OSC

VT

SRESET

FG2

H1H

H1L

H2H

H2L

H3H

H3L

VHB

ECR

BMS

START

20

FG

10

Logic Circuit

7

6

5

4

3

2

1

EC

8

9

30

11

Bias

BC4

Thermal

Divider

BC3

Booster

Protect

17

BC1

BC2

PWMOUT

Start/Stop

VPUMP

Pre-Driver

CSOUT

VLP

Pin No.

Pin Name Function

1 VHB Hall bias pin 2 H3L Hall element 3 input (-) 3 H3H Hall element 3 input (+) 4 H2L Hall element 2 input (-) 5 H2H Hall element 2 input (+) 6 H1L Hall element 1 input (-) 7 H1H Hall element 1 input (+)

VM1

8 EC Torque command input pin

9 ECR Torque command ref. input pin 10 FG1 FG signal lout put pin (0.C) 11 START Start/Stop switching pin 12 VPUMP Booster pin 13 BC1 Booster cap. connecting pin 1 14 BC2 Torque command input pin 2 15 BC3 Torque command input pin 3 16 BC4 Torque command input pin 4 17 GND GND pin 18 VDD Power pin 19 VM2 Motor power pin 2 20 FG2 3x FG signal output pin (0.C) 21 A31 Drive output 3 22 A32 Drive output 3 23 CS2 Current detect pin 2 24 A21 Drive output 2 25 A22 Drive output 2

3ø Bridge

VM2

19

A11

27

A12

28

A21

24

A22

25

A31

21

A32

22

CS2

23

CS1

26

26 CS1 Current detect pin 1 27 A11 Drive output 1 28 A12 Drive output 1

X5

GND

17

29 NC N.C. 30 BMS Brake mode switching pin 31 VM1 Motor power pin 1 32 VLP Pre-driver lower power

88

BH7862F (SY: IC708)

01CTRAP

02MUTE1 MUTE1

6dB

75ohm

TEST

32

31

DVD-3910

COUT

TEST

CIN

03

04GND

05YIN

06VCC

07GND

08PYIN

09GND

10PYTRAP

11VCC

12PbIN

13GND

14PrIN

15MUTE2

16PrTRAP

1.5-6M

20k

CLAMP

20k

MUTE2

BPF

LPF

12M LPF

LPF

6M

6dB

75ohm

30

29

28

27

22

21

20

19

18

17

MIXOUT

MIXFB

GND

YTRAP

GND26

YOUT25

YFB24

GND23

PYOUT

PYFB

GND

PbOUT

N.C.

PrOUT

BH7862F Terminal Function

Pin No.

Port

1 CTRAP 10 PYTRAP 16 PrTRAP

Pin for LC resonation

27 YTRAP 2 MUTE1 Mute control pin, L: C, MIX, Y simultaneous mute 3 CIN 12 PbIN Signal input pin, chroma signal & color-difference signal 14 PrIN 4, 7, 9, 13, 20, 23, 26, 28

GND GND pin 5 YIN Signal input pin, luminance signal 8 PYIN 6 11 Power supply for PY, Pb, Pr

VCC

Power supply for C, MIX, Y

15 MUTE2 Mute control pin, L: PY, Pb, Pr simultaneous mute 17 PrOUT 19 PbOUT

Signal output pin, color-difference signal

18 N.C.  21 PYFB 22 PYOUT 24 YFB 25 YOUT 29 MIXFB 30 MIXOUT

Signal output pin, luminance signal (progressive)

Signal output pin, luminance signal (interlace)

Signal output pin, Y/C MIX signal

31 TEST TEST pin 32 COUT Signal output pin, chroma signal

Description

89

PCM1796 (SY: IC221,222 AP: IC311,312)

(TOP VIEW)

DVD-3910

ZEROL

ZEROR

MSEL

LRCK

DATA

BCK SCK

DGND

V

DD

MS

MDI

MC

MDO

RST

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VCC2L AGND3L I

L−

OUT

I

L+

OUT

AGND2 V

1

CC

V

L

COM

V

R

COM

I

REF

AGND1 I

R−

OUT

I

R+

OUT

AGND3R V

2R

CC

Terminal Functions

TERMINAL

NAME PIN

AGND1 19 − Analog ground (internal bias)

AGND2 24 − Analog ground (internal bias)

AGND3L 27 − Analog ground (L-channel DACFF)

AGND3R 16 − Analog ground (R-channel DACFF)

BCK 6 I Bit clock input

DATA 5 I Serial audio data input

DGND 8 − Digital ground

I

L+ 25 O L-channel analog current output+

OUT

I

L– 26 O L-channel analog current output–

OUT

I

R+ 17 O R-channel analog current output+

OUT

I

R– 18 O R-channel analog current output–

OUT

I

REF

LRCK 4 I Left and right clock (fS) input

MC 12 I Mode control clock input

MDI 11 I Mode control data input

MDO 13 I/O Mode control readback data output

MS 10 I/O Mode control chip-select input

MSEL 3 I I2C/SPI select

RST 14 I Reset

SCK 7 I System clock input

VCC1 23 − Analog power supply, 5 V

VCC2L 28 − Analog power supply (L-channel DACFF), 5 V

VCC2R 15 − Analog power supply (R-channel DACFF), 5 V

V

L 22 − L-channel internal bias decoupling pin

COM

V

R 21 − R-channel internal bias decoupling pin

COM

V

DD

ZEROL 1 I/O Zero flag for L-channel

ZEROR 2 I/O Zero flag for R-channel

(1)

Schmitt-trigger input, 5-V tolerant

(2)

Schmitt-trigger input and output. 5-V tolerant input and CMOS output

(3)

Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS output.

20 − Output current reference bias pin

9 − Digital power supply, 3.3 V

I/O

DESCRIPTIONS

(1)

(3)

(2)

(1)

(2)

90

LRCK

BCK

DATA

RST

MDO

MDI

MC

MS

MSEL

Audio

Data Input

I/F

Function

Control

I/F

8

Oversampling

Digital

Filter

and

Function

Control

Advanced

Segment

DAC

Modulator

Current

Segment

DAC

Bias

and Vref

Current

Segment

DAC

I

OUT

I

OUT

V

COM

I

REF

V

COM

I

OUT

I

OUT

L−

L+

R−

R+

DVD-3910

V

L

OUT

L

R

I/V and Filter

V

OUT

R

ZEROL

ZEROR

Zero

Detect

SM8701BM (MA: IC106)

MLEN/R2

P/S

V

GND

XTO

GNDP

DD

V

MO

XTI

DD

1

2

DD

3

4

5

6

7

P

8

3

9

10

20

19

18

17

16

15

14

13

12

11

MCK/R1

MDT/R0

RSTN

SO3

DD

O

V

GNDO

SO2

SO4

SO1

MON

System

Clock

Power Supply

Manager

SCK

DGND

V

DD

AGND2

AGND1

AGND3L

SM8701BM Terminal Function

Pin No.

Pin Name Function

1 MLEN/R2 Ip

2 P/S Ip

3VDD  5V supply (Digital block) 4 GND  Ground (Digital block) 5 XTO O Reference signal crystal oscillator element connection

6 XTI I

7 GNDP  Ground (PLL block) 8VDDP  5V supply (PLL block)

9VDD3  3.3V supply (output buffer) 10 MO O 27 MHz fixed-frequency output 11 MON O 27 MHz fixed-frequency output (inverted) 12 SO1 O 33.8688 MHz fixed-frequency output 13 SO4 O 768fs output 14 SO2 O 256fs output 15 GNDO  Ground (output buffer) 16 VDDO  3.3V supply (output buffer) 17 SO3 O 384fs output 18 RSTN Ip2LOW-level reset input

19 MDT/R0 Ip

20 MCK/R1 Ip

Note: 1. Schmitt trigger input with pull-down resistor

2. Schmitt trigger input with pull-up resistor

I/O

Control signal input.

1

In serial mode: latch enable signal In parallel mode: sampling rate select signal

Mode select signal.

1

LOW: serial mode, HIGH: parallel mode

Reference signal crystal oscillator element connection or external clock input

Control signal input.

1

In serial mode: control data input signal In parallel mode: sampling frequency select signal

Control signal input.

1

In serial mode: clock signal In parallel mode: sampling frequency select signal

1

CC

V

AGND3R

2L

V

CC

2R

CC

V

I/V and Filter

91

CY2302 (IE: IC110,505 SY: IC205)

Pin Configuration

DVD-3910

FBIN

GND

FS0

1

IN

2

3

4

8

7

6

5

OUT2

VDD

OUT1

FS1

Configuration Options

FBIN FS0 FS1 OUT1 OUT2

OUT1 0 0 2 X REF REF

OUT1 1 0 4 X REF 2 X REF

OUT1 0 1 REF REF/2

OUT1 1 1 8 X REF 4 X REF

OUT2 0 0 4 X REF 2 X REF

OUT2 1 0 8 X REF 4 X REF

OUT2 0 1 2 X REF REF

OUT2 1 1 16 X REF 8 X REF

Block Diagram

FS0

FS1

IN

Reference

Input

Phase

Detector

VCO

FBIN

÷Q

External feedback connection to OUT1 or OUT2, not both

Charge

Pump

Loop Filter

Output

Buffer

÷2

Output

Buffer

OUT1

OUT2

92

BR24L32F-W (MA: IC116)

Block diagram

z

1

A0

32kbit EEPROM array

DVD-3910

V

CC

8

GND 4

Pin configuration

z

A1 2

A2 3

12bit

Address decoder

12bits

Control logic

High voltage generator

V

CC

Slave word

address register

STOPSTART

Vcc level detect

SCLA2SDA

WP

BR24L32F-W

8bit

Data

WP7

register

6SCL

ACK

SDA5

5678

Pin name

z

Pin name

V

CC

GND

A0, A1, A2

SCL

SDA

WP

∗ An open drain output requires a pull-up resistor.

I / O

−

IN

IN / OUT

IN

Power supply

Ground (0V)

Slave address set

Serial clock input

Slave and word address, serial data input, serial data output

Write protect input

1234

A0

A1

GND

Function

∗

93

TOP245Y (AP: IC901)

CONTROL (C)

EXTERNAL

CURRENT LIMIT (X)

LINE-SENSE (L)

FREQUENCY (F)

Z

C

SHUNT REGULATOR/

ERROR AMPLIFIER

I

FB

CURRENT

LIMIT

ADJUST

R

E

-

+

VBG+ V

V

BG

LINE

SENSE

Tab Internally

Connected to

V

C

5.8 V

V

I (LIMIT)

SOFT

START

ON/OFF

T

1 V

OV/UV

DC

MAX

SOURCE Pin

+

5.8 V

-

4.8 V

INTERNAL UV

COMPARATOR

STOP LOGIC

STOP

DC

MAX

HALF FREQ.

OSCILLATOR WITH JITTER

SOFT-

START

D

CLOCK

MAX

SAW

LIGHT LOAD FREQUENCY REDUCTION

SOFT START

÷ 8

SHUTDOWN/

AUTO-RESTART

HYSTERETIC

THERMAL

SHUTDOWN

-

+

PWM

COMPARATOR

DVD-3910

7 D

5 F 4 S

3 X 2 L

1 C

0

INTERNAL SUPPLY

1

-

+

CURRENT LIMIT

COMPARATOR

CONTROLLED

TURN-ON

GATE DRIVER

SRQ

LEADING

EDGE

BLANKING

DRAIN (D)

RN5VD15AA (IE: IC203)

BD4730G (SY: IC201, 235) RN5VD30AA (IE: IC206)

54

(mark side)

R

3

2

1

D

TOP

VIEW

123

VCC

Vref

GND

4

NC

D

C

5

Block Diagram

5

VOUT

µCOM RESET

DD

V

2

4

3

Vref

GND

V

DD

OUT

5

CD

SOURCE (S)

1

3

OUT

GND

94

TA76432FC (AP: IC902)

Block Diagram

LM1117MPX-1.8 (SY: IC101 IE: IC205)

Connection Diagrams

DVD-3910

95

●FLTUBE(15-BT-97GNK)

DVD-3910

96

PRINTED WIRING BOARD

GU-3618 MAIN PWB UNIT

DVD-3910

97

COMPONENT SIDE

DVD-3910

98

FOIL SIDE

GU-3517B IEEE1394 UNIT B

DVD-3910

99

COMPONENT SIDE

DVD-3910

100

FOIL SIDE

Denon DVD-3910 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

SAFETY PRECAUTIONS

WIRE ARRANGEMENT

DISASSEMBLY

Iop Measurement (Judging for Traverse Unit Replacement)

DIAGNOSTICS OF OPTICAL PICKUP AND REPLACING TRAVERSE UNIT

How to Replace Traverse Unit

SERVICE MODE

TROUBLE SHOOTING

ELECTRICAL ADJUSTMENT FOR VIDEO

BLOCK DIAGRAM