Dell Latitude E520 ,Latitude E5470 ,Latitude E5570 Schematics
A
Vinafix.com
COMPAL CONFIDENTIAL
B
C
D
E
1 1
MODEL NAME : ADM60
PCB NO : DAA000AD000
BOM P/N : 4319XY31L01/L02
Park City 12" UMA
Skylake U
2 2
@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
CXDP@ : XDP Component
3 3
CONN@ : Connector Component
2015-09-25
REV : 1.0 (A00)
X76@ : SATA REDRIVER OPTION
MB PCB
Part Number
DAA000AD000
4 4
COPYRIGHT 2015
ALL RIGHT RESERVED
REV: A00
PWB: 6N3K7
Description
PCB 1DK LA-C621P REV0 MB
Layout Dell logo
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-C621P
LA-C621P
LA-C621P
1 60Thursday, September 24, 2015
1 60Thursday, September 24, 2015
1 60Thursday, September 24, 2015
E
1.0
1.0
1.0
A
Vinafix.com
B
C
D
E
Reverse Type
Block Diagram
Memory BUS (DDR4)
2133MHz
1 1
EDP CONN
VGA CONN
P25
DOCKING
CONN
2 2
P38
P26
VGA Switch
P25
VGA
DP
DP
SYNATICS
VMM3320
DAI
LAN
SATA1
DOCK_USB2.0[5]
DOCK_USB2.0[6]
DOCK_USB3.0[5]
SD4.0
eDP Lane x 2
HDMI 1.4b
CONN
P24
To M2 WiGig card
Card reader
RTS5250
DP DeMUX
PS8338
WIGIG DP
P23
P28P28
P22
DDI[1]
DDI[2]
PCIE[10]
SKYLAKE_U MCP
SPI
PAGE 6~19
SATA[2]/PCIE[11],[12]
USB2.0[1]
USB
HD Audio I/F
SATA[0]/PCIE[7]
PI5USB2544
USB POWER SHARE
DDR4-SO-DIMM X2
BANK 0, 1, 2, 3
P20~21
USB2.0[1]_PS
P36
HDA Codec
ALC3235
USB2.0[9]
USB2.0[2]
USB3.0[1]
USB2.0[4]
USB3.0[4]
USB2.0[3]
USB3.0[3]
P30
LCD Touch
P26
Camera
P26
USB3.0 Conn
PS(RIGHT)
USB3.0 Conn
(REAR LEFT)
USB3.0 Conn
(LEFT)
INT.Speaker
Universal Jack
P30
P30
Trough eDP Cable
P36
P37
P37
Dig. MIC
W25Q128FVSIQ
PCIE[9] PCIE[5]
PCIE[3]
PCIE[6]
LPC
W25Q64CVSSIQ
3 3
Intel Jacksonville
I219LM
Transformer
P27
P27
M.2,3042 Key B
WWAN/LTE/HCA
P29
USB2.0[10]
USB3.0[5]
M.2,3030 Key A
WLAN+BT/WIGIG
USB2.0[8]
WIGIG_DP
SMSC SIO
P29 P31
ECE5048
BC BUS
TPM2.0
NPCT650JAAYX
KB/TP CONN
SMSC KBC
P39
P33
P8
P8
SATA REPEATER
P42
SATA/PCIE REPEATER X1
PS8555
P34
SATA/PCIE REPEATER X1
PS8555
P34
Spindle
HDD Conn
Key M
HDD Conn
P35
P42
reserve PCIE signal for SATA express HDD
MEC5085
RJ45
P27
P32
FAN CONN
P32
Trough eDP Cable
LID SWITCH
LED/B
USH CONN
CPU&PCH XDP Port
AUTOMATIC POWER
SWITCH(APS)
P33
P14
P11
DC/DC Interface
4 4
Smart Card
A
TDA8034HN
RFID/NFC
Fingerprint
CONN
SPI
SPI
USH TPM1.2
BCM58102
B
USB2.0[7]
USH board
P30
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
POWER ON/OFF
SW & LED
Block diagram
Block diagram
Block diagram
LA-C621P
LA-C621P
LA-C621P
E
P41
P40
1.0
1.0
2 60Thursday, September 24, 2015
2 60Thursday, September 24, 2015
2 60Thursday, September 24, 2015
1.0
5
Vinafix.com
4
3
2
1
POWER STATES
S
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFL
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
(SOFT OFF) / M-OFF
S5
Signal
P
SLP
L
S3#
S4#
HIGH
HIGH HIGH
LOW HIGH HIGH
LOW
LOW
W HIGHLOW
O
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
S5#
SLP
A
#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
O
FF
OFF
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-6
PM TABLE
C C
power
plane
State
S0
+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW
+3.3V_ALW_PCH +1.2V_MEM
+RTC_CELL
+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT
ON
+3.3V_SUS
+1.0V_VCCST
+2.5V_MEM
ON ON
+5V_RUN
+3.3V_RUN
+
0.6V_DDR_VTT
+1.5V_RUN
(M-OFF)
+3.3V_M +3.3V_M
ON
+VCC_CORE
+VCC_GT
+1.0VS_VCCIO
+VCC_SA
ON
SSIC
SSIC-1
SSIC-2
PCIE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
PCIE-7
PCIE-8
PCIE-9
PCIE-10
PCIE-11
PCIE-12
SATA
SATA-0
SATA-1
SATA-1*
SATA-2
JUSB3-->Right
EDOCK PORT1
JUSB1-->LEFT
JUSB2-->Rear LEFT
M2 3042(WWAN)USB3.0-5
NA
M.2 3042(HCA or QCA LTE)
NA
M.2 3030(WLAN)
M.2 3030(WIGIG)
HDD SATA
EDOCK E-SATA
LOM
Card Reader
M.2 Socket 3 (Key M)
(PCIex2 or SATA)
USB PORT#DESTINATION
USH
DESTINATION
1
2
3
4
5
6
7
8
9
10
JUSB1-->Right
Camera
JUSB2-->LEFT
JUSB3-->Rear LEFT
EDOCK PORT1
EDOCK PORT2
USH
M.2 304230(BT)
Touch Screen
M2 3042(WWAN)
0
1
BIO
NA
Check
B B
A A
S3
S5 S4/AC
S5 S4/AC doesn't exist
ON
ON
OFF
OFFOFF
OFFON
OFF
OF
F
ON
ON
OFF
OFF
OFFOFF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-C621P
LA-C621P
LA-C621P
3 60Thursday, September 24, 2015
3 60Thursday, September 24, 2015
3 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
Vinafix.com
RT8207M
U201)
(P
ADAPTER
D D
CHARGER
BQ24777
(PU801)
+PWR_SRC
BATTERY
C C
ISL95857
(PU602)
SYX198D
(PU301)
T
PS62134A
(PU401)
HUB_LP_EN
PS62134B
T
(PU402)
SYX198C
(PU100)
SYX198B
(PU100)
AO6405
(QV1)
SIO_SLP_S4#
SIO_SLP_SUS#
ALWON
4
1.2V_MEM
+
RUN_ON
TPS22961
(UV28)
SIO_SLP_SUS#
ALWON
+1.0V_PRIM
+1.0VS_VCCIO
+1.0V_RUN_VMM
+1.0V_PRIM_CORE
+5V_ALW
5V_ALW2
+
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
LDOIN
RT8207
U201)
(P
3
0.675_DDR_VTT_ON
TPS22961
(UZ20)
TPS22961
(UZ19)
TPS22961
(UZ21)
TPS22967
(UZ23)
EM5209
(U
Z4)
EM5209
(UZ5)
PI5USB2544
(UI3)
SY6288
(UI1)
SY6288
(UI2)
SY8032A
(PU501)
EM5209
(UZ2)
+0.6V_DDR_VTT
MPHYP_PWR_EN
SIO_SLP_S3#
SIO_SLP_S4#
3.3V_HDD_EN
RUN_ON
AUD_PWR_EN
USB_PWR_EN1#
USB_PWR_EN2#
SIO_SLP_SUS#
SIO_SLP_LAN#
3.3V_WWAN_EN
@SIO_SLP_WLAN#
+5V_HDD
+5V_RUN
+5V_RUN_AUDIO
USB_PWR_SHR_VB US_EN
+1.0V_MPHYGT
+1.0V_VCCSTG
+1.0V_VCCST
+USB_LEFT_PWR
+USB_REAR_PWR
+1.8V_PRIM
+3.3V_LAN
+3.3V_WWAN
2
+5V_USB_CHG_PWR
AP7175SP
(PU1500)
SIO_SLP_S4#
1
CPU PWR
PCH PWR
GPU PWR
Peripheral Device PWR
+2.5V_MEM
IMVP_VR_ON
B B
V
CC_SA
A A
IMVP_VR_ON
IMVP_VR_ON
+BL_PWR_SRC
+VCC_GT+
+VCC_CORE
5
EN_INVPWR
EM5209
(UZ3)
EM5209
(UZ5)
TPS22967
(UZ8)
EM5209
(UZ4)
TPS22967
(UZ18)
AP2821
(U
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
V24)
@SIO_SLP_WLAN#
ENVCC_PCH
3
AUX_EN_WOWL
RUN_ON
AUD_PWR_EN
A_ON
SIO_SLP_SUS#
@PCH_ALW_ON
CV2_ON
+3.3V_WLAN
+3.3V_RUN
+3.3V_RUN_AUDIO
+3.3V_M
+3.3V_ALW_PCH
+3.3V_CV2
+LCDVDD
USH/B
LP2301
(QV8)
AP7175SP
(P
U502)
P2301A
L
(QZ1)
2
3.3V_TS_EN
+3.3V_RUN
3.3V_CAM_EN#
+3V_TSP
+1.5V_RUN
+3.3V_CAM
+3.3V_HDD
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-C621P
LA-C621P
LA-C621P
1
1.0
1.0
4 60Thursday, September 24, 2015
4 60Thursday, September 24, 2015
4 60Thursday, September 24, 2015
1.0
5
Vinafix.com
B4
A3
B5
A4
EM_SMBCLK
M
MEM_SMBDATA
SML0_SMBCLK
ML0_SMBDATA
S
1K
1K
DOCK_SMB_CLK
D
OCK_SMB_DAT
+3.3V_ALW_PCH
R7
R8
D D
SKL-U
R9
W2
V3W
3
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
499
499
4
1K
1K
+3.3V_ALW_PCH
2N7002
N7002
2
+3.3V_ALW_PCH
28
1
3
LOM
3
2
1
2.2K
2.2K
+3.3V_RUN
202
200
202
200
DIMMA
DIMMB
53
5
1
XDP
2.2K
2.2K
+3.3V_ALW
1
129
27
Dock
2.2K
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
@2.2K
@2.2K
A50
53
B
USH_SMBCLK
USH_SMBDAT
B B
MEC 5085
1E
1E
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
7
6
BATTERY
CONN
2.2K
2.2K
+3.3V_CV2
M9
L9
USH
USH/B
A49
2B
B52
2B
B50
A47
B7
A7
B48
B
49
CHARGER_SMBCLK
HARGER_SMBDAT
C
GPU_SMBDAT
GPU_SMBCLK
1G
1G
A A
2D
2D
2A
2A
5
0K
1
10K
2.2K
2.2K
4
+3.3V_ALW
+3.3V_RUN
9
8
Charger
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SMbus Block diagram
SMbus Block diagram
SMbus Block diagram
LA-C621P
LA-C621P
LA-C621P
5 60Thursday, September 24, 2015
5 60Thursday, September 24, 2015
5 60Thursday, September 24, 2015
1
1.0
1.0
1.0
5
Vinafix.com
4
3
2
1
+3.3V_RUN
CPU_DP1_CTRL_CLK
RC175 2.2K_0402_5%
RC178 2.2K_0402_5%
D D
RC176 2.2K_0402_5%
RC177 2.2K_0402_5%
C C
B B
12
CPU_DP1_CTRL_DATA
12
CPU_DP2_CTRL_CLK
12
CPU_DP2_CTRL_DATA
12
+1.0VS_VCCIO
CPU_DP1_N0<22>
CPU_DP1_P0<22>
CPU_DP1_N1<22>
CPU_DP1_P1<22>
CPU_DP1_N2<22>
CPU_DP1_P2<22>
CPU_DP1_N3<22>
CPU_DP1_P3<22>
CPU_DP2_N0<23>
CPU_DP2_P0<23>
CPU_DP2_N1<23>
CPU_DP2_P1<23>
CPU_DP2_N2<23>
CPU_DP2_P2<23>
CPU_DP2_N3<23>
CPU_DP2_P3<23>
CPU_DP1_CTRL_CLK<22>
CPU_DP1_CTRL_DATA<22> CPU_DP1_HPD <22>
CPU_DP2_CTRL_CLK<23>
CPU_DP2_CTRL_DATA<23>
@
T120
PAD~D
1 2
RC2 24.9_0402_1%
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
GPP_E23 CPU_DP1_HPD
EDP_COMP
UC1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKL-U_BGA1356
SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
UC1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
SKL-U_BGA1356
SKL-U
DDI
DISPLAY SIDEBANDS
SKL_ULT
EDP
1 OF 20
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
EDP_DISP_UTIL
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
9 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
CSI2_COMP
RC3
EMMC_RCOMP
EDP_TXN0 <26>
EDP_TXP0 <26>
EDP_TXN1 <26>
EDP_TXP1 <26>
CPU_DP1_AUXN
CPU_DP1_AUXP
CPU_DP3_AUXN
CPU_DP3_AUXP
CPU_DP2_HPD <23>
EDP_HPD <26>
PANEL_BKLEN <26>
EDP_BIA_PWM <26>
ENVDD_PCH <26,32>
1 2
100_0402_1%
1 2
RC4 200_0402_1%
Support QHD
EDP_AUXN <26>
EDP_AUXP <26>
CPU_DP2_AUXN <23>
CPU_DP2_AUXP <23>
@
T1
PAD~D
@
T2
PAD~D
CPU_DP1_AUXN
CPU_DP2_AUXN
CPU_DP2_AUXP
CPU_DP1_AUXP
EDP_HPD
CPU_DP2_HPD
+3.3V_RUN
12
RC179100K_0402_5%
12
RC181100K_0402_5%
12
RC182100K_0402_5%
12
RC180100K_0402_5%
12
RC1100K_0402_5%
12
@
RC312100K_0402_5%
12
RC242100K_0402_5%
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (1/14)
CPU (1/14)
CPU (1/14)
LA-C621P
LA-C621P
LA-C621P
6 60Thursday, September 24, 2015
6 60Thursday, September 24, 2015
6 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
Vinafix.com
4
DDR_A_DQS#[0..7]<20>
DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>
DDR_A_MA[0..16]<20>
3
2
1
D D
DDR4, Ballout for side by side(Non-Interleave)
UC1B
DDR_A_D0
AL71
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
C C
B B
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
SKL-U_BGA1356
SKL-U
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_M A[15]
DDR0_WE#/DDR0_CA B[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_M A[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
DDR_B_DQS#[0..7]<21>
DDR_B_D[0..63]<21>
DDR_B_DQS[0..7]<21>
DDR_B_MA[0..16]<21>
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
2 OF 20
DDR_A_CLK#0
AU53
DDR_A_CLK0
AT53
DDR_A_CLK#1
AU55
DDR_A_CLK1
AT55
DDR_A_CKE0
BA56
DDR_A_CKE1
BB56
DDR_A_CKE2
AW56
DDR_A_CKE3
AY56
DDR_A_CS#0
AU45
DDR_A_CS#1
AU43
DDR_A_ODT0
AT45
DDR_A_ODT1 DDR_B_ODT0
AT43
DDR_A_MA5
BA51
DDR_A_MA9
BB54
DDR_A_MA6
BA52
DDR_A_MA8
AY52
DDR_A_MA7
AW52
DDR_A_BG0
AY55
DDR_A_MA12
AW54
DDR_A_MA11
BA54
DDR_A_ACT#
BA55
DDR_A_BG1
AY54
DDR_A_MA13
AU46
DDR_A_MA15
AU48
DDR_A_MA14 DDR_B_MA15
AT46
DDR_A_MA16
AU50
DDR_A_BA0
AU52
DDR_A_MA2
AY51
DDR_A_BA1
AT48
DDR_A_MA10
AT50
DDR_A_MA1
BB50
DDR_A_MA0
AY50
DDR_A_MA3
BA50
DDR_A_MA4
BB52
DDR_A_DQS#0
AM70
DDR_A_DQS0
AM69
DDR_A_DQS#1
AT69
DDR_A_DQS1
AT70
DDR_A_DQS#4
BA64
DDR_A_DQS4
AY64
DDR_A_DQS#5
AY60
DDR_A_DQS5
BA60
DDR_B_DQS#0
BA38
DDR_B_DQS0
AY38
DDR_B_DQS#1
AY34
DDR_B_DQS1
BA34
DDR_B_DQS#4
BA30
DDR_B_DQS4
AY30
DDR_B_DQS#5
AY26
DDR_B_DQS5
BA26
DDR_A_ALERT#
AW50
DDR_A_PARITY
AT52
AY67
+DDR_VREF_A_DQ
AY68
BA67
AW67
DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>
DDR_A_CKE0 <20>
DDR_A_CKE1 <20>
@
PAD~D
@
PAD~D
DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>
Check ODT schematic 0918
DDR_A_BG0 <20>
DDR_A_ACT# <20>
DDR_A_BG1 <20>
DDR_A_BA0 <20>
DDR_A_BA1 <20>
DDR0_PAR,DDR0_ALERT# for DDR4
DDR_A_ALERT# <20>
+DDR_VREF_CA
+DDR_VREF_B_DQ
DDR_VTT_CTRL <20>
PAD~D
@
T132
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
T3
T4
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
UC1C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKL-U_BGA1356
SKL-U
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_M A[15]
DDR1_WE#/DDR1_CA B[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_M A[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DRAM_RESET#
DDR_RCOMP[0]
DDR CH - B
DDR_RCOMP[1]
DDR_RCOMP[2]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
3 OF 20
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT1
DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
DDR_B_ACT#
DDR_B_BG1
DDR_B_MA13
DDR_B_MA14
DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>
DDR_B_CKE0 <21>
DDR_B_CKE1 <21>
DDR_B_CS#0 <21>
DDR_B_CS#1 <21>
DDR_B_ODT0 <21>
DDR_B_ODT1 <21>
DDR_B_BG0 <21>
DDR_B_ACT# <21>
DDR_B_BG1 <21>
DDR_B_BA0 <21>
DDR_B_BA1 <21>
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_B_ALERT# <21>DDR_A_PARITY <20>
DDR_B_PARITY <21>
DDR_DRAMRST# <20>
@
T5
PAD~D
@
T6
PAD~D
C
heck ODT schematic 0918
DDR4 COMPENSATION SIGNALS
A A
5
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
1 2
RC5 121_0402_1%
1 2
RC6 80.6_0402_1%
1 2
RC7 100_0402_1%
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/14)
CPU (2/14)
CPU (2/14)
LA-C621P
LA-C621P
LA-C621P
7 60Thursday, September 24, 2015
7 60Thursday, September 24, 2015
7 60Thursday, September 24, 2015
1
1.0
1.0
1.0
5
Vinafix.com
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
PCH_SPI_D1
1 2
PCH_SPI_DO_XDP<14>
PCH_SPI_DO2_XDP<14>
D D
+3.3V_RUN
10K_0402_5%
12
RC267@
10K_0402_5%
12
RC268
DIMM Detect
HIGH
LOW
C C
PCH_SPI_CLK_1_R PCH _SPI_CLK_0_R
33_0402_5%
1 2
1 2
B B
A A
RC10 1K_0402_1%
RC11 1K_0402_1%
ONE_DIMM#
1 DIMM
2 DIMM
RC28
@EMC@
33P_0402_50V8J
CC7
@EMC@
1 2
PCH_SPI_CS#2<33>
+3.3V_RUN
12
SIO_RCIN#<32>
+3.3V_RUN
33_0402_5%
RC29
@EMC@
1 2
33P_0402_50V8J
CC8
@EMC@
1 2
9/5 MOW
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI
flash device on the platform has HOLD functionality disabled by default.
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms
with ES and SKL S/H platforms with pre-ES1/ES1 samples.
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
MEDIACARD_IRQ#<28>
PCH_CL_DATA1<29>
RC13
10K_0402_5%
IRQ_SERIRQ<31,32>
RC21 10K_0402_1%
+3.3V_SPI
@
@
@
@
RC37 0_0402_5%
RC39 33_0402_5%
RC42 0_0402_5%
@
RC43 33_0402_5%
@
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
1 2
1 2
1 2
ONE_DIMM#
PCH_SPI_D2_R1
PCH_SPI_D3_R1
PCH_SPI_D3_R1
TPM_PIRQ#<33>
FFS_INT2<42>
PCH_CL_CLK1<29>
PCH_CL_RST1#<29>
1 2
RC30 1K_0402_5%
RC31 1K_0402_5%
RC316 1K_0402_5%
1 2
1 2
1 2
1 2
4
UC1E
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN#
AY11
GPP_A6/SERIRQ
SKL-U_BGA1356
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
SPI - FLASH
SPI - TOUCH
C LINK
PCH_SPI_D1_R1<33>
PCH_SPI_D0_R1<33>
PCH_SPI_CLK_R1<33>
128Mb Flash ROM
UC5
1
2
3
4
W25Q128FVSIQ_SO8
64Mb Flash ROM
UC6
1
2
3
4
W25Q64FVSSIQ_SO8
/CS
DO(IO1)
/WP(IO2)
GND
@
/CS
DO(IO1)
/WP(IO2)
GND
SKL-U
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
PCH_SPI_D3_R1
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1
VCC
/HOLD(IO3)
CLK
DI(IO0)
VCC
/HOLD(IO3)
CLK
DI(IO0)
SMBUS, SMLINK
LPC
GPP_A14/SUS_STAT#/ESPI_RESET#
SOFTWARE TAA
RPC1
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
RPC2
@
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
+3.3V_SPI
0.1U_0201_10V6K
8
PCH_SPI_D3_0_R
7
6
PCH_SPI_D0_0_R
5
+3.3V_SPI
0.1U_0201_10V6K
8
PCH_SPI_D3_1_R
7
PCH_SPI_CLK_1_R
6
PCH_SPI_D0_1_R
5
3
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
5 OF 20
PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R
PCH_SPI_D3_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R
CC9
1 2
@
CC10
1 2
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
+3.3V_SPI
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
SML0_SMBCLK
SML0_SMBDATA
GPP_C5
SML1_SMBCLK
SML1_SMBDATA
GPP_B23
SUS_STAT#
PCI_CLK_LPC0
PCI_CLK_LPC1
CLKRUN# <31,32>
RC32 0_0402_5%
@
RC33 0_0402_5%
RC34 0_0402_5%
RC35 0_0402_5%
RC36 0_0402_5%
RC38 0_0402_5%
RC40 0_0402_5%
+3.3V_ALW_PCH
+3.3V_M
@
RC41 0_0402_5%
SML0_SMBCLK <27>
SML0_SMBDATA <27>
SML1_SMBCLK <32>
SML1_SMBDATA <32>
LPC_LAD0 <31,32>
LPC_LAD1 <31,32>
LPC_LAD2 <31,32>
LPC_LAD3 <31,32>
LPC_LFRAME# <31,32>
Reserve
RC16EMC@ 22_0402_5%
RC18EMC@ 22_0402_5%
RC22EMC@ 22_0402_5%
RC24EMC@ 22_0402_5%
CLK_PCI_5048
27P_0402_50V8J
CLK_PCI_MEC
27P_0402_50V8J
CLK_PCI_LPDEBUG
27P_0402_50V8J
CLK_PCI_DOCK
27P_0402_50V8J
Reserve for RF
PCH_SPI_CS#1_R1
12
PCH_SPI_CS#1
PCH_SPI_D0_R1
12
PCH_SPI_D0
PCH_SPI_D1_R1
12
PCH_SPI_D1
PCH_SPI_CLK_R1
12
PCH_SPI_CLK
PCH_SPI_CS#0_R1
12
PCH_SPI_CS#0
PCH_SPI_D2_R1
12
PCH_SPI_D2
PCH_SPI_D3_R1
12
PCH_SPI_D3
@
RC289 0_0402_5%
RC276 0_0402_5%@
+3.3V_SPI_R
12
1 2
1 2
1 2
1 2
12
12
2
12
EMC@
CC3
12
EMC@
CC4
12
EMC@
CC5
12
EMC@
CC6
E-T_6705K-Y20N-00L
22
GND2
21
GND1
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JSPI1
CONN@
MEM_SMBCLK
MEM_SMBDATA
DMN65D8LDW-7_SOT363-6
CLK_PCI_5048 <31>
CLK_PCI_MEC <32>
CLK_PCI_LPDEBUG <32>
CLK_PCI_DOCK < 38>
SIO_SLP_A#<11,32>
SIO_SLP_SUS#<11,17,18,32,41,46,47,48>
1
+3.3V_RUN
DDR_XDP_WAN_S MBDAT
DDR_XDP_WAN_S MBCLK
2
1
5
3 4
QC2B
6
DMN65D8LDW-7_SOT363-6
DDR_XDP_WAN_S MBCLK <14,20,21,42>
QC2A
DDR_XDP_WAN_S MBDAT <14,20,21,42>
SML0_SMBCLK
SML0_SMBDATA
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SUS_STAT#
SML0_SMBCLK
SML0_SMBDATA
CLKRUN#
FFS_INT2
PCH_SMB_ALERT#
R
eserve
@
RC19 499_0402_1%
@
RC20 499_0402_1%
1 2
1 2
1 2
RC12 1K_0402_5%
1 2
RC14 1K_0402_5%
1 2
RC15 1K_0402_5%
1 2
RC17 1K_0402_5%
1 2
RC26@ 10K_0402_5%
1 2
RC347 499_0402_1%
1 2
RC348 499_0402_1%
8/5 CKLT0.9
1 2
RC27 8.2K_0402_5%
1 2
RC322 10K_0402_5%
RC23 2.2K_0402_5%
TLS CONFIDENTIALITY
GPP_C5
HIGH
LOW(DEFAULT)
RC25 10K_0402_5%@
ENABLE
DISABLE
1 2
EC interface
HIGH
LOW(DEFAULT)
+3.3V_RUN +3.3V_ALW_PCH
150K_0402_5%
@
RC326
@
RC327 0_0402_5%
12
12
S
G
WEAK INTERNAL PD
1 2
GPP_B23 GPP_B 23_Q
@
RC339 0_0402_5%
RC340@ 0_0402_5%
ESPI
LPC
12
D
13
@
QC3
L2N7002WT1G_SC-70-3
2
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
+3.3V_ALW_PCH
12
+3.3V_ALW_PCH
150K_0402_5%
1 2
ENABLED
DIABLED
+3.3V_RUN
12
RC3182.2K_0402_5%
12
RC3192.2K_0402_5%
+3.3V_LAN
+3.3V_ALW_PCH
+3.3V_RUN
RC317
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/14)
CPU (3/14)
CPU (3/14)
LA-C621P
LA-C621P
LA-C621P
8 60Thursday, September 24, 2015
8 60Thursday, September 24, 2015
8 60Thursday, September 24, 2015
1
1.0
1.0
1.0
5
Vinafix.com
4
3
2
1
+3.3V_ALW_PCH
+3.3V_RUN
UC1F
LPSS ISH
AN8
3.3V_TP_EN
D D
C C
1 2
RC270 10K_0402_5%
1 2
RC282 100K_0402_5%
1 2
RC335 49.9K_0402_1%
@
1 2
RC336 49.9K_0402_1%
@
1 2
RC279 10K_0402_5%
1 2
RC292 10K_0402_5%
RC237 10K_0402_5%
+3.3V_ALW_PCH
1 2
RC283 10K_0402_5%
1 2
RC330 49.9K_0402_1%
1 2
RC331 49.9K_0402_1%
+3.3V_ALW_PCH
12
1 2
RC186 4.7K_0402_5%
@
R
eserve
TS_EN
LPSS_UART2_TXD
LPSS_UART2_RXD
AUD_PWR_EN
HOST_SD_WP#
SIO_EXT_SCI#
SIO_EXT_WAKE#
LPSS_UART2_RXD
LPSS_UART2_TXD
NRB_BIT
SIO_EXT_SCI#<32>
TS_EN<26>
HDD_EN<42>
UART0_TXD<32>
HOST_SD_WP#<28>
SIO_EXT_WAKE#<32>
I2C_1_SDA<39>
Reserve
I2C_1_SCL<39>
NRB_BIT
3.3V_TP_EN
LPSS_UART2_RXD
LPSS_UART2_TXD
Reserve
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
SKL-U_BGA1356
SKL-U
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA /I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_S CL
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALER T#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
6 OF 20
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
DIMM_TYPE
CLKDET#
NON_DOCK
9/24: Reserve for embedded location ,refer Intel PDG 0.9
ISH_I2C2_SDA <29>
ISH_I2C2_SCL <29>
ISH_UART0_RXD <29>
ISH_UART0_TXD <29>
ISH_UART0_RTS# <29>
ISH_UART0_CTS# <29>
LCD_CBL_DET# <26>
@
T121
PAD~D
VMM3320_LPM_DIS <24>
KB_DET# <39>
AUD_PWR_EN <30>
IR_CAM_DET# <26>
WWAN
WLAN
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
Weak IPD
B B
+3.3V_ALW_PCH
12
RC184
@
8.2K_0402_5%
HDD_EN
No REBOOT
REBOOT ENABLE
+5V_ALW
LPSS_UART2_TXD
LPSS_UART2_RXD
JUART1
1
1
2
2
3
3
4
4
5
GND
6
GND
ACES_50207-00471-P01
8/21
KB_DET#
LCD_CBL_DET#
IR_CAM_DET#
NON_DOCK
+3.3V_ALW_PCH
12
@
12
1 2
RC288 10K_0402_5%
1 2
RC287 100K_0402_5%
1 2
RC346 100K_0402_5%
1 2
RH359 100_0402_1%
@
RC341
10K_0402_5%
DIMM_TYPE
RC342
10K_0402_5%
HIGH
DIMM_TYPE
DDR3L
DR4LOW
D
+3.3V_RUN
BOOT BIOS Destination(Bit 10)
HIGH
LOW(DEFAULT)
LPC
SPI
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (4/14)
CPU (4/14)
CPU (4/14)
LA-C621P
LA-C621P
LA-C621P
9 60Thursday, September 24, 2015
9 60Thursday, September 24, 2015
9 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
Vinafix.com
4
3
2
1
UC1H
PCIE/USB3/SATA
D D
WWAN
WWAN --->
WLAN --->
WIGIG--->
C C
SATA HDD--->
E DOCK ESATA--->
10/100/1G LAN --->
Card Reader --->
SATA EXPRESS HDD --->
B B
USB3_PRX_DTX_N5<29>
USB3_PRX_DTX_P5<29>
USB3_PTX_DRX_N5<29>
USB3_PTX_DRX_P5<29>
PCIE_PRX_DTX_N3<29>
PCIE_PRX_DTX_P3<29>
PCIE_PTX_DRX_N3<29>
PCIE_PTX_DRX_P3<29>
PCIE_PRX_DTX_N5<29>
PCIE_PRX_DTX_P5<29>
PCIE_PTX_DRX_N5<29>
PCIE_PTX_DRX_P5<29>
PCIE_PRX_DTX_N6<29>
PCIE_PRX_DTX_P6<29>
PCIE_PTX_DRX_N6<29>
PCIE_PTX_DRX_P6<29>
SATA_PRX_DTX_N0<42>
SATA_PRX_DTX_P0<42>
SATA_PTX_DRX_N0<42>
SATA_PTX_DRX_P0<42>
SATA_PRX_DTX_N1<38>
SATA_PRX_DTX_P1<38>
SATA_PTX_DRX_N1<38>
SATA_PTX_DRX_P1<38>
PCIE_PRX_DTX_N9<27>
PCIE_PRX_DTX_P9<27>
PCIE_PTX_DRX_N9<27>
PCIE_PTX_DRX_P9<27>
PCIE_PRX_DTX_N10<28>
PCIE_PRX_DTX_P10<28>
PCIE_PTX_DRX_N10<28>
PCIE_PTX_DRX_P10<28>
1 2
RC45 100_0402_1%
PCIE_PRX_DTX_N11<34>
PCIE_PRX_DTX_P11<34>
PCIE_PTX_DRX_N11<34>
PCIE_PTX_DRX_P11<34>
PCIE_PRX_DTX_N12<34>
PCIE_PRX_DTX_P12<34>
PCIE_PTX_DRX_N12<34>
PCIE_PTX_DRX_P12<34>
PCIE_RCOMPN
PCIE_RCOMPP
CPU_XDP_PRDY#<14>
CPU_XDP_PREQ#<14>
HDD_FALL_INT<42>
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKL-U_BGA1356
SKL-U
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
8 OF 20
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USBCOMP
USB_OC3#
SATAGP1
USB3_PRX_DTX_N1 <36>
USB3_PRX_DTX_P1 <36>
USB3_PTX_DRX_N1 <36>
USB3_PTX_DRX_P1 <36>
USB3_PRX_DTX_N2 <38>
USB3_PRX_DTX_P2 <38>
USB3_PTX_DRX_N2 <38>
USB3_PTX_DRX_P2 <38>
USB3_PRX_DTX_N3 <37>
USB3_PRX_DTX_P3 <37>
USB3_PTX_DRX_N3 <37>
USB3_PTX_DRX_P3 <37>
USB3_PRX_DTX_N4 <37>
USB3_PRX_DTX_P4 <37>
USB3_PTX_DRX_N4 <37>
USB3_PTX_DRX_P4 <37>
USB20_N1 <36>
USB20_P1 <36>
USB20_N2 <26>
USB20_P2 <26>
USB20_N3 <37>
USB20_P3 <37>
USB20_N4 <37>
USB20_P4 <37>
USB20_N5 <38>
USB20_P5 <38>
USB20_N6 <38>
USB20_P6 <38>
USB20_N7 <33>
USB20_P7 <33>
USB20_N8 <29>
USB20_P8 <29>
USB20_N9 <26>
USB20_P9 <26>
USB20_N10 <29>
USB20_P10 <29>
1 2
RC44 113_0402_1%
@
1 2
RC337 0_0402_5%
1 2
RC338 1K_0402_5%
USB_OC0# <36>
USB_OC1# <37>
USB_OC2# <37>
R
eserve
HDD_DEVSLP <42>
M2_DEVSLP <35>
HDD_DET# <42>
Reserve
IFDET_SATA#_PCIE <34,35>
PCH_SATA_LED# <35,40>
-----> Ext USB3 Port 3 Charge(RIGHT)
-----> EDOCK
-----> Ext USB3 Port 1(LEFT)
-----> Ext USB3 Port 2(REAR LEFT)
-----> Ext USB Port 3 Charge(RIGHT)
-----> Camera
-----> Ext USB Port 1(LEFT)
-----> Ext USB Port 2(REAR LEFT)
-----> EDOCK PORT1
-----> EDOCK PORT2
-----> USH
-----> BT
-----> LCD Touch
-----> M2 3042(WWAN)
8/19 for layout routing change
USB_OC0#
USB_OC3#
USB_OC1#
USB_OC2#
HDD_FALL_INT
IFDET_SATA#_PCIE
PCH_SATA_LED#
HDD_DET#
SATAGP1
RPC3
4 5
3
6
2
7
1
8
10K_8P4R_5%
RPC4
4 5
3
6
2
7
1
8
10K_8P4R_5%
1 2
RC246 10K_0402_5%
CKLT0.9
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_ALW_PCH
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (5/14)
CPU (5/14)
CPU (5/14)
LA-C621P
LA-C621P
LA-C621P
10 60Thursday, September 24, 2015
10 60Thursday, September 24, 2015
10 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
Vinafix.com
CLK_PCIE_N0<29>
WWAN
D D
WLAN--->
WIGIG--->
SATA EXPRESS HDD--->
LAN--->
MMI --->
H_CPUPWRGD VCCST_PW RGD
100P_0402_50V8J
12
CC300EMC@
C C
+1.0V_VCCST
RC71 1K_0402_5%
+3.3V_ALW_PCH
RC74 10K_0402_5%@
10/6 depop, prevent singal step.
B B
100P_0402_50V8J
12
SD Request:place near CPU side
E
1 2
1 2
@
T9
PAD~D
VCCST_PWRGD<14,32>
RC215
POP
DE-POP
PCH_DPWROK PCH_RSMRST#_Q
0.01UF_0402_25V7K
12
1
CC266
A A
2
CLK_PCIE_P0<29>
CLKREQ_PCIE#0<29>
CLK_PCIE_N1<29>
CLK_PCIE_P1<29>
CLKREQ_PCIE#1<29>
CLK_PCIE_N2<29>
CLK_PCIE_P2<29>
CLKREQ_PCIE#2<29>
CLK_PCIE_N3<35>
CLK_PCIE_P3<35>
CLKREQ_PCIE#3<35>
CLK_PCIE_N4<27>
CLK_PCIE_P4<27>
CLKREQ_PCIE#4<27>
CLK_PCIE_N5<28>
CLK_PCIE_P5<28>
CLKREQ_PCIE#5<28>
CC301@EMC@
VCCST_PWRGD
ME_SUS_PWR_AC K
RC75 10K_0402_5 %
NO Support Deep sleep
Support Deep sleep
1 2
RC215 0_0402_5%
@
100K_0402_1%
RC220
1 2
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_ALW_DSW
+3.3V_RUN
RC189 10K_0402_5%
1 2
RC47 10K_0402_5 %
1 2
RC50 10K_0402_5 %
1 2
RC59 10K_0402_5 %
1 2
RC51 10K_0402_5 %
1 2
RC190 10K_0402_5%
PCH_PLTRST#
1 2
RC67 1K_0402_5%
1 2
RC323 10K_0402_5%
1 2
RC225@ 8.2K_0402_5%
PCH_RSMRST#_Q<14,39>
1 2
1 2
RC77 1K_0402_5%@
1 2
RC78 60.4_0402_1%
PCH_DPWROK<32> POWER_SW#_M B<32,40>
ME_SUS_PWR_AC K<32>
PCH_PCIE_WAKE#<31,32>
PM_LANPHY_ENABLE<27>
XDP_DBRESET#<14>
+3.3V_ALW_PCH
1
2
UC7
TC7SH08FU_SSOP5~D
PCH_PCIE_WAKE# SIO_SLP_LAN#
LAN_WAKE#
ME_RESET#
PCH_PLTRST#
SYS_RESET#
PCH_RSMRST#_Q
H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU
RESET_OUT#<14,32>
PCH_PWROK<49>
SUSACK#<32>
LAN_WAKE#<27,32>
3.3V_CAM_EN#<26>
1 2
RC311 10K_0402_5%
8/28 schematic review
XDP_DBRESET#
RC227@ 8.2K_0402_5%
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
5
4
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKL-U_BGA1356
12
12
12
12
RC244 @0_0402_5%
12
RC600_0402_5%
12
RC325 @0_0402_5%
5
P
B
O
A
G
3
AN10
B5
AY17
A68
B65
B6
BA20
BB20
AR13
AP11
BB15
AM15
AW17
AT15
@
RC290 0_0402_5%
ME_RESET#
12
4
UC1J
RC610_0402_5%
@
RC62 @0_0402_5%
RC64 @0_0402_5%
@
PCH_PLTRST#_AND
4
12
RC65
@
100K_0402_5%
UC1K
GPP_B13/PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
VCCST_PWRGD
SYS_PWROK
PCH_PWROK
DSW_PWROK
GPP_A13/SUSWARN#/SUSPW RDNACK
GPP_A15/SUSACK#
WAKE#
GPD2/LAN_WAKE#
GPD11/LANPHYPC
GPD7/RSVD
SKL-U_BGA1356
1 2
+3.3V_RUN
5
1
B
2
A
3
CLOCK SIGNALS
PLTRST_VMM2320# <24>
PLTRST_LAN# <27>
PLTRST_5048# <31>
PCH_PLTRST#_EC <32>
PLTRST_TPM# <33>
PCH_PLTRST#_AND <28,29,33,35>
SYSTEM POWER MANAGEMENT
P
4
O
G
UC12@
74AHC1G09GW_TSSOP5
SKL_ULT
SKL-U
SYS_RESET#_R
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
10 OF 20
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
GPP_B11/EXT_PWR_GATE#
1 2
RC224 1K_0402_5%
INTRUDER#
GPP_B2/VRALERT#
+3.3V_RUN
SYS_RESET#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SUSCLK
CLK_ITPXDP_N
F43
CLK_ITPXDP_P
E43
BA17
XTAL24_IN
E37
XTAL24_OUT
E35
XCLK_BIASREF
E42
PCH_RTCX1
AM18
PCH_RTCX2
AM20
AN18
SRTCRST#
AM16
PCH_RTCRST#
CMOS1 must take care short & touch risk on layout placement
8/21 can change to 10K for merge to RP
PCH_BATLOW#
AC_PRESENT
AT11
AP15
BA16
AY16
AN15
SLP_SUS#
AW15
SLP_LAN#
BB17
AN16
BA15
AY15
PCH_BATLOW#
AU13
AU11
PME#
AP16
INTRUDER#
AM10
AM11
VRALERT#
11 OF 20
12
RC291
@
10K_0402_5%
3
2
1 2
RC48 1K_0402_5%@
1 2
RC297 0_0402_5%@
1 2
RC298 0_0402_5%@
SUSCLK <29,35>
For Skylake pop RC52 and depop RC324
For Cannonlake depop RC52 and pop RC324
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
1 2
RC52 2.7K_0402_1%
1 2
@
RC324 59_0402_1%
@
@
SIO_SLP_S0# <17,33,47>
SIO_SLP_S3# <17,32,48>
SIO_SLP_S4# <17,32,45,54>
SIO_SLP_S5# <32>
1 2
RC56 20K_0402_5 %
1 2
CC24 1U_0402_6.3V6K
1 2
RC57 20K_0402_5 %
1 2
CC25 1U_0402_6.3V6K
1
1
2
SHORT PADS~D
@
CMOS1
1 2
RC344 10K_0402_5%
1 2
RC68 10K_0402_5%
1 2
RC72 8.2K_0402_5%
1 2
RC243 10K_0402_5%
SIO_SLP_SUS# <8,17,18,32,41,46,47,48>
SIO_SLP_LAN# <32,41>
SIO_SLP_WLAN# <31,41>
SIO_SLP_A# <8,32>
SIO_PWRBTN# <14,32>
AC_PRESENT <32>
PAD~D
MPHYP_PWR_EN <18>
co
nnect to VCCMPHYGTAON_1P0 enable pin
@
+3.3V_ALW
+3.3V_ALW_DSW
T115
CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>
+1.0V_CLK5
+RTC_CELL
2
+3.3V_ALW_PCH
INTRUDER#
VRALERT#
SLP_S0# for support connect stand by mode
8/21 CRB1.0 change to 0603 1/10W
2
1M_0402_1%
RC46
XTAL24_IN
XTAL24_OUT XTAL24_OUT_R
PCH_RTCX1
PCH_RTCX2
1 2
RC69 1M_0402_5%
1 2
@
RC73 10K_0402_5%
1 2
RC343 10K_0402_5%
1 2
1 2
@
RC295 0_0402_5%
For Skylake YC1 24MHz(50 Ohm ESR)
For Cannonlake YC1 38.4MHz(30 Ohm ESR)
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
RC54
10M_0402_5%
1 2
@
RC296 0_0402_5%
+RTC_CELL
+3.3V_ALW_PCH
+3.3V_ALW_DSW
+3.3V_ALW_DSW
SYS_RESET#
0.1U_0402_25V6
@EMC@
12
CC302
ESD Request:place near CPU side
1 2
+3.3V_ALW_PCH+3.3V_ALW
PCH_RTCX2_R
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
1
3
4
YC1
24MHZ_12PF_X3G024000DC1H
1
2
12
YC2
32.768KHZ 9PF10PPM 9H03200055
ESR MAX=50k ohm
CPU (6/14)
CPU (6/14)
CPU (6/14)
LA-C621P
LA-C621P
LA-C621P
1
CC21
1 2
15P_0402_50V8J
CC22
1 2
15P_0402_50V8J
CC23
12
5P_0402_50V8C
CC26
12
5P_0402_50V8C
JAPS1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
CONN@
ACES_50506-01841-P01
11 60Thursday, September 24, 2015
11 60Thursday, September 24, 2015
11 60Thursday, September 24, 2015
1.0
1.0
1.0
5
Vinafix.com
+1.0V_VCCST
8/21 DG0.9
@
RC79 49.9_0402_1%
RC80 1K_0402_5%
+1.0V_VCCSTG
/19 DG0.9
8
RC83 1K_0402_5%
+3.3V_RUN
D D
RC272 10K_0402_5%
10K_8P4R_5%
+3.3V_ALW_PCH
RC236 10K_0402_5%
C C
B B
1 2
1 2
1 2
1 2
RPC5
4 5
3
2
1
1 2
H_CATERR#
H_THERMTRIP#
H_PROCHOT#
TOUCH_SCREEN_PD#
6
CAM_MIC_CBL_DET#
7
CONTACTLESS_DET#
8
SIO_EXT_SMI#
HDA_SYNC_R<30>
HDA_BIT_CLK_R<30>
HDA_SDOUT_R<30>
22P_0402_50V8J
Close to RC93
CC27
HDA_RST#_R<30>
H_PROCHOT#<32,49,51>
H_THERMTRIP#<20,21,32>
1 2
RC92 33_0402_5%
1 2
RC93 33_0402_5%EMC@
1 2
RC94 33_0402_5%
ME_FWP
HDA_BIT_CLK_R
1
2
1 2
RC223 1K_0402_5%
RC95 33_0402_5%
8/19 DG0.9
1 2
RC84 499_0402_1%
TOUCH_SCREEN_PD#<26>
TOUCHPAD_INTR#<39>
TOUCH_SCREEN_DET#<26>
12
1 2
PECI_EC<32>
SIO_EXT_SMI#<32>
RC88
SPKR<30>
XDP_OBS0_R<14>
XDP_OBS1_R<14>
T10
T11
12
49.9_0402_1%
4
@
PAD~D
@
PAD~D
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
12
RC90
RC89
49.9_0402_1%
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0<30>
HDA_RST#
H_CATERR#
H_PROCHOT#_R
H_THERMTRIP#TOUCHPAD_INT R#
XDP_OBS2_R
XDP_OBS3_R
EOPIO_RCOMP
12
RC91
49.9_0402_1%
49.9_0402_1%
AW22
AW20
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
AT16
AU16
H66
H65
UC1G
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
SKL-U_BGA1356
UC1D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
SKL-U_BGA1356
AUDIO
CPU MISC
SKL-U
SKL-U
3
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
4 OF 20
SDIO/SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
CPU_XDP_TCLK
B61
CPU_XDP_TDI
D60
CPU_XDP_TDO
A61
CPU_XDP_TMS
C60
CPU_XDP_TRST#
B59
PCH_JTAG_TCK
B56
PCH_JTAG_TDI
D59
PCH_JTAG_TDO
A56
PCH_JTAG_TMS
C59
CPU_XDP_TRST#
C61
XDP_JTAGX
A59
RC87 1K_0402_5%@
@
RC328 0_0402_5%
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
1 2
7 OF 20
CPU_XDP_TCLK <1 4>
CPU_XDP_TDI <14>
CPU_XDP_TDO < 14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>
PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
CPU_XDP_TCLK
12
CONTACTLESS_DET#
SD_RCOMP
+1.0V_VCCSTG
2
RC86 51_0402_5%@
CAM_MIC_CBL_DET# <26>
RC96 200_0402_1%
12
CONTACTLESS_DET# <33>
1 2
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
+3.3V_ALW_PCH
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
PCH_JTAG_TDI
51_0402_5%
PCH_JTAG_TDO
100_0402_1%
PCH_JTAG_TMS
51_0402_5%
12
@
RC222
1K_0402_5%
+1.0V_VCCSTG
12
RC81
12
RC82
12
RC130
ME_FWPME_FWP_EC
ME_FWP
12
@
1
2
3
4
5
@
RC221 0_0402_5%
PT,ST pop RC222 and SW1; MP pop RC221
ME_FWP_EC<31>
SW1
A
B
C
G1
G2
SS3-CMFTQR9_3P
1
+3.3V_ALW_PCH +3.3V_ALW_PCH
1 2
RC183 8.2K_0402_5%@
TOP SWAP STRAP
A A
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
SPKR
RC187 4.7K_0402_5%@
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
1 2
HDA_SDOUT
DISABLE
ENABLE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (7/14)
CPU (7/14)
CPU (7/14)
LA-C621P
LA-C621P
LA-C621P
12 60Thursday, September 24, 2015
12 60Thursday, September 24, 2015
12 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
Vinafix.com
D D
4
3
2
1
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin
CFG[0..19]<14>
C C
1 2
RC113 10K_0402_1%@
CFG0
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
+1.0V_PRIM_XDP
1 2
RC112 10K_0402_1%@
1 2
RC110 10K_0402_1%@
RC114 49.9_0402_1%
RC115 1.5K_0402_5%
ITP_PMODE<14>
CFG_RCOMP
12
ITP_PMODE
12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
Stall reset sequence
HIGH(DEFAULT)
LOW
B B
No stall(Normal Operation)
stall
1 2
RC109 1K_0402_5%
CFG4
@
T16
PAD~D
@
T17
PAD~D
eDP enable For Skylake RC120 depop
HIGH(DEFAULT)
LOW
Disabled
Enabled
AL25
AL27
BA70
BA68
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
UC1S
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKL-U_BGA1356
RESERVED SIGNALS-1
SKL-U
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
19 OF 20
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
AR56
AW71
AW70
AP56
C64
@
For Cannonlake RC120 pop
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
@
T12
PAD~D
@
T13
PAD~D
@
T14
PAD~D
@
T15
PAD~D
@
T128
PAD~D
@
T129
PAD~D
@
T130
PAD~D
@
T126
PAD~D
@
T127
PAD~D
@
T113
PAD~D
@
T114
PAD~D
1 2
RC120 100K_0402_5%
ZVM# for SKYLAKE-U 2+3e
1/5 2014WW52 MOW reserve to support
C
annonlake-U PCH compatibility
close UC1.U11/U12 and <400mil
1 2
RC313 0_0402_5%@
+1.0V_VCCST
+VCC_1P8+1.8V_PRIM
1
2
MSM# for SKYLAKE-U 2+3e
SPARE
SKL-U
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
F6
E3
C11
B11
A11
D12
C12
F52
UC1T
AW69
RSVD_AW69
AW68
RSVD_AW68
AU56
RSVD_AU56
AW48
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
RSVD_H11
SKL-U_BGA1356
CC222
@
1U_0402_6.3V6K
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (8/14)
CPU (8/14)
CPU (8/14)
LA-C621P
LA-C621P
LA-C621P
13 60Thursday, September 24, 2015
13 60Thursday, September 24, 2015
13 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
CC29
Vinafix.com
5
+1.0V_PRIM_XDP
XDP_OBS0_R<12>
XDP_OBS1_R<12>
RC123 1K_0402_5%@
RC124
CXDP@ 1K_0402_5%
PCH_SPI_DO_XDP<8>
RESET_OUT#<11,32>
RC239 0_0402_5%
CXDP@
RC240 0_0402_5%
CXDP@
RC5 need to close to JCPU1
1 2
1 2
FIVR_EN
CFG0
RC217 0_0402_5%
@
RC126 1K_0402 _5%
@
RC128 0_0402_5%
CXDP@
RC129 0_0402_5%
@
DDR_XDP_WAN_S MBDAT<8,20,21,42>
DDR_XDP_WAN_S MBCLK<8,20,21,42>
CPU_XDP_PREQ#<10>
CPU_XDP_PRDY#<10>
1 2
1 2
1 2
1 2
1 2
1 2
PCH_JTAG_TCK<12>
CPU_XDP_TCLK<12>
CPU XDP
H_VCCST_PWRGD_XD P
SIO_PWRBTN#<11,32>
CPU_XDP_PREQ#
CPU_XDP_PRDY#
RESET_OUT#_R
CPU_XDP_TCLK
+1.0V_PRIM
1 2
RC216 0_0603_1%
@
+1.0V_PRIM_XDP
0.1U_0201_10V6K
0.1U_0201_10V6K
@
@
CC28
1
1
2
2
D D
Place near
JXDP1
VCCST_PWRGD<11,32>
PCH_RSMRST#_Q<11,39>
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
FIVR_EN_R
4
XDP_PRSNT_PIN1
1 2
RC121 1K_0402_5%
1 2
RC122 0_0402_5%@
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
CXDP@
CFG3
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TRST#
TMS
GND17
CONN@SAMTE_BSH-030-01-L-D-A
TD0
TDI
+1.0V_PRIM_XDP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
ITP_PMODE
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS
3
CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>
ITP_PMODE <13>
XDP_DBRESET# <11>
PCH_SPI_DO2_XDP <8>
2
CFG[0..19]<13>
+3.3V_RUN
CC30
1 2
0.1U_0201_10V6K
TDO_XDP
TDI_XDP
XDP_TMS
TRST#_XDP
RUNPWROK<31,32>
UC8
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
GND
GND PAD
1
3
1B
6
2B
8
3B
11
4B
7
15
CPU_XDP_TDO < 12>
CPU_XDP_TDI <12>
CPU_XDP_TMS <12>
CPU_XDP_TRST# <12>
+1.0VS_VCCIO
C C
B B
+1.0V_VCCST
+3.3V_RUN
+1.0V_PRIM_XDP
1 2
RC132 150_0402_5%
1 2
RC218 150_0402_5%
@
1 2
RC219 10K_0402_5%
@
1 2
RC137
1 2
RC138
@
FIVR_EN_R
FIVR_EN
FIVR_EN
XDP_DBRESET#
1K_0402_5%
CPU_XDP_PREQ#
51_0402_5%
CKLT0.9
+3.3V_ALW_PCH
0.1U_0402_25V6
CC33@
Place near JXDP1.47
12
RC133
1.5K_0402_5%
CXDP@
PCH_SPI_DO_XDP
RESET_OUT#_R
12
9/1 follow SPI PWR rail
Place near JXDP1.48
XDP_DBRESET#
CPU_XDP_TMS
51_0402_5%
+3.3V_ALW_DSW
0.1U_0402_25V6
CC32
CXDP@
12
SIO_PWRBTN#
12
12
E
DS0.7
1.5K_0402_5%
RC241
@
0.1U_0402_25V6
CC269
@
Place near JXDP1.41
CPU_XDP_TDI
51_0402_5%
CPU_XDP_TDO
100_0402_1%
CPU_XDP_TRST#
51_0402_5%
CPU_XDP_TCLK
51_0402_5%
XDP_TMS
1 2
@
RC228 0_0402_5%
TDI_XDP
1 2
@
RC229 0_0402_5%
TDO_XDP
1 2
@
RC230 0_0402_5%
12
12
12
12
12
RC131
RC134
RC135
RC136 CXDP@
RC139
+1.0V_VCCSTG
PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (9/14)
CPU (9/14)
CPU (9/14)
LA-C621P
LA-C621P
LA-C621P
14 60Thursday, September 24, 2015
14 60Thursday, September 24, 2015
14 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
Vinafix.com
4
3
2
1
+VCC_CORE: 0.3~1.35V
D D
@
T122
PAD~D
@
T123
PAD~D
C C
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)
+VCC_CORE +VCC_CORE
+VCC_CORE_G0
+VCC_CORE_G1
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD_K32
AK32
RSVD_AK32
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
SKL-U_BGA1356
UC1L
SKL-U
CPU POWER 1 OF 4
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
12 OF 20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
VCCSENSE
VSSSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
+1.0V_VCCSTG_R
VIDSCLK <49>
+VCC_CORE
12
RC140
100_0402_1%
12
RC141
100_0402_1%
1 2
@
RC143 0_0603_5%
VCCSENSE <49>
VSSSENSE < 49>
+1.0V_VCCSTG
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package
Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
ESD Request
+VCC_CORE +1.2V_MEM
+1.0V_PRIM +VCC_CORE
CC282
CC283
CC284
CC285
CC286
CC287
1 2
1 2
1 2
1 2
1 2
1 2
22U_0603_6.3V6M@EMC@
22U_0603_6.3V6M@EMC@
22U_0603_6.3V6M@EMC@
+3.3V_RUN+1.0V_PRIM
22U_0603_6.3V6M@EMC@
+1.2V_MEM+1.0V_PRIM
22U_0603_6.3V6M@EMC@
+3.3V_RUN+VCC_CORE
22U_0603_6.3V6M@EMC@
B B
8/21 CRB1.0 , DG0.9
SVID ALERT
VIDALERT_N<49>
SVID DATA
A A
VIDSOUT<49>
5
4
+1.0V_VCCST
12
+1.0V_VCCST
12
56_0402_1%
RC152
100_0402_1%
RC157
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils
H_CPU_SVIDALRT#
12
RC153220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/14)
CPU (10/14)
CPU (10/14)
LA-C621P
LA-C621P
LA-C621P
15 60Thursday, September 24, 2015
15 60Thursday, September 24, 2015
15 60Thursday, September 24, 2015
1
1.0
1.0
1.0
5
Vinafix.com
4
3
2
1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
+VCC_GT +VCC_GT
D D
C C
+VCC_GT
12
RC161
100_0402_1%
VCC_GT_SENSE<49>
VSS_GT_SENSE<49>
B B
VCC_GT_SENSE
VSS_GT_SENSE
12
RC163
100_0402_1%
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
UC1M
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
SKL-U_BGA1356
CPU POWER 2 OF 4
SKL-U
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCC_GTUS
VCCGTX for SKYLAKE-U 2+3e
Reserve for soldering
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (11/14)
CPU (11/14)
CPU (11/14)
LA-C621P
LA-C621P
LA-C621P
16 60Thursday, September 24, 2015
16 60Thursday, September 24, 2015
16 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
Vinafix.com
4
3
2
1
+1.2V_MEM+1.2V_MEM_CPUCLK
1 2
@
RC231 0_0402_5%
D D
C C
BSC PSC
1
2
BSC
1
2
CC256
@
1U_0402_6.3V6K
1
1
1
CC174
CC175
2
2
@
@
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
2
1
2
2
CC254
CC257
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
CC176
2
10U_0402_6.3V6M
1
2
CC255
@
1U_0402_6.3V6K
+1.0V_VCCST
1
CC177
2
10U_0402_6.3V6M
CC294
22U_0603_6.3V6M
PSC
1
2
CC195
1U_0402_6.3V6K
1
CC178
2
10U_0402_6.3V6M
1
2
CC295
22U_0603_6.3V6M
+1.0V_VCCSTG
CC179
1
2
VDDQ: 8.45A
10U_0402_6.3V6M
CC296
22U_0603_6.3V6M
BSC
1
CC199
2
@
1
2
DG0.9
CC297
1U_0402_6.3V6K
10U_0402_6.3V6M
+VCC_SFR_OC
+1.2V_MEM_CPUCLK
BSC
1
CC194
2
@
1U_0402_6.3V6K
1
2
CC288
1U_0402_6.3V6K
+1.2V_MEM
1.35V in DDR3L,
1.2V in LPDDR3 and DDR4
UC1N
CPU POWER 3 OF 4
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
SKL-U_BGA1356
+1.0V_VCCST
1
2
CC202
1U_0402_6.3V6K
SKL-U
PSC
D
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
+VCC_SA
G0.9
+1.0VS_VCCIO
AK28
VCCIO
AK30
VCCIO
AL30
VCCIO
AL42
VCCIO
AM28
VCCIO
AM30
VCCIO
AM42
VCCIO
AK23
VCCSA
AK25
VCCSA
G23
VCCSA
G25
VCCSA
G27
VCCSA
G28
VCCSA
J22
VCCSA
J23
VCCSA
J27
VCCSA
K23
VCCSA
K25
VCCSA
K27
VCCSA
K28
VCCSA
K30
VCCSA
14 OF 20
RC168 100_0402_1%
AM23
AM22
H21
H20
1 2
VCCIO_SENSE
VSSIO_SENSE
+VCC_SA
+1.0VS_VCCIO
12
RC166
100_0402_1%
VSA_SEN- <49>
VSA_SEN+ <49>
12
RC165
12
RC167
8/14 PWR request
100_0402_1%
VCCIO_SENSE <47>
VSSIO_SENSE <47>
100_0402_1%
12
CZ95 1U_0402_6.3V6K
SIO_SLP_S4#<11,17,32,45,54>
+5V_ALW
+1.0V_VCCST source
+1.0V_PRIM
UZ21
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
+1.0VS_VCCIO
SIO_SLP_S0#
SIO_SLP_S3#
PSC
AND
VOUT
1
1
2
2
CC182
CC181
@
@
1U_0402_6.3V6K
1
1
2
2
CC252
CC253
1U_0402_6.3V6K
+1.0V_VCCST_C
6
5
GND
INTEL PDG 1.0
1
1
2
2
CC185
CC186
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
CC250
CC251
1U_0402_6.3V6K
1U_0402_6.3V6K
S0 S0Ix S3
HIGH
HIGH
HIGH LOW LOW
LOW
HIGH
LOW
LOW
PJP27
12
PAD-OPEN1x1m
1 2
@
CZ78 0.1U_0201_10V6K
+1.0V_VCCST
BSCBSC
1
1
CC248
CC249
2
2
@
@
10U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0402_6.3V6M
B B
A A
+VCCPLL_OC source
SIO_SLP_S3#<11,17,32,48>
SIO_SLP_SUS#<8,11,18,32,41,46,47,48>
SIO_SLP_S4#<11,17,32,45,54>
5
UC14
TC7SH08FU_SSOP5~D
12
CZ113 1U_0402_6.3V6K
+5V_ALW
1 2
@
RZ120 0_0402_5%
+3.3V_ALW
1 2
@
CZ115 0.1U_0201_10V6K
5
1
P
B
4
O
2
A
G
3
+1.2V_MEM
1 2
RZ119 0_0603_5%@
UZ26
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4
VOUT
GND
+VCC_SFR_OC
6
5
1 2
@
CZ114 0.1U_0201_10V6K
CZ87 1U_0402_6.3V6K
SIO_SLP_S0#<11,33,47>
SIO_SLP_S3#<11,17,32,48>
TC7SH08FU_SSOP5~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+1.0V_VCCSTG source
UC13
RC320 0_0402_5%@
12
+5V_ALW
+3.3V_ALW
5
1
P
B
2
A
G
3
1 2
O
+1.0V_PRIM
4
UZ19
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6A
TR=12.5us@Vin=1.05V
2
+1.0V_VCCST+1.0V_VCCSTG
1 2
RC238 0_0603_5%@
pop option with UZ19
1 2
@
CZ82 0.1U_0201_10V6K
VOUT
GND
6
5
12
PJP32
PAD-OPEN1x1m
+1.0V_VCCSTG_C
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (12/14)
CPU (12/14)
CPU (12/14)
LA-C621P
LA-C621P
LA-C621P
17 60Thursday, September 24, 2015
17 60Thursday, September 24, 2015
17 60Thursday, September 24, 2015
1
1.0
1.0
1.0
5
Vinafix.com
+1.0V_PRIM
LC1
+1.0V_PRIM_CORE
+1.0V_MPHYAON
+1.0V_CLK6
+1.0V_DTS
+1.0V_CLK1
+1.0V_CLK3
+3.3V_1.8V_PGPPG
0/30: layout limit, change from 0603 to 0402
1
+3.3V_1.8V_PGPPA
+3.3V_PGPPD
+3.3V_PGPPE
1
CC310
2
0.1U_0402_25V6
22U_0603_6.3V6M
@
22U_0603_6.3V6M
@
CC279
CC280
1
1
2
2
8/26 vender suggest depop
5
+1.0V_MPHYGT
close UC1.AF20 and <400mil
8/26 vender suggest depop
1 2
RC194 0_0805_5%
@
Imax : 2.57A
D D
+1.8V_PRIM
C C
+3.3V_ALW_PCH
+1.8V_PRIM
+3.3V_ALW_PCH
B B
+3.3V_ALW_PCH +3.3V_VCCHDA
A A
1 2
@
RC299 0_0603_5%
1 2
@
RC300 0_0402_5%
1 2
@
RC301 0_0402_5%
1 2
@
RC302 0_0402_5%
1 2
@
RC303 0_0402_5%
1 2
@
RC234 0_0402_5%
1 2
@
RC235 0_0402_5%
1 2
@
RC211 0_0402_5%
1 2
@
RC212 0_0402_5%
1 2
@
RC307 0_0402_5%
1 2
@
RC308 0_0402_5%
1 2
BLM15HG601SN1D
1
CC215
2
@
1U_0402_6.3V6K
+3.3V_ALW +3.3V_ALW_DSW
1 2
@
RC214 0_0402_5%
+1.0V_MPHYAON
1
2
CC203
1U_0402_6.3V6K
close UC1.N15 and CC210 <400mil, CC211 <120mil
1
1
CC210
2
2
CC211
@
1U_0402_6.3V6K
47U_0805_6.3V6M
+1.0V_SRAM
1
2
close UC1.K15, UC1.L15 and <100mil
1 2
@
RC169 0_0603_5%
1
2
CC281
@
0.1U_0201_10V6K
+1.0V_PRIM
LC2
1 2
BLM15HG601SN1D
1
CC225
2
@
47U_0805_6.3V6M
+3.3V_ALW +1.8V_PRIM +1.0V_PRIM
1
CC271
2
47U_0805_6.3V6M
4
close UC1.AL1 and <120mil
1
2
CC204
1U_0402_6.3V6K
CC217
+1.0V_APLLEBB
@
1U_0402_6.3V6K
close UC1.N18 and <120mil
1
2
CC218
1U_0402_6.3V6K
+1.0V_AMPHYPLL+1.0V_MPHYGT
1
CC219
2
@
47U_0805_6.3V6M
+1.0V_VCCAPLL
+1.0V_PRIM_CORE
1
1
CC272
2
CC273
2
47U_0805_6.3V6M
47U_0805_6.3V6M
4
+1.0V_PRIM_CORE+1.0VO_DSW
+1.0V_PRIM
close UC1.K15 and <120mil
1
2
CC264
@
1
CC311
2
+1.0V_AMPHYPLL
+1.0V_VCCAPLL
+1.0V_PRIM
+3.3V_ALW_DSW
+3.3V_VCCHDA
+3.3V_SPI
+3.3V_ALW_PCH
1U_0402_6.3V6K
0.1U_0402_25V6
1
CC274
2
47U_0805_6.3V6M
close UC1.AB19 and <400milclose UC1.K17 and <120mil
+1.0V_PRIM
1
CC206
2
@
AB19
1U_0402_6.3V6K
AB20
AF18
AF19
AB17
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
AJ21
AK20
@
RC170 0_0402_5%
close UC1.K19 and <100mil
8/26 vender suggestion
UC1O
VCCPRIM_1P0
VCCPRIM_1P0
P18
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17
VCCHDA
VCCSPI
VCCSRAM_1P0
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
SKL-U_BGA1356
1 2
close UC1.N20 and <100mil
3
PCH PWR
CPU POWER 4 OF 4
+1.0V_CLK2+1.0V_PRIM
1
CC220
2
@
47U_0805_6.3V6M
SKL-U
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
15 OF 20
close UC1.L19 and <100mil
close UC1.AG15 and <120mil
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+3.3V_1.8V_PGPPA
+3.3V_PGPPD
+1.8V_PRIM
+3.3V_1.8V_PGPPG
+1.0V_DTS
+3.3V_ALW_PCH
close UC1.AK19 and <120mil
+DCPRTC
close UC1.BB10 and <120mil
+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5
CORE_VID0 <47>
CORE_VID1 <47>
Take care!!! Note1 on Page 19
1 2
@
RC171 0_0402_5%
2
close UC1.Y16 and <400mil
+3.3V_ALW_PCH
close UC1.AA1 and <400mil
1
2
+1.0V_CLK6
1
CC221
2
@
47U_0805_6.3V6M
+3.3V_ALW_PCH
+RTC_CELL
1
2
CC214
D
G0.9
0.1U_0201_10V6K
close UC1.A10 and <120mil
1
CC216
2
@
1U_0402_6.3V6K
+1.0V_MPHYGT source
+1.0V_CLK4+1.0V_PRIM
1 2
@
RC173 0_0402_5%
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
CC226
2
@
47U_0805_6.3V6M
SIO_SLP_SUS#<8,11,17,32,41,46,47,48>
MPHYP_PWR_EN<11>
11
/0 change power source
CZ84 1U_0402_6.3V6K@
+1.0V_PRIM
12
+5V_ALW
12
RZ82 0_0402_5%@
12
RZ83 0_0402_5%@
2
1
+1.0V_MPHYGT
1 2
@
+3.3V_ALW_PCH
1
2
CC212
1U_0402_6.3V6K
CC224
1U_0402_6.3V6K
VOUT
GND
RC309 0_0603_5%
1 2
@
RC310 0_0603_5%
close UC1.V19 and <120mil
CC209
@
1U_0402_6.3V6K
Pop PJP35 & Depop UZ20/RZ83/CZ84
1 2
PAD-OPEN1x3m
+1.0V_MPHYGT
6
5
1
2
@
CC270
0.1U_0201_10V6K
DG0.9
+3.3V_PGPPE
1
2
close UC1.T16 and <400mil
1
CC208
2
@
1U_0402_6.3V6K
+1.8V_PRIM
CC213
1U_0402_6.3V6K
+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM
1
CC223
2
0.1U_0201_10V6K
@
UZ20
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6A
TR=12.5us@Vin=1.05V
1
2
close UC1.AK17 and <120mil
1
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (13/14)
CPU (13/14)
CPU (13/14)
LA-C621P
LA-C621P
LA-C621P
1
+1.0V_SRAM
+1.0V_APLLEBB
PJP35
CZ85
0.1U_0201_10V6K
18 60Thursday, September 24, 2015
18 60Thursday, September 24, 2015
18 60Thursday, September 24, 2015
+1.0V_MPHYGT+1.0V_PRIM
1.0
1.0
1.0
Loading...