Dell Latitude 5480, Latitude 5488 Schematics

A

COMPAL CONFIDENTIAL

B

C

D

E

1 1

MODEL NAME :CDM70
PCB NO : LA-E082P
BOM P/N :

BR14 KBL-U DSC

Kabylake U

2 2

@ : Nopop Component

EMC@ : EMI, ESD and RF Component

CXDP@ : XDP Component

CONN@ : Connector Component

3 3

2016-11-07

REV : 1.0 (A00)

MB PCB

Part Number

DAA000CR000

Description

PCB 1SD LA-E082P REV0 MB DSC 1

Layout Dell logo

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

COPYRIGHT 2015

ALL RIGHT RESERVED
REV:X00
PWB: DKJP1

T

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

C

D

itle

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-E082P

LA-E082P

LA-E082P

1 75Monday, December 12, 2016

1 75Monday, December 12, 2016

1 75Monday, December 12, 2016

E

1.0

1.0

1.0

A

B

C

D

E

Breckenridge 14 DSC Block Diagram

Memory BUS (DDR4)

USB

2133 MHz
Up

to 2x8GB Modules

USB2.0[1]

USB POWER SHARE

HD Audio I/F

SATA/PCIE REPEATER

PS8558x2

SATA/PCIE MUX

SS3415

HD3

SLGC55544BVTR

USB3 Repeater

713B

PS8

dGPU
23X

23

E

DP CONN

HDMI 1.4
CON

N

DP TO VGA
RTD2166

M.2,3042 Key B

WWAN/LTE

USB3.0[2]

E 48~52

P29

P23

P24

P32

USB2.0[4]

P34

P34

2GB
DDR3L

PAGE 53~54 PAG

VGA
CONN

P24

PCIE[9]

Intel Jacksonville

WGI219LM

Transformer

RJ45

P33

P33

P33

1 1

2 2

PCIE[1]

Card reader
RTS5242

SD4.0

3 3

PCIE[5][6][7][ 8]

2-Lane eDP1.3

SW2_DP1

To Type C

SW2_DP2

To M2 WiGig card

SW2_DP3

To VGA

PCIE[4]

M.2,3030 Key A

WLAN+BT/WIGIG

SW2_DP2

Expander IO
IT8

DP DeMUX

PS8348B

PCIE[3]

P32

USB2.0[7]

010F N

P35

DDI[1]

DDI[2]

P22

INTEL

KABYLAKE_U MCP

PAGE 6~19

SPI

SATA[2] /PCIE[12][1 1]

W25Q128FVSI Q

P8

P8

reserve

P37

P45

35

P

ESPI

SMSC KBC
MEC5105

P34-3 5

128M 4K sector

W25Q128FVSI Q

128M 4K sector

TPM

2.0

ATTPM20P-G1MA1-ABF

KB/TP CONN

FAN CONN

Reverse Type

DDR4-SO-DIMM X2

BAN

P20~21

P43

P42

HDA Codec
ALC3246

P38

P39

K 0, 1, 2, 3

USB2.0[8]

USB2.0[5]

USB2.0[1]_PS

USB3.0USB3.0[1]

USB2.0[2]

USB3.0[3]

USB2.0[3]

USB3.0[4]

P33

LCD

Touch

P29

Camera

P29

USB3.0 Conn
PS(

Ext Port 1)

P43

USB3.0 Conn
(Ext Port 2)

USB3.0 Conn
(Ext Port 3)

INT.Speaker

Universal Jack

Dig.

MIC

P44

P44

P33

P33

P29

Trough eDP Cable

Trough eDP Cable

LID SWITCH

USH CONN

P47

P38

Non-AR Type C

P41

USB2.0[10]

M.2 2280

SSD Conn

P39

P40

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

DP1.2 4 lanes

TX/RX

USB 3.0 + AM
Type C CONN.

4 4

USB

CC

Vbus

2.0

HS Redriver Switch
TUSB546

P25

GPIO

PD Solut i on
TPS65982D

P26-2 7P28

SW2_DP1

USB3.0[6]

SMBUS

USB2.0[9]

Smart Card

TDA8034HN

RFID/NFC

Fingerprint
CONN

SPI

SPI

5V VR

Charger

A

B

C

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

E SECRET AND OTHER PR OPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

TRAD
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

SATA HDD

Conn

USH TPM1.2

M58102

BC

USH

board

CPU&PCH XDP Port

AUTOMATIC POWER
SWITCH(APS)

Free Fall sensor

Interface

DC/DC

POWER ON/OFF

SW & LED

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Block diagram

Block diagram

Block diagram

LA-E082P

LA-E082P

LA-E082P

E

2 75Monday, December 1 2, 2016

2 75Monday, December 1 2, 2016

2 75Monday, December 1 2, 2016

P14

P11

P41

P47

P46

1.0

1.0

1.0

5

POWER STATES

Signal

State

S0 (Full ON) / M0

S3 (Suspend to RAM) / M3 LOW

D D

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

SLP
S3#

HIGH

LOW

LOW

LOW LOW LOW

OW LOW LOW LOW

L

SLP

SLP

S5#

S4#

HIGH HIGH

HIGH HIGH

HIGH HIGH

LOW

LOW

LOW

HIGH HIGH

HIGH

ALWAYS

SLP

PLANE

A#

HIGH

ON

HIGH

ON ON ON

ON ON

HIGH

ON ON

ON ON

LOW

ON

ON

PM TABLE

+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW

power

C C

State

S0

S3

S5 S4/AC

S5 S4/AC doesn't exist

plane

+3.3V_ALW_PCH +1.2V_MEM

+RTC_CELL

1.8V_PRIM

+
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT

ON ON ON

ON

ON

+3.3V_CV2

+2.5V_MEM
+1.0V_VCCST

ON

OFF

OFFOFF

+5V_RUN

+3.3V_RUN

+0.6V_DDR_VTT

1.8V_RUN

+
+VCC_CORE

+VCC_GT

+VCC_SA
+1.0VS_VCCIO

4

M
PLANE

ON

OFF OFF OFF

OFF OFF OFF OFF

OFF OFF OFF OFF

OFF

OFF

OFF

RUN

SUS

PLANE

PLANE

ON ON ON

OFF

OFF

OFF

OFF

OFFLOW

CLOCKS

OFF

OF

F

OFF

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

U

SB3.0-5

USB3.0-6

SSIC

SSIC

3

PCIE

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

PCIE-9

PCIE-10

PCIE-11

PCIE-12

SATA

SATA-0

TA-1

SA

SATA-1*

SATA-2

ESTINATION

J

USB1-->Right

M.2 3042(LTE)

JUSB2-->Lef t

JUSB3-->Rear Lef t

Card Reader

Type-C Port

M.2 3030(WLAN)

M.2 3030(WIGIG)

Discrete Graphics x4

LOM

NA

NA

SATA HDD

M.2 2280 SSD

PCIex2 or SATA)

(

2

USB PORT#D

For Breckenridge14/15 DSC

DESTINATION

1

2

3

4

5

6

7

8

9

10

JUSB1-->Right

JU

SB2-->Lef t

JUSB3-->Rear Lef t

M

2 3042(WWAN)

Camera

NA

M.2 3030(BT)

Touch Screen

Type-C Port

USH

1

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

T

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

5

4

3

2

Title

ize Document Number Re v

Size Document Number Re v

Size Document Number Re v

S

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-E082P

LA-E082P

LA-E082P

1

3 75Monday, December 12, 2016

3 75Monday, December 12, 2016

3 75Monday, December 12, 2016

1.0

1.0

1.0

5

Barrel
ADAPTER

D D

CHARGER
ISL88

738

(PU801)

Type-C
ADAPTER

+PWR_SRC

BATTERY

C C

SY82

10A

(PU200)

SYX198D

(PU301)

SY82

88C

(PU102)

SYX196D

(PU800)

RT8813A

(PU701)

88B

SY82

(PU100)

4

IO_SLP_S4#

S

0.6V_DDR_VTT_ON

SIO_

SLP_SUS#

ALWO

DGPU_PWROK
GPU_GC6_FB_EN

3V3_MAIN_EN

ALWON

N

+1.2V_MEM

+0.6V_DDR_VTT

+1.0V_PRIM

+5V_ALW

+5V_ALW2

+1.35V_MEM_GFX

+GPU_CORE

+3.3V_RTC_LDO

+3.3V_ALW2

+3.3V_ALW

TPS22961

(UZ26)

3

SIO_SLP_SUS#
SIO_SLP_S4#

TPS62134C

(PU401)

TPS62134D

(PU402)

EM5209

(UZ4)

55544C

SLGC

(UI3)

SY62

88

(UI1)

SY6288

(UI2)

+VCC_SFR_OC

RUN_ ON

SIO_SLP_SUS#

RUN_ ON

USB_PW R_SHR_ EN#

USB_PWR_EN1#

USB_PWR_EN2#

2

TPS22961

(UZ19)

TPS22961

(UZ21)

EM5

(UV15)

+1.0VS_VCCIO

+1.0V_PRIM_CORE

+5V_RUN

+5V_USB_CHG_PWR

+USB_EX2_PWR

+USB_EX3_PWR

209VF

RUN_ ON

SLP_S0#

SIO_

SIO_SLP_S4#

3V3_MAIN_EN

LP2301

(QV8)

EM5209

(@UZ5)

+1.0V_VCCSTG

+1.0V

_VCCST

+1.0V_PEX_VDD

3.3V_TS_EN

AUD_PW R_EN

1

CPU PWR

PCH PWR

GT3 PWR

Peripheral Device PWR

TYPE-C Power

GPU PWR

+5V_TSP

+5V_RUN_AUDIO

SIO_SLP_SUS#

02KTTR

AP34

(PU501)

857

ISL95857

(PU602)

IMVP_VR_ON

B B

ISL95

(PU604)

IMVP_VR_ON

+VCC_GT+VCC_SA

ISL95857

(PU603)

IMVP_VR_ON

+VCC_CORE

AO6405

(QV1)

EN_IN VPWR

+BL_PWR_SRC

EM5209

(UZ2)

EM5209

(UZ3)

EM5209

(UZ4)

G524B1T11U
(UV24)

SIO_SLP_L AN#

AUX_EN_WOW L

@SIO_SLP_WLAN#

SIO_SLP_SUS#

@PCH_ALW _ON

RUN_ ON

3.3V_W WAN_EN

ENVCC_PCH

+3.3V_LAN

+3.3V_WLAN

+3.3V_ALW_PCH

+3.3V_RUN

+3.3V_WWAN

LCDVDD

+

TYPE-C

+TBTA_VBUS(5V~20V)

TPS22967

(UZ18)

AP7175SP

A A

AP2204

(UT8)

5

ALW

+5V_

+5V_TBT_VBUS

AP2112K

(UT7)

+3.3V_TBT_SX

4

(PU503)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

3

CV2_ON

SIO_SLP_S4#

+3.3V_CV2

+2.5V_MEM

for DDR4

USH/

2

AOZ13

36

(UZ8)

LP2301A

(QZ1)

EM5209

(@UZ5)

LP2301A

(QV1)

EM5209VF

(UV15)

B

ON

RUN_

3.3V_CAM_EN#

AUD_PW R_EN

DGPU_PWR_EN

3V3_MAIN_EN

+3.3V_CAM

+3.3V_RUN_AUDIO

+3.3V_GFX_AON

_RUN_GFX

+3.3V

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Power rails

Power rails

Power rails

LA-E082P

LA-E082P

LA-E082P

1

4 75Monday, December 12, 2016

4 75Monday, December 12, 2016

4 75Monday, December 12, 2016

1.0

1.0

1.0

5

4

3

2

1

PD &
FW reflash

2.2K

2.2K

+3.3V_RUN

202
200

202

200

DIMMA

DIMMB

53
51

1
4

XDP

LNG2DMTR

1

K

+3.3V_ALW_PCH

2.2K

2.2K

@2.2K

@2.2K

2.2K

2.2K

+3.3V_ALW_PCH

DMN66D0LDW-7
DMN66D0LDW-7

+3.3V_TP

+3.3V_ALW

+3.3V_ALW

DMN66D0LDW-7
DMN66D0LDW-7

28
31

LOM

UPD1_SMBC LK_Q
UPD1_SMBDAT_Q

DDR_XDP_WAN_SMBCLK
D

DR_XDP_ WAN_SMBDAT

2.2K

2.2K

2.2K

2.2K

9

TP

8

+3.3V_CV2

M9

USH

L9

USH/B

+3.3V_TBT_FLASH

B5
A5

R
R8

D D

SKL-U

R9

W3

SML1_SMBDATA

SML1_SMBCLK

03

W2

02
02

01
01

00 D7
00

V3

E11 D8

0

3

C C

KBC

04
04

MEM_SMBCLK

7

MEM_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

1K

+3.3V_ALW_PCH

DAT_TP_SIO_I2C_CLK
CLK_TP_SIO_I2C_DAT

USH_SMBCLK

USH_SMBDAT

UPD1_SMBCLK
UPD1_SMBDAT

C12
E

B3
E5

E7

C3
B4

1

K

10

1K

499

499

MEC 5105

F7

05

B6

05

A

12

B B

A A

5

06

N10

06

07

7

0

08

09

09

10
10

EXPANDER_GPU_SMCLK

M4

EXPANDER_GPU_SMDATA

M7

C508
C8

F6

E9

PBAT_CHARGER_SMBCLK

N2

3

M

PBAT_CHARGER_SMBDAT

2.2K

2.2K

2.2K
.2K

2

+3.3V_ALW

+3.3V_ALW

100 ohm

100 ohm

MN66D0LDW-7

D
DMN66D0LDW-7

1.8K

1.8K

+3.3V_RUN_GFX

GPU

EXPANDER

Charger

7

BATTERY

6

CONN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-E082P

LA-E082P

LA-E082P

1

5 75Monday, December 12, 2016

5 75Monday, December 12, 2016

5 75Monday, December 12, 2016

1.0

1.0

1.0

5

4

3

2

1

For 2LANE EDP,BR/SB12

+3.3V_RUN

CPU_DP1_CTRL_CLK

RC175 2.2K_0402_5%
RC178 2.2K_0402_5%

D D

RC176 2.2K_0402_5%
RC177 2.2K_0402_5%

C C

B B

12

CPU_DP1_CTRL_DATA

12

CPU_DP2_CTRL_CLK

12

CPU_DP2_CTRL_DATA

12

HDMI

PS8

338(AR)/

PS8348(NON AR)

+1.0VS_VCCIO

CPU_DP1_N0<23>
CPU_DP1_P0<23>
CPU_DP1_N1<23>
CPU_DP1_P1<23>
CPU_DP1_N2<23>
CPU_DP1_P2<23>
CPU_DP1_N3<23>
CPU_DP1_P3<23>

CPU_DP2_N0<22>
CPU_DP2_P0<22>
CPU_DP2_N1<22>
CPU_DP2_P1<22>
CPU_DP2_N2<22>
CPU_DP2_P2<22>
CPU_DP2_N3<22>
CPU_DP2_P3<22>

12

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

GPP_E23

EDP_COMP

CPU_DP1_CTRL_CLK<23>

CPU_DP1_CTRL_DATA<23>

CPU_DP2_CTRL_CLK<22>

CPU_DP2_CTRL_DATA<22>

@

T120

PAD~D

RC2 24.9_0402_1%

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils , Spacing=25mil,
Ma

x length=100 mils.

UC1A

CPU@

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL

-U_BGA1356

SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0

UC1I

CPU@

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL

-U_BGA1356

SKL-U

DDI

DISPLAY SIDEBANDS

SKL_U LT

EDP

1 OF 20

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

EDP_DISP_UTIL

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

DDI1_AUXN

DDI1_AUXP

DDI2_AUXN

DDI2_AUXP

DDI3_AUXN

DDI3_AUXP

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

CPU_DP1_AUXN

G50

CPU_DP1_AUXP

F50
E48
F48

CPU_DP3_AUXN

G46

CPU_DP3_AUXP

F46
L9

L7
L6
N9
L10

R12
R11
U13

CSI2_COMP
TBT_FORCE_PWR

EMMC_RCOMP

RC4 200_0402_1%

EDP_TXN0 <29>
EDP_TXP0 <29>
EDP_TXN1 <29>
EDP_TXP1 <29>

EDP_AUXN <29>
EDP_AUXP <29>

PAD~D
PAD~D

CPU_DP2_AUXN <22>

CPU_DP2_AUXP <22>

PAD~D
PAD~D

CPU_DP1_HPD <23>
CPU_DP2_HPD <22>

EDP_HPD <29>

PANEL_BKLEN <29>
EDP_BIA_PWM <29>
ENVDD_PCH <29,34>

1 2

RC3 100_0402_1%

1 2

PAD~D

@

T19

@

T281

@

T282

@

T1

@

T2

EDP_HPD

1 2

RC1 100K_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (1/14)

CPU (1/14)

CPU (1/14)

LA-E082P

LA-E082P

LA-E082P

6 75Monday, December 12, 2016

6 75Monday, December 12, 2016

6 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For DDR4

DDR_A_DQS#[0..7]<20>

2 OF 20

DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>

DDR_A_MA[0..16]<20>

DDR_A_CLK#0

AU53

DDR_A_CLK0

AT53

DDR_A_CLK#1

AU55

DDR_A_CLK1

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56

DDR_A_CKE2

AW56

DDR_A_CKE3

AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1 DDR_B_ODT0

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54

DDR_A_ACT#

BA55

DDR_A_BG1

AY54

DDR_A_MA13

AU46

DDR_A_MA15

AU48

DDR_A_MA14 DDR_B_MA15

AT46

DDR_A_MA16

AU50

DDR_A_BA0

AU52

DDR_A_MA2

AY51

DDR_A_BA1

AT48

DDR_A_MA10

AT50

DDR_A_MA1

BB50

DDR_A_MA0

AY50

DDR_A_MA3

BA50

DDR_A_MA4

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#4

BA64

DDR_A_DQS#5

AY60

DDR_A_DQS5

BA60

DDR_B_DQS#0

BA38

DDR_B_DQS0

AY38

DDR_B_DQS#1

AY34

DDR_B_DQS1

BA34

DDR_B_DQS#4

BA30

DDR_B_DQS4

AY30

DDR_B_DQS#5

AY26

DDR_B_DQS5

BA26

DDR_A_ALERT#

AW50

DDR_A_PARITY

AT52
AY67

+DDR_VREF_A_DQ

AY68
BA67

AW67

DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>

DDR_A_CKE0 <20>
DDR_A_CKE1 <20>

@

T3

PAD~D

@

T4

PAD~D

DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>

DDR_A_BG0 <20>

DDR_A_ACT# <20>
DDR_A_BG1 <20>

DDR_A_BA0 <20>
DDR_A_BA1 <20>

DDR0_PAR,DDR0_ALERT# for DDR4

DDR_A_ALERT# <20>

+DDR_VREF_CA

@

T132

PAD~D

+DDR_VREF_B_DQ

DDR_VTT_CTRL <20>

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26

DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]
DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SK

L-U_BGA1356

CPU@

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DRAM_RESET#
DDR_RCOMP[0]

DDR CH - B

DDR_RCOMP[1]
DDR_RCOMP[2]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR4, Ballout for side by side(Non-Interleave)

D D

UC1B

CPU@

DDR_A_D0

AL71

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42

C C

B B

DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SK

L-U_BGA1356

SKL-U

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

DDR0_ODT[1]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_ALERT#

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_ALERT#

DDR1_PAR

3 OF 20

DDR_B_DQS#[0..7]<21>

DDR_B_D[0..63]<21>
DDR_B_DQS[0..7]<21>

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70

AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

DDR_B_MA[0..16]<21>

DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT1
DDR_B_MA5

DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
DDR_B_ACT#
DDR_B_BG1

DDR_B_MA13
DDR_B_MA14

DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3

DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7

DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>

DDR_B_CKE0 <21>
DDR_B_CKE1 <21>

@

T5

PAD~D

@

T6

PAD~D

DDR_B_CS#0 <21>
DDR_B_CS#1 <21>
DDR_B_ODT0 <21>
DDR_B_ODT1 <21>

DDR_B_BG0 <21>

DDR_B_ACT# <21>
DDR_B_BG1 <21>

DDR_B_BA0 <21>
DDR_B_BA1 <21>

D

DR1_PAR,DDR1_ALERT# for DDR4

DDR_B_ALERT# <21>DDR_A_PARITY <20>
DDR_B_PARITY <21>
DDR_DRAMRST# <20>

DDR4 COMPENSATION SIGNALS

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

A A

1 2

RC5 121_0402_1%

1 2

RC6 80.6_0402_1%

1 2

RC7 100_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (2/14)

CPU (2/14)

CPU (2/14)

LA-E082P

LA-E082P

LA-E082P

7 75Monday, December 12, 2016

7 75Monday, December 12, 2016

7 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

SPI_MOSI= SPI_IO0
SP

I_MISO= SPI_IO1

PCH EDS R0.7 p.235~236

PCH_SPI_CLK
PCH_SPI_D1

1 2

PCH_SPI_DO_XDP<14>

D D

PCH_SPI_DO2_XDP<14>

RC10 1K_0402_1%CXDP@

1 2

RC11 1K_0402_1%CXDP@

+3.3V_RUN

+3.3V_1.8V_ESPI

PCH_SPI_CS#2<36>

PCH_CL_CLK1<32>
PCH_CL_DATA1<32>
PCH_CL_RST1#<32>

RC13 10K_0402_5%LPC@

SIO_RCIN#<34>

ESPI_ALERT#<34>

RC21 8.2K_0402_1%

PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2

12

12

AW3
AW2

AU4
AU3
AU2
AU1

AW13

AY11

AV2
AV3

M2
M3

J4
V1
V2

M1

G3
G2
G1

4

UC1E

CPU@

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#
GPP_A6/SERIRQ

SKL

-U_BGA1356

SKL-U

SMBUS, SMLINK

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

3

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

5 OF 20

R7
R8
R10

R9
W2
W1

W3
V3
AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#

SML0_SMBCLK
SML0_SMBDATA
GPP_C5

SML1_SMBCLK
SML1_SMBDATA
GPP_B23

ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R

ESPI_CLK
PCI_CLK_LPC1

SML0_SMBCLK <30>
SML0_SMBDATA <30>

SML1_SMBCLK <34>
SML1_SMBDATA <34>

1 2

RC366 15_0402_5%

1 2

RC367 15_0402_5%

1 2

RC368 15_0402_5%

1 2

RC369 15_0402_5%

ESPI_CS# <34,35>
ESPI_RESET# <34>

1 2

RC16EMI@ 15_0402_5%

1 2

CLKRUN# <34>

RC22@ 22_0402_5%

2

MEM_SMBCLK

MEM_SMBDATA

ESPI_IO0 <34,35>
ESPI_IO1 <34,35>
ESPI_IO2 <34,35>
ESPI_IO3 <34,35>

+3.3V_RUN

6

5

DMN65D8LDW-7_SOT363-6

3 4

QC2B

DMN65D8LDW-7_SOT363-6

ESPI_CLK_5105 <34,35>

Fo

2

1

DDR_XDP_WAN_SMBCLK <14,20,21,41>

QC2A

DDR_XDP_WAN_SMBDAT <14,20,21,41>

DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK

MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA

1

r BR/SB

1 2

RC318 2.2K_0402_5%

1 2

RC319 2.2K_0402_5%

1 2

RC12 1K_0402_5%

1 2

RC14 1K_0402_5%

1 2

RC15 1K_0402_5%

1 2

RC17 1K_0402_5%

1 2

RC347 499_0402_1%

1 2

RC348 499_0402_1%

+3.3V_RUN

+3.3V_ALW_PCH

C C

SOFTWARE TAA

PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R

33_0402_5%

@EMI@

12

RC28

33P_0402_50V8J

@EMI@

12

CC7

B B

A A

33_0402_5%

@EMI@

12

RC29

33P_0402_50V8J

@EMI@

12

CC8

+3.3V_SPI

RC31 1K_0402_5%@

RC316 1K_0402_5%@

03/02:follow Intel MOW_2015WW06

PCH_SPI_D2_R1

12

PCH_SPI_D3_R1

12

PCH_SPI_D1_R1<36>

PCH_SPI_D0_R1<36>

PCH_SPI_CLK_R1<36>

12

PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R

@

1 2

RC37 0_0402_5%

1 2

RC39 33_0402_5%

PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R

1

/CS

2

IO1

3

IO2

4

GND

W25Q128FVSIQ_SO8

PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1

PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1

8Mb Flash ROM

UC5

VCC
CLK

IO3
IO0

8
7
6
5

128Mb Flash ROM

UC6

PCH_SPI_CS#1_R1
PCH_SPI_D2_R1

RC42 0_0402_5%@
RC43 33_0402_5%@

1 2
1 2

PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R

@

1

/CS

2

IO1

3

IO2

4

GND

W25Q128FVSIQ_SO8

VCC
CLK

8
7

IO3

6
5

IO0

1 8
2 7
3 6
4 5

1 2

RC407 33_0402_5%@

1 2

RC408 33_0402_5%@

1 2

RC409 33_0402_5%@

1 2

RC410 33_0402_5%@

+3.3V_SPI

PCH_SPI_D3_0_R
PCH_SPI_D0_0_R

+3.3V_SPI

PCH_SPI_D3_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R

RPC1

CC9

1 2

0.1U_0201_10V6K

CC10

@

1 2

0.1U_0201_10V6K

PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R

PCH_SPI_D3_1_RPCH_SPI_D3_R1
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R

+3.3V_SPI

ESPI_CLK_5105

SML0_SMBCLK

SML1_SMBCLK

RC32 0_0402_5%

@

+3.3V_ALW_PCH

12
12
12
12
12
12
12

@

RC330_0402_5%

@

RC340_0402_5%

@

RC350_0402_5%

@

RC360_0402_5%

@

RC380_0402_5%

@

RC400_0402_5%

12

RC410_0402_5%

PCH_SPI_CS#1_R1

PCH_SPI_CS#1

PCH_SPI_D0_R1

PCH_SPI_D0

PCH_SPI_D1_R1

PCH_SPI_D1

PCH_SPI_CLK_R1

PCH_SPI_CLK

PCH_SPI_CS#0_R1

PCH_SPI_CS#0

PCH_SPI_D2_R1

PCH_SPI_D2

PCH_SPI_D3_R1

PCH_SPI_D3

@

RF Request

1 2

CC316@RF@ 33P_0402_50V8J

1 2

CC318@RF@ 33P_0402_50V8J

1 2

CC319@RF@

CC320@RF@ 33P_0402_50V8J

Place close CPU side

JSPI1

22

GND2

21

GND1

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E-T_6705K-Y20N-00L

CONN@

SML0_SMBCLK
SML0_SMBDATA

CLKRUN#

PCH_SMB_ALERT#

TLS C ONFIDENTIALITY

HIGH
LOW(DEFAULT)

WEAK INTERNAL 20K PD

GPP_C5

EC interface

HIGH

W(DEFAULT)

LO

WEAK INTERNAL 20k PD

GPP_B23

RC317 150K_0402_5%

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

WEAK INTERNAL PD

1 2

RC19 499_0402_1%@

1 2

RC20 499_0402_1%@

1 2

RC27 8.2K_0402_5%LPC@

1 2

RC23 2.2K_0402_5%

ENABLE
DISAB LE

1 2

RC25 4.7K_0402_5%ESPI@

ESPI

LPC

1 2

ENABLED
DI

+3.3V_LAN

+3.3V_RUN

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW_PCH

ABLE D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (3/14)

CPU (3/14)

CPU (3/14)

LA-E082P

LA-E082P

LA-E082P

8 75Monday, December 12, 2016

8 75Monday, December 12, 2016

8 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For BR DSC

UC1F

+3.3V_RUN

AN8
AP7
AP8
AR7

AM5
AN7
AP5
AN5

AB1
AB2

AB3
AD1

AD2
AD3
AD4

AH9

AH10
AH11

AH12
AF11

AF12

W4

U7
U6

U8
U9

Reserve

MEDIACARD_IRQ#<31>

HDD_FALL_INT<41>

SIO_EXT_SCI#<34>

I2C1_SDA_TP<45>
I2C1_SCK_TP<45>

+3.3V_RUN

10K_0402_5%

TPM_PIRQ#<36>

3.3V_TS_EN<29>

RC405 100K_0402_5%@

SBIOS_TX<35>

RC267@

HDD_FALL_INT

D D

C C

RC370 10K_0402_5%
RC282 100K_0402_5%

RC237 10K_0402_5%
RC402 49.9K_0402_1%@
RC403 49.9K_0402_1%@

+3.3V_ALW_PCH

RC283 10K_0402_5%
RC330 49.9K_0402_1%
RC331 49.9K_0402_1%

+3.3V_RUN

RC186 4.7K_0402_5%@

12
12

12
12
12

12
12
12

12

3.3V_TS_EN

SIO_EXT_SCI#

NRB_BIT

LPSS_UART2_RXD
LPSS_UART2_TXD

SIO_EXT_WAKE#
LPSS_UART2_RXD
LPSS_UART2_TXD

ONE_DIMM#
NRB_BIT
HDD_FALL_INT

BBS_BIT6
GPP_C8

12

LPSS_UART2_RXD
LPSS_UART2_TXD

CPU@

LPSS ISH

GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

SK

L-U_BGA1356

NO REBOOT STRAP

H

IGH

LOW(DEFAULT)

Internal 20k PD

B B

+3.3V_ALW_PCH

RC184 8.2K_0402_5%@

No REBOOT

REBOOT ENABLE

BBS_BIT6

12

1 2

10K_0402_5%

12

DIMM Detect

HIGH

OW

L

ONE_DIMM#

RC268

1 DIMM
2 DIMM

LPSS_UART2_TXD
LPSS_UART2_RXD

BOOT BIOS Dest i nat i on (Bi t 6)

HIGH
LOW(DEFAULT)

Internal 20k PD

LPC
S

PI

SKL-U

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

CONN@

JUART1

1

1

2

2

3

3

4

4

5

GND

6

GND

CVILU_CI1804M1VRA-NH

CI1804M1VRA-NH LINK DON

+3.3V_ALW_PCH

MEM_INTERLEAVED

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/BM_BUSY#/ISH_GP6

RC371

@

10K_0402_5%

1 2

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

6 OF 20

E

MEM_INTERLEAVED

P2
P3

AR_DET#

P4
P1

M4
N3

N1
N2

ISH_I2C2_SDA

AD11

ISH_I2C2_SCL

AD12

U1
U2
U3
U4

AC1

RTD3_CIO_PWR_EN

AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

DGPU_HOLD_RST# <48>
DGPU_PWR_EN <52>

ISH_I2C2_SDA <32>
ISH_I2C2_SCL <32>

9/24: Reserve for embedded locat i on ,r ef er I nt el PDG

ISH_UART0_RXD <32>

ISH_UART0_TXD <32>
ISH_UART0_RTS# <32>

ISH_UART0_CTS# <32>

SIO_EXT_WAKE# <34>

@

PAD~D

HDD_EN

CLKDET#

TPM_TYPE
LID_CL#_PCH

LCD_CBL_DET# <29>

HDD_EN <41>

@

T258

PAD~D

PAD~D

WWAN

T18

@

T268

GPP_A GROUP is +1.8V

+3.3V_ALW_PCH

RC400
10K_0402_5%

1 2

AR_DET#

WLAN

0. 9

Reserved

ISH_I2C2_SDA
ISH_I2C2_SCL

LCD_CBL_DET#
DGPU_PWR_EN

DGPU_PWR_EN

TPM_TYPE

1 2

RC363 1K_0402_5%

1 2

RC362 1K_0402_5%

1 2

RC287 100K_0402_5%

1 2

RC386 10K_0402_5%

1 2

RC385 10K_0402_5%@

1 2

RC349 100_0402_1%@

+1.8V_RUN

+3.3V_RUN

12

10K_0402_5%
RC372

A A

DIMM TYPE

HIGH

LOW

Interleave

Non-Interleave

12

10K_0402_5%
RC401

@

AR_DET#

H

IGH NON AR

LOW A

R

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (4/14)

CPU (4/14)

CPU (4/14)

LA-E082P

LA-E082P

LA-E082P

9 75Monday, December 12, 2016

9 75Monday, December 12, 2016

9 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For Non AR,Breckenridge 14/15 DSC

UC1H

CPU@

PCIE/US B3/SATA

D D

Card Reader RTS5242----->

Type-C Port ----->

M.2 3030(WLAN) --->

M.2 3030(WiGig) --->

PEG_CTX_C_GRX_N1
PEG_CTX_C_GRX_P1

Discrete Graphics--->

C C

/100/1G LAN --->

10

PEG_CTX_C_GRX_N2
PEG_CTX_C_GRX_P2

PEG_CTX_C_GRX_N3
PEG_CTX_C_GRX_P3

M2 2280 SSD --->

B B

PEG_CRX_GTX_P[0..3]<48>
PEG_CRX_GTX_N[0..3]<48>

PEG_CTX_C_GRX_P[0..3]<48>
PEG_CTX_C_GRX_N[0..3]<48>

PCIE_PRX_DTX_N1<31>
PCIE_PRX_DTX_P1<31>
PCIE_PTX_DRX_N1<31>
PCIE_PTX_DRX_P1<31>

USB3_PRX_DTX_N6<25>
USB3_PRX_DTX_P6<25>
USB3_PTX_DRX_N6<25>
USB3_PTX_DRX_P6<25>

PCIE_PRX_DTX_N3<32>
PCIE_PRX_DTX_P3<32>
PCIE_PTX_DRX_N3<32>
PCIE_PTX_DRX_P3<32>

PCIE_PRX_DTX_N4<32>
PCIE_PRX_DTX_P4<32>
PCIE_PTX_DRX_N4<32>
PCIE_PTX_DRX_P4<32>

1 2

CC34 0.22U_0402_16V7K

1 2

CC35 0.22U_0402_16V7K

1 2

CC36 0.22U_0402_16V7K

1 2

CC37 0.22U_0402_16V7K

1 2

CC38 0.22U_0402_16V7K

1 2

CC39 0.22U_0402_16V7K

1 2

CC40 0.22U_0402_16V7K

1 2

CC41 0.22U_0402_16V7K

PCIE_PRX_DTX_N9<30>
PCIE_PRX_DTX_P9<30>

1 2

RC45 100_0402_1%

CPU_XDP_PRDY#<14>

CPU_XDP_PREQ#<14>

PCIE_PRX_DTX_N11<38>
PCIE_PRX_DTX_P11<38>
PCIE_PTX_DRX_N11<38>
PCIE_PTX_DRX_P11<38>
PCIE_PRX_DTX_N12<38>
PCIE_PRX_DTX_P12<38>
PCIE_PTX_DRX_N12<38>
PCIE_PTX_DRX_P12<38>

PEG_CRX_GTX_P[0..3]

PEG_CRX_GTX_N[0..3]

PEG_CTX_C_GRX_P[0..3]
PEG_CTX_C_GRX_N[0..3]

PEG_CRX_GTX_N0
PEG_CRX_GTX_P0
PEG_CTX_GRX_N0PEG_CTX_C_GRX_N0
PEG_CTX_GRX_P0PEG_CTX_C_GRX_P0

PEG_CRX_GTX_N1
PEG_CRX_GTX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1

PEG_CRX_GTX_N2
PEG_CRX_GTX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2

PEG_CRX_GTX_N3
PEG_CRX_GTX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3

PCIE_RCOMPN
PCIE_RCOMPP

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN
PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL

-U_BGA1356

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN
USB3_1_RXP

USB3_1_TXN
USB3_1_TXP

USB3_4_RXN
USB3_4_RXP

USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1

AH7
AH8

AG3

USB2_VBUSSENSE

AG4
A9

C9
D9

USB_OC3#

B9
J1

J2
J3

H2

SATAGP0

H3

SATAGP1
M2280_PCIE_SATA#

G4
H1

SATALED#

USB2_ID

USB3_PRX_DTX_N1 <42>
USB3_PRX_DTX_P1 <42>
USB3_PTX_DRX_N1 <42>

USB3_PTX_DRX_P1 <42>

USB3_PRX_DTX_N2 <32>
USB3_PRX_DTX_P2 <32>
USB3_PTX_DRX_N2 <32>

USB3_PTX_DRX_P2 <32>

USB3_PRX_DTX_N3 <44>
USB3_PRX_DTX_P3 <44>
USB3_PTX_DRX_N3 <44>

USB3_PTX_DRX_P3 <44>

USB3_PRX_DTX_N4 <44>
USB3_PRX_DTX_P4 <44>
USB3_PTX_DRX_N4 <44>

USB3_PTX_DRX_P4 <44>

USB20_N1 <43>
USB20_P1 <43>

USB20_N2 <44>
USB20_P2 <44>

USB20_N3 <44>
USB20_P3 <44>

USB20_N4 <32>
USB20_P4 <32>

USB20_N5 <29>
USB20_P5 <29>

USB20_N7 <32>
USB20_P7 <32>

USB20_N8 <29>
USB20_P8 <29>

USB20_N9 <26>
USB20_P9 <26>

USB20_N10 <37>
USB20_P10 <37>

USB2_ID <26>

1 2

RC338 1K_0402_5%

USB_OC0# <43>
USB_OC1# <44>
USB_OC2# <44>

Reserve

M2280_DEVSLP <40,41>

M2280_PCIE_SATA# <38,39>

SATALED# <32,40,46>

-----> Ext USB3 Port 1 Charge

-----> M.2 3042(LTE)

-----> Ext USB3 Port 2

-----> Ext USB3 Port 3

--

---> Ext USB Port 1 Charge(RIGHT)

-----> Ext USB Port 2(LEFT)

-----> Ext USB Port 3(REAR LEFT)

-----> M2 3042(WWAN)

-----> Camera

-----> M.2 3030(BT)

-----> LCD Touch

-----> Typce-C(Non AR)

USB2_ID

@

-----> USH

SATAGP1

RC337 0_0402_5%

RC416 1K_0402_5%

USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#

M2280_PCIE_SATA#
SATAGP0

SATALED#
SATAGP1

1 2

1 2

10K_8P4R_5%

1
2
3
4 5

4 5
3
2
1

10K_8P4R_5%

2

RPC3

RPC4

1K_0402_5%

+3.3V_ALW_PCH

8
7
6

6
7
8

+3.3V_RUN

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (5/14)

CPU (5/14)

CPU (5/14)

LA-E082P

LA-E082P

LA-E082P

10 75Monday, December 12, 2016

10 75Monday, December 12, 2016

10 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For BR DSC

1 2

RC417 3 3_0402_5%
1M_0402_1%

UC1J

CPU@

CLK_PCIE_N0<48>

D D

GPU--->

WLAN--->

WIGIG--->

M.2 SDD--->

N--->

LA

Card Reader --->

C C

B B

CLK_PCIE_P0<48>

CLKREQ_PCIE#0<48>

+3.3V_RUN

CLK_PCIE_N1<32>
CLK_PCIE_P1<32>

CLKREQ_PCIE#1<32>

+3.3V_RUN

CLK_PCIE_N2<32>
CLK_PCIE_P2<32>

CLKREQ_PCIE#2<32>

+3.3V_RUN

CLK_PCIE_N3<40>
CLK_PCIE_P3<40>

CLKREQ_PCIE#3<40>

+3.3V_RUN

CLK_PCIE_N4<30>
CLK_PCIE_P4<30>

CLKREQ_PCIE#4<30>

+3.3V_RUN

CLK_PCIE_N5<31>
CLK_PCIE_P5<31>

CLKREQ_PCIE#5<31>

+3.3V_RUN

+3.3V_LAN

+3.3V_ALW_DSW

+1.0V_VCCST

+3.3V_ALW_PCH

10/6 depop, prevent singal step.

H_CPUPW RGD VCCST_PWRGD

100P_0402_50V8J

12

CC300ESD@

RC215

POP
DE-POP

PCH_DPW ROK PCH_RS MRST#_AND

0.01UF_0402_25V7K

12

1

@

CC266

2

RC189 10K_0402_5%

RC47 10K _0402_5%

RC50 10K _0402_5%

RC59 10K _0402_5%

RC51 10K _0402_5%

RC190 10K_0402_5%

RL70 10K_0402_5%@

RC323 10 K_0402_5%

RC67 1K_0402_5%

RC71 1K_0402_5%

RC74 10K_0402_5%@

2

RC411 10K_040 2_5%@

@

T9

PAD~D

100P_0402_50V8J

12

CC301ESD@

ESD Request:place near CPU side

NO Support Deep sleep
Support Deep sleep

1 2

RC215 0_0402_5%@

100K_0402_1%

RC220

LAN_WAKE#

12

12

PCH_PCIE_ WAKE#

12

VCCST_PW RGD

12

ME_SUS_PWR_ACK

12

VCCST_PWRGD<14,34,35>

12

12

RC3730_0402_5%

12

12

RC3740_0402_5%

12

12

RC3750_0402_5%

12

12

RC3760_0402_5%

12

12

RC3770_0402_5%

12

12

RC3780_0402_5%

12

PCH_RSMRST#_AND<14,45>

RC75
10K_040 2_5%

CLKREQ_P CIE#0_R

@RF@

CLKREQ_P CIE#1_R

@RF@

CLKREQ_P CIE#2_R

@RF@

CLKREQ_P CIE#3_R

@RF@

CLKREQ_P CIE#4_R

@RF@

CLKREQ_P CIE#5_R

@RF@

PCH_PLTRST#

TC7SH08FU_S SOP5~D

1 2

RC77 1K_0402_5%@

1 2

RC78 60.4 _0402_1%

SYS_PWROK<14,34>
PCH_PWROK<63>

PCH_DPWROK<35>

ME_SUS_PWR_ACK<34>

SUSACK#<34>

PCH_PCIE_WAKE#<34,35>

LAN_WAKE#<30,34>

PM_LANPHY_ENABLE<30>

3.3V_CAM_EN#<29>

RC311 10K_0 402_5%

XDP_DBRESET#<14>

+3.3V_RUN

RC225@ 8.2K_0402_5%
RC227@ 8.2K_0402_5%

PCH_RSMRST#_AND

D42

CLKOUT_PCIE _N0

C42

CLKOUT_PCIE _P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE _N1

A42

CLKOUT_PCIE _P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE _N2

C41

CLKOUT_PCIE _P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE _N3

C40

CLKOUT_PCIE _P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE _N4

A40

CLKOUT_PCIE _P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE _N5

E38

CLKOUT_PCIE _P5

AU7

GPP_B10 /SRCCLKREQ5#

SKL

@

1 2

RC62 0_0 402_5%

@

1 2

RC244 0_0402_5%

@

1 2

RC406 0_0402_5%

+3.3V_ALW_PCH

5

1

P

B

4

O

2

A

G

UC7

3

PCH_PLTRST#

AN10

SYS_RESET#

H_CPUPW RGDH_CPUPW RGD_R
VCCST_PW RGD_CPU

12

XDP_DBRESET#

GPP_B13 /PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PW RGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PW ROK

AR13

GPP_A13 /SUSWARN#/SUSPWRDNACK

AP11

GPP_A15 /SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LA NPHYPC

AT15

GPD7/RSVD

SKL

12
12

-U_BGA1356

PCH_PLTRST#_AND

12

RC65

@

100K_04 02_5%

UC1K

CPU@

-U_BGA1356

@

RC290 0_0402_5%

ME_RESET#

SKL_ ULT

CLOCK SIGNALS

PLTRST_LAN# <30>
PCH_PLTRST#_EC <35>
PLTRST_GPU# <48>

PCH_PLTRST#_AND <31,32,37,40>

SYSTEM POWER MANAGEMENT

1 2

+3.3V_RUN

5

1

P

B

4

O

2

A

G

UC12@

74AHC1G0 9GW_TSSOP 5

3

SKL-U

SYS_RESET#_R

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIA SREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

10 OF 20

PCH_PLTRST#

PCH_PLTRST#_ AND

GPP_B12 /SLP_S0#

GPD4/SLP _S3#
GPD5/SLP _S4#

GPD10/SL P_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP _WLAN#

GPD6/SLP _A#

GPD3/PW RBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11 /PME#

INTRUDER#

GPP_B11 /EXT_PWR_G ATE#

GPP_B2/VRALERT#

11 OF 20

1 2

RC224 1K_0402_5%

CLK_ITPXDP _N

F43

CLK_ITPXDP _P

E43
BA17

SUSCLK
XTAL24_IN

E37

XTAL24_OUT

E35

XCLK_BIA SREF

E42

PCH_RTCX1

AM18

PCH_RTCX2

AM20
AN18

SRTCRST#

AM16

PCH_RTCRST# <34>

PCH_RTCRST#

CMOS1 must take care short & touch risk on layout placement

RC60 0_0 402_5%@

@

RC325 0_0402_5%

SIO_SLP_S0#

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15

PCH_BATLOW#

AU13

AU11

PME#

AP16

INTRUDER#
MPHYP_PW R_EN

AM10
AM11

VRALERT#

+3.3V_RUN

@

RC291

10K_0402_5%

1 2

SYS_RESET#

1 2

RC297 0_0402_5%@

1 2

RC298 0_0402_5%@

SUSCLK <32,40>

1 2

RC52 2.7K_0402_ 1%

1 2

RC324 59 _0402_1%@

546765_546765_2014WW48_Skylake_MOW_Rev_ 1_0

1 2

RC56 20K _0402_5%

1 2

CC24 1U_0402_6 .3V6K

1 2

RC57 20K _0402_5%

1 2

CC25 1U_0402_6 .3V6K

1

1

2

SHORT PADS~D

@

CMOS1

1 2

1 2

SIO_SLP_S0# <17,36,61>
SIO_SLP_S3# <34,35>
SIO_SLP_S4# <17,34,59,62>
SIO_SLP_S5# <34>

SIO_SLP_SUS# <17,34,47,60,61,62>
SIO_SLP_LAN# <34,47>

SIO_SLP_WLAN# <34,47>
SIO_SLP_A# <34>

SIO_PWRBTN# <14,34>

AC_PRESENT <34>

@

T115

PAD~D

connect to VCCMPHYGTAON_1P0 enable pin

CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>

+1.0V_CLK5

For

Skylake, pop RC52,depop RC324

For Cannonlake, pop RC324,depop RC52

2

PLTRST_TPM# <36>

+RTC_CELL

XTAL24_IN
XTAL24_OUT

PCH_RTCX1
PCH_RTCX2

SYS_RESET#

0.1U_0402_25V6

12

ESD Request:place near CPU side

RC46

1 2

1 2

RC295 33 _0402_5%

546765_546765_2014WW48_Skylake_MOW_Rev_ 1_0

1 2

@

RC296 0_0402_5%

8/21 can change to 10K for merge to RP

PCH_BATLOW#
AC_PRESE NT

INTRUDER#

MPHYP_PW R_EN

VRALERT#

SIO_SLP_LAN#

SUSCLK

+3.3V_ALW_PCH

+3.3V_ALW

+3.3V_ALW

@ESD@

CC302

For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)

RC54
10M_0402_5%

1 2

POWER_SW#_MB<35,46>

XTAL24_IN_R

3

4

1

2

XTAL24_OUT_R

12

PCH_RTCX2_R

1 2

RC72 8.2K _0402_5%

1 2

RC243 10K_0402_5 %

1 2

RC69 1M_0 402_5%

1 2

RC387 10K_0402_5 %@

1 2

RC73 10K_0402_5%@

1 2

RC344 10K_0402_5 %@

1 2

RC68 10K_0402_5%@

1 2

RC48 1K_0402_5%@

SIO_SLP_S3#
SIO_SLP_S5#

SIO_SLP_S4#
SIO_SLP_A#

PCH_RTCRST#

SYS_RESET#
SIO_SLP_S0#

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

CC21

1 2

15P_040 2_50V8J

YC1
24MHZ_12PF_X3G0240 00DC1H

CC22

1 2

15P_040 2_50V8J

CC23

1 2

12P_040 2_50V8J

YC2

32.768K HZ_12.5PF_9H03200042

ESR MAX=50k ohm

CC26

1 2

12P_040 2_50V8J

+3.3V_ALW_DSW

+RTC_CELL

+3.3V_ALW_PCH

+3.3V_ALW

JAPS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

GND

20

GND

CONN@

ACES_50506-01841-P01

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (6/14)

CPU (6/14)

CPU (6/14)

Document Number Re v

Document Number Re v

Document Number Re v

LA-E082P

LA-E082P

LA-E082P

1

11 75Monday, December 12, 2016

11 75Monday, December 12, 2016

11 75Monday, December 12, 2016

1.0

1.0

1.0

5

4

3

2

+1.0V_VCCSTG

1

PCH_JTAG_TDI
PCH_JTAG_TDO

D D

+1.0V_VCCST

RC79 49.9_0402_1%@

RC80 1K_0402_5%

+1.0V_VCCSTG

RC83 1K_0402_5%

+3.3V_RUN

RC414 10K_0402_5%
RC413 10K_0402_5%

C C

B B

RC278 10K_0402_5%
RC272 10K_0402_5%@
RC279 10K_0402_5%
RC345 100K_0402_5%
RC292 10K_0402_5%
RC404 10K_0402_5%

+3.3V_ALW_PCH

RC346 10K_0402_5%

RC288

H_CATERR#

12

H_THERMTRIP#

12

H_PROCHOT#

12

TOUCHPAD_INTR#

12

CAM_MIC_CBL_DET#

12

CONTACTLESS_DET#

12

TOUCH_SCREEN_PD#

12

AUD_PWR_EN

12

IR_CAM_DET#

12

HOST_SD_WP#

12

FFS_INT2

12

SIO_EXT_SMI#

12

12

HDA_SYNC_R<33>

HDA_BIT_CLK_R<33>

HDA_SDOUT_R<33>

HDA_RST#_R<33>

RF@

47P_0402_50V8J

Close to RC93

CH_SCREEN_PD# don't move to RPC,

TOU

ME_FWP

HDA_BIT_CLK_R

1

CC27

2

PECI_EC<34>

H_PROCHOT#<34,63,66>

H_THERMTRIP#<20,21,35>

1 2

RC93 33_0402_5%EMI@

1 2

RC94 33_0402_5%

1 2

RC223 1K_0402_5%

1 2

RC95 33_0402_5%

RC84 499_0402_1%

XDP_OBS0_R<14>

XDP_OBS1_R<14>

T10
T11

TOUCH_SCREEN_PD#<29>
TOUCHPAD_INTR#<34,45>

TOUCH_SCREEN_DET#<29>

12

FFS_INT2<41>

IR_CAM_DET#<29>

HDD_DET#<39,41>

DGPU_PWROK<35,52,68>

1 2

@

PAD~D

@

PAD~D

SIO_EXT_SMI#<34>

12

RC88

49.9_0402_1%

KB_DET#<45>

SPKR<33>

RC89

HDA_BIT_CLK
HDA_SDOUT

HDA_SDIN0<33>

HDA_RST#

H_PROCHOT#_R
H_THERMTRIP#

XDP_OBS2_R
XDP_OBS3_R

TOUCHPAD_INTR#

CPU_POPIRCOMP
PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

EOPIO_RCOMP

12

12

RC90

49.9_0402_1%

49.9_0402_1%

FFS_INT2

IR_CAM_DET#

KB_DET#

H_CATERR#

RC91

49.9_0402_1%

AY22
BB22
BA21
AY21

AW22

AY20

AW20

AK10

AW5

D63
A54
C65
C63
A65

C55
D55
B54
C56

A6

A7
BA5
AY5

AT16

AU16

H66
H65

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1
GPP_B14/SPKR

U_BGA1356

UC1D

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

SKL-

U_BGA1356

RF Request. Place near CPU side (Intel MOW)

1

2

HDA_RST#

CC331

2.2P_0402_50V8C

@RF@

+3.3V_ALW_PCH +3.3V_ALW_PCH

HDA_SDOUT

12

ENABLE
DISAB LE

SPKR

5

RC183 8.2K_0402_5%@

TOP SWAP STRAP

A A

HIGH
LOW(DEFAULT)

Inte

rnal 20k PD

RC187 4.7K_0402_5%@

Flash Descriptor Security override

HIGH
LOW(DEFAULT)

12

DISABLE

ENABLE

4

CPU@

CPU MISC

SKL-U

JTAG

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

HDA_SDIN0

1

2

CC332

2.2P_0402_50V8C

@RF@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B61

PROC_TCK

D60

PROC_TDI

A61

PROC_TDO

C60

PROC_TMS

B59
B56

D59
A56
C59
C61

PCH_TRST#

A59

JTAGX

4 OF 20

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

HDA_SDOUT

1

2

CC333

2.2P_0402_50V8C

@RF@

3

CPU_XDP_TCLK XDP_JTAGX

CPU_XDP_TCLK
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TMS
CPU_XDP_TRST#

PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
CPU_XDP_TRST#
XDP_JTAGX

RC87 1K_0402_5%@

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

1 2

GPP_F23

7 OF 20SKL-

CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>

PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>

AB11

GC6_EVENT#

AB13
AB12

GPU_GC6_FB_EN

W12

CONTACTLESS_DET#

W11
W10

AUD_PWR_EN

W8
W7

BA9
BB9

SD_RCOMP

AB7

AF13

12

RC3280_0402_5%

+1.0V_VCCSTG

1 2

RC96 200_0402_1%

PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX

0.1U_0402_25V6

@ESD@

12

CC303

@

1 2

RC86 51_0402_5%@

CAM_MIC_CBL_DET# <29>

GC6_EVENT# <48>
GPU_GC6_FB_EN <48,52>

CONTACTLESS_DET# <37>

HOST_SD_WP# <31>

AUD_PWR_EN <33>

ESD request,Place near CPU side.

PCH_JTAG_TMS

Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the ent ir e r egi on of t he SPI f la sh to be updat ed usi ng FPT.

+3.3V_ALW_PCH

ME_FWP PCH has internal 20K PD.
(su

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short

David_xie

0.1U_0402_25V6

@ESD@

12

CC304

2

1 2

RC81 51_0402_5%

1 2

RC82 100_0402_5%

1 2

RC130 51_0402_5%

ME_FW_EC

@

RC221 0_0402_5%

PT,ST pop RC222 and SW1; MP pop RC221

RC222

@

1K_0402_5%

1 2

ME_FW_EC<34>

1 2

ME_FWP

ME_FWP

@

SW1

1

A

2

B

3

C

4

G1

5

G2

SS3-CMFTQR9_3P

spend power rail)

H_THERMTRIP# H_PROCHOT#

0.1U_0402_25V6

0.1U_0402_25V6

@ESD@

12

CC305

@ESD@

12

CC312

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (7/14)

CPU (7/14)

CPU (7/14)

LA-E082P

LA-E082P

LA-E082P

0.1U_0402_25V6

@ESD@

12

CC310

1.0

1.0

12 75Monday, December 12, 2016

12 75Monday, December 12, 2016

12 75Monday, December 12, 2016

1

1.0

5

D D

4

CFG[0..19]<14>

3

2

1

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

12

RC113 10K_0402_1%@

CFG0

RC112 10K_0402_1%@
RC110 10K_0402_1%@

12
12

Stall reset sequence

HIGH(DEFAULT )
LOW

C C

RC109 1K_0402_5%

eDP enable

HIGH(DEFAULT )
LOW

B B

No stall(Normal Operat i on)

al l

st

12

CFG4

Disa bled
Enabled

+1.0V_PRIM_XDP

RC114 49.9_0402_1%
RC115 1.5K_0402_5%

ITP_PMODE<14>

@

T16

PAD~D

@

T17

PAD~D

CFG_RCOMP

12

ITP_PMODE

12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

CFG18
CFG19

AL25
AL27

BA70
BA68

E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70

E63
F63

E66
F66

E60

E8

AY2
AY1

D1
D3

K46
K45

C71
B70

F60
A52

J71
J68

F65
G65

F61
E61

UC1S

CPU@

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP
ITP_PMODE
RSVD_AY2

RSVD_AY1
RSVD_D1

RSVD_D3
RSVD_K46

RSVD_K45
RSVD_AL25

RSVD_AL27
RSVD_C71

RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70

RSVD_TP_BA68
RSVD_J71

RSVD_J68
VSS_F65

VSS_G65
RSVD_F61

RSVD_E61

SK

L-U_BGA1356

RESERVED SIGNALS-1

SKL-U

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

TP5
TP6

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

TP4

RSVD_A69
RSVD_B69

RSVD_AY3
RSVD_D71

RSVD_C70
RSVD_C54

RSVD_D54

TP1
TP2

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

19 OF 20

BB68
BB69

AK13
AK12

BB2
BA3

AU5
AT5

D5
D4
B2
C2

B3
A3

AW1
E1

E2
BA4

BB4
A4

C4
BB5
A69

B69

D71
C70

C54
D54

AY4
BB3

AY71
AR56

AW71
AW70

AP56
C64

PROC_SELECT#:This pin is for compatibility
wi
for KBL

@

T12

PAD~D

@

T13

PAD~D

@

T14

PAD~D

@

T15

PAD~D

@

T128

PAD~D

@

T129

PAD~D

@

T130

PAD~D

@

T126

PAD~D

@

T127

PAD~D

@

T113

PAD~D

@

T114

PAD~D

1 2

RC120 100K_0402_5%@

For Skylake , RC120 depop

or Cannonlake, RC120 pop

F

546765_546765_2014WW48_Skylake_MOW_Rev_1_0

th future platforms. It should be unconnected

1/5 2014WW52 MOW reserve to support
C

annonlake-U PCH compatibility

close UC1.U11/U12 and <400mil

1 2

RC313 0_0402_5%@

Z

VM# for SKYLAKE-U 2+3e

+1.0V_VCCST

+VCC_1P8+1.8V_PRIM

MSM# for SKYLAKE-U 2+3e

CPU@

SPARE

SKL-U

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

20 OF 20

F6
E3
C11
B11
A11
D12
C12
F52

UC1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

1

2

CC222

@

RSVD_H11

SK

L-U_BGA1356

1U_0402_6.3V6K

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (8/14)

CPU (8/14)

CPU (8/14)

LA-E082P

LA-E082P

LA-E082P

13 75Monday, December 12, 2016

13 75Monday, December 12, 2016

13 75Monday, December 12, 2016

1

1.0

1.0

1.0

@

CC29

5

+1.0V_PRIM_XDP

XDP_OBS0_R<12>
XDP_OBS1_R<12>

RC123 1K_0402_5%@

RC124CXDP@

PCH_SPI_DO_XDP<8>

SYS_PWROK<11,34>

RC239 0_0402_5%CXDP@
RC240 0_0402_5%CXDP@

RC5 need to close to JCPU1

1 2
1 2

1K_0402_5%

FIVR_EN
CFG0

RC217 0_0402_5%@
RC126 1K_0402_5%@
RC128 0_0402_5%CXDP@
RC129 0_0402_5%@

DDR_XDP_WAN_SMBDAT<8,20,21,41>

DDR_XDP_WAN_SMBCLK<8,20,21,41>

1 2
1 2
1 2
1 2

CPU_XDP_PREQ#<10>

CPU_XDP_PRDY#<10>

1 2
1 2

PCH_JTAG_TCK<12>

CPU_XDP_TCLK<12>

CPU XDP

H_VCCST_PWRGD_XDP

SIO_PWRBTN#<11,34>

CPU_XDP_PREQ#
CPU_XDP_PRDY#

RESET_OUT#_R

CPU_XDP_TCLK

+1.0V_PRIM

1 2

RC216 0_0603_1%@

+1.0V_PRIM_XDP

0.1U_0201_10V6K

0.1U_0201_10V6K

@

CC28

1

1

2

2

D D

Place near
JX

DP1

VCCST_PWRGD<11,34,35>

PCH_RSMRST#_AND<11,45>

+1.0V_PRIM_XDP

CFG0
CFG1

CFG2
CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

FIVR_EN_R

4

XDP_PRSNT_PIN1

1 2

RC121 0_0402_5%

1 2

RC122 0_0402_5%@

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12
PWRGOOD/HOOK039ITPCLK/HOOK4

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

CXDP@

CFG3

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

CONN@SAMTE_BSH-030-01-L-D-A

TD0

TDI

+1.0V_PRIM_XDP

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

ITP_PMODE
XDP_DBRESET#

TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS

3

CFG[0..19]<13>

CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>

ITP_PMODE <13>
XDP_DBRESET# <11>

PCH_SPI_DO2_XDP <8>

2

+3.3V_RUN

CC30

12

0.1U_0201_10V6K

TDO_XDP

TDI_XDP

XDP_TMS

TRST#_XDP

RUNPWROK<34>

UC8

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

GND

GND PAD

1

3

1B

6

2B

8

3B

11

4B

7
15

CPU_XDP_TDO <12>

CPU_XDP_TDI <12>

CPU_XDP_TMS <12>

CPU_XDP_TRST# <12>

FIVR_EN_R

C C

B B

RC132 150_0402_5%

+1.0V_VCCST

RC218 150_0402_5%@

RC219 10K_0402_5%@

+3.3V_RUN

+1.0V_PRIM_XDP

RC137 3K_0402_5%

RC138 51_0402_5%@

12

FIVR_EN

12

FIVR_EN

12

XDP_DBRESET#

12

CPU_XDP_PREQ#

12

+3.3V_ALW_PCH+1.0VS_VCCIO

RC133

1.5K_0402_5%

1 2

CXDP@

PCH_SPI_DO_XDP
RESET_OUT#_R

0.1U_0402_25V6

12

CC33@

Place near JXDP1.47

Place near JXDP1.48

XDP_DBRESET#

0.1U_0402_25V6

CXDP@

12

CC32

SIO_PWRBTN#

Place near JXDP1.41

+3.3V_ALW_DSW

1.5K_0402_5%

1 2

0.1U_0402_25V6

12

@

RC241

CC269

@

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

0.1U_0402_25V6

@ESD@

12

CC306

ESD request,Place near JXDP1 side. ES

12

CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO

CPU_XDP_TRST#
CPU_XDP_TCLK

XDP_TMS
TDI_XDP

@

TDO_XDP

@

0.1U_0402_25V6

@ESD@

CC307

1 2

RC131 51_0402_5%

1 2

RC134 51_0402_5%

1 2

RC135 100_0402_5%

1 2

RC136@ 51_0402_5%

1 2

RC139 51_0402_5%

1 2
1 2

RC229 0_0402_5%

1 2

RC230 0_0402_5%

0.1U_0402_25V6

@ESD@

12

CC308

D request,Place near UC8 side.

+1.0V_VCCSTG

PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (9/14)

CPU (9/14)

CPU (9/14)

LA-E082P

LA-E082P

LA-E082P

14 75Monday, December 12, 2016

14 75Monday, December 12, 2016

14 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

+VCC_CORE: 0.3~1.35V

D D

@

T122

PAD~D

@

T123

PAD~D

C C

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e

(w/ on package cach e)

+VCC_CORE +VCC_CORE

+VCC_CORE_G0
+VCC_CORE_G1

AK33
AK35
AK37
AK38
AK40

AL33
AL37

AL40
AM32
AM33
AM35
AM37
AM38

AK32
AB62

AC63
AE63

AE62
AG62

AL63

AJ62

A30
A34
A39
A44

G30
K32

P62
V62

H63
G61

SKL

UC1L

CPU@

VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32
RSVD_AK32
VCCOPC_AB62

VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE

VSSOPC_SENSE
VCCEOPIO

VCCEOPIO
VCCEOPIO_SENSE

VSSEOPIO_SENSE

-U_BGA1356

SKL-U

CPU POWER 1 OF 4

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

VCCSENSE
VSSSENSE

H_CPU_SVIDALRT#
VIDSCLK

VIDSOUT

+1.0V_VCCSTG_R

VIDSCLK <63>

RC143 0_0603_5%@

+VCC_CORE

1 2

12

1 2

RC140

RC141

100_0402_1%

100_0402_1%

VCCSENSE <63>
VSSSENSE <63>

+1.0V_VCCSTG

VIDSCLK

RF Request

1 2

CC321@RF@ 33P_0402_50V8J

Place close CPU side

PSC(Primary side cap) : Place as close to the package as
BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

possible

B B

SVID ALERT

VIDALERT_N<63>

SVID DATA

A A

VIDSOUT<63>

+1.0V_VCCST

1 2

+1.0V_VCCST

1 2

56_0402_1%

RC152

100_0402_1%

RC157

CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

12

RC153220_0402_5%

CAD Note: Place the PU resistors close to CPU

RC208close to CPU 300 - 1500mils

VIDSOUT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (10/14)

CPU (10/14)

CPU (10/14)

LA-E082P

LA-E082P

LA-E082P

15 75Monday, December 12, 2016

15 75Monday, December 12, 2016

15 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

+VCCGT: 0.3~1.35V
+V

CCGTX : 0.3~1.35V

+VCC_GT +VCC_GT

D D

C C

RC161

100_0402_1%

1 2

VCC_GT_SENSE<63>
VSS_GT_SENSE<63>

B B

VCC_GT_SENSE
VSS_GT_SENSE

12

RC163

100_0402_1%

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

M62
N63
N64
N66
N67
N69

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68

L70
L71

J70
J69

UC1M

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKL

-U_BGA1356

CPU@

CPU POWER 2 OF 4

SKL-U

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58

VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

13 OF 20

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50

VCCGTX for SKYLAKE-U 2+3e

AL53
AL56
AL60
AM48

AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

Reserve for soldering

+VCC_GTUS

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (11/14)

CPU (11/14)

CPU (11/14)

LA-E082P

LA-E082P

LA-E082P

16 75Monday, December 12, 2016

16 75Monday, December 12, 2016

16 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

+5V_ALW

@

CZ104

1 2

4

O

@

1

2

CC253

1U_0402_6.3V6K

UZ34

1

2

+1.2V_MEM

1

2

CC250

1U_0402_6.3V6K

@

RZ119 0_0402_5%

UZ26

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

CC251

1U_0402_6.3V6K

SIO_SLP_S0#

SIO_SLP_S3#

AND

1 2

+VCCPLL_OC source

+1.2V_MEM+1.2V_MEM_CPUCLK

@

1 2

RC231 0_0402_5%

P

D D

SC

1

1

2

1

CC177

CC176

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

PSC

22U_0603_6.3V6M

CC294

1

1

2

2

+1.0V_VCCST

C C

B B

PSC

1

2

CC195

1U_0402_6.3V6K

VDDQ: 8.45A

1

CC179

CC178

2

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

CC296

CC295

1

2

+1.0V_VCCSTG

BSC

1

PS

C

1

CC297

2

10U_0402_6.3V6M

CC199

1U_0402_6.3V6K

+1.2V_MEM_CPUCLK

+VCC_SFR_OC

2

CC288

1U_0402_6.3V6K

2

CC322

RF@

RF Request

+1.0V_VCCST source

+1.2V_MEM

2.2P_0402_50V8C

AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51

AM40

AL23

A18
A22

K20
K21

UC1N

CPU POWER 3 OF 4

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20

VCCPLL_K21

SK

L-U_BGA1356

+1.0V_VCCST

CPU@

1

2

CC202

1U_0402_6.3V6K

SKL-U

+VCC_SA

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

14 OF 20

1 2

RC168 100_0402_1%

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

+1.0VS_VCCIO

VCCIO_SENSE
VSSIO_SENSE

+VCC_SA

+1.0VS_VCCIO

12

RC166

100_0402_1%

VSA_SEN- <63>
VSA_SEN+ <63>

RC165

1 2

12

RC167

100_0402_1%

VCCIO_SENSE <61>
VSSIO_SENSE <61>

100_0402_1%

12

CZ102 1U_0402_6.3V6K

VCCSTG_EN

SIO_SLP_SUS#<11,34,47,60,61,62>
SIO_SLP_S4#<11,17,34,59,62>

1 2

@

RZ120 0_0402_5%

+3.3V_ALW

5

1

P

B

2

A

G

3

+1.0VS_VCCIO

0.1U_0402_10V7K

TC7SH08FU_SSOP5~D

PSC

1

2

CC252

1U_0402_6.3V6K

+1.0V_VCCSTG source

+VCC_SFR_OC

6

VOUT

5

GND

S0

HIGH

HIGH

HIGH LOW LOW

S0Ix

LOW

HIGH

S3

LOW

LOW

1 2

CZ103 0.1U_0201_10V6K

+1.0V_VCCST+1.0V_VCCSTG

1 2

RZ151 0_0603_5%@

+1.0V_PRIM

12

CZ100 1U_0402_6.3V6K

SIO_SLP_S4#<11,17,34,59,62>

A A

5

+1.0V_PRIM

+5V_ALW

UZ21

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

+1.0V_VCCST_C

6

5

4

PJP1

12

PAD-OPEN1x1m

1 2

CZ101 0.1U_0201_10V6K

+1.0V_VCCST

SIO_SLP_S0#<11,36,61>

RUN_ON<34,35,47,61>

TC7SH08FU_SSOP5~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

12

CZ105 1U_0402_6.3V6K

UZ35

RZ320 0_0402_5%@

+5V_ALW

+3.3V_ALW

5

1

B

2

A

3

1 2

P

O

G

4

VCCSTG_EN

UZ19

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
R=12.5us@Vin=1.05V

T

2

VOUT

GND

12

PJP2
PAD-OPEN1x1m

+1.0V_VCCSTG_C

6

5

DELL CONFIDENTIAL/PROPRIETARY

pop option with UZ19

1 2

CZ106 0.1U_0201_10V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (12/14)

CPU (12/14)

CPU (12/14)

LA-E082P

LA-E082P

LA-E082P

17 75Monday, December 12, 2016

17 75Monday, December 12, 2016

17 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

+1.0V_PRIM

+1.0V_MPHYAON

ose UC1.K17 and <120mil

1

D D

+1.8V_PRIM

C C

+3.3V_ALW_PCH

+1.8V_PRIM

@ESPI@

B B

1 2

@

RC299 0_0603_5%

1 2

@

RC300 0_0402_5%

1 2

@

RC301 0_0402_5%

1 2

@

RC302 0_0402_5%

1 2

@

RC303 0_0402_5%

1 2

@

RC304 0_0402_5%

1 2

RC234 0_0402_5%@

1 2

@

RC235 0_0402_5%

1 2

RC211 0_0402_5%LPC@

1 2

RC212 0_0402_5%

1 2

@

RC305 0_0402_5%

1 2

@

RC306 0_0402_5%

1 2

@

RC307 0_0402_5%

1 2

@

RC308 0_0402_5%

+3.3V_ALW_PCH

1 2

LC1 BLM15GA750SN1D_2P

1

CC215

2

RF@

47P_0402_50V8J

+1.0V_MPHYAON

+1.0V_CLK6

+1.0V_DTS

+1.0V_CLK1

+1.0V_CLK3

+1.8V_PGPPF

+3.3V_1.8V_PGPPG

close UC1.AF20 and <400mil

+3.3V_1.8V_PGPPA

+3.3V_1.8V_ESPI

PJP4

+3.3V_PGPPB+3.3V_ALW_PCH

PAD-OPEN1x1m

Must be +1.8V for eSPI I/F

+3.3V_PGPPC

+3.3V_PGPPD

+3.3V_PGPPE

8/28 schematic review

LC1,LC2 need link SM01000S100(S SUPPRE_ FBMA-1H-100505-601T 0402)

+3.3V_VCCHDA

1

CC313

2

0.1U_0201_10V6K

close UC1.AJ19 and <400mil

2

CC203

1U_0402_6.3V6K

+1.0V_MPHYGT

close UC1.N15 and CC210 <400mil, CC211 <120mil

1

2

+1.0V_SRAM

1

2

close UC1.K15, UC1.L15 and <100mil

@

1 2

RC169 0_0603_5%

1

2

CC281

@

0.1U_0201_10V6K

+1.0V_PRIM

1 2

LC2 BLM15GA750SN1D_2P

1

CC225

2

@

47U_0805_6.3V6M

close UC1.V15 and <100mil

4

close UC1.AL1 and <120mil

1

2

CC204

1U_0402_6.3V6K

1

CC210

2

@

CC211

1U_0402_6.3V6K

47U_0805_6.3V6M

CC217

+1.0V_APLLEBB

@

1U_0402_6.3V6K

2

CC218

+1.0V_AMPHYPLL+1.0V_MPHYGT

1

CC219

2

@

47U_0805_6.3V6M

+1.0V_PRIM_CORE+1.0VO_DSW

1

2

close UC1.AB19 and <400milcl

1

CC205

2

@

1U_0402_6.3V6K

close UC1.AF18 and <400mil

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_VCCHDA

+3.3V_SPI

+3.3V_ALW_PCH

+1.0V_PRIM

1U_0402_6.3V6K

close UC1.K15 and <120mil

1

2

CC264

@

1U_0402_6.3V6K

+1.0V_APLL

1

CC314

2

0.1U_0201_10V6K

+1.0V_PRIM

CC206

@

1U_0402_6.3V6K

UC1O CPU@

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

1 2

@

RC170 0_0402_5%

close UC1.K19 and <100mil

1 2

@

RC173 0_0402_5%

close UC1.N20 and <100mil

3

PCH PWR

CPU POWER 4 OF 4

+1.0V_CLK2+1.0V_PRIM

1

CC220

2

@

47U_0805_6.3V6M

+1.0V_CLK4+1.0V_PRIM

1

CC226

2

@

SKL-U

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

close UC1.L19 and <100mil

close UC1.Y16 a nd <400mil

close UC1.AG15 and <120mil

Must be +1.8V

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19
T1
AA1
AK17
AK19

BB14
BB10
A14
K19
L21
N20
L19
A10
AN11

AN13

+3.3V_1.8V_PGPPA

+3.3V_PGPPD
+1.8V_PGPPF

+3.3V_1.8V_PGPPG

+1.0V_DTS

+3.3V_ALW_PCH

close UC1.BB10 and <120mil

+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5

+3.3V_PGPPB

close UC1.AA1 and <400mil

close UC1.AK19 and <120mil

+DCPRTC

CORE_VID0 <61>
CORE_VID1 <61>

Take care!!! Note1 on Page 19

1 2

@

RC171 0_0402_5%

1

CC221

2

@

47U_0805_6.3V6M

+1.0V_MPHYGT source

2

1

CC265

2

@

1

2

+1.0V_CLK6

+3.3V_PGPPC

1

CC207

2

@

1U_0402_6.3V6K

1U_0402_6.3V6K

+RTC_CELL

1

2

CC270

CC214

0.1U_0201_10V6K

close UC1.A10 and <120mil

1

CC216

2

@

1U_0402_6.3V6K

+3.3V_PGPPE

close UC1.T16 a nd <400mil

1

2

1

2

CC213

1U_0402_6.3V6K

0.1U_0201_10V6K

+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM

CC208

@

1U_0402_6.3V6K

+1.8V_PRIM

1

2

close UC1.AK17 and <120mil

1

1

CC223

2

2

0.1U_0201_10V6K

+1.0V_MPHYGT

@

RC309 0_0603_5%

@

RC310 0_0603_5%

+3.3V_ALW_PCH

1

CC209

2

@

CC212

1U_0402_6.3V6K

+1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB

CC224

1U_0402_6.3V6K

1

1 2

1 2

+1.0V_SRAM

+1.0V_APLLEBB

+3.3V_1.8V_PGPPG

close UC1.AD15 and <400mil

1

CC326

2

1U_0402_6.3V6K

close UC1.V19 and <120mil

1U_0402_6.3V6K

RF Request

1

1

2

2

CC324

CC323

RF@

RF@

2.2P_0402_50V8C

2.2P_0402_50V8C

PJP3

1 2

PAD-OPEN1x3m

1

2

CC325

RF@

2.2P_0402_50V8C

+1.0V_MPHYGT+1.0V_PRIM

561280_561280_KBL_UY_PDG_Rev0p9 :MPHY has defeature

47U_0805_6.3V6M

+3.3V_ALW +3.3V_ALW_DSW

A A

1 2

@

RC214 0_0402_5%

22U_0603_6.3V6M

@

22U_0603_6.3V6M

@

CC279

CC280

1

1

2

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (13/14)

CPU (13/14)

CPU (13/14)

LA-E082P

LA-E082P

LA-E082P

18 75Monday, December 12, 2016

18 75Monday, December 12, 2016

18 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmendat i on

CPU@

SKL-U

UC1P

GND 1 OF 3

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

D D

C C

B B

AA65
AA68
AB15
AB16
AB18
AB21

AB8
AD13
AD16
AD19
AD20
AD21
AD62

AD8
AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH6
AH63
AH64
AH67

AJ15
AJ18
AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AK8
AL28

AL32
AL35
AL38

AL45
AL48
AL52
AL55
AL58
AL64

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF1

VSS
VSS
VSS
VSS

AF2

VSS

AF4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL2

VSS
VSS
VSS
VSS
VSS

AL4

VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL

-U_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

16 OF 20

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48

AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6

AW60
AW62
AW64
AW66

AW8

AY66

BA10
BA14
BA18

BA23
BA28
BA32
BA36

BA45

CPU@

SKL-U

UC1Q

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B10

VSS

B14

VSS

B18

VSS

B22

VSS

B30

VSS

B34

VSS

B39

VSS

B44

VSS

B48

VSS

B53

VSS
VSS

B62

VSS

B66

VSS

B71

VSS

BA1

VSS
VSS
VSS
VSS

BA2

VSS
VSS
VSS
VSS
VSS

F68

VSS
VSS

SKL

-U_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

17 OF 20

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71

F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

CPU@

SKL-U

UC1R

GND 3 OF 3

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKL

-U_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

18 OF 20

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

R1

: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (14/14)

CPU (14/14)

CPU (14/14)

LA-E082P

LA-E082P

LA-E082P

19 75Monday, December 12, 2016

19 75Monday, December 12, 2016

19 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For DDR4

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>

DDR_A_MA[0..16]<7>

Layout Note:

D D

C C

B B

A A

Place near JDIMM1

+1.2V_MEM

10U_0603_10V6M

10U_0603_10V6M

CD2

CD1

12

12

+1.2V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

CD9

CD10

+0.6V_DDR_VTT

12

DIMM Select

SA01SA1

DIMM1

DIMM2

DIMM3

DIMM4

10U_0603_10V6M

CD3

12

1U_0402_6.3V6K

12

CD11

Layout Note:
Place near
JDIMM1.258

10U_0603_10V6M

CD22

0

0

0

1

0

1

1

10U_0603_10V6M

10U_0603_10V6M

CD5

CD4

12

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

12

CD13

CD12

1U_0402_6.3V6K

1U_0402_6.3V6K

CD23

CD24

1

1

2

2

SA2

0

0

0

0

10U_0603_10V6M

1U_0402_6.3V6K

12

12

CD6

12

12

CD14

RD4

@

0_0402_5%

@

RD5
0_0402_5%

10U_0603_10V6M

330U_D3_2.5VY_R6M

10U_0603_10V6M

12

@

CD8

CD17

CD7

12

+

+2.5V_MEM

1U_0402_6.3V6K

CD19

12

1

2

10U_0603_10V6M

1

CD20

2

@

RD10
0_0603_5%

2.2U_0402_6.3V6M
CD27

10U_0603_10V6M

1

CD21

2

+3.3V_RUN_DIMM1

0.1U_0201_10V6K
CD28

1

2

DDR_XDP_WAN_SMBCLK<8,14,21,41>

DDR_A_CKE0<7>

DDR_A_BG1<7>
DDR_A_BG0<7>

DDR_A_CLK0<7>
DDR_A_CLK#0<7>

DDR_A_CS#1<7>

DDR_A_ODT1<7>

+2.5V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD15

CD16

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

RD6

@

0_0402_5%

12

@

RD7
0_0402_5%

12

@

0_0402_5%

12

0.1U_0402_10V6K

1

CD25

2

RD8

DIMM1_SA0
DIMM1_SA1
DIMM1_SA2

@

RD9
0_0402_5%

1U_0402_6.3V6K

1

1

CD18

2

2

2.2U_0402_6.3V6M

@

1

CD26

2

+3.3V_RUN

DDR_A_D1
DDR_A_D0
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D6
DDR_A_D2
DDR_A_D13
DDR_A_D12

DDR_A_D15
DDR_A_D14
DDR_A_D35
DDR_A_D37
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D38
DDR_A_D34
DDR_A_D44
DDR_A_D45

DDR_A_D42
DDR_A_D46

DDR_A_CKE0
DDR_A_BG1

DDR_A_BG0
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA6
DDR_A_MA3

DDR_A_MA1
DDR_A_CLK0

DDR_A_CLK#0
DDR_A_PARITY

DDR_A_ODT1

T51PAD~D @

DDR_A_D30
DDR_A_D26
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D27
DDR_A_D29
DDR_A_D21
DDR_A_D17

DDR_A_D19
DDR_A_D22
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57

DDR_A_D63
DDR_A_D62

+3.3V_RUN_DIMM1

+1.2V_MEM

JDIMM1

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5
DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16
DM1_n/DBI_n33DQS1_t

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25
DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36
DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45
DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1
VDD13 VDD14
CS0_n BA0
WE_n/A14 RAS_n/A16
VDD15 VDD16
ODT0 CAS_n/A15
CS1_n A13
VDD17 VDD18

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LCN_DAN05-Q0406-0103
CONN@

LINK DAN05-Q0406-0103 DONE

VSS11

DQ12

VSS13
VSS15

DQS1_c

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26
VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46
VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1
VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67
DQS5_c
DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87
DQS7_c
DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

VSS2
VSS4
VSS6
VSS7
VSS9

+1.2V_MEM

2
4

DQ4

6
8

DQ0

10
12
14
16

DQ6

18
20

DQ2

22
24
26
28

DQ8

30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130
132

A2

134
136
138
140
142
144

A0

146

162
164
166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

VTT

260

SA1

262

DDR_A_D4
DDR_A_D5

DDR_A_D3
DDR_A_D7
DDR_A_D9
DDR_A_D8
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D32
DDR_A_D36

DDR_A_D39
DDR_A_D33
DDR_A_D40
DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D47
DDR_A_D43

DDR_DRAMRST#_R
DDR_A_CKE1

DDR_A_ACT#
DDR_A_ALERT#

DDR_A_MA11
DDR_A_MA7

DDR_A_MA5
DDR_A_MA4

DDR_A_MA2
JDIMM1_EVENT#

DDR_A_CLK1
DDR_A_CLK#1

DDR_A_BA0

DDR_A_MA15

DIMM1_SA2
DDR_A_D31
DDR_A_D25

DDR_A_D28
DDR_A_D24
DDR_A_D20
DDR_A_D16
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18
DDR_A_D23
DDR_A_D53
DDR_A_D52

DDR_A_D54
DDR_A_D55
DDR_A_D61

DDR_A_D60

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D58

DDR_A_D59

DIMM1_SA0
DIMM1_SA1

DDR_A_CKE1 <7>
DDR_A_ACT# <7 >

DDR_A_ALERT# <7>

DDR_A_BA0 <7>

+DDR_VREF_A_CA

T50 PAD~D@

+DDR_VREF_A_CA

DDR_XDP_WAN_SMBDAT <8,14,2 1,41>

+0.6V_DDR_VTT

+1.2V_MEM

470_0402_1%

12

RD11

1 2

@

RD12 0_0402_5%

+1.2V_MEM

12

12

1

CD29

@

0.1U_0402_25V6

2

JDIMM1_EVENT#

DDR_VTT_CTRL<7>

1 2

RD14 1K_0402_5%@

UD1

1

NC

VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

+1.2V_MEM

5

4

Y

DDR_DRAMRST#

1K_0402_1%

RD15

1 2

RD17 2_0402_1%

1K_0402_1%

RD16

1 2

CD32@ 0.1U_0201_10V6K

1 2

RD19 100K_0402_5%

DDR_DRAMRST# <7>DDR_DRAMRST#_R<21>

+DDR_VREF_CA+DDR_VREF_A_CA

0.022U_0402_16V7K

CD31

12

24.9_0402_1%

12

RD18

H_THERMTRIP# <12,21,35>

0.6V_DDR_VTT_ON <59>

+3.3V_RUN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

ADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

TR

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTE N CONSENT.

2

Title

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

DDR4

DDR4

DDR4

LA-E082P

LA-E082P

LA-E082P

1

20 75Monday, December 12, 2016

20 75Monday, December 12, 2016

20 75Monday, December 12, 2016

1.0

1.0

1.0

5

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>

DDR_B_MA[0..16]<7>

Layout Note:

10U_0603_10V6M

CD33

12

1U_0402_6.3V6K

12

CD41

SA01SA1

0

1

0

1

Place near JDIMM2

10U_0603_10V6M

CD35

CD34

12

12

1U_0402_6.3V6K

12

12

CD43

CD42

+0.6V_DDR_VTT

10U_0603_10V6M

CD54

12

SA2

0

0

0

0

0

0

1

10U_0603_10V6M

10U_0603_10V6M

CD36

12

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD44

Layout Note:
Place near
JDIMM2.258

1U_0402_6.3V6K

CD55

1

2

CD37

CD45

12

12

12

12

1U_0402_6.3V6K

1

2

@

0_0402_5%

RD21
0_0402_5%

10U_0603_10V6M

330U_D3_2.5VY_R6M

10U_0603_10V6M

10U_0603_10V6M

12

@

CD39

CD49

CD40

CD38

12

12

+

+2.5V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

CD48

CD47

CD46

CD56

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

12

@

RD20

@

12

RD22
0_0402_5%

RD23

@

0_0402_5%

12

@

0_0402_5%

DIMM2_SA0
DIMM2_SA1
DIMM2_SA2

RD24

@

RD25
0_0402_5%

1U_0402_6.3V6K

1

CD50

2

+DDR_VREF_B_CA

1

2

+3.3V_RUN

1U_0402_6.3V6K

1

CD51

2

0.1U_0402_10V6K
CD57

1

2

12

@

RD26
0_0603_5%

2.2U_0402_6.3V6M

12

CD59

D D

+1.2V_MEM

10U_0603_10V6M

12

+1.2V_MEM

1U_0402_6.3V6K

12

C C

B B

DIMM Select

DIMM1

DIMM2

DIMM3

*

DIMM4

A A

10U_0603_10V6M

1

1

CD52

2

2

2.2U_0402_6.3V6M

@

CD58

+3.3V_RUN_DIMM2

0.1U_0201_10V6K

1

CD60

2

4

3

2

1

For DDR4

+1.2V_MEM

DDR_B_D1
DDR_B_D4
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D7
DDR_B_D6
DDR_B_D13
DDR_B_D12

DDR_B_D14
DDR_B_D15
DDR_B_D33
DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D39
DDR_B_D38
DDR_B_D42
DDR_B_D43

10U_0603_10V6M

CD53

DDR_B_CKE0<7>

DDR_B_BG1<7>
DDR_B_BG0<7>

DDR_B_CLK0<7>
DDR_B_CLK#0<7>

DDR_B_PARITY<7>

DDR_B_ODT1<7>

DDR_XDP_WAN_SMBCLK<8,14,20,41>

DDR_B_BA1<7>

+2.5V_MEM

DDR_B_D44
DDR_B_D45

DDR_B_CKE0
DDR_B_BG1

DDR_B_BG0
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA6
DDR_B_MA3

DDR_B_MA1
DDR_B_CLK0

DDR_B_CLK#0
DDR_B_PARITY

DDR_B_BA1

T55PAD~D @

DDR_B_D21
DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D23
DDR_B_D22
DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27
DDR_B_D52
DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D55
DDR_B_D54
DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

+3.3V_RUN_DIMM2

JDIMM2

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5
DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16
DM1_n/DBI_n33DQS1_t

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25
DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36
DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45
DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13
CS0_n BA0
WE_n/A14 RAS_n/A16
VDD15 VDD16
ODT0 CAS_n/A15
CS1_n A13
VDD17 VDD18
ODT1 C0/CS2_n/NC
VDD19 VREFCA

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LCN_DAN05-Q0406-0103
CONN@

VSS11

DQ12

VSS13
VSS15

DQS1_c

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26
VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46
VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1
VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12
A10/AP

VDD14

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

VSS2
VSS4
VSS6
VSS7
VSS9

+1.2V_MEM

2
4

DQ4

6
8

DQ0

10
12
14
16

DQ6

18
20

DQ2

22
24
26
28

DQ8

30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130
132

A2

134
136
138
140
142
144

A0

146
148

166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

VTT

260

SA1

262

DDR_B_D5
DDR_B_D0

DDR_B_D2
DDR_B_D3
DDR_B_D9
DDR_B_D8
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D11
DDR_B_D10
DDR_B_D37
DDR_B_D32

DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_DRAMRST#_R
DDR_B_CKE1

DDR_B_ACT#
DDR_B_ALERT#

DDR_B_MA11
DDR_B_MA7

DDR_B_MA5
DDR_B_MA4

DDR_B_MA2
JDIMM2_EVENT#

DDR_B_CLK1
DDR_B_CLK#1

DDR_B_MA0
DDR_B_MA10

DIMM2_SA2
DDR_B_D16
DDR_B_D17

DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D31
DDR_B_D30
DDR_B_D53
DDR_B_D48

DDR_B_D50
DDR_B_D51
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62
DDR_B_D63

DIMM2_SA0
DIMM2_SA1

DDR_B_CKE1 <7>
DDR_B_ACT# <7>

DDR_B_ALERT# <7>

DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>

DDR_XDP_WAN_SMBDAT <8,14,20,41>

+0.6V_DDR_VTT

JDIMM2_EVENT#

RD27 1K_0402_5%@

1

CD61

@

0.1U_0402_25V6

2

+DDR_VREF_B_CA

1 2

DDR_DRAMRST#_R <20>

+1.2V_MEM

1K_0402_1%

12

RD28

1 2

RD30 2_0402_1%

1K_0402_1%

12

RD29

H_THERMTRIP# <12,20,35>

0.022U_0402_16V7K

CD62

12

24.9_0402_1%

12

RD31

+DDR_VREF_B_DQ

LINK DAN05-Q0406-0103 DONE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

T

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTE N CONSENT.

2

Title

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

DDR4

DDR4

DDR4

LA-E082P

LA-E082P

LA-E082P

1

21 75Monday, December 12, 2016

21 75Monday, December 12, 2016

21 75Monday, December 12, 2016

1.0

1.0

1.0

A

B

C

D

E

+3.3V_RUN

SW2_DP1_AUXN

RV70 100K_0402_5%
RV71 100K_0402_5%
RV72 100K_0402_5%

1 1

RV73 1M_0402_5%

RV74 1M_0402_5%
RV75 1M_0402_5%

RV76 100K_0402_5%
RV77 100K_0402_5%
RV78 100K_0402_5%

@

@

RV81

RV79

1 2

2 2

3 3

Internally t i ed t o V DD33/2, 3. 3 V I / O;
PCx =

(defaul t)

L:Portx output with f i xed 400 mV a nd 0dB
x=1, 2, 3

4.7K_0402_5%

12

RV82

RV80

@

@

4.7K_0402_5%

M:Portx output conf i gur at i on is set by l i nk t raini ng

H:Portx output with f i xed 800 mV a nd 0dB

12

SW2_DP2_AUXN

12

SW2_DP3_AUXN

12

0.01UF_0402_25V7K

SW2_DP1_CADET

12

SW2_DP2_CADET

12

SW2_DP3_CADET

12

SW2_DP1_AUXP

12

SW2_DP2_AUXP

12

SW2_DP3_AUXP

12

+3.3V_RUN

@

@

RV85

RV83

1 2

1 2

4.7K_0402_5%

12

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

12

RV86

RV84

@

@

4.7K_0402_5%

4.7K_0402_5%

@

RV89

RV87

1 2

1 2

4.7K_0402_5%

4.7K_0402_5%

12

12

RV88

RV90

@

4.7K_0402_5%

4.7K_0402_5%

@

@

RV93

RV91

1 2

1 2

4.7K_0402_5%

12

12

RV92

@

4.7K_0402_5%

RV95

1 2

1 2

4.7K_0402_5%

4.7K_0402_5%

12

12

RV94

RV96

@

@

4.7K_0402_5%

4.7K_0402_5%

PS8348B_PI0
PS8348B_PI1
PS8348B_SW1
PS8348B_SW0
PS8348B_PEQ
PS8348B_CFG
PS8348B_PC1

PS8348B_PC3

PI0:Automat i c E Q di s abl e, I nt er nal pull do wn ~150K oh m, 3. 3 V I / O
PI0 = L: Automat i c E Q enabl e( def ault)

H: Automat i c E Q di sabl e

CPU_DP2_P0<6>
CPU_DP2_N0<6>

CPU_DP2_P1<6>
CPU_DP2_N1<6>

CPU_DP2_P2<6>
CPU_DP2_N2<6>

CPU_DP2_P3<6>
CPU_DP2_N3<6>

CPU_DP2_AUXP<6>
CPU_DP2_AUXN<6>

CPU_DP2_CTRL_CLK<6>

CPU_DP2_CTRL_DATA<6>

0.01UF_0402_25V7K
CV81

CV80

12

12

CV86 0.1U_0201_10V6K
CV87 0.1U_0201_10V6K

CV88 0.1U_0201_10V6K
CV89 0.1U_0201_10V6K

CV90 0.1U_0201_10V6K
CV91 0.1U_0201_10V6K

CV92 0.1U_0201_10V6K
CV93 0.1U_0201_10V6K

CV94 0.1U_0201_10V6K
CV95 0.1U_0201_10V6K

CPU_DP2_HPD<6> SW2_DP2_P3 <32>

0.01UF_0402_25V7K

12

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

0.1U_0201_10V6K
CV83

CV82

1

1

2

2

PS8348B_PI0
PS8348B_PI1

PS8348B_SW1
PS8348B_SW0

PS8348B_CFG
PS8348B_PC1
PS8348B_PC2
PS8348B_PC3

PS8348B_PEQ

0.1U_0201_10V6K
CV84

1

2

CPU_DP2_P0_C
CPU_DP2_N0_C

CPU_DP2_P1_C
CPU_DP2_N1_C

CPU_DP2_P2_C
CPU_DP2_N2_C

CPU_DP2_P3_C
CPU_DP2_N3_C

CPU_DP2_AUXP_C
CPU_DP2_AUXN_C

T204@ PAD~D

T223@ PAD~D

T224@ PAD~D

0.1U_0201_10V6K
CV85

+3.3V_RUN

12

RV97

4.99K_0402_1%

UV7

1

VDD33

10

VDD33

34

VDD33

11

IN_D0p

12

IN_D0n

14

IN_D1p

15

IN_D1n

16

IN_D2p

17

IN_D2n

19

IN_D3p

20

IN_D3n

64

IN_AUXp

63

IN_AUXn

66

IN_DDC_SCL

65

IN_DDC_SDA

8

IN_CA_DET

7

IN_HPD

2

PI0 / SDA_CTL

3

PI1 / SCL_CTL

4

SW1

5

SW0

21

CFG

22
23

PC2

45

PC3

18

PEQ

13

PD

9

REXT

67

PAD(GND)

For Breckenridge 12/14/15

Priority: Type-C -> WiGig -> VGA

OUT1_D0p
OUT1_D0n

OUT1_D1p
OUT1_D1n

OUT1_D2p
OUT1_D2n

OUT1_D3p
OUT1_D3n

OUT2_D0p
OUT2_D0n

OUT2_D1p
OUT2_D1n

OUT2_D2p
OUT2_D2n

OUT2_D3p
OUT2_D3n

OUT3_D0p
OUT3_D0n

OUT3_D1p
OUT3_D1n

OUT3_D2p
OUT3_D2n

OUT3_D3p
OUT3_D3n

OUT1_AUXp_SCL
OUT1_AUXn_SDA

OUT2_AUXp_SCL
OUT2_AUXn_SDA

OUT3_AUXp_SCL
OUT3_AUXn_SDA

OUT1_CA_DET

OUT1_HPD

OUT2_CA_DET

OUT2_HPD

OUT3_CA_DET

OUT3_HPD

PS8348BQFN66GTR-A0_QFN66_5X10

CEXT

55
54

52
51

50
49

47
46

44
43

41
40

39
38

36
35

33
32

30
29

28
27

25
24

62

60
59

58
57

SW2_DP1_CADET

48
53

SW2_DP2_CADET

37
42

SW2_DP3_CADET

26
31

56

2.2U_0402_6.3V6M
CV96

1

2

SW2_DP1_P0 <25>
SW2_DP1_N0 <25>

SW2_DP1_P1 <25>
SW2_DP1_N1 <25>

SW2_DP1_P2 <25>
SW2_DP1_N2 <25>

SW2_DP1_P3 <25>
SW2_DP1_N3 <25>

SW2_DP2_P0 <32>
SW2_DP2_N0 <32>

SW2_DP2_P1 <32>
SW2_DP2_N1 <32>

SW2_DP2_P2 <32>
SW2_DP2_N2 <32>

SW2_DP2_N3 <32>

SW2_DP3_P0 <24>
SW2_DP3_N0 <24>

SW2_DP3_P1 <24>
SW2_DP3_N1 <24>

SW2_DP1_AUXP <25,26>
SW2_DP1_AUXN <25,26>
SW2_DP2_AUXP <32>

SW2_DP2_AUXN <32>
SW2_DP3_AUXP <24>

SW2_DP3_AUXN <24>

SW2_DP1_HPD <25,26>

SW2_DP2_HPD <32>

SW2_DP3_HPD <24>

-----> WIGIG

-----> TYPE C

---

--> VGA

Internally pull down ~150K.3.3V I/O
For Control Switching Mode (CFG = L):
[SW1,SW0 ]= [L,L], Port1 is selected (default)
[SW1,SW0 ]= [L,H], Port2 is selected
[SW1,SW0 ]= [H,L], Port3 is selected
[SW1,SW0 ]= [H,H], Port3 is selected

4 4

For Automat i c S witc hi ng Mode ( CF G0= H):
[SW1,SW0 ]= [L,L], Port1 >Port2 >Port3 (default)
[SW1,SW0 ]= [L,H], Port1 >Port3 >Port2
[SW1,SW0 ]= [H,L], Port3 >Port2 >Port1
[SW1,SW0 ]= [H,H], Port3 >Port1 >Port2
[SW1,SW0 ]= [L,M], Port2 >Port1 >Port3
[SW1,SW0 ]= [M,M], Port2 >Port3 >Port1

A

Internally t i ed t o V DD33/2, 3. 3 V I / O

Q =

PE

M:default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H:HEQ , compensate channel loss up to 14.5dB @ HBR2
L:LLEQ, compensate channel loss up to 8.5dB @ HBR2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

B

PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

C

D

Date: Sheet of

Compal Electronics, Inc.

DP SW2 PS8348B

DP SW2 PS8348B

DP SW2 PS8348B

LA-E082P

LA-E082P

LA-E082P

22 75Monday, December 12, 2016

22 75Monday, December 12, 2016

22 75Monday, December 12, 2016

E

1.0

1.0

1.0

544332211

0.1U_0201_10V6K

CV39

1

@

2

+3.3V_RUN

+3.3V_RUN

+5V_RUN

1

AP2330W-7_SC59-3

IN

UV2

GND2OUT

3

12

RV19@10K_0402_5%

1 2

RV10 470_0402_1%

1 2

RV11 470_0402_1%

1 2

RV12 470_0402_1%

1 2

RV13 470_0402_1%

1 2

RV14 470_0402_1%

1 2

RV15 470_0402_1%

1 2

RV16 470_0402_1%

1 2

RV17 470_0402_1%

1 2

RV18 10K_0402_5%

+VHDMI_VCC

0.1U_0201_10V6K

1

@

2

HDMI_HPD

HDMI_CTRL_DATA
HDMI_CTRL_CLK

HDMI_CEC
HDMI_L_CLKN

HDMI_L_CLKP
HDMI_L_TX_N0

HDMI_L_TX_P0
HDMI_L_TX_N1

HDMI_L_TX_P1
HDMI_L_TX_N2

HDMI_L_TX_P2

HDMI_OB

2

G

For 1.65G HDMI from CPU

10U_0603_10V6M

CV41

12

CV40

HDMI connector

JHDMI1

CONN@

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CONCR_099BKAC19YBLCNF

LINK 099BKAC19YBLCNF DONE

1

D

QV4
L2N7002W T1G_SC-70-3

3

GND
GND
GND
GND

20
21
22
23

5

1 2

RV24 5.6_0402_5%EMI@

LV3

EMI@

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

RV25 5.6_0402_5%EMI@

1 2

RV27

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

RV28

1 2

RV30 5.6_0402_5%EMI@

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

RV31

1 2

RV33

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

RV34 5.6_0402_5%EMI@

LV6

LV9

LV12

4

3

5.6_0402_5%EMI@

4

3

5.6_0402_5%EMI@

4

3

5.6_0402_5%EMI@

5.6_0402_5%

4

3

D D

C C

CPU_DP1_P0<6>

CPU_DP1_N0<6>

CPU_DP1_P1<6>

CPU_DP1_N1<6>

CPU_DP1_P2<6>

CPU_DP1_N2<6>

CPU_DP1_P3<6>

CPU_DP1_N3<6>

1 2

CV31 0.1U_0402_25V6

1 2

CV32 0.1U_0402_25V6

1 2

CV33 0.1U_0402_25V6

1 2

CV34 0.1U_0402_25V6

1 2

CV35 0.1U_0402_25V6

1 2

CV36 0.1U_0402_25V6

12

0.1U_0402_25V6

CV37

12

0.1U_0402_25V6

CV38

HDMI_TX_P2

HDMI_TX_N2

HDMI_TX_P1

HDMI_TX_N1

HDMI_TX_P0

HDMI_TX_N0

HDMI_CLKP

HDMI_CLKN

HDMI_L_TX_P2

4

EMI@

RV26
200_0402_5%

3

1 2

HDMI_L_TX_N2

RV29
200_0402_5%

1 2

RV32
200_0402_5%

1 2

RV35
200_0402_5%

1 2

EMI@

EMI@

EMI@

HDMI_L_TX_P1

HDMI_L_TX_N1

HDMI_L_TX_P0

HDMI_L_TX_N0

HDMI_L_CLKP

HDMI_L_CLKN

HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN

4

3

4

3

4

3

1M_0402_5%

RV20

CPU_DP1_HPD<6>

1 2

G

123

D

S

QV5

L2N7002W T1G_SC-70-3

HDMI_HPD

1 2

RV21 20K_0402_5%

B B

+3.3V_RUN

QV3A

2

DMN65D8LDW-7_SOT363-6

CPU_DP1_CTRL_CLK<6>

CPU_DP1_CTRL_DATA<6>

1

5

QV3B

DMN65D8LDW-7_SOT363-6

HDMI_CTRL_CLK

6

HDMI_CTRL_DATA

34

1 2

RV22 2.2K_0402_5%

1 2

RV23 2.2K_0402_5%

+VHDMI_VCC

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

Title

Title

Title

ze Document Number Rev

Size Document Number Re v

Size Document Number Re v

Si

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

HDMI CONN

HDMI CONN

HDMI CONN

LA-E082P

LA-E082P

LA-E082P

23 75Monday, December 12, 2016

23 75Monday, December 12, 2016

23 75Monday, December 12, 2016

1.0

1.0

1.0

5

4

3

2

1

For Breckenridge 12/14/15
For Realtek Solution

+3.3V_RUN

+3.3V_RUN

D D

RV106 4.7K_0402_5%@
RV107 4.7K_0402_5%@

RV102 100K_0402_5%

C C

12

ISPSCL

12

ISPSDA

SW2_DP3_HPD

12

SW2_DP3_AUXP<22>

SW2_DP3_AUXN<22>

SW2_DP3_P0<22>
SW2_DP3_N0<22>
SW2_DP3_P1<22>
SW2_DP3_N1<22>

60ohm/1A

1 2

LV14 BLM15PX600SN1D_2P

+3.3V_RUN

+3.3V_VGA

1 2

CV1110.1U_0402_10V7K

1 2

CV1120.1U_0402_10V7K

1 2

CV1070.1U_0402_10V7K

1 2

CV1080.1U_0402_10V7K

1 2

CV1090.1U_0402_10V7K

1 2

CV1100.1U_0402_10V7K

1 2

RV123 4.7K_0402_5%

1 2

RV124 4.7K_0402_5%

CLK_DDC2_CRT
DAT_DDC2_CRT

SW2_DP3_HPD<22>

+VCCK_12

SW2_DP3_AUXP_C
SW2_DP3_AUXN_C

SW2_DP3_P0_C
SW2_DP3_N0_C
SW2_DP3_P1_C
SW2_DP3_N1_C

ISPSCL
ISPSDA

SW2_DP3_HPD

1

AVC33

4

AVCC_12

14

VCC_33

2

AUX_P

3

AUX_N

5

LANE0_P

6

LANE0_N

7

LANE1_P

8

LANE1_N

10

POL1/SPI_CEB

9

POL2

11

GPI1/SPI_CLK

12

GPI2/SPI_SI

13

GPI3/SPI_SO

15

VGA_SCL

16

VGA_SDA

30

SMB_SCL

29

SMB_SDA

32

HPD

UV6

RTD2166

RTD2166-CG_QFN32_4X4

VDD_DAC_33

VCCK_12
PVCC_33

HVSYNC_PWR

VSYNC
HSYNC

BLUE_P

GREEN_P

RED_P

LDO_RSTB

EXT_CLK_IN

EXT1.2V_CTRL

GND

EPAD_GND

20
25
26

17
18
19

21
22
23

27
28
31

24
33

+VDD_DAC_33

+VCCK_12

VSYNC_CRT
HSYNC_CRT

BLUE_CRT
GREEN_CRT
RED_CRT

60ohm/1A

+3.3V_RUN

Operation Mode Table

1(P10)

POL

10

0

X

X
POL2
(P9)

1

ROM EEPROM

+CRT_VCC

0.1U_0402_25V6

1

2

+3.3V_RUN

12

LV30BLM15PX600SN1D_2P

CV101

0.1U_0402_25V6

1

2

4.7U_0402_6.3V6M
CV102

1

2

Place near UV6.4 Place near UV6.25 Place near UV6.26

+VCCK_12

0.1U_0402_25V6
CV103

CV100

1

2

2.2U_0402_16V6K

0.1U_0402_25V6
CV105

CV104

1

1

2

2

+3.3V_RUN

1

2

0.1U_0402_25V6
CV106

PJDLC05C_SOT23-3

2

3

@ESD@

DV5

1

RED_CRT

B B

A A

5

4

GREEN_CRT
BLUE_CRT

12

12

RV116

75_0402_1%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

12

1

RV118

75_0402_1%

2

12P_0402_50V8J

CV126

DAT_DDC2_CRT
CLK_DDC2_CRT
HSYNC_CRT
VSYNC_CRT

CV127

RV117

75_0402_1%

3

1

2

12P_0402_50V8J

+CRT_VCC

RV119

LV16 BLM15BB470SN1D_2PEMI@
LV17 BLM15BB470SN1D_2PEMI@
LV18 BLM15BB470SN1D_2PEMI@

1

2

CV128

1 2

2.2K_0402_5%

LV19 BLM15AG121SN1D_L0402_2PEMI@
LV20 BLM15AG121SN1D_L0402_2PEMI@

1 2
1 2
1 2

12P_0402_50V8J

RV120

1 2

2.2K_0402_5%

1 2
1 2

1

2

RV121

RV122

1 2

@

@

1K_0402_5%

1

CV132

CV133

2

22P_0402_50V8J

1

CV129

@

3.3P_0402_50V8C

1 2

1K_0402_5%

1

2

22P_0402_50V8J

CV130

@

2

3.3P_0402_50V8C

2

PJDLC05C_SOT23-3

2

3

@ESD@

DV6

1

1

CV131

@

2

3.3P_0402_50V8C

1

IN

GND2OUT

3

40mils

@

0.1U_0402_16V4Z
CV135

1

2

UV4
AP2330W-7_SC59-3

+CRT_VCC

1

CV134
1U_0402_6.3V6K

2

T87 PAD~D

HSYNC_CONN

VSYNC_CONN

M_ID2#

JCRT1

6

JCRT-11
RED

GREEN

BLUE

Link C070546HR015M29CZR don

Link C070546HR015M29CZR don

Link C070546HR015M29CZR don

Link C070546HR015M29CZR don

11

1

7

12

2

8

13

3

9

14

G

4

16

G

10

17

15

5

CCM_C070546HR015M29CZR

CONN@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.
DP to VGA & VGA Conn

DP to VGA & VGA Conn

DP to VGA & VGA Conn

LA-E082P

LA-E082P

LA-E082P

24 75Monday, December 12, 2016

24 75Monday, December 12, 2016

24 75Monday, December 12, 2016

1

1.0

1.0

1.0

e

e

e

e

5

4

3

2

1

+3.3V_RUN_UT9

+3.3V_CPS

For NON-AR port1

1 2

LT11 BLM15PX600SN1D_2P

D D

@

RT398

12

+3.3V_RUN_UT9

+3.3V_RUN_UT9

AUX1_SNOOP_EN#

1K_0402_5%

@

RT137

1 2

20K_0402_5%

1K_0402_5%

12

12

RT138

@

RT302

+3.3V_RUN

1 2

RT397 0_0603_5%@

+3.3V_VDD_PIC

1 2

0_0603_5%

+3.3V_RUN_UT9

C C

RT308 4.7K_0402_5%

MUX1_SSEQ0

B B

10U_0402_6.3V6M

12

0.1U_0201_10V6K
CT118

1

CT117

2

MUX1_DPEQ1

1

2

TBTA_RX1N<28>
TBTA_RX1P<28>

TBTA_RX2N<28>
TBTA_RX2P<28>

USB3_PTX_DRX_P6<10>
USB3_PTX_DRX_N6<10>

0.1U_0201_10V6K
CT119

1

2

SW2_DP1_P0<22>
SW2_DP1_N0<22>

SW2_DP1_P1<22>
SW2_DP1_N1<22>

SW2_DP1_P2<22>
SW2_DP1_N2<22>

SW2_DP1_P3<22>
SW2_DP1_N3<22>

+3.3V_RUN_UT9

1 2

12

0.1U_0201_10V6K

0.1U_0201_10V6K
CT121

CT120

1

2

1 2
1 2

CT103 0.1U_0402_25V6
CT104 0.1U_0402_25V6

1 2
1 2

CT105 0.1U_0402_25V6
CT106 0.1U_0402_25V6

1 2
1 2

CT107 0.1U_0402_25V6
CT108 0.1U_0402_25V6

1 2
1 2

CT109 0.1U_0402_25V6
CT110 0.1U_0402_25V6

1 2
1 2

CT113 0.1U_0402_25V6
CT114 0.1U_0402_25V6

SW2_DP1_HPD<22,26>

f

or pin control , connect to PD GPIO

Check I2C or Pin control

1K_0402_5%

@

RT247

20K_0402_5%

@

1K_0402_5%

12

RT248

RT303

TUSB546: Pop RT246,Depop CT122
PS8740:Depop RT246,Pop CT122

1 2

@

RT246 0_0402_5%

USB3_PTX_C_DRX_P6
USB3_PTX_C_DRX_N6

1 2

@

RT380 0_0402_5%

MUX1_USB_EQ0

12

CT1222.2U_0402_6.3V6M @

+3.3V_CPS_R1

SW2_DP1_P0_C
SW2_DP1_N0_C

SW2_DP1_P1_C
SW2_DP1_N1_C

SW2_DP1_P2_C
SW2_DP1_N2_C

SW2_DP1_P3_C
SW2_DP1_N3_C

AUX1_SNOOP_EN#

+3.3V_RUN_UT9

20
28

10
12

13
15

16
18

19

31
30

39
40

29
32

41

1K_0402_5%

@

RT143

1 2

1K_0402_5%

12

RT144

UT9

1

VCC

6

VCC
VCC
VCC

9

DP0p
DP0n

DP1p
DP1n

DP2p
DP2n

DP3p
DP3n

RX1n
RX1p

RX2n
RX2p

8

SSTXp

7

SSTXn

SNK_CAD/DCI_DAT
HPDIN/DCI_CLK

PAD

TUSB546_QFN40_4X6

20K_0402_5%

@

12

RT304

I2C_EN

DPEQ1

DPEQ0/A1

SSEQ1

SSEQ0/A0

FLIP/SCL

CTL0/SDA

CTL1

TX1n
TX1p

TX2p
TX2n

SSRXp
SSRXn

SBU1
SBU2

AUXp
AUXn

EQ1
EQ0

MUX1_USB_EQ1

35

MUX1_USB_EQ0

38

MUX1_I2C_EN

17

MUX1_DPEQ1

2

MUX1_DPEQ0

14

MUX1_SSEQ1

3

MUX1_SSEQ0

11

MUX1_FLIP_SEL

21

MUX1_USB_SEL

22

MUX1_DP_SEL

23

34
33

37
36

USB3_PRX_C_DTX_P6

5

USB3_PRX_C_DTX_N6

4

TUSB546A_SBU1_R

27

TUSB546A_SBU2_R

26

SW2_DP1_AUXP_C

24

SW2_DP1_AUXN_C

25

MUX1_FLIP_SEL <26>
MUX1_USB_SEL <26>
MUX1_DP_SEL <26>

TBTA_TX1N <28>
TBTA_TX1P <28>

TBTA_TX2P <28>
TBTA_TX2N <28>

12

1 2
1 2

12

12
12

CT111 0.1U_0402_25V6
CT112 0.1U_0402_25V6

RT132 0_0402_5%@
RT133 0_0402_5%@

CT115 0.1U_0402_25V6@
CT116 0.1U_0402_25V6@

MUX1_I2C_EN

I2C Programming or Pin Strap Programming Select,Internally
30k pull-up and 60k pull-down
I2C_EN =
0: Tie 1k to GND,Pin Strap(I2C disable)
R:Tie 20k to GND,TI Test Mode(I2C enabled)
F: Float,TI Test Mode(I2C enabled)

USB3_PRX_DTX_P6 <10>
USB3_PRX_DTX_N6 <10>

TBTA_SBU1 <26,28>
TBTA_SBU2 <26,28>

SW2_DP1_AUXP <22,26>
SW2_DP1_AUXN <22,26>

1:Tie 1k to VCC,I2C enabled

SW2_DP1_AUXN_C

SW2_DP1_AUXP_C

+3.3V_RUN_UT9

1K_0402_5%

1 2

1K_0402_5%

12

1 2

1 2

@

RT145

20K_0402_5%

@

12

RT301

RT300

+3.3V_RUN_UT9

RT131100K_0402_5%

RT130100K_0402_5%

Ser the USB receiver equalizer gain for upstream faci
SSTXP/N,Internally 30k pull-up and 60k pull-down
SSEQ =
0: Tie 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC

+3.3V_RUN_UT9

1K_0402_5%

MUX1_SSEQ1

A A

1 2

1K_0402_5%

12

5

ng

@

RT135

20K_0402_5%

@

12

RT136

RT305

Select the DisplayPort receiver equalizer gain ,Internally
30k pull-up and 60k pull-down
DPEQ =
0: Tie 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC

1K_0402_5%

@

RT139

1 2

20K_0402_5%

@

1K_0402_5%

12

12

RT306

@

RT140

4

Ser the USB receiver equalizer gain for downstream facing
RX1 and RX2 when USB utilized,Internally 30k pull-up and
60k pull-down
USB_EQ =
0: Tie 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC

+3.3V_RUN_UT9+3.3V_RUN_UT9

1K_0402_5%

@

RT141

MUX1_USB_EQ1MUX1_DPEQ0

1 2

20K_0402_5%

@

1K_0402_5%

12

12

RT142

RT307

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number R ev

Size Document Number R ev

Size Document Number R ev

Si

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DP/USB3 Repeater SW TUSB546

DP/USB3 Repeater SW TUSB546

DP/USB3 Repeater SW TUSB546

LA-E082P

LA-E082P

LA-E082P

25 75Monday, December 12, 2016

25 75Monday, December 12, 2016

25 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

+3.3V_TBTA_FLASH+3.3V_TBTA_FLASH

12

12

CT70

TBTA_ROM_HOLD#_PD
TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R

TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R
TBTA_ROM_DO_PD_R
TBTA_ROM_CS#_PD_R

JXT_FP241AH-006GAAM

DIV = R2/(R1+R2)

DIV_mi n DIV _max

0.00 0.0 8

0.10 0.1 8

0.20 0.2 8

0.30 0.3 8

0.40 0.4 8

0.50 0.5 8

0.60 0.6 8

12

.1U_0402_16V7K

8
7
6
5

JDB1

7

GND

8

GND

CONN@

VCC

DO(IO1)

HOLD#(IO3)

WP#(IO2)

CLK
DI(IO0)

W25Q80DVSSIG_SO8

1

TBTA_ROM_CLK_PD_R

1

2

TBTA_ROM_DI_PD_R

2

3

TBTA_ROM_DO_PD_R

3

4

TBTA_ROM_CS#_PD_R

4

5

5

6

6

Factory Device
Config uration

0

1

3

4

5

6

71.0 00.70

UT6

TBTA_ROM_CS#_PD_R

1

TBTA_ROM_DO_PD_R

CS#

2

TBTA_ROM_WP#_PD

3
4

GND

TBTA_ROM_CLK_PD

@

12

RT540_0402_5%

TBTA_ROM_DI_PD

@

12

RT550_0402_5%

TBTA_ROM_DO_PD

@

12

RT560_0402_5%

TBTA_ROM_CS#_PD

@

12

RT570_0402_5%

+3.3V_TBTA_FLASH

Descrip tion

UFP only
5V @0.9A Sink capability with "A sk for Max/" for
anything from 0.9 -3.0A
TBT Alternate Modes not supported
DisplayPort Alternate Modes not supported
TI VID supported

UFP only
5V @0.9A Sink capability with "A sk for Max/" for
anything from 0.9 -3.0A
TBT Alternate Modes not supported

TI VID supported

UFP only
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not s upported
TI VID supported

UFP only
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Mode s -Sin k, C and D pin configuration

DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not supported
TI VID supported
Accepts data and power role swaps , but does not
initiat e.

DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Al ternate Modes - Source, C, D, and E
pin confi gurations.
TI VID supported
Accepts pow er role sw aps but will not initiate.
Accepts data role swap to UFP and can i nitiate.

DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Al ternate Modes - Source, C, D, and E
pin confi gurations.
TI VID supported
Accepts pow er role sw aps but will not initiate.
Accepts data role swap to DFP and can i nitiate.

Infinite boot retry from Flash to Hos t I/F cycles.

RT50

3.3K_0402_5%

D D

C C

B B

A A

RT51

3.3K_0402_5%

12

12

RT52

RT53

3.3K_0402_5%

3.3K_0402_5%

and D pi n confi guration

UPD1_SMBCLK<34>

Route in pass through manner so AUX can be s nooped by

+3.3V_TBTA_FLASH

4

DMN66D0LDW-7_SOT363-6

@

RT58 0_0402_5%

UPD1_SMBDAT<34>

@

1 2
12

10K_0402_1%

43K_0402_1%

12
12

12

12

RT60 0_0402_5%

RT76

PD1_GPIO8

UART_MOSI
UART_MISO

MUX1_FLIP_SEL
MUX1_USB_SEL

TBTA_AUXN_C

TBTA_AUXP_C

UPD1_ALERT#<34>

+3.3V_TBTA_FLASH

RT81 100K_0402_5%
RT82 1M_0402_5%@

MUX1_FLIP_SEL/MUX1_USB_SEL control by:

O: Pop RT69,RT90;Depop RT375,RT376

GPI
I2C:Depop RT69,RT90;pop RT375,RT376

RT95 100K_0402_5%

RT96 100K_0402_5%

+3.3V_VDD_PIC

126

QT1A

@

1 2

DMN66D0LDW-7_SOT363-6

@

RT59 0_0402_5%

1 2

TI is 3x1uf

5

QT1B

@

1 2

RT375 0_0402_5%@
RT376 0_0402_5%@

UPD1_SMBCLK_Q

34

UPD1_SMBUS_ALERT#

1

CT71

2

2.2U_0402_16V6K

MUX1_FLIP_SEL<25>

EN_PD_HV_1<67>
AC1_DISC#<66,6 7>

SW2_DP1_HPD<2 2,25>

MUX1_DP_SEL<25>
MUX1_USB_SEL<25>

1 2
1 2

546

+VCC1V8D_TBTA_LDO

3

UPD1_SMBDAT_Q

+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO
+VCC1V8A_TBTA_LDO

1

1

CT72

2

2

2.2U_0402_16V6K

RT97 0_0402_5%@

+3.3V_VDD_PIC

CT73

2.2U_0402_16V6K

+3.3V_TBTA_FLASH

+3.3V_ALW

MUX1_FLIP_SEL

EN_PD_HV_1

UART_MOSI
UART_MISO

T219@ PAD~D
T220@ PAD~D

MUX1_USB_SEL

UPD1_SMBCLK_Q TBTA_DEBUG1
UPD1_SMBDAT_Q

SW2_DP1_AUXP<22,25>
SW2_DP1_AUXN<22,25>

1 2

PJP7

1 2

PAD-OPEN1x1m

+3.3V_TBTA_FLASH

RT66 3.3K_0402_5%@
RT67 3.3K_0402_5%@
RT68 10K_0402_5%@

RT71 1M_0402_5%

RT74 0_0402_5%@
RT75 0_0402_5%@

USB20_P9<10>
USB20_N9<10>

RT84 0_0402_5%@
RT85 0_0402_5%@

RT86 1M_0402_5%

1 2

RT87 0_0402_5%@

1 2

RT88 0_0402_5%@

1 2

@

1 2

RT89 0_0402_5%

@

RT90 0_0402_5%

1 2

@

1 2

RT92 0_0402_5%

@

RT93 0_0402_5%

1 2

CT80 0.1U_0201_10V6K

1 2

CT81 0.1U_0201_10V6K

+3.3V_TBTA_FLASH

@

RT98

0_0402_5%

1 2

12

@

RT99
0_0402_5%

+5V_ALW

RT378 10K_0402_5%
RT379 10K_0402_5%

12
12
12

12

RT690_0402_5%

12

RT700_0402_5%

12
12

RT720_0402_5%

12

RT730_0402_5%

12
12

12

@
@

@
@

PAD-OPEN 1x3m

1

2

PJP8

1 2

@

RT63 0_0402_5%

CT74

1U_0402_16V6K

12
12

UPD1_SMBDAT_Q
UPD1_SMBCLK_Q
UPD1_SMBUS_ALERT#

MUX1_FLIP_SEL_R
EN_PD_HV_1_R

AC1_DISC#_R
SW2_DP1_HPD_R
OTG_ID
PD1_GPIO6

TBTA_ROM_CS#_PD

12

@

RT830_0402_5 %

12
12

TBTA_MRESET

TBTA_LSTX_R
TBTA_LSRX_R

TBTA_DEBUG3
TBTA_DEBUG4

TBTA_DEBUG2

TBTA_AUXP_C
TBTA_AUXN_C

TBTA_ROSC

12

RT100

15K_0402_1%

TI is 1x47uf+1x0.1uf

1 2

F1
D1

D2
C1

A5
B5
B6

B2
C2

G11
C10
E10
G10

B3

L5

K5
E2

F2
F4

G4

E11

L4

K4

L3

K3

L2

K2

J1
J2

F10

G2

1

1

CT76

CT75

2

2

22U_0805_25V6M

22U_0805_25V6M

+3.3V_VDD_PIC_PDA

H1

UT5

I2C_ADDR
I2C_SDA1

I2C_SCL1
I2C_IRQ1_N

I2C_SDA2
I2C_SCL2
I2C_IRQ2_N

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SS_N

USB_RP_P
USB_RP_N

UART_TX
UART_RX

SWD_DATA
SWD_CLK

MRESET

TBT_LSTX/R2P
TBT_LSRX/P2R

DIG_AUD_P/DEBUG3
DIG_AUD_N/DEBUG4

DEBUG1
DEBUG2

AUX_P
AUX_N

BUSPOWER_N

R_OSC

2

1

For NON-AR port1

1

1

CT78

CT77

2

2

22U_0805_25V6M

22U_0805_25V6M

+5V_ALW_PDA

B1

VDDIO

VIN_3V3

H10

A11

B11

C11

LDO_BMC

GND

G5

GND

GNDH4GND

H5

PP_5V0

PP_5V0

PP_CABLE

GND

GNDF6GNDF7GND

GND

GND

E8

B8

D8

0.22U_0402_16V7K

D11

PP_5V0

PP_5V0

F8

G6

CT87

A2

K1

E1

LDO_1V8A

LDO_1V8D

GND

GND

HRESET

GNDE5GND

F5

E7

A1

E6

D6

12

RT101

100K_0402_5%

+TBTA_Vbus_1

1 2

RT64 0_0402 _5%@

1 2

RT65 0_0402 _5%@

HV_GATE1_A

HV_GATE2_A

A10

B7

GNDA6GNDA7GNDA8GND

A9

B10

HV_GATE1B9HV_GATE2

VBUS
VBUS
VBUS
VBUS

H11
J10
J11
K11

H2

+TBTA_Vbus_1

TI has 1x1uf

12

+3.3V_PDA_VOUT

1

CT82

CT83

2

1U_0603_25V6K

+3.3V_TBTA_FLASH

1U_0402_16V6K

1

CT84

2

10U_0603_6.3V6M

SENSEP

SENSEN

G1

K6

C_USB_TP

L6

C_USB_TN

K7

C_USB_BP

L7

C_USB_BN

L9

C_CC1

L10

C_CC2

WHEN CONNECT BUSPOWERZ TO GND,
CO

NNECT ALSO RPD_ Gn to C_CCn

K9

RPD_G1
RPD_G2

DEBUG_CTL1
DEBUG_CTL2

C_SBU1
C_SBU2

RESET_N

GND

GND

GNDG7GND

SSH7GNDL1GND

TPS65982_BGA96

H8

G8

L11

12

1

RT103

2

0_0402_5%

@

K10

E4
D5

K8
L8

F11

@
@

TBTA_DBG_CTL1
TBTA_DBG_CTL2

TBTA_TOP_P <28>
TBTA_TOP_N <28>

TBTA_BOT_P <28>
TBTA_BOT_N <28>

TI has 2x220pf

1 2
1 2

RT104 0_0402_5%
RT105 0_0402_5%

RT106 10K_0402_5%
RT107 10K_0402_5%

TBTA_SBU1_R

1 2

@

RT108 0_0402_5%

TBTA_SBU2_R

1 2

@

RT109 0_0402_5%

PDA_RESET#_R

1 2
1 2

12

TBTA_CC1 <28>

TBTA_CC2 <28>

+3.3V_TBTA_FLASH

RT1100_0402_5% @

1

2

TBTA_SBU1 <25,28>
TBTA_SBU2 <25,28>

1

CT85

CT86

2

470P_0402_50V7K

470P_0402_50V7K

Link TPS65982D (from SA00 009W200 to SA00009W210) 08/ 04

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Compal Electronics, Inc.

Title

Title

Title

[Type C]PD Controller TI

[Type C]PD Controller TI

[Type C]PD Controller TI

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

LA-E082P

LA-E082P

LA-E082P

1

26 75Monday, December 12, 2016

26 75Monday, December 12, 2016

26 75Monday, December 12, 2016

1.0

1.0

1.0

+5V_ALW

5

4

3

2

1

DT1

+5V_TBT_VBUS

D D

C C

1N4148WS-7-F_SOD323-2

1N4148WS-7-F_SOD323-2

DT3

1 2

1N4148WS-7-F_SOD323-2

1U_0402_10V6K

1

CT93

2

12

DT2

12

+5V_TBTA_VBUS_D

+5V_PD_VDD +3.3V_VDD_PIC

100K_0402_5%

12

3

VOUT

AP2204R-5.0TRG1_SOT89-3

@

1U_0402_10V6K

0.1U_0201_10V6K

RT393

UT8

VCC

GND

1

1

CT89

CT88

2

2

1

2

1 2

RT111 100K_0402_5%

+TBTA_Vbus_1

1U_0603_50V6K

1

CT94

2

UT7

VCC1VOUT

2

GND
EN3ADJ/NC

AP2112K-3.3TRG1_SOT23-5

1

CT90
1U_0402_10V6K

2

5

4

2.2U_0603_25V6K

1

12

CT91

2

place near UT7

0.1U_0402_25V6K

@

CT92

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

[Type C]PD Power

[Type C]PD Power

[Type C]PD Power

LA-E082P

LA-E082P

LA-E082P

27 75Monday, December 12, 2016

27 75Monday, December 12, 2016

27 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For NON AR Config

D D

+TBTA_VBUS+TBTA_VBUS +TBTA_VBUS +TBTA_VBUS

JUSBC1

A1

GND_A1

A2

TX1+

A3

TX1-

A4

VBUS_A4

A5

CC1

A6

D+_A6

A7

D-_A7

A8

SBU1
VBUS_A9
RX2-

RX2+
GND_A12

GND1
GND2
GND3

TOP

A9

A10
A11

A12

1
2
3

12

CT990.47U_0201_25V

TBTA_CC1
TBTA_TOP_P_R

TBTA_TOP_N_R
TBTA_SBU1

12

CT1010.47U_0201_25V

TBTA_TX1P_C
TBTA_TX1N_C

1 2

TBTA_TX1P<25>
TBTA_TX1N<25>

TBTA_TOP_P<26 >

C C

TBTA_TOP_N<26 > TBTA_BOT_P <26>

CT95 0.22U_0201_6.3V6K

1 2

CT96 0.22U_0201_6.3V6K

TBTA_CC1<26>

1 2

@EMI@

1 2

RT120 0_0402_5%

@EMI@

RT121 0_0402_5%

TBTA_RX2N<25>
TBTA_RX2P<25>

B12

GND_B12

B11

RX1+

B10

RX1-

B9

VBUS_B9

SBU2
D-_B7

D+_B6

CC2

Bottom

VBUS_B4

TX2-

TX2+

GND_B1

GND4
GND5
GND6

TBTA_SBU2

B8

TBTA_BOT_N_R

B7

TBTA_BOT_P_R

B6

TBTA_CC2

B5
B4

TBTA_TX2N_C

B3

TBTA_TX2P_C

B2
B1

4
5
6

TBTA_RX1P <25>

TBTA_RX1N <25>

1 2

CT100 0. 47U_0201_25V

TBTA_SBU2 <25,26>

1 2

@EMI@

1 2

RT122 0_0402_5%

@EMI@

RT123 0_0402_5%

TBTA_CC2 <26>TBTA_SBU1<25,26>

1 2

CT102 0. 47U_0201_25V

12P_0402_50V8J

RF@

82P_0402_50V8J

RF@

1

1

CT189

CT190

2

TBTA_BOT_N <26>

12

CT980.22U_0 201_6.3V6K

TBTA_TX2N <25>

12

CT970.22U_0 201_6.3V6K

TBTA_TX2P <25 >

2

2

3

ESD@

L30ESD24VC3-2_SOT23-3

1

DT4

DX07BD24JJ2 LINK DONE

Premium 12/14/15 UMA:Check SBU1/SBU2 connect to PD or PS8740B

DT13

RF Request

DT5

B B

A A

TBTA_TX1P_C

TBTA_TX1N_C

TBTA_CC1

TBTA_SBU1

TBTA_RX2N

TBTA_RX2P

TBTA_TOP_P_R

TBTA_TOP_N_R

ESD@

1 2

ESD8011MUT5G_X3DFN2-2

DT6

ESD@

1 2

ESD8011MUT5G_X3DFN2-2

DT7

ESD@

1 2

ESD8011MUT5G_X3DFN2-2

DT8

ESD@

1 2

ESD8011MUT5G_X3DFN2-2

DT9

ESD@

1 2

ESD8011MUT5G_X3DFN2-2

DT10

ESD@

1 2

ESD8011MUT5G_X3DFN2-2

DT11

ESD@

1 2

ESD8011MUT5G_X3DFN2-2

DT12

ESD@

1 2

ESD8011MUT5G_X3DFN2-2

TBTA_RX1P

TBTA_RX1N

TBTA_SBU2

TBTA_CC2

TBTA_TX2P_C

TBTA_TX2N_C

TBTA_BOT_P_R

TBTA_BOT_N_R

ESD@
1 2

ESD8011MUT5G_X3DFN2-2

DT14

ESD@
1 2

ESD8011MUT5G_X3DFN2-2

DT15

ESD@
1 2

ESD8011MUT5G_X3DFN2-2

DT16

ESD@
1 2

ESD8011MUT5G_X3DFN2-2

DT17

ESD@
1 2

ESD8011MUT5G_X3DFN2-2

DT18

ESD@
1 2

ESD8011MUT5G_X3DFN2-2

DT19

ESD@
1 2

ESD8011MUT5G_X3DFN2-2

DT20

ESD@
1 2

ESD8011MUT5G_X3DFN2-2

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USB 3.0 CONN TYPE C

USB 3.0 CONN TYPE C

USB 3.0 CONN TYPE C

Document Number Re v

Document Number Re v

Document Number Re v

LA-E082P

LA-E082P

LA-E082P

1

28 75Monday, December 12, 2016

28 75Monday, December 12, 2016

28 75Monday, December 12, 2016

1.0

1.0

1.0

5

LINK 50398-04041-001 DONE

JEDP1

1
2
3
4
5
6
7
8

9
10
11
12
13
14

D D

+BL_PWR_SRC

C C

Close to JEDP1.17~19

BIA_PWM

4.7K_0402_5%

12

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

41

36

G1

42

37

G2

43

38

G3

44

39

G4

45

40

G5

ACES_50398-04041-0 01

CONN@

0.1U_0603_50V7K

12

@

CV11

RV1

+5V_TSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

+LCDVDD

Close to JEDP1.30~31 Close to JEDP1.11 C lose to JEDP1.1 Close to JEDP1.10

DV1

1

USB20_N5_R
USB20_P5_R

+BL_PWR_SRC

1 2

LV1

EMI@

DISP_ON

+LCDVDD

TOUCH_SCREEN_DET#
EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C

0.1U_0201_10V6K

1

@

CV12

2

EDP_BIA_PWM

3

BIA_PWM_EC

2

+3.3V_RUN
+3.3V_CAM

CAM_MIC_CBL_DET# <12>

Pin15: LOOP_BACK

EDP_HPD <6>

LCD_TST <34>

LCD_CBL_DET# <9>

TOUCH_SCREEN_PD# <12>

100P_0402_50V8J

12

BIA_PWM

BLM15PX221SN1D_2P

CV1 0.1U_0402_25V6
CV2 0.1U_0402_25V6
CV3 0.1U_0402_25V6
CV4 0.1U_0402_25V6
CV5 0.1U_0402_25V6
CV6 0.1U_0402_25V6

+3.3V_CAM +5V_TSP

100P_0201_25V7K

1

2

EDP_BIA_PWM <6>

BIA_PWM_EC <34>

EMI Request

TOUCH_SCREEN_DET# <12>

12
12
12
12
12
12

RF@

CZ1

12

CA5@EMI@

EDP_HPD

0.1U_0201_10V6K

1

2

@

RF Request

+LCDVDD +3.3V_CAM +BL_PWR_SRC

12P_0402_50V8J

12P_0402_50V8J

B B

1

2

RF@

RF@

82P_0402_50V8J

RF@

1

1

CV22

CV20

CV21

2

2

12P_0402_50V8J

RF@

82P_0402_50V8J

RF@

82P_0402_50V8J

RF@

1

1

2

1

CV24

CV23

CV25

2

2

100P_0402_50V8J

CA6@EMI@

RV7 10 0K_0402_5%@

EDP_AUXN <6>

EDP_AUXP <6>
EDP_TXP0 <6>
EDP_TXN0 <6>
EDP_TXP1 <6>
EDP_TXN1 <6>

CZ2

DISP_ON

12

1 2

4.7K_0402_5%
RV2

4

+3.3V_RUN

+3.3V_RUN

10K_0402_5%

1 2

3

EXC24CQ9 00U_4P

1 2

LV27

EMI@

RV8

34

RF Request

+5V_TSP

12P_0402_50V8J

RF@

1

CV18

2

USB20_N8 <10>

USB20_P8 <10>

82P_0402_50V8J

RF@

1

CV19

2

JIR1

1

IR_CAM_DET# <12>

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_50208-0060N-P0 1

CONN@

Link ACES_50208-0060N-P01 don e

3.3V_TS_EN<9>

TOUCH_PANEL_INTR#:
Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 >> Enable touch events

DMIC0 <33>
DMIC_CLK0 <33>

223

1

3

1

USB20_N8 _R
USB20_P8_R

AZC199-02SPR7G_SOT23-3

@ESD@

DV4

ESD depop locat i on

+LCDVDD

Reserve for EA

100P_0201_25V7K

RF@

1

CA7

2

DV2

3

1

2

TOUCH_SCREEN_DET#

If touch panel, GPIO Low-> Touch Mic. EQ ;
others the GPIO is High -> Non-Touch Mic.
EQ

PANEL_BKLEN <6>

PANEL_BKEN_EC <34>

+PWR_SRC

2

G

2

47K_0402_5%

RV6

1 2

13

D

S

+PWR_SRC

100P_0402_50V8J

RF@

1

CZ3

2

RF Request

L2N7002WT1G_SC-70-3

QV7

1

For 2LANE EDP &5V_TSP

For Breckenridge 14/15

+5V_RUN+5V_RUN +5V_TSP

QV8

LP2301A LT1G_SOT23-3

123

D

S

G

LC

DVDD POWER

WebCAM

+3.3V_CAM +3.3V_RUN

3.3V_CAM_EN#<11>

A A

USB20_P5<10>

5

EXC24CQ9 00U_4P

1 2

LZ1

EMI@

QZ1

LP2301A LT1G_SOT23-3

123

D

S

G

USB20_P5_R

34

USB20_N5_R

Backlight POWER

+PWR_SRC

1000P_0402_50V7K

270K_0402_5%

CV13

RV4

1 2

1 2

BL_PWR_SRC_ON

0.01U_0402_50V7K

1

2

4

CV14

1 2

RV5 47K_0402_5%

EN_INVPWR<34>USB20_N5<10>

S

4 5

3

QV1

D

6
2

1

G

AO6405_ TSOP6

QV2

L2N7002 WT1G_SC-70-3

123

D

S

G

+BL_PWR_SRC

12

0.1U_0603_50V7K

CV15

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+LCDVDD +EDP_VDD

CV16

@

12

10U_060 3_10V6M

LCD_VCC_TEST_EN<34>

ENVDD_PCH<6,34>

2

PJP12

1 2

PAD-OPEN1 x1m

BAT54CW_SOT323-3

+3.3V_ALW

UV24

1

VOUT

2

GND

3

/OC

DV3

2

3

G524B1T11U_SOT23-5

1

EN_LCDPWR

5

VIN

4

EN

0.01UF_0402_25V7K

@

CV17

12

100K_0402_5%

RV3

1 2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

eDP CONN & Touch screen

eDP CONN & Touch screen

eDP CONN & Touch screen

Document Number Re v

Document Number Re v

Document Number Re v

LA-E082P

LA-E082P

LA-E082P

1

29 75Monday, December 12, 2016

29 75Monday, December 12, 2016

29 75Monday, December 12, 2016

1.0

1.0

1.0

5

+3.3V_LAN

RL1@ 10K_0402_5%
RL2@ 10K_0402_5%
RL4 4.7K_0402_5%@

D D

PM_LANPHY_ENABLE<11>

+0.9V_LAN

22U_0603_6.3V6M

1

12

CL12

2

Note:
+1.0V_LAN will work at 0.95V to 1.15V

C C

TP_LAN_JTAG_TMS

12

TP_LAN_JTAG_TCK

12

CLKREQ_PCIE#4

12

+3.3V_LAN

1 2

@

RL7 0_0402_5%

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
CL9

1

2

0.1U_0201_10V6K

CL11

CL10

CL8

1

1

2

2

1 2

12

XTALO_R

27P_0402_50V8J

12

CL13

PCIE_PRX_DTX_P9<10>

PCIE_PRX_DTX_N9<10>

10K_0402_5%

RL5 @

10K_0402_5%

RL9@

1 2

@

RL34 0_0402_5%

YL1

3

OUT

4

GND

GND

25MHZ_18PF_7V25000034

CLKREQ_PCIE#4<11>

PLTRST_LAN#<11 >

CLK_PCIE_P4<11>
CLK_PCIE_N4<11>

PCIE_PTX_DRX_P9<10>

PCIE_PTX_DRX_N9<10>

SML0_SMBCLK<8>

SML0_SMBDATA<8>

LAN_WAKE#<11,34>

SMBus Device Address 0xC8

T88@ PAD~D
T89@ PAD~D

12

1

IN

2

12

CLKREQ_PCIE#4

PCIE_PRX_C_DTX_P9

1 2

CL1 0.1U_0402_25V6

PCIE_PRX_C_DTX_N9

1 2

CL2 0.1U_0402_25V6

PCIE_PTX_C_DRX_P9

1 2

CL5 0.1U_0402_25V6

PCIE_PTX_C_DRX_N9

1 2

CL6 0.1U_0402_25V6

RL11
1M_0402_5%

27P_0402_50V8J

CL14

LAN_DISABLE#_R

LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#

TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK

LAN_TEST_EN

3.01K_0402_1%

1K_0402_5%

12

12

RL13

RL12

4

UL1

48

CLK_REQ_N

36

PE_RST_N

44

PE_CLKP

45

PE_CLKN

38

PETp

39

PETn

41

PERp

42

PERn

28

SMB_CLK

31

SMB_DATA

2

LANWAKE_N

3

LAN_DISABLE_N

26

LED0

27

LED1

25

LED2

32

JTAG_TDI

34

JTAG_TDO

33

JTAG_TMS

35

JTAG_TCK

9

XTALO

XTAL_OUT

10

XTALI

XTAL_IN

30

TEST_EN

12

RBIAS

WGI219LM-QREF- A0_QFN48_6X6~D

change to SA000081G0L, S IC A32 WGI219LM QREF A0 QFN 48P PHY

PCIE

SMBUS

JTAG LED

MDI_PLUS0

MDI_MINUS0

MDI_PLUS1

MDI_MINUS1

MDI_PLUS2

MDI

MDI_MINUS2

MDI_PLUS3

MDI_MINUS3

SVR_EN_N

RSVD_VCC3P3_1

VDD3P3_IN

VDD3P3_4

VDD3P3_15
VDD3P3_19
VDD3P3_29

VDD0P9_47
VDD0P9_46
VDD0P9_37

VDD0P9_43
VDD0P9_11
VDD0P9_40

VDD0P9_22
VDD0P9_16

VDD0P9_8

CTRL0P9

VSS_EPAD

Place CL3, CL4 and LL1 close to UL1

LAN_MDIP0

13

LAN_MDIN0

14

LAN_MDIP1

17

LAN_MDIN1

18

LAN_MDIP2

20

LAN_MDIN2

21

LAN_MDIP3

23

LAN_MDIN3

24

6

+RSVD_VCC3P3_1

1
5
4
15

19
29

47
46
37

43
11
40

22
16
8

+REGCTL_PNP10RE S_BIAS

7
49

VCT_LAN_R1

Layout Not i ce : Pl ace bead as
close UL4 as possible

1 2

RL71 2.2_0603_5%

1 2

RL72 2.2_0603_5%

1 2

RL73 2.2_0603_5%

1 2

RL74 2.2_0603_5%

1 2

RL75 2.2_0603_5%

1 2

RL76 2.2_0603_5%

1 2

RL77 2.2_0603_5%

1 2

RL78 2.2_0603_5%

1 2

+3.3V_LAN_OUT

12

+0.9V_LAN

1 2

Idc_min=5 00mA
DCR=100 mohm

0.1U_0201_10V6K
CL7

LL14.7UH_BRC2012T4R7MD_20%

@

1

2

1

2

3

RL30_0402_5%

22U_0805_6.3V6M

CL28

+0.9V_LAN

0.1U_0201_10V6K
CL3

12

LAN_MDIP0_L
LAN_MDIN0_L

LAN_MDIP1_L
LAN_MDIN1_L

LAN_MDIP2_L
LAN_MDIN2_L

LAN_MDIP3_L
LAN_MDIN3_L

1 2

RL64.7K_0402_5%

1 2

@

RL80_0603_5%

Place C L28 close to UL1.5

10U_0603_10V6M

@

CL4

+3.3V_LAN

+3.3V_LAN

RF Request

+3.3V_LAN_OUT

@RF@

12P_0402_50V8J

1

CL29

2

LAN_ACTLED_YEL#

RJ45_MDIN3
RJ45_MDIP3
RJ45_MDIN1
RJ45_MDIN2
RJ45_MDIP2
RJ45_MDIP1
RJ45_MDIN0

RJ45_MDIP0
LED_10_GRN#
LED_100_ORG#

2

@RF@

82P_0402_50V8J

1

CL30

2

12

LAN_ACTLED_YEL_R#

1 2

RL14 150_040 2_5%

1 2

RL19 150_0402_5%

1 2

RL20 150_0402_5%

LED_10_GRN_R#
LED_100_ORG_R#

1

+3.3V_LAN

470P_0402_50V7K

0.1U_0201_10V6K

1

CL18

CL19

2

RJ45 LOM circuit

+3.3V_LAN:20mils

JLOM1

CONN@

10

Yellow LED-

9

Yellow LED+

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

11

Green LED-

13

Orange LED-

12

Green-Orange LED+

SANTA_130456-831

GND_2
GND_1

15
14

When LAN & WLAN are exist at the same time , WLAN will disable

+3.3V_LAN

CL15

@

1 2

0.1U_0201_10V6K

LOM_SPD100LED_ORG#

B B

A A

LOM_SPD10LED_GRN#

LOM_ACTLED_YEL#

+3.3V_LAN

12

RL29
1M_0402_5%

LOM_SPD100LED_ORG#

+3.3V_LAN

12

RL30
1M_0402_5%

LOM_SPD10LED_GRN#

For W LAN can't recognize during enable
Unobtrusive mode(BITS152312)

5

1

P

B

2

A

G

3

QL1A

DMN65D8LDW-7_SOT363-6

126

SYS_LED_MASK#

QL1B

DMN65D8LDW-7_SOT363-6

34

5

SYS_LED_MASK#

QL2A

DMN65D8LDW-7_SOT363-6

126

SYS_LED_MASK#

QL2B

DMN65D8LDW-7_SOT363-6

34

5

4

O

UL2

TC7SH08FU_SSOP5~D

LAN_ACTLED_YEL#

SYS_LED_MASK# <34,46>

LED_100_ORG#

LED_10_GRN#

LOM_CABLE_DETECT# <3 4>

12

CL16 0.1U_0201_10V6K

12

CL17 0.1U_0201_10V6K

12

CL20 0.1U_0201_10V6K

12

CL21 0.1U_0201_10V6K

LAN_MDIN3_L
LAN_MDIP3_L

LAN_MDIN1_L
LAN_MDIP1_L

LAN_MDIN2_L
LAN_MDIP2_L

LAN_MDIN0_L
LAN_MDIP0_L

GND

GND

ASSIS

CHASSIS

CH

TL1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+
TD4-12MX4-

1 2

CL22 10P_1808_3KV8JEMI@

MCT1
MX1+

MX1­MCT2
MX2+

MX2­MCT3
MX3+

MX3­MCT4
MX4+

350UH_IH-160

24

RJ45_MDIN3

23

RJ45_MDIP3

22
21

RJ45_MDIN1

20

RJ45_MDIP1

19
18

RJ45_MDIN2

17

RJ45_MDIP2

16
15

RJ45_MDIN0

14

RJ45_MDIP0

13

+GND_CHASSIS

use 40mil trace if necessary

Z2808

Z2806

Z2807

Z2805

12

12

12

12

RL16 75_0402_1%

RL15 75_0402_1%

RL17 75_0402_1%

RL18 75_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

ADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

TR

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTE N CONSENT.

2

Title

LAN Clarkvillie & RJ45

LAN Clarkvillie & RJ45

LAN Clarkvillie & RJ45

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R e

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

LA-E082P

LA-E082P

LA-E082P

1

30 75Monday, December 12, 2016

30 75Monday, December 12, 2016

30 75Monday, December 12, 2016

1.0

1.0

1.0

v

A

B

C

D

E

For PCIE Interface

1 1

+3.3V_MMI_IN+3.3V_RUN

PJP14

+3.3V_MMI_AUX

RR19 10K_0402_5%

1 2

PAD-OPEN1x2m

1 2

12

+3.3V_MMI_AUX+3.3V_MMI_IN

R2740_0603_5% @

MEDIACARD_IRQ#

support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/of f 3V3A UX)

7/18 Vender suggest.

PCH_PLTRST#_AND< 11,32,37,40>

CLKREQ_PCIE#5<11>

CLK_PCIE_P5<11>
CLK_PCIE_N5<11>

1 2

PCIE_PTX_DRX_P1<10>

PCIE_PTX_DRX_N1<10>
PCIE_PRX_DTX_P1<10>
PCIE_PRX_DTX_N1<10>

CR11 0.1U_0402_25V6
CR12 0.1U_0402_25V6
CR13 0.1U_0402_25V6
CR14 0.1U_0402_25V6

+1.2V_LDO

CR13 close to UR2.10
C

R9 CR10 close to UR2.14

0.1U_0201_10V6K

4.7U_0603_6.3V6K

1

CR5

12

2

1 2
1 2
1 2

CR6

MEDIACARD_IRQ#<9>

0.1U_0201_10V6K

+1.8V_RUN_CARD

1

CR7

2

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1
PCIE_PRX_C_DTX_P1
PCIE_PRX_C_DTX_N1

SD/MMCCD#

12

+RREF

RR4

1

2

32
31
30

10
14

13

6.2K_0402_1%

+3.3V_MMI_AUX

4.7U_0402_6.3V6M

1

CR1

2

UR1

1

PERST#

2

CLK_REQ#

5

REFCLKP

6

REFCLKN

3

HSIP

4

HSIN

7

HSOP

8

HSON

WAKE#
MS_INS#
SD_CD#

AV12
DV12S

SD_VDD2

9

RREF

0.1U_0201_10V6K

CR2

27

RTS5242

33

11

3V3aux

E-PAD

CARD_3V3

3V3_IN

SD_LN1_P

SD_LN1_M

SD_LN0_P

SD_LN0_M

+3.3V_MMI_IN

10U_0402_6.3V6M

0.1U_0201_10V6K
CR4

1

1

CR3

2

2

12
18

DV33_18

15

SD/MMCDAT1/RCLK-

SP1

16

SD/MMCDAT0/RCLK+

SP2

17

SD/MMCCLK

SP3

19

SD/MMCCMD

SP4

20

SD/MMCDAT3

SP5

21

SD/MMCDAT2

SP6

29

SDWP

SP7

SD_UHS2_D1P

22

SD_UHS2_D1N

23

SD_UHS2_D0P

26

SD_UHS2_D0N

25
24

+SDREG2

SDREG2

28

GPIO

RTS5242-GR_QFN32_4X4

+DV33_18

SD_GPIO

+3.3V_RUN_CARD

@
@

@EMI@

@
@
@

7/18 Vender suggest

1 2

CR15

1U_0402_6.3V6K

12

RR310K_0402_5%

1 2

CR22 1U_0402 _6.3V6K

1 2
1 2

RR9 0_0402_5%

1 2

RR10 0_0402_5%

1 2

RR5 0_0402_5%

1 2

RR6 0_0402_5%

1 2

RR7 0_0402_5%
RR8 0_0402_5%

+3.3V_MMI_AUX

SD/MMCDAT1/RCLK-_R
SD/MMCDAT0/RCLK+_R

SD/MMCCLK_R
SD/MMCCMD_R
SD/MMCDAT3_R
SD/MMCDAT2_R

@EMI@

5P_0402_50V8C

12

CR21

EMI depop locat i on

RF Request

+3.3V_MMI_IN+3.3V_MMI_AUX

@RF@

@RF@

@RF@

12P_0402_50V8J

82P_0402_50V8J

1

1

CR27

CR28

2

2

2 2

@RF@

12P_0402_50V8J

82P_0402_50V8J

1

1

CR25

CR26

2

2

3 3

QR1

HOST_SD_W P#

4 4

High

Low

SDWP _Q SDWP

High

High

Low

Low

High

High

Low

High

STATUS

Write Protect(SD LOCK)

Write Enable

Write Protect(SD& FW LOCK)

Write Protect(FW LOCK)

HOST_SD_WP#<12>

L2N7002WT1G_SC-70-3

SDWP_Q

1 3

D

SDWP

S

G

2

+3.3V_RUN_CARD +1.8V_RUN_CARD

2

CR17

1 2

CR18

1

0.1U_0201_10V6K

4.7U_0603_6.3V6K

CR38,CR39 n ear JSD1.4 CR40,CR41 near JSD1.14

JSD1

CONN@

+3.3V_RUN_CARD
+1.8V_RUN_CARD

2

CR19

CR20

1 2

1

0.1U_0201_10V6K

4.7U_0603_6.3V6K

SD/MMCCMD_R
SD/MMCCLK_R

SD/MMCCD#
SDWP_Q

SD/MMCDAT0/RCLK+_R
SD/MMCDAT1/RCLK-_R
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N

4

VDD/VDD1

14

VDD2

2

CMD

5

CLK

18

CARD DETECT

19

WRITE PROTEC

7

DAT0/RCLK+

8

DAT1/RCLK-

9

DAT2

1

CD/DAT3

11

D0+

12

DO-

16

D1+

15

D1-

3

VSS1

6

VSS2

10

VSS3

13

VSS4
VSS517GND7

T-SOL_156-2000302608_NR

GND1
GND2
GND3
GND4
GND5
GND6

20
21
22
23
24
25
26

LINK SP070011U00 DONE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THIRD

A

B

C

PARTY WITHOUT DE LL'S EXPRESS WRITTE N CONSENT.

D

Title

Size

Size

Size

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Card Reader RTS5242

Card Reader RTS5242

Card Reader RTS5242

Document Number R ev

Document Number R ev

Document Number R

LA-E082P

LA-E082P

LA-E082P

E

31 75Monday, December 12, 2016

31 75Monday, December 12, 2016

31 75Monday, December 12, 2016

ev

1.0

1.0

1.0

5

4

3

2

1

+3.3V_WW AN

WWAN_P WR_EN

12

RZ43 47K_0402_5%

D D

C C

+3.3V_WW AN

33P_0402_50V8J

.047U_0402_16V7K

.047U_0402_16V7K

12

12

CZ17

B B

UIM_CLK

A A

22U_0603_6.3V6M

CZ20

12

12

CZ19

CZ18

USB3_PRX_DTX_P2<10>

USB3_PRX_DTX_N2<10>

USB3_PTX_DRX_P2<10> USB20_P4<10>

USB3_PTX_DRX_N2<10>

SIM Card Push-Push

+SIM_PWR

4.7U_0402_6.3V6M

UIM_RESET

12

UIM_CLK

CZ37

100P_0402_50V8J

RF@

12

33P_0402_50V8J

12

CZ21

JSIM1

1

VCC

2

RST

3

CLK

4

RFU1

10

GND

11

GND

12

GND

13

GND

T-SOL_5-991503004000-6

T-SOL_5-991503004000-6 LINK DON

47P_0402_50V8J

@RF@

12

CZ38

51_0402_5%

@RF@

12

RZ334

5

SLOT2_CONFIG_3<34>

CZ198

SLOT2_CONFIG_0<34>
WWAN_W AKE#<34>

SLOT2_CONFIG_1<34>

SLOT2_CONFIG_2<34>

RF Request

+3.3V_WW AN

2000P_0402_50V7K

47P_0402_50V8J

100P_0402_50V8J

RF@

RF@

100U_B2_6.3VM_R35M

RF@

1

12

12

12

CZ23

USB3_PTX_C_DRX_P2

12

CI30 0.1U_0402_25V6

USB3_PTX_C_DRX_N2

12

CI29 0.1U_0402_25V6

CONN@

5

GND

6

VPP

7

I/O

8

RFU2

9

DTSW

14

GND

15

GND

16

GND

+SIM_PWR

12

UIM_DATA UIM_RESET

12

15K_0402_5%

33P_0402_50V8J

UIM_DATA

SIM_DET

@RF@

RZ335

@RF@

CZ39

+

CZ25

CZ24

2

RF@

CZ26

NGFF slot B Key B

JNGFF2

1

1

3

3

USB20_P4_L
USB20_N4_L

RZ326 0_0402_5%@RF@

USB3_PRX_L_DTX_N2
USB3_PRX_L_DTX_P2

USB3_PTX_L_DRX_N2
USB3_PTX_L_DRX_P2

T225PAD~D @

1 2

RI27 0_0402_5%@RF@

1 2

HCM1012GH900BP_4P

1 2

RI28 0_0402_5%@RF@

1 2

RI29 0_0402_5%@RF@
LI17

RF@

1 2

HCM1012GH900BP_4P

1 2

RI30 0_0402_5%@RF@

33P_0402_50V8J

@RF@

12

CZ40

5

5

7

7

9

9

11

11

13

13

15

15

12

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

GND

BELLW_80149-4221 LINK DON

BELLW_80149-4221

USB3_PRX_L_DTX_N2

34

USB3_PTX_L_DRX_P2

USB3_PTX_L_DRX_N2

34

CONFIG_0 CONFIG_21CONFIG_3

STATE #

0 GND

8
14

E

15

+SIM_PWR

0.1U_0402_25V6

RF@

1

CZ41

2

RF Request

4

CONN@

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

GND

WWAN_RADIO_DIS#<34>

HW_GPS_DISABLE#<34>

CONFIG_1

GND

GND

HIGH
GND
GND

HIGH
HIGH HIGH

+3.3V_WW AN

WWAN_P WR_EN

WWAN_RADIO_DIS#_R

SLOT2_SATA_LED#

HW_GPS_DISABLE#_R

ISH_I2C2_SCL_R
ISH_I2C2_SDA_R

PCH_PLTRST#_AND

RZ131 0_0402_5%@
RZ132 0_0402_5%@

WWAN_COEX3
WWAN_COEX2
WWAN_COEX1

USB20_N4<10>

UIM_RESET
UIM_CLK
UIM_DATA

PCIE_WAKE#

SIM_DET

E

GND
GND
GND
HIGH
HIGH

RN101 0_0402_5%@

RZ76 0_0402_5%@
RZ77 0_0402_5%@

1 2

+SIM_PWR

SATALED# <10,40,46>

12

ISH_I2C2_SCL <9>

12

ISH_I2C2_SDA <9>

9/24: Reserve for embedded locat i on , refer I nt el PD G 0

12
12

RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

1 2

RZ128 0_0201_5%@RF@

1 2

RZ129 0_0201_5%@RF@

1 2

RZ130 0_0201_5%@RF@

1 2

DZ5

1 2

DZ6

RI47 0_0402_5%@RF@

LI8

RF@

1 2

MCM1012B900F06BP_4P

PORT80_DET# <34>

HOST_DEBUG_TX <34,35>

WWAN_RADIO_DIS#_R

HW_GPS_DISABLE#_R

1 2

34

1 2

RI48 0_0402_5%@RF@

WLAN_COEX3
WLAN_COEX2
WLAN_COEX1

Module Type

GND

SSD-SATA

GND

SSD-PCIE(2 lane)

GNDHIGH
HIGH
HIGH

WWAN

HCA-PCIE(1 lane)

NA

USB20_P4_L

USB20_N4_L

M3042_PCIE#_SATA

High
Low
Low
Low
Low

3

. 9

WLAN

WIGI

USB20_P7_L
USB20_N7_L

SW2_DP2_HPD<22>

1 2

RB751S40T1G_SOD523-2

1 2

RB751S40T1G_SOD523-2

SW2_DP2_N3_C
SW2_DP2_P3_C

SW2_DP2_N2_C
SW2_DP2_P2_C

PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3

PCIE_WAKE#

PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4

DZ1

DZ2

RI49 0_0402_5%@RF@

MCM1012B900F06BP_4P

1 2

LI9

RF@

2

SW2_DP2_N3<22>
SW2_DP2_P3<22>

SW2_DP2_N2<22>
SW2_DP2_P2<22>

PCIE_PTX_DRX_P3< 10>
PCIE_PTX_DRX_N3<10>

PCIE_PTX_DRX_P4< 10>
PCIE_PTX_DRX_N4<10>

WLAN_WIGIG60GHZ_DIS#<34>

BT_RADIO_DIS#<34>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTE N CONSENT.

1 2
1 2

CV145 0.1U_0402_25V6
CV146 0.1U_0402_25V6

1 2
1 2

CV148 0.1U_0402_25V6
CV147 0.1U_0402_25V6

1 2

CZ12 0.1U_0402_25V6

1 2

CZ13 0.1U_0402_25V6

PCIE_PRX_DTX_P3< 10>
PCIE_PRX_DTX_N3<10>

CLK_PCIE_P1<11>
CLK_PCIE_N1<11>

CLKREQ_PCIE#1<11>

PCIE_WAKE#<35,40>

1 2

CZ14 0.1U_0402_25V6

1 2

CZ15 0.1U_0402_25V6

PCIE_PRX_DTX_P4< 10>
PCIE_PRX_DTX_N4<10>

CLK_PCIE_P2<11>
CLK_PCIE_N2<11>

USB20_P7<10>

USB20_N7<10>

for Brekenridge 14/15 DSC

NGFF slot A Key A

CONN@

PWR
Rail

+3.3V

+3.3V_WLAN

2

2

4

4

6

6

8

8

10

SW2_DP2_AUXN_C

10

12

SW2_DP2_AUXP_C

12

14

14

16

SW2_DP2_N1_C

16

18

SW2_DP2_P1_C

18

20

20

22

SW2_DP2_N0_C

22

24

SW2_DP2_P0_C

24

26

26

28

28

30

30

32

32

34

WLAN_COEX3

34

36

WLAN_COEX2

36

38

WLAN_COEX1

38

40
42
44
46
48
50
52
54
56
58
60
62
64
66

68

WIGIG_32KHZ
PCH_PLTRST#_AND
BT_RADIO_DIS#_R

WLAN_WIGIG60GHZ_DIS#_R

ISH_UART0_RXD_R
ISH_UART0_TXD_R
ISH_UART0_CTS#_R
ISH_UART0_RTS#_R
PCH_PLTRST#_AND

PCIE_WAKE#

9/24: Reserve for embedded locat i on , refer I nt el PD G 0. 9

40
42
44
46
48
50
52
54
56
58
60
62
64
66

GND

E

0.1U_0201_10V6K

0.01UF_0402_25V7K

1

12

CZ30

CZ28

2

RF Request

+3.3V_WLAN

15P_0402_50V8J

15P_0402_50V8J

RF@

RF@

12

12

CZ33

CZ34

Power Rating TBD

Voltage
Toleranc e

Primary Power Aux Power

Peak Normal Normal

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R e

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

12

JNGFF1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

GND

BELLW_80148-4221

BELLW_80148-4221 LINK DON

WLAN_WIGIG60GHZ_DIS#_R

BT_RADIO_DIS#_R

RF

Request

1 2

USB20_P7_L

34

USB20_N7_L

1 2

RI50 0_0402_5%@RF@

12

SW2_DP2_AUXN <22>

12

CV1500.1U_0402_ 25V6

SW2_DP2_AUXP <22>

CV1490.1U_0402_ 25V6

12

SW2_DP2_N1 <22>

12

CV1520.1U_0402_ 25V6

SW2_DP2_P1 <22>

CV1530.1U_0402_ 25V6

12

SW2_DP2_N0 <22>

12

CV1560.1U_0402_ 25V6

SW2_DP2_P0 <22>

CV1570.1U_0402_ 25V6

PCH_CL_RST1# <8>

PCH_CL_DATA1 <8>

PCH_CL_CLK1 <8>

0_0402_5%

PCH_PLTRST#_AND <11,31,37,40>

RZ78 0_0402_5%@
RZ79 0_0402_5%@
RZ80 0_0402_5%@
RZ81 0_0402_5%@

CLKREQ_PCIE#2 <11>

10U_0603_10V6M

1

CZ27

2

Place near JNGFF1.2/JNGFF1.4Place near JNGFF1.72/JNGFF1.74

15P_0402_50V8J

15P_0402_50V8J

RF@

12

CZ35

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

12
12
12
12

0.01UF_0402_25V7K

1

12

CZ29

2

RF@

CZ36

NGFF Card

NGFF Card

NGFF Card
LA-E082P

LA-E082P

LA-E082P

1

@

RZ56

12

0.1U_0201_10V6K

12

CZ31

SUSCLK <11,40>

ISH_UART0_RXD <9>
ISH_UART0_TXD <9>

ISH_UART0_CTS# <9>

ISH_UART0_RTS# <9>

4.7U_0603_6.3V6K

CZ32

32 75Monday, December 12, 2016

32 75Monday, December 12, 2016

32 75Monday, December 12, 2016

1.0

1.0

1.0

v

5

1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per uni t, there are tw o transducer units in one speaker box.)

Internal Speakers Header

40 mils trace keep 20 mil spacing

1 2

LA6 BLM15PD800SN1D_2PEMI@

1 2

INT_SPK_R+
INT_SPK_R-

D D

1000P_0402_50V7K

12

LA7 BLM15PD800SN1D_2PEMI@

1 2

LA8 BLM15PD800SN1D_2PEMI@

1 2

LA9 BLM15PD800SN1D_2PEMI@

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

12

12

12

CA19@EMI@

CA23@EMI@

CA22@EMI@

CA24@EMI@

INT_SPKR_L+INT_SPK_L+
INT_SPKR_L-INT_SPK_L­INT_SPKR_R+
INT_SPKR_R-

L03ESDL5V0CC3-2_SOT23-3

2

2

3

@ESD@

DA6

1

1

CONN@

JSPK1

1

1

2

2

3

3

4

4

5

L03ESDL5V0CC3-2_SOT23-3

G1

6

3

G2

@ESD@

ACES_50278-00401-001

Link 50278-00401-001 DONE

DA7

Close to UA1

Close to UA1 pin6

HDA_BIT_CLK_R

33_0402_5%

12

RA17@EMI@

10P_0402_50V8J

12

C C

CA33@EMI@

+3.3V_RUN_AUDIO

Place closely to Pin 14.

AUD_HP_NB_SENSE

12

place close to UA1 pin3

100K_0402_1%

12

RA59

200K_0402_1%

12

RA60

DMIC_CLK0

10P_0402_50V8J

CA54@EMI@

+3.3V_RUN_AUDIO

0.1U_0402_25V6

12

@

CA41

Add for solve
pop noise and
detect issue

4

+3.3V_RUN_AUDIO

1 2

1U_0603_10V6K

12

LA12 BLM15PX600SN1D_2P

12

LA14 BLM15PX600SN1D_2P

0.1U_0201_10V6K

1

2

place close to pin1

HDA_SYNC_R<12>

HDA_BIT_CLK_R<12>

HDA_SDOUT_R<12>

RA52100K_0402_5%

12

RA1810K_0402_5%

12

CA31

+3.3V_RUN_AUDIO

HDA_BIT_CLK_R

P

lace R A9 close to codec

HDA_SDIN0<12>

DMIC0<29>

DMIC_CLK0 DMIC_CLK_CODEC

DMIC_CLK0<29>

PD#

10U_0603_10V6M

CA10

CA61

12

HDA_SDOUT_R
HDA_SDIN0_R

1 2

RA9 33_0402_5 %

1 2

RA14EMI@ 22_0402_5%

INT_SPK_L+
INT_SPK_L­INT_SPK_R­INT_SPK_R+

AUD_SENSE_A
AUD_SENSE_B

1 2

RA61 100K_0402_1%

1

2

12

12

RA44100K_0402_5%

12

CA5110U_0603_10V6M

12

CA5210U_0603_10V6M
CA5310U_0603_10V6M

3

+3.3V_RUN_AUDIO_IO

10U_0603_10V6M

0.1U_0201_10V6K
CA56

CA55

12

lace close to pin9

p

+3.3V_RUN_AUDIO_DVDD

1

41

9

UA1

DVDD

11

I2C_SDA

12
10

6
5
8

4
2

3
47
48

27
39

7

42
43
44
45

13
14
15

DVDD-IO

I2C_SCL
SYNC

BIT-CLK
SDATA-OUT
SDATA-IN

EAPD/DC DET
GPIO0/DMIC-DATA12
GPIO1/DMIC-CLK
PDB
SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/ MIC-GPI

LDO1-CAP
LDO2-CAP
LDO3-CAP

SPK-L+
SPK-L­SPK-R­SPK-R+

HP/LINE1 JD1
MIC2/LINE2 JD2
SPDIFO/FRONT JD3/GPIO3

+5V_RUN_PVDD_L

26

46

AVDD1

PVDD1

PVDD2

lace close to pin41

0.1U_0201_10V6K

1

2

36

40

AVDD2

CPVDD

LINE1-VREFO-L

LINE1-VREFO-R

MIC2-VREFO

CPVEE

MIC2-L/RING2

MIC2-R/SLEEVE

MIC-CAP

LINE2-L
LINE2-R
LINE1-L
LINE1-R

PCBEEP
HP-OUT-L
HP-OUT-R

AVSS1
AVSS2

THERMAL PAD

place close to pin46p

10U_0603_10V6M

CA45

1

1

CA46

2

2

+VDDA_AVDD1

+1.8V_RUN_AUDIO

31

+LINE1-VREFO-L

30

+LINE1-VREFO-R

29

+MIC2-VREFO

28

VREF

35

CBN

37

CBP

20

5VSTB

34

SLEEVE/RING2 please keep 40 mils trace width

17

RING2

18

SLEEVE

19
24
23

LINE1_L HP_OUT_L

22

LINE1_R

21

AUD_PC_BEEP

16

HP_OUT_L AUD_HP_OUT_L

32

HP_OUT_R

33
25

38
49

1 2

HCB2012VF-601T20_2P

10U_0603_10V6M

0.1U_0201_10V6K
CA47

1

CA48

2

place close to pin26

10U_0603_10V6M

12

place close to pin40

10U_0603_10V6M

12

1 2

RA57 4.7K_0402_5%

1 2

RA58 4.7K_0402_5%

1 2

CA35 2.2U_0402_6.3V6M

12

CA29 1U_0603_10V6K

1 2

RA53 0_0402_5%@

@

1 2

RA54 0_0402_5%

1 2

CA49 1U_0603_10V6K

LA13

600 Ohm/2A

1

CA9

2

CA58

1

2

AUD_PC_BEEP

1 2

1 2
1 2

1 2
1 2

0.1U_0201_10V6K
CA60

1

2

LA5

1 2

0.1U_0201_10V6K

BLM15PX600SN1D_2P

CA8

1 2

@

RA3 0_0603_5%

0.1U_0201_10V6K
CA57

Place CA29 close to Codec

+5V_ALW
+RTC_CELL

CA2510U_0603_10V6M

HP_OUT_R

CA4310U_0603_10V6M
CA4410U_0603_10V6M

AUD_HP_OUT_R

RA716.2_04 02_1%
RA816.2_04 02_1%

2

+5V_RUN_AUDIO

10U_0603_10V6M

1

CA59

2

+5V_RUN_AUDIO

+1.8V_RUN

AUD_HP_OUT_L
AUD_HP_OUT_R

AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

12
12

CA27 0.1U_0402_25V6
CA28 0.1U_0402_25V6

AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

+MIC2-VREFO

SPKR_R
BEEP_R

SPKR_R

1 2
1 2

1 2
1 2

RING2
SLEEVE

RA5 2.2K _0402_5%
RA6 2.2K _0402_5%

RA12 1K_0402_5%
RA13 1K_0402_5%

12

SPKR <12>
BEEP <34>

100P_0402_50V8J

12

CA72@

1

10K_0402_5%

@

RA51

+1.8V_RUN_AUDIO

33P_0402_50V8J

1

2

BEEP_R

100P_0402_50V8J

10K_0402_5%

@

12

12

CA62@

RA45

RF Request

+5V_RUN_AUDIO

12P_0402_50V8J

RF@

68P_0402_50V8J

RF@

1

1

CA63

CA64

2

2

RF Request

+1.8V_RUN

RF@

CA69

12P_0402_50V8J

RF@

1

CA65

2

RF Request

+3.3V_RUN_AUDIO

12P_0402_50V8J

RF@

1

CA67

2

68P_0402_50V8J

RF@

1

CA66

2

68P_0402_50V8J

RF@

1

CA68

2

CLASS-D POWER DOWN CONTR OL CIRCUIT

B B

1 2

@

place at AGND and DGND plane

1 2

@

RA35 0_0402_5%

1 2

@

RA36 0_0402_5%

1 2

@

RA37 0_0402_5%

Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN

+5V_RUN_AUDIO

Reserve for support D3 cold

+5V_RUN

A A

AUD_PWR_EN<12>

+5V_ALW

+3.3V_RUN

5

UZ5

@

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14_2X3

VOUT1
VOUT1

VOUT2

GPAD

CT1

GND

CT2

+5V_RUN_AUDIO_UZ5

14
13

12
11
10
9

+3.3V_RUN_AUDIO_UZ5

8
15

PJP19

1 2

PAD-OPEN1x1m

+5V_RUN

12

PJP15

@

+3.3V_RUN +3.3V_RUN_AUDIO

PAD-OPEN1x1m

1 2

CZ125 0.1U_0201_10V6K@

1 2

220P_0402_50V7K

CZ126

@

1 2

1000P_0402_50V7K

CZ127

@

PJP16

@

1 2

PAD-OPEN1x1m

CZ128 0.1U_0201_10V6K@

+3.3V_RUN_AUDIO

1 2

AUD_NB_MUTE#<34>

HDA_RST#_R<12>

HDA_Link is 3.3V,no need level shift circuit

PJP17

1 2

+5V_RUN_AUDIO

PAD-OPEN1x2m

PJP18

1 2

PAD-OPEN1x1m

500mA

4

2.5A

RA48 0_0402_5%

DA8

@

RB751S40T1G_SOD523-2

1 2

RA50 0_0402_5%@

21

RE313 @one control line if DVDD is 3.3V
DE2@two control lines 1

PD#

2016/01/01

2016/01/01

2016/01/01

RING2_R
AUD_HP_OUT_L1

AUD_HP_OUT_R1
SLEEVE_R

680P_0402_50V7K

ESD@

2

1

CA1

1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

@EMI@

330P_0402_50V8J

CA2

@EMI@

680P_0402_50V7K

330P_0402_50V8J

1

1

CA3

2

2

Deciphered Date

Deciphered Date

Deciphered Date

RING2
AUD_HP_OUT_L

AUD_HP_OUT_R
SLEEVE

3

1 2

LA10 BL M15PX330SN1D_2PESD@

1 2

LA15 BL M15PX330SN1D_2PEMI@

Only BR15U UMA use LA2,LA3,bec ause 6L

LA16

EMI@

1 2

BLM15PX330SN1D_2P

1 2

LA11 BL M15PX330SN1D_2PESD@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OFT HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OFT HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OFT HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS
MAYB EUSED B YOR DISCLOSED T OANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPALELECT RONICS, INC.

MAYB EUSED B YOR DISCLOSED T OANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPALELECT RONICS, INC.

MAYB EUSED B YOR DISCLOSED T OANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPALELECT RONICS, INC.

ESD@

CA4

ESD@

2

3

DA1

AZ5123-02S.R7G_SOT23-3

1

Add this Filter to avoid other
c

omponents/chips be influenced

680P_0402_50V7K

@ESD@

1

CA13

2

AUD_HP_NB_SENSE

ESD@

2

3

2

DA2

L03ESDL5V0CC3-2_SOT23-3

1

1

<Deciphered_Date>

<Deciphered_Date>

<Deciphered_Date>

HP-Out-Right

HP-Out-L ef t

Universal Jack

ESD@

3

DA3

AZ5123-02S.R7G_SOT23-3

680P_0402_50V7K

@ESD@

Link 2SJ3095-136111F DONE

1

CA12

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Codec ALC3246

Codec ALC3246

Codec ALC3246

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number R

C

C

C

LA-E082P

LA-E082P

LA-E082P

Monday, December 12, 2016

Monday, December 12, 2016

Monday, December 12, 2016

Date : Sheet of

Date : Sheet of

Date : Sheet of

Nokia-MIC

Global Headset

JHP1

7

GND

4

#4 G/M

1

#1 L

5

#5

6

#6 AGND

2

#2 R

3

#3 M/G

SINGA_2SJ3095-136111F

CONN@

1

iPhone-MIC

Norma l
Open

33 75

33 75

33 75

ev

1.0

1.0

1.0

5

+RTC_CELL

+3.3V_ALW_UE1

+3.3V_ALW

+3.3V_ALW_UE1

D D

0.1U_0201_10V6K
CE19

1

2

cl

ose to pin G8/M9

RF Request

+3.3V_ALW

0.1U_0201_10V6K

+3.3V_ALW_UE1

CE20

1

2

+3.3V_ALW_UE1

12

1 2

10U_0603_6.3V6M

CE16

0.1U_0201_10V6K

1

CE15

PJP22

PAD-OPEN1x1m

12

RE314100_04 02_1%

+VSS_PLL

2

68P_0402_50V8J

RF@

12P_0402_50V8J

RF@

1

1

CE60

CE59

2

2

PJP20

+1.8V_PRIM

C C

+3.3V_ALW

RPE10

8
7

100K_0804_8P4R_5%

1 2

RE95 100K_0402_5%@

B B

A A

1 2

1

PAD-OPEN1x1m

CE22

0.1U_0201_10V6K

2

PJP21

@

1 2

PAD-OPEN1x1m

CV2_ON_R

1

IMVP_VR_ON_EC

2

PCH_ALW_ON

3456

RUN_ON_EC

TBT_RESET_N_EC_R

1

JTAG1 @

@SHORT PADS~D

1

2

2

MEC_XTAL1 MEC_XTAL2

10P_0402_50V8J

32.768KHZ_9PF_X1A000141000200

12

CE28

Close to pin H1

+1.8V_3.3V_ALW_VTR3

+3.3V_ALW

@

RE505 100K_0 402_5%
RE526 10K_0402 _5%@

+3.3V_ALW

100K_0402_5%

RE63

1 2

JTAG_RST#

1U_0402_6.3V6K

100_0402_1%

12

12

RE65@

CE30

MEC_XTAL2_R

32 KHz Clock

YE1

1 2

5

VCCST_PWRGD<11,14,35>

CE21

1

0.1U_0201_10V6K

Close to pin N5

2

12
12
12

+3.3V_ALW2

LOM_CABLE_DETECT#

BCM5882_ALERT#

RE57 1K_0402_5%

12

@

RE290
0_0402_5%

8/28 schematic review

10P_0402_50V8J

12

CE29

12

RE320_0402_5%

1U_0402_6.3V6K

0.1U_0201_10V6K
CE13

1

12

2

0.1U_0201_10V6K

22U_0603_6.3V6M

@

1

1

CE17

2

2

SIO_SLP_SUS#<11,17,47,60,61,62>

1 2

@

RE308 0_0402_5%

USH_DET#

12

@

0.1U_0201_10V6K

CE14

CE23

1

2

CE18

1 2

RE349 43K_0402_1%

WLAN_WIGIG60GHZ_DIS#<32>

CLK_TP_SIO_I2C_DAT< 45>
DAT_TP_SIO_I2C_CLK< 45>

12

100K_0402_5%

RE58

For MEC5105 Rev.A :Pop RE361,Depop RE360,RE362

r MEC5105 Rev.B/C:Depop RE361,Pop RE 360,RE362

Fo
For WDT iss ue fix options&assessm ent:Pop RE361, Depop RE362

SHD_IO2

PRIM_PWRGD_GPIO024

GPIO055 use fo r SHD_CS# (LPC) or PCH_RSMRST#(eSPI)
GPIO024 use for SHD_IO2 (LPC) or PRIM_PWRGD(eSPI)

PCH_RSMRST#_GPIO204

SHD_CS#

CLKRUN#<8>

SIO_EXT_SMI#<12>
SIO_RCIN#<8>

SIO_EXT_SCI#<9>

+3.3V_ALW_UE1

+1.8V_3.3V_ALW_VTR3

PCH_DPWROK_EC<35>

RUN_ON_EC<35>

SIO_EXT_WAKE#<9>

BT_RADIO_DIS#<32>

PBAT_PRES#<57,66>

PCH_ALW_ON<47>
AC_PRESENT<11>

SML1_SMBDATA<8>

SML1_SMBCLK<8>

WWAN_W AKE#<32>

SUSACK#<11>

SIO_PWRBTN#<11,14>

LID_CL_NB#<35>

JTAG_TDI<35>

JTAG_TDO<35>

JTAG_CLK<35>

JTAG_TMS<35>

FAN1_TACH<35>

LCD_TST<29>

WWAN_RADIO_DIS#<32>

FAN1_PWM<35>

BIA_PWM_EC<29>

ACAV_IN_NB<57,66,67>

PANEL_BKEN_EC<29>

SIO_SLP_WLAN#<11,47>

AC_DIS< 66>

BCM5882_ALERT#<37>

MSCLK<35>

MSDATA<35>

AUD_NB_MUTE#<33>

EN_INVPWR<29>

IMVP_VR_ON_EC<35>

SIO_SLP_S3#<11,35>
SIO_SLP_S5#<11>

AC_DISC#<57,67>

USH_DET#<37>

BC_DAT_ECE1117<45>
BC_CLK_ECE1117<45>

SLOT2_CONFIG_3<32>

ESPI_RESET#<8>

ESPI_ALERT#<8>

PCH_PLTRST#_5105<35>

ESPI_CLK_5105<8,35>

ESPI_CS#<8,3 5>

ESPI_IO0<8,35>
ESPI_IO1<8,35>
ESPI_IO2<8,35>
ESPI_IO3<8,35>

SYS_PWROK<11,14>

ENVDD_PCH<6,29>

4

GPIO223

GPIO224

+RTC_CELL_VBAT

0.1U_0201_10V6K
CE11

1

2

+3.3V_EC_PLL

RUN_ON_EC
BT_RADIO_DIS#

PCH_ALW_ON

WWAN_W AKE#

WLAN_W IGIG60GHZ_DIS#

VCCST_PWRGD_EC

JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#

LCD_TST
WWAN_RA DIO_DIS#

PS_ID<57>

SHD_CS#
SHD_CLK

TBT_RESET_N_EC_R PORT80_DET#

VGA_ID
AC_DIS

MSCLK
MSDATA

EN_INVPWR

PRIM_PWRGD_GPIO024

IMVP_VR_ON_EC

GPIO126

RTCRST_ON_GPIO122

SIO_EXT_SMI#_EC
SIO_RCIN#_EC

CLKRUN#_EC
SIO_EXT_SCI#_EC
SYS_PWROK

MEC_XTAL1
MEC_XTAL2_R

@

1 2

RE360 0_0402_5%

@

1 2

RE361 49.9K_0402_1%

1 2

RE362 100K_0402_5%

1 2

RE363 0_0402_5%LPC@

1 2

@ESPI@

RE364 0_0402_5%

1 2

RE337 0_0402_5%LPC@

1 2

RE338 0_0402_5%LPC@

1 2

RE339 0_0402_5%LPC@

1 2

RE341 0_0402_5%LPC@

4

eSPI
LPC

SHD_I O0

GPIO204

eSPI

RSMRST#

LPC

UE1

A2

VBAT

B7

VTR_ANALOG

K2

VREF_ADC

F1

VTR_PLL

H1

VTR_REG

G8

VTR1

M9

VTR2

N5

VTR3

F8

GPIO020

E8

GPIO045

M12

GPIO120

C2

GPIO166

F9

GPIO175

N4

GPIO230

M8

GPIO231

K8

GPIO233

E11

GPIO007/SMB03_DATA/PS2_CLK0B

D8

GPIO010/SMB03_CLK/PS2_DAT0B

M13

GPIO110/PS2_CLK2

K12

GPIO111/PS2_DAT2

L13

GPIO112/PS2_CLK1A

K11

GPIO113/PS2_DAT1A

K10

GPIO114/PS2_CLK0A/nEC_SCI

N11

GPIO115/PS2_DAT0A

E10

GPIO154/SMB02_DATA/PS2_CLK1B

C12

GPIO155/SMB02_CLK/PS2_DAT1B

E9

GPIO145/SMB09_DATA/JTAG_TDI

F6

GPIO146/SMB09_CLK/JTAG_TDO

C8

GPIO147/SMB08_DATA/JTAG_CLK

C5

GPIO150/SMB08_CLK/JTAG_TMS

G13

JTAG_RST#

E3

GPIO050/FAN_TACH0/GTACH0

D1

GPIO051/FAN_TACH1/GTACH1

M2

GPIO052/FAN_TACH2/LRESET#

L10

GPIO053/PWM0/GPWM0

L11

GPIO054/PWM1/GPWM1

M5

GPIO055/PWM2/SHD_CS#/(RSMRST#)

J8

GPIO056/PWM3/SHD_CLK

N1

GPIO001/PWM4

L8

GPIO002/PWM5

N6

GPIO014/PWM6/GPTP-IN6

J9

GPIO015/PWM7

H11

GPIO035/PWM8/CTOUT1

D9

GPIO133/PWM9

H12

GPIO134/PWM10/UART1_RTS#

G10

GPIO135/UART1_CTS#

H10

GPIO170/TFDP_CLK/UART1_TX

G9

GPIO171/TFDP_DATA/UART1_RX

A4

GPIO022/GPTP-IN0

B2

GPIO023/GPTP-IN1

C1

GPIO024/nRESETI

N7

GPIO031/GPTP-OUT1

K9

GPIO032/GPTP-OUT0

N8

GPI0040/GPTP-OUT2

F13

GPIO121/PVT_IO0

E13

GPIO124/GPTP-OUT6/PVT_CS#

C13

GPIO125/GPTP-OUT5/PVT_CLK

E12

GPIO126/PVT_IO3

F11

GPIO122/BCM0_DAT/PVT_IO1

F12

GPIO123/BCM0_CLK/PVT_IO2

D12

GPIO046/BCM1_DAT

D13

GPIO047/BCM1_CLK

F4

GPIO041/SYS_SHDN#

B1

SYSPWR_PRES

K7

GPIO011/nSMI

N3

GPIO021/LPCPD#

K6

GPIO061/LPCPD#/ESPI_RESET#

H7

GPIO063/SER_IRQ/ESPI_ALERT#

K1

GPIO064/LRESET#

G7

GPIO065/PCI_CLK/ESPI_CLK

H6

GPIO066/LFRAME#/ESPI_CS#

K5

GPIO070/LAD0/ESPI_IO0

L4

GPIO071/LAD1/ESPI_IO1

G6

GPIO072/LAD2/ESPI_IO2

L5

GPIO073/LAD3/ESPI_IO3

L2

GPIO067/CLKRUN#

M1

GPIO100/nEC_SCI

G4

GPIO106/PWROK

L12

GPIO107/nSMI

A1

XTAL1

A3

XTAL2

1.8V_PRIM_PWRGD <62>

+3.3V_ALW

PCH_RSMRST# <45>

CLKRUN#_EC
SIO_EXT_SMI#_EC

SIO_RCIN#_EC
SIO_EXT_SCI#_EC

NA NANA

NA

SHD_I O1

GPIO011

NA NA

SIO_EXT_SMI#

VSS1

VSS2

A6

A13

GPIO227

*PRIM_ PWRGD NA

SHD_I O2

* For Version B IC

E6

RUN_ON<17,35,47,61>

3

GPIO056

GPIO016
SHD_I O3

GPIO100
SIO_EXT_SC I#

GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD#

GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR#

GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR#

GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI#

VSS_ADCH4VR_CAPJ1VSS_PLL

VSS3

+VR_CAP

12

CE31 1U_0402_6.3V6K

GPIO055
PCH_RS MRST#

SHD_CL K

SHD_CS #

GPIO021

GPIO067
SIO_R CIN#
LPCPD #

CLKRU N#

GPIO033/RC_ID0

GPIO034/RC_ID1/SPI0_CLK

GPIO036/RC_ID2/SPI0_MISO
GPIO003/SMB00_DATA/SPI0_CS#
GPIO004/SMB00_CLK/SPI0_MOSI

GPIO057/VCC_PWRGD

GPIO060/KBRST/48MHZ_OUT

GPIO104/UART0_TX
GPIO105/UART0_RX

GPIO127/A20M/UART0_CTS#

GPIO225/UART0_RTS#

GPIO025/TIN0/nEM_INT/UART_CLK

GPIO005/SMB01_DATA/GPTP-OUT4

GPIO006/SMB01_CLK/GPTP-OUT7

GPIO016/GPTP-IN7/SHD_IO3/ICT3

C4

GPIO026/TIN1
GPIO027/TIN2
GPIO030/TIN3

GPIO017/GPTP-IN5

GPIO151/ICT4

GPIO152/GPTP-OUT3

GPIO156/LED0
GPIO157/LED1
GPIO153/LED2
GPIO226/LED3

GPIO012/SMB07_DATA/TOUT3

GPIO013/SMB07_CLK/TOUT2

GPIO130/SMB10_DATA/TOUT1

GPIO131/SMB10_CLK/TOUT0

GPIO132/SMB06_DATA

GPIO140/SMB06_CLK/ICT5

GPIO200/ADC00
GPIO201/ADC01
GPIO202/ADC02
GPIO203/ADC03
GPIO204/ADC04
GPIO205/ADC05
GPIO206/ADC06
GPIO207/ADC07
GPIO210/ADC08
GPIO211/ADC09
GPIO212/ADC10
GPIO213/ADC11
GPIO214/ADC12
GPIO215/ADC13
GPIO216/ADC14
GPIO217/ADC15

GPIO222/SER_IRQ

GPIO223/SHD_IO0

GPIO224/GPTP-IN4/SHD_IO1

GPIO227/SHD_IO2

GPIO164/VCI_OVRD_IN

GPIO163/VCI_IN0#
GPIO162/VCI_IN1#
GPIO161/VCI_IN2#
GPIO000/VCI_IN3#

GPIO165/32KHZ_IN/CTOUT0

GPIO221/GPTP-IN3/32KHZ_OUT

GPIO044/VREF_VTT

GPIO042/PECI_DAT/SB-TSI_DAT

GPIO043/SB-TSI_CLK

GPIO103/THERMTRIP2#

THERMTRIP1#

GPIO160/PWM11/PROCHOT#

VSS_ANALOG

MEC5105_WFBGA169_11X11

G1

+VSS_PLL

+3.3V_ALW

100K_0402_5%

RUNPWROK

RE68

1 2

RUN_ON#

DMN65D8LDW-7_SOT363-6

61

QE2A

2

3

NA

VCI_OUT

DN1_DP1A
DP1_DN1A
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A

+3.3V_RUN

5

BGPO0

VSET

RE67

2

TYPEC_ID

F2

PANEL_ID

J10

BOARD_ID

J13

UPD2_SMBDAT

E7

UPD2_SMBCLK

D7
G3

HW_GPS_DISABLE#

H5
G11
G12
B13

UPD1_ALERT#

F10

PCIE_WAKE#_R

N13
N12
M11
H9

L9
M10
N9

C11
D10
D11
E1

E5
B3

EXPANDER_GPU_SMDAT

M7

EXPANDER_GPU_SMCLK

M4

PBAT_CHARGER_SMBDAT

M3

PBAT_CHARGER_SMBCLK

N2
N10

SYS_LED_MASK#

A12

RTCRST_ON_GPIO141

B6
F7

UPD1_SMBDAT

B4

UPD1_SMBCLK

C3

I_BATT_R

J4

I_SYS_R

J5
J6
G2
H2
J2
J3
K3
D3
D2
E2
G5
F5
K4
L1
L3

H8
J7
L6
L7
M6

D6
C7
A5
D5
B5
D4
E4

C6
F3

J11
K13
J12
A8
A7
A10
A9
B9
B8
A11
B10
C10

VIN

C9
B11

VCP

H3
B12
H13

10K_0402_5%

1 2

DMN65D8LDW-7_SOT363-6

34

QE2B

@

PCH_RSMRST#_GPIO204
USB_PWR_SHR_VBUS_ EN
USB_PWR_SHR_LFT_EN#
USB_PWR_EN1#

USB_PWR_EN2#
UPD2_ALERT#
PORT80_DET#

CV2_ON_R
SHD_IO0
SHD_IO1
SHD_IO2
SHD_IO3

VCI_IN1#
VCI_IN2#
POA_WAKE#

32KHZ_OUT

+PECI_VREF
PECI_EC_R
M3042_PCIE#_SATA
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P

REM_DIODE4_N
REM_DIODE4_P
+VR_CAP
VSET_5105

THERMATRIP2#
THERMATRIP1#

H_PROCHOT#_R1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTE N CONSENT.

TYPEC_ID <35>
PANEL_ID <35>
BOARD_ID <3 5>

RUNPWROK <14>
HW_GPS_DISABLE# <32>
HOST_DEBUG_TX <32,35>
ME_FW_EC <12>
ME_SUS_PWR_ACK <11>
UPD1_ALERT# <26>

PCIE_WAKE#_R <35>
SIO_SLP_S4# <11,17,59,62>
SIO_SLP_A# <11>
SIO_SLP_LAN# <11,47>

BEEP <33>
SLOT2_CONFIG_1 <32>
SLOT2_CONFIG_0 <32>

BREATH_LED# <46>
BAT1_LED# <46>
BAT2_LED# <46>
LCD_VCC_TEST_EN <29>

USH_SMBDAT <37>
USH_SMBCLK <37>
EXPANDER_GPU_SMDAT <35,48>
EXPANDER_GPU_SMCLK <35,48>
PBAT_CHARGER_SMBDAT <57,66>
PBAT_CHARGER_SMBCLK <57,66>
SLOT2_CONFIG_2 <32>

SYS_LED_MASK# <30,46>

UPD1_SMBDAT <26>
UPD1_SMBCLK <26>

1 2

RE64 300_0402_5%

1 2

RE312 300_0402_5%

1 2

RE318 0_0402_5%

USB_PWR_SHR_VBUS_EN <42,43>
USB_PWR_SHR_LFT_EN# <43>
USB_PWR_EN1# <44>
AUX_EN_WOWL <47>
LOM_CABLE_DETECT# <3 0>
BC_INT#_ECE1117 <45>
USB_PWR_EN2# <44>

PORT80_DET# <32>

PCH_PCIE_WAKE# <11,35>

LAN_WAKE# <11,30>

SHD_IO0 <35>

1 2

RE539 100_0402_5%

1 2

RE366 24.9_0402_1%LPC@

1 2

RE368 24.9_0402_1%LPC@

1 2

RE370 24.9_0402_1%LPC@

1 2

RE372 24.9_0402_1%LPC@

Place near UE1

EC_FPM_EN <37>

ACAV_IN <35,66>
ALWON <58>
POWER_SW_IN# <35>

POA_WAKE# <37>

3.3V_WWA N_EN <47>

1 2

CE54 10P_0402_ 50V8J@

1 2

RE60 43_0402_5%

1 2

CE24 2200P_0402_50V7K

1 2

CE26 2200P_0402_50V7K

1 2

CE27 2200P_0402_50V7K

VSET_5105 <35>

I_ADP <66>

THERMATRIP2# <35>

THERMATRIP1# <48>

1 2

RE288 100_0402_5%

RTCRST_ON_GPIO141
RTCRST_ON_GPIO122

@

RE514 0_0402_5%

@

RE515 0_0402_5%

SHD_IO0_R1
SHD_IO1_R1
SHD_IO2_R1
SHD_IO3_R1

1 2
1 2

2

I_BATT < 66>
I_SYS <63,66>

TOUCHPAD_INTR# <12,45>

CV2_ON <37>

PECI_EC <12>

@

PAD~D

H_PROCHOT# <12,63,66>

RTCRST_ON

100K_0201_5%

LPC@

1 2

RE374 24.9_0402_1%

1 2

RE367 45.3_0402_1%LPC@

1 2

RE369 45.3_0402_1%LPC@

1 2

RE371 45.3_0402_1%LPC@

1 2

RE373 45.3_0402_1%LPC@

ce near UE9

Pla

+PECI_VREF

0.1U_0201_10V6K
CE25

12

T269

REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P

REM_DIODE4_N
REM_DIODE4_P

13

D

2

G

12

S

RE93

For EMI request

ESPI_CLK_5105

33_0402_5%

@EMI@

12

RE350

33P_0402_50V8J

@EMI@

12

CE57

SHD_IO0_R2
SHD_IO1_R2
SHD_IO2_R2
SHD_IO3_R2

RE59 close to UE2 at least 250mils

12

@

RE590_0402_5%

REM_DIODE1_N <35>
REM_DIODE1_P <35>
REM_DIODE2_N <35>
REM_DIODE2_P <35>

REM_DIODE4_N <35>
REM_DIODE4_P <35>

RE94

1 2

75_0402_5%

QE12
L2N7002WT1G_SC-70-3

1

For BR DSC

SHD_CLK_R1SHD_CLK

+1.0V_VCCST

PCH_RTCRST# <11>

UPD1_SMBDAT
UPD1_SMBCLK
UPD1_ALERT#
UPD2_ALERT#
PBAT_CHARGER_SMBDAT
PBAT_CHARGER_SMBCLK

EXPANDER_GPU_SMDAT
EXPANDER_GPU_SMCLK

UPD2_SMBCLK
UPD2_SMBDAT

SLOT2_CONFIG_1
SLOT2_CONFIG_2
SLOT2_CONFIG_0
SLOT2_CONFIG_3

USB_PWR_EN2#
USB_PWR_SHR_LFT_EN#
USB_PWR_EN1#
USB_PWR_SHR_VBUS_ EN

AC_DIS
HW_GPS_DISABLE#
WLAN_W IGIG60GHZ_DIS#
WWAN_W AKE#
SYS_LED_MASK#

THERMATRIP1#
PCIE_WAKE#_R

GPIO126
BC_DAT_ECE1117

WWAN_RA DIO_DIS#
BT_RADIO_DIS#

SHD_IO2_R1
SHD_IO3_R1
SHD_CS#

+3.3V_ALW

SHD_IO3_R2
SHD_CLK_R1
SHD_IO0_R2

EXPANDER_GPU_SMDAT
EXPANDER_GPU_SMCLK

I_BATT_R
I_SYS_R

PCH_RSMRST#
SYS_PWROK
I_SYS_R
LCD_TST
EN_INVPWR
PORT80_DET#

VGA_ID
VGA_ID

VCI_IN1#
VCI_IN2#
POA_WAKE#

8
7
6
5

Discrete
UMA

1 2

RE302 2.2K_0402_5%

1 2

RE303 2.2K_0402_5%

1 2

RE91 100K_0402_5%

1 2

RE92 100K_0402_5%

1 2

RE37 2.2K_0402_5%

1 2

RE43 2.2K_0402_5%

1 2

RE524 2.2K_0402_5%

1 2

RE525 2.2K_0402_5%

1
2
3
4 5

2.2K_0804_8P4R_5%

1
2
3
4 5

100K_0804_8P4R_5%

1
2
3
4 5

100K_0804_8P4R_5%

1 2

RE83 100K_0402_5%@

1 2

RE12 100K_0402_5%

1 2

RE8 100K_0402_5%

1 2

RE38 10K_0402_5%

1 2

RE21 10K_0402_5%

1 2

RE301 10K_0402_5%

1 2

RE35 10K_0402_5%

1 2

RE5 10K _0402_5%

1 2

RE365 100K_0 402_5%

1 2

RE10 100K_0402_5%

1 2

RE11 100K_0402_5%

1 2

RE512 100K_0402_5%

1 2

RE507 100K_0402_5%

1 2

RE508 100K_0402_5%

1 2

RE324 100K_0402_5%

1 2

RE376 1K_0402_5%LPC@
RE377 1K_0402_5%LPC@

1 2

RE98 4.7K_0402_5%LPC@

UE9

LPC@

CS#

VCC

DO(IO1)

HOLD#(IO3)

WP#(IO2)

CLK

GND

DI(IO0)

W25Q80DVSSIG_SO8

1 2

CE504 10P_0402_50V8J@

1 2

CE505 10P_0402_50V8J@

1 2

CE3 2200P_04 02_50V7K

1 2

CE4 2200P_04 02_50V7K

1 2

RE342 10K_0402_5%

1 2

RE56 10K_0402_5%

1 2

@

RE313

1 2

RE20 100K_0402_5%

1 2

RE55 100K_0402_5%

1 2

RE513 100K_0402_5%@

1 2

RE84 100K_0402_5%@

1 2

RE85 100K_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R e

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

EC MEC5105

EC MEC5105

EC MEC5105

LA-E082P

LA-E082P

LA-E082P

1

RPE12

RPE9

RPE11

1
2
3
4

VGA_ID0

8
7
6

8
7
6

8
7
6

SHD_CS#
SHD_IO1_R2
SHD_IO2_R2

10K_0402_5%

0
1

34 75Monday, December 12, 2016

34 75Monday, December 12, 2016

34 75Monday, December 12, 2016

+3.3V_ALW

+RTC_CELL

+3.3V_ALW

+3.3V_ALW

1.0

1.0

1.0

v

5

2. EC fetches code and the drives GPIO223 to LOW to turn of f QE13B. When QE13B i s off, un-pl ug/plug AC will not af fect DSW_ DP WROK .

+1.8V_3.3V_ALW _VTR3

+3.3V_ALW

UE6

1

5

NC

VCC

PCH_PLTRST#_EC<11>

D D

JXT_FP241AH-010G AAM

2

A

4

Y

3

GND

74AUP1G07GW_TSS OP5

+3.3V_RUN

JESPI

1

1

2

2

3

3

4

4

5

5

6

6

7

7
8

11

GND

9

12

GND

10

CONN@

1 2

8

RE375 0_0402 _5%LPC@

9
10

1 2

PCH_PLTRST#_EC

RE340
10K_0402_ 5%

PCH_PLTRST#_5105 <34>

ESPI_IO0 <8,34>
ESPI_IO1 <8,34>
ESPI_IO2 <8,34>
ESPI_IO3 <8,34>

ESPI_CS# <8,34>

ESPI_CLK_5105 <8,34>

PA

GE

8

18 RC212_0ohm RC211_0ohm

JXT_FP241AH-010GAAM LINK DONE

LPC 80Port Debug LPC ESPI

1

+3.3V_RU N

2

+3.3V_RU N

+3.3V_RU N

+3.3V_RU N

LPC_LAD0

3

4

5

C C

6

7

8

9

10

WDT opt i on

MEC5105 rev.B

MEC5105 rev.C

B B

Pop RE361, QE13, CE503, RE530, UE7, CE5,CE6, RE348
Depop RE362, RE536, RE537

Pop RE362, RE536,
Depop RE361, QE13, CE503 , RE530, UE7, C E5,CE6, RE348, RE537

@

ACAV_IN<34,35 ,66>

In DC mode, ACAV_IN is LOW. This circuit doesn't af f ect PCH_DP WR OK.
In AC mode, 1. ACAV_IN is h igh. GPIO223 is tri-state. QE13B i s ON. QE13A can prevent backdrive to PCH_DPWROK.

Control Byte

0 1 0 0 A

R/W = 0 = Write
R/W = 1 = Read

2 A1 A0 R/W

SMBus address 0x40

+3.3V_ALW

10K_0402_5%

12

RE6

A A

WRST#

1U_0402_6.3V6K

12

CE500

ESPI_IO0

LPC_LAD1

ESPI_IO1

LPC_LAD2

ESPI_IO2

LPC_LAD3

ESPI_IO3

LPC_FRAM E#

ESPI_CS#

PCH_PLTRS T#

NA

GND

GND

LPC_CLOC K

ESPI_CLK

PCH_DPWROK_EC<34>

GPIO223 is OD. When E C fetches

RE530 1M_0402 _5%

3. When WDT occurs, GPIO223 is tri-state (EC reset). ACAV_IN charges CE503. When AC is removed, ACAV_IN goes LOW immediately.

+3.3V_ALW

10K_0402_5%

12

@

RE13

10K_0402_5%

12

RE14

the code, set GPIO223 to Low.

12

1U_0402_6.3V6K

@

CE503

12

5

@

QE13B
DMN65D8LDW-7 _SOT363-6

QE13B st ill kepps on according t o RC discharging rate. P CH_DP WR OKis L O Wbecause ACAV_I Nis L O W.

+3.3V_ALW

10K_0402_5%

10K_0402_5%

12

12

@

@

RE15

RE17

10K_0402_5%

10K_0402_5%

12

12

RE16

RE18

@

0_0402_5%

SHD_IO0 <34>ACAV_IN<34 ,35,66>

34

6 1

0.1U_0402_25V6K

1

CE1

2

EXPANDER_GPU_SMCLK<34,48>

EXPANDER_GPU_SMDAT<34,48>

@

T267

PAD~D

CE6@

1 2

RE34

2

@

QE13A
DMN65D8LDW-7 _SOT363-6

1U_0402_6.3V6K

12

CE2

WRST#

EXPANDER_ALERT#

31

32

+3.3V_ALW

1

2

1 2

1 2

To prevent backdrive to PCH_DPWROK_EC
when AC is plugged before +3.3V_ALW ramps up.

UE2

18

VSTBY33

19

SCL

20

SDL

1

A2

2

A1

3

A0

4

WRST#

7

INT

5

NC

6

NC

8

NC

MCP23008T-E-ML_ QFN20_4X4

4

ESPI LPC

RC25_10K RC8_15ohm

RC13/RC27_8.2K

0603 0603

RE337,RE338
RE339,RE340,
RE341

0_ohm

RE2 / RE3

_ohm

0

UE7

@

5

1

PCH_DPWROK <11 >

4

CT

12

CT: 3300 pF ~ 10ms delay

VBUS2_ECOK <57,67>
DCIN2_EN <57>
SATA_LED_EN <46>
VBUS1_ECOK <67>

DCIN1_EN <67>
DGPU_PWROK <12,52,68>
GPU_PWR_LEVEL <48>

USH_PWR_STATE# <37>

CE5

@

3300P_040 2_50V7-K

RE348

@

10K_0402_ 5%

@

RE537
10K_0402_ 5%

VDD

RESET

3

MR

RT9826-30GB

1 2

RE536

0_0402_5%

Reset Threshold Level 3.0V

16

GP7

15

GP6

14

GP5

13

GP4

12

GP3

11

GP2

10

GP1

9

GP0

17

VSS

21

EPAD

3

12

678

RE71

123

JDEG1

+EC_DEBUG_VCC

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

11

9

GND

9

12

10

GND

10

JXT_FP241AH-010G AAM

CONN@

JXT_FP241AH-010GAAM LINK DONE

49.9_0402_1%

DEBUG_TX

@

RE30 0_ 0402_5%

+1.0V_VCCST

4 5

1 2

10K_8P4R_5%

RPE7

JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO

MSCLK
MSDATA

HOST_DEBUG_TX

+1.0VS_VCCIO

SBIOS_TX<9>

POWER_SW_IN#<34>

LID_CL_NB#

JTAG_TDI <34>
JTAG_TMS <34>
JTAG_CLK <34>
JTAG_TDO <34>

HOST_DEBUG_TX <32,3 4>
MSDATA <34>
MSCLK <34>

QE11

@

2

G

1 3

D

L2N7002WT1G _SC-70-3

1 2

@

RE90 0_ 0402_5%

+RTC_CELL

100K_0402_5%

12

RE31

RE33 1K_0402_ 5%

2.2U_0402_6.3V6M

12

CE12

+3.3V_ALW

100K_0402_5%

RE25

12

.047U_0402_16V7K

12

CE8

+3.3V_ALW

10K_0402_5%

12

RE72

1 2

RE306

@

0_0402_5%

SIO_SLP_S3# <11,34,35>

1 2

RE70 2.2 K_0402_5%

S

1 2

RE26

10_0402_5 %

10K_0402_5%

12

RE73

+3.3V_ALW

CE10@

1 2

1U_0402_6.3 V6K

POWER_SW#_MB <11,46>

12

LID_CL# <46>LID_CL_NB#<34>

RF Request

+3.3V_ALW

TYPEC_ID<34>

CE62RE343

4700p240K

*

4700p130K
62K
33K

4700p

8.2K

4700p

4700p

4700p

4700p

1K

PD_ACE_DET# rise t i me i s measured fr o m 5 %~68 %.

10K_0402_5%

100K_0402_5%

12

12

RE74

RE75@

RE86

10K_0402_ 5%

1 2

RE69

1 2

8.2K_0402 _5%

H_THERMTRIP#<12,20,21>

0.1U_0402_25V6

LMBT3904WT1G SC70-3

CE36

12

C

QE4

2

B

E

3 1

2

IMVP_VR_ON_EC<34>
SIO_SLP_S3#<11,34,35>

1

CE61

2

RF@

THERMATRIP2# <34>

RUN_ON_EC<34>

68P_0402_50V8J

+3.3V_ALW

12

RE343
240K_0402 _5%

12

CE62
4700P_040 2_25V7K

REV
Single Port ACE w/o AR
Single Port ACE w/AR
Dual Port ACE w/o AR
Dual Port ACE w/AR
Dual Port ACE (w/AR +w/o AR)

@

12

@

RE3040_0402 _5%

@

CE53

1 2

0.1U_0402_2 5V6K

4

@

RE2800_0402_5 %

12

@

RE2920_0402 _5%

@

CE52

1 2

0.1U_0402_2 5V6K

4

O

+3.3V_ALW

12

12

CE40
4700P_040 2_25V7K

REV

X00
X01
X02
X

03
X04
A00

RE79

4.3K_0402 _5%

1 2

IMVP_VR_ON

+3.3V_ALW

5

1

P

B

2

A

G

UE3

3

1 2

+3.3V_ALW

1

B

2

A

UE5

RE79

CE40

240K 4700p
130K

4700p
4700p

62K4700p
33K 4700p

8.2K

4700p
4700p4.3K

12

RE2750 _0402_5%

O

5

P

G

3

PCIE_WAKE#_R<34>

Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)

IMVP_VR_ON_EC

SIO_SLP_S3#

TC7SH08FU_SSOP5~D

RUN_ON_EC

TC7SH08FU_SSOP5~D

BOARD_ID<34> PANEL_ID<34>

*

4700p1K

BOARD_ID rise t i me i s measured fr o m 5%~68%.

+3.3V_RUN

VSET_5105

0.1U_0402_25V6

12

CE38

Rest=1.69K , Tp=97 degree

1 2

RE48 10K_0402_5 %

1 2

RE51 10K_0402_5 %

Thermal diode mapping

5085 Channel

DP1/DN1

DP2/DN2

DN2a/DP2a

DP3/DN3

DP4/DN4

DP4/DN4 for Sk in on
QE6, place QE6 close to
Vcore VR choke.

100P_0402_50V8J

C

@

2

CE39

B

E

QE6

3 1

1 2

LMBT3904WT1G SC70-3

1.69K_0402_1%

12

RE77

FAN1_PWM
FAN1_TACH

Locat i on

CPU (QE3)

WiGig (QE5)

DDR (QE7)

NA

CPU VR (QE6)

REM_DIODE4_P <34>

REM_DIODE4_N <34>

VSET_5105 <34>

Link 50271-0040N-001 DONE

ACES_50271-0 040N-001

100P_0402_50V8J

CE46@

1

For BR DSC

PCIE_WAKE# <32,40>

PCH_PCIE_WAKE# <11,34 >

RE2740_0402_5 % @

+3.3V_ALW

UE4

1

5

NC

VCC

2

A

4

VCCST_PWRGD <11,14,34>

Y

3

GND

74AUP1G07GW_TSS OP5

IMVP_VR_ON <63>

RUN_ON <17,34,47,6 1>

+3.3V_ALW

12

RE300
130K_0402 _5%

PANEL_IDBOARD_ID

12

CE47
4700P_040 2_25V7K

RE300 CE47

*

33K

PANEL_ID rise t i me is measured fr o m 5%~68%.

JFAN1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

CONN@

Place under CPU
Place CE35 close to the QE3 as possible

100P_0402_50V8J

C

2

CE35@

B

1 2

E

QE3

3 1

LMBT3904WT1G SC70-3

DP2/DN2 for WiGig on QE5, place QE5 c lose
to WiGig and CE37 close to QE5

DN2a/DP2a for DDR on QE7, place QE7 close
to DDR and CE 46 close to QE7

100P_0402_50V8J

E

31

CE37@

B

12

2

QE7

C

LMBT3904WT1G SC70-3

4700p240K
4700p130K
4700p
4700p4.3K

FAN1_PWM
FAN1_TACH

12

12

10U_0603_6.3V6M

C

3 1

PANEL SIZE

12"
1
15"
17"

FAN1_PWM <34>
FAN1_TACH <34>

+5V_RUN

RB751S40T1G_SOD523-2

@

DE1

CE32

2 1

REM_DIODE1_P <34>

REM_DIODE1_N <34>

2

B

E

QE5

LMBT3904WT1G SC70-3

4"

REM_DIODE2_P <34>

REM_DIODE2_N <34>

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADES ECRETAND OTHER PROPRIETARY INFORMATIONOF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Shee t of

Date: Shee t of

Date: Shee t of

MEC5105 Support

MEC5105 Support

MEC5105 Support

Document Number Rev

Document Number Rev

Document Number Rev

LA-E082P

LA-E082P

LA-E082P

35 75Monday, December 12 , 2016

35 75Monday, December 12 , 2016

1

35 75Monday, December 12 , 2016

1.0

1.0

1.0

5

4

3

2

1

For NUVOTON TPM

@

1 2

VSB

VDD
VHIO
VHIO

GND

GND

GND

GND

PGND

+3.3V_ALW

1
8

14
22

2

NC

7

NC

10

NC

11

NC

25

NC

26

NC

31

NC

9
16
23
32
33
12

RZ89 0_0402_5%

0.1U_0201_10V6K

1

1

CZ51

2

2

+UZ12_TPM

+3.3V_RUN

D D

TPM_PIRQ#

TPM_PIRQ#<9>

PLTRST_TPM#<11>

@

T283

+3.3V_M_TPM

+3.3V_RUN

12

PAD~D

12

RZ362

@

10K_0402_5%

TPM_LPM#

PCH_SPI_D1_2_R
PCH_SPI_D0_2_R

PCH_SPI_CLK_2_R
PCH_SPI_CS#2_R

TPM_GPIO4

10K_0402_5%

RZ62

UZ12

29

GPIO0/SDA/XOR_OUT

30

GPIO1/SCL

3

GPIO2/GPX

6

GPIO3/BADD

24

LAD0/MISO

21

LAD1/MOSI

18

LAD2/SPI_IRQ#

15

LAD3

19

LCKL/SCLK

20

LFRAME#/SCS#

17

LRESET#/SPI_RST#/SRESET#

27

SERIRQ

13

CLKRUN#/GPIO4/SINT#

28

LPCPD#

4

PP

5

TEST

Reserved

+3.3V_ALW_PCH

+3.3V_M_TPM

SIO_SLP_S0#<11,17,61>

C C

PCH_SPI_D1_R1<8>

PCH_SPI_D0_R1<8>

PCH_SPI_CLK_R1<8>

PCH_SPI_CS#2<8>

PJP391

1 2

PAD-OPEN1x1m

1 2

RZ69 10K_0402_5%

1 2

RZ112 0_0402_5%@

1 2

@

RZ363 0_0402_5%

1 2

RZ58 33_0402_5%

1 2

RZ59 33_0402_5%

1 2

RZ60 33_0402_5%EMI@

@

1 2

RZ61 0_0402_5%

+UZ12_TPM

4.7U_0402_6.3V6M

1

CZ75

2

10U_0603_10V6M

place CZ51,CZ52 as close as UZ12.1

CZ52

0.1U_0201_10V6K

1

2

CZ

53,CZ55 as close as UZ 12.14

CZ54 as close as UZ12.22

place CZ50, CZ75 as close as U Z12.8

0.1U_0201_10V6K

1

CZ50

2

+3.3V_M_TPM

0.1U_0201_10V6K

10U_0603_10V6M

1

1

CZ54

CZ53

CZ55

2

2

RF Request RF Request

+3.3V_ALW +3.3V_M_TPM

12P_0402_50V8J

12P_0402_50V8J

RF@

68P_0402_50V8J

RF@

1

1

CZ57

CZ58

2

2

RF@

1

CZ59

2

68P_0402_50V8J

RF@

1

CZ60

2

JB2YX change to VB2YX 09/08

PCH_SPI_CLK_2_R

33_0402_5%

@EMI@

B B

A A

RZ63

0.1U_0402_25V6

1 2

@EMI@

12

CZ56

PCH_SPI_CS#2_R

1 2

RZ113 100_0402_5%@

RZ113

1K

100

RZ111

10K

+3.3V_M_TPM

S

3

G

2

D

1

POP

BT39061K

MM
LP2301A

LP2301ALT1G_SOT23-3

QZ9@

TPM_LPM#

12

10K_0402_5%

RZ111

@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USH & TPM

USH & TPM

USH & TPM

LA-E082P

LA-E082P

LA-E082P

36 75Monday, December 12, 2016

36 75Monday, December 12, 2016

36 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For ATMEL TPM

D D

+3.3V_ALW

1 2

RZ8 2.2K_0402_5%

1 2

RZ9 2.2K_0402_5%

1 2

RZ10 100K_0402_5%

USH_SMBCLK
USH_SMBDAT

USH_PWR_STATE#

USH CONN

C C

+PWR_SRC

PCH_PLTRST#_AND<11,31,32,40>

B B

RZ114 0_0402_5%@

USH_DET#<34>

PCH_PLTRST#_AND

.047U_0402_16V7K

12

CZ61ESD@

For ESD solution

@

1 2

RZ85 0_0402_5%

BCM5882_ALERT#<34>

1 2

USH_PWR_STATE#<35>

CONTACTLESS_DET#<12>

@

1 2

RZ87 0_0402_5%

DZ7

@

RB751S40T1G_SOD523-2

+PWR_SRC_R

CV2_ON<34>

POA_WAKE#<34>

EC_FPM_EN<34>

USB20_N10<10>
USB20_P10<10>

USH_SMBCLK<34>
USH_SMBDAT<34>

USH_DET#_R

12

Close to JUSH1

0.1U_0201_10V6K

1

@

CZ64

2

JUSH1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14
15
16

17

17
18
19
20

21

21

22

22

23

23

24

24

25

25

26

26

27

GND1

28

GND2

CVILU_CF5026FD0RK-05-NH

CONN@

Link CVILU_CF5026FD0RK-05-NH

+3.3V_ALW+3.3V_RUN+5V_RUN+5V_ALW

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

@

CZ66

2

2

0.1U_0201_10V6K

1

@

CZ67

2

@

CZ68

68P_0402_50V8J

1

2

RF Request

RF@

CZ73

RF Request

USH_SMBCLK

A A

USH_SMBDAT

1 2

CZ62 68P_0402_50V8J@RF@

1 2

CZ63 68P_0402_50V8J@RF@

68P_0402_50V8J

RF@

1

CZ69

2

68P_0402_50V8J

RF@

1

CZ71

2

+3.3V_ALW+3.3V_RUN+5V_RUN+5V_ALW

68P_0402_50V8J

RF@

1

CZ72

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USH & TPM

USH & TPM

USH & TPM

LA-E082P

LA-E082P

LA-E082P

37 75Monday, December 12, 2016

37 75Monday, December 12, 2016

37 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

10K_0402_5%

@

RN28

RD1_A_DE0
RD1_A_DE1
RD1_B_DE0
RD1_B_DE1

10K_0402_5%

@

RN41

@

12

RN57

12

RN61

10K_0402_5%

@

RN58

RD2_A_DE0
RD2_A_DE1
RD2_B_DE0
RD2_B_DE1

10K_0402_5%

@

RN62

5

+3.3V_RUN

12

12

10K_0402_5%

10K_0402_5%

10K_0402_5%

@

12

12

RN49

RN50

RN51

10K_0402_5%

10K_0402_5%

10K_0402_5%

@

@

@

12

12

RN53

RN52

RN54

+3.3V_RUN

+3.3V_RUN

10K_0402_5%

10K_0402_5%

10K_0402_5%

@

@

@

12

12

D D

10K_0402_5%

12

Programmable output de-emphasis level
set t i ng for cha nnel A .
A_DE0: internally pulled up at ~150K;
A_DE1 internally pulled down at ~150K

[A_DE1,A_DE0] ==

Programmable output de-emphasis level

C C

set t i ng f or channel B.
B_DE0: internally pulled up at ~150K;
B_DE1 internally pulled down at ~150K

[B_DE1,B_DE0] ==

Equalizer control and program for c hannel A.
A_EQ0, A_EQ1 and A_EQ2: internally pulled dow n at ~150K

[A_EQ2,A_EQ1,A_EQ0] ==

Equalizer control and program for channel B.
B_EQ0, B_EQ1 and B_EQ2: internally pulled down at ~150K

[B_EQ2,B_EQ1,B_EQ0] ==

B B

+3.3V_RUN

A A

12

12

RN27

RN25

RN26

10K_0402_5%

10K_0402_5%

@

12

12

12

RN40

RN39

RN38

LL: -2dB

HL: -7.5dB

LH: -3.5dB (default)

HH: -6dB

LL: -2dB

HL: -7.5dB

LH: -3.5dB (default)

HH: -6dB

LLL: For channel loss up to 17dB (default)
LHL: For channel loss up to 14dB
HLL: For channel loss up to 19dB
HHL: For channel loss up to 21dB
LLH: For channel loss up to 18dB
LHH: For channel loss up to 10dB
HLH: For channel loss up to 16dB

HHH: For channel loss up to 20dB

LLL: For channel loss up to 17dB (default)
LHL: For channel loss up to 14dB
HLL: For channel loss up to 19dB
HHL: For channel loss up to 21dB
LLH: For channel loss up to 18dB
LHH: For channel loss up to 10dB
HLH: For channel loss up to 16dB
HHH: For channel loss up to 20dB

10K_0402_5%

10K_0402_5%

10K_0402_5%

@

@

12

12

12

RN55

RN56

10K_0402_5%

10K_0402_5%

10K_0402_5%

@

12

12

12

RN59

RN60

RD1_B_EQ 0
RD1_B_EQ 1
RD1_B_EQ 2

IFDET_SATA_P CIE#

M2280_PCIE_SATA#

10K_0402_5%

12

12

RN69

10K_0402_5%

@

12

12

RN72

10K_0402_5%

10K_0402_5%

RN70

@

RN73

+3.3V_RUN

10K_0402_5%

@

12

RN71

10K_0402_5%

@

12

RN74

10K_0402_5%

10K_0402_5%

12

12

12

12

RN42

RN43

10K_0402_5%

10K_0402_5%

@

@

12

12

RN176

RN179

M2280_PCIE_SATA#

1 2

RN186 0_0402_5%

1 2

RN184 0_0402_5%@

RD2_B_EQ 0
RD2_B_EQ 1
RD2_B_EQ 2

10K_0402_5%

RN44

10K_0402_5%

@

RN174

RD1_A_EQ 0
RD1_A_EQ 1
RD1_A_EQ 2

+3.3V_RUN

2

100K_0402_5%

12

@

12

6

1

2

RN185

4

100K_0402_5%

RN171

QN4A

DMN65D8LDW-7_SOT363-6

+3.3V_RUN

10K_0402_5%

12

6

1

4

IFDET_SATA_P CIE#

IFDET_SATA_P CIE#

M2280_PCIE_SATA#

RN64

RD2_A_EQ 1_R

IFDET_SATA_P CIE#

QN5A

M2280_PCIE_SATA#

DMN65D8LDW-7_SOT363-6

1 2

RN192 0_0402_5%

1 2

RN182 0_0402_5%@

1 2

RN224 0_0402_5%

RN189 0_0402_5%

RN187 0_0402_5%@

RD2_A_EQ 1

1 2

1 2

12

100K_0402_5%

+3.3V_RUN

5

@

RN183

100K_0402_5%

12

+3.3V_RUN

5

@

RN188

10K_0402_5%

12

RN65

34

RD2_A_EQ 2_R

QN4B

DMN65D8LDW-7_SOT363-6

10K_0402_5%

12

RN63

RD2_A_EQ 0_R

34

QN5B

DMN65D8LDW-7_SOT363-6

3

1 2

RD2_A_EQ 0

1 2

RN225 0_0402_5%

3

2

+3.3V_RUN

0.1U_0201_10V6K

0.01UF_0402_25V7K

CN20

1

1

2

2

PCIE_PTX_C_RD_DRX_P11

1 2

PCIE_PTX_DRX_P11<10>
PCIE_PTX_DRX_N11<10>

PCIE_PRX_DTX_P11<10>
PCIE_PRX_DTX_N11<10>

if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD

RD2_A_EQ 2

PCIE_PTX_DRX_P12<10>
PCIE_PTX_DRX_N12<10>

PCIE_PRX_DTX_P12<10>
PCIE_PRX_DTX_N12<10>

if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

1 2
1 2

CN220 .22U_0402_ 10V6K

PCIE_PTX_C_RD_DRX_N11

CN230 .22U_0402_ 10V6K

PCIE_PRX_C_RD_DTX_P11

CN260 .22U_0402_ 10V6K

PCIE_PRX_C_RD_DTX_N11

CN270 .22U_0402_ 10V6K

1 2

CN320 .22U_0402_ 10V6K

1 2

CN330 .22U_0402_ 10V6K

1 2

CN360 .22U_0402_ 10V6K

1 2

CN370 .22U_0402_ 10V6K

+3.3V_RUN

0.1U_0201_10V6K
CN30

1

2

PCIE_PTX_C_RD_DRX_P12
PCIE_PTX_C_RD_DRX_N12

PCIE_PRX_C_RD_DTX_P12
PCIE_PRX_C_RD_DTX_N12

2

For Parade 2 Lane solution

CN21

PCIE/SATA Repeater

UN4

12

VDD_3.3

24

VDD_3.3

1

A_INP

A_OUTP

2

A_INN

A_OUTN

5

B_OUTP

B_INP

4

B_OUTN

RD1_A_EQ 0
RD1_A_EQ 1
RD1_A_EQ 2

RD1_B_EQ 0
RD1_B_EQ 1
RD1_B_EQ 2

0.01UF_0402_25V7K

1

2

CN31

RD2_A_EQ 0
RD2_A_EQ 1
RD2_A_EQ 2

RD2_B_EQ 0
RD2_B_EQ 1
RD2_B_EQ 2

B_INN

23

A_DE0

A_EQ0

22

A_DE1

A_EQ1

19

A_EQ2

11

B_EQ0

B_DE0

21

B_DE1

B_EQ1

16

B_EQ2

PWD

7

GND

REXT

25

EPAD

MODE

PS8558B TQFN24GTR2-A_TQFN2 4_4X4

0

1

PCIE/SATA Repeater

UN5

12

VDD_3.3

24

VDD_3.3

1

A_INP

A_OUTP

2

A_INN

A_OUTN

5

B_OUTP

4

B_OUTN

23

A_DE0

A_EQ0

22

A_DE1

A_EQ1

19

A_EQ2

11

B_EQ0

B_DE0

21

B_DE1

B_EQ1

16

B_EQ2

7

GND

25

EPAD

PS8558B TQFN24GTR2-A_TQFN2 4_4X4

1

PCIE/SATA Redriver for 2280

Breken ridge12

Brekenridge14U UMA

Brekenridge14U DSC

Brekenridge15U UMA

Brekenridge15U DSC

Steamb oat12

Steamb oat14

Kirkwo od12&13

PWD Funtion

0

1

18
17

14
15

RD1_A_DE0

6

RD1_A_DE1

8

RD1_B_DE0

13

RD1_B_DE1

9

3

RD1_REXT

10

M2280_PCIE_SATA#

20

PCIE_PTX_RD_DRX_P11 <39>

PCIE_PTX_RD_DRX_N11 <39 >

PCIE_PRX_RD_DTX_P11 <39>
PCIE_PRX_RD_DTX_N11 <39 >

1 2

RN30 4.9 9K_0402_1 %

M2280_PCIE_SATA# <10,39>

SATA

PCIE

B_INP
B_INN

PWD

REXT

MODE

18
17

14
15

RD2_A_DE0

6

RD2_A_DE1

8

RD2_B_DE0

13

RD2_B_DE1

9

3

RD2_REXT

10

M2280_PCIE_SATA#

20

PCIE_PTX_RD_DRX_P12 <39>

PCIE_PTX_RD_DRX_N12 <39 >

PCIE_PRX_RD_DTX_P12 <39>
PCIE_PRX_RD_DTX_N12 <39 >

1 2

RN31 4.99 K_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SATA/PCIE REPEATER for M.2 2280

SATA/PCIE REPEATER for M.2 2280

SATA/PCIE REPEATER for M.2 2280

Document Number Re v

Document Number Re v

Document Number Re v

1

Need

Need

Need

Need

Need

No need

Need

Check

Normal mode(default)

power down mode

LA-E082P

LA-E082P

LA-E082P

38 75Monday, December 12, 2016

38 75Monday, December 12, 2016

38 75Monday, December 12, 2016

1.0

1.0

1.0

5

4

3

2

1

For Breckenridge 14/15 DSC

D D

NEED LINK TI hd3ss3415 as main

+3.3V_RUN

0.1U_0201_10V6K

0.01UF_0402_25V7K

CN52

1

1

CN53

2

2

C C

Spindle HDD(MUXA)

PCIE_PRX_RD_DTX_P12<38>

PCIE_PRX_RD_DTX_N12<38>
PCIE_PTX_RD_DRX_P12<38>
PCIE_PTX_RD_DRX_N12<38>

PCIE_PRX_RD_DTX_P11<38>
PCIE_PRX_RD_DTX_N11<38>
PCIE_PTX_RD_DRX_P11<38>
PCIE_PTX_RD_DRX_N11<38>

Co-lay with 2nd part

HDD_DET#

UN8

9

VDD

19

VDD

26

VDD

34

VDD

41

VDD

1

A0+

2

A0-

5

A1+

6

A1-

10

A2+

11

A2-

14

A3+

15

A3-

21

NC

25

NC
NC

35

NC

39

NC

30

HD3SS3415RUAR_WQFN42_9X3P5

GND
GND
GND
GND
GND
GND
GND

center pad

37

B0+

36

B0-

33

B1+

32

B1-

28

B2+

27

B2-

24

B3+

23

B3-

3

C0+

4

C0-

7

C1+

8

C1-

12

C2+

13

C2-

16

C3+

17

C3-

18
20
22
29
38
40
42
43

PCIE_PRX_MUXA_DTX_P12 <41>
PCIE_PRX_MUXA_DTX_N12 <41>
PCIE_PTX_MUXA_DRX_P12 <41>

PCIE_PTX_MUXA_DRX_N12 <41>

PCIE_PRX_MUXB_DTX_P12 <40>
PCIE_PRX_MUXB_DTX_N12 <40>
PCIE_PTX_MUXB_DRX_P12 <40>

PCIE_PTX_MUXB_DRX_N12 <40>

PCIE_PRX_MUXB_DTX_P11 <40>
PCIE_PRX_MUXB_DTX_N11 <40>
PCIE_PTX_MUXB_DRX_P11 <40>

PCIE_PTX_MUXB_DRX_N11 <40>

M2 2280(MUXB)

HDD_DET#

+3.3V_RUN

12

RN12410K_0402_5%

B B

IFDET_SATA#_P CIE

SATAL

H

M2280_PCIE_SATA#<10,38>

A A

5

PCIE

DN1

1

BAT54AW-7-F_SOT323-3

4

HDD_DET#

2

3

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

HDD_SEL(HDD_D ET#)

H

HDD_DET# <12,41>

IFDET_SATA#_PCIE_D <40>

Spindle HDD(MUXA)L

M.2 2280(MUXB)

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SATA/PCIE DEMUX

SATA/PCIE DEMUX

SATA/PCIE DEMUX

LA-E082P

LA-E082P

LA-E082P

39 75Monday, December 12, 2016

39 75Monday, December 12, 2016

39 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For Breckenridge 14/15 DSC

RF

Request

PCIE_PRX_MUXB_DTX_N11<39>
PCIE_PRX_MUXB_DTX_P11<39>

PCIE_PTX_MUXB_DRX_N11<39>
PCIE_PTX_MUXB_DRX_P11<39>

PCIE_PRX_MUXB_DTX_P12<39>
PCIE_PRX_MUXB_DTX_N12<39>

PCIE_PTX_MUXB_DRX_N12<39>
PCIE_PTX_MUXB_DRX_P12<39>

+3.3V_HDD_M2

68P_0402_50V8J

@RF@

1

CN60

2

+3.3V_HDD_M2

RN37@ 10K_0402_5%

1 2

D D

C C

+3.3V_HDD_M2

0.1U_0201_10V6K

0.1U_0201_10V6K

@

CN61

1

2

CN62

1

2

Place near HDD CONN

M2280_DEVSLP

CN69 0.22U_0402_10V6K
CN70 0.22U_0402_10V6K

CN71 0.22U_0402_10V6K
CN72 0.22U_0402_10V6K

if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD

12
12

RN820_0402_5%

RN810_0402_5%

12
12

12
12

RN770_0402_5%

RN780_0402_5%

12
12

22U_0603_6.3V6M

12

CN63

@
@

@
@

22U_0603_6.3V6M

12

CN64

PCIE_PRX_MUXB_C_DTX_N11
PCIE_PRX_MUXB_C_DTX_P11

PCIE_PTX_MUXB_C_DRX_N11
PCIE_PTX_MUXB_C_DRX_P11

PCIE_PRX_MUXB_C_DTX_P12
PCIE_PRX_MUXB_C_DTX_N12

PCIE_PTX_MUXB_C_DRX_N12
PCIE_PTX_MUXB_C_DRX_P12

2280 SSD

NGFF slot

JNGFF3

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53
55 56
57 58

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

C Key M

+3.3V_HDD_M2

NVME_LED#

RN100 0_0402_5%@

PCIE_WAKE#

1 2

1 2

PAD-OPEN1x3m

M2280_DEVSLP <10,41>

PCH_PLTRST#_AND <11,31,32,37>

CLKREQ_PCIE#3 <11>

PCIE_WAKE# <32,35>

2.

PJP31

8A

+3.3V_RUN

SATALED# <10,32,46>

67

67

IFDET_SATA#_PCIE_D<39>

B B

69

69

71

71

73

73

75

75

77

GND1

LCN_DAN05-67356-0103

CONN@

GND2

68

68

70

70

72

72

74

74

76

SUSCLK_R

1 2

@

RN99 0_0402_5%

SUSCLK <11,32>

Link LCN_DAN05-67356-0103 DONE

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

M2 2280 Socket

M2 2280 Socket

M2 2280 Socket

LA-E082P

LA-E082P

LA-E082P

40 75Monday, December 12, 2016

40 75Monday, December 12, 2016

40 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

D D

C C

4

3

For Breckenridge 14/15 DSC

DDR_XDP_WAN_SMBDAT<8,14,20,21>
DDR_XDP_WAN_SMBCLK<8,14,20,21>

2

+3.3V_RUN

12

1

+5V_HDD

100K_0402_5%

12

+3.3V_RUN

100K_0402_5%

12

RN2

DMN65D8LDW-7_SOT363-6

6

FFS_INT2

2

1

0.1U_0201_10V6K

10U_0603_10V6M

12

CN2

CN1

0.1U_0201_10V6K

12

CN3

Free Fall Sensor

LGA1

LNG2DM

10

VDD_IO

9

VDD

3

SDO/SA0

4

SDA/SDI/SDO
SCL/SPC1GND

2

CS

LNG2DMTR_LGA12_2X2

RES

INT 1
INT 2

GND
GND

RN1@

FFS_INT2_Q

DMN65D8LDW-7_SOT363-6

34

QN1B

5

QN1A

5
12

11
6

7
8

INT1/IN2:Push-Pull,active high

FFS_INT2

HDD_FALL_INT <9>
FFS_INT2 <12>

+3.3V_HDD

M2280_DEVSLP

1 2

RN3@ 10K_0402_5%

B B

PCIE_PTX_MUXA_DRX_P12<39>
PCIE_PTX_MUXA_DRX_N12<39>

PCIE_PRX_MUXA_DTX_N12<39>
PCIE_PRX_MUXA_DTX_P12<39>

+3.3V_RUN

HDD& M2 2280 MUX

+5V_HDD +3.3V_HDD

1000P_0402_50V7K

+3.3V_RUN

12

RN4

@

10K_0402_5%

12

10K_0402_5%

HDD_EN

HDD_EN<9>

RN5<BOM Structure>

5

A A

+5V_HDD source

+5V_ALW

UZ23

1

VOUT

VIN

2

VOUT

VIN

3

ON

4

VBIAS

AOZ1336_DFN8_2X2

GND
GND

CT

7

+5V_HDD_UZ23

8
6

5
9

4

PJP32

1 2
1 2

1.5A

+5V_HDD

1 2

PAD-OPEN1x1m

CZ129 0.1U_0201_10V6K
CZ130 470P_0402_50V7K

PJP33

@

PAD-OPEN1x1m

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+5V_HDD+5V_RUN

12

Place near HDD CONN

3

0.1U_0201_10V6K

CN8

12

12

12

CN4 0.01UF_0402_25V7K

12

CN5 0.01UF_0402_25V7K

12

CN6 0.01UF_0402_25V7K

12

CN7 0.01UF_0402_25V7K

PJP34

1 2

PAD-OPEN1x2m

0.1U_0201_10V6K

0.1U_0201_10V6K

CN9

12

CN11

12

@

CN10

2

PCIE_PTX_MUXA_C_DRX_P12
PCIE_PTX_MUXA_C_DRX_N12

PCIE_PRX_MUXA_C_DTX_N12
PCIE_PRX_MUXA_C_DTX_P12

+3.3V_HDD

M2280_DEVSLP<10,40>

HDD_DET#<12,39>

+5V_HDD

DELL CONFIDENTIAL/PROPRIETARY

FFS_INT2_Q

Link 59003-02006-002 DONE

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CONN@

JSATA1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

G1

22

G2

23

G3

24

G4

ACES_59003-02006-002

HDD CONN

HDD CONN

HDD CONN

LA-E082P

LA-E082P

LA-E082P

1

1.0

1.0

41 75Monday, December 12, 2016

41 75Monday, December 12, 2016

41 75Monday, December 12, 2016

1.0

5

4

3

2

1

USB3_PTX_DRX_P1<10>
USB3_PTX_DRX_N1<10>

+3.3V_USB_UI5

+3.3V_USB_UI5

12

CI39 0.1U_0402_10V7K

12

CI40 0.1U_0402_10V7K

USB3_PRX_RD_DTX_P1<43>
USB3_PRX_RD_DTX_N1<43>

1 2

@

RI81 0_0402_5%

2K_0402_5%

0.01UF_0402_25V7K

0.1U_0402_16V4Z

1

1

CI38

CI37

2

2

USB3_PTX_C_RD_DRX_P1
USB3_PTX_C_RD_DRX_N1

USB3_PRX_RD_DTX_P1
USB3_PRX_RD_DTX_N1

4.99K_0402_1%

@

RI37

RI36

1 2

1 2

LInk CIS ok

UI5

1

VDD

13

USB1_A_EQ1
USB1_A_DE0
USB1_A_EQ0
USB1_A_DE1

USB3_PD#
USB1_TEST

0_0402_5%

@

RI35

1 2

VDD

15

A_EQ1/SDA_CTL

16

A_DE0/SCL_CTL

17

A_EQ0/NC

18

A_DE1/NC

19

A_INp

20

A_INn

9

B_INp

8

B_INn

5

PD#

7

REXT

14

TEST

24

I2C_EN

PS8713BTQFN24GTR2_TQFN24_4X4

CPN: SA00005OR30

: PS8713BTQFN24GTR2-A2

MPN
PCB footprint: PS8713BTQFN24GTR2_TQFN24_4X4

B_EQ1/I2C_ADDR1

B_DE0/I2C_ADDR0

B_EQ0/NC
B_DE1/NC

A_OUTp

A_OUTn

B_OUTp

B_OUTn

GND
GND

GPAD

USB1_B_EQ1

4

USB1_B_DE0

3

USB1_B_EQ0

2

USB1_B_DE1

6

USB3_PTX_RD_DRX_P1

12

USB3_PTX_RD_DRX_N1

11

USB3_PRX_C_RD_DTX_P1

22

USB3_PRX_C_RD_DTX_N1

23

10
21
25

USB3_PTX_RD_DRX_P1 <43>
USB3_PTX_RD_DRX_N1 <43>

12

CI41 0.1U_0402_10V7K

12

CI42 0.1U_0402_10V7K

Br

ekenridg e12

Brekenridge14U UMA

Brekenridge14U DSC

Brekenridge15U UMA

Brekenridge15U DSC

Steamboat12

Steamboat14

Kirkwood1 2&13

USB3_PRX_DTX_P1 <10>
USB3_PRX_DTX_N1 <10>

+3.3V_RUN

1 2

D D

+3.3V_ALW_PCH

1 2

RI34 4.7K_0402_5%@

C C

+3.3V_ALW_PCH

USB1_TEST

RI79 0_0603_5%@

1 2

@

RI800_0603_5%

USB_PWR_SHR_VBUS_EN<34,43>

USB3 Red river for charge

No need

Need

Need

Need

Need

Need

Need

Check

+3.3V_ALW_PCH+3.3V_ALW_PCH +3.3V_ALW_PCH+3.3V_ALW_PCH +3.3V_ALW_PCH+3.3V_ALW_PCH

RI42

RI40

RI38

@

B B

4.7K_0402_5%

1 2

12

RI39

@

4.7K_0402_5%

USB1_A_EQ0USB1_A_EQ1 USB1_B_EQ0USB1_B_EQ1 USB1_A_DE0USB1_A_DE1 USB1_B_DE1 USB1_B_DE0

@

4.7K_0402_5%

1 2

12

@

4.7K_0402_5%

RI41

@

4.7K_0402_5%

1 2

12

@

4.7K_0402_5%

RI43

4.7K_0402_5%

1 2

12

@

4.7K_0402_5%

@

RI45

RI44

@

4.7K_0402_5%

1 2

12

@

4.7K_0402_5%

RI51

RI52

@

4.7K_0402_5%

1 2

12

@

4.7K_0402_5%

RI53

RI54

+3.3V_ALW_PCH +3.3V_ALW_PCH

RI57

@

4.7K_0402_5%

1 2

12

@

4.7K_0402_5%

RI55

RI56

@

4.7K_0402_5%

1 2

12

@

4.7K_0402_5%

RI58

Parade_PS8713B

EQ10A_EQ0

0

0

A A

1

1

Both A_EQ&B_EQ have internal pull-down 150k

5

B_EQ0B_EQ1

0

01 10

10 01

1 loss up to 7.5dB

Recommended EQA_

loss up to 9.5dB

loss up to 13dB

loss up to 4.5dB

1

B_DE0B_DE1

0

0

0

01 10

10 01

1

1 5dB de-emphasis

1

Recommended DEA_DE10A_DE0

3.5dB de-emphasis

No de-emphasis

2.7dB de-emphasis

1

Both A_DE&B_DE have internal pull-down 150k

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USB3.0 Repeater

USB3.0 Repeater

USB3.0 Repeater
LA-E082P

LA-E082P

LA-E082P

42 75Monday, December 12, 2016

42 75Monday, December 12, 2016

42 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For w/ Repeater

+5V_USB_CHG_PWR

150U_B2_6.3VM_R35M

100U_1206_6.3V6M

DI4

ESD@

1

1

2

2

4

4

5

5

3

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

SW_USB20_P1
SW_USB20_N1

RI14

USB3_PRX_RD_DTX_N1
USB3_PRX_RD_DTX_P1
USB3_PTX_C_DRX_N1
USB3_PTX_C_DRX_P1

12

ILIM_SEL

USB3_PRX_RD_DTX_N1<42>
USB3_PRX_RD_DTX_P1<42>
USB3_PTX_RD_DRX_N1<42>
USB3_PTX_RD_DRX_P1<42>

+5V_ALW

UI3

1

VIN

2

DM_OUT

3

DP_OUT

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1
CTL2

8

CTL3

SLGC55544CVTR_TQFN16_3X3

Link Seligro SA000097E10 Done

CI13 0.1U_0402_25V6
CI16 0.1U_0402_25V6

Thermal Pad

MAIN:SLGC5 5544CVT R

VOUT

DP_IN

DM_IN

ILIM_L

ILIM_HI

GND

12
12

12

10
11

15
16

NC

14
17

+5V_USB_CHG_PWR

D D

C C

USB20_N1<10>
USB20_P1<10>

USB_OC0#<10>

USB_PWR_SHR_VBUS_EN<34,42>

+5V_ALW

ILIM_SEL

RI13

12

10K_0402_5%

9

10

8

9

7

7

6

6

SW_USB20_N1

SW_USB20_P1

USB3_PRX_RD_DTX_N1
USB3_PRX_RD_DTX_P1
USB3_PTX_C_DRX_N1
USB3_PTX_C_DRX_P1

LI7

1 2

EXC24CQ900U_4P

EMI@

@

1

CI32

+

2

34

1

CI14

2

USB20_N1_R

USB20_P1_R

0.1U_0201_10V6K
CI17

1

2

3

1

1

AZC199-02SPR7G_SOT23-3

ESD@

223

DI5

USB20_N1_R
USB20_P1_R

USB3_PRX_RD_DTX_N1
USB3_PRX_RD_DTX_P1

USB3_PTX_C_DRX_N1
USB3_PTX_C_DRX_P1

Link C-K_26230A-8K1A-02 DONE

R

+5V_USB_CHG_PWR

1
2
3
4
5
6
7
8
9

F Request

12P_0402_50V8J

RF@

1

1

CI43

2

2

JUSB1

VBUS
D­D+
GND
SSRX­SSRX+
GND
SSTX­SSTX+

C-K_26230A-8K1A-02

CONN@

68P_0402_50V8J

RF@

CI44

GND
GND
GND
GND

10
11
12
13

B B

A A

+5V_ALW

1

2

47U_0603_6.3V6M

47U_0603_6.3V6M

@

1

CI34

2

@

1

CI33

2

Place near UI3.1

10U_0402_6.3V6M

0.1U_0201_10V6K

@

CI19

1

CI31

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

JUSB1+PS

JUSB1+PS

JUSB1+PS
LA-E082P

LA-E082P

LA-E082P

43 75Monday, December 12, 2016

43 75Monday, December 12, 2016

43 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

USB3_PRX_DTX_N3<10>
USB3_PRX_DTX_P3<10>
USB3_PTX_DRX_N3<10>
USB3_PTX_DRX_P3<10>

D D

C C

4

CI5 0.1U_0402_25V6
CI4 0.1U_0402_25V6

12

3

DI1

USB3_PRX_DTX_N3 USB3_PRX_DTX_N3
USB3_PRX_DTX_P3 USB3_PRX_DTX_P3

12
12

USB3_PRX_DTX_N4 USB3_PRX_DTX_N4
USB3_PRX_DTX_P4 USB3_PRX_DTX_P4

USB3_PTX_C_DRX_N3 USB3_PTX_C_DRX_N3
USB3_PTX_C_DRX_P3 USB3_PTX_C_DRX_P3

USB20_P2<10>

USB20_N2<10>

USB20_P2

USB20_N2

DFB request:
mai

n SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P)
Pitch change from 0.5mm to 0.55mm

DI6

ESD@

1

1

2

2

4

5

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

ESD@

1

1

2

2

4

4

5

5

3

3

8

L05ESDL5V0NA-4_SLP2510P8-10-9

LI3

1 2

EXC24CQ900U_4P

9

10

8

9

7

9

10

8

9

7

7

6

6

EMI@

34

USB20_P2_R

USB20_N2_R

For Breckenridge 14&15/Steamboat 14

RF Request

+USB_EX2_PW R

12P_0402_50V8J

RF@

1

1

CI45

2

2

+5V_ALW

10U_0603_10V6M

12

RF

Request

+USB_EX3_PW R

12P_0402_50V8J

RF@

68P_0402_50V8J

CI47

2

2

2

+USB_EX2_PWR

0.1U_0201_10V6K

100U_1206_6.3V6M

68P_0402_50V8J

RF@

CI46

0.1U_0201_10V6K
CI7

@

1

CI6

2

RF@

CI48

12

+USB_EX3_PWR

12

CI3

1

CI1

2

USB_PWR_EN1#<34>

0.1U_0201_10V6K

100U_1206_6.3V6M

CI10

CI8

AZC199-02SPR7G_SOT23-3

ESD@

DI3

3

1

3

1

AZC199-02SPR7G_SOT23-3

223

1

223

1

USB3_PTX_C_DRX_P3
USB3_PTX_C_DRX_N3

USB20_P2_R
USB20_N2_R

USB3_PRX_DTX_P3
USB3_PRX_DTX_N3

ESD@

DI2

UI1

5
4

SY6288D20AAC_SOT23-5

USB20_N3_R

Link LOTES_AUSB0014-P003A_9P DONE

OUT

IN

GND

EN

OCB

" not support

12

1

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

LOTES_AUSB0014-P003A

CONN@

+USB_EX2_PWR

1
2
3

JUSB3

1

VBUS

2

D­D+

4

GND
StdA-SSRX­StdA-SSRX+
GND-DRAIN
StdA-SSTX­StdA-SSTX+

C-K_26210B-8K1A-02

10

GND

11

GND

12

GND

13

GND

USB_OC1# <10>

CONN@

10

GND

11

GND

12

GND

13

GND

Link C-K_26210B-8K1A-02 DONE

B B

LI4

USB20_P3<10>

USB20_N3<10>

A A

USB20_P3

USB20_N3

EMI@

1 2

EXC24CQ900U_4P

34

USB20_P3_R

USB20_N3_R

+5V_ALW

12

0.1U_0201_10V6K

10U_0603_10V6M

@

CI11

1

2

USB_PWR_EN2#<34>

CI12

5
4

+USB_EX3_PWR

UI2

1

OUT

IN

2

GND

EN

3

OCB

SY6288D20AAC_SOT23-5

USB_OC2# <10>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

JUSB2&JUSB3

JUSB2&JUSB3

JUSB2&JUSB3

LA-E082P

LA-E082P

LA-E082P

1

44 75Monday, December 12, 2016

44 75Monday, December 12, 2016

44 75Monday, December 12, 2016

1.0

1.0

1.0

5

Touch Pad

D D

DAT_TP_SIO_I2C_CLK<34>
CLK_TP_SIO_I2C_DAT<34>

C C

I2C1_SDA_TP<9>
I2C1_SCK_TP<9>

I2C From CPU

10P_0402_50V8J

10P_0402_50V8J

12

12

CZ80

CZ81

4

+3.3V_TP

4.7K_0402_5%

4.7K_0402_5%

12

12

RZ18

RZ19

PS2

12

RZ22 0_0402_5%@

12

RZ23 0_0402_5%@

12

@

RZ3460_0402_5%

12

@

RZ3470_0402_5%

DAT_TP_SIO_R
CLK_TP_SIO_R

I2C1_SDA_TP_R
I2C1_SCK_TP_R

I2C From EC

+3.3V_TP +3.3V_TP

10K_0402_5%

12

2.2K_0402_5%

2.2K_0402_5%

12

12

RZ20

RZ21

1 2

@

RZ26 0_0402_5%

1 2

@

RZ29 0_0402_5%

I2C1_SDA_TP_R
I2C1_SCK_TP_R

@

RZ116

3

+3.3V_RUN +3.3V_TP

PJP35

1 2

PAD-OPEN1x1m

Keyboard

KB_DET#<12>

+5V_RUN

+3.3V_ALW

BC_INT#_ECE1117<34>

BC_DAT_ECE1117<34>

BC_CLK_ECE1117<34>

10K_0402_5%

12

@

RZ117

+3.3V_TP

TOUCHPAD_INTR#<12,34>

2

KB_DET#

BC_INT#_ECE1117
BC_DAT_ECE1117

BC_CLK_ECE1117

DAT_TP_SIO_R
CLK_TP_SIO_R

I2C1_SDA_TP_R
I2C1_SCK_TP_R

+3.3V_TP

1

RF@

68P_0402_50V8J

2

CVILU_CF5020FD0RK-05-NH

22

GND

21

GND

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JKBTP1

CONN@

CZ83

1

RF Request

KB_DET#

BC_INT#_ECE1117

BC_DAT_ECE1117

BC_CLK_ECE1117

DAT_TP_SIO_R

CLK_TP_SIO_R

1 2

CZ84 68P_0402_50V8JRF@

1 2

CZ85 68P_0402_50V8J@RF@

1 2

CZ86 68P_0402_50V8J@RF@

1 2

CZ87 68P_0402_50V8J@RF@

1 2

CZ88 68P_0402_50V8J@RF@

1 2

CZ89 68P_0402_50V8J@RF@

+5V_RUN+3.3V_ALW+3.3V_TP

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

2

@

@

CZ91

CZ90

2

Place close to JKBTP1

0.1U_0201_10V6K

1

@

CZ92

2

Link HRS_TF49-20S-0P5SH done

Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues

B B

R

SMRST circuit

+3.3V_ALW

PCH_RSMRST#<34>

ALW_PWRGD_3V_5V<58>

A A

1
2

@

1 2

0.1U_0201_10V6K

5

P

B

4

O

A

G

3

TC7SH08FU_SSOP5~D

CZ82

PCH_RSMRST#_AND <11,14>

UZ6

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

T
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Keyboard

Keyboard

Keyboard
LA-E082P

LA-E082P

LA-E082P

45 75Monday, December 12, 2016

45 75Monday, December 12, 2016

45 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

Bat t ery LE D

means EC can switch battery white led and HDD LED by hot key “ Fn+H”

SATA_LED_EN<35>

D D

SATALED#<10,32, 40>

BAT2_LED#<34,46>

HDD LED MUX

5

BAT2_LED#_R

34

QZ2B

@

DMN65D8LDW-7_SOT363-6

+3.3V_ALW

2

61

QZ2A

@

DMN65D8LDW-7_SOT363-6

BAT2_LED#_R

BATT_WHITE#

BAT2_LED#<34,46>

R1=10K;R2= 10K

QZ3

@

R2

2

DDTA114EUA-7-F_SOT323-3

Need LINK SB000002T00 Symbol

R1

1 3

RZ25 150_0402_5%@

1 2

BAT1_LED#<34>

1 2

RZ361 150_0402_5%

1 2

RZ28 330_0402_5%

BATT_WHITE#

BATT_YELLOW#

LED P/N change to SC50000FL00 from S C50000BA00

Breath LED

QZ7B

C C

+3.3V_ALW

CZ93

@

1 2

0.1U_0201_10V6K

5

1

SYS_LED_MASK#<30,34>

LID_CL#<35,46>

B

2

A

P

MASK_BASE_LEDS#

4

O

G

UZ10

TC7SH08FU_SSOP5~D

3

BREATH_LED#<34>

DMN65D8LDW-7_SOT363-6

BREATH_LED#_Q BREATH_WHITE_LED_SNIFF#

34

5

MASK_BASE_LEDS#

1 2

RZ32 330_0402_5%

LTW-C193DC-C_WHITE

Place LED3 close to SW3

+5V_ALW

LED3

21

POWER & INSTANT ON SWITCH

SW3

1

H_3P8

2

3

4

SKRBAAE010_4P

LED Circuit Control Table

SYS_LED_MASK# LID_CL#

H9@

1

H10@

H_2P5

H_3P0

1

CLIP1@

CLIP_SH1506X616

1

4

X

H12@

H_4P0

1

H16@

H18@

H15@

H14@

H_2P3

H_4P0

H_4P0

1

1

1

H20@

H17@

H_2P5

H_4P0

1

1

1

H_4P0

H23@

H22@

H_2P5

H_2P5

1

1

H26@

H25@

H24@

H_2P3

H_2P2

1

1

1

3

H_2P5

H29@

H28@

H32@

H_2P5

H_2P6X3P6

1

1

1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTE N CONSENT.

2

0
1 0

CPU

H3@

H4@

H_3P8

H_1P1N

1

1

H36@

H37@

H_3P3

H_3P3

1

1

NGFF Standof f

H5@

H6@

H_1P1N

1

H38@

H_3P8

1

1

H8@

H7@

H_3P2

H_3P2

1

1

For JAE JSIM1 boss hole

H42@

H_0P7N

1

H43@

H_0P9N

H_2P3

1

POWER_SW#_M B<11,35>

B B

Fiducial Mark

FD1@

1

FIDUCIAL MARK~D

FD2@

1

FIDUCIAL MARK~D

FD3@

1

FIDUCIAL MARK~D

FD4@

1

FIDUCIAL MARK~D

A A

Mask All LEDs (Unobtrusive mode)

Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11

H1@

H2@

H_3P8

H_3P8

1

1

EDP Standof f GPU Standof f Frame Standof f

H34@

H35@

H_3P2

H_3P2

1

1

5

LED board CONN

CONN@

JLED1

1

1

2

2

3

3

4

4

5

5

6

6

CVILU_CF5006FD0R0-05-NH

Link CF5006FD0R0-05-NH DONE

LID_CL#<35,46>

BATT_YELLOW#
BATT_WHITE#

+3.3V_ALW

+5V_ALW

7

GND1

8

GND2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

PAD, LED

PAD, LED

PAD, LED

Document Number R ev

Document Number R ev

Document Number R e

LA-E082P

LA-E082P

LA-E082P

1

46 75Monday, December 12, 2016

46 75Monday, December 12, 2016

46 75Monday, December 12, 2016

1.0

1.0

1.0

v

5

4

3

2

1

+3.3V_WWAN/+3.3V_LAN source

PJP41

+3.3V_ALW

D D

3.3V_WWAN_EN<34>

3.3V_WWAN_EN

1 2

RZ40 100K_0402_5%

3.3V_WWAN_EN

+5V_ALW

SIO_SLP_LAN#<11,34>

UZ2

1

VIN1

VOUT1

2

VIN1

VOUT1

3

ON1

4

VBIAS

5

ON2

6

VIN2

VOUT2

VIN27VOUT2

GPAD

EM5209VF_SON14_2X3

GND

+3.3V_WW AN_UZ2

14
13

12

CT1

11
10

CT2

9

+3.3V_LAN_UZ2

8
15

1 2

PAD-OPEN1x3m

1 2

CZ119 0.1U_0201_10V6K

1 2

CZ109 470P_0402_50V7K

1 2

CZ110 470P_0402_50V7K

1 2

CZ111 0.1U_0201_10V6K

PJP37

1 2

PAD-OPEN1x1m

+3.3V_LAN

1A

+3.3V_WWAN

.5A

2

+3.3V_WWAN_UZ2

1

RF@

2200P_0402_50V7K

2

RF Request

CZ124

+1.8V_RUN source

RUN_ON<17,34,35,47,61>

1 2

@

RZ345 0_0402_5%

Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V

RUN_ON_1.8V

+5V_ALW

12

CZ197

@

470P_0402_50V7K

+1.8V_PRIM

UZ8

1

VOUT

VIN

2

VOUT

VIN

3

ON

4

VBIAS

AOZ1336_DFN8_2X2

GND
GND

0.013A

PJP42

1 2

7

+1.8V_RUN_UZ8

8
6

CT

5
9

PAD-OPEN1x1m

1 2

CZ120 0.1U_0201_10V6K

1 2

CZ121 470P_0402_50V7K

+1.8V_RUN

+3.3V_ALW_PCH/+3.3V_RUN source

0.63A

PJP38

1 2

+3.3V_ALW

C C

1 2

PCH_ALW_ON<34>

SIO_SLP_SUS#<11,17,34,60,61,62>

RZ65 0_0402_5%@

@

1 2

RZ64 0_0402_5%

+5V_ALW

RUN_ON

UZ3

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14_2X3

VOUT1
VOUT1

GND

VOUT2

GPAD

CT1

CT2

+3.3V_ALW_PCH_UZ3

14
13

12
11
10
9

+3.3V_RUN_UZ3

8
15

1 2

CZ112 0.1U_0201_10V6K

1 2

CZ113 470P_0402_50V7K

1 2

CZ114 1000P_0402_50V7K

1 2

CZ115 0.1U_0201_10V6K

1 2

PAD-OPEN1x1m

PJP39

+3.3V_ALW_PCH

+3.3V_RUN

.435A

3

+5V_RUN/+3.3V_WLAN source

B B

PJP40

+5V_ALW

RUN_ON<17,34,35,47,61>
SIO_SLP_WLAN#<11,34>
AUX_EN_WOW L<34>

1 2

RZ38 100K_0402_5%

A A

1 2

RZ71 0_0402_5%@

1 2

@

RZ70 0_0402_5%

+3.3V_ALW

AUX_EN_WOW L

5

UZ4

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14_2X3

VOUT1
VOUT1

GND

VOUT2

GPAD

CT1

CT2

14
13

12
11
10

+3.3V_WLAN_UZ4

9
8

15

+5V_RUN_UZ4

1 2

CZ116 0.1U_0201_10V6K

CZ117 470P_0402_50V7K

CZ118 470P_0402_50V7K

CZ122 0.1U_0201_10V6K

1 2

4

PAD-OPEN1x2m

1 2

1 2

1 2
1 2

PAD-OPEN1x2m

PJP36

2A

+5V_RUN

+3.3V_WLAN

2A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Power control

Power control

Power control

LA-E082P

LA-E082P

LA-E082P

1

47 75Monday, December 12, 2016

47 75Monday, December 12, 2016

47 75Monday, December 12, 2016

1.0

1.0

1.0

5

PEG_CTX_C_GRX_P[0..3]<10>
PEG_CTX_C_GRX_N[0..3]<10>

PEG_CRX_GTX_P[0..3]<10>
PEG_CRX_GTX_N[0..3]<10>

D D

CLKREQ_PCIE#0<11>

C C

B B

A A

PEG_CRX_GTX_P0
PEG_CRX_GTX_N0

PEG_CRX_GTX_P1 PEG_CRX_C_GTX_P1
PEG_CRX_GTX_N1

PEG_CRX_GTX_P2
PEG_CRX_GTX_N2

PEG_CRX_GTX_P3
PEG_CRX_GTX_N3

VRAM_EN<52,69>

RV202

10K_0402_5%

DGPU_HOLD_RST#<9>

PLTRST_GPU#<11>

SYS_PEX_RST_MON#
GPU_PEX_RST_HOLD#

GPU_PWR_LEVEL<35>

CV201 0.22U_0402_16V7K
CV202 0.22U_0402_16V7K

CV203 0.22U_0402_16V7K
CV204 0.22U_0402_16V7K

CV205 0.22U_0402_16V7K
CV206 0.22U_0402_16V7K

CV207 0.22U_0402_16V7K
CV208 0.22U_0402_16V7K

QV10

1 3

D

L2N7002W T1G_SC-70-3

1 2

RV200 0_0402_5%@

+3.3V_ALW

12

1
2

+3.3V_ALW

0.1U_0402_10V7K

1

@

CV311

2

1
2

5

+3.3V_GFX_AON

2

G

S

5

P

B

O

A

G

UV14

3

TC7SH08FU_SSOP5~D

5

UV25

P

B

Y

A

G

TC7SH08FU_SSOP5

3

1 2

@

RV210

PEG_CTX_C_GRX_P[0..3]
PEG_CTX_C_GRX_N[0..3]
PEG_CRX_GTX_P[0..3]
PEG_CRX_GTX_N[0..3]

12
12

12
12

12
12

12
12

10K_0402_5%

RV201

12

DGPU_PEX_RST# DGPU_PEX_RST_R#

0.1U_0402_10V7K

@

CV209

1

2

SYS_PEX_RST_MON#_R

4

4

0_0402_5%

PEG_CRX_C_GTX_P0

PEG_CRX_C_GTX_N0

PEG_CRX_C_GTX_N1

PEG_CRX_C_GTX_P2

PEG_CRX_C_GTX_N2

PEG_CRX_C_GTX_P3

PEG_CRX_C_GTX_N3

GFXCLK_REQ_Q#

CLK_PCIE_P0<11>
CLK_PCIE_N0<11>

1 2

RV207 200_0402_1%@

1 2

@

RV208

RV209 2.49K_0402_1%

1 2

@

RV204

10K_0402_5%

12

RV203

0_0402_5%

12

@

RV206

DGPU_PEX_RST#

10K_0402_5%

12

RV205

GPU_HOT#

12

0_0402_5%

4

PEG_CTX_C_GRX_P0
PEG_CTX_C_GRX_N0
PEG_CTX_C_GRX_P1
PEG_CTX_C_GRX_N1
PEG_CTX_C_GRX_P2
PEG_CTX_C_GRX_N2
PEG_CTX_C_GRX_P3
PEG_CTX_C_GRX_N3

PEG_CRX_C_GTX_P0
PEG_CRX_C_GTX_N0
PEG_CRX_C_GTX_P1
PEG_CRX_C_GTX_N1
PEG_CRX_C_GTX_P2
PEG_CRX_C_GTX_N2
PEG_CRX_C_GTX_P3
PEG_CRX_C_GTX_N3

CLK_PCIE_N0

GFXCLK_REQ_Q#
PEX_TSTCLK_OUT

PEX_TSTCLK_OUT#

SYS_PEX_RST_MON# <49>

0_0402_5%

GPU_PWR_LEVEL

LOW Low Performace
HIGH

4

UV1A

AG6

PEX_RX0

AG7

PEX_RX0_N

AF7

PEX_RX1

AE7

PEX_RX1_N

AE9

PEX_RX2

AF9

PEX_RX2_N

AG9

PEX_RX3

AG10

PEX_RX3_N

AF10

NC

AE10

NC

AE12

NC

AF12

NC

AG12

NC

AG13

NC

AF13

NC

AE13

NC

AE15

NC

AF15

NC

AG15

NC

AG16

NC

AF16

NC

AE16

NC

AE18

NC

AF18

NC

AG18

NC

AG19

NC

AF19

NC

AE19

NC

AE21

NC

AF21

NC

AG21

NC

AG22

NC

AC9

PEX_TX0

AB9

PEX_TX0_N

AB10

PEX_TX1

AC10

PEX_TX1_N

AD11

PEX_TX2

AC11

PEX_TX2_N

AC12

PEX_TX3

AB12

PEX_TX3_N

AB13

NC

AC13

NC

AD14

NC

AC14

NC

AC15

NC

AB15

NC

AB16

NC

AC16

NC

AD17

NC

AC17

NC

AC18

NC

AB18

NC

AB19

NC

AC19

NC

AD20

NC

AC20

NC

AC21

NC

AB21

NC

AD23

NC

AE23

NC

AF24

NC

AE24

NC

AG24

NC

AG25

NC

AE8

PEX_REFCLK

AD8

PEX_REFCLK_N

AC6

PEX_CLKREQ_N

AF22

PEX_TSTCLK_OUT

AE22

PEX_TSTCLK_OUT_N

AC7

PEX_RST_N

AF25

PEX_TERMP

GM108-ES-S-A1_FCBGA595

High Performace

Part 1 of 6

PCI EXPRESS

GPIO

DACsI2C

CLK

CV215

18P_0402_50V8J

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

OVERT

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

PEX_WAKE_NC

TSEN_VREF

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2CS_SCL

I2CS_SDA

PLLVDD

SP_PLLVDD

XTAL_IN

XTAL_OUT

XTAL_SSIN

XTAL_OUTBUFF

27MHZ_12PF_X1E000021042600

1

2

GPU_SMBCLK_R

3

GPU_GC6_FB_EN

C6
B2
D6
C7
F9
A3

GC6_EVENT#_D

A4
B6

THERMATRIP_GPU#

A6
F8

FBVREF_ALTV

C5

GPU_PWM_VID

E7

GPU_HOT#

D7
B4
B3
C3
D5
D4
C2
F7
E6
C4

AB6

AG3

NC

AF4

NC

AF3

NC

AE3

NC

AE4

NC

W5

NC

AE2
AF2

NC

B7
A7

RV212 1.8K_0402_5%
RV213 1.8K_0402_5%

C9
C8

RV214 1.8K_0402_5%
RV215 1.8K_0402_5%

A9
B9

RV216 1.8K_0402_5%
RV217 1.8K_0402_5%

GPU_SMBCLK_R

D9

GPU_SMBDAT_R

D8

L6
M6

N6

GPU_CLK_27M_IN

C11

GPU_CLK_27M_OUT

B10
A10

XTALSSIN

C10

XTALOUTBUFF

YV1

1

IN

OUT

2

GND

GND

1 2

RV231 0_0402_5%@

QV12B

4

5
2

QV12A

1 2

RV234 0_0402_5%@

3

2

GPU_GC6_FB_EN <12,52>

GPU_PEX_RST_HOLD#

1 2
1 2

1 2
1 2

1 2
1 2

3V3_MAIN_EN <52,68>

GPU_PWM_VID <68>
NVVDD_PSI <68>

GC6_EVENT#_D

THERMATRIP_GPU#

RB751S40T1G_SOD523-2

1 2

RV211 0_0402_5%@

DGPU_PEX_RST#

Place close to ball

+CORE_PLLVDD

1 2
1 2

RV228 10K_0402_5%
RV229 10K_0402_5%

GPU_CLK_27M_OUT_RGPU_CLK_27M_IN

3
4

1

CV216

2

18P_0402_50V8J

0.1U_0402_10V7K

1

+PLLVDD

1 2

RV230 910_0402_5%

0.1U_0402_10V7K

1

2

GPU_CLK_27M_OUT

CV210

CV212

22U_0603_6.3V6M

PBY160808T-300Y-N_2P

CV211

22U_0603_6.3V6M

4.7U_0603_6.3V6K

1

1

CV214

CV213

2

2

SP_PLLVDD and VID_PLLVDD Powe
rail Filtering Combined

Capacitor Typ

EXPANDER_GPU_SMCLK

3

DMN66D0LDW-7_SOT363-6

@

RV232

RV233 0_0402_5%@

DMN66D0LDW-7_SOT363-6

EXPANDER_GPU_SMDATGPU_SMBDAT_R

61

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2
1 2

DGPU_PEX_RST#

0_0402_5%

EXPANDER_GPU_SMCLK <34,35>

+3.3V_RUN_GFX

EXPANDER_GPU_SMDAT <34,35>

2

Bead 180 oh
(ESR=0.2 ohm)
060

12

DV10

D

S

13

QV11

G

L2N7002W T1G_SC-70-3

2

LV10

12

LV8

PBY160808T-181Y-N_2P

0.1uF 040

4.7uF 060
22uF 0805

3

12

2
3

m

1

GC6_EVENT# <12>

THERMATRIP1# <34>

e

+1.0V_PEX_VDD

Populatio
1 per bal

1
1

1

GPU_SMBCLK_R
GPU_SMBDAT_R

THERMATRIP_GPU#
NVVDD_PSI
GPU_HOT#
3V3_MAIN_EN
GPU_PEX_RST_HOLD#
GC6_EVENT#_D
SYS_PEX_RST_MON#

FBVREF_ALTV
GPU_GC6_FB_EN

+1.0V_PEX_VDD

r

n
l

1 2

RV218 1.8K_0402_5%

1 2

RV219 1.8K_0402_5%

RV222 10K_0402_5%

1 2

RV220 10K_0402_5%

1 2

RV221 100K_0402_5%
RV223 10K_0402_5%
RV224 10K_0402_5%
RV225 10K_0402_5%
RV226 10K_0402_5%@

1 2

RV227 100K_0402_5%
RV299 10K_0402_5%

PLLVDD Filterin

Capacitor Typ

0.1uF 040

2

22uF 0805
Bead 30 ohm
(ESR=0.05 ohm
040

2

12

12
12
12
12

12

e

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

N15S PCIE,I2C,DAC,GPIO

N15S PCIE,I2C,DAC,GPIO

N15S PCIE,I2C,DAC,GPIO
LA-E082P

LA-E082P

LA-E082P

1

+3.3V_RUN_GFX

+3.3V_GFX_AON

g

Populatio

)

48 75Monday, December 12, 2016

48 75Monday, December 12, 2016

48 75Monday, December 12, 2016

n
1
1

1

1.0

1.0

1.0

5

4

3

2

1

UV1C

AC3

NC

AC4

NC

Y4

NC

Y3

NC

AA3

NC

AA2

NC

AB1

NC

AA1

NC

AA4

NC

AA5

D D

I2CS Slave Addres

SMBUS_ALT_ADD

01

s

R

0x9E(Default)

Description

0x9C(Multi-GPU usage)

VGA_DEVICE Settin

VGA_DEVIC

0

1

C C

Resistance Mapping to Hex Value

Resistor ValuePull-up to VDD33Pull-down to GN

4.99K

10K

15K

20K

24.9K

30.1K

34.8K

45.3K

B B

Decive

+3.3V_GFX_AON +3.3V_RUN_GFX

g

EDescriptio

n

Non-Primary 3D Acceleration Device(Class Code 302h)

Primary Display or VGA Device(Class Code 300h

s

D

100

0

100

1

101

0

101

1

110

0

110

1

111

0

111

1

000

0

000

1

001

0

001

1

010

0

010

1

011

0

011

1

ID change to 0x1056

)

NC

AB5

NC

AB4

NC

AB3

NC

AB2

NC

AD3

NC

AD2

NC

AE1

NC

AD1

NC

AD4

NC

AD5

NC

T2

NC

T3

NC

T1

NC

R1

NC

R2

NC

R3

NC

N2

NC

N3

NC

V3

NC

V4

NC

U3

NC

U4

NC

T4

NC

T5

NC

R4

NC

R5

NC

N1

NC

M1

NC

M2

NC

M3

NC

K2

NC

K3

NC

K1

NC

J1

NC

M4

NC

M5

NC

L3

NC

L4

NC
NC

K5

NC

J4

NC

J5

NC

N4

NC

N5

NC

P3

NC

P4

NC

J2

NC

J3

NC

H3

NC

H4

NC

GM108-ES-S-A1_FCBGA595

Part 3 of 6

NC

GENERAL

MULTI_STRAP_REF0_GND

LVDS/TMDS

GND_SENSE

TEST

JTAG_TRST_N

SERIAL

FBA_CMD32

BUFRST_N

GPIO8

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

THERMDP
THERMDN

VDD_SENSE

TESTMODE

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

ROM_CS_N

ROM_SI

ROM_SO

ROM_SCLK

F11

NC

AD10

NC

AD7

NC

B19
V5

NC

V6

NC

G1

NC

G2

NC

G3

NC

G4

NC

G5

NC

G6

NC

G7

NC

V1

NC

V2

NC

W1

NC

W2

NC

W3

NC

W4

NC

D11
D10

NC

E9
E10

NC

F10

NC

D1
D2
E4
E3
D3
C1

NC

F6
F4

NC

F5

NC

F12
E12

F2

F1

AD9
AE5
AE6
AF6
AD6
AG4

D12
B12
A12
C12

1 2

RV251 10K_0402_5%@

SYS_PEX_RST_MON#

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GND
MULTI_STRAP_REF2_GND

GPU_VDD_SENSE <68>

GPU_VSS_SENSE <68>

GPU_TESTMODE
GPU_JTAG_TCK
GPU_JTAG_TDI
GPU_JTAG_TDO
GPU_JTAG_TMS
GPU_JTAG_TRST#

ROM_SI_GPU
ROM_SO_GPU
ROM_SCLK_GPU

SYS_PEX_RST_MON# <48>

1 2
1 2

RV252 40.2K_0402_1%

1 2

RV253 40.2K_0402_1%@
RV254 40.2K_0402_1%@

1 2

RV255 10K_0402_5%

1 2

RV256 10K_0402_5%

UV1E

A2

GND_001

A26

GND_002

AB11

GND_003

AB14

GND_004

AB17

GND_005

AB20

GND_006

AB24

GND_007

AC2

GND_008

AC22

GND_009

AC26

GND_010

AC5

GND_011

AC8

GND_012

AD12

GND_013

AD13

GND_014

AD15

GND_015

AD16

GND_016

AD18

GND_017

AD19

GND_018

AD21

GND_019

AD22

GND_020

AE11

GND_021

AE14

GND_022

AE17

GND_023

AE20

GND_024

AF1

GND_025

AF11

GND_026

AF14

GND_027

AF17

GND_028

AF20

GND_029

AF23

GND_030

AF5

GND_031

AF8

GND_032

AG2

GND_033

AG26

GND_034

B1

GND_035

B11

GND_036

B14

GND_037

B17

GND_038

B20

GND_039

B23

GND_040

B27

GND_041

B5

GND_042

B8

GND_043

E11

GND_044

E14

GND_045

E17

GND_046

E2

GND_047

E20

GND_048

E22

GND_049

E25

GND_050

E5

GND_051

E8

GND_052

H2

GND_053

H23

GND_054

H25

GND_055

H5

GND_056

GM108-ES-S-A1_FCBGA595

GPU_JTAG_TDO
GPU_JTAG_TDI
GPU_JTAG_TCK
GPU_JTAG_TMS

Part 5 of 6

RPV1

@

6
7
8

10K_8P4R_5%

45
3
2
1

GND

+3.3V_GFX_AON

GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112

GND
GND

K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5

AA7
AB7

Strap Pin Name Logical Strapping Bit 3 Logical Strapping Bit 2 Logical Strapping Bit 1 Logical Strapping Bit 0

OM_SCLK

RV237

RV235

@

1 2

8.45K_0402_1%

49.9K_0402_1%

A A

RV236

RV238

2K_0402_1%

2K_0402_1%

@

@

1 2

RV241

RV239

@

@

1 2

1 2

8.45K_0402_1%

8.45K_0402_1%

RV240

RV242

2K_0402_1%

2K_0402_1%

@

@

1 2

1 2

RV245

RV243

@

1 2

1 2

8.45K_0402_1%

@

1 2

8.45K_0402_1%

2K_0402_1%

RV244

RV246

1 2

@

4.99K_0402_1%

5

RV249

RV247

@

@

1 2

1 2

1 2

34.8K_0402_1%

8.45K_0402_1%

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU

RV250

RV248

10K_0402_1%

1 2

1 2

1 2

4.99K_0402_1%

R

ROM_SI

ROM_SO

STRAP0

STRAP1
STRAP2
STRAP3
STRAP4

EVID_SEL/PCIE_CFG defaul set 0, need refer Platform Update Notification for the latest configuration

D

4

SOR3_EXPOSED->0 SOR2_EXPOSED->0 SOR1_EXPOSED->0 SOR0_EXPOSED->0

RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]

DEVID_SEL->0(default) PCIE_CFG->0(defual) SMB_ALT_ADDR->0(default) VGA_DEVICE->0

Keep pull up to 3V3_AON and pull-down to GND footprint and stuff 50k ohm pull up

Reserve

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Note

ROM_SCLK pull-down RV246 4.99k to GND

ROM_SI pull-down RV248 24.9k to GND

ROM_SO pull-down RV250 4.99k to GND

STRAP0 pull up RV235 50k to +3.3V_GFX_AON

2

STRAP

VENDER

Hyn ix

Micron

Samsung

0x7

0x6

0x1

Part Number

H5TC4G63CFR-N0C

MT41J256M16LY-091G:N

K4W4G1646E-BC1A

Note(ROM_SI)

RV248 45.3k PD

RV248 34.8k PD

RV248 10k PD

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.
N15S DP, STRAP, GND

N15S DP, STRAP, GND

N15S DP, STRAP, GND
LA-E082P

LA-E082P

LA-E082P

1

1.0

1.0

49 75Monday, December 12, 2016

49 75Monday, December 12, 2016

49 75Monday, December 12, 2016

1.0

5

+1.35V_MEM_GFX

22U_0603_6.3V6M

1

1

CV217

2

D D

2

DDR3 CPU side FBVDD/FBVDD

I=2000mA

PL

ACE UNDER GPUPLACE NEAR GPU

10U_0603_6.3V6M

4.7U_0603_6.3V6K

1

CV218

CV219

2

1U_0402_6.3V6K

4.7U_0603_6.3V6K

1

1

CV221

CV220

2

2

Q
Combined Decoupling
Capacitor Typ

0.1uF 040

1.0uF 060

4.7uF 060

10uF 0805

C C

B B

22uF 0805

Power Supply Rail

Power Supply Rail

Power Supply Rail

Power Supply Rail

GPU_Cor

e

GPU_Cor

e

GPU_Cor

e

GPU_Cor

e

GPU_FBI

O

GPU_FBI

O

GPU_FBI

O

GPU_FBI

O

PEX_IOVDD/Q

PEX_PLLVD

D

FBA_PLL_AVD

FBA_DLL_AVD

PLL_VDD

SP_PLLVDD

1.1V Tota

1.1V Tota

1.1V Tota

1.1V Tota

VDD33+3V3AO

PEX_SVDD_3V

PEX_PLL_HVD

3.3V Tota

3.3V Tota

3.3V Tota

3.3V Tota

e

2

Populatio

3
3

n
2
2
2
1
1

N16S-GM

R

N16S-GM

R

N16S-GM

R

N16S-GM

R

(V)

(V)

(V)(V

-

-

-

-

1.5/1.3

1.5/1.3

1.5/1.3

1.5/1.3

1.0

1.0

D

1.0

D

1.0

1.0

1.0

l

l

1.0

l

l

N

3.3

3

3.3

D

3.3

l

l

3.3

3.3

l

l

3.33.

3

(A)

(A)

)

(A)(A

)

2

1

5

5

5

5

1.4

0.8

0.0

6

4

UV1D

B26

C25

E23
E26

1U_0402_6.3V6K

1

CV222

2

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

CV224

CV223

2

2

F14

F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26

J21
K21
L22
L24
L26

M21
N21
R21

T21
V21

W21

V7

W7

AA6

W6

Y6

M7
N7
T6
P6

T7
R7
U6
R6

J7

K6
H6

J6

GM108-ES-S-A1_FCBGA595

FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27

NC
NC
NC
NC
NC

NC
NC
NC
NC

IFPD_PLLVDD_2
NC
IFPD_RSET
NC

NC
NC
NC
NC
NC

Part 4 of 6

FB_CAL_TERM_GND

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

POWER

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

PEX_PLL_HVDD_1
PEX_PLL_HVDD_2

PEX_SVDD_3V3

PEX_PLLVDD_1

PEX_PLLVDD_2

3

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

AA22
AB23
AC24
AD25
AE26
AE27

G10

3V3_AON

G12

3V3_AON

G8

VDD33_3

G9

VDD33_4

D22

C24

B25

AA8
AA9

AB8

AA14
AA15

PEX_PLLVDD Decoupling

Capacitor Typ

0.1uF 040

4.7uF 080

PLACE NEAR BALLS PLACE NEAR GPU

1 2

RV257 40.2_0402_1%

1 2

RV258 42.2_0402_1%

1 2

RV259 51.1_0402_1%

1U_0402_6.3V6K

1

CV225

2

+1.35V_MEM_GFX

PLACE NEAR BGA

4.7U_0603_6.3V6K

1

2

CV239

Populatio

4.7U_0603_6.3V6K

CV237

CV238

1

2

1U_0402_6.3V6K

1

2

11

1

0.1U_0402_10V7K
CV236

1

2

PLACE UNDER GPUPLACE NEAR GPU

0.1U_0402_10V7K

1

2

e

2

1uF 060

3

5

CV240

n

4.7U_0603_6.3V6K

1

CV226

2

+3.3V_GFX_AON

4.7U_0603_6.3V6K

1

CV241

2

2

PLACE BETWEEN GPU
AN

D POWER SUPPLY

10U_0603_6.3V6M

1

CV227

2

22U_0603_6.3V6M

1

2

+1.0V_PEX_VDD

CV228

PLACE NEAR GPUPLACE UNDER GPU

1

2

+1.0V_PEX_VDD

0.1U_0402_10V7K

1

CV229

2

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CV232

CV233

2

1U_0402_6.3V6K

1

CV230

2

1U_0402_6.3V6K

1

CV234

2

PEX_SVDD/PEX_PLL_HVDD Decouplin

Capacitor TypePopulatio

0.1uF 040

4.7uF 060

2

12

3

+3.3V_GFX_AON

4.7U_0603_6.3V6K

1

CV231

2

4.7U_0603_6.3V6K

1

CV235

2

g

n

1

PEX_IOVDD/Q Power Rail Combined

Capacitor Typ

1uF 040

4.7uF 060

e

Populatio

2

3
10uF 0805
22uF 0805

GC6 2.0 G10/G12 pin connect t
+3.3V_GFX_AON

+3.3V_RUN_GFX

3V3_MAIN Decoupling

Capacitor Typ

0.1uF 040
1uF 060

4.7uF 060

e

Populatio

2

21

3

3

1

n

11

11

o

n

3V3_AON Decouplin

Capacitor Typ

0.1uF 040

A A

1uF 060

4.7uF 060

g

e

Populatio

2

3

3

n
1
1
1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.
N15S Power

N15S Power

N15S Power
LA-E082P

LA-E082P

LA-E082P

50 75Monday, December 12, 2016

50 75Monday, December 12, 2016

50 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

Caps on Power Side
1UX4 4.7UX10 under GPU

4.7UX5 22UX1 47UX2 330UX2 near GPU

D D

+GPU_CORE

C C

UV1F

K10

VDD_001

K12

VDD_002

K14

VDD_003

K16

VDD_004

K18

VDD_005

L11

VDD_006

L13

VDD_007

L15

VDD_008

L17

VDD_009

M10

VDD_010

M12

VDD_011

M14

VDD_012

M16

VDD_013

M18

VDD_014

N11

VDD_015

N13

VDD_016

N15

VDD_017

N17

VDD_018

P10

VDD_019

P12

VDD_020

GM108-ES-S-A1_FCBGA595

Part 6 of 6

POWER

VDD_041
VDD_040
VDD_039
VDD_038
VDD_037
VDD_036
VDD_035
VDD_034
VDD_033
VDD_032
VDD_031
VDD_030
VDD_029
VDD_028
VDD_027
VDD_026
VDD_025
VDD_024
VDD_023
VDD_022
VDD_021

+GPU_CORE

V18
V16
V14
V12
V10
U17
U15
U13
U11
T18
T16
T14
T12
T10
R17
R15
R13
R11
P18
P16
P14

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

TRADE
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

N15S Power GFX Core

N15S Power GFX Core

N15S Power GFX Core
LA-E082P

LA-E082P

LA-E082P

Monday, December 12, 2016

Monday, December 12, 2016

Monday, December 12, 2016

1.0

1.0

51

51

51

1

1.0

75

75

75

5

DDR3L CMD Mapping Table

CS0#

CMD0
CMD1
CMD2
CMD3
CMD4

CMD6
CMD7

D D

CMD8

CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CM

D28
CMD29
CMD30
CMD31

C C

+1.0V_PEX_VDD

B B

LV26

1 2

PBY160808T-300Y-N_2P

FBx_PLL_AVDD and FB_DLL_AVD
Combine

d

Capacitor TypePopulatio

0.1uF 040

CMD32
CMD33

ODT

CMD34

CKE

CMD35

A14

CMD36
RSTCMD5
A9

CMD38
A7

CMD39
A2

CMD40
A0

CMD41
A4

CMD42
A1

CMD43
BA0

CMD44
WE#

CMD45

A1

CMD46

5 A15

CAS#

CMD49

CMD50

CMD51
A13

CMD52
A8

CMD53
A6

CMD54
A11

CMD55
A5

CMD56
A3

CMD57
BA2

CMD58
BA1

CMD59
A12

CMD60
A10

CMD61
RAS#

CMD62

CMD63

+FB_PLLAVDD

1

2

ACE CLOSE to GPU

PL

+1.35V_MEM_GFX

2

21

A14
RSTCMD37
A9
A7
A2
A0
A4
A1
BA0
WE#

CAS#CMD47
CS0#CMD48

ODT
CKE
A13
A8
A6
A11
A5
A3
BA2
BA1
A12
A10
RAS#

PLACE UNDER GPU

22U_0603_6.3V6M

1

CV242

2

D

n

0.1U_0402_10V7K

0.1U_0402_10V7K

1

@

CV243

CV244

2

0.1U_0402_10V7K

1

CV245

2

@ PAD~D

T95

I=35mA

FB_CLAMP_GPU

RV260 10K_0402_5%

RV261 60.4_0402_1%@
RV262 60.4_0402_1%@

12

12
12

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53

FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

D20
D21

D15

C13

D13
C16

C19
C23

C20
C21
R22
R24

R23
N25
N26
N23
N24

U22
AA24
AA23

AD27
AB25
AD26
AC25
AA27
AA26

R26

N27

R27

W27

W25

D23

H22

4

UV1B

E18

FBA_D00

F18

FBA_D01

E16

FBA_D02

F17

FBA_D03
FBA_D04
FBA_D05

F20

FBA_D06

E21

FBA_D07

E15

FBA_D08
FBA_D09

F15

FBA_D10

F13

FBA_D11
FBA_D12

B13

FBA_D13

E13

FBA_D14
FBA_D15

B15

FBA_D16
FBA_D17

A13

FBA_D18

A15

FBA_D19

B18

FBA_D20

A18

FBA_D21

A19

FBA_D22
FBA_D23

B24

FBA_D24
FBA_D25

A25

FBA_D26

A24

FBA_D27

A21

FBA_D28

B21

FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33

T22

FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39

V23

FBA_D40

V22

FBA_D41

T23

FBA_D42
FBA_D43

Y24

FBA_D44
FBA_D45

Y22

FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54

Y25

FBA_D55
FBA_D56

T25

FBA_D57
FBA_D58
FBA_D59

V26

FBA_D60

V27

FBA_D61
FBA_D62
FBA_D63

F16

FB_PLLAVDD_1

P22

FB_PLLAVDD_2
FB_VREF_PROBE

FB_DLLAVDD

F3

FB_CLAMP

F22

FBA_CMD34

J22

FBA_CMD35

GM108-ES-S-A1_FCBGA595

Part 2 of 6

MEMORY

FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_DQS_RN0
FBA_DQS_RN1

INTERFACE A

FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_CLK0_N

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_CLK0

FBA_CLK1

C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26

D19
D14
C17
C22
P24
W24
AA25
U25

F19
C14
A16
A22
P25
W22
AB27
T27

E19
C15
B16

R25
W23
AB26
T26

D24
D25

N22
M22

D18
C18
D17
D16
T24
U24
V24
V25

FBA_CMD1
FBA_CMD2
FBA_CMD3

FBA_CMD17
FBA_CMD18
FBA_CMD19

FBA_CMD31

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_RN0
FBA_RN1
FBA_RN2
FBA_RN3
FBA_RN4
FBA_RN5
FBA_RN6
FBA_RN7

FBA_WP0
FBA_WP1
FBA_WP2

FBA_WP4
FBA_WP5
FBA_WP6
FBA_WP7

3

FBA_CMD0 <53>

T110 @PAD~D

FBA_CMD2 <53>
FBA_CMD3 <53>
FBA_CMD4 <53,54>
FBA_CMD5 <53,54>
FBA_CMD6 <53,54>
FBA_CMD7 <53,54>
FBA_CMD8 <53,54>
FBA_CMD9 <53,54>
FBA_CMD10 <53,54>
FBA_CMD11 <53,54>
FBA_CMD12 <53,54>
FBA_CMD13 <53,54>
FBA_CMD14 <53,54>
FBA_CMD15 <53,54>
FBA_CMD16 <54>

T111 @PAD~D

FBA_CMD18 <54>
FBA_CMD19 <54>
FBA_CMD20 <53,54>
FBA_CMD21 <53,54>
FBA_CMD22 <53,54>
FBA_CMD23 <53,54>
FBA_CMD24 <53,54>
FBA_CMD25 <53,54>
FBA_CMD26 <53,54>
FBA_CMD27 <53,54>
FBA_CMD28 <53,54>
FBA_CMD29 <53,54>
FBA_CMD30 <53,54>

T112 @PAD~D

CLKA0 <53>
CLKA0# <53>

CLKA1 <54>
CLKA1# <54>

RV263

RV269

FBA_D[32..63]

FBA_DQM[4..7]

1 2

3V3_MAIN_EN_R

0_0402_5%

FBA_D[0..31]
FBA_RN[0..3] FBA_RN[4..7]
FBA_DQM[0..3]
FBA_WP[0..3] FBA_WP[4..7]

3V3_MAIN_EN<48,68>

FBA_CMD5

FBA_D[0..31] <53>

FBA_RN[0..3] <53>

FBA_DQM[0..3] <53>

FBA_WP[0..3] <53>

FBA_RST

10K_0402_5%

12

@

+1.35V_MEM_GFX

+5V_ALW

+3.3V_RUN

2

FBA_D[32..63] <54>

FBA_RN[4..7] <54>

FBA_DQM[4..7] <54>

FBA_WP[4..7] <54>

DGPU_PWR_EN<9>

+1.0V_PRIM

FBA_ODT_L
FBA_ODT_H
FBA

_CKE_L

FBA_CKE_H

+5V_RUN

100K_0402_5%

12

13

D

2

G

S

UV15

1

VIN1

VOUT1

2

VIN1

VOUT1

3

ON1

ON2
VIN2

VOUT2

VIN27VOUT2

GPAD

CT1

CT2

4
5
6

EM5209VF_SON14_2X3

+3.3V_RUN

RV268

L2N7002WT1G_SC-70-3

QV13

14
13

12
11
10
9

8
15

FBA_CMD2
FBA_CMD18
FBA_CMD3
FBA_CMD19

QV14

LP2301ALT1G_SOT23-3

S

DGPU_PWR_EN#

+1.0V_PEX_VDD

+1.05V_PEX_VDD_UV15

+3.3V_RUN_GFX_UV15

1 2

RV264

1 2

RV265

1 2

RV266

1 2

RV267

+3.3V_GFX_AON

D

123

G

12

PJP44
PAD-OPEN1x1m

CV246 0.1U_0402_10V7K

CV247

CV248 470P_0402_50V7K

0.1U_0402_10V7K
CV249

1 2

1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

0.1U_0402_25V6
CV252

12

1 2

1 2

1 2

PJP43

1 2

PAD-OPEN1x1m

4700P_0402_25V7K

+3.3V_RUN_GFX

22uF 0805

Bead 30 ohm
(ESR=0.01 ohm

060

3

A A

1

)

DGPU_PWROK<12,35,68>

GPU_GC6_FB_EN<12,48>

DGPU_PWROK

DV8

3

2

BAT54CW_SOT323-3

1

200K_0402_5%

12

@

RV270

VRAM_EN <48,69>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.
N15S Memory

N15S Memory

N15S Memory
LA-E082P

LA-E082P

LA-E082P

52 75Monday, December 12, 2016

52 75Monday, December 12, 2016

52 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

Memory Partition A - Upper 16 bits

3

256x16 DDR3L

2

1

FBA_D[0..31]

FBA_WP[0..3]
FBA_DQM[0..3]
FBA_RN[0..3]

D D

C C

CLKA0<52>

CLKA0#<52>

B B

A A

FBA_D[0..31] <52>

FBA_WP[0..3] <52>
FBA_DQM[0..3] <52>
FBA_RN[0..3] <52>

+FBA_VREF_CA0
+FBA_VREF_DQ0

FBA_CMD9<52,54>
FBA_CMD11<52,54>
FBA_CMD8<52,54>
FBA_CMD25<52,54>
FBA_CMD10<52,54>
FBA_CMD24<52,54>
FBA_CMD22<52,54>
FBA_CMD7<52,54>
FBA_CMD21<52,54>
FBA_CMD6<52,54>
FBA_CMD29<52,54>
FBA_CMD23<52,54>
FBA_CMD28<52,54>
FBA_CMD20<52,54>
FBA_CMD4<52,54>
FBA_CMD14<52,54>

FBA_CMD12<52,54>
FBA_CMD27<52,54>
FBA_CMD26<52,54>

RV300

1 2

162_0402_1%

80.6_0402_1%

@

12

RV281

CLKA0_C

0.01UF_0402_25V7K

@

CV309

1

2

+1.35V_MEM_GFX +1.35V_MEM_GFX

1.33K_0402_1%

12

RV288

1.33K_0402_1%

12

RV289

0.01UF_0402_25V7K

1

2

5

@

12

RV282

FBA_CMD5<52,54>

+FBA_VREF_CA0

CV274

80.6_0402_1%

+FBA_VREF_CA0
+FBA_VREF_DQ0

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14 FBA_CMD14

FBA_CMD12
FBA_CMD27
FBA_CMD26

CLKA0

12

CLKA0#

RV285

FBA_CMD3<52>

FBA_CMD2<52>
FBA_CMD0<52>
FBA_CMD30<52,54>
FBA_CMD15<52,54>
FBA_CMD13<52,54>

243_0402_1%

FBA_CMD3

FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13

FBA_WP2

FBA_DQM1
FBA_DQM2

FBA_RN2 FBA_RN3

FBA_CMD5
FBA_ZQ0

1.33K_0402_1%

12

RV286

1.33K_0402_1%

12

RV287

0.01UF_0402_25V7K
CV273

1

2

+FBA_VREF_DQ0

UV17

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2
R3
R7

N7

M7

M2
N8
M3

C7

D3

G3

ADDRESSControl & DQM

A7

T8

A8
A9

L7

A10/AP
A11
A12/BC

T3

A13

T7

A14
NC

BA0
BA1
BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL
DQSU

E7

DML
DMU

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC

L1

NC

J9

NC

L9

NCZQ1

96-BALL
SDRAM DDR3

H5TC4G63AFR-11C_FBGA96

4

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

DATAPOWERGND

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ
VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

SA00006E800 Link done

FBA_D11
FBA_D13
FBA_D10
FBA_D15
FBA_D9
FBA_D14
FBA_D8
FBA_D12

FBA_D17
FBA_D21
FBA_D18
FBA_D20
FBA_D19
FBA_D22
FBA_D16
FBA_D23

0.1U_0402_10V7K

0.1U_0402_10V7K
CV284

1

2

2

PLACE UNDER DRAM

+1.35V_MEM_GFX +1.35V_MEM_GFX

20130610

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CV283

CV281

CV282

2

2

2

CV280

1U_0402_6.3V6K

2

10U reserve

10U_0603_6.3V6M

@

CV277

CV279

2

PLACE CLOSE DRAM

DDR3 per Memory FBVDD/Q Decouplin
FBVDD/Q Combine
Capacitor Typ

0.1uF 040

1.0uF 060
10uF 0805

d

e

Populatio
2
3

3

n

24

0

+FBA_VREF_CA0
+FBA_VREF_DQ0

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4

FBA_CMD12
FBA_CMD27
FBA_CMD26

CLKA0
CLKA0#

FBA_CMD3

FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13

FBA_WP0

FBA_RN0FBA_RN1

FBA_CMD5
FBA_ZQ1

243_0402_1%

12

RV294

UV18

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

ADDRESSControl & DQM

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC

L1

NC

J9

NC

L9

NCZQ1

96-BALL
SDRAM DDR3

H5TC4G63AFR-11C_FBGA96

A00006E800 Link done

S

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DATAPOWERGND

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

FBA_D4

F7

FBA_D3

F2

FBA_D6

F8

FBA_D0

H3

FBA_D7

H8

FBA_D2

G2

FBA_D5

H7

FBA_D25

D7

FBA_D29

C3

FBA_D26

C8

FBA_D28

C2

FBA_D27

A7

FBA_D30

A2

FBA_D24

B8

FBA_D31

A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9

H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

PLACE UNDER DRAM

0.1U_0402_10V7K

0.1U_0402_10V7K
CV290

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV289

1

2

1U_0402_6.3V6K

CV287

CV288

1

1

2

2

1U_0402_6.3V6K

CV285

CV286

1

2

20130610
10U reserve

10U_0603_6.3V6M

@

CV278

1

2

PLACE CLOSE DRAM

FBA_D1

E3

g

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.
MARX-VRAM_A Lower

MARX-VRAM_A Lower

MARX-VRAM_A Lower
LA-E082P

LA-E082P

LA-E082P

53 75Monday, December 12, 2016

53 75Monday, December 12, 2016

53 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

Memory Partition A - Lower 16 bits

3

256x16 DDR3L

2

1

FBA_D[32..63]

FBA_WP[4..7]
FBA_DQM[4..7]
FBA_RN[4..7]

D D

C C

CLKA1<52>

CLKA1#<52>

B B

FBA_D[32..63] <52>

FBA_WP[4..7] <52>
FBA_DQM[4..7] <52>
FBA_RN[4..7] <52>

RV301

1 2

162_0402_1%

80.6_0402_1%

@

12

RV290

CLKA1_C

0.01UF_0402_25V7K

@

CV310

1

2

+FBA_VREF_CA1
+FBA_VREF_DQ1 FBA_D49

FBA_CMD9<52,53>
FBA_CMD11<52,53>
FBA_CMD8<52,53>
FBA_CMD25<52,53>
FBA_CMD10<52,53>
FBA_CMD24<52,53>
FBA_CMD22<52,53>
FBA_CMD7<52,53>
FBA_CMD21<52,53>
FBA_CMD6<52,53>
FBA_CMD29<52,53>
FBA_CMD23<52,53>
FBA_CMD28<52,53>
FBA_CMD20<52,53>
FBA_CMD4<52,53>
FBA_CMD14<52,53>

FBA_CMD12<52,53>
FBA_CMD27<52,53>
FBA_CMD26<52,53>

80.6_0402_1%

@

12

RV291

FBA_CMD5<52,53>

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4

FBA_CMD14 FBA_CMD14

FBA_CMD12
FBA_CMD27
FBA_CMD26

CLKA1

12

CLKA1#

FBA_CMD19<52>

FBA_CMD18<52>
FBA_CMD16<52>
FBA_CMD30<52,53>
FBA_CMD15<52,53>
FBA_CMD13<52,53>

RV292

243_0402_1%

FBA_WP5

FBA_DQM6
FBA_DQM5

FBA_RN6
FBA_RN5

FBA_CMD5
FBA_ZQ2

FBA_CMD19

FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13

UV19

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2
R3
R7

N7

M7

M2
N8
M3

C7

D3

G3

ADDRESSControl & DQM

A7

T8

A8
A9

L7

A10/AP
A11
A12/BC

T3

A13

T7

A14
NC

BA0
BA1
BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL
DQSU

E7

DML
DMU

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC

L1

NC

J9

NC

L9

NCZQ1

96-BALL
SDRAM DDR3

H5TC4G63AFR-11C_FBGA96

SA00006E800 Link done

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

DATAPOWERGND

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ
VDDQ
VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

FBA_D52
FBA_D53

FBA_D50
FBA_D54
FBA_D48
FBA_D55
FBA_D51

FBA_D44
FBA_D40
FBA_D46
FBA_D41
FBA_D45
FBA_D43
FBA_D47
FBA_D42

+1.35V_MEM_GFX

20130610

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

CV300

CV299

1

1

1

2

2

2

1U_0402_6.3V6K

CV298

CV297

1

1

2

2

PLACE UNDER DRAM PLA

10U reserve

10U_0603_6.3V6M

1U_0402_6.3V6K

@

CV293

CV295

CV296

1

1

2

2

PLACE CLOSE DRAM

+FBA_VREF_CA1
+FBA_VREF_DQ1

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4

FBA_CMD12
FBA_CMD27
FBA_CMD26

CLKA1
CLKA1#

FBA_CMD19

FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13

FBA_RN4
FBA_RN7

FBA_CMD5
FBA_ZQ3

243_0402_1%

12

RV293

UV20

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

ADDRESSControl & DQM

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC

L1

NC

J9

NC

L9

NCZQ1

96-BALL
SDRAM DDR3

H5TC4G63AFR-11C_FBGA96

00006E800 Link done

SA

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DATAPOWERGND

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

FBA_D37

F7

FBA_D34

F2

FBA_D39

F8

FBA_D33

H3

FBA_D38

H8

FBA_D32

G2

FBA_D36

H7

FBA_D56

D7

FBA_D60

C3

FBA_D58

C8

FBA_D61

C2

FBA_D57

A7

FBA_D63

A2

FBA_D59

B8

FBA_D62

A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9

H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

CV306

CV305

1

1

1

2

2

2

CE UNDER DRAM

1

CV304

2

+1.35V_MEM_GFX

1U_0402_6.3V6K

1U_0402_6.3V6K

CV302

CV303

1

1

2

2

20130610
10U reserve

PLACE CLOSE DRAM

10U_0603_6.3V6M

1U_0402_6.3V6K

@

CV294

CV301

1

2

FBA_D35

E3

0.01UF_0402_25V7K
CV276

1

2

20130606
reduce 1 ???

+FBA_VREF_CA1

1.33K_0402_1%

12

RV295

+FBA_VREF_DQ1

1.33K_0402_1%

0.01UF_0402_25V7K

12

RV296

CV275

1

2

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+1.35V_MEM_GFX +1.35V_MEM_GFX

1.33K_0402_1%

12

RV297

A A

1.33K_0402_1%

12

RV298

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

e Document Number Re v

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Compal Electronics, Inc.
MARX-VRAM_A Lower

MARX-VRAM_A Lower

MARX-VRAM_A Lower
LA-E082P

LA-E082P

LA-E082P

54 75Monday, December 12, 2016

54 75Monday, December 12, 2016

54 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

Timing Diagram for S5 to S0 mode

D D

6

C C

VCCST_PWRGD

12

H_CPUPWR GD

15

PCH_PLTRS T#

17

0.6V_DDR_VTT_ON

12

+1.0V_PRIM_CORE

+1.8V_PRIM

6

6

+1.0V_PRIM SYX198

CPU

VCCST_PWRGD

PROCPWRGD

PLTRST#

DDR_VTT_CNT L

+PWR_SRC

TLV62130

+3.3V_ALW

TLV62130

+PWR_SRC

VCCIO

VCCGT

VDDQ

VDDQC

VCCPLL_OC

VCCST

VC

CSTG

VCCPL L

VCCSA

SIO_SLP_SU S#

+VCC_CORE

VCC

+1.0VS_VCCIO

+VCC_GT

+1.2V_MEM

+1.0V_VCCST

+VCC_SA

4

+1.0V_PRIM

11

TPS22961

SIO_SLP_S4 #

+LCDVDD

11

+5V_TSP

3

+3.3V_ALW

+3.3V_SPI

LP2301ALT1G

LP2301ALT1G+3.3V_CAM

3

+1.0V_MPHYGT

+3.3V_ALW_DSW

+3.3V_ALW_PCH

5

6

+1.0V_PRIM_CORE

6

17

4

+3.3V_ALW

AP2821K

+3.3V_ALW

EM5209VF+3.3V_LAN

+5V_RUN

+3.3V_RUN

+1.0V_PRIM

+1.8V_PRIM

+RTC_CEL L

PCH_PLTRS T#

PCH_DPWR OK

ENVDD_PCH

SIO_SLP_LAN#

3.3V_TS_EN

3.3V_CAM_EN#

VCCPRIM_1P0
VCCPRIM_CORE
DCPDSW _1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~ 6
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB

VCCDSW_3P 3

VCCHDA
VCCSPI
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM

VCCPGPPG
VCCATS

VCCRTC

VCCPRIM_CORE

PLTRST#

DSW_PWROK

EDP_VDDEN

LP_LAN#

S

GPP_B21

GPD7

PCH

PWRBTN#

RSMRST#

SLP_SUS #

SLP_S5 #

SLP_S4 #

SLP_S3 #

SLP_LAN#

SLP_WLAN#/GPD 9

SYS_PWROK

PCH_PWRO K

VCCST_PWRGD

PROCPWRGD

SLP_A#

2

SIO_PWRBTN#

PCH_RSMRST #

SIO_SLP_SU S#

SIO_SLP_S5 #

SIO_SLP_S4 #

SIO_SLP_S3 #

SIO_SLP_A#

SIO_SLP_LAN#

SIO_SLP_WLAN#

RESET_OUT#

PCH_PWRO K

VCCST_PWRGD

H_CPUPWR GD

16

15

10

11

14
12

1

8

7

5

9

+5V_ALW

+5V_RUN

+3.3V_RUN

+1.0VS_VCCIO

13

SM BUS

+5V_HDD

+3.3V_HDD

+VCC_CORE

+VCC_SA

+VCC_GT

10

+PWR_SRC

ISL95857

PCH_PWRO K

14

BATTERY

7
4

16

5

9

11

PCH_RSMRST #

PCH_DPWR OK

RESET_OUT#

SIO_SLP_SU S#

SIO_SLP_S4 #

SIO_SLP_S5 #

SIO_SLP_LAN#

SIO_SLP_S3 #

SIO_SLP_A#

12

IMVP_VR_ON

5

SIO_SLP_SU S#

@PCH_ALW_ON

EN_INVPWR

10

SIO_SLP_S4 #

0.6V_DDR_VTT_ON

+PWR_SRC

EM5209VF

.3V_ALW

+3

M5209VF

E

B B

@SIO_SLP_WLAN #

+3.3V_ALW

.3V_WLAN EM5209VF

+3

11

AUX_EN_WOWL

+PWR_SRC

TLV62130

MCP 23008

A A

SYX198EC 5105

SYX198

+3.3V_ALW

EM5209VF

+PWR_SRC

AO6405

+PWR_SRC

RT8207MZ

+5V_ALW2

V_ALW

+5

+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW

+3.3V_ALW_PCH

+BL_PWR_SRC

+1.2V_MEM
+0.6V_DDR_VTT

12

1BAT

2AC

5

Pop option

+3.3V_SPI

18

VDDQ

VTT

DDR

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date : Sheet of

Date : Sheet of

Date : Sheet of

LA-E082P

LA-E082P

LA-E082P

Power Sequence

Power Sequence

Power Sequence

1

55 75Monday, Dec ember 12, 201 6

55 75Monday, Dec ember 12, 201 6

55 75Monday, Dec ember 12, 201 6

1.0

1.0

1.0

5

D D

1

C C

4

3

2

1

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Stack-up

Stack-up

Stack-up

LA-E082P

LA-E082P

LA-E082P

56 75Monday, December 12, 2016

56 75Monday, December 12, 2016

56 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

+COINCELL

COIN RTC Battery

12

PR2

PD3

PQ1B

3

PBAT_PRES# <34,66>PBAT_CHARGER_SMBCLK <34,66>

12

PR17
100K_0402_5%

34

+Z4012

2

1

PS_ID <34>

5

1K_0402_5%

@

0_0402_5%

1

2

PR25

+COINCELL

+RTC_CELL

PC3
1U_0603_25V6K

+3.3V_VDD_DCIN

12

12

+3.3V_RTC_LDO

D D

2

100K_0402_1%

15K_0402_1%

12

PR14

1

PD2

EMC@

TVNST52302AB0_SOT523-3

3

PBAT_CHARGER_SMBDAT <34,66>

PR6

1 2

PR8

1 2

+DC_IN_SS

12

PC8

10U_0805_25V6K

100K_0402_5%

PBATT+_C

@
1 2

0_0402_5%

1 3

D

2

B

PR3

2

C

E

3 1

PL1

EMC@

FBMJ4516HS720NT_2P

1 2

PL2

EMC@

FBMJ4516HS720NT_2P

1 2

+PBATT

+3.3V_ALW

12

PR1
100K_0402_5%

BAS40CW SOT-323

+3.3V_ALW

PR4

S

D

1 3

DMN65D8LDW-7_SOT363-6

2.2K_0402_5%

1 2

+SDC_IN

12

PR10
300K_0402_1%

G

2

12

PR15
100K_0402_5%

61

2

PQ1A

VBUS2_ECOK <35,67>

PR19

@

0_0402_5%

+3.3V_VDD_DCIN

12

DMN65D8LDW-7_SOT363-6

2

PR5

33_0402_5%

1 2

S

PQ2
FDV301N-G_SOT23-3

G

PQ3
MMST3904-7-F_SOT323~D

PD5

5A_100V 15UA_0.88V_TO227-3

2
3

2

PQ4
AON7409_DFN8-5

4

12

PR16

49.9K_0402_1%

13

D

PQ7

S

L2N7002WT1G_SC70-3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

1
2
35

1 2

2

G

PR11 499K_0402_1%

PR20

@

0_0402_5%

+5V_ALW

12

PC4 0.022U_0603_50V7K

12

PR7
10K_0402_1%

12

12

PR24

100K_0402_5%

+SDC_IN

PQ5 AO3409_SOT23

1

PD1

EMC@

TVNST52302AB0_SOT523-3

2

Primary Battery Connector

PBATT1

@

1

1

2

2

3

3

4

4

5

5

12

PC1

EMC@

2200P_0402_50V7K

C C

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

DEREN_40-42251-01001RHF

PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C

GND

NB_PSID PS_ID

2

3

1

PRP1

100_0804_8P4R_5%

EMC@

BLM15AG102SN1D_2P

PD4

EMC@

PESD5V0U2BT_SOT23-3

+DC_IN

PL4

EMC@

FBMJ4516HS720NT_2P

1 2

B B

PR28

+3.3V_ALW

PC5

EMC@

1000P_0603_50V7K

L2N7002WT1G_SC70-3

S

12

PR29

@

100K_0402_5%

12

ACAV_IN_NB<34,66,67>

PQ8

D

13

G

2

0_0402_5%

1 2

12

PC7

0.1U_0603_25V7K

@EMC@

+3.3V_VDD_DCIN

12

PR13

4.7K_0805_5%

@

12

PR27

100K_0402_5%

PC9

0.1U_0402_10V7K
PR21

@

0_0402_5%

1 2
1 2

PR22

@

0_0402_5%

12

1

B

2

A

PJPDC1

@

7

GND

6

GND

-DCIN_JACK-DCIN_JACK

5

5

4

4

+DCIN_JACK

3

3

2

2

1

1

CVILU_CI0805M1HRC-NH

PR26

@

0_0402_5%

1 2

DCIN2_EN<35>

A A

5

12

PC6

1 2

0.022U_0603_50V7K

+3.3V_VDD_DCIN

PU1

5

MC74VHC1G08DFT2G_SC70-5

P

4

O

G

3

4

3

18
27
36
45

PL3

12

DC_IN+ Source

S1 S

PQ9

AON7409_DFN8-5

1
2
3 5

4

PR12

499K_0402_1%

12

49.9K_0402_1%

13

D

PR23

@

2

12

G

0_0402_5%

S

PR18

PQ6

L2N7002WT1G_SC70-3

12

PC2

JRTC1

@

EMC@

2200P_0402_50V7K

1

3

1

G

4

22G

ACES_50271-0020N-001

+DC_IN

PC10

2.2U_0402_10V6M

AC_DISC# <34,67>

PU2

3

AP2204RA-3.3TRG1_SOT89-3

VOUT

GND

11/11

2

VIN

1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

+DCIN

+DCIN

+DCIN

Document Number Re v

Document Number Re v

Document Number Re v

LA-E082P

LA-E082P

LA-E082P

1

57 71Monday, December 12, 2016

57 71Monday, December 12, 2016

57 71Monday, December 12, 2016

1U_0603_50V6K

1

PC11

2

0.1

0.1

0.1

A

1 1

+PWR_SRC

PJP100

@

21

PAD-OPEN 1x2m~D

PC100

RF@

100P_0402_50V8J

2 2

+3.3V_ALW

12

PC103

RF@

100P_0402_50V8J

PR107
100K_0402_5%

1 2

PGOOD_3V

12

3V_VIN

PC105

12

PC104

10U_0805_25V6K

10U_0805_25V6K

B

BST_3V

2

5

LX_3V

3V5V_EN

PU100

6

LX

7

GND

8

SY8288BRAC_QFN20_3X3

GND

9

PG

10

NC

11

ENLDO_3V5V

12

EN112EN2

IN3IN4IN

FF13OUT14NC

1

IN

BS

20

LX

19

LX

18

GND

17

LDO

16

NC

21

GND

15

PC113
1000P_0402_50V7K

1 2

@

1 2

0_0603_5%

1 2

@

1 2

@

3.3V LDO 150mA~300mA

12

PC111

4.7U_0603_6.3V6K

PR108

1K_0402_5%

3V_FB_R3V_FB

1 2

PR100

PR104
0_0402_5%

PR105
0_0402_5%

C

BST_3V_R

LX_3V

+3.3V_RTC_LDO

PC102

1 2

0.1U_0603_25V7K

+3.3V_ALW2

12

PR106

RF@

4.7_1206_5%

3V_SN

12

PC112

RF@

680P_0603_50V7K

PGOOD_3V
PGOOD_5V

ENLDO_3V5V

PL100

1.5UH_9A_20%_7X7X3_M

1 2

D

PR119

@

0_0402_5%

1 2
1 2

PR120

@

0_0402_5%

12

PR103

499K_0402_1%

12

PR102
499K_0402_1%

1 2

12

PC106

22UF_0805_6.3V6M

12

PC108

PC107

22UF_0805_6.3V6M

ALW_PWRGD_3V_5V <45>

12

22UF_0805_6.3V6M

Vout is 3.234V~3.366V

+3.3V_ALWP +3.3V_ALW

+PWR_SRC

12

PC109

PC129

22UF_0805_6.3V6M

22UF_0805_6.3V6M

12

+3.3V_ALWP

PC110

3VALWP
TDC

6.8 A

Peak Current 9.7 A

22UF_0805_6.3V6M

OCP Current 9 A f i x by I C

PJP102

@

2

112

JUMP_43X118

E

+PWR_SRC

PJP101

@

21

PAD-OPEN 1x2m~D

3 3

PD100

@

RB520SM-30T2R_EMD2-2

2 1

PR114

@

ALWON<34>

4 4

1 2

0_0402_5%

12

5V_VIN

PC117

10U_0805_25V6K

12

PC118

10U_0805_25V6K

PR113
100K_0402_5%

1 2

12

PGOOD_5V

12

PC115

RF@

100P_0402_50V8J

PR116

1M_0402_1%

12

PC116

RF@

100P_0402_50V8J

+3.3V_ALW

3V5V_EN

12

PC128

4.7U_0402_6.3V6M

EN1 and EN2 dont't floating

LX_5V

5

PU102

6

LX

7

GND

8

SY8288CRAC_QFN20_3X3

GND

9

PG

10

NC

11

3V5V_EN

ENLDO_3V5V

EN112EN2

2

1

IN

IN3IN4IN

BS

FF13OUT14LDO

15

12

PC127
1000P_0402_50V7K

LX

LX
GND
VCC

NC

GND

+5V_ALW2

5V LDO 150mA~300mA

PC126

4.7U_0603_6.3V6K

1 2

BST_5V

20
19
18
17
16
21

@

1 2

0_0603_5%

PC119

1 2

4.7U_0603_6.3V6K

5V_FB_R5V_FB

PR111

1K_0402_5%

1 2

LX_5V

PR117

BST_5V_R

PC114

1 2

0.1U_0603_25V7K

PL101

1.5UH_9A_20%_7X7X3_M

1 2

12

PR112

@EMC@

4.7_1206_5%

5V_SN

12

PC125

@EMC@

680P_0603_50V7K

12

12

12

PC121

PC120

22UF_0805_6.3V6M

22UF_0805_6.3V6M

5VALWP
TDC 6.5 A
Peak Current 9.3 A
OCP Current 9 A f i x by I C

12

12

PC123

PC122

22UF_0805_6.3V6M

22UF_0805_6.3V6M

PJP103

@

112

JUMP_43X118

2

+5V_ALW+5V_ALWP

+5V_ALWP

12

PC124

PC130

22UF_0805_6.3V6M

22UF_0805_6.3V6M

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

LA-E082P

LA-E082P

LA-E082P

58 71Monday, December 12, 2016

58 71Monday, December 12, 2016

58 71Monday, December 12, 2016

E

0.1

0.1

0.1

5

D D

4

3

2

1

+PWR_SRC

C C

The current limit is
se

t to 8A, 12A or 16A
when this pin is pull
low, floating or pull
high
+1.2V_DDR OCP set 8A

B B

PJP202

@

PAD-OPEN 1x2m~D

21

12

PC200

10U_0805_25V6K

+3.3V_ALW

1 2

1 2

0.6V_DDR_VTT_ON<20>

12

PC201

PR205

@

0_0402_5%

PR207

@

0_0402_5%

+1.2V_DDR_B+

12

12

PC203

PC202

10U_0805_25V6K

0.1U_0402_25V6
2200P_0402_50V7K

@EMC@

@EMC@

SIO_SLP_S4#<11,17,34,62>

PR208

@

0_0402_5%

PR210

@

0_0402_5%

+3.3V_ALW

1U_0402_6.3V6K

12

12

PR209

12

PC206

12

1M_0402_5%

+1.2V_DDR_VCC

2.2U_0402_6.3V6M

12

PC207

EN_1.2V

12

PC221

@

0.1U_0402_10V7K

1M_0402_5%

12

PR212

ILMT_DDR

EN_0.6V

12

PU200

10

IN

13

BYP

14

VCC

4

VTTGND

9

PGND

15

SGND

17

ILMT

1

S5

2

S3

SY8210AQVC_QFN19_4X3

0.1U_0402_10V7K

@

PC222

19

OT

18

PG

+1.2V_DDR_BST

12

BS

+1.2V_DDR_LX

11

LX

+1.2V_DDR_FB

16

FB

+1.2V_DDRP

8

VDDQSNS

7

VLDOIN

6

VTT

5

VTTSNS
VTTREF

Mode S3 S5 VOUT VTT
Normal H H on on
Stadby L H on off
Shutdown L L off off

+1.2V_DDR_VTTREF

3

PR203

@

0_0603_5%

1 2

12

PC205

0.1U_0603_16V7K

+1.2V_DDR_BST_R

1 2

22U_0603_6.3V6M

PC218

1U_0402_10V6K

12

PC209

22U_0603_6.3V6M

1 2

+0.6VSP

PC219

PR202

RF@

4.7_1206_5%

1 2

PL201

1 2

1UH_11A_20%_7X7X3_M

+1.2V_DDR_SNB

330P_0402_50V7K

12

PJP200

@

JUMP_43X118

112

+1.2V_DDR
TDC 6.2A
Peak Current 8.9A
OCP Current 10.6A

PC208

R1

RF@

12

12

PC204

680P_0603_50V7K

1 2

102K_0402_1%

PR204

12

100K_0402_1%

PR206

2

+1.2V_DDRP

22U_0603_6.3V6M

22U_0603_6.3V6M

PC211

PC210

12

22U_0603_6.3V6M

22U_0603_6.3V6M

PC213

PC212

12

12

10U_0603_6.3V6M

PC223

12

@

JUMP_43X39

112

12

PJP201

10U_0603_6.3V6M

2200P_0402_50V7K

PC214

100P_0402_50V8J

PC217

PC216

12

12

@EMC@

@EMC@

+0.6V_DDR_VTT+0.6VSP+1.2V_MEM+1.2V_DDRP

2

0.6Volt +/- 5%
C 1.05A

TD
Peak Current 1.5A
OCP Current 2A (fix)

Note: S3 - sleep ; S5 - power off

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

e Document Number Re v

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+1.2V_MEN/+0.6V_DDR_VTT

+1.2V_MEN/+0.6V_DDR_VTT

+1.2V_MEN/+0.6V_DDR_VTT

LA-E082P

LA-E082P

LA-E082P

59 71Monday, December 12, 2016

59 71Monday, December 12, 2016

59 71Monday, December 12, 2016

1

0.1

0.1

0.1

5

4

3

2

1

D D

+1VALW P_EN

+PWR_SRC

C C

+3.3V_ALW

12

PR307

+1VALW P_ILMT

12

PR310

@

0_0402_5%

B B

PJP301

@

PAD-OPEN 1x2m~D

21

12

12

PC303

PC301

100P_0402_50V8J

RF@

RF@

+1.0V_PRIM
TD

C 5.4A
Peak Current 10.5 A
OCP 12.6A
OCP Current 9 A Fix by IC

Choke DCR 11.0mohm , 12.0mohm

12

PC305

100P_0402_50V8J

10U_0603_25V6M

TYP MAX

+1VALW P_B+

12

PC306

10U_0603_25V6M

+1VALW P_ILMT

PU301

8

IN

EN

GND

ILMT
PG

BS
LX

FB
BYP
LDO

9

3
2

SYX196DQNC_QFN10_3X3

1

+1VALW P_BST

6
10

4
7
5

+1VALWP_LDO

12

0.1U_0603_25V7K

+1VALW P_LX

+1VALW P_FB

12

PC313

4.7U_0603_6.3V6K

PC304

1 2

PC312

4.7U_0603_6.3V6K

+1VALW P_BST_C

+3.3V_ALW

12

1M_0402_1%
PR302

PR304

@

0_0603_5%

1 2

PR312

@

0_0402_5%

1 2

PR303

RF@

4.7_1206_5%

1 2

0.68UH_7.9A_20%_5X5X3_M

+1VALW P_SNB

PL301

1 2

PR306

SIO_SLP_SUS# <11,17,34,47,61,62>

PC302

RF@

680P_0603_50V7K

1 2

12

12

12

21.5K_0402_1%
PR308

1K_0402_5%

12

PR311

31.6K_0402_1%

+1VALWP

12

PC307

330P_0402_50V7K

PJP302

@

2

112

JUMP_43X118

+1.0V_PRIM

+1VALWP

12

12

PC308

PC309

22U_0603_6.3V6M

22U_0603_6.3V6M

12

PC310

PC311

22U_0603_6.3V6M

22U_0603_6.3V6M

The current limit is set to 6A, 9A or 12A when this pin

pull low, floating or pull high

is

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+1VALWP

+1VALWP

+1VALWP

LA-E082P

LA-E082P

LA-E082P

60 71Monday, December 12, 2016

60 71Monday, December 12, 2016

60 71Monday, December 12, 2016

1

0.1

0.1

0.1

5

4

3

2

1

+3.3V_ALW

LPM LOGIC

PS62134 C 1 0

EN_1VS_VCCIO

13

PU401

EN

PVIN

PVIN

TPS62134CRGT_QFN16_3X3

AVIN

VID0

VID1

8

12

PR427

0_0402_5%

@

12

LPM_1VS_VCCIOLPM_1.0V_PRIM_COREP

14

@

0_0402_5%

LPM

7

SS_1VS_VCCIO

12

PR404

PJP401

@

JUMP_43X79

2

+1VS_VCCIOP

12

PR421

0_0402_5%

112

PR422

@

1 2

0_0402_5%

12

12

PC407

PC406

22U_0603_6.3V6M

VCCIO_SENSE <17>

VSSIO_SENSE <17>

12

PC422

22U_0603_6.3V6M

22U_0603_6.3V6M

+1VS_VCCIOP +1.0VS_VCCIO

15

17

TP

PGND16PGND

1

VOS

2

SW

3

SW

4

PG

FBS5AGND6SS

PC410

FB_1VS_VCCIO

470P_0402_50V7K

LX_1VS_VCCIO

+1VS_VCCIOP

PL402

1UH_1277AS-H-1R0N-P2_3.3A_30%

1 2

12

RF@

PR405

4.7_0603_5%

SNUB_1VS_VCCIO

12

RF@

PC401
680P_0402_50V7K

@

1 2

PR412

0_0402_5%

T

+1VS_VCCIOP

PR425

@

0_0402_5%

PR402

PR403

1M_0402_1%

1 2

12

VIN_1VS_VCCIO

VID0_VCCIO

VID1_VCCIO

12

PC402

@

0.1U_0402_25V6

12

11

10

9

SIO_SLP_S0#<11,17,36,61>

@

0_0402_5%

RUN_ON<17,34,35,47>

D D

Vin=3~17V

+5V_ALW

+3.3V_ALW

PR413

PR415

12

PR414

10K_0402_1%

12

PR416

@

10K_0402_1%

VID0_VCCIO
VID1_VCCIO

12

@

10K_0402_1%

12

C C

10K_0402_1%

PJP403

@
1 2

PAD-OPEN1x1m

12

PC408

0.1U_0402_25V6

@EMC@

12

PC409

100P_0402_50V8J

RF@

1 2

12

12

PC403

PC404

10U_0603_10V6M

10U_0603_10V6M

VID1 LOGIC

0

1

1

1

+1.0VS_VCCIO
TDC 2.2 A
Peak Current 3.1 A
OCP Current 4.2 A Fix by IC

Choke DCR 48.0mohm

VID0 LOGIC

X

0

1

1

TYP MAX

"R" for SILERGY

OUTPUT VOLTAGE

X

0

1

0

1 1 .05

0(LPM)

0.80

0.95

1.00

+3.3V_ALW

PR426

@

0_0402_5%

SIO_SLP_S0#<11,17,36,61>

1

12

PR410

@

0_0402_5%

PJP402

@

Rup

JUMP_43X79

112

2

+1.0V_PRIM_COREP

12

PC424

12

12

PC416

PC415

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

+1.0V_PRIM_CORE
TDC 1.8 A
Peak Current 2.6 A
OCP Current 4.2 A Fix by IC

Choke DCR 48.0mohm

TYP MAX

LPM LOGIC

TPS62134 D 1 0

VID1 LOGIC

0

1

1

1

VID0 LOGIC

X

0

1

1

OUTPUT VOLTAGE

X

0

1

0

1 1.00

0.7(LPM)

0

0.90

0.95

.85

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

+1VS_VCCIOP/+1.0V_PRIM_COREP

+1VS_VCCIOP/+1.0V_PRIM_COREP

+1VS_VCCIOP/+1.0V_PRIM_COREP

Document Number Re v

Document Number Re v

Document Number Re v

LA-E082P

LA-E082P

LA-E082P

1

61 71Monday, December 12, 2016

61 71Monday, December 12, 2016

61 71Monday, December 12, 2016

0.1

0.1

0.1

PR406

@

0_0402_5%

SIO_SLP_SUS#<11,17,34,47,60,62>

VID0_PRIM_CORE
VID1_PRIM_CORE

Vin=3~17V

+5V_ALW

PJP404

@
1 2

PAD-OPEN1x1m

12

PC417

0.1U_0402_25V6

@EMC@

CORE_VID0<18>

CORE_VID1<18>

12

PC418

2200P_0402_50V7K

@EMC@

B B

+3.3V_ALW

PR417

PR419

12

PR418

10K_0402_1%

12

PR420

@

10K_0402_1%

5

12

10K_0402_1%

12

@

10K_0402_1%

A A

1 2

PR407

1M_0402_1%

VIN_1V_PRIM

12

12

PC412

PC413

10U_0603_10V6M

10U_0603_10V6M

PR408

@

0_0402_5%

1 2

PR411

@

0_0402_5%

1 2

4

12

@

VID0_PRIM_CORE

"

R" for SILERGY

12

PC411

0.1U_0402_25V6

12

11

10

9

EN_1.0V_PRIM_COREP

13

PU402

EN

PVIN

PVIN

TPS62134DRGT_QFN16_3X3

AVIN

VID0

VID1

8

VID1_PRIM_CORE

14

15

17

LPM

PGND16PGND

7

SS_1V_PRIM

12

12

PR428

PC420

@

1M_0402_1%

470P_0402_50V7K

+1.0V_PRIM_COREP +1.0V_PRIM_CORE

TP

1

VOS

SW

SW

PG

FBS5AGND6SS

FB_PRIM_CORE

+1.0V_PRIM_COREP

PL404

1UH_1277AS-H-1R0N-P2_3.3A_30%

2

3

4

LX_1V_PRIM

3

1 2

12

RF@

PR409

4.7_0603_5%

SNUB_1V_PRIM

12

RF@

PC419
680P_0402_50V7K

1 2

PR423

@

0_0402_5%

12

PR424

@

100K_0402_1%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

D D

SIO_SLP_SUS#<11,17,34,47,60,61>

C C

4

PC502

22U_0603_6.3V6M

1 2

PJP501

@

PR504
0_0402_5%

1M_0402_1%

1 2

PAD-OPEN1x1m

PR505

PR517

100K_0402_5%

12

+3.3V_ALW

+3.3V_ALW

1.8V_PRIM_PWRGD<34>

1 2

@

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage

12

EN_1.8VALW

12

PC505

@

0.1U_0402_16V7K

VIN_1.8VALW

PU501

4

IN

5

PG
FB6EN

RT8097ALGE_SOT23-6

3

@

PJP502

PL501

1 2

20K_0402_1%

FB_1.8VALW

10K_0402_1%

1 2

PAD-OPEN1x1m

PR501

PR506

12

Rup

12

Rdown

+1.8VALWP

Imax= 2A, Ipeak= 3A
FB=0.6V

LX_1.8VALW

3

LX

2

GND

1

1UH_1277AS-H-1R0N-P2_3.3A_30%

12

RF@

PR502

4.7_0603_5%

SNUB_1.8VALW

12

RF@

PC506
680P_0402_50V7K

+1.8V_PRIM

12

PC503

68P_0402_50V8J

2

+1.8VALWP

12

12

PC501

PC504

22U_0603_6.3V6M

22U_0603_6.3V6M

+1.8V_PRIM
TDC 0.7 A
Peak Current 1A
OCP Current 3.5A f i x by I C

1

Vout=0.6V* (1+Rup/Rdown)

B B

+2.5V_MEN
TDC 0.3A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=1.1A.
Pd=(3.3-2.5)*1.1=0.88W < 1.7W
OCP is 1.1~1.5A

@

PJP505

+3.3V_ALW

SIO_SLP_S4#<11,17,34,59>

A A

1 2

PAD-OPEN1x1m

1 2

PR513

@

0_0402_5%

1M_0402_1%

PR514

+2.5V_VIN

12

PC514

4.7U_0603_6.3V6K

12

EN_2.5V

12

@

.1U_0402_16V7K

AP7361C-FGE-7_U-DFN3030-8_3X3

9
8
7
6
5

PC513

PU503

PJP506

PAD-OPEN1x1m

12

PC516

22U_0603_6.3V6M

@

1 2

+2.5V_MEM

GND

1

OUT

IN

2

NC

NC

3

ADJ/NC

NC

4

GND

EN

PR515

21.5K_0402_1%

12

12

PR516

10.2K_0402_1%

2.5VSP

12

PC515

0.01UF_0402_25V7K

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

+1.8VALWP/+2.5VSP

+1.8VALWP/+2.5VSP

+1.8VALWP/+2.5VSP

Document Number Re v

Document Number Re v

Document Number Re v

LA-E082P

LA-E082P

LA-E082P

1

62 71Monday, December 12, 2016

62 71Monday, December 12, 2016

62 71Monday, December 12, 2016

0.1

0.1

0.1

5

4

3

2

1

+1.0V_VCCST

12

12

Local sense put on HW site

D D

H_PROCHOT#<12,34,66>

470K_0402_5%

VCC_GT_SENSE<16>

C C

VSS_GT_SENSE<16>

ISUMP_GT<64>

ISUMN_GT<64>

B B

A A

PH601

1 2
1 2

PR631

27.4K_0402_1%

2200P_0402_50V7K

@

1 2

330P_0402_50V7K

PC619

1 2

0.01UF_0402_25V7K

12

PR628

4.42K_0402_1%

12

PH602

10K_0402_5%

PC614

1 2

PC618

PC641

NTC_GT_R

PC616
68P_0402_50V8J

1 2

12

PR633

12

.1U_0402_16V7K

1 2

PC605 47P_0402_50V8J~D

PR610
10K_0402_1%

1 2

PR617

3.92K_0402_1%

1 2

12

11K_0402_1%

PC624

12

PC620

@

0.033U_0402_16V7K

VIDSCLK<15>

VIDALERT_N<15>
VIDSOUT<15>

PR678

100_0402_1%

1 2

PC617

1200P_0402_50V7K

1 2

1.91K_0402_1%

PC621

1200P_0402_50V7K

1 2

0.082U_0402_16V7K

12

PC626

0.047U_0402_25V7K

1 2

PR622

1 2

PR632

1K_0402_1%

1 2

PR613

84.5K_0402_1%

1 2

PC613
330P_0402_50V7K

1 2

PR621

316_0402_1%

PR623
2K_0402_1%

1 2

PC627

2200P_0402_50V7K

PR638

340_0402_1%

1 2

1 2

PR601

@

45.3_0402_1%

+3.3V_RUN

I_SYS<34,66>

+5V_ALW

VCCSENSE<15>

VSSSENSE<15>

12

12

PC602

PR605

PR604

75_0402_1%

100_0402_1%

0.1U_0402_25V6

1 2

PR61849.9_0402_1%

1 2

PR6250_0402_5%@

1 2

PR62610_0402_1%

VIDSOUT_B

PR6121.91K_0402_1%

VR_READY_CPU

EN_CPU

PSYS
IMON_B
NTC_B
COMP_B
FB_B
RTN_B
ISUMP_B
ISUMN_B
ISEN1_B
ISEN2_B

AGND

1 2

PR635

10K_0402_1%

316_0402_1%

VIDSCLK_B

39

38

37

40

VR_HOT#

VR_READY

VR_ENABLE

FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A

IMON_IA

12

2K_0402_1%

PR650

PC647

1 2

1200P_0402_50V7K

12

PC653

@

0.082U_0402_16V7K

VIDALERT_N_B

36

35

SCLK

ALERT#

16

NTC_IA

COMP_IA

VR_HOT#_CPU

1 2

PCH_PWROK<11>

IMVP_VR_ON<35>

470K_0402_5%

2200P_0402_50V7K

1 2

PR614 0_0402_5%@

1 2

PR616 0_0402_5%@

PC629

1 2

68P_0402_50V8J

PR648

1 2

PC651

1
2
3
4
5
6
7
8
9

10
41

PC625

330P_0402_50V7K

1 2

PR629

95.3K_0402_1%

1 2

PR639

3.6K_0402_1%

1 2

PC636

1 2

1 2

PU602

PR645

PR620

@

0_0402_5%

1 2

NTC_GT

COMP_GT

FB_GT
RTN_GT

ISUMN_R_GT IMON_VSA

FCCM_GT<64>

PH603

1 2

27.4K_0402_1%

PR647

1 2

PC639

2200P_0402_50V7K

1 2

1.5K_0402_1%

@

1 2

330P_0402_50V7K

PC654

1 2

0.01UF_0402_25V7K

12

PC603

1 2

PR608

78.7K_0402_1%

1 2

PR611

48.7K_0402_1%

VCC_CPU

VIN_CPU

PROG1_CPU

PROG2_CPU

33

34

32

VIN

SDA

VCC

PROG231PROG1

PWM_C

FCCM_C
ISUMN_C
ISUMP_C

RTN_C

FB_C

COMP_C

IMON_C
PWM_A

FCCM_A

FB_A

RTN_A18ISUMP_A19ISUMN_A

17

20

ISL95857AHRTZTS27_TQFN40_5X5~D

FB_IA

0.033U_0402_16V7K

0.047U_0402_25V7K

11K_0402_1%

PR657

4.42K_0402_1%

1 2

ISUMP_IA <64>

1U_0603_10V6K

30
29
28
27
26
25
24
23
22
21

1 2

1 2

1 2

12

PC604

0.22U_0603_25V7K

PWM_VSA
FCCM_VSA
ISUMN_R_VSA

FB_VSA
COMP_VSA

12

PC630

2200P_0402_50V7K

12

PR644

1K_0402_1%

PC642

1 2

PC646

1 2

PR656

10KB_0402_5%

1 2

PR602

@

0_0402_5%

PR603

@

0_0402_5%

PWM_IA <64>
FCCM_IA <64>

12

PR640

PH605

CPU_B+

365_0402_1%

PC645

.1U_0402_16V7K

+5V_ALW

12

ISUMN_IA <64>

1 2

BST_C_SA

PC611

0.22U_0603_16V7K

BST_SA

1 2

PWM_SA

PR606

@

0_0402_5%

1 2

PWM_VSA

12

PC628

33P_0402_50V8J

PC631

12

330P_0402_50V7K

PC643

PR651

PR619 2.2_0603_5%

1
2
3

12

PR630

12

4700P_0402_25V7K

12

130K_0402_1%

Local sense put on HW site

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFID ENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VCC_SA
TDC 4A
Peak Current 4.5A
OCP current 5.4A
Choke DCR 13 m ohm

SA_UGATE

PU614
ISL95808HRZ-TS2778_DFN8_2X2~D

UGATE
BOOT
PWM
GND4LGATE

8

PHASE

7

FCCM

6

VCC

5

TP

9

+5V_ALW

PC685

1 2

PC632
1000P_0402_50V7K

PR646

1 2

316_0402_1%

1 2

1.62K_0402_1%

PR652

2K_0402_1%

@

PC601

@

680P_0402_50V7K

2

1 2

PR636 665_0402_1%

1 2

2200P_0402_50V7K

PR649

2.49K_0402_1%

12

12

1U_0402_10V6K

PC640

SA_LGATE

12

1K_0402_1%

@

PJP603

VCCSA_B+ CPU_B+

1 2

PAD-OPEN1x1m

VCCSA_B+

12

12

PC608

PC612

10U_0805_25V6K

10U_0805_25V6K

4

3

2

1

PQ501
AON7934_DFN3X3A-8-10

D1

D1

D1

G1

SA_SW

9

S2

S2

G2

6

7

8

PR627

@EMC@

PC622

@EMC@

12

PC637

0.033U_0402_16V7K

PC644

.1U_0402_16V7K

1 2

@

12

4.7_1206_5%

SA_SNUBSA_SNUB

12

ISUMP_VSA

680P_0603_50V7K

12

PC650

1 2

0.082U_0402_16V7K

12

PR679
0_0402_5%

FCCM_VSA

1 2

PR641

D110D2/S1

S2

5

@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number R ev

Size Document Number R ev

Size Document Number R ev

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

VCCSA_ISL95857

VCCSA_ISL95857

VCCSA_ISL95857

LA-E082P

LA-E082P

LA-E082P

PL614

0.47UH_MMD05CZR47M_12A_20%

12

12

PR624

3.65K_0603_1%

ISUMN_VSA

PR642

1 2

3300P_0402_25V7K

PC649

0.01UF_0402_25V7K

1 2

@

PC652

330P_0402_50V7K

1 2

1

PR643

11K_0402_1%

63 71Monday, December 12, 2016

63 71Monday, December 12, 2016

63 71Monday, December 12, 2016

PC633

+VCC_SA

12

2.61K_0402_1%

12

PH604

10KB_0402_5%

ISUMN_VSA

VSA_SEN- <17>

VSA_SEN+ <17>

0.1

0.1

0.1

5

4

3

2

1

D D

CPU_B+

12

12

PC657

PR662

5.11K_0402_1%

10U_0805_25V6K

2.2_0603_5%

12

12

PC663

PC658

10U_0805_25V6K

PC655

0.22U_0603_16V7K

BST_C_IA

1 2

BST_R_IA

1 2

PR660

12

PC680
1000P_0402_50V7K

10U_0805_25V6K

BST_IA

12

PC656

10U_0805_25V6K

PWM_IA<63>

C C

B B

12

PC686

10P_0402_50V8K

12

12

PC606

PC660

PC659

2200P_0402_50V7K

0.1U_0402_25V6K~D

@EMC@

@EMC@

PU610

9

PGND2

8

PWM

7

VSW

BOOT

PGND1

6

VDD

BOOT_R

5

SKIP#

VIN

CSD97396Q4M_VSON8_3P5X4P5

PR659

@

0_0402_5%

<63>

@

PJP601

1 2

PAD-OPEN 4x4m

@EMC@

9A Z80 10M 1812_2P

1 2

1

+

2

100U_D_20VM_R55M

4
3
2
1

FCCM_R_IA

12

@

FCCM_IA

+PWR_SRC

PL602

IA_SW

12

PC661

1U_0402_10V6K

12

PR681

5.11K_0402_1%

VCC_core
TDC 21A
Peak Current 32A
OCP current 38.4A
Choke DCR 0.9 +-7%m ohm

PL610

0.15UH_MMD06CZER15MG_37A_20%

4
3

12

12

PR663

@EMC@

+5V_ALW

PR661

3.65K_0603_1%

4.7_1206_5%

ISUMP_IA

IA_SNUB

12

PC662

680P_0603_50V7K

@EMC@

VCC_GT
TDC 18A
Peak Current 31A
OCP current 37.2A

1
2

<63>

ISUMN_IA

+VCC_CORE

<63>

GPU_B+

12

12

12

12

PC665

PC672

10U_0805_25V6K

10P_0402_50V8K

PC673

10U_0805_25V6K

0.22U_0603_16V7K

2.2_0603_5%

12

PR680

5.11K_0402_1%

10U_0805_25V6K

PC671

1 2

BST_C_GT

1 2

PR672

12

PC679
1000P_0402_50V7K

9
8

BST_GT

7

BST_R_GT

6
5

CSD97396Q4M_VSON8_3P5X4P5

PC664

10U_0805_25V6K

PWM1_GT<63>

12

PC688

Choke DCR 0.9 +-7%m ohm

PAD-OPEN 1x2m~D

PU612

PGND2
PWM
BOOT

BOOT_R
VIN

VSW

PGND1

VDD

SKIP#

@

0_0402_5%

<63>

PR671

GT_SW1

4
3
2
1

FCCM_R_GT

12

12

PC677

1U_0402_10V6K

12

FCCM_GT

PR682

@

5.11K_0402_1%

@

PJP602

+5V_ALW

21

CPU_B+GPU_B+

PL612

0.15UH_MMD06CZER15MG_37A_20%

1

4

12

PR676

4.7_1206_5%

@EMC@

GT_SNUB1

12

PC678

680P_0603_50V7K

@EMC@

3

GT1P

PR674

3.65K_0603_1%

1 2

ISUMP_GT

<63>

2

+VCC_GT

<63>

ISUMN_GT

A A

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFID ENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

VCC_CORE/GT_ISL95857

VCC_CORE/GT_ISL95857

VCC_CORE/GT_ISL95857

LA-E082P

LA-E082P

LA-E082P

1

0.1

0.1

64 71Monday, December 12, 2016

64 71Monday, December 12, 2016

64 71Monday, December 12, 2016

0.1

A

B

C

D

E

VCC_CORE Place on CPU
22U_0603 * 33 pcs +1U_0201*35 pcs
+330u_D2*2 pcs

VCC_GT Place on CPU (U22)
22U_0603 * 26 pcs +1U_0201*12 pcs
+330u_D2*2 pcs

+VCC_CORE +VCC_GT

1 1

2 2

12

12

12

12

12

PC1076

22U_0603_6.3V6M

12

12

PC1083

1U_0201_6.3V6M

12

PC1099

1U_0201_6.3V6M

12

PC1077

PC1078

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1081

PC1080

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1030

PC1031

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1095

PC1094

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1079

22U_0603_6.3V6M

12

PC1082

22U_0603_6.3V6M

12

PC1032

1U_0201_6.3V6M

12

PC1096

1U_0201_6.3V6M

12

PC1002

PC1001

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1067

PC1072

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1034

PC1033

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1093

PC1090

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1004

PC1003

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1069

PC1074

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1035

PC1036

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1097

PC1091

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1005

22U_0603_6.3V6M

12

PC1070

22U_0603_6.3V6M

12

PC1037

1U_0201_6.3V6M

12

PC1092

1U_0201_6.3V6M

12

12

PC1007

PC1006

22U_0603_6.3V6M

PC1061

22U_0603_6.3V6M

PC1038

1U_0201_6.3V6M

PC1098

1U_0201_6.3V6M

PC1008

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

12

12

12

PC1066

PC1071

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1084

PC1039

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1050

PC1051

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1009

22U_0603_6.3V6M

12

PC1073

22U_0603_6.3V6M

12

PC1086

1U_0201_6.3V6M

12

PC1052

1U_0201_6.3V6M

12

12

PC1011

PC1010

22U_0603_6.3V6M

PC1068

22U_0603_6.3V6M

PC1085

1U_0201_6.3V6M

PC1053

1U_0201_6.3V6M

PC1012

PC1013

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

12

PC1075

PC1064

PC1065

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

12

12

PC1087

PC1088

1U_0201_6.3V6M

PC1054

1U_0201_6.3V6M

PC1089

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

12

PC1125

PC1164

PC1126

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

12

12

1

+

2

12

12

PC1015

PC1014

22U_0603_6.3V6M

PC1133

22U_0603_6.3V6M

PC1040

1U_0201_6.3V6M

330U_D2_2.5VM_R9M

PC1128

PC1016

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

12

1

+

2

12

PC1129

PC1137

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1042

PC1041

1U_0201_6.3V6M

1U_0201_6.3V6M

330U_D2_2.5VM_R9M

PC1063

12

12

PC1181

100P_0603_50V8

RF@

12

12

12

PC1018

PC1017

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1136

PC1132

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1043

PC1044

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1180

PC1177

@

100P_0603_50V8

22U_0603_6.3V6M

RF@

12

PC1019

PC1020

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1134

PC1135

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1045

PC1046

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1176

PC1179

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1021

PC1022

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1027

PC1138

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1048

PC1047

1U_0201_6.3V6M

1U_0201_6.3V6M

12

PC1178

PC1175

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1023

22U_0603_6.3V6M

12

PC1028

22U_0603_6.3V6M

12

PC1049

1U_0201_6.3V6M

12

PC1025

PC1024

22U_0603_6.3V6M

PC1130

22U_0603_6.3V6M

PC1055

1U_0201_6.3V6M

PC1026

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1131

PC1029

22U_0603_6.3V6M

22U_0603_6.3V6M

12

PC1056

1U_0201_6.3V6M

330U_D2_2.5VM_R9M

330U_D2_2.5VM_R9M

1

3 3

4 4

1

PC1127

PC1062

+

2

12

+

2

12

12

PC1170

PC1171

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1172

100P_0603_50V8

RF@

PC1174

PC1173

@

100P_0603_50V8

22U_0603_6.3V6M

RF@

VCC_SA Place on CPU
22U_0603 * 12 pcs + 1U_0201*7 pcs

+VCC_SA

12

12

PC1057

22U_0603_6.3V6M

12

12

PC1153

1U_0201_6.3V6M

12

12

PC1058

22U_0603_6.3V6M

12

PC1147

1U_0201_6.3V6M

12

PC1060

PC1059

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1149

PC1148

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1139

PC1140

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1150

PC1151

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

PC1141

22U_0603_6.3V6M

PC1152

1U_0201_6.3V6M

12

PC1143

PC1142

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

PC1146

PC1145

PC1144

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

LA-E082P

LA-E082P

LA-E082P

65 71Monday, December 12, 2016

65 71Monday, December 12, 2016

65 71Monday, December 12, 2016

E

0.1

0.1

0.1

A

+SDC_IN

1 1

PR909

3.3_0402_1%

12

PC926

DCIN_ISL88738

VDD_ISL88738

SDA_ISL88738
SCL_ISL88738

PC938

10P_0402_50V8J

1 2

BATGONE_ISL88738

1U_0402_25V6K

ADP_ISL88738

DCIN

18

VDD
ACIN
OTGEN/CMIN

21

SDA

22

SCL

23

PROCHOT#

24

ACOK

PR933

100K_0402_1%

1 2

PR951

0_0402_5%@

1 2

COMP_ISL88738

12

PR934

12

499_0402_1%

PC943

@

12

560P_0402_50V7K

PC944

0.01UF_0402_25V7K

Close to EC ADP_I pin

PD901

PD903

2 1

PD904

1 2

13

D

2

G

S

PR927

1M_0402_1%

12

12

PC933

1U_0402_6.3V6K

PR925

154K_0402_1%

1 2

12

12

PR916
1_0805_5%~D

PR918
100K_0402_1%

1 2

PBAT_CHARGER_SMBDAT<34,57>
PBAT_CHARGER_SMBCLK<34,57>

PBAT_PRES#<34,57>

+PWR_SRC

SDMK0340L-7-F_SOD323-2~D

+VBUS_DC_SS

+VBUS_DC_SS

+VBUS_DC_SS+VBUS_DC_SS

2 2

+DC_IN_SS

+DC_IN_SS

+DC_IN_SS+DC_IN_SS

L2N7002WT1G_SC70-3

3 3

RB520SM-30T2R_EMD2-2

SDMK0340L-7-F_SOD323-2~D

PC931 1U_0603_25V6

ACAV_IN1

PQ909

AC_DIS<34>

12

+SDC_IN

12

12

12

PC1286

0.1U_0402_25V6

H_PROCHOT#<12,34,63>

PROCHOT#_ISL88738<67>

PR931

100K_0402_1%

1 2

PR928 0_0402_5%@

1 2

PR944
442K_0402_1%

ACIN_ISL88738

PR945
100K_0402_5%

1 2

@

0_0402_5%

1
1 2
1 2
1 2

@

100K_0402_1%

1 2

PR920 0_0402_5%@
PR922 0_0402_5%@
PR926 0_0402_5%@

PR930

@

PR943
0_0603_5%

12

PROCHOT#_ISL88738

ACOK_ISL88738

+3.3V_ALW

CMOUT<67>

4 4

PR901

0.01_1206_1%

1
2

12

3.3_0402_1%

CSIP_ISL88738

PC925

4.7U_0402_6.3V6M

1 2

CSIP_ISL88738

CSIN_ISL88738

15

16

14

13

ADP

CSIP

CSIN

BATGONE

OTGPG/CMOUT26PROG27AMON/BMON29PSYS30VBAT

28

25

12

PR932

105K_0402_1%

12

12

PR947

0_0402_5%

@

PR935 0_0402_5%

@

I_BATT

I_BATT <34>

I_ADP <34>

B

+PWR_SRC_AC

4
3

12

PR910

CSIN_ISL88738

PC930

0.22U_0603_25V7K

1 2

PR914

3.3_0603_1%

1 2

UG1_ISL88738

BOOT1_ISL88738

11

12

BOOT1

UGATE1

ASGATE

CMOP

12

VBAT1_ISL88738

PR949 0_0402_5%@

12

PC947

0.1U_0402_25V6

I_ADP

PL901

EMC@

1UH_6.6A_20%_5X5X3_M

PJP901

@

1 2

PAD-OPEN 4x4m

12

PC927

1U_0402_25V6K

LG1_ISL88738

LX1_ISL88738

PU901

10

9

33

ISL88738HRTZ-T TQFN 32P PWM

PAD

LGATE1

PHASE1

VDDP

7

LGATE2
PHASE2
UGATE2

4

BOOT2

3

VSYS

2

CSOP

1

CSON

BGATE

31

32

BGATE_ISL88738

12

12

PR948

PR936

0_0402_5%

@

I_SYS <34,63>

PC950

@

0.1U_0402_25V6

12

PR915

4.7_0402_5%

1 2

VDDP_ISL88738
LG2_ISL88738

BOOT2_ISL88738
VSYS_ISL88738
CSOP_ISL88738
CSON_ISL88738

4.7U_0402_6.3V6M

12.7K_0402_1%

1 2

12

PC902

0.1U_0402_25V6

@EMC@

VDD_ISL88738

PC932

1U_0402_6.3V6K

PC934

0.22U_0603_25V7K

PC945

12

PR940

100_0402_5%

12

PC903

2200P_0402_50V7K

@EMC@

12

PR929 0_0402_5%@

1 2

1 2

+PBATT

12

PC911

PC904

22U_0805_25V6M

PR921

12

4.7_0603_5%

1 2

PC939 0.1U_0402_25V6@

1 2

PC942 1U_0402_25V6K

1 2

PR937 2.2_0402_1%

1 2

PR938 2.2_0402_1%

1 2

PC946 1U_0402_25V6K

12

22U_0805_25V6M

+PWR_SRC

12

PC905

22U_0805_25V6M

AC1_DISC#<26,67>

ACAV_IN_NB<34,57,67>

+CHARGER_SRC

12

PC906

@

22U_0805_25V6M

15U_B2_25VM_R100M

PQ905
CSD87351Q5D_SON8-7

C

1

1

+

+

PC909

PC910

2

2

@

15U_B2_25VM_R100M

1

2.2UH_PCMB103T-2R2MS_13A_20%

7
6
5

SW1_ISL88738

12

8

SNUB_CHG1

12

PR939

0_0402_5%@

1 2

PR941

0_0402_5%@

1 2

1

+

PC951

2

@

15U_B2_25VM_R100M

PL902

1

PR923

4.7_1206_5%

EMC@

PC940

680P_0603_50V7K

EMC@

3

2

SW2_ISL88738

12

PR924

4.7_1206_5%

EMC@

SNUB_CHG2

12

PC941

680P_0603_50V7K

EMC@

@

0_0402_5%

1 2

PD905

BAT54CW-7-F SOT-323

1

ACAV_IN1

+PWR_SRC

PQ904
CSD87351Q5D_SON8-7

1

7
6
5

8

PR950

PC949

0.1U_0402_10V7K

1 2

1 2

PR942

@

0_0402_5%

LM393_P

1
2

2

4

B
A

12

PC913

10U_0805_25VAK

12

PC928

0.1U_0402_25V6

@EMC@

UG2_ISL88738

LX2_ISL88738

5

P

Y

G

3

12

12

PC915

PC914

10U_0805_25VAK

10U_0805_25VAK

12

PC929

2200P_0402_50V7K

@EMC@

PR917

0.005_1206_1%

1
2

MC74VHC1G08DFT2G_SC70-5

PU903

PR946

@

0_0402_5%

4

1 2

12

PC916

10U_0805_25VAK

4
3

12

12

12

PC918

PC917

10U_0805_25VAK

10U_0805_25VAK

+VCHGR

12

PC935

10U_0805_25V6K

ACAV_IN<34,35>

PR953
100K_0402_1%

For IT8010 voltage
leakage issue

PC919

10U_0805_25VAK

12

PC936

10U_0805_25V6K

D

12

12

PC920

10U_0805_25VAK

PQ906
AON7409_DFN8-5

1
2
3 5

PC937

@

+PBATT

4

1 2

BGATE_ISL88738

4700P_0402_25V7K

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEETMAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D

AND TRADE SECRET INFORMATION. THIS SHEETMAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D

AND TRADE SECRET INFORMATION. THIS SHEETMAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSEDTO ANY THIRD PARTY WITHOUT PRIORW RITTEN CONSENTOF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSEDTO ANY THIRD PARTY WITHOUT PRIORW RITTEN CONSENTOF COMPAL ELECTRONICS, INC.

A

B

MAYBE USED BY OR DISCLOSEDTO ANY THIRD PARTY WITHOUT PRIORW RITTEN CONSENTOF COMPAL ELECTRONICS, INC.

<Issued_Date> <Deciphered_Date>

<Issued_Date> <Deciphered_Date>

<Issued_Date> <Deciphered_Date>

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CHARGE

CHARGE

CHARGE

LA-E082P

LA-E082P

LA-E082P

D

66 71Monday, December 12, 2016

66 71Monday, December 12, 2016

66 71Monday, December 12, 2016

0.1

0.1

0.1

5

DCIN_AC_Detector

PC1201

@

0.01U_0402_25V7K~D

1 2

12

PC1206

220P_0402_50V8J~D

12

PC1215

100P_0402_50V8J

@EMC@

12

PR1237

100K_0402_1%

@

12

PR1247

100K_0402_1%

PD1801

3

1
2

BAT54CW-7-F SOT-323

1.8M_0402_1%

LM393_P

8

3

P

+

2

-

G

4

EMI Part

EMC@

5A_Z120_25M_0805 _2P

1 2

1 2
EMC@

5A_Z120_25M_0805 _2P

12

PC1208

EMC@

1000P_0402_50V7K

S3 OVP

PD1205

@

SDMK0340L-7-F_SOD323-2

1 2

@

0_0402_5%

1 2

5

6

12

PC1212

@

100P_0402_50V8J

LM393_P

PR1203

1 2

PU1201A
LM393DGKR_VSSOP8

1

O

PL1201

PL1202

PR1238

LM393_P

8

P

+

O

-

G

4

+3.3V_VDD_DCIN

12

12

PC1207

1200P_0402_50V7K

12

12

PC1209

0.1U_0402_25V6

@EMC@

PU1201B
LM393DGKR_VSSOP8

7

PC1213

@

PR1206
1K_0402_1%

ACAV_IN_NB

PR1227

100K_0402_5%

12

12

1200P_0402_50V7K

PC1216

100P_0402_50V8J

EMC@

PR1240
100K_0402_1%

PR1243

@

0_0402_5%

1 2

ACAV_IN_NB <34,57,66,67 >

+TBTA_Vbus_1

12

+3.3V_VDD_DCIN

+DC_IN

D D

C C

+3.3V_VDD_DCIN

+3.3V_VDD_PIC

12

12

PR1201

PR1208

240K_0402_1%

102K_0402_1%

(>17.6V)

12

12

PR1219

23.2K_0402_1%

12

PC1205

PR1217

84.5K_0402_1%
100P_0402_50V8J~D

+TBTA_VBUS

+TBTA_Vbus_1 +3.3V_VDD_PIC

B B

12

PR1239

150K_0402_1%

@

12

12

PC1211

PR1246

100P_0402_50V8J

@

100K_0402_1%

@

+TBTA_Vbus_1

4

5

12

PC1214

@

+AC_IN

+3.3V_VDD_PIC

PR1236
100K_0402_5%

1 2
34

PQ1209B
DMN65D8LDW-7_SOT363-6

0.01UF_0402_25V7K

@

112

JUMP_43X118

S3

PQ1206
AON7409_DFN8-5

2

PJP1202

2

4

PC1210

12

PR1229

49.9K_0402_1%

61

PQ1209A
DMN65D8LDW-7_SOT363-6

1
2
35

1 2

1500P_0402_50V7K

+3.3V_VDD_PIC

EN_PD_HV_1<26,67>

12

12

PR1253
100K_0402_5%

EN_PD_HV_1#

5

EN_PD_HV_1<26,67>

(From TI GPIO1)

12

PR1228

499K_0402_1%

34

PR1210

1M_0402_5%

DCIN1_EN<35 >

@

PR1255

150K_0402_1%

3

S4 S

PQ1213

AON7409_DFN8-5

1
2

12

PR1251
300K_0402_1%

S

G

2

D

PQ1215

1 3

PC1204

0.1U_0402_10V7K

1

2

PR1215
0_0402_5%

12

PR1224

100K_0402_5%

PC1202

AO3409_SOT23

12

5

P

B
A

G

3

PQ1205

L2N7002WT1G_SC70-3

S

G

12

PR1252
100K_0402_5%

61

2

PQ1214A

DMN65D8LDW-7_SOT363-6

PQ1214B

DMN65D8LDW-7_SOT363-6

PR1254 0_0402_ 5%@

12

1 2

PR1211 0_0402_ 5%@

1 2
1 2

@

PR1221

@

0_0402_5%

1 2

3 5

12

12

PR1205

499K_0402_1%

2200P 50V K X7R 0603

+3.3V_VDD_PIC

PU1200
MC74VHC1G08DFT2G_SC70-5

4

O

D

13

2
12

PR1225

PR1226

0_0402_5%

1 2

100K_0402_5%

@

+3.3V_VDD_PIC

EN_PD_HV_1<26,67>

AC1_DISC#<26,66>

PR1216

@

1 2

4

2

0_0402_5%

PR1260

@

0_0402_5%

1 2

1 2

PR1244

@

0_0402_5%

12

PR1212

49.9K_0402_1%

61

PQ1201A

DMN65D8LDW-7_SOT363-6

PR1259

100K_0402_5%

5

G

+VBUS_DC_SS

+3.3V_ALW

100K_0402_5%

1 2

34

D

PQ1208B

S

DMN65D8LDW-7_SOT363-6

ACAV_IN_NB<34,57 ,66,67>

VBUS1_ECOK<35,67>

VBUS2_ECOK<35,57>
VBUS1_ECOK<35,67>

PR1234

2

@

0_0402_5%

1 2

2

PD1202

5A_100V 15UA_0.88V_TO227 -3

2

1

3

5

PQ1202
AON7409_DFN8-5

1
2
35

4

12

PR1213

49.9K_0402_1%

34

VBUS1_ECOK

1 2

61

D

G

PQ1208A

S

PR1261

PR1241

@

0_0402_5%

1 2

PR1220

@

12

0_0402_5%

PR1222

100K_0402_5%

+3.3V_ALW +3.3V_ALW

PR1242

@

0_0402_5%

1 2
1 2

PR1257

@

0_0402_5%

PR1232

100K_0402_5%

DMN65D8LDW-7_SOT363-6

5

G

12

1 2

+3.3V_ALW

S

5

@

100K_0402_5%

2

G

1 2

34

D

PR1235

PQ1207B
DMN65D8LDW-7_SOT363-6

1 2

@

0_0402_5%

PR1258

PQ1201B

DMN65D8LDW-7_SOT363-6

61

2

G

PQ1211A

+3.3V_ALW

DMN65D8LDW-7_SOT363-6

12

PR1207 499K_0402_1%

100K_0402_5%

1 2

5

G

1 2
61

D

S

12

PC1203 1500P_04 02_50V7K

PR1233

@

PR1230
100K_0402_5%

PQ1207A
DMN65D8LDW-7_SOT363-6

S

D

1 3

PQ1203 AO3409_SOT23

AC_DISC# <34,57,67>

12

34

@

PQ1211B

DMN65D8LDW-7_SOT363-6

12

PR1202
300K_0402_1%

G

2

12

PR1209
100K_0402_5%

34

PQ1204B

DMN65D8LDW-7_SOT363-6

+3.3V_ALW

PR1231
100K_0402_5%

@

1 2

0_0402_5%

1

61

D

PC1217

PQ1210A

S

DMN65D8LDW-7_SOT363-6

1500P_0402_50V7K

PR1245

5

G

1 2

@

2

PR1218
0_0402_5%

G

+3.3V_VDD_PIC

2

G

1

12

PR1214
100K_0402_5%

61

PQ1204A

DMN65D8LDW-7_SOT363-6

CMOUT <66>

34

D

PQ1210B

DMN65D8LDW-7_SOT363-6

PROCHOT#_ISL88738 <66>

13

D

S

PQ1216

L2N7002WT1G_SC70-3

2

PR1223

@

0_0402_5%

+SDC_IN

12

AC_DISC# <34,57,67>

OVP set t i ng: 5. 5V

LPS_PROTECT#

PT1@
PAD~D

(From

EN_PD_HV_1 <26,67>

EC)

PR1248

12

PR1249
10K_0402_5%

@

0_0402_5%

1 2

PR1250

@

0_0402_5%

1 2

13

D

2

G

S

PQ1212

L2N7002WT1G_SC70-3

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

ParkCity_TypeC_PD

ParkCity_TypeC_PD

ParkCity_TypeC_PD

LA-E082P

LA-E082P

LA-E082P

1

0.1

0.1

67 71Monday, December 12, 2016

67 71Monday, December 12, 2016

67 71Monday, December 12, 2016

0.1

5

Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot)

Rt=Rrefadj // (Rboot+Rref2)
Vm

in= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)]

Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2]

Vout=Vmin+N*Vstep
Vstep=(Vmax-Vmin)/Nmax

PWM-VID Spec and component Values

D D

PWM VID and Output voltage control

Boot mode

1.

2.Standby mode (don't support)

3.Normal mode

12

DSC@

+GPU_PWR_SRC

PR1313

T_typical T_max

110C 113.4C

PC1301

1U_0402_6.3V6K

DSC@

DSC@

1

0.01UF_0402_25V7K

2

12

@DSC@

PC1313

47P_0402_50V8J

5

12

1 2

PR1300

499K_0402_1%

1 2

@DSC@

PC1300

C C

GPU_VSS_SENSE<49>

B B

GPU_VDD_SENSE<49>

+GPU_CORE

1. VSNS Soft-Start time (Internal) is 0.7ms (PC1315 un-pop)
Tss=(Css*Vrefin)/Iss+2.3ms

=0.01U*0.9V/5uA+2.3ms=4.1ms (PC1315 pop)

2. Switching frequency setting:

Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)
=301.5Khz(Vin=13.5V)

3. Thermal monitoring:

(VGPU_VREF-VTSNS)/PR620=VTSNS/Rth

A A

@DSC@

DSC@

@DSC@

DSC@

1 2

0_0402_5%

1 2

PR1314

100_0402_1%

1 2

PR1315

0_0402_5%

1 2

PR1317

100_0402_1%

T_min

PR1318=18.7K

PR

96.73C 100C 103.1C

106.38C

1318=13K

PWM-VID Spec Config A Config B

Vmin
Vm

ax

Vboot

Voltage step

N of Voltage level

PR1308

18K_0402_1%

@DSC@

PR1310
0_0402_5%

GPU_FB

@DSC@

0.01U_0402_25V7K

ef2=PR10+PR12

Rr

PR1306

DSC@

2K_0402_5%

1 2

1

PC1307

2

0.01U_0402_25V7K

@DSC@

PC1315

1 2

12

PH1300

@DSC@

470K_0402_5%_TSM0B474J4702RE

Rrefadj
Rref1

Rboot

GPU_FBRTN

C

12

DSC@

12

GPU_VREF
GPU_TON

GPU_COMP

GPU_VREF

12

PR1318

18.7K_0402_1%

DSC@

12

PC1319

1U_0402_6.3V6K

@DSC@

PR1307
PR1303
PR1306
PR1308
PR1310
PC1308

DSC@

PR1303
20K_0402_1%

PR1307

20K_0402_1%

1 2

PC1308

2700P_0402_50V7K

DSC@

GPU_REFIN

0.6V 0.6V 0.65V

1.

2V 1.2V 1.15V

0.875V 0.9V 0.9V

6.25mV 6.25mV 25mV

96 96 20

39K 20K 39K

K 20K 30K

39

1.5K 2K 3K
30K 18K 24K

1.5K

1.5nf 2.7nf 1.8nf

GPU_REFADJ

6

PU1300

DSC@

7

REFADJ

REFIN

8

VREF

9

TON

10

RGND

11

VSNS

12

SS

TSNS/ISEN3

GND

13

25

GPU_TSNS/ISEN3

4

Current Limit threshold setting
Ro

cset= (Ivalley * Rds(on) + 40 mV) / 10uA

I_ripple=(6-0.9)*0.9/
(287Khz*0.22u*6)=12.12A

OCP=47.4A/2=23.7A per phase
Ivalley=23.7A-12.12A/2=17.64A

H-side MOS:CSD87351

Config C

0

3K

PR1301

@DSC@

1K_0402_5%

1 2

1 2

PR1302

@DSC@

0_0402_5%

1 2

@DSC@

0_0402_5%

GPU_VID

GPU_PSI

GPU_EN

U2_UGATE1

2

3

4

5

EN

PSI

VID

UGATE1

TALERT/ISEN2

PGOOD

VCC/ISNE1

14

17

16

15

U2_UGATE2

GPU_DSBL/ISEN1

4

PR1305

12

PC1309

U2_BOOT1

0.1U_0402_25V6

@DSC@

1

BOOT1

PHASE1
LGATE1

GND/PWM3

PVCC
LAGTE2
PHASE2

BOOT218UGATE2

RT8813AGQW_WQFN24_4X4

+3.3V_RUN

U2_BOOT2

DSC@

PR1321

10K_0402_1%

+3.3V_RUN

GPU_PWM_VID <48>

PSI Pull high on HW side

NVVDD_PSI <48>

PR1309

DSC@

1K_0402_5%

1 2

Reserve Location

U2_PHASE1

24

U2_LGATE1

23

U2_PWM3

22
21

U2_LGATE2

20

U2_PHASE2

19

12

Rds(on):

8.8m ohm(max)@Vgs=4.5V

Choke: 0.22uH (Size:7*7*3)
Rdc=0.98mohm +-5%
Heat Rating Current=28A

Saturation Current=28A

C=1*330uF (6mohm)=330uF
Vripple=Iripple*ESR(min)=12.79A*6mohm=76.74mV

Operation phase NumberPSI Voltage setting

phase with DEM 0V to 0.8V

1
1 phase with CCM 1.2V to 1.8V
Active phase with CCM 2.4V to 5.5V

3V3_MAIN_EN <48,52>

Pull high on HW side

DGPU_PWROK <12,35,52>

DSC@

2.2_0603_5%

1 2

12

DSC@

PC1318

1U_0402_6.3V6K

+5V_RUN

PR1320

3

VGA Chip

OpenVReg Configurations

ted TDP Power at Tj=102C

Ra

Bo

osted GPU Total at Tj=102C

L-side MOS:CSD87351

Rds(on):

3.1m ohm(max)@Vgs=4.5V

EDP-Continuous at Tj=102C
EDP-Peak at Tj=102C

Istep max (Evaluation)

OCP Setting Current
Rocset

Recommendation

Polymer Cap (330uF)

PR1304 2.2_0603_5%DSC@

U2_BOOT1

1 2

U2_UGATE1

U2_LGATE1

U2_BOOT2

1 2

U2_UGATE2

U2_PHASE2

U2_LGATE2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

DSC@

PC1306

0.22U_0603_25V7K

2

2

DSC@

PQ1300

12

PR1312

9.76K_0402_1%

DSC@

PR1316 2.2_0603_5%DSC@

1

DSC@

PC1314

0.22U_0603_25V7K

2

CSD87351Q5D_SON8-7

2

3
4

2

N16S-GMR-S

Config B

18W
23W

21A

39.5A
28A

47.4A

9.76K

2phase

6mohm * 1

+GPU_PWR_SRC

1

8

1

DSC@

8

PQ1301
CSD87351Q5D_SON8-7

2

7
6

7
6
5

12

12

12

PC1302

PC1303

0.1U_0402_25V6

@EMCDSC@

U2_PHASE1_C

12

12

PC1304

10U_0805_25V6K

2200P_0402_50V7K

DSC@

@EMCDSC@

PL1301

DSC@

0.22UH_PCME064T-R22MS0R985_28A_20%

1 2

PR1311

4.7_1206_5%

GPU_SNUB1

RFDSC@

PC1312

680P_0603_50V7K

RFDSC@

PC1316

10U_0805_25V6K

DSC@

PL1302

DSC@

0.22UH_PCME064T-R22MS0R985_28A_20%

U2_PHASE2_C

12

12

1 2

PR1319

4.7_1206_5%

GPU_SNUB2

RFDSC@

PC1320

680P_0603_50V7K

RFDSC@

1

PL1300

@EMCDSC@

PC1305

10U_0805_25V6K

DSC@

12

12

12

PC1317

10U_0805_25V6K

DSC@

HCB2012KF-121T50_0805

1 2

PJP1301

@

1 2

PAD-OPEN 4x4m

+VGA_CORE
EDP-Continuous 21 A
EDP-Peak 39.5 A
OCP 47.4A

+PWR_SRC

+GPU_PWR_SRC

1

+

2

PC1311

330U_D2_2.5V_R6M

DSC@

+GPU_CORE

+GPU_CORE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

+GPU_CORE

+GPU_CORE

+GPU_CORE

Document Number Re v

Document Number Re v

Document Number Re v

LA-E082P

LA-E082P

LA-E082P

1

68 71Monday, December 12, 2016

68 71Monday, December 12, 2016

68 71Monday, December 12, 2016

0.1

0.1

0.1

5

D D

4

3

2

1

1 2

PR1400

@DSC@

0_0402_5%

EN_+1.35_VRAM

+PWR_SRC

C C

+3.3V_ALW

12

@DSC@

PR1406

12

@DSC@

PR1407

0_0402_5%

B B

PJP1400

@

PAD-OPEN 1x2m~D

ILMT_+1.35_VRAM

21

12

12

PC1402

PC1400

100P_0402_50V8J

RFDSC@

RFDSC@

+1.35_VRAM
T

DC 4.13 A
Peak Current 5.9 A
OCP Current 9 A Fix by IC

Choke DCR 11.0mohm , 12.0mohm

12

PC1404

100P_0402_50V8J

10U_0805_25V6K

@DSC@

TYP MAX

+1.35_VRAM_B+

12

PC1405

10U_0805_25V6K

DSC@

ILMT_+1.35_VRAM

DSC@

PU1400

8

IN

EN

GND

ILMT
PG

BS
LX

FB
BYP
LDO

9

3
2

SYX196DQNC_QFN10_3X3

1

DSC@

BST_+1.35_VRAM

6

SW_+1.35_VRAM

10

4
7

LDO_+1.35_VRAM

5

12

PC1411

4.7U_0603_6.3V6K

DSC@

PC1403

0.1U_0603_25V7K

BST_+1.35_VRAM_C

1 2

12

PC1412

4.7U_0603_6.3V6K

DSC@

+3.3V_ALW

@DSC@

12

1M_0402_1%

DSC@

PR1403

0_0603_5%

1 2

PR1401

RFDSC@

4.7_1206_5%

1 2

DSC@

FB_+1.35_VRAM

PR1402

SNB_+1.35_VRAM

PL1400

1UH_6.6A_20%_5X5X3_M

PR1404

DSC@

RFDSC@

12

12

30.1K_0402_1%

12

VRAM_EN <48,52>

680P_0603_50V7K

1 2

12

12

PR1405

1K_0402_5%

DSC@

DSC@

PR1408
24K_0402_1%

+1.35_VRAMP

PC1401

12

PC1407

PC1406

330P_0402_50V7K

DSC@

DSC@

PJP1401

@

2

112

JUMP_43X118

+1.35V_MEM_GFX

+1.35_VRAMP

12

12

PC1408

22U_0805_6.3VAM

22U_0805_6.3VAM

DSC@

12

PC1409

PC1410

22U_0805_6.3VAM

22U_0805_6.3VAM

DSC@

DSC@

The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

GPU_VRAM(SYX198D)

GPU_VRAM(SYX198D)

GPU_VRAM(SYX198D)

LA-E082P

LA-E082P

LA-E082P

69 71Monday, December 12, 2016

69 71Monday, December 12, 2016

69 71Monday, December 12, 2016

1

0.1

0.1

0.1

5

4

3

2

1

D D

+GPU_CORE

nVidia GB4-64 package
Under GPU

12

12

C C

+GPU_CORE

12

12

PC1500

PC1501

DSC@

DSC@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

12

12

PC1510

PC1511

1U_0402_6.3V

1U_0402_6.3V

DSC@

DSC@

12

12

PC1503

PC1502

DSC@

DSC@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

12

PC1513

PC1512

1U_0402_6.3V

1U_0402_6.3V

DSC@

DSC@

12

12

12

PC1504

DSC@

4.7U_0603_6.3V6K

PC1506

PC1505

DSC@

DSC@

4.7U_0603_6.3V6K

12

PC1507

PC1508

DSC@

4.7U_0603_6.3V6K

DSC@

4.7U_0603_6.3V6K

4.7uF 0603 * 10

12

PC1509

1uF 0402 * 4

DSC@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

nVidia GB4-64 package
Ne

ar GPU

47uF 0805 *1

12

12

12

B B

12

PC1515

PC1514

47U_0805_6.3V6M

DSC@

PC1516

22U_0805_6.3V6M

DSC@

DSC@

12

PC1517

DSC@

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

12

12

PC1518

DSC@

4.7U_0805_6.3V6K

PC1520

PC1519

DSC@

DSC@

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

22uF 0805 *1

4.7uF 0805 *5

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

LA-E082P

LA-E082P

LA-E082P

70 71Monday, December 12, 2016

70 71Monday, December 12, 2016

70 71Monday, December 12, 2016

1

0.1

0.1

0.1

5

4

Version Change List ( P. I. R. List )

3

2

1

Request

Item Issue DescriptionDate

D D

1

67

2

66

3

67 Compal

4

VCCSA_ISL95857

63~

5

6

C C

7

8

9

64

66

57
67

VCC_CORE/
GT_ISL95857

VCCSA_ISL9585763

CHARGER66

Title

1Type-C PD
Selector

CHARGER

1Type-C PD
Selector

1Type-C PD
Selector

CHARGER

+DCIN
1Type-C PD
Selector

2016
05/20

2016
05/30

2016
05/30

2016
06/13

06/13

2016
06/13

2016
06/20

2016
06/22

2016
06/27

Owner

Compal

Compal

Compal67

Compal2016

Compal

Compal

Compal

Compal

Change the S4 fast turn off circuit to
avoid the leakage.

Add the Circuit for Multiple Input Detach
detection & PROCHOT#

Add the Circuit for Multiple Input Detach
detection & PROCHOT#

For Temp/Voltage test to fine tune the DC-IN
detect voltage from 17.6V to 16.9V

location alignment

To decrease the charger input leakage voltage for
TypeC AC.

To solve the MOS leakage problem to avoid
the error active.

IA/GT/SA CORE static LL optimization

EMI request

Re-connect the PR1251.1 and PQ1215.3 from +VBUS_DC_SS to +AC_IN.

Add PR960 0_0402_5%(SD028000080) and depop PR919 0_0402_5%(SD028000080)
let the PU901.20 CMIN connect to GND.
PU901.23 add cross page net PROCHOT#_ISL88738

Add PQ1216 DMN65D8LW-7_SOT323-3(SB00000UO00) to drive the PROCHOT#
Reserve PC1217 1500P_0402_50V7K(SE074152K80)

PR1219 change from 22.6K to 23.2K(SD034232280)

IA_CORE change location PU603 to PU610, PL603 to PL610
GT_CORE change location PU604 to PU612, PL604 to PL612
SA_CORE change location PU606 to PU614, PL601 to PL614

PD903 change from SDMK0340L-7-F_SOD323-2~D(SCS0340L010)
to RB520SM-30T2R_EMD2-2(SCS00006C00)

PR12, PR11, PR1205, PR1207, PR1228 change from 1M_0402_5%(SD028100480)
to 499K_0402_1%(SD034499380)
PR16, PR18, PR1212, PR1213, PR1229 change from 1M_0402_5%(SD028100480)
to 49.9K_0402_1%(SD034499280)
PR10, PR1251 and PR1202 change from 100K_0402_5%(SD028100380)
to 300K_0402_1%(SD034300380)

PC621, PC647 change from 680P(SE074681K80) to 1200P(SE074122K80)
PR640 change from 383_0402_1%(SD034383080) to 365_0402_1%(SD034365080)
PR638 change from 374_0402_1%(SD034374080) to 340_0402_1%(SD00000KT80)
PR629 change from 93.1K_0402_1%(SD034931280) to 95.3K_0402_1% (SD034953280)

PR921 change from 2.2_0603_5%(SD013220B80) to 4.7_0603_5%(SD013470B80)
PR914 change from 0_0603_5%(SD013000080) to 3.3_0603_1%(SD014330B80)
pop PR923, PR924 4.7_1206_5%(SD001470B80)
pop PC940, PC941 680P_0603_50V7K(SE025681K80)

Solution Description

Rev.Page#

X01

X01

X01

X01

X01

X01

X01

X01

X01

B B

10

11

12

13

14

A A

15 2016

+5V/+3.3V
+1.2V_MEN

58~61

+0.6V_DDR

68~69

1VALWP/VCCIO PRIM
GPU_COREP/GPU_VRAM

CHARGER Reserve the OVP function to protect the typeC device.

66

CHARGER

CHARGER

66 Compal X03

+VCCSA_ISL95857 2016

63 Compal

VCCIO/PRIM

5

2016
06/28

2016
07/01

2016
07/01

2016
09/02

09/21

09/29

Compal

Compal

Compal X0166

RF request

Change the charger version from A version to B version.

For IT8010 voltage leakage issue Add PR953 100K_0402_1%(SD034100380)

Change CPU core version to MP version.

PCH LPM functionCompal61

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

TRADE
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

pop PC100, PC103, PC115, PC116, PC301, PC303, PC409, PC1400, PC1402
100P_0402_50V8J(SE071101J80)
pop PC1320, PC1312, PC204, PC302, PC112 680P_0603_50V7K(SE025681K80)
pop PR1319, PR1311, PR202, PR303, PR106 4.7_1206_5%(SD000010280)

Depop PJP1202, PR1255, PR1239, PR1246, PC1211, PR1237, PC1212
, PD1205, PC1213, PC1214, PR1248
Change PR1247 from 200K_0402_1%(SD034200380) to 100K_0402_1%(SD034100380)
Re-modify the S11 OVP description to S3 OVP.

Change PU901 from ISL88738HRTZ REV.A-T TQFN 32P PWM(SA00009VW10)
to ISL88738HRTZ REV.B-T TQFN 32P PWM(SA00009VW20)

Change PU602 from SA0000A4A00 to SA0000A4A0L

Unpop PR410 0_0402_5%(SD028000080)
Pop PR426 0_0402_5%(SD028000080)

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ize Document Number R ev

Size Document Number Re v

Size Document Number Re v

S

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P.I.R

P.I.R

P.I.R

LA-E082P

LA-E082P

LA-E082P

1

71 71Monday, December 12, 2016

71 71Monday, December 12, 2016

71 71Monday, December 12, 2016

X01

X01

X03

0.1

0.1

0.1

5

4

Version Change List ( P. I. R. List )

3

2

1

Item

D D

Page# Re

4 HW

25

5

6

7

C C

9

10

11

12

46 0.2(X01)

43,46 0.2(X01)

Title

Date

HW 2016/05/241 34 COMPAL 0.2(X01)For Schematic align Remove RA2

2016/05/24 UE1.C1 pin name change to GPIO024/nRESETI

COMPALHW352 Symbol pin name change

Symbol pin name changeCOMPAL2016/05/24 UT5.A6/A7/A8/B7 pin name change to GND,

2016/05/24 COMPAL Symbol pin name change UT9.20 pin name change to SNK_CAD/DCI_DAT,

HW

2016/05/24 COMPAL

DP HPD base on INTEL PDG Delete RC312/RC2426

Disable AUX snoop feature Pop RT308COMPAL2016/05/24HW25

Remove HDD LED MUX feature Depop RN100/RN101COMPAL2016/05/24HW33,40

HW8

HW

HW

COMPAL2016/05/246

2016/05/24 COMPAL S0ix(modern standy) support for VCCPLL_OC17 Pop RZ120 and Depop UZ34

PORT80_DET# Reserve RE513 100k (SD028100380) to GNDCOMPAL2016/05/2435

Follow Intel PDG AUX topology

Request Owner

Issue

Description

UT5.D6 pin name change to HRESET

UT9.32 pin name change to HPDIN/DCI_CLK

Delete RC179/RC180/RC181/RC182
Add test point T281/T282 for CPU_DP1_AUXN and CPU_DP1_AUXP

Add net name VCCSTG_EN(UZ19.4) and connect to RZ120.1

1.add CLIP1

Solution
Description

v.

0.2(X01)

0.2(X01)3 9 HW

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

13

B B

30

HW

HW

14

15

16

17

12

33

3318

19

A A

35 HW COMPAL

HW

HW 2016/06/07 0.2(X01)

HW

HW COMPAL

2016/05/27 COMPAL25 For Schematic align SW2_DP1_HPD Add RT380 place near TUSB546

CZ28,CZ29 change from 0.047uF to 0.01uF

2016/06/01

INTEL Intel reviwe result

CZ27 change from 0.1uF(@)_0201 to 10uF_0603
CZ32/CZ31/CZ29 place near JNGFF1.2/JNGFF1.4
CZ27/CZ30/CZ28 place near JNGFF1.72/JNGFF1.74

change to Nuvoton TPM form ATMEL TPM37,38 2016/06/07 DELL Delete ATMEL TPM circuit, Add Nuvoton TPM circuit

Add CC331 2.2PF (SE07122AC80) for HDA_RST#

INTEL

2016/06/07 INTEL

Intel MOW request

Intel reviwe result
(WWAN Coex feature support)

Add CC332 2.2PF (SE07122AC80) for HDA_SDIN0
Add CC333 2.2PF (SE07122AC80) for HDA_SDOUT

Add RZ128 0 ohm connect WWAN_COEX3 and WLAN_COEX3
Add RZ129 0 ohm connect WWAN_COEX2 and WLAN_COEX2
Add RZ130 0 ohm connect WWAN_COEX1 and WLAN_COEX1

Debug card reserve Add RZ131, RZ132 for PORT80_DET# and HOST_DEBUG_TX2016/06/07

2016/06/07 For MEC5105K-D1-TN sample 1.UE1 change to SA00009GL00(S IC MEC5105K-D1-TN WFBGA 169P EC)

2.Depop RE361,Pop RE360,RE362

2016/06/17 Base on ME drawing H10 change from H_4P0 to H_3P020 46 HW COMPAL

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (1/6)

EE P.I.R (1/6)

EE P.I.R (1/6)

LA-E082P

LA-E082P

LA-E082P

72 75Monday, December 12, 2016

72 75Monday, December 12, 2016

72 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

Version Change List ( P. I. R.

3

2

1

List )

Item

D D

Page# R

24

25

26

C C

27

28

29

30

34 HW 2016/06/20 COMPAL Base on Audio EA result RA7,RA8 change from 24.9 to 16.2 ohm(SD00001U900)

30 EMI request CL22 change from 1500pF to 10pF

29

35

36

31

32 0.2(X01)

Title

Date

HW 2016/06/1721 42 COMPAL 0.2(X01)

2016/06/22HW

2016/06/22HW12 UE1.D7 add HDD_DET#

2016/06/28 For VGA test result Pop RV121/RV122/CV132/CV133COMPALHW24

Request
Owner

Issue

Description

Base on USB3 EA result,B_EQ change to13dB Depop RI42,pop RI44

COMPALHW1122 0.2(X01)2016/06/17 Base on Crystal EA result

COMPAL2016/06/17HW4123 BITS284924-HDD is still working after press

COMPALHW38,45

power button into S5 during POST.

ME request2016/06/20

COMPAL2016/06/22HW

COMPAL2016/06/22

COMPAL

DELL

COMPAL2016/06/22HW29

COMPAL BIOS need detect Storage type and dynamic

EMI request Change LV1 from SM01000BV00 to SM01000NY00HW29

ME request JIR1 change from SP010023D00 to SP010013W20

The posibility of GPIO map update,RTCRST_ON
change from GPIO141 to GPIO122

RF request

change the name

Solution
Description

CC23 change form 15pF to 12pF

Depop RN5

1.JKBTP1 change from HRS_TF49-20S-0P5SH_20P-T to
CVILU_CF5020FD0RK-05-NH_20P-T

2.JUSH1 change from HRS_TF49-26S-0P5SH_26P-T to
CVILU_CF5026FD0RK-05-NH_26P-T

(SE167100J80 S CER CAP 10P 3KV J NPO 1808 AC250V X2Y3)

Add RE514(@),RE515 for RTCRST_ON2016/06/22HW

、、、、

CZ1 change to 100pF(0201)SE174101J80

CA7

ev.

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)33

34 0.2(X01)

B B

35 0.2(X01)

COMPAL2016/06/29HW38 X8 have no difference JUSH1 pin define

36 0.2(X01)

37

HW4138

A A

COMPAL2016/06/29 0.2(X01)FFS VDD_IO change to +3.3V_RUNBITS283552 - [BR_CSLP] FFS AP no function

For DFX request CLIP1.1 change from GND to NCCOMPAL2016/06/28HW46

concern

Depop DZ7,Pop RZ87

Let USH_PWR_STATE# keep low at S5COMPAL2016/06/29HW38 RZ10 change from 1M to 100k ohm

Foe X01 Board IDCOMPAL2016/06/29HW36 RE79 change from 240k to 130k ohm

when execute FF generator or shake SU

RF request29 POP CC27 & change value from 22p to 47pCOMPAL2016/08/04HW39

DSC BOM change Pop RC385, Depop RC386COMPAL2016/08/04HW1839

0.2(X01)

0.3(X02)

0.3(X02)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ize Document Number R ev

Size Document Number Re v

Size Document Number Re v

S

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (2/6)

EE P.I.R (2/6)

EE P.I.R (2/6)

LA-E082P

LA-E082P

LA-E082P

73 75Monday, December 12, 2016

73 75Monday, December 12, 2016

73 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

Version Change List ( P. I. R.

3

2

1

List )

Item

D D

Page# Re

45 HW

45 42 HW 2016/08/05 USB3 repeater power rail

46 11 HW COMPAL2016/08/08 EMI request add RC417 (0 ohm) for Xtak24_IN

C C

42 COMPAL47 HW 2016/08/08 schematic modify 1. pop RI37

1849
4850

52
53

54

B B

57

58

59
60

61

62

42
35

42

38

35

34
34

34

37

63

64

65

A A

33

66

Title

Date

HW 2016/08/0440 34, 35 COMPAL 0.3(X02)Vendor schematic review 1. Add net WRST# to UE2.4 and CE500 1uf (SE000000K80)

2016/08/0444

HW

2016/08/11
2016/08/12HW

2016/08/16 COMPAL EA requestHW55 42 depop RI38, RI44, RI53, RI57 for USB3 repeater

HW

HW

HW

HW

HW

HW
HW35
HW34

HW

HW39

HW3567

5

2016/09/20
2016/09/20

2016/09/20

2016/09/20

2016/09/20

Request
Owner

Issue

Description

2. Add RE523 0 ohm for UE2 power pin soft start

3. Change RE14,RE15,RE18 from 100k ohm to 10k ohm

4. Change RPE12.1 to RE524 (10Kohm) for EXPANDER_GPU_SMDAT

5. Change RPE12.2 to RE525 (10Kohm) for EXPANDER_GPU_SMCLK

6. Reserve CE504~CE505 for EXPANDER_GPU_SMDAT/CLK to GND.

Intel suggestion14

RC137 change from 1K to 3KCOMPAL2016/08/04HW41

Solution
Description

For UT7 2nd source issueCOMPAL2016/08/04HW27 Add RT393 PD 100K ohm to +5V_PD_VDD for discharging instantly42

Touchpad I2C EACOMPAL2016/08/0443

Chagne RZ20, RZ21 from 4.7k ohm to 2.2k ohm
Change CZ80, CZ81 from 330pf to 10pf

Change UT5 from SA00009W200 to SA00009W210For PD sample COMPALHW26

COMPAL BITS290368-System can't be waked from S3

when connect to right USB port
via USB3.0 to LAN Dongle.

DFB requestCOMPAL2016/08/09HW32, 3748

Add RI79 0ohm to +3.3V_RUN and De-pop it.
Add RI80 0ohm to +3.3V_ALW_PCH and pop it.

2. RI79, RI80 footprint change form 0402 to 0603

3. add QI1 controlling USB3 repeater PD#
SMT concern DZ1, DZ2, DZ5, DZ6 PCB pad is too small,

suggest use the symbol "RB520SM-30T2R_EMD2-2" follow PD903

DA8,DE1,DV10 follow symbol "RB520SM-30T2R_EMD2-2"Footprint alignCOMPAL2016/08/10HW33, 35, 4851
COMPAL2016/08/11HW change USB repeater PD# enable pin to "USB_PWR_SHR_VBUS_EN"
COMPAL

COMPAL

schematic modify
schematic align

schematic modify

add power rail +3.3V_ALW_UE2 for UE2

delete QI1, depop RI37,

add RI81 connecting "USB_PWR_SHR_VBUS_EN" & "USB3_PD#'

DGPU_PWR_EN need to use BIOS solutionCOMPAL2016/09/08HW56 depop RC385,pop RC3869

TPM change to NPCT650VB2YXCOMPAL Change UZ12 from to SA00008EL70 to SA00008EL802016/09/08

COMPAL2016/09/08

Expander I/O change from ITE8010 to MCP23008

COMPAL2016/09/08

Change UE2 from SA00009VL00 to SA0000ADQ00, remove RE523
Change RE524, RE525 from 10Kohm to 2.2Kohm

Change RE79 to 33kohm (SD028330280)Board ID

Reserve RE526(10K) PU for USH_DET# to +3.3V_ALWschematic alignCOMPAL2016/09/08

COMPAL2016/09/08

COMPAL2016/09/08

COMPAL
COMPAL

COMPAL

COMPAL

EC request for power consumption

WDT schematic option 2

EMI request

NV GPU seqest

EMI requestCOMPAL

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Add RE505 PU to +3.3V_ALW for LOM_CABLE_DETECT# (Reserve)
Add RE532 PU to +3.3V_ALW for BCM5882_ALERT#

POP RZ8,RZ9 for USH SMBusUSH/B de-pop, pop on MB side

Add RE536/RE537 for resistors for PCH_DPWROK circuitDELL request
use Option2: pop RE361 / depop RE362

1. L6~L9 change to 80ohm bead (BLM15PD800SN1D, SM01000N000) for BR14/15

2. depop CA2, CA3

3. RA55,RA56 change location toLA15, LA16 with 33ohm bead
(BLM15PX330SN1D,SM01000NA00)
CV247 change from 3900pf t0 4700pf (SE075472K80)
CV248 change form 220pf to 470pf (SE074471K80)

RC295/RC417 change from 0 to 33 ohm

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (2/6)

EE P.I.R (2/6)

EE P.I.R (2/6)

LA-E082P

LA-E082P

LA-E082P

1

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.4(X03)

0.4(X03)

0.4(X03)

0.4(X03)

0.4(X03)

0.4(X03)

0.4(X03)

0.4(X03)

0.4(X03)

0.4(X03)

74 75Monday, December 12, 2016

74 75Monday, December 12, 2016

74 75Monday, December 12, 2016

v.

1.0

1.0

1.0

5

IGS

4

Version Change List ( P. I. R.

3

2

1

List )

Item

D D

Page# R

68 35

2469 HW depop RV121/RV122U-line VGA EA PASSCOMPAL2016/10/04
2670 CT85,CT86 change to 470p.(SE074471k80)TI CC pin for ESD requestCOMPAL2016/10/04

74

75
76

C C

78

36

36
36

36

36
79
80

81

36

36

Title

Date

HW CE12 change to 2.2u (SE000008880)

HW
HW2571

HW3572

HW3473

HW

HW
HW

HW

HW

2016/10/04
2016/10/04

2016/10/06

2016/10/06

2016/10/31
2016/10/31

2016/10/31 COMPAL For DFB request.

2016/10/31

2016/10/31HWCOMPAL36

HW

Request
Owner

COMPAL2016/10/04

COMPAL

COMPAL

COMPAL

COMPAL

COMPAL2016/10/31

Issue

Description

BITS294007 - Sometimes need to
press power button twice to power on system.

BR14 OTP issue

UE1.H8 to prevent EOS issue on MEC5105COMPAL
BOARD ID

BOARD IDCOMPAL
Change R1 to R3 for MP part

Service Mode Switch remove
RE374 change BS to LPC@

For MEC5105 rev. C

Solution
Description

RE33 change to 1K (SD028100180)

RE77 change to 1.69K_1% (SD00000JB80)
add QE13,RE530,CE503EC watchdog reserveCOMPAL

Change RE79 to 8.2k ohm(SD028820180)

Change RE79 to 4.3k ohm(SD028430180)
Change UL1 CP/N to SA000081G1L

Change UE1 CP/N to SA00009GL30
change UV1 CP/N to SA00009S01L

Close solder mask CMOS1 (-NPM) and other co-lay part77

Depop SW1 and RC222 and RC221 change to short pad
RE374 change BS to LPC@

Pop RE362,RE536;
Depop RE361,QE13,CE503,RE530,UE7,CE5,CE6,RE348,RE537

ev.

0.4(X03)

0.4(X03)

0.4(X03)

0.4(X03)

0.5(X04)

0.5(X04)Add RE539(100ohm) to CV2_ON

0.5(X04)

1.0(A00)

1.0(A00)

1.0(A00)

1.0(A00)

1.0(A00)

1.0(A00)

1.0(A00)

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

EE P.I.R (2/6)

EE P.I.R (2/6)

EE P.I.R (2/6)

LA-E082P

LA-E082P

LA-E082P

75 75Wednesday, December 14, 2016

75 75Wednesday, December 14, 2016

75 75Wednesday, December 14, 2016

1

1.0

1.0

1.0

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ize Document Number R ev

Size Document Number Re v

Size Document Number Re v

S

Date: Sheet of

Date: Sheet of

Date: Sheet of