Dell Latitude 3470 Schematics

5

D D

4

3

2

1

Loveland Schematics

Skylake-U

C C

2015-09-18 REV : A00

B B

DY : None Installed

A A

UMA: UMA only installed OPS: DISCRTE OPTIMUS installed

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, September 18, 2015

Date: Sheet of

Cover Page

Loveland SKL-U

Taipei Hsien 221, Taiwan, R.O.C.

1 105

1

A00

5

Project code: Love14 SKL --> 4PD060010001 Love15 SKL --> 4PD061010001

Loveland SKL-U Block Diagram

PCB P/N: 14291 Revision: A00

D D

VRAM(DDR3L) *4

2GB

78,79

DDR3L

DIS only

DDR3L 1600

SODIMM A

DDR3L 1600

C C

14"/15" LCD

55

Touch Panel

IR Camera

Digital MIC

55

SODIMM B

USB2.0 x 1

LAN 10/100/1000 RJ45

Conn.

32

B B

HDMI V1.4a

Left side

57

USB1(USB3.0)

35,36

Left side

USB3(USB3.0)

35,36

A A

Universal Jack

29

5

2CH SPEAKER (2CH 2W/4ohm)

29

MIC_IN/GND

HP_R/L

DDR3L 1333/1600MHz Channel A

12

DDR3L 1333/1600MHz Channel B

12

RTL8111G

HDA

CODEC

Realtek ALC3246

GPU

NVDIA N16V-GM-S

25W

73,74,75,76,77

31

27

4

eDP

PCIE x 1

DDI1

USB2.0 x 1

USB3.0 x 1

USB2.0 x 1

USB3.0 x 1

HDA

4

PCIE x 4

Intel CPU

Skylake U 2+2U

15W (UMA&DIS)

SKL PCH-LP

10 USB 2.0/1.1 ports

6 USB 3.0 ports

High Definition Audio

3 SATA ports 6 PCIE ports LPC I/F ACPI 5.0

3

DDI2

USB2.0 x 1

USB2.0

PCIE x 1

USB2.0 x 1

SM Bus

SATA(Gen3) x 1

LPC BUS

Flash ROM

SPI

I2C

3

SPI

16MB

25

TPM 2.0

NPCT650JAAYX

DP/VGA Converter

REALTEK RTD2168-CGT

USB2(USB2.0)

IOBD 4

CardReader

Realtek RTS5170

NGFF WLAN

802.11a/b/g/n BT V4.0 combo AC 3160

61

Free Fall Sensor

ST LNG2DM

HDD P11

HDD

KBC

SMSC

MEC1404-NU-GP

PS2

91

67

60

Int. KB

2

VGA

IOBD 6

IO Board

SD Card Slot

FRINGERPRINT

NB-2020-U

SMBUS

24

65

PrecisionTouch pad

2

VGA DB

VGA Conn.

92

LPC debug port

Thermal

NUVOTON NCT7718W

FAN

65

IOBD 6

26

1

CHARGER

BQ24780RUYR

INPUTS

AD+

BT+

SYSTEM DC/DC

RT6576DGQW

INPUTS

DCBATOUT

CPU Core Power

NCP81208MNTXG NCP81382MNTXG X2 NCP81253MNTBG

INPUTS

DCBATOUT

DCBATOUT +VCCGT

DDR3L SUS

TPS51716RUKR

INPUTS OUTPUTS

DCBATOUT 1D35V_S3

OUTPUTS

DCBATOUT

OUTPUTS

3D3V_AUX_S5 5V_PWR_2 5V_S5 3D3V_S5

OUTPUTS

VCC_CORE

+VCCSADCBATOUT

0D675V_S0

CPU DCDC-V1D00A

SY8208DQNC

INPUTS OUTPUTS

DCBATOUT

LDO-V1D5V

S-1339D15-M5001

3D3V_S5

INPUTS OUTPUTS

3D3V_S5

68

L1:Top L2:VCC L3:Signal L4:Signal

26

Title

Size Document Num ber Rev

A2

Date: Sheet of

L5:GND L6:Bottom

Block Diagram

Loveland SKL-U

1

1D0V_S5

OUTPUTSINPUTS

1D5V_S0

LDO-V1D8V

APL5930KAI-TRG

1D8V_S5

5V/3V S0

G5016KD1U

INPUTS

5V_S5

VCCSTG

M5938ARD1U

5V_S5

VCCST

M5938ARD1U

PCB LAYER

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

2 105Tuesday, Septem ber 15, 2015

OUTPUTS

5V_S0 3D3V_S03D3V_S5

OUTPUTSINPUTS

+VCCIO +VCCSTG

OUTPUTSINPUTS

+V1.00U_CPU5V_S5 +VCCST_CPU

46~50

40

44

45

51

53

54

5

4

3

2

1

Main Func = CPU

D D

C C

(Blanking)

B B

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

(Reserved)

2

Loveland SKL-U

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

3 105Tuesday, September 15, 2015

1

A00

5

4

3

2

1

Main Func = CPU

#544669 CRB Rev0.52

+VCCST_CPU

D D

+VCCSTG

12

[PECI] and [PROCHOT#] Impedance control: 50 ohm

H_PECI[24]

H_PROCHOT#[24,43,44,46]

XDP_BPM[3:0][99]

#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm #544669 Rev0.52: Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm

C C

TOUCH_PANEL_INTR#[24,55]

INT_TP#[24,65]

1 2

Rb

R404Do Not Stuff R404Do Not Stuff

(#543016) PROCHOT# Routing Guidelines

B B

+VCCSTG = 1.0 V

R401

R401 1KR2J-1-GP

1KR2J-1-GP

H_PROCHOT#_R_R H_PROCHOT#_R

Do Not Stuff

1 2

Ra

TP403

TP404

TP401

Do Not Stuff

R403

1 2

499R2F-2-GP

TP402

1

R2045Do Not Stuff R2045Do Not Stuff

1

R41249D9R2F-GP R41249D9R2F-GP R41349D9R2F-GP R41349D9R2F-GP

H_CATERR#

1

PCH_THERMTRIP SKTOCC#

1

XDP_BPM0 XDP_BPM1 XDP_BPM2

XDP_BPM3 GPP_E3/CPU_GP0 TOUCHPAD_INTR#

GPP_B4/CPU_GP3

CPU_POPIRCOMP

12

PCH_POPIRCOMP

12

PCH_THERMTRIP

CPU1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-GP-U

071.SKYLA.000U

XDP_TMS XDP_TDI

XDP_TDO_CPU

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

XDP_TCK_JTAGX

XDP_TRST# XDP_TCLK

PCH_JTAG_TCK

CPU MISC

12

R419

R419 1KR2J-1-GP

1KR2J-1-GP

R420

1 2

DY

Do Not Stuff

SKYLAKE_ULT

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

+VCCSTG = 1.0 V

1 2

DY

R421Do Not Stuff

DY

DY DY

DY

R421Do Not Stuff R422Do Not Stuff

R422Do Not Stuff R423Do Not Stuff

R423Do Not Stuff

R40851R2J-2-GP R40851R2J-2-GP R40951R2J-2-GP R40951R2J-2-GP R41651R2J-2-GP R41651R2J-2-GP R417Do Not Stuff

R417Do Not Stuff

1 2 1 2

1 2 1 2 1 2 1 2

R402 Do Not Stuff

1 2

DY

R406 51R2J-2-GPR406 51R2J-2-GP R407 Do Not Stuff

R407 Do Not Stuff

DY

1 2 1 2

DY

4 OF 20

JTAGX

+VCCSTG

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

H_THERMTRIP# [40]

XDP_TCLK [99]

XDP_TDI [99] XDP_TDO_CPU [99] XDP_TMS [99] XDP_TRST# [99]

PCH_JTAG_TCK [99] PCH_JTAG_TDI [99] PCH_JTAG_TDO [99] PCH_JTAG_TMS [99] XDP_TRST# [99] XDP_TCK_JTAGX [99]

M1,2,3,4,5: <3 inches M6: 1-11 inches MCPU: 0.3-1.5 inches

A A

Mt <0.3 mils Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

5

4

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

CPU_(JTAG/CPU SIDE BAND)

Custom

Loveland SKL-U

4 105Tuesday, September 15, 2015

1

A00

Main Func = CPU

M_A_DQ[63:0][12]

5

4

3

2

1

DDR3L ball type: Interleaved Type

M_B_DQ[63:0][13]

D D

CPU1B

M_A_DQ0

AL71

M_A_DQ1 M_A_DQ2 M_A_DQ3

M_A_DQ[0:7]

M_A_DQ[8:15]

M_B_DQ[0:7]

M_B_DQ[8:15]

C C

M_A_DQ[16:23]

M_A_DQ[24:31]

M_B_DQ[16:23]

M_B_DQ[24:31]

DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.

B B

Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential clock pair to clock pair swapping within a channel is not allowed.

M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

AF65

DDR1_DQ[0]/DDR0_DQ[8]

AF64

DDR1_DQ[1]/DDR0_DQ[9]

AK65

DDR1_DQ[2]/DDR0_DQ[10]

AK64

DDR1_DQ[3]/DDR0_DQ[11]

AF66

DDR1_DQ[4]/DDR0_DQ[12]

AF67

DDR1_DQ[5]/DDR0_DQ[13]

AK67

DDR1_DQ[6]/DDR0_DQ[14]

AK66

DDR1_DQ[7]/DDR0_DQ[15]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

SKYLAKE-GP-U

071.SKYLA.000U

SKYLAKE_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5]

DDR0_DQ[16]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9]

DDR0_DQ[17]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6]

DDR0_DQ[18]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8]

DDR0_DQ[19]

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7]

DDR0_DQ[20]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_DQ[21]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[ 12]

DDR0_DQ[22]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[ 11]

DDR0_DQ[23]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT # DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[ 13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[ 10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]

DDR CH - A

DDR1_DQSN[0]/DDR0_DQ[2] DDR1_DQSP[0]/DDR0_DQ[2] DDR1_DQSN[1]/DDR0_DQ[3] DDR1_DQSP[1]/DDR0_DQ[3]

PDG: DDR/ODT

A A

5

2 OF 20

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

M_A_DQ32

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

M_A_A5

BA51

M_A_A9

BB54

M_A_A6

BA52

M_A_A8

AY52

M_A_A7

AW52 AY55

M_A_A12

AW54

M_A_A11

BA54

M_A_A15

BA55

M_A_A14

AY54

M_A_A13

AU46 AU48 AT46 AU50 AU52

M_A_A2

AY51 AT48

M_A_A10

AT50

M_A_A1

BB50

M_A_A0

AY50

M_A_A3

BA50

M_A_A4

BB52

M_A_DQS_DN0

AM70

M_A_DQS_DP0

AM69

M_A_DQS_DN1

AT69

M_A_DQS_DP1

AT70

M_B_DQS_DN0

AH66

M_B_DQS_DP0

AH65

M_B_DQS_DN1

AG69

M_B_DQS_DP1

AG70

M_A_DQS_DN2

BA64

M_A_DQS_DP2

AY64

M_A_DQS_DN3

AY60

M_A_DQS_DP3

BA60

M_B_DQS_DN2

AR66

M_B_DQS_DP2

AR65

M_B_DQS_DN3

AR61

M_B_DQS_DP3

AR60 AW50

DDR0_PAR

AT52 AY67

AY68 BA67

AW67

4

M_A_CLK#0 [12] M_A_CLK0 [12 ] M_A_CLK#1 [12] M_A_CLK1 [12 ]

M_A_CKE0 [12] M_A_CKE1 [12]

M_A_CS#0 [12 ] M_A_CS#1 [12 ] M_A_DIMA_ODT0 [12] M_A_DIMA_ODT1 [12]

M_A_BS2 [12]

M_A_CAS# [12]

M_A_WE# [12]

M_A_RAS# [12]

M_A_BS0 [12] M_A_BS1 [12]

M_A_DQS0

M_A_DQS1

M_B_DQS0

M_B_DQS1

M_A_DQS2 M_A_DQS3 M_B_DQS2 M_B_DQS3

TP501 Do Not StuffT P501 Do Not Stuff

1

V_SM_VREF_CN T [42] M_VREF_DQ_D IM0 [42] M_VREF_DQ_D IM1 [42]

SM_PGCNTL [51]

M_A_DQ[32:39]

M_A_DQ[40:47]

M_B_DQ[32:39]

M_B_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_DQ[48:55]

M_B_DQ[56:63]

M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

3

CPU1C

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-GP-U

071.SKYLA.000U

M_A_A[15:0] [12]

M_A_DQS_DN[7 :0] [12]

M_A_DQS_DP[7:0] [12]

SKYLAKE_ULT

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[ 12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[ 11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[ 13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[ 10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0]

DDR CH - B

DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

3 OF 20

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

BA38 AY38 AY34 BA34 AT38 AR38 AT32 AR32 BA30 AY30 AY26 BA26 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7

M_B_A12 M_B_A11 M_B_A15 M_B_A14

M_B_A13

M_B_A2 M_B_A10

M_B_A1 M_B_A0 M_B_A3 M_B_A4

M_A_DQS_DN4 M_A_DQS_DP4 M_A_DQS_DN5 M_A_DQS_DP5 M_B_DQS_DN4 M_B_DQS_DP4 M_B_DQS_DN5 M_B_DQS_DP5 M_A_DQS_DN6 M_A_DQS_DP6 M_A_DQS_DN7 M_A_DQS_DP7 M_B_DQS_DN6 M_B_DQS_DP6 M_B_DQS_DN7 M_B_DQS_DP7

DDR1_PAR SM_DRAMRST # SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

M_B_CLK#0 [13] M_B_CLK#1 [13] M_B_CLK0 [13] M_B_CLK1 [13]

M_B_CKE0 [13] M_B_CKE1 [13]

M_B_CS#0 [13] M_B_CS#1 [13] M_B_DIMB_ODT0 [13] M_B_DIMB_ODT1 [13]

M_B_BS2 [13]

M_B_CAS# [13]

M_B_WE# [13]

M_B_RAS# [13]

M_B_BS0 [13] M_B_BS1 [13]

M_A_DQS4 M_A_DQS5 M_B_DQS4 M_B_DQS5 M_A_DQS6 M_A_DQS7 M_B_DQS6 M_B_DQS7

TP502 Do Not StuffT P502 Do Not Stuff

1

R501 121R2F- GPR501 121R2F- GP

1 2

R502 80D6R2F -L-GPR502 80D6R2F -L-GP

1 2

R503 100R2F- L1-GP-UR503 100R2F- L1-GP-U

1 2

#543016

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

Layout Note:

M_B_A[15:0] [13]

M_B_DQS_DN[7 :0] [13]

M_B_DQS_DP[7:0] [13]

Design Guideline: SM_RCOMP keep routing length less than 500 mils.

M_B_DQS_DN0 M_B_DQS_DN1 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

2

1D35V_S3

12

R505

R505 470R2F-GP

470R2F-GP

R504Do Not Stuff R504Do N ot Stuff

DY

1 2

D502

Do Not Stuff

1 2

DDR3_DR AMRST# [12,1 3]

close to CPU

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU_(DDR)

Loveland SKL-U

1

5 105Tuesday, Septem ber 15, 2015

A00

5

4

3

2

1

Main Func = CPU

CPU1S

RESERVED SIGNALS-1

CFG[19:0][99]

D D

ITP_PMODE[99]

C C

TP601Do Not Stuff TP601Do Not Stuff TP602Do Not Stuff TP602Do Not Stuff

TP612Do Not Stuff TP612Do Not Stuff TP613Do Not Stuff TP613Do Not Stuff

B B

PCH strap pin:

CFG3

DY

12

R604

R604 Do Not Stuff

Do Not Stuff

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

CFG_RCOMP

R60149D9R2F-GP R60149D9R2F-GP

12

RSVD_TP_BA70

1

RSVD_TP_BA68

1

RSVD_F65

1

RSVD_G65

1

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

D1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

SKYLAKE-GP-U

071.SKYLA.000U

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

RESERVED SIGNALS-1

SKYLAKE_ULT

RSVD_TP_AW71 RSVD_TP_AW70

1 : DISABLED

CFG4

12

R605

R605 1KR2J-1-GP

1KR2J-1-GP

(#543016)

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

An external Display Port device is connected to the Embedded Display Port.

1 : DISABLED (Default) No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

19 OF 20

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3 RSVD_D71

RSVD_C70 RSVD_C54

RSVD_D54

VSS_AY71

ZVM#

RSVD_AW71 RSVD_AW70

MSM#

PROC_SELECT#

TP5 TP6

TP4

TP1 TP2

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1 E1

E2 BA4

BB4 A4

C4 BB5 A69

B69 AY3 D71

C70 C54

D54 AY4

BB3 AY71

AR56 AW71

AW70 AP56

C64

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

TP5_AU5 TP6_AT5

TP4_BB5

TP1_AY4 TP2_BB3

VSS_AY71 ZVM#

Do Not Stuff

RSVD_TP_AW71 RSVD_TP_AW70

MSM# PROC_SELECT#

R602

1 2

R603

R603 100KR2J-1-GP

100KR2J-1-GP

1 1

1

1 1

TP603 Do Not StuffTP603 Do Not Stuff TP604 Do Not StuffTP604 Do Not Stuff

TP605 Do Not StuffTP605 Do Not Stuff TP606 Do Not StuffTP606 Do Not Stuff

TP607 Do Not StuffTP607 Do Not Stuff TP608 Do Not StuffTP608 Do Not Stuff

TP609 Do Not StuffTP609 Do Not Stuff

TP610 Do Not StuffTP610 Do Not Stuff TP611 Do Not StuffTP611 Do Not Stuff

TP616 Do Not StuffTP616 Do Not Stuff TP614 Do Not StuffTP614 Do Not Stuff

TP615 Do Not StuffTP615 Do Not Stuff TP617 Do Not StuffTP617 Do Not Stuff

#54469 CRB.

CFG TERMINATIONS

20140807 david

#544669 Rev0.52 (CRB)

+VCCST_CPU

A A

5

SKL(#543016): Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

4

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(RESERVED)

Loveland SKL-U

6 105Tuesday, September 15, 2015

1

A00

5

4

3

2

1

Main Func = CPU

CPU1M

+VCCGT

CPU1L

VCC_CORE VCC_C ORE

D D

TP704Do N ot Stuff TP704Do Not St uff TP708Do N ot Stuff TP708Do Not St uff

C C

Layout Note: The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch). Route the Alert signal between the Clock and the Data signals.

VCC_OPC_1P8 _H63

1

VCC_OPC_1P8 _H63

1

CPU1L

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD_K32

VCCG0

AK32

RSVD_AK32

VCCG1

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

SKYLAKE-GP-U

071.SKYLA.000U

CPU POWER 1 OF 4

SKYLAKE_ULT

12 OF 20

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

H_CPU_SVIDALR T# H_CPU_SVIDC LK H_CPU_SVIDD AT

VCC_SENSE [46] VSS_SENSE [46]

+VCCSTG

VCCGT_SEN SE[46] VSSGT_SENSE[46]

SVID DATA

+VCCST_CP U

CLOSE TO CPU

H_CPU_SVIDD AT

SVID CLOCK

B B

H_CPU_SVIDC LK

12

R726

R726 100R2F-L1-GP- U

100R2F-L1-GP- U

R709 Do Not StuffR709 Do Not Stuff

R732 Do Not StuffR732 Do Not Stuff

1 2

#543016

1 2

+VCCST_CP U

12

DY

R723

R723 Do Not Stuff

Do Not Stuff

#543016 CLOSE TO VR

VR_SVID_DATA [46]

VR_SVID_CLK [46]

SVID_543016:

CPU1M

CPU POWER 2 OF 4

A48

VCCGT

A53

VCCGT

A58

VCCGT

A62

VCCGT

A66

VCCGT

AA63

VCCGT

AA64

VCCGT

AA66

VCCGT

AA67

VCCGT

AA69

VCCGT

AA70

VCCGT

AA71

VCCGT

AC64

VCCGT

AC65

VCCGT

AC66

VCCGT

AC67

VCCGT

AC68

VCCGT

AC69

VCCGT

AC70

VCCGT

AC71

VCCGT

J43

VCCGT

J45

VCCGT

J46

VCCGT

J48

VCCGT

J50

VCCGT

J52

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K48

VCCGT

K50

VCCGT

K52

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_SENSE

J69

VSSGT_SENSE

SKYLAKE-GP-U

071.SKYLA.000U

SKYLAKE_ULT

13 OF 20

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCCGT

12

C722

DY

Do Not Stuff

#544669 CRB.

R705

1 2

Do Not Stuff

1D35V_S3+VDDQ_CPU _CLK

12

DY

12

+VDDQ_CPU _CLK1D35V_S3

12

C719

C719 SC1U10V2KX-1G P

SC1U10V2KX-1G P

+VDDQ_CPU _CLK

C715S C10U6D3V3MX- GP C715SC10U6D3V3MX- GP

+VCCST_CP U

C716S C1U10V2KX-1GP C716S C1U10V2KX-1GP

+VCCSTG

C717D o Not Stuff

1D35V_S3

C718S CD1U16V2KX- 3GP C 718SC D1U16V2KX-3GP

+V1.00U_CPU

12

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

+VCCIO

VCCIO_VR_FB VSSIO_VR_FB

+VCCIO(ICCMAX.=2.73A)

+VCCSA

VCCIO_VR_FB VSSIO_VR_FB

VCCSA_SENS E VSSSA_SENSE

+VCCIO

+VCCSA

12

R735

R735 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R734

R734 100R2F-L1-GP- U

100R2F-L1-GP- U

VSSSA_SENSE [46] VCCSA_SENS E [46]

R733

R733 100R2F-L1-GP- U

100R2F-L1-GP- U

R730

R730 100R2F-L1-GP- U

100R2F-L1-GP- U

CPU1N

CPU POWER 3 OF 4

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

0.12 A

C721

SCD1U16V2KX-3GP

VCC_CORE

+VCCGT

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKYLAKE-GP-U

071.SKYLA.000U

12

R719

R719 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R720

R720 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R721

R721 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R722

R722 100R2F-L1-GP- U

100R2F-L1-GP- U

0.04 A

12

C720

SCD1U16V2KX-3GP

14 OF 20

VCCIO VCCIO

SKYLAKE_ULT

VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

VCC_SENSE [46 ]

VSS_SENSE [46]

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

VCCGT_SEN SE [46]

VSSGT_SENSE [46]

+VCCST_CP U

#543016

12

CLOSE TO CPU

R727

R727 56R2J-4-GP

56R2J-4-GP

R728

H_CPU_SVIDALR T#

A A

R728

12

220R2J-L2-GP

5

VR_SVID_ALERT# [46]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, Septem ber 15, 2015

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU(VCC_CORE)

Loveland SKL-U

1

7 105

A00

5

4

3

2

1

Main Func = CPU

D D

CPU1A

SKYLAKE_ULT

HDMI_DATA2#[57]

HDMI_DATA2[57]

HDMI

3D3V_S0

RN801

2 3 1

SRN2K2J-1-GP

C C

3D3V_S0

R804

1 2

2K2R2J-2-GP

2K2R2J-2-GP R803

R803

1 2

Do Not Stuff

DY

CPU_DP1_CTRL_DATA CPU_DP1_CTRL_CLK

4

CPU_DP2_CTRL_DATA

CPU_DP2_CTRL_CLK

DP to VGA

HDMI

Check

+VCCIO

HDMI_DATA1#[57]

HDMI_DATA1[57]

HDMI_DATA0#[57]

HDMI_DATA0[57]

HDMI_CLK#[57]

PCH_DPC_N0[66]

PCH_DPC_P0[66]

PCH_DPC_N1[66]

PCH_DPC_P1[66]

R801

1 2

24D9R2F-L-GP

HDMI_CLK[57]

CPU_DP1_CTRL_CLK[57]

CPU_DP1_CTRL_DATA[57]

Do Not Stuff

TP802

CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA

DDPD_CTRLDATA

1

EDP_COMP

(#543016) eDP_RCOMP Guideline

Signal Trace

Width

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%

Isolation Spacing

Resistor Value

Length

Max = 100 mils

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-GP-U

071.SKYLA.000U

(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.

SKYLAKE_ULT

DDI

DISPLAY SIDEBANDS

Strap

EDP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

1 OF 20

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9

CPU_DP2_HPD1

L7 L6

CPU_DP2_HPD3

N9 L10

R12 R11 U13

EDP_DISP_UTIL

Do Not Stuff

R807 Do Not Stuff

1

R805

1 2 1 2

DY

eDP_TX_CPU_N0 [55] eDP_TX_CPU_P0 [55] eDP_TX_CPU_N1 [55] eDP_TX_CPU_P1 [55]

eDP_AUX_CPU_N [55] eDP_AUX_CPU_P [55]

TP801 Do Not StuffTP801 Do Not Stuff

PCH_DPC_AUXN [66] PCH_DPC_AUXP [66]

CPU_DP1_HPD [57] CPU_DP2_HPD [66] SIO_EXT_SMI#_R [24]

EDP_HPD [55]

L_BKLT_EN [24] L_BKLT_CTRL [55] EDP_VDD_EN [55]

3D3V_S0

(#543016) DDI Disabling and Termination Guidelines

B B

Port Strap Enable Port Disable Port

Port 1

Port 2

DDPB_CTRLDATA

DDPC_CTRLDATA

PU to 3.3 V with 2.2-k ±5% resistor

NC

SIO_EXT_SMI#_R

Strap pin:

Port B / Port C Detected

DDPB_CTRLDATA

DDPC_CTRLDATA

These two signals have weak internal pull-down.

Design Guideline: Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.

A A

5

Sampled at rising edge of PCH_PWROK

0 = Port B is not detected. 1 = Port B is detected.

*

0 = Port C is not detected. 1 = Port C is detected.

*

4

3

12

R806

R806 100KR2J-1-GP

100KR2J-1-GP

R802 10KR2J-3-GPR802 10KR2J-3-GP

1 2

CPU_DP2_HPD

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(DISPLAY)

Loveland SKL-U

8 105Tuesday, September 15, 2015

1

A00

5

4

3

2

1

Main Func = CPU

D D

C C

(Blanking)

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

(Reserved)

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Loveland SKL-U

9 105Tuesday, September 15, 2015

1

A00

Main Func = CPU

5

4

3

2

1

(#543016 PDG)

CORE

VCC_CORE

PC1001

12

S

S C22U6D3V3MX-1-GP

+VCCIO

PC1010

12

PC1021

12

C22U6D3V3MX-1-GP

S

S C22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

S

S C22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

D D

C C

PC1002

12

PC1011

12

PC1022

12

PC1003

12

S

S C22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

PC1012

12

S

S C22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

PC1023

12

S

S C22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

22U 0603 x 30

PC1004

PC1005

12

SC22U6D3V3MX-1-GP

S

S C22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

PC1014

PC1013

12

S

SC22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

PC1024

PC1025

12

S

SC22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

PC1006

12

PC1015

12

PC1026

12

PC1007

12

SC22U6D3V3MX-1-GP

PC1016

12

SC22U6D3V3MX-1-GP

PC1027

12

SC22U6D3V3MX-1-GP

+VCCPRIM_CO RE

PC1008

12

PC1017

12

PC1028

12

PC1009

12

SC22U6D3V3MX-1-GP

PC1018

PC1020

PC1019

12

SC22U6D3V3MX-1-GP

PC1029

PC1030

12

SC22U6D3V3MX-1-GP

1D35V_S3

12

PC1056SC10U6D3V3MX-GP PC1056SC10U6D3V3MX-GP

PC1057SC10U6D3V3MX-GP PC1057SC10U6D3V3MX-GP

PC1055SC10U6D3V3MX-GP PC1055SC10U6D3V3MX-GP

12

PC1063Do Not StuffDYPC1063Do Not Stuff

PC1064

DY

Do Not Stuff

VCCSA

PC1048

PC1046

12

SC22U6D3V3MX-1-GP

+VCCSA

PC1062Do Not StuffDYPC1062Do Not Stuff

DY

12

PC1058SC10U6D3V3MX-GP PC1058SC10U6D3V3MX-GP

12

EC1001S C1U10V2KX-1GP EC1001SC1 U10V2KX-1GP

PC1049

12

SC22U6D3V3MX-1-GP

12

PC1059Do Not StuffDYPC1059Do Not Stuff

PC1060Do Not StuffDYPC1060Do Not Stuff

DY

12

EC1002SCD1U25V2KX-GP EC1002SCD1U25V2KX-GP

EC1003S C1U10V2KX-1GP EC1003SC1 U10V2KX-1GP

EC1004S C1U10V2KX-1GP EC1004SC1 U10V2KX-1GP

22U 0603 x 9

PC1050

12

SC22U6D3V3MX-1-GP

10U 0603 x 4

12

PC1061Do Not StuffDYPC1061Do Not Stuff

DY

12

EC1005SCD1U25V2KX-GP EC1005SCD1U25V2KX-GP

PC1052

PC1051

12

SC22U6D3V3MX-1-GP

PC1053

12

SC22U6D3V3MX-1-GP

Do Not Stuff

DY

+VCCIO(ICCMAX.=2.73A)

12

C1037Do Not Stuff

C1036SC22U6D3V3MX-1-GPPC1036SC22U6D3V3MX-1-GP

C1035SC22U6D3V3MX-1-GPPC1035SC22U6D3V3MX-1-GP P

P

+VCCGT

P

DY

VCCGT

PC1031

12

S

S C22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

PC1032

12

PC1033

12

SC22U6D3V3MX-1-GP

PC1038

PC1039

12

SC22U6D3V5MX-2GP

22U 0603 x28

PC1034

PC1041

12

SC22U6D3V3MX-1-GP

PC1097

PC1054

PC1047

12

PC1071

12

SC22U6D3V3MX-1-GP

PC1072

PC1073

12

SC22U6D3V3MX-1-GP

12

PC1069

PC1044

PC1070

PC1042

PC1043

12

SC22U6D3V3MX-1-GP

PC1070

12

SC22U6D3V3MX-1-GP

PC1074

12

PC1065

12

SC22U6D3V3MX-1-GP

PC1075

12

SC22U6D3V3MX-1-GP

PC1066

12

DY

PC1076

12

PC1067

12

Do Not Stuff

DY

PC1077

12

SC22U6D3V3MX-1-GP

PC1097

PC1068

12

Do Not Stuff

DY

PC1078

12

SC22U6D3V3MX-1-GP

Do Not Stuff

PC1079

12

PC1098

12

Do Not Stuff

DY

SC22U6D3V3MX-1-GP

B B

PC1087

PC1081

PC1082

PC1080

12

S

S C22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

A A

5

PC1083

PC1084

12

S

S C22U6D3V3MX-1-GP

C22U6D3V3MX-1-GP

PC1084

12

SC22U6D3V3MX-1-GP

PC1085

12

PC1087

PC1089

PC1086

12

SC22U6D3V3MX-1-GP

PC1089

PC1088

12

SC22U6D3V3MX-1-GP

Do Not Stuff

SC22U6D3V3MX-1-GP

DY

PC1090

12

DY

PC1092

PC1094

PC1093

Do Not Stuff

DY

Do Not Stuff

DY

4

PC1093

PC1091

12

Do Not Stuff

PC1096

PC1095

12

Do Not Stuff

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU_(Power CAP1)

Loveland SKL-U

1

A00

10 105Tuesday, Septem ber 15, 2015

A00

5

4

3

2

1

Main Func = CPU

+VCCGT

12

C1138

12

C1148

12

C1149

C1150

SC1U10V2KX-1GP

1U 0402 x 6

SC1U10V2KX-1GP

C1147

S

C1U10V2KX-1GP

12

C1136

S

S C1U10V2KX-1GP

C1U10V2KX-1GP

D D

+VCCIO

+VCCIO(ICCMAX.=2.73A)

12

C1151

C1152

SC1U10V2KX-1GP

VCCIO

12

C1153

C1154

SC1U10V2KX-1GP

PCH DERIVED RAILS

1D0V_S5 +V1.00A_SIP

R1117

1 2

Do Not Stuff

C C

VCCPRIM_COR E

B B

R1125 Do Not StuffR1125 Do Not Stuff

1 2

R1122 Do Not StuffR1122 Do Not Stuff

1 2

R1112 Do Not StuffR1112 Do Not Stuff

1 2

R1114 Do Not StuffR1114 Do Not Stuff

1 2

R1121 Do Not StuffR1121 Do Not Stuff

1 2

R1133 Do Not StuffR1133 Do Not Stuff

1 2

R1134 Do Not StuffR1134 Do Not Stuff

1 2

R1130 Do Not StuffR1130 Do Not Stuff

1 2

R1131 Do Not StuffR1131 Do Not Stuff

1 2

R1132 Do Not StuffR1132 Do Not Stuff

1 2

+VCCSA

3 PAD SHARING

R1104

1 2

DY

+V1.00A_SIP

R1105

1 2

DY

R1103

1 2

Do Not Stuff

+VCCF24NS_ 1P0_L

+VCC24TBT_1 P0

+VCCPRIM_1P0

+VCCF100_1P0_L

+VCCF135_1P0

+VCCFHV

+VCCMPHYAON _1P0

+VCCDTS_1P 0

+VCC19P2_1P0

+VCCF100OC _1P0_L

+VCCPRIM_CO RE

3D3V_S5_PCH

Do Not Stuff

+VCCPGPPA(ICCMAX.=0.05A)

+V1.8A_SIP +VCCPGPPA

+V3.3A_SIP

Do Not Stuff

R1110

1 2

Do Not Stuff

+V1.8A_SIP

Do Not Stuff

+VCCPRIM_CO RE +VCCIO

R1107

1 2

DY

R1111

1 2

DY

Do Not Stuff

Do Not Stuff R1109

R1109

1 2

R1115

1 2

R1116

1 2

R1123

1 2

R1124

1 2

R1127

1 2

R1126

1 2

R1128

1 2

R1136

1 2

DY

Do Not Stuff

+VCCPRTC PRIM_3P3

+VCCPGPPB

+VCCPGPPC

+VCCPGPPE

+VCCPRIM_3P3

+VCCPSPI

+VCCPGPPG

+VCCMPHYGTA ON_1P0_LS_SIP

12

C1182

C1174

C1182

SC1U10V2KX-1GP

DY

+V3.3A_SIP

+V1.8A_SIP

Do Not Stuff

1 2

Do Not Stuff

1 2

Do Not Stuff

R1135

R1118

DY

+VCCPAZIO

+VCCMPHYGTA ON_1P0_LS_SIP

R1101

1 2

0R3J-0-U-G P

+VCCMPHYGTAON_1P0(ICCMAX.=3.5A)

+VCCAPLLEBB_1 P0

C1180

C1173

12

DY

Do Not Stuff

SC1U10V2KX-1GP

+VCCMPHYGTA ON_1P0_LS_SIP

R1102

1 2

0R3J-0-U-G P

+VCCAMPHYPLL_1P 0_L

SC22U6D3V3MX-1-GP

12

C1181

C1172

SC1U10V2KX-1GP

12

+VCCMPHYGT AON_1P0_LS_SIP

R1106

1 2

Do Not Stuff

+VCCSRAM_1P 0

12

C1176

SC10U10V5KX-2GP

C1175

SC1U10V2KX-1GP

VCC_CORE

12

C1101

C1102

C1103

S

C1U10V2KX-1GP

A A

U-line 23e 28W IccMax current-10ms max = 34 A

C1U10V2KX-1GP

5

12

C1116

C1117

S

S C1U10V2KX-1GP

C1U10V2KX-1GP

C1117

SC1U10V2KX-1GP

1U 0402 x 5

4

+V3.3A_SIP

+V1.8A_SIP

1 2

Do Not Stuff

1 2

Do Not Stuff

3

R1108

R1129

DY

+VCCPGPPD _TCH

Do Not Stuff

+VCCPGPPD _TCH

12

R1113

1 2

C1183

SC10U10V5KX-2G P

+VCCPGPPD

+VCCAMPHYPLL_1P 0_L +VCCAMPHYPLL_1P 0 +V1 .00A_SIP +VCCAPLL_1P0

R1120

1 2

0R3J-0-U-G P

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU_(Power CAP2)

Loveland SKL-U

1

11 105Tuesday, Septem ber 15, 2015

+V1.8A +V1 .8A_SIP

R1139

12

Do Not Stuff

+V1.8A_SIP

Do Not Stuff

R1138

+VCCPGPPF

12

1 2

2

R1119

0R3J-0-U-G P

12

C1184

C1184 SC22U6D3V3MX- 1-GP

SC22U6D3V3MX- 1-GP

A00

5

4

3

2

1

Main Func = DDR SODIMM

DM1

M_A_A[15:0][5]

D D

M_A_BS2[5] M_A_BS0[5]

M_A_BS1[5]

M_A_DQ[63:0][5]

M_A_DQ[0:7]

M_A_DQ[8:15]

12

C1201

Layout Note:

Place these caps close to VREF_CA

M_VREF_CA_D IMMA

12

C1218

C1202

M_A_DQ[16:23]

SCD1U16V2KX-3GP

Layout Note:

Place these caps close to VREF_DQ

M_VREF_DQ_D IMMA

12

C1205

Do Not Stuff

C1206

SCD1U16V2KX-3GP

M_A_DQ[24:31]

M_A_DQ[32:39]

M_A_DQ[40:47]

SCD1U16V2KX-3GP

M_A_DQ[48:55]

SCD1U16V2KX-3GP

C C

SCD1U16V2KX-3GP

12

C1204

DY

SCD1U16V2KX-3GP

Layout Note:

Place these caps close to VTT1 and VTT2.

M_A_DQ[56:63]

Do Not Stuff

C1217

M_A_DQS_DN[7: 0][5]

M_A_DQS_DP[7:0][5]

M_A_DIMA_ODT0[5] M_A_DIMA_ODT1[5]

DY

M_VREF_CA_D IMMA M_VREF_DQ_D IMMA

12

B B

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

DDR3_DR AMRST#[5,13]

M_A_DIMA_ODT0 M_A_DIMA_ODT1

DY

D1217

D1217 Do Not Stuff

Do Not Stuff

1 2

Do Not Stuff

0D675V_S0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ3 M_A_DQ1 M_A_DQ4 M_A_DQ7 M_A_DQ2 M_A_DQ6 M_A_DQ0 M_A_DQ5 M_A_DQ9 M_A_DQ13 M_A_DQ14 M_A_DQ10 M_A_DQ8 M_A_DQ12 M_A_DQ15 M_A_DQ11 M_A_DQ20 M_A_DQ16 M_A_DQ23 M_A_DQ19 M_A_DQ21 M_A_DQ17 M_A_DQ22 M_A_DQ18 M_A_DQ25 M_A_DQ28 M_A_DQ26 M_A_DQ30 M_A_DQ24 M_A_DQ29 M_A_DQ31 M_A_DQ27 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ46 M_A_DQ47 M_A_DQ44 M_A_DQ45 M_A_DQ43 M_A_DQ42 M_A_DQ53 M_A_DQ49 M_A_DQ55 M_A_DQ54 M_A_DQ52 M_A_DQ48 M_A_DQ51 M_A_DQ50 M_A_DQ61 M_A_DQ56 M_A_DQ62 M_A_DQ63 M_A_DQ60 M_A_DQ57 M_A_DQ58 M_A_DQ59

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

close to dimm

A A

close to dimm

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 252-GP-U

62.10017.I31

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104 11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198 199

SA0_DIMA

197

SA0

SA1_DIMA

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D35V_S3

M_A_RAS# [5] M_A_WE# [5] M_A_CAS# [5]

M_A_CS#0 [5] M_A_CS#1 [5]

M_A_CKE0 [5] M_A_CKE1 [5]

M_A_CLK0 [5] M_A_CLK#0 [5]

M_A_CLK1 [5] M_A_CLK#1 [5]

PCH_SMBDAT A [13,18, 65,66,67,99] PCH_SMBCLK [13,18,65,6 6,67,99]

3D3V_S0

ESD A00

SA0_DIMA SA1_DIMA

12

R1202

Do Not Stuff

1D35V_S3

12

C1203

SCD1U16V2KX-3GP

Layout Note:

Place these Caps near DIMM1.

0D675V_S0

12

C1214

C1215

SC1U10V2KX-1GP

Note: SA0 DIM0 = 0, SA1_DIM0 = 0

12

SO-DIMMA SPD Address is 0xA0

R1201

Do Not Stuff

SO-DIMMA TS Address is 0x30

12

DY

TC1201

Do Not Stuff

12

C1213

C1212

SC1U10V2KX-1GP

12

C1220

SCD1U16V2KX-3GP

1U 0402 x 3

12

C1216

SC1U10V2KX-1GP

10U 0603 x 3

12

C1207

C1209

C1208

SC10U6D3V3MX-GP

12

C1222

C1221

SCD1U16V2KX-3GP

1U 0402 x 2

0.1U 0402 x 5

12

C1211

C1210

SCD1U16V2KX-3GP

Place these Caps near DIMM1.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, Septem ber 15, 2015

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

DDR3-SODIMM1

Loveland SKL-U

1

12 105

A00

5

4

3

2

1

Main Func = DDR SODIMM

DM2

M_B_A[15:0][5]

D D

M_B_BS2[5] M_B_BS0[5]

M_B_BS1[5]

M_B_DQ[63:0][5]

M_B_DQ[8:15]

M_B_DQ[0:7]

M_B_DQ[16:23]

M_B_DQ[24:31]

M_B_DQ[32:39]

M_B_DQ[40:47]

CD1U16V2KX-3GP

CD1U16V2KX-3GP S

S

Do Not Stuff

12

C1309

CD1U16V2KX-3GP

CD1U16V2KX-3GP S

S

12

C1310

CD1U16V2KX-3GP

CD1U16V2KX-3GP S

S

Layout Note:

Place these caps close to VREF_CA

Layout Note:

Place these caps close to VREF_DQ

M_VREF_CA_D IMMB

12

C1308

C1306

CD1U16V2KX-3GP

CD1U16V2KX-3GP S

S

M_VREF_DQ_D IMMB

C C

12

C1302

DY

1305

1305 C

C

CD1U16V2KX-3GP

CD1U16V2KX-3GP S

S

M_B_DQ[48:55]

M_B_DQ[56:63]

M_B_DQS_DN[7: 0][5]

B B

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

DDR3_DR AMRST#[5,12]

M_B_DQS_DP[7:0][5]

M_B_DIMB_ODT0[5] M_B_DIMB_ODT1[5]

M_VREF_CA_D IMMB M_VREF_DQ_D IMMB

12

C1301

DY

Do Not Stuff

close to dimm

0D675V_S0

DY

D1319

D1319 Do Not Stuff

Do Not Stuff

1 2

close to dimm

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ10 M_B_DQ11 M_B_DQ13 M_B_DQ15 M_B_DQ9 M_B_DQ14 M_B_DQ12 M_B_DQ8 M_B_DQ4 M_B_DQ0 M_B_DQ2 M_B_DQ3 M_B_DQ1 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ31 M_B_DQ25 M_B_DQ29 M_B_DQ27 M_B_DQ24 M_B_DQ28 M_B_DQ26 M_B_DQ30 M_B_DQ33 M_B_DQ36 M_B_DQ34 M_B_DQ39 M_B_DQ37 M_B_DQ32 M_B_DQ35 M_B_DQ38 M_B_DQ45 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ40 M_B_DQ44 M_B_DQ46 M_B_DQ47 M_B_DQ51 M_B_DQ49 M_B_DQ55 M_B_DQ48 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ50 M_B_DQ58 M_B_DQ56 M_B_DQ60 M_B_DQ59 M_B_DQ57 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS_DN1 M_B_DQS_DN0 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

M_B_DQS_DP1 M_B_DQS_DP0 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78 79

109 108

5

7 15 17

4

6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10 27 45 62

135 152 169 186

12 29 47 64

137 154 171 188

116 120

126

1 30

203 204

DM2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA VREF_DQ

RESET#

VTT1 VTT2

DDR3-204P- 259-GP

62.10024.S11

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104 11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198 199

SA0_DIMB

197

SA0

SA1_DIMB

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D35V_S3

M_B_RAS# [5] M_B_WE# [5] M_B_CAS# [5]

M_B_CS#0 [5] M_B_CS#1 [5]

M_B_CKE0 [5] M_B_CKE1 [5]

M_B_CLK0 [5] M_B_CLK#0 [5]

M_B_CLK1 [5] M_B_CLK#1 [5]

PCH_SMBDAT A [12,18, 65,66,67,99] PCH_SMBCLK [12,18,65,6 6,67,99]

3D3V_S0

12

ESD A00

C1311

SCD1U16V2KX-3GP

Layout Note:

Place these Caps near DIMM2.

0D675V_S0

12

C1307

1D35V_S3

SC1U10V2KX-1GP

SA1_DIMB SA0_DIMB

Do Not Stuff

12

C1304

3D3V_S0

12

R1302

R1302 10KR2J-3-GP

10KR2J-3-GP

12

R1301

12

SC1U10V2KX-1GP

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

12

C1317

SC10U6D3V3MX-GP

12

C1322

C1321

SC1U10V2KX-1GP

12

C1315

SCD1U16V2KX-3GP

1U 0402 x 3

C1303

SC1U10V2KX-1GP

10U 0603 x 3

12

C1318

C1323

SC10U6D3V3MX-GP

12

C1314

C1316

SCD1U16V2KX-3GP

1U 0402 x 2

0.1U 0402 x 5

12

C1313

C1312

SCD1U16V2KX-3GP

Place these Caps near DIMM2.

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

DDR3-SODIMM2

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, Septem ber 15, 2015

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Loveland SKL-U

1

13 105

A00

5

D D

4

3

2

1

C C

(Blanking)

B B

Wistron Corporation

A A

Title

(Reserved)_SODIMM _SODIMM4

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Loveland SKL-U

14 105Tuesday, September 15, 2015

1

A00

5

4

3

2

1

Main Func = PCH

CPU1I

SKYLAKE_ULT

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

D D

C C

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-GP-U

071.SKYLA.000U

SKYLAKE_ULT

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

9 OF 20

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

WIFI_RF_EN

DC resistance < 0.5ohm.

CSI2_COMP

WIFI_RF_EN [61]

GPP_F: VCCPGPPF = 1.8V Only

EMMC_RCOMP

1 2

R1501

1 2

R1502

200R2F-L-GP

R1503

12

DY

Do Not Stuff

100R2F-L1-GP-U

3D3V_S0

[#545659 Rev0.7]

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(CS-2/EMMC)

Loveland SKL-U

15 105Tuesday, September 15, 2015

1

A00

Main Func = PCH

5

4

3

2

1

#543016: 220 nF nominal capacitors are recommended for Gen 3. 100 nF nominal capacitors are recommended for Gen 2.

CPU_RXN_C_dGPU_TXN0[73] CPU_RXP_C_dGPU_TXP0[73] dGPU_RXN_C_CPU_TXN0[73] dGPU_RXP_C_CPU_TXP0[73]

CPU_RXN_C_dGPU_TXN1[73]

D D

Layout Note:

C C

B B

CPU_RXP_C_dGPU_TXP1[73] dGPU_RXN_C_CPU_TXN1[73] dGPU_RXP_C_CPU_TXP1[73]

CPU_RXN_C_dGPU_TXN2[73]

GPU

CPU_RXP_C_dGPU_TXP2[73] dGPU_RXN_C_CPU_TXN2[73] dGPU_RXP_C_CPU_TXP2[73]

CPU_RXN_C_dGPU_TXN3[73] CPU_RXP_C_dGPU_TXP3[73] dGPU_RXN_C_CPU_TXN3[73] dGPU_RXP_C_CPU_TXP3[73]

PCIE_RX_CPU_N5[61] PCIE_RX_CPU_P5[61]

WLAN

PCIE_TX_CON_N5[61] PCIE_TX_CON_P5[61]

PCIE_RX_CPU_N6[31] PCIE_RX_CPU_P6[31] PCIE_TX_CON_N6[31]

LAN

PCIE_TX_CON_P6[31]

SATA_RX_CPU_N0[60] SATA_RX_CPU_P0[60]

HDD1

SATA_TX_CPU_N0[60] SATA_TX_CPU_P0[60]

1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) Note: Must maintain low DC resistance routing (<0.1 ohm).

2. Isolation Spacing: At least 12 mils to any adjacent high speed I/O.

R1604

XDP_PRDY#[99]

XDP_PREQ#[99]

3D3V_S0

PCIE Table

Port

Device

Share BUS

USB3.0_3

N/A

1

2

3

4

5(L0~L3)

6(L3)

6(L2)

6(L0~L1)

N/A

WLAN

LAN

GPU

HDD

N/A

USB3.0_4

SATA0

#545659 (SKL_PCH_U_Y_EDS Rev0.7)

C1606

C1606 C1605

C1605

C1608

C1608 C1607

C1607

C1610

C1610 C1609

C1609

C1612

C1612 C1611

C1611

C1601

C1601 C1602

C1602

C1603

C1603 C1604

C1604

1 2

100R2F-L1-GP-U

1 2 1 2

OPS

OPS OPS

OPS

OPS OPS

OPS

OPS OPS

OPS

OPS OPS

OPS

SCD22U10V2KX-1GP

PEG_TX_CPU_N0 PEG_TX_CPU_P0

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

PEG_TX_CPU_N1 PEG_TX_CPU_P1

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

PEG_TX_CPU_N2 PEG_TX_CPU_P2

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

PEG_TX_CPU_N3 PEG_TX_CPU_P3

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

PCIE_TX_CPU_N5 PCIE_TX_CPU_P5

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

PCIE_TX_CPU_N6 PCIE_TX_CPU_P6

SCD1U16V2KX-3GP

PCIE_RCOMPN PCIE_RCOMPP

PIRQA#

R160710KR2J-3-GP R160710KR2J-3-GP

12

USB 2.0 Table

Pair

0

1

2

3

4

5

6

7

Device

USB3.0 port1

USB3.0 Port2

USB2.0 Port3 (IOBD)

Fringer print

CAMERA

Card Reader

Touch Panel

WLAN

CPU1H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKYLAKE-GP-U

071.SKYLA.000U

SKYLAKE_ULT

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

8 OF 20

(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.

H8

USB3_1_RXN

G8

USB3_1_RXP

C13

USB3_1_TXN

D13

USB3_1_TXP

J6 H6 B13 A13

J10 H10 B15 A15

E10

USB3_4_RXN

F10

USB3_4_RXP

C15

USB3_4_TXN

D15

USB3_4_TXP

AB9

USB2N_1

AB10

USB2P_1

AD6

USB2N_2

AD7

USB2P_2

AH3

USB2N_3

AJ3

USB2P_3

AD9

USB2N_4

AD10

USB2P_4

AJ1

USB2N_5

AJ2

USB2P_5

AF6

USB2N_6

AF7

USB2P_6

AH1

USB2N_7

AH2

USB2P_7

AF8

USB2N_8

AF9

USB2P_8

AG1

USB2N_9

AG2

USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

DC resistance < 0.5ohm.

AH7 AH8

USBCOMP

AB6 AG3 AG4

A9 C9 D9 B9

J1

SIO_EXT_SCI#_R

J2 J3

GPP_E0/SATAXPCIE0/SATAGP0

H2

GPP_E1/SATAXPCIE1/SATAGP1

H3

GPP_E2/SATAXPCIE2/SATAGP2

G4 H1

(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND using 8.2 KΩ to 10 KΩ on the motherboard. Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable.

USB30_RX_CPU_N1 [36] USB30_RX_CPU_P1 [36] USB30_TX_CPU_N1 [36] USB30_TX_CPU_P1 [36]

USB30_RX_CPU_N2 [36] USB30_RX_CPU_P2 [36] USB30_TX_CPU_N2 [36] USB30_TX_CPU_P2 [36]

USB_CPU_PN0 [36] USB_CPU_PP0 [36]

USB_CPU_PN1 [36] USB_CPU_PP1 [36]

USB_CPU_PN2 [37] USB_CPU_PP2 [37]

USB_CPU_PN3 [92] USB_CPU_PP3 [92]

USB_CPU_PN4 [55] USB_CPU_PP4 [55]

USB_CPU_PN5 [33] USB_CPU_PP5 [33]

USB_CPU_PN6 [55] USB_CPU_PP6 [55]

USB_CPU_PN7 [61] USB_CPU_PP7 [61]

R1603 113R2F-GPR1603 113R2F-GP

1 2

USB_OC0# [35] USB_OC1# [35] USB_OC2# [35] USB_OC3# [24]

HDD_DEVSLP [60] SIO_EXT_SCI#_R [24] LOM_CABLE_DETECT# [31]

1 1 1

SATA_LED# [64]

USB1 (USB3.0 Port1)

USB2 (USB3.0 Port2)

USB1 (USB3.0 port1)

USB2 (USB3.0 Port2)

USB3 (IO BD/USB2.0 Port3)

Finger Print (USB2.0 Port4)

CAMERA (USB2.0 Port5)

Card Reader (USB2.0 Port6)

Touch Panel (USB2.0 Port7)

WLAN (USB2.0 Port8)

(#543016) When used as DEVSLP, no external pull-up or pull-down termination required from SATA Host DEVSLP.

TP1601 Do Not StuffTP1601 Do Not Stuff TP1602 Do Not StuffTP1602 Do Not Stuff TP1603 Do Not StuffTP1603 Do Not Stuff

USB_OC2# USB_OC0# USB_OC3# USB_OC1#

RN1602

8 7

SRN10KJ-6-GP

3D3V_S5_PCH

1 2 3456

(#543611) The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.

SATA_LED#

LOM_CABLE_DETECT#

SIO_EXT_SCI#_R

R1606

R1609

R1608

12

10KR2J-3-GP

12

10KR2J-3-GP

12

10KR2J-3-GP

3D3V_S0

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(PCIE/SATA/USB)

Loveland SKL-U

1

16 105Tuesday, September 15, 2015

A00

5

4

3

2

1

Main Func = PCH

3D3V_S5

R1709

1 2

10KR2J-3-GP

10KR2J-3-GP R1714

R1714

1 2

10KR2J-3-GP

+VCCPDSW _3P3

D D

C C

R1703

1 2

1KR2J-1-GP

1KR2J-1-GP R1723

R1723

1 2

10KR2J-3-GP

RTC_AUX_S5

R1730

330KR2J-L1-GP

1 2

R1733 10KR2J-3-GPR1733 10KR2J-3-GP R1732 10KR2F-2-GPR 1732 10KR2F-2-GP

R1717 Do Not Stuff

1 2 1 2

12

DY

AC_PRESENT

PCIE_WLAN_W AKE#

PCH_WA KE#

PCH_BATLOW #

#544669 (CRB): 330k.

SM_INTRUDER #

PM_RSMRST# PM_PCH_PW ROK

SYS_PWROK

#544669 Rev0.52 CRB: No PL resistor on THERMTRIP#.

H_CPUPW RGD

EC_WAKE#[24]

DY

R1736

R1736 Do Not Stuff

Do Not Stuff

+V3.3A_SIP

3D3V_S5

Layout note: 3 PAD SHARING

12

R405

R405 Do Not Stuff

Do Not Stuff

1 2

DY

1 2

Do Not Stuff

+VCCMPHYGTAON_1P0

SKL: 1.0V

+VCCMPHYGTAON_1P0(ICCMAX.=3.5A)

+VCCMPHYGTA ON_1P0_LS_SIP1D0V _S5

R1724

1 2

Do Not Stuff

R1735

1 2

Do Not Stuff

B B

12

C1704

C1704 SC10U10V5KX-2G P

SC10U10V5KX-2G P

PCIE_LAN_WA KE#[31]

PCIE_WLAN_W AKE#[61]

For EMI Reserved

EC1710

DY

Do Not Stuff

Layout Note:

close to CPU1

DS3 BOM Option

SUSACK#_RME_SUS_PW R_ACK_R

R1708

1 2

Do Not Stuff

RN1702

SUSACK#_R

1 2

R1726

R1726 10KR2J-3-GP

10KR2J-3-GP

3V_5V_POK#

2 3

DS3

1

Do Not Stuff

R1727

100KR2J-1-GP

1 2

NON DS3

6

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

5

4

Q1701

2345 1

2N7002KDW -GP

ME_SUS_PW R_ACK_R

PM_RSMRST# 3V_5V_POK_C

SUSACK#[24]

ME_SUS_PW R_ACK[24]

3D3V_AUX_S5

A A

1 2 1 2

Do Not Stuff

R1729

R1729 Do Not Stuff

Do Not Stuff

PCH_DPW ROK

1KR2J-1-GP

1KR2J-1-GP R1702

R1702

R1728

DS3

1 2

R1718 D o Not Stuff

1 2

DS3

EC1711

SIO_SLP_SUS#

1 2

12

DY

Do Not Stuff

R1712

DY

R1711

ME_SUS_PW R_ACK_R[20]

GPD2/LAN_W AKE#

2

1

BAW56-9-G P

75.00056.07D

H_CPUPWRGD

EC1713

Do Not Stuff

1 2

R1725

R1725 Do Not Stuff

Do Not Stuff

+VCCPDSW _3P3

Do Not Stuff

XDP_DBRESE T#[99]

H_THERMT RIP_EN[40]

SYS_PWROK[24] RESET_OUT #[24,26,40]

+VCCPDSW _3P3

D1702

3

PM_PCH_PWROK

DY

1 2

3V_5V_POK [40,45,53,54]

EC1712

12

DY

Do Not Stuff

4

+VCCPRIM_3P3

12

R1701

R1701 3KR2J-2-GP

3KR2J-2-GP

PCH_PLTRST #

1 2

DY

1 2

R1704

1 2

Do Not Stuff

1 2 1 2

SIO_SLP_S3#[24,40]

EC1706

PM_RSMRST#[99]

1 2

12

DY

EC1702

Do Not Stuff

R1710 Do Not Stuff

H_VCCST_PW RGD_R

R1706 Do Not StuffR1706 Do Not Stuff

R1705 Do Not StuffR1705 Do Not Stuff R1707 10KR2J-3-GPR1707 10KR2J-3-GP

(PDG#543016) WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.

PCIE_WAKE#

PCH_RSMRS T# [24]

60D4R2F-GP

60D4R2F-GP R1734

R1734

ALL_SYS_PWRG D[24,40]

12

DY

EC1703

12

DY

Do Not Stuff

K A

EC1704

XDP_DBRESE T#

H_CPUPW RGD H_VCCST_PW RGD

SYS_PWROK PM_PCH_PW ROK PCH_DPW ROKPM_RSMRST#

ME_SUS_PW R_ACK_R SUSACK#_R

PCH_WA KE#PCIE_WAKE# GPD2/LAN_W AKE#

1 2

Do Not Stuff

D1701

1N4148WS-7 -F-GP

U1702

NC#1 A GND3Y

12

DY

Do Not Stuff

PLT_RST#[24,31,40,55,61,68,73,91]

DY

Do Not Stuff

VCC

3

12

R1715

DY

CPU1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/USB2_WAKEOUT#

SKYLAKE-GP-U

071.SKYLA.000U

3D3V_S5

5

C1703

Do Not Stuff

12

4

DY

1 2

R1716

R1716 Do Not Stuff

Do Not Stuff

12

EC1709

DY

Do Not Stuff

XDP_DBRESE T#

SYS_PWROK PLT_RST# RESET_OUT #

R1713

1 2

Do Not Stuff

C1701

C1701 Do Not Stuff

Do Not Stuff

SYSTEM POWER MANAGEMENT

U1701

NC#1

VCC A GND3Y

74LVC1G07GW -GP

73.01G07.0HG

DY

PCH_PLTRST #

SCD1U16V2KX-3GP

C1702

5

4

12

DY

SKYLAKE_ULT

3D3V_S5

12

R1719

R1719 Do Not Stuff

Do Not Stuff

AC_PRESENT

EC1707

GPP_B11/EXT_PWR_GATE#

+VCCSTG

12

R1722

R1722 1KR2J-1-GP

1KR2J-1-GP

H_VCCST_PW RGD_R

EC1708

12

DY

Do Not Stuff

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B2/VRALERT#

12

DY

Do Not Stuff

11 OF 20

SLP_SUS#

SLP_LAN#

GPD6/SLP_A#

INTRUDER#

[#543016 Rev0.7] EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k pull-down that is active during the early portion of the power up sequence

SIO_SLP_S0#

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

SIO_SLP_S5#

SLP_LAN# AUX_EN_W OWL_R SIO_SLP_A#

AC_PRESENT PCH_BATLOW #

PME# SM_INTRUDER #

EXT_PWR _GATE# GPP_B2/VRALER T#

3D3V_AUX_S5

1

1 1

1

R1737

1 2

NON DS3

100KR2J-1-GP

TP1703

TP1703 Do Not Stuff

Do Not Stuff TP1704

TP1704 Do Not Stuff

Do Not Stuff TP1706

TP1706 Do Not Stuff

Do Not Stuff

TP1707 Do N ot StuffTP1707 Do Not Stuff

TP1708 Do N ot StuffTP1708 Do Not Stuff

PM_RSMRST#_M

SIO_SLP_S0# [24,27,40,51,52,54] SIO_SLP_S3# [24,27,40,51,52,54]

SIO_SLP_S4# [24,40,51]

SIO_SLP_SUS# [2 4,40,53,54]

R1721

1 2

DY

Do Not Stuff

SIO_PWRBTN # [24,99] AC_PRESENT [76]

Q1702

PM_RSMRST#_R PM_RSMRST#

2345

NON DS3

1

6

2N7002KDW -GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

AUX_EN_W OWL [24,40,53 ,54]

EXT_PWR _GATE#

BATLOW#: Pull-up required even if not implemented.

D1703

D1703 RB751V-40H-G P

RB751V-40H-G P

KA

PWR_CH G_ACOK [24,44]

83.R2004.G8F

AC_PRESENT

R1720

1 2

Do Not Stuff

VCCST_PWRGD / HWM201:

#543016 Rev0.7

1. VCCST_PWRGD is only 1.0 V tolerant.

2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

CPU_(POWER MANAGEMENT)

Size Document Num ber Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Loveland SKL-U

1

R1731

20KR2J-L2-GP

17 105Tuesday, Septem ber 15, 2015

3D3V_S5_PCH

12

A00

SIO_RCIN#

SERIRQ

5

3D3V_S5_PCH

12

DY

PCH strap pin:

eSPI or LPC

SML0ALERT# / GPP_C5

This signal has a weak internal pull-down.

SPI_HOLD_CPU

SPI0_MOSI_XDP[99]

XDP_SPI0_IO2[99]

SPI_WP_ROM[25]

SPI_HOLD_ROM[25] SPI_CS_ROM_N0[24,25] SPI_CS_ROM_N1[25]

HDD_FALL_INT[67]

HDD_PW R_EN[67]

CL_CLK[61] CL_DATA[61]

CL_RST#[61]

R1835

R1835 1KR2J-1-GP

1KR2J-1-GP

R1836

R1836 Do Not Stuff

Do Not Stuff

Sampled at rising edge of RSMRST# This signal has a weak internal pull-down.

0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.

PLACE WITHIN 1.1 INCH OF PCH

Resister value will check later

SPI_CLK_ROM[24,25,91]

SPI_SO_ROM[24,25,91]

SPI_SI_ROM[24,25,91]

SPI_CS2#_R[91]

SIO_RCIN#[24]

SERIRQ[24]

R1826

1 2

DY

Do Not Stuff

R1827

1 2

DY

Do Not Stuff

R180610R2F- L-GP R 180610R2F-L -GP

1 2

R180710R2F- L-GP R 180710R2F-L -GP

1 2

R180810R2F- L-GP R 180810R2F-L -GP

1 2

R180910R2F- L-GP R 180910R2F-L -GP

1 2

R181110R2F- L-GP R 181110R2F-L -GP

1 2

R1812Do Not Stuff R 1812D o Not Stuff

1 2

R1828Do No t Stuff

1 2

DY

R1816Do Not Stuff R 1816D o Not Stuff

1 2

Do Not Stuff

12

EC1805

DY

Main Func = PCH

D D

3D3V_S5_PCH

12

R1834

R1834 1KR2J-1-GP

1KR2J-1-GP

SPI_WP_CPU

3D3V_S0

R2021

1 2

10KR2J-3-GP

R2032

1 2

10KR2J-3-GP

SERIRQ PH: PDG: 8.2k CRB: 10k

C C

RCIN#: Frequency to Avoid: 33 MHz

4

PCH Prim

3D3V_S5_PCH

12

R1822

DY

Do Not Stuff

GPP_C5/SML0ALER T#

(#543016)Optional, can be left as OPEN/No-Connect.

SPI_SI_CPU

SPI_WP_CPU

SPI_CLK_CPU SPI_SO_CPU SPI_SI_CPU SPI_WP_CPU SPI_HOLD_CPU SPI_CS_CPU_N0 SPI_CS_CPU_N1 PCH_SPI_CS2#

CPU_D1_TP

TP1801Do Not S tuff TP1801Do Not Stuff

1

CPU_D4_TP

TP1804Do Not S tuff TP1804Do Not Stuff

1

CPU_D5_TP

TP1805Do Not S tuff TP1805Do Not Stuff

1

CPU_D6_TP

TP1806Do Not S tuff TP1806Do Not Stuff

1

12

R1823

DY

Do Not Stuff

CPU1E

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

SPI - TOUCH

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

C LINK

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

SKYLAKE-GP-U

071.SKYLA.000U

SPI - FLASH

Strap

PCH strap pin:

BOOT HALT

SPI0_MOSI

This signal has a weak internal pull-up.

0 = ENABLED 1 = DISABLED WEAK INTERNAL PU

SKYLAKE_ULT

LPC

SMBUS, SMLINK

GPP_A14/SUS_STAT#/ESPI_RESET#

3

LPC_LAD[3..0][24,68]

5 OF 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

Strap

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

Strap

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

SPI_SI_CPU

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

PCH Prim

LPC_LAD[3..0]

MEM_SMBCLK MEM_SMBDATA GPP_C2/SMBALER T#

SML0_SMBCLK SML0_SMBDATA GPP_C5/SML0ALER T#

GPP_B23/SML1ALERT #

LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R LPC_LFRAME#_R SUS_STAT#/LPC PD#

PCI_CLK_LPC0 PCI_CLK_LPC1 CLKRUN#_R

3D3V_S5_PCH

12

R1824

DY

Do Not Stuff

12

R1825

DY

Do Not Stuff

LPC_LAD0 LPC_LAD2 LPC_LAD1 LPC_LAD3

1 2

Do Not Stuff

8 7 6

SML1_SMBCLK [24,26,76] SML1_SMBDATA [24,26,76]

R1801

12

Do Not Stuff

R1819

2

PCH strap pin:

No Reboot

SMBALERT# / GPP_C2

The signal has a weak internal pull-down.

RN1806

SRN0J-7-GP -U

Sampled at rising edge of PCH_PWROK

0 = Disable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no confidentiality). 1 = Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Must be pulled up to support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

LPC_LAD0_R

1

LPC_LAD2_R

2

LPC_LAD1_R

3

LPC_LAD3_R

45

SUS_STAT#/LPC PD#

CLKRUN#_R

LPC_LFRAME# [24,68]

CLKRUN# [24]

PCI_CLK_LPC0 PCI_CLK_LPC1

20140820 DAIVD

3D3V_S5_PCH

R1814

12

DY

Do Not Stuff

3D3V_S0

R1818

8K2R2F-1-GP

1 2

MEM_SMBDATA

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

MEM_SMBCLK

R1804 Do Not Stuff

1 2

LPC

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

84.2N702.A3F

12

DY

1

3D3V_S5_PCH

RN1807

SML1_SMBDATA SML1_SMBCLK SML0_SMBDATA SML0_SMBCLK

GPP_B23/SML1ALERT #

GPP_C2/SMBALER T#

MEM_SMBCLK MEM_SMBDATA

3D3V_S0

2N7002KDW -GP

1

6

2345

Q1801

CLK_PCI_LPC [68] CLK_PCI_LPC_MEC [24]

EC1801

EC1802

Do Not Stuff

12

DY

RN1807

8 7 6

SRN2K2J-4-G P

R1820

R1821

1 2

SRN2K2J-1-G P

4

RN1811

RN1810

4

SRN10KJ-5-G P

1 2 3 45

150KR2F-L-GP

12

2K2R2J-2-GP

23 1

23

3D3V_S0

1

PCH_SMBDAT A [12,13 ,65,66,67,99]

PCH_SMBCLK [12,13,65,6 6,67,99]

3D3V_S0

CLKREQ_PEG#0

R1817

1 2

10KR2J-3-GP

CLKREQ_PCIE#1

R1829

B B

A A

1 2

10KR2J-3-GP

R1830

1 2

10KR2J-3-GP

R1831

1 2

10KR2J-3-GP

R1832

1 2

10KR2J-3-GP

R1833

1 2

10KR2J-3-GP

GPU WLAN

LAN

CLKREQ_PCIE#2 CLKREQ_PCIE#3 CLKREQ_PCIE#4 CLKREQ_PCIE#5

PEG_CLK1_CPU #[61] PEG_CLK1_CPU[61]

CLKREQ_PCIE#1[6 1]

PEG_CLK2_CPU #[31] PEG_CLK2_CPU[31]

CLKREQ_PCIE#2[3 1]

5

C1804

SC5P50V2CN- 2GP

CPU1J

CLK_PCIE_VGA#[73] CLK_PCIE_VGA[73] CLKREQ_PEG#0[73]

CLKREQ_PCIE#1

CLKREQ_PCIE#3

CLKREQ_PCIE#4

CLKREQ_PCIE#5

AR10

AT10

AU8

AU7

4

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

SKYLAKE-GP-U

071.SKYLA.000U

CLOCK SIGNALS

SKYLAKE_ULT

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

10 OF 20

XTAL24_IN

XTAL24_OUT

RTCX1 RTCX2

SRTCRST#

RTCRST#

SC5P50V2CN- 2GP

F43 E43

SUSCLK_R

BA17

XTAL24_IN

E37

XTAL24_OUT

E35

XCLK_BIASREF

E42

RTC_X1

AM18

RTC_X2

AM20

SRTC_RST #

AN18

RTC_RST#

AM16

3

1 2

R1815 10M R2J-L-GPR 1815 10MR 2J-L-GP

X1802

4 1

12

XTAL-32D768KH Z-68-GP

82.30001.G01

R1813

1 2

Do Not Stuff

R1803

1 2

2K7R2F-GP

Intel recommend: 2.71k ohm 5%

RTCRST_O N[24]

+VCCF24NS _1P0_L

Do Not Stuff

RTC_X1 RTC_X2

12

C1803

C1803 SC5P50V2CN- 2GP

SC5P50V2CN- 2GP

23

PCIE_CLK_XDP_N [99] PCIE_CLK_XDP_P [99]

SUS_CLK [24]

+V1.05S_AXCK_LCPLL

Q1901

G

12

R1902

10KR2J-3-GP

12

EC1808

DY

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

D

(#514849)

XTAL24_IN XTAL24_IN_R

XTAL24_OUT

21

12

G1901

Do Not Stuff

C1901

SC1U10V2KX-1GP

RTC_AUX_S5

1

23

4

12

1 2

12

R1802

R1802 1MR2J-1-GP

1MR2J-1-GP

RN1901

RN1901 SRN20KJ-1-G P

SRN20KJ-1-G P

C1902

C1902 SC1U10V2KX-1G P

SC1U10V2KX-1G P

R1810

R1810 Do Not Stuff

Do Not Stuff

SUSCLK_R

23

12

EC1806

DY

Layout: Place at the open door area.

2

4 1

SRTC_RST # RTC_RST#

Do Not Stuff

12

DY

C1801

SC15P50V2JN-2- GP

X1801

X1801 XTAL-24MHZ- 81-GP

XTAL-24MHZ- 81-GP

82.30004.841

C1802

SC15P50V2JN-2- GP

EC1803

DY

1 2

Do Not Stuff

EC1807

12

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

CPU_(LPC/SPI/SMBUS/CL/CLK)

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Loveland SKL-U

1

18 105Tuesday, Septem ber 15, 2015

A00

5

Main Func = PCH

PCH strap pin:

4

3

2

1

D D

C C

B B

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

Low = Default High = Enable

*

The internal pull-down is disabled after PLTRST# deasserts

DMIC_PCH_CLK[55] DMIC_PCH_DATA[55]

DGPU_PWROK[24,82,83]

PCH strap pin:

NO REBOOT

Low = Enable (Default)

HDA_SPKR

The internal pull-down is disabled after PLTRST# deasserts

*

High = Disable

CPU1G

AUDIO

HDA_SYNC HDA_BITCLK HDA_SDOUT

HDA_SDIN0[27]

HDA_RST#

Do Not Stuff

R1910

R1910 R1913

R1913

SPKR[27]

Do Not Stuff

1 2

DY

1 2

DY

Do Not Stuff

DMIC_PCH_CLK_R DMIC_PCH_DATA_R

DGPU_PWROK

SPKR

3D3V_S0

R2006 Do Not Stuff

R1904 Do Not Stuff

EC1901 Do Not Stuff

EC1902 Do Not Stuff

EC1903 Do Not Stuff

BA22 AY22 BB22 BA21 AY21

AW22

J5

AY20

AW20

AK7 AK6 AK9

AK10

H5 D7

D8 C8

AW5

1 2

DY

1 2

UMA

1 2

DY

12

DY

12

DY

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKYLAKE-GP-U

071.SKYLA.000U

SPKR

DGPU_PWROK

HDA_CODEC_BITCLK

HDA_CODEC_RST#

DGPU_PWROK

SKYLAKE_ULT

SDIO/SDXC

GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

HDA_CODEC_BITCLK[27] HDA_CODEC_SYNC[27] HDA_CODEC_RST#[27]

HDA_CODEC_SDOUT[27]

7 OF 20

GPP_G0/SD_CMD

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

ME_FWP_EC[24,98]

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9

CPU_A16_TP

BB9

SD_RCOMP

AB7

AF13

R1907 33R2J-2-GPR1907 33R2J-2-GP R1908

R1908 R1911

R1911

R1912 33R2J-2-GPR1912 33R2J-2-GP R1909 1KR2J-1-GPR1909 1KR2J-1-GP

R1901

1 2

200R2F-L-GP

1 2 1 2

Do Not Stuff

1 2

Do Not Stuff

1 2 1 2

KB_LED_BL_DET [65]

TP1902

1

Do Not Stuff

HDA_BITCLK HDA_SYNC HDA_RST#

HDA_SDOUT

Wistron Corporation

A A

Title

CPU_(AUDIO/SDIO/SDXC)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

CPU_(AUDIO/SDIO/SDXC)

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Loveland SKL-U

19 105Tuesday, September 15, 2015

1

A00

5

Main Func = PCH

EC2002

12

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP RN2009

D D

C C

RN2009

1 2 3

OPS

SRN10KJ-5-GP

3D3V_S0

R2002 Do Not Stuff

1 2

DY

R2043 10KR2J-3-GPR2043 10KR2J-3-GP

1 2

R2044 10KR2J-3-GPR2044 10KR2J-3-GP

1 2

R2047 10KR2J-3-GPR2047 10KR2J-3-GP

1 2

R2050 Do Not Stuff

1 2

DY

R2051 10KR2J-3-GPR2051 10KR2J-3-GP

1 2

3D3V_S5_PCH

R2039 Do Not Stuff

1 2

DY

R2040 10KR2J-3-GPR2040 10KR2J-3-GP

1 2

R2041 10KR2J-3-GPR2041 10KR2J-3-GP

1 2

DGPU_HOLD_RST#

4

DGPU_PWR_EN

R204851KR2J-1-GP R204851KR2J-1-GP

12

R204951KR2J-1-GP R204951KR2J-1-GP

12

R204651KR2J-1-GP R204651KR2J-1-GP

12

R200910KR2J-3-GP R200910KR2J-3-GP

12

DGPU_HOLD_RST# [73]

LPSS_UART2_RXD LPSS_UART2_TXD

LPSS_UART2_CTS#

KB_DET#

BLUETOOTH_EN

DBC_PANEL_EN HDD_DET# LCD_CBL_DET# SD_READ_MODE# IR_CAMERA_DET#

RTC_DET# SIO_EXT_WAKE#

PCH strap pin:

No Reboot

GSPI1_MOSI / GPP_B22

The signal has a weak internal pull-down.

GPU_EVENT#[76]

GC6_FB_EN[75,76,83]

ME_SUS_PWR_ACK_R [17]

Sampled at rising edge of PCH_PWROK

This field determines the destination of accesses to the BIOS memory range. Also controllable using Boot BIOS Destination bit (Chipset Configuration Registers: Offset 3410h:Bit 10). This strap is used in conjunction with Boot BIOS Destination Selection 0 strap.

PCH Prim

3D3V_S5_PCH

PCH strap pin:

No Reboot

GSPI0_MOSI / GPP_B18

The signal has a weak internal pull-down.

B B

For debug USB/UART:

LPSS_UART2_CTS#

1

TP2009

TP2009 Do Not Stuff

Do Not Stuff

Sampled at rising edge of PCH_PWROK

0 = Disable “No Reboot” mode. 1 = Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

5V_S5

LPSS_UART2_TXD LPSS_UART2_RXD

ACES-CON4-37-GP

DB2

1 2

3 4

56

20.F1897.004

4

Bit 10 Boot BIOS Destination

0 SPI 1 LPC

R2003 Do Not Stuff

1 2

GC6_20

R2004 Do Not Stuff

1 2

GC6_20

DBC_PANEL_EN[55]

SD_READ_MODE#[66]

BLUETOOTH_EN[61]

LCD_CBL_DET#[55]

SIO_EXT_WAKE#[55]

PTP

12

DY

12

DY

I2C0_SDA_TCH_PAD[65] I2C0_SCL_TCH_PAD[65]

R2007

R2007 Do Not Stuff

Do Not Stuff

GPP_B18/GSPI0_MOSI

R2019

R2019 Do Not Stuff

Do Not Stuff

HDD_DET#[60]

GPU_EVENT_MCP# GC6_FB_EN_MCP VRAM_ID1

GPP_B18/GSPI0_MOSI

BOARD_ID2

LPSS_UART2_RXD LPSS_UART2_TXD

LPSS_UART2_CTS#

R2015

10KR2J-3-GP

Loveland

PROJECT_ID1

R2016

Do Not Stuff

Iris2

BOARD_ID2

CPU1F

LPSS ISH

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKYLAKE-GP-U

071.SKYLA.000U

3D3V_S0 3D3V_S0

OPS

3D3V_S0

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

R2017

Do Not Stuff

PROJECT_ID2

R2018

Do Not Stuff

BIOS strap pin:

BIOS UMA/DIS Strap pin

UMA

12

R2008

R2008 Do Not Stuff

Do Not Stuff

DIS

3

(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up to the same voltage rail as the device/end point.

SKYLAKE_ULT

Strap

SKYLAKE_ULT

GPP_D13/ISH_UART0_RXD/SML0BDATA

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_D9/ISH_SPI_CS#

GPP_D10/ISH_SPI_CLK GPP_D11/ISH_SPI_MISO GPP_D12/ISH_SPI_MOSI

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D14/ISH_UART0_TXD/SML0BCLK

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

BIOS strap pin:

3D3V_S0

N16V-GM

PROJECT_ID2

0

12

R2025

R2025 10KR2J-3-GP

10KR2J-3-GP

12

R2026

R2026 Do Not Stuff

Do Not Stuff

12

DY

12

DY

BIOS VRAM Size Strap pin

Iris2

Loveland

Tulip

GPP_C11 GPP_A21

BOARD_ID2

BOARD_ID3

0

1

N15V-GM

2

6 OF 20

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

GPP_A18GPP_A19

PROJECT_ID1

0

10

00

BIOS strap pin:

BIOS UMA/DIS Strap pin

N15V-GM-S

N16V-GM

USB_UART_SEL_D9

DGPU_HOLD_RST# RTC_DET# I2C0_SDA

I2C0_SCL

I2C1_SDA I2C1_SCL

1.8V Only

UART0_TXD UART0_RTS# UART0_CTS#

UART1_RXD UART1_RTS#

UART1_CTS# PROJECT_ID1

PROJECT_ID2

(PDG#543016) If the UART/GPIO functionality is also not used, the signals can be left as no-connect.

BOARD_ID3 VRAM_ID2

TP2006 Do Not StuffTP2006 Do Not Stuff

1

TP2012 Do Not StuffTP2012 Do Not Stuff

1

TP2013 Do Not StuffTP2013 Do Not Stuff

1

TP2014 Do Not StuffTP2014 Do Not Stuff

1

TP2015 Do Not StuffTP2015 Do Not Stuff

FFS_INT2 [67]

1

TP2016 Do Not StuffTP2016 Do Not Stuff

1

TP2017 Do Not StuffTP2017 Do Not Stuff

KB_DET# [65]

PANEL_SIZE_ID [55]

BOARD_ID3

0

1

IR_CAMERA_DET# [20]

I2C0_SCL I2C0_SDA

I2C1_SCL I2C1_SDA

1 2 3

RTC_DET# [25]

DGPU_PWR_EN [82,83]

Do Not Stuff

Do Not Stuff RN2007

RN2007

4

DY

RN2008

4

DY

Do Not Stuff

1

3D3V_S0

Intel has removed EHCI controller from BDW and proposed to use UART interface for Win7 debug.

12

R2033

VRAM_4G

A A

5

4

VRAM_ID2

VRAM_1G / 2G

R2033 Do Not Stuff

Do Not Stuff

12

R2034

R2034 10KR2J-3-GP

10KR2J-3-GP

VRAM_ID1

VRAM_1G / 4G

VRAM_2G

3

3D3V_S03D3V_S0

12

R2023

R2023 10KR2J-3-GP

10KR2J-3-GP

12

R2024

Do Not Stuff

BIOS strap pin:

BIOS VRAM Size Strap pin

1G

2G

4G

VRAM_ID2

0

GPP_B17GPP_A23

VRAM_ID1

0

10

01

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

CPU_(LPSS/ISH)

Taipei Hsien 221, Taiwan, R.O.C.

Loveland SKL-U

1

20 105Tuesday, September 15, 2015

A00

5

Main Func = PCH

4

3

2

1

+VCCPRIM_1P0

D D

+VCCPRIM_CORE

2.57A

C2120

12

S

S C1U10V2KX-1GP

C1U10V2KX-1GP

C C

+VCCMPHYAON_1P0

+VCCMPHYGTAON_1P0_LS_SIP

+VCCDSW _1P0

+VCCAMPHYPLL_1P0

+VCCAPLL_1P0

+V1.00A_SIP

+VCCPDSW_3P3

+VCCPAZIO

+VCCPSPI

+VCCSRAM_1P0

+VCCPRIM_3P3 +VCCFHV

+VCCAPLLEBB_1P0

CPU1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKYLAKE-GP-U

071.SKYLA.000U

CPU POWER 4 OF 4

SKYLAKE_ULT

1.8V Only

15 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19 T1 AA1 AK17 AK19

BB14 BB10 A14 K19 L21 N20 L19 A10 AN11

AN13

+VCCPGPPA +VCCPGPPB +VCCPGPPC +VCCPGPPD +VCCPGPPE +VCCPGPPF +VCCPGPPG

+VCCPRIM_3P3 +VCCDTS_1P0 +V1.8A_SIP

+VCCPRTCPRIM_3P3

VCCRTCEXT

+VCC19P2_1P0 +VCCF100_1P0_L +VCCF135_1P0 +VCCF100OC_1P0_L +VCCF24NS_1P0_L +VCC24TBT_1P0

V0.85A_VID0 V0.85A_VID1

+VCCPRTC_3P3

C2112 SCD1U16V2KX-3GPC2112 SCD1U16V2KX-3GP

1 2

TP2101 Do Not StuffTP2101 Do Not Stuff

1

TP2102 Do Not StuffTP2102 Do Not Stuff

1

RTC_AUX_S5

Do Not Stuff

R2106

1 2

+VCCPRTC_3P3

RTC_AUX_S5

C2118

C2119

SCD1U16V2KX-3GP

Do Not Stuff

12

DY

12

C2117

SC1U10V2KX-1GP

CAP need close to VCCRTC

B B

A A

+VCCPRIM_1P0 +VCCPRIM_CORE

C

C 2101

2101

Do Not Stuff

DY

12

DY

5

+VCCDSW _1P0

C2102

Do Not Stuff

12

+VCCMPHYAON_1P0

C2103

SC1U10V2KX-1GP

12

+VCCF100_1P0_L

SC22U6D3V3MX-1-GP

C2113

12

C2104

SC1U10V2KX-1GP

12

+VCCPRIM_3P3

C2105

12

+VCCF24NS_1P0_L

SC22U6D3V3MX-1-GP

C2115

12

4

+VCCPGPPC +VCCPGPPE

C2106

SC1U10V2KX-1GP

C2106

12

+VCCF100OC_1P0_L

SC22U6D3V3MX-1-GP

12

SC1U10V2KX-1GP

C2114

+V1.8A_SIP

+VCCPRTCPRIM_3P3

C2107

SC1U10V2KX-1GP

12

C2108

SC1U10V2KX-1GP

12

C2109

SC1U10V2KX-1GP

12

C2110

SCD1U16V2KX-3GP

3

12

C2111

SCD1U16V2KX-3GP

+VCC24TBT_1P0

C2116

12

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(POWER1)

Loveland SKL-U

21 105Tuesday, September 15, 2015

1

A00

5

4

3

2

1

Main Func = PCH

D D

CPU1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

SKYLAKE-GP-U

C C

SKYLAKE-GP-U

071.SKYLA.000U

SKYLAKE_ULT

SPARE

20 OF 20

RSVD_F6

RSVD_E3

RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12

RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

B B

Wistron Corporation

A A

Title

CPU_(RSVD)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU_(RSVD)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Loveland SKL-U

22 105Tuesday, September 15, 2015

1

A00

5

4

3

2

1

Main Func = PCH

CPU1P

GND 1 OF 3

Do Not Stuff

1 1

Do Not Stuff

NCTF_A5 NCTF_A70

TP2307

D D

TP2301

C C

B B

GND 1 OF 3

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

VSS

AE68

VSS

AE69

VSS

AF1

VSS

AF10

VSS

AF15

VSS

AF17

VSS

AF2

VSS

AF4

VSS

AF63

VSS

AG16

VSS

AG17

VSS

AG18

VSS

AG19

VSS

AG20

VSS

AG21

VSS

AG71

VSS

AH13

VSS

AH6

VSS

AH63

VSS

AH64

VSS

AH67

VSS

AJ15

VSS

AJ18

VSS

AJ20

VSS

AJ4

VSS

AK11

VSS

AK16

VSS

AK18

VSS

AK21

VSS

AK22

VSS

AK27

VSS

AK63

VSS

AK68

VSS

AK69

VSS

AK8

VSS

AL2

VSS

AL28

VSS

AL32

VSS

AL35

VSS

AL38

VSS

AL4

VSS

AL45

VSS

AL48

VSS

AL52

VSS

AL55

VSS

AL58

VSS

AL64

VSS

SKYLAKE-GP-U

071.SKYLA.000U

SKYLAKE_ULT

16 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

TP2302

TP2302 TP2305

TP2305

TP2306

Do Not Stuff

NCTF_B71

1

NCTF_BA1

1

Do Not Stuff

NCTF_BA2

1

Do Not Stuff

CPU1Q

GND 2 OF 3

AT63

VSS

AT68

VSS

AT71

VSS

AU10

VSS

AU15

VSS

AU20

VSS

AU32

VSS

AU38

VSS

AV1

VSS

AV68

VSS

AV69

VSS

AV70

VSS

AV71

VSS

AW10

VSS

AW12

VSS

AW14

VSS

AW16

VSS

AW18

VSS

AW21

VSS

AW23

VSS

AW26

VSS

AW28

VSS

AW30

VSS

AW32

VSS

AW34

VSS

AW36

VSS

AW38

VSS

AW41

VSS

AW43

VSS

AW45

VSS

AW47

VSS

AW49

VSS

AW51

VSS

AW53

VSS

AW55

VSS

AW57

VSS

AW6

VSS

AW60

VSS

AW62

VSS

AW64

VSS

AW66

VSS

AW8

VSS

AY66

VSS

B10

VSS

B14

VSS

B18

VSS

B22

VSS

B30

VSS

B34

VSS

B39

VSS

B44

VSS

B48

VSS

B53

VSS

B58

VSS

B62

VSS

B66

VSS

B71

VSS

BA1

VSS

BA10

VSS

BA14

VSS

BA18

VSS

BA2

VSS

BA23

VSS

BA28

VSS

BA32

VSS

BA36

VSS

F68

VSS

BA45

VSS

SKYLAKE-GP-U

071.SKYLA.000U

SKYLAKE_ULT

17 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

NCTF_BA71

Do Not Stuff

NCTF_BB70 NCTF_C1

Do Not Stuff

1

Do Not Stuff

1 1

TP2303

TP2304

TP2304 TP2308

TP2308

CPU1R

GND 3 OF 3

F8

VSS

G10

VSS

SKYLAKE_ULT

G22 G43 G45 G48

G52 G55 G58

G60 G63 G66

H15 H18 H71

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71

J11 J13 J25 J28 J32 J35 J38 J42

L11 L16 L17

SKYLAKE_ULT

VSS VSS VSS VSS

G5

VSS VSS VSS VSS

G6

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKYLAKE-GP-U

071.SKYLA.000U

18 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(VSS)

Loveland SKL-U

1

23 105Tuesday, September 15, 2015

A00

5

Main Func = KBC

1D0V_S 5

R2402

1 2

Do Not Stuff

+VCCSTG

R2440

1 2

DY

Do Not Stuff

+V1.00U_C PU

R2492

1 2

DY

Do Not Stuff

D D

3D3V_S 5_KBC

C C

B B

A A

Layout Note:

Need very close to EC

RN2412

KSI0

1

8

KSI3

2

7

KSI1

3

6

KSI5

4 5

SRN10KJ -6-GP

RN2411

KSI2

1

8

KSI4

2

7

KSI6

3

6

KSI7

4 5

SRN10KJ -6-GP

RN2410

KSO6

1

8

KSO7

2

7

KSO4

3

6

KSO5

4 5

SRN100K J-5-GP

RN2409

KSO2

1

8

KSO1

2

7

KSO3

3

6

KSO8

4 5

SRN100K J-5-GP

R2422

I_SYS

12

330R2J -3-GP

12

2427

2427 C

C

SC2200P50V2KX-2GP

EC_AGND

R2423

I_BATT

12

330R2J -3-GP

12

2441

2441 C

C

Need very close to EC

SC2200P50V2KX-2GP

EC_AGND

Power Switch Logic(PSL)

KBC_PW RBTN#[6 4]

EC_GPIO47 High Active

CMP_VOUT 1

12

R2417

Do Not Stuff

DY

3D3V_S 5_KBC

EC2401

R2510

C2402

P_SYS [44,46]

boost_m on [44]

Layout Note:

R2432

1 2

1KR2J-1 -GP

G

S

1 2 3 4 5

SRN100K J-5-GP

1 2 3 4 5

SRN100K J-5-GP

R2418

R2418 Do Not Stuff

Do Not Stuff

1 2

DY

Q2408

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

3D3V_S 5 3D3V_S 5_KBC

12

SCD1U16V2KX-3GP

3D3V_S 5_KBC

1 2

DY

1 2

LED_SA TA_DIA G_OUT#[64]

POWER _SW_I N#

C2426

12

SC1U10V 2KX-1GP

R2416

1 2

Do Not Stuff

12

C2415

DY

Do Not Stuff

R2450

R2450 100KR2 J-1-GP

100KR2 J-1-GP

R2449

R2449 Do Not Stuff

Do Not Stuff

CLK_PC I_LPC_ MEC[1 8]

SPI_CS _ROM_N0[18,25 ]

ME_SUS_PW R_AC K[17]

PM_LAN_ENA BLE[3 1] AUX_EN_W OWL[31]

ALL_SYS _PWRG D[1 7,40]

3D3V_S 5

12

C2411

C2420

C2412

SCD1U16V2KX-3GP

KSO[0..16 ][65]

KSI[0..7][65]

CLK_TP _SIO[65] DAT_TP _SIO[65] SIO_PW RBTN#[17,99]

PCH_RSMRS T#[17 ]

LPC_LA D[3..0][18,68]

LPC_LF RAME#[18,68 ]

PLT_RS T#[17,31,40,55,6 1,68,73,9 1]

CLKRUN#[18]

SERIRQ[18]

TP_EN#[65] SIO_RC IN#[1 8]

R2485 10R2F-L-G PR2485 10 R2F-L-GP

SPI_CL K_ROM[18,25,91]

R2486 10R2F-L-G PR2486 10 R2F-L-GP

SPI_SI _ROM[18,25,9 1]

R2487 10R2F-L-G PR2487 10 R2F-L-GP

SPI_SO _ROM[18,25,91]

RTCRST _ON[18]

SIO_SL P_S4#[17,40,51]

AC_DIS[43]

PCH_ALW _ON[41]

INT_TP#[4,65]

R2401 Do Not Stuff

RESET_ OUT#[17,26,40]

DY

SUS_CLK[18]

12

C2403

C2403 Do Not Stuff

Do Not Stuff

R2428 Do Not Stuff

1 2

H_PROCHOT # [4,43 ,44,46]

EC_VTT

12

C2406

SCD1U16V2KX-3GP

12

C2421

SCD1U16V2KX-3GP

EC_AGND

RN2403

KSO10

8

KSO11

7

KSO14

6

KSO13

RN2404

KSO15

8

KSO16

7

KSO12

6

KSO0

DGPU_PW ROK

12

DY

Do Not Stuff

CLKRUN#

12

DY

Do Not Stuff

PCH_PLT RST#_E C

1 2

DY

Do Not Stuff

Layout Note:

Need very close to EC

ALL_SYS_PWRGD a ssert, delay 10ms; RES ET_OUT# assert .

ECVBAT

H_PROCHOT #_EC

D

R2451

R2451 100KR2 J-1-GP

100KR2 J-1-GP

1 2

C2416

R2446

1 2

Do Not Stuff

12

C2410

C2414

SCD1U16V2KX-3GP

CAP_LE D#

PCH_PLT RST#_E C

R2410

12

Do Not Stuff

1 2 1 2 1 2

R2490

1 2

Do Not Stuff

R2431 D o Not StuffR24 31 Do Not S tuff

1 2

R2491 Do Not StuffR2491 Do Not S tuff

12 12

DY

R2481 Do Not StuffR2481 Do Not S tuff

12

DY

X2401

1 2

XTAL-32 D768KHZ -83-GP

082.30003.0131

C2425

C2425 SC10P5 0V2JN-4G P

SC10P5 0V2JN-4G P

Microchip: Use CL=9p Xtal，C = 10p

12

C2413

SCD1U16V2KX-3GP

SCD1U16 V2KX-3G P

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

LPC_LA D0 LPC_LA D1 LPC_LA D2 LPC_LA D3

SIO_EX T_SMI# TP_EN#

SIO_EX T_SCI#

EC_SPI _CLK EC_SPI _MOSI EC_SPI _MISO

EC_SPI _CS0#

XTAL2 XTAL1

3D3V_S 5_KBC

4

If don't need RTC alarm wake up, can change to 3D3V_AUX_S5

12

C2417

DY

Do Not Stuff

C2428

PTP_INT #_EC LAN_EN

USB_EN# RUNPWRO K

R2458

R2458 Do Not Stuff

Do Not Stuff

1 2

XTAL_K BC_2

1 2

3D3V_S 5_KBC

R2478

R2478 Do Not Stuff

Do Not Stuff

DB3

DY

R2414

1 2

Do Not Stuff

HOST_DE BUG_TX E51_TX D_R

RTC_AUX _S53D3V_AUX_S5

R2472

DY

Do Not Stuff

1 2

ECVBAT

12

KBC24

2

GPIO027/KSO00/PVT_IO1

14

GPIO015/KSO01/PVT_CS#

15

GPIO016/KSO02/PVT_SCLK

16

GPIO017/KSO03/PVT_IO0

37

GPIO045/BCM_INT1#/KSO04

38

GPIO046/BCM_DAT1/KSO05

39

GPIO047/BCM_CLK1/KSO06

50

GPIO025/KSO07/PVT_IO2

46

GPIO055/PWM2/KSO08/PVT_IO3

68

GPIO102/KSO09/CR_STRAP

72

GPIO106/KSO10

74

GPIO110/KSO11

75

GPIO111/KSO12

76

GPIO112/PS2_CLK1A/KSO13

77

GPIO113/PS2_DAT1A/KSO14

86

GPIO125/KSO15

92

GPIO132/KSO16

93

GPIO140/KSO17

98

GPIO143/KSI0/DTR#

99

GPIO144/KSI1/DCD#

6

GPIO005/SMB00_DATA/SMB00_DATA18/KSI2

7

GPIO006/SMB00_CLK/SMB00_CLK18/KSI3

104

GPIO147/KSI4/DSR#

105

GPIO150/KSI5/RI#

107

GPIO151/KSI6/RTS#

108

GPIO152/KSI7/CTS#

78

GPIO114/PS2_CLK0

79

GPIO115/PS2_DAT0

52

GPIO026/PS2_CLK1B

88

GPIO127/PS2_DAT1B

59

GPIO040/LAD0

60

GPIO041/LAD1

61

GPIO042/LAD2

62

GPIO043/LAD3

58

GPIO044/LFRAME#

56

GPIO064/LRESET#

57

GPIO034/PCI_CLK

63

GPIO067/CLKRUN#

55

GPIO063/SER_IRQ

10

GPIO011/SMI#/EMI_INT#

49

GPIO060/KBRST

53

GPIO061/LPCPD#

66

GPIO100/EC_SCI#

32

GPIO126/SHD_SCLK

28

GPIO133/SHD_IO0

29

GPIO134/SHD_IO1

30

GPIO135/SHD_IO2

31

GPIO136/SHD_IO3

27

GPIO123/SHD_CS#

67

GPIO101/SPI_CLK

69

GPIO103/SPI_IO0

71

GPIO105/SPI_IO1

42

GPIO052/SPI_IO2

33

GPIO062/SPI_IO3

3

GPIO001/SPI_CS#/32KHZ_OUT

13

RESET_IN#/GPIO014

48

GPIO057/VCC_PWRGD

73

GPIO107/RESET_OUT#

125

XTAL2

123

XTAL1

MEC1404 -NU-GP

071.01404.000E

C2424

C2424 SC10P5 0V2JN-4G P

SC10P5 0V2JN-4G P

3D3V_S 5_KBC

R2476 Do Not Stuff

DB3

ICSP_C LOCK

R2463 Do Not Stuff

DB3

ICSP_D ATA

R2464 Do Not Stuff

DB3

R2466 Do Not Stuff

DB3

ICSP_C LR

R2465 Do Not Stuff

DB3

1 2

R2473

R2473 Do Not Stuff

Do Not Stuff

124

12 12

12

VSS_VBAT

1 2

Do Not Stuff

43

103

122

VTR5VTR19VTR

VTR65VTR82VTR

VBAT

GPIO007/SMB01_DATA/SMB01_DATA18

GPIO010/SMB01_CLK/SMB01_CLK18

GPIO012/SMB02_DATA/SMB02_DATA18

GPIO013/SMB02_CLK/SMB02_CLK18

GPIO130/SMB03_DATA/SMB03_DATA18

GPIO131/SMB03_CLK/SMB03_CLK18

GPIO141/SMB04_DATA/SMB04_DATA18

GPIO142/SMB04_CLK/SMB04_CLK18

MEC1404

GPIO030/BCM_INT0#/PWM4

GPIO031/BCM_DAT0/PWM5 GPIO032/BCM_CLK0/PWM6

GPIO157/LED0/TST_CLK_OUT

GPIO116/TFDP_DATA/UART_RX

GPIO117/TFDP_CLK/UART_TX

GPIO035/SB-TSI_CLK

GPIO033/PECI_DAT/SB_TSI_DAT

GPIO145/ICSP_CLOCK

GPIO146/ICSP_DATA

SYSPWR_PRES/GPIO003

VCI_OUT/GPIO036 VCI_IN1#/GPIO162 VCI_IN0#/GPIO163

VCI_OVRD_IN/GPIO164

GPIO124/CMP_VOUT0

GPIO020/CMP_VIN0

GPIO165/CMP_VREF0 GPIO120/CMP_VOUT1

GPIO021/CMP_VIN1

GPIO166/CMP_VREF1/UART_CLK

GPIO024/CMP_STRAP0

GPIO023/ADC6/A20M

VR_CAP18VSS17VSS51AVSS

VSS

VSS64VSS

84

112

100

EC_AGND

VR_CAP

12

C2418

C2418 SC1U10V 2KX-1GP

SC1U10V 2KX-1GP

R2445

Layout Note:

EC_AGND

Connect GND an d AGND planes v ia either 0R resistor o r connect dir ectly.

3D3V_A UX_KBC_ R ICSP_C LK_R

ICSP_D ATA_R

ICSP_C LR_R

VTR_33_18

GPIO050/TACH0 GPIO051/TACH1

GPIO053/PWM0 GPIO054/PWM1

GPIO056/PWM3

GPIO002/PWM7

GPIO156/LED1 GPIO104/LED2

VREF_CPU

ICSP_MCLR

BGPO/GPIO004

GPIO160/DAC_0 GPIO161/DAC_1

DAC_VREF

GPIO022/ADC5 GPIO153/ADC4 GPIO154/ADC3 GPIO155/ADC2 GPIO122/ADC1 GPIO121/ADC0

ADC_VREF

DB3

7 1

2 3

DB3

4 5 6 8

Do Not Stuff

3D3V_S 5_KBC

R2462

R2462 Do Not Stuff

Do Not Stuff

1 2

12

C2423

SCD1U16V2KX-3GP

3D3V_AUX_KBC_33

ALL_SYS_PWRGD d e-assert,

54

delay 100ms; SY S_PWROK assert .

SMBDA1

8

SMBCLK1KSO9

9

SMBDA2

11

SMBCLK2

12

SYS_PW ROK

89

L_BKLT _EN_EC

91 96

PBAT_P RES#

97

FAN1_TA CH

40 41

44 45

DGPU_PW ROK_K BC

47 34 35 36

PWR_L ED#

4

BAT1_L ED#

1

BAT2_L ED#

106 70

80 81

PTP_DI S#

90

PECI_E C

94

EC_VTT

95

ICSP_C LOCK

101

ICSP_D ATA

102

ICSP_C LR

87

EC_MUTE#

119

+3VLP

120

ALWON

121

VCI_IN1 #

126

POWER _SW_I N#

127

ACAV_I N

128 23

24 22

CMP_VOUT0

85

CMP_VIN0

20

VCREF0

25

CMP_VOUT1

83 21

LCD_TS T

26

CMP_STR AP0

118 117 116

MODEL_I D

109

I_ADP

110

BOARD_ ID

111

I_SYS

113

I_BATT

114 115

3D3V_S 5_KBC

C2422

12

EC_AGND

SCD1U16V2KX-3GP

Do Not Stuff

SCD1U16 V2KX-3G P

C2435

EC_AGND

12

DY

EC_MUTE# [27] ALWON [40]

MASK_BAS E_LED S# [64]

12

3

BOARD_ ID_C

C2408

DY

1 2

Do Not Stuff

EC_AGND

1 2

DY

Do Not Stuff

(To EC)

BOARD_ ID

1 2

DY

Do Not Stuff

(To EC)

R2499

1 2

Do Not Stuff

SYS_PW ROK [17]

R2427

1 2

OPS

0R2J-2-G P

1 2

R2437

C2405

43R2J-G P

Need very clos e to EC

R2469

12

Do Not Stuff

FAN1_DA C_1 [26 ]

C2429

1 2

R2470

12

Do Not Stuff

R2421

12

330R2J -3-GP

Need very clos e to EC

SC2200P50V2KX-2GP

USB_EN#

L_BKLT _EN_EC

12

LCD_TS T

3D3V_S 5

12

R2443

R2443 Do Not Stuff

Do Not Stuff

PCB_REV

12

R2444

DY

Do Not Stuff

AC_IN_K BC#BOARD_I D

R2494

BOARD_ ID_C

R2495

AUX_EN_W OWL

MODEL_I D MODEL_ID_C

(To EC)

SMBDA1 [43,44] SMBCLK1 [43,44]

SIO_SL P_SUS# [17,40 ,53,54] PBAT_P RES# [4 3,44]

LID_CL _SIO# [64]

BKLGT_ PWM [65]

BEEP [27] DGPU_PW ROK [1 9,82,83]

SUSACK# [17] EC_WA KE# [1 7]

SIO_SL P_S3# [17,27,40,5 1,52,54]

ME_FWP _EC [19,98] HOST_DEB UG_TX [61]

H_PECI [4]

ECVBAT

R2452

100KR2 J-1-GP

1 2

PWR_C HG_ACOK [17,44 ]

R2424

20KR2F -L-GP

3D3V_S 5_KBC

CMP_VOUT0 [26]

CMP_VIN0_ R [26]

OVER_C URRENT_P8 # [76]

R2448

10KR2F -2-GP

PANEL_BK EN_EC [55]

SIO_EX T_WAK E# [20] AD_IA [44]

3D3V_S 5

R2479

1 2

Do Not Stuff

R2435

12

Do Not Stuff

eDP backlight Control from PC H

R2436

R2436 100KR2 J-1-GP

100KR2 J-1-GP

R2419

1 2

Do Not Stuff

PS_ID [4 3]

12

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

R2497

1 2

Do Not Stuff

1 2

12

R2434

R2434 100KR2 J-1-GP

100KR2 J-1-GP

L_BKLT _EN [8]

3D3V_S 5_KBC

Vref = 1.117 temp around 85

12

C2409

C2409 SCD01U5 0V2KX-1 GP

SCD01U5 0V2KX-1 GP

USB_PW R_EN# [35]

LCD_TS T_EN [55]

LCD_TS T [55]

100.0K

100.0K 174.0K

R2493

AC_IN_K BC#_R

12

DY

Do Not Stuff

MODEL_ID _C

3D3V_S 0

R2430

R2430 10KR2J -3-GP

10KR2J -3-GP

1 2

83.R2004.G8F

3D3V_A UX_S5

+3VLP

LID_CL _SIO# MASK_BAS E_LEDS # TP_EN#

TOUCH_PANE L_INTR#

Touch Panel PH internally.

CMP_STRA P0

SMBDA2

SMBCLK2

VOLTAGEPULL-HIGH RESISTORPULL-LOW RESISTORBoard_ID_DET(GPIO153)

10.0K

17.8K

33.0K

47.0K

64.9K

76.8K

100.0K

3D3V_S 5_KBC

U2401

1

6

A2

SEL

2

5

GND

VDD

DY

4

A13DA

Do Not Stuff

D2403

KA

FAN_TACH1 [26]

RB751V -40H-GP

12

R2467

R2467 1KR2J-1 -GP

1KR2J-1 -GP

12

R2454

R2454 100KR2 J-1-GP

100KR2 J-1-GP

R2433 100KR2 J-1-GPR2433 100KR 2J-1-GP

1 2

R2438 10KR2J -3-GPR2 438 10KR2J-3 -GP

1 2

R2409 100KR2 J-1-GPR2409 100KR 2J-1-GP

1 2

R2429 Do Not Stuff

1 2

DY

R2420 10KR2J -3-GPR2 420 10KR2J-3 -GP

1 2

'CMP_STRAP0' p ull high to ena ble Comparator fun ction 11/24

SMBDA2 SML1_SMBDATA

1 2

Do Not Stuff

1 2

Do Not Stuff

3D3V_S 5_KBC 3D3V_S5_PC H

1

23

RN2603

RN2603 Do Not Stuff

Do Not Stuff

DS3

4

Do Not Stuff

2nd = 84.2 N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65V

1.358V100.0K 143.0K

1.204V

1.048V215.0K100.0K

R2482

R2483

MODEL_ID

(To EC)

6

Do Not Stuff

DS3

Q2604

2

ALL_SYS_ PWRG D[17,40 ]AC_IN_K BC#[43]

3D3V_S 5

3D3V_S 0

3D3V_S 5_KBC

SML1_SMBC LKSMBCLK2

1 2345

MODEL_ID _C

C2407

3D3V_S 5

R2442

Do Not Stuff

MODEL_ID

1 2

EC_AGND

SCD1U16V2KX-3GP

BAT1_L ED#

BAT2_L ED#

CAP_LE D#

PWR_L ED#

SML1_SMBD ATA [18,26,76]

SML1_SMBC LK [18,26,76]

12

R2441

R2441 100KR2 F-L1-GP

100KR2 F-L1-GP

3D3V_S 5

LID_CL _SIO#

PTP_DI S#

SMBCLK1 SMBDA1

PCH_ALW _ON

PBAT_P RES# SIO_EX T_SCI# SIO_EX T_SMI#

3D3V_S 5

1 2

3D3V_S 5

1 2

3D3V_S 5

1 2

3D3V_S 5

1 2

RB751V -40H-GP

R2484

R2484 100KR2 J-1-GP

100KR2 J-1-GP

S

G

R2488

R2488 100KR2 J-1-GP

100KR2 J-1-GP

S

G

R2489

R2489 100KR2 J-1-GP

100KR2 J-1-GP

S

G

Q2414

R2498

R2498 100KR2 J-1-GP

100KR2 J-1-GP

S

G

Q2416

D2402

K A

D2405

K A

Love_land_UMA_X01 Love_land_UMA_X02 Love_land_UMA_A00

Reserved

Love_land_DIS_X01 Love_land_DIS_X02 Love_land_DIS_A00

Reserved Reserved

RN2402

SRN4K7J -8-GP

R2496 Do Not Stuff

1 2

R2415 10KR2J-3 -GPR2 415 10KR2J-3-G P

1 2

R2411 Do Not StuffR2411 Do Not Stuff

1 2

R2412 Do Not StuffR2412 Do Not Stuff

1 2

R2457 Do Not Stuff

1 2

Q2412

D

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

Q2413

D

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

83.R2004.G8F

PULL-LOW RESISTOR

100.0K 3.143V

100.0K

100.0KReserved

100.0K

3D3V_S5 _KBC

1234

DS3

84.2N702.J31

2N7002K -2-GP

TOUCH_PANE L_INTR# [4,55]

TP_LOCK # [65]

DY

2N7002K -2-GP

3D3V_S5 _KBC

1

PULL-HIGH RESISTORMODEL_ID_DET(GPIO153)

4.99K(64.49925.6DL)

16.2K(64.16225.6DL)

28.7K(64.28725.6DL) 59K(64.59025.6DL)

76.8K(64.76825.6DL) 100K(64.10035.6DL) 130K(64.13035.6DL) 169K(64.16935.6DL) 1.227V 226K(64.22635.6DL) 1.012V

SIO_EXT _SCI# _R [16 ] SIO_EXT _SMI#_ R [8]

USB_OC3# [16 ]

BATT_W HITE_L ED# [64]

CHG_AMBER _LED# [64]

CAP_LED #_S [65]

PWR_L ED#_S [64]

VOLTAGE

2.840V

2.564V

2.307V43K(64.43025.6DL)

2.075V

1.866V

1.650V

1.435V

Reserved for DS3 circuit

Title

KBC SMSC 1404

Size Docume nt Number R ev

Size Docume nt Number R ev Custom

Custom

Loveland SKL-U

Tuesday, Sep tember 15 , 2015

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Se c.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Se c.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 22 1, Taiwan, R.O.C.

Taipei Hsien 22 1, Taiwan, R.O.C.

24 105

A00

5

Main Func = SPI Flash

4

3

2

1

R2501

4K7R2J-2-GP

SPI_WP_ROM_R

12

DY

R2515

Do Not Stuff

12

DY

3D3V_S5_PCH

DY

1 2

3D3V_S5_PCH

DY

1 2

SPI1_SO_ROM_R SPI1_WP_ROM_R

4

1

DY

2 3

4

1

2 3

RN2501

RN2501 Do Not Stuff

Do Not Stuff

SPI25

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

W25Q128FVSIG-GP

72.25128.0A1

RN2502

RN2502 Do Not Stuff

Do Not Stuff

SPI252

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

Do Not Stuff

VCC

HOLD#/IO3

CLK

DI/IO0

Do Not Stuff

VCC

CLK

DI/IO0

Do Not Stuff

8 7 6 5

HOLD#/RESET#/IO3

DY

Do Not Stuff

3D3V_S5_PCH

8 7 6 5

EC2501

3D3V_S5_PCH

SPI1_HOLD_ROM_R

SPI1_CLK_ROM_R SPI1_SI_ROM_R

12

EC2506

SPI_HOLD_ROM_RSPI_SO_ROM_R

SPI_CLK_ROM_R SPI_SI_ROM_R

12

DY

Do Not Stuff

DY

C2501

12

SPI Flash ROM(16M) for PCH

SKT25

SPI_CS_ROM_N0[18,24] SPI_SO_ROM[18,24,91]

SKT25

1 2

DY

3 6 4

Do Not Stuff

8 7

5

R2507 10R2F-L-GPR2507 10R2F-L-GP R2508 10R2F-L-GPR2508 10R2F-L-GP

D D

SPI_CS_ROM_N0 SPI_SO_ROM_R SPI_WP_ROM_R

SPI_WP_ROM[18]

3D3V_S5_PCH

SPI_HOLD_ROM_R SPI_CLK_ROM_R SPI_SI_ROM_R

1 2 1 2

Do Not Stuff

EC2502

SPI Flash ROM(8M) for PCH

C C

SKT26

SPI_CS_ROM_N1 SPI1_SO_ROM_R SPI1_WP_ROM_R

SPI_CS_ROM_N1[18] SPI_SO_ROM[18,24,91]

SPI_WP_ROM[18]

SKT26

1

8

2

7

DY

3 6 4

5

Do Not Stuff

R2513 Do Not Stuff

1 2

R2514 Do Not Stuff

1 2

SPI1_HOLD_ROM_R SPI1_CLK_ROM_R SPI1_SI_ROM_R

DY

DY DY

DY

Do Not Stuff

3D3V_S5_PCH

EC2504

3D3V_S5_PCH

12

DY

12

DY

C2505

DY

R2509 Do Not Stuff

R2509 Do Not Stuff R2511 Do Not Stuff

R2511 Do Not Stuff R2512 Do Not Stuff

R2512 Do Not Stuff

EC2505

EC2505 Do Not Stuff

Do Not Stuff

12

C2502

C2502 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

R2503 10R2F-L-GPR2503 10R2F-L-GP

1 2

R2505 10R2F-L-GPR2505 10R2F-L-GP

1 2

R2506 10R2F-L-GPR2506 10R2F-L-GP

1 2

EC2503

EC2503 Do Not Stuff

Do Not Stuff

3D3V_S5_PCH

12

1 2

DY

1 2

DY

1 2

DY

12

C2504

C2504 Do Not Stuff

Do Not Stuff

SPI_HOLD_ROM [18] SPI_CLK_ROM [18,24,91] SPI_SI_ROM [18,24,91]

B B

Main Func = RTC

RTC_AUX_S5+RTC_VCC 3D3V_AUX_S5

AFTP2502AFTP2502

RTC1

ACES-CON2-11-GP-U

20.F0772.002

A A

5

+RTC_VCC

1

R2502

1KR2J-1-GP

3 1

2 4

1

4

1KR2J-1-GP

AFTP2501AFTP2501

12

R2504

R2504 10MR2J-L-GP

10MR2J-L-GP

RTC_PW R

D2501

1

2

BAS40C-2-GP

75.00040.07D

75.00040.07D 2nd = 75.00040.C7D

2nd = 75.00040.C7D 3rd = 75.00040.A7D

3rd = 75.00040.A7D

Q2505

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

3

12

C2503

DY

Do Not Stuff

D

3

RTC_DET# [20]

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, September 15, 2015

Date: Sheet of

Flash/RTC

Loveland SKL-U

Taipei Hsien 221, Taiwan, R.O.C.

25 105

1

A00

5

Main Func = Thermal Sensor

D D

Do Not Stuff

Q2603

C

T8

o Not Stuff

o Not Stuff D

D

E

2.System Sensor, Put on palm rest

C C

3D3V_S0

R2603 Do Not Stuff

R2603 Do Not Stuff R2604 Do Not Stuff

R2604 Do Not Stuff

B B

3D3V_S0

SML1_SMBDATA[18,24,76]

12

C2601

C2602

DY

12

C2606

DY

1 2

T8

1 2

T8

C2606 Do Not Stuff

Do Not Stuff

B

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

C2602

T8

Do Not Stuff

NCT7718_DXP

12

T8

NCT7718_DXN

Layout Note:

C2812 close U2801

NCT7718_ALERT#

T_CRIT#

C2607

C2607 Do Not Stuff

Do Not Stuff

12

DY

T_CRIT#

R2601

R2601 Do Not Stuff

Do Not Stuff

SML1_SMBCLK[18,24,76]

1 2 3

RESET_OUT#[17,24,40]

THERM_SYS_SHDN#

4

Do Not Stuff

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

THM26

VDD D+ DT_CRIT#4GND

Do Not Stuff

SCL SDA

T8

ALERT#

8 7 6 5

6 5

NCT7718_ALERT#

3D3V_S0 3D3V_S0

Do Not Stuff

1 2

T8

34

Q2601

Q2602

G

D

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

THERM_SYS_SHDN#

1

T8

4

DY

23

RN2602

RN2602 Do Not Stuff

Do Not Stuff

12

DY

C2608

Do Not Stuff

12

3

THM_SML1_DATA

THM_SML1_CLK

THM_SML1_CLK THM_SML1_DATA

12

C2609

Do Not Stuff

R2612 Do Not Stuff

C2610

Do Not Stuff

1 2

Do Not Stuff

Layout Note:

Signal Routing Guideline: Trace width = 15mil

PURE_HW _SHUTDOWN# [40,76]

DY

R2607

1 2

10KR2J-3-GP

CMP_VOUT0

1 2

need to check with NTD team Barkley 1404 test result

3D3V_S5_KBC

R2602

Do Not Stuff

CMP_VOUT0 [24]

2

R2605

Do Not Stuff

1 2

DY

5V_S0

FAN1_DAC_1[24]

Layout Note:

Need 10 mil trace width.

12

C2604

DY

FAN_VCC1

D2601

KA

DY

Do Not Stuff

FAN_TACH1[24]

EC2602

12

Do Not Stuff

SC10P50V2JN-4GP

FAN_TACH1 FAN_VCC1

12

DY

Fan controller1

FAN261

FON#

1

FON#

2

VIN

3

VOUT VSET4GND

AP2113MTR-G1-GP

74.02113.0E1

FAN_VCC1

12

C2603

SC2200P50V2KX-2GP

EC2601

GND GND GND

FAN_TACH1_C

R2606

Do Not Stuff

1 2

AFTP2802AFTP2802 AFTP2801AFTP2801

8 7 6 5

1 1

6 4

3 2

1 5

FAN1

FAN1 ACES-CON4-17-GP-U1

ACES-CON4-17-GP-U1

20.F1621.004

1

AFTP2803AFTP2803

FAN_TACH1_C FAN_VCC1

1

5V_S0

12

C2611

C2605

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

Close to KBC

Close to Thermal sensor

3D3V_S5_KBC3D3V_AUX_S5

DY

12

R2609

Do Not Stuff

12

R2608

R2608 25K5R2F-GP

25K5R2F-GP

VD_IN1 for system thermal sensor

12

C2612

R2610

NTC-100K-8-GP

A A

5

4

12

SCD1U16V2KX-3GP

VD_IN1_C

3

12

C2613

SC100P50V2JN-3GP

CMP_VIN0_R [24]

R2611

1 2

Do Not Stuff

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL NCT7718W/Fan

Size Document Number Rev

Size Document Number Rev A3

A3

Loveland SKL-U

Tuesday, September 15, 2015

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

26 105

1

A00

5

4

3

2

1

Main Func = Audio

Audio Codec Chip (ALC3234 & ALC3246 co-lay)

R2731

1 2

Do Not Stuff

D D

Do Not Stuff

3D3V_S0

25mA

R2725

1 2

3234

Do Not Stuff

1D8V_S0

R2726

1 2

Do Not Stuff

1.5A

5V_S0 +5V_PVDD

R2702

1 2

Do Not Stuff

Do Not Stuff R2704

R2704

1 2

Do Not Stuff

moat

C C

3D3V_S0

1D8V_S0

1D5V_S0

R2713

1 2

R2705

1 2

3234

R2710 Do N ot Stuff

1 2

DY

AVDD2: +1.8VD@3246 +1.5VD@3234

Do Not Stuff

+3V_1D5V_AVDD

AUD_AGND

Azalia I/F EMI

EC2708

12

SC22P50V2JN-4GP

B B

Layout Note:

Close pin41

12

C2715

SC4D7U6D3V3KX-GP

HDA_CODE C_SDOUT HDA_CODE C_BITCLK

EC2709

12

SC22P50V2JN-4GP

+3V_AVDD

ALC3234 and ALC3246

CPVDD

C2714

12

C2706

12

C2721

C2701

SC4D7U6D3V 3KX-GP

Close pin36

SCD1U16V2KX-3GP

C2708

C2709

C2707

12

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP

Layout Note:

Close pin46

+3V_AVDD

Layout Note:

EC_MUTE#[ 24]

1 2

DMIC_CLK[55]

SC22P50V2JN-4G P

Speaker trace width >40mil @ 2W4ohm speaker power

Close pin40

SCD1U16V2KX-3GP

Close pin3

AUD_AGND AUD_AGND

R2724

DY

Do Not Stuff

DMIC_DATA_R

C2723

12

1 2

C2712 SC10U6D3V3MX-GPC2712 SC10U6D3V3MX- GP

1 2

+3V_1D5V_AVDD

AUD_SPK_L+[ 29]

AUD_SPK_L-[29] AUD_SPK_R-[29] AUD_SPK_R+[29]

R2708

1 2

Do Not Stuff

EC2701

SC10P50V2JN-4GP

TP2702

Do Not Stuff

DMIC_DATA[5 5]

HDA_CODE C_SDOUT[19] HDA_CODE C_BITCLK[19]

HDA_SDIN0[19]

HDA_CODE C_SYNC[19]

HDA_CODE C_RST#[19]

+5V_PVDD

AUD_SPK_L+ AUD_SPK_LAUD_SPK_RAUD_SPK_R+

+5V_PVDD

COMBO-GPI

1

SC4D7U6D3V 3KX-GP

LINE1_VREFO_R[29] LINE1_VREFO_L[29]

AUD_HP1_JAC K_L[29] AUD_HP1_JAC K_R[29]

SC1U10V2KX-1G P

12

C2703

C2703 SC1U10V2KX-1G P

SC1U10V2KX-1G P

HDA27

CBP

37

CBP

38

AVSS2

LDO2_CAP

39

LDO2-CAP

40

AVDD2

41

PVDD1

42

SPK-OUT-L+

43

SPK-OUT-L-

44

SPK-OUT-R-

45

SPK-OUT-R+

46

PVDD2

PD#

47

PDB

48

SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC -CLK-IN

49

GND

ALC3246-CG-G P-U

+3V_AVDD

12

C2716

R271422R2J -2-GP R271422R 2J-2-GP

1 2

R271622R2J -2-GP R271622R 2J-2-GP

1 2

R2719Do Not Stuff R2719D o Not Stuff

1 2

R272022R2J-2- GP R272022R2J -2-GP

1 2

R271822R2J-2- GP R271822R2J -2-GP

1 2

C2704

1 2

CPVDD

CPVEE

CBN

31

32

33

34

35

36

CBN

CPVEE

CPVDD

HPOUT-L_PORT-I-L

HPOUT-R_PORT-I-R

071.03246.0003

(71.03234.003)

DVDD1GPIO0/DMIC-DATA122GPIO1/DMIC-CLK3DC_DET4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10I2C-DATA11I2C-CLK

DVSS

12

C2717

12

DY

Do Not Stuff

R2732

SCD1U16V2KX-3GP

DMIC_DATA_R DMIC_CLK_R

CODEC_SD OUT_R CODEC_BITC LK_R HDA_CODE C_SDIN0 HDA_CODE C_SYNC

HDA_CODE C_RST#

C2705

12

C2702

SC2D2U10V3KX-1GP

AUD_VREF

LDO1_CAP

27

28

29

30

VREF

LDO1-CAP

LINE2-L_PORT-E-L

MIC2-VREFO

LINE1-VREFO-L

LINE2-R_PORT-E-R

LINE1-VREFO-R

LINE1-L_PORT-C-L

LINE1-R_PORT-C-R

MIC2-R_PORT-F-R/SLEEVE

MIC2-L_PORT-F-L/RING2

SPDIFO/FRONT-JD_JD3/GPIO3

MIC2/LINE2-JD_JD2

HP/LINE1-JD_JD1

+3V_AVDD

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7 U6D3V3KX-GP

C2719SCD1U16V2KX -3GP C2719SCD1U16V2KX-3GP

RESETB@3234

12

R2721

MIC2_VREFO [29]

AUD_AGND

Reserved for ALC3234

12

R2711

R2711 100KR2J-1-GP

100KR2J-1-GP

SC4D7U6D3V3KX-GP

+5V_AVDD AUD_AGND

25

26

AVSS1

AVDD1

24 23 22 21 20

VD33STB

19

MIC2-CAP

18 17 16

PCBEEP

15 14 13

12

AUD_PC_BEEP

PCBEEP@3234

HDA_CODEC_RST#_R

3234

1 2

Do Not Stuff

V3D3_STB MIC_CAP

AUD_PC_BEEP _3246 JDREF

AUD_SENSE_A

R2715

1 2

3234

Do Not Stuff

12

C2711

SCD1U16V2KX-3GP

AUD_AGND

SC4D7U6D3V3KX-GP

LINE1_L [29] LINE1_R [29]

R2712 Do N ot StuffR271 2 Do Not Stu ff

1 2

SLEEVE [29] RING2 [29]

DY

R2709

Layout Note:

Place close to Pin 13

Do Not Stuff

Layout Note:

Place close to Pin 26

1 2

AUD_SENSE

C2710

C2713 SC 10U6D3V3MX-GPC2713 SC10U6D3V3MX -GP

R2707 D o Not Stuff

1 2

200KR2F-L-GP

moat

AUD_PC_BEEP _R

SPKR[19]

BEEP[24]

moat

R2703

1 2

moat

2 3 1

R2723

1 2

Do Not Stuff

RN2701

SRN0J-6-GP

5V_S0+5V _AVDD

3D3V_S5

AUD_AGND

Layout Note:

AUD_PC_BEEP _R

AUD_AGND

AUD_SENSE [29 ]

4

moat

EC2707 Do Not Stuff

1 2

DY

EC2706 SC1KP50V2KX-1GPEC 2706 SC1KP50V2KX-1GP

1 2

EC2705 SCD1U25V2KX-GPEC2705 SCD1U25V2KX-GP

1 2

EC2704 Do Not Stuff

1 2

DY

EC2703 SCD1U25V2KX-GPEC2703 SCD1U25V2KX-GP

1 2

AUD_AGND

R2706

1 2

Do Not Stuff

R2727

1 2

Do Not Stuff

R2730

1 2

Do Not Stuff

Layout Note:

AUD_AGND

Tied at point only under Codec or near the Codec

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

moat

R2722

HDA_SPKR_R

KBC_BEEP_R

75.00054.E7D

75.00054.E7D 2nd = 83.R2003.W81

2nd = 83.R2003.W81 3rd = 75.00054.A7D

3rd = 75.00054.A7D 4th = 83.R2003.V81

4th = 83.R2003.V81

D2701

2

1

BAT54C-7-F- 3-GP

AUD_SENSE_A

+3.3VD@3234 follow Pin1 Power setting@3246

AUD_PC_BEEP _C

3

12

C2720

1 2

R2717

R2717 1KR2J-1-GP

1KR2J-1-GP

R2722

100KR2J-1-GP

AUD_PC_BEEP _R

SCD1U16V2KX- 3GP

+3V_AVDD

12

1D8V_S01D8V_S5

Q4008

DMP2130L-7-GP

150mA

12

3246

Q4009

G

S

2N7002K-2-GP

3246

3D3V_S0

SIO_SLP_S3#[17,24,40,51,52,54]

A A

5

4

DY

Do Not Stuff

R2728

1 2

Do Not Stuff

Q4009_G

R2729

1 2

R4046

C4029

3246

10KR2J-3-GP

SCD1U16V2KX-3GP

1D8V_EN#

D

3

R4047

1 2

3246

4K7R2J-2-GP

3246

12

1D8V_EN_R#

S

C4028

SCD22U10V2KX- 1GP

84.02130.031

84.02130.031 2nd = 84.00102.031

2nd = 84.00102.031 3rd = 84.03413.B31

3rd = 84.03413.B31

DMP2130L-7-GP

3246

D

G

12

C4030

Do Not Stuff

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Numb er Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Audio Codec ALC3234

Loveland SKL-U

1

27 105Tuesday, Sep tember 15, 2015

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Loveland SKL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

28 105Tuesday, September 15, 2015

1

A00

5

Main Func = Audio

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

12 12

EC2906

12

AUD_SPK_L+_C AUD_SPK_L-_C

AUD_SPK_R+_C AUD_SPK_R-_C

SC100P50V2JN-3GP

EC2905

12

D D

C C

MIC2_VREFO[27]

SLEEVE[27]

AUD_HP1_JACK_L[27]

LINE1_L[27]

LINE1_VREFO_L[27]

AUD_HP1_JACK_R[27]

LINE1_R[27]

LINE1_VREFO_R[27]

RING2[27]

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

B B

Layout Note:

C2907

C2908

1 2

AUD_SPK_L+[27] AUD_SPK_L-[27]

AUD_SPK_R+[27] AUD_SPK_R-[27]

LINE1-L_C

SC4D7U6D3V3KX-GP

LINE1-L_R

SC4D7U6D3V3KX-GP

1 2

EC2901

SC1KP50V2KX-1GP

RN2901

2 3 1

4

SRN2K2J-1-GP

SRN2K2J-1-GP R2908 10R2F-L-GPR2908 10R2F-L-GP

1 2

R2922 1KR2J-1-GPR2922 1KR2J-1-GP

1 2

R2912 4K7R2J-2-GPR2912 4K7R2J-2-GP

1 2

R2910 10R2F-L-GPR2910 10R2F-L-GP

1 2

R2921 1KR2J-1-GPR2921 1KR2J-1-GP

1 2

R2913 4K7R2J-2-GPR2913 4K7R2J-2-GP

1 2

EC2903

EC2902

SC1KP50V2KX-1GP

1 2

EC2904

SC1KP50V2KX-1GP

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1 AUD_PORTA_R_HPMIC1

SC100P50V2JN-3GP

EC2908

EC2907

Do Not Stuff

R2920

12

DY

EC2907

12

AUD_AGND AUD_AGND

L2904PBY160808T-121Y-GP L2904PBY160808T-121Y-GP L2903PBY160808T-121Y-GP L2903PBY160808T-121Y-GP

L2902PBY160808T-121Y-GP L2902PBY160808T-121Y-GP L2901PBY160808T-121Y-GP L2901PBY160808T-121Y-GP

SC100P50V2JN-3GP

Do Not Stuff

R2919

12

DY

Speaker

SPK1

1 2

3 4

ACES-CON4-29-GP

20.F1639.004

2nd = 20.F1804.004

3rd = 20.F1352.004

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C

AUD_SPK_R+_C

R2906Do Not Stuff R2906Do Not Stuff R2907Do Not Stuff R2907Do Not Stuff

R2909Do Not Stuff R2909Do Not Stuff R2911Do Not Stuff R2911Do Not Stuff

5

6

CONN Pin Pin1 Pin2 Pin3 Pin4

AFTP2901AFTP2901

1

AFTP2902AFTP2902

1

AFTP2903AFTP2903

1

AFTP2904AFTP2904

1

Net name SPK_R+ SPK_RSPK_L+ SPK_L-

A00 08/17

HPMIC1

12 12

SLEEVE_HPMIC1 AUD_PORTA_L_HPMIC1

JACK_PLUG JACK_PLUG_DET

RING2_HPMIC1

AUD_AGND

HPMIC1

3 1

5

Shift Issue

6 2 4

MS

Audio(IP/NK comb)

PAD-AUDIO-JK509-GP-U-1

ZZ.00PAD.IB1

HPMIC1 Main Source : 022.10002.0981 2nd : 022.10002.00D1 3rd : 022.10002.00P1

JACK_PLUG

AUD_PORTA_R_HPMIC1

AUD_PORTA_L_HPMIC1 RING2_HPMIC1

ED301

12

AZ5125-01H-R7G-GP

ED302

12

JACK_PLUG JACK_PLUG_DET SLEEVE_HPMIC1

3

JACK_PLUG_DET

10 mils

A A

5

12

AUD_AGND

R307

R307 Do Not Stuff

Do Not Stuff

moat

4

AZ5125-01H-R7G-GP

ED303

ED304

12

AZ5125-01H-R7G-GP

ED306

ED305

12

10 mils 10 mils

R2923

1 2

Do Not Stuff

2

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Loveland SKL-U

Tuesday, September 15, 2015

Date: Sheet of

AUD_SENSE [27]

Audio IO

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

29 105

1

A00

5

4

3

2

1

Main Func = Audio

D D

C C

(Blanking)

B B

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

Size Document Number Rev A4

A4

A4 Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Loveland SKL-U

Tuesday, September 15, 2015

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

30 105

1

A00

Dell Latitude 3470 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual