COMPAL LA-1181
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
2001-11-16
uFCBGA/uFCPGA Coppermine-T or Tualatin
REV: 2.0
Tang/TangBTO Schematics Document
ADY11 LA-1181
2
Cover Sheet
1 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCI BUS
LPC BUS
Clock Generator
USB conn
uFCBGA/uFCPGA CPU
CardBus Controller
Almador-M
GMCH-M
HUB Link
HD#(0..63)HA#(3..31)
Compal confidential
Model Name :ADY11(Tang)
AMP& Phone
Jack
page 4,5
page 15
page 21
page 24
page 14
page 8,9,10
page 30
File Name : LA-1181
Coppermine-T or
Tualatin
Block Diagram
Power Circuit
DC/DC
page
32,33,34,35,36,37
Slot 0
page 22
page 31
DC/DC Interface
Suspend
IDE Connector
(HDD/CR-ROM)
page 19
AC97
Codec
page 23
SIOPIO
FDD
page 27 page 27
page 19
NS PC87393
page 26
Power On/Off
Reset & RTC
page 30
PSB
ICH3-M
BIOS
Int.KBD
Touch Pad
14M_5V
EC 87570
PS/2 conn
page 28
page 27
page 29 page 27
page 29
EC I/O Buffer
page 29
LPC to X-BUS
& Super I/O
X BUS
OZ 6912
DVO Link
Memory BUS
CPU Bypass
& CPUVID
page 6
133MHz
1.8V 66MHz
3.3V 33MHz
3.3V 133MHz
3.3V 48MHz
3.3V 24.576MHz
3.3V ATA100
3.3V 33MHz
LAN
3COM -3C920
page 20
MDC
page 25
page 7
VCH Conn
page 15
625 BGA
421 BGA
page 16,17
SO-DIMM X2
BANK 0, 1, 2, 3
page 12,13
VCH
Board
Thermal Sensor
MAX6654 W320-04
page 5
Fan Control
page 7
STAC9700
RJ45
page 20
IDSEL:AD17
(PIRQA#,GNT# 3,REQ#3)
IDSEL:AD20
(PIRQA/B#,GN T#2,REQ#2)
AC-LINK
ITP Connector
CRT Connector
PCI debug
port
page 27
ADY11 LA-1181
2
Block Diagram
2 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS,INC.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Compal Electronics, Inc.
SST-Build
FW82830MG FW82801CAM
QB63QB88
3C920-ST06CHIPS Rev CHIPS Rev
Lot:M28010
DC:C0117
SST2-Build
Lot:M28010
DC:C0117
QC34 QB62
PT-Build
QB62 Lot:M28010
DC:C0117
TangM2P3
FDD
PS/2
Series port
Parallel port
RJ45
Function
Model
3Com Lan
chipset(3C920)
YES
YES
NO
YES
YES
NO
YES
NO
YES
NO
NOYES
Note:"@" means all model depop
"#" means Tang depop
Note:"@" means all model depop
"&" means M2P3 depop
"#" means Tang depop
Lot:M28010
DC:C0117
ST-Build
QC34
QC34 QC42
ADY11 LA-1181
2
Note & Revision
3 41Friday, November 16, 2001
Title
Size Document Number Rev
Date: Sheet of
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Mobile
Tualatin
Address
Lines
Request
Signals
Interface
Error
Arbitration
Signals
VCC
Snoop
Signals
VSS VCC
Data
Signals
ADY11 LA-1181
2
Mobile Tualatin uFCPGA
4 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
HD#[0..63]
HREQ#[0..4]
HA#[3..31]
HD#52
HD#43
HD#14
HA#27
HA#14
HA#11
HD#41
HD#40
HD#39
HD#38
HD#9
HA#22
HA#20
HA#12
HD#26
HD#25
HD#63
HD#19
HD#15
HD#10
HREQ#4
HA#23
HA#17
HD#33
HD#16
HA#30
HA#21
HA#9
HA#3
HD#51
HD#50
HD#42
HD#32
HD#31
HD#30
HD#12
HA#16
HA#26
HA#24
HA#18
HD#62
HD#8
HD#6
HD#11
HD#5
HD#3
HA#31
HA#29
HD#57
HD#56
HD#55
HD#54
HD#53
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#18
HD#29
HD#1
HD#0
HREQ#3
HD#28
HD#27
HREQ#2
HREQ#1
HREQ#0
HA#28
HA#15
HA#7
HA#6
HA#4
HD#24
HD#23
HD#22
HD#21
HD#20
HD#17
HD#13
HD#2
HA#25
HA#10
HA#5
HD#61
HD#60
HD#7
HD#4
HA#13
HA#8
HD#59
HD#58
HD#37
HD#36
HD#35
HD#34
HA#19
+CPU_CORE
+1.5VS
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS,INC.
R108 1.5K
1 2
R121 10_0402
1 2
U5A
TUALATIN
K1
J1
G2
K3
J2
H3
G1
A3
J3
H1
D3
F3
G3
C2
B5
B11
C6
B9
B7
C8
A8
A10
B3
A13
A9
C3
C12
C10
A6
A15
A14
B13
A12
R1
L3
T1
U1
L1
T4
AA3
W2
AB3
P3
C14
AF23
AF4
L2
R2
AD23
C22
C4
A7
V3
T3
U2
AA2
A16
B17
A17
D23
B19
C20
C16
A20
A22
A19
A23
A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
M26
P24
AA26
T26
U24
Y25
W26
V26
AB25
T25
Y24
W24
Y26
AB24
AA24
V24
D22
F22
E21
H22
G21
K22
J21
M22
L21
P22
N21
T22
R21
V22
U21
Y22
W21
AB22
AA21
AC21
D20
F20
E19
AB20
AA19
AC19
D18
F18
E17
AB18
AA17
AC17
D16
F16
E15
AB16
AA15
AC15
D14
F14
E13
AB14
AA13
AC13
D12
F12
E11
AB12
AA11
AC11
D10
F10
E9
AB10
AA9
AC9
D8
F8
E7
AB8
AA7
AC7
D6
F6
E5
H6
G5
K6
J5
N5
T6
V6
U5
Y6
W5
AB6
AA5
AC5
M6
P6
E16
R4
E25
G25
J25
L25
N25
R25
U25
W25
AA25
AC25
AF25
AE26
C23
F23
H23
K23
M23
P23
T23
V23
Y23
AB23
AE23
B22
D21
F21
E22
H21
G22
K21
J22
M21
L22
P21
N22
T21
R22
V21
U22
Y21
W22
AB21
AA22
AC22
AE21
B20
D19
AB19
AA20
AC20
AE19
B18
D17
F17
E18
AB17
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
RP#
ADS#
AERR#
AP#0
AP#1
BERR#
BINIT#
IERR#
BNR#
BPRI#
NC
NC
NC
BREQ0#
LOCK#
DEFER#
HITM#
HIT#
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
HA#[3..31]<8>
HREQ#[0..4]<8>
HD#[0..63] <8>
HADS#<8>
HBNR#<8>
HBPRI#<8>
HLOCK#<8>
HIT#<8>
HITM#<8>
HDEFER#<8>
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Place
R_K<0.1"
from CPU
Note :
GHI# Pull-Up internally
Mobile
Tualatin
Data
Compatibility
Signals
VTT Ref
Analog
VCCT VID
Test
Access
PORT
( ITP )
Debug
Break
Point
APIC
Request
Signals GND
If used ITP port mu st depop
GTL Reference Voltage
1. Place R_A and R_B between and GMCH and CPU.
2. Place decoupling caps near CPU.(Within 500mils)
Layout note :
R_A
R_B
Address :1001_110X
W=15mil
Thermal Sensor
MAX6654MEE
CMOS Reference Voltage
1. Place R_E1 and R_F near CPU.
2. Place decoupling caps near CPU.
Layout note :
R_E
R_F
R_K
ADY11 LA-1181
2
Mobile Tualatin uFCPGA & Thermal sensor
5 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
ITP_TCK
H_THERMDA
H_IGNNE#
H_INTR
TESTHI2
H_THERMDC
ITP_TDI
H_A20M#
CLK_HCLK#
TESTLO2
TESTHI1
ITP_TMS
ITP_TRST#
ITP_PREQ#
CLK_HCLK
H_NMI
TESTLO1
+VTT_PLL
ITP_TDO
VTT_PWRGD
ITP_PRDY#
ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK
ITP_PREQ#
ITP_PRDY#
TESTHI1
TESTHI2
TESTLO1
TESTLO2
+VTT_C
VTT_PWRGD
H_THERMDA
H_THERMDC
+VTT_PLLIN
+3VS
+VTT
+CPU_CORE
+V_AGTLREF
+VTT
+VTT
+VS_CMOSREF
+VTT
+1.5VS
+1.5VS
+1.5VS
+1.8VS
+VTT
+VTT
+1.5VS
+VTT
+VTT
+V_AGTLREF
+5VALW
+5VALW
+5VALW
+1.5VS
+VS_CMOSREF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS,INC.
R24
1.5K
12
R18
1.5K
12
R28
56.2_1%
12
R34 110_1%
1 2
R37
150
12
R30 56.2_1%
1 2
R134 14_1%
1 2
R19
3K
12
R36
150
12
R6
10K_0402
12
L22 FLM-201209-4R7K
1 2
R11
1K_0402
12
Q2
3904
2
3
1
C38
@10PF_0402
R35
@33_0402
1 2
U5B
TUALATIN
Y3
V1
U3
M5
W1
AC3
AF6
AF5
AD9
AD3
AB4
AE4
AF8
AD15
AE14
AE6
B15
Y1
W3
AF14
AF13
AF10
AE12
AF16
AE20
AF22
AD22
AD21
AD7
AD10
AD11
AF7
AF15
AF19
AE22
AD5
AF12
AE16
L5
AF21
AB26
H26
A21
AF9
A4
N1
AA1
Y4
R5
N3
N2
P1
P5
E1
F1
AC1
AD1
M1
AF18
AD16
AF11
AE8
N24
E2
P4
AD19
AD17
AF20
AE10
AE24
AD25
AE25
AC24
AF24
AD26
AC26
AD24
AD4
A5
D1
AD13
B1
P26
A11
E3
D26
AA18
AC18
AE17
B16
D15
F15
AB15
AA16
AC16
AE15
B14
D13
F13
E14
AB13
AA14
AC14
AE13
B12
D11
F11
E12
AB11
AA12
AC12
AE11
B10
D9
F9
E10
AB9
AA10
AC10
AE9
B8
D7
F7
E8
AB7
AA8
AC8
AE7
B6
F5
H5
G6
K5
J6
N6
L6
T5
R6
V5
U6
Y5
W6
AB5
AA6
AC6
AE5
B4
D4
F4
H4
K4
M3
U4
W4
B2
D2
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AE1
A25
C25
E20
F19
A26
G23
J23
L23
N23
R23
U23
W23
AA23
C21
C19
AD20
C17
AD18
C15
C13
AD14
C11
AD12
C9
C7
AD8
C5
AD6
AC23
AA4
E4
G4
J4
L4
AC4
V4
AE3
AF2
AF1
AE18
D5
E6
AB1
AC2
AE2
AF3
R3
B26
M4
AF26
C1
AF17
N4
RS#0
RS#1
RS#2
RSP#
TRDY#
A20M#
FERR#
FLUSH#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP#
INTR/LINT0
NMI/LINT1
INIT#
RESET#
DRDY#
DBSY#
THERMDC
THERMDA
SELFSB1
SELFSB0
EDGECTRLP
RP3#
RP2#
BPM0#
BPM1#
TDI
TCK
TDO
TMS
TRST#
PREQ#
PRDY#
CMOSREF_0
CMOSREF_1
RTTIMPDEP
GHI#
VREF_1
VREF_2
VREF_3
VREF_4
VREF_5
VREF_6
VREF_7
VREF_8
TESTLO
VCC
PLL1
PLL2
NC
NC
NC
NC
CLK0
CLK0#
TESTLO
NC
NCHCTRLP
TESTHI
NC
NC
TESTHI
NC
PICD0
PICD1
PICCLK
NC
DEP#0
DEP#1
DEP#2
DEP#3
DEP#4
DEP#5
DEP#6
DEP#7
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
VTTPWRGOOD
NC
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VCCT_1
VCCT_2
VCCT_3
VCCT_4
VCCT_5
VCCT_6
VCCT_7
VCCT_8
VCCT_9
VCCT_10
VCCT_11
VCCT_12
VCCT_13
VCCT_14
VCCT_15
VCCT_16
VCCT_17
VCCT_18
VCCT_19
VCCT_20
VCCT_21
VCCT_22
VCCT_23
VCCT_24
VCCT_25
VCCT_26
VCCT_27
VCCT_28
VCCT_29
VCCT_30
VCCT_31
VCCT_32
VCCT_33
VCCT_34
VCCT_35
VCCT_36
VCCT_37
VCCT_38
VID0
VID1
VID2
VID3
VID4
VSS
VSS
VSS
NC
NC
NC
RP6 8P4R_1.5K
1 8
2 7
3 6
4 5
R136 1.5K
12
R38 56.2_1%
12
R7 1K_0402
12
R10 1K_0402
12
R25 1K_0402
12
R9 1K_0402
12
+
C22
33UF_D2_16V
R14
19.6K
1 2
R31
1K_1%
12
R21
2K_1%
12
C26
.1UF_0402
12
C41
.1UF_0402
12
C30
.1UF_0402
12
C36
.1UF_0402
12
R26
10K_0402
1 2
C34
2200PF
12
C35
.1UF_0402
1 2
R23
1K_0402
1 2
R27
10K_0402
1 2
R29 1K_0402
12
R20
499_1%
12
C33
.1UF_0402
12
R22
1K_1%
12
C31
.1UF_0402
12
C25
.1UF_0402
12
U6
MAX6654MEE
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
NC
VCC
DXP
DXN
NC
ADD1
GND
GND NC
ADD0
ALERT
SMBDATA
NC
SMBCLK
STBY
NC
R15
0_0402
12
H_RS#0<8>
H_RS#1<8>
H_RS#2<8>
H_TRDY#<8>
H_A20M#<16>
H_IGNNE#<16>
H_SMI#<16>
H_STPCLK#<16>
H_DPSLP#<16,32>
H_INTR<16>
H_NMI<16>
H_INIT#<16>
H_DBSY#<8>
H_DRDY#<8>
H_BSEL0<14>
H_BSEL1<14>
CLK_CPU_APIC<14>
PM_CPUPERF#<16>
CLK_HCLK <14>
CLK_HCLK# <14>
CPU_VR_VID4 <6>
CPU_VR_VID1 <6>
CPU_VR_VID2 <6>
CPU_VR_VID0 <6>
CPU_VR_VID3 <6>
SMB_EC_DA1 <15,28,29,33>
SMB_EC_CK1 <15,28,29,33>
H_PWRGD<16>
H_FERR#<16>
H_RESET#<8>
ITP_TCK<7>
ITP_TDI<7>
ITP_TDO<7>
ITP_TMS<7>
ITP_TRST#<7>
ITP_PREQ#<7>
VTT_PWRGD# <14,28>
VTT_PWRGD<32>
ITP_PRDY#<7>
THRM# <29>
PICD0<16>
PICD1<16>
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
EMI Clip PAD for CPU
Layout note :
Place .22uF caps underneath balls on solder side.
Use 2~3 vias per PAD.
Place 10uF caps on the peripheral near balls.
Place close to CPU, Use 2~3 vias per PAD.
Pls used X7R(uFCPGA EMTS Rev0.7)
Pls used X7R(uFCPGA EMTS Rev0.7)
Pls used X7R(uFCPGA EMTS Rev0.7)
Pls used X7R(uFCPGA EMTS Rev0.7)
Place close to CPU,
Use 2 vias per PAD.
Layout note :
CPU Voltage ID
PM_GMUXSEL = 0 : for low Voltage A-C
1 : for high Voltage B-C
D4 D3 D2 D1 D0 CPU_Core(V) ES(before MP)
-------------------------------------------------------
0 0 1 0 1 1.50V
1.15V0 1 1 0 0
-------------------------------------------------------
D4 D3 D2 D1 D0 CPU_Core(V) QS ( MP)
-------------------------------------------------------
0 1 1.40V
1.15V0 1 1 0 0
-------------------------------------------------------
Tualatin Coppermine-T
D4 D3 D2 D1 D0 CPU_Core(V) ES(before MP)
------------------------------------------------------ -
0 0 0 0 1 1.70V
1.35V0 1 0 0 0
------------------------------------------------------ -
D4 D3 D2 D1 D0 CPU_Core(V) QS ( MP)
------------------------------------------------------ -
0
1 0
0
00
0
0
------------------------------------------------------ -
10
1.35V
1.70V0 1 1
ADY11 LA-1181
2
CPU Bypass & CPU VID
6 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
CPU_VID4
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+VTT
+VTT
+CPU_CORE
+3VS
+5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS,INC.
PAD2
PAD-2.5X3
1
PAD7
PAD-2.5X3
1
PAD6
PAD-2.5X3
1
PAD8
PAD-2.5X3
1
C234
.22UF_X7R
12
C230
.22UF_X7R
12
C146
.22UF_X7R
12
C196
.22UF_X7R
12
C216
.22UF_X7R
12
C229
.22UF_X7R
12
C205
.22UF_X7R
12
C233
.22UF_X7R
12
C142
.22UF_X7R
12
C188
.22UF_X7R
12
C228
.22UF_X7R
12
C235
.22UF_X7R
12
C212
.22UF_X7R
12
C192
.22UF_X7R
12
C194
.22UF_X7R
12
C165
.22UF_X7R
12
C231
.22UF_X7R
12
C145
.22UF_X7R
12
C143
.22UF_X7R
12
C141
.22UF_X7R
12
C174
.22UF_X7R
12
C200
10UF_10V_1206
12
C202
10UF_10V_1206
12
C28
10UF_10V_1206
12
C183
10UF_10V_1206
12
C151
10UF_10V_1206
12
C191
10UF_10V_1206
12
C24
10UF_10V_1206
12
C184
10UF_10V_1206
12
+
C29
220UF_D2_4V
12
+
C126
@220UF_D2_4V
12
+
C292
220UF_D2_4V
12
+
C153
220UF_D2_4V
12
+
C293
@220UF_D2_4V
12
+
C210
@220UF_D2_4V
12
+
C119
220UF_D2_4V
12
+
C260
220UF_D2_4V
12
C173
.22UF_X7R
12
C144
.22UF_X7R
12
C164
.22UF_X7R
12
C201
10UF_10V_1206
12
C182
10UF_10V_1206
12
+
C118
@220UF_D2_4V
12
C130
1UF
12
C135
1UF
12
C152
1UF
12
+
C37
220UF_D2_4V
12
C129
1UF
12
C248
1UF
12
C249
1UF
12
C222
1UF
12
C227
1UF
12
C199
1UF
12
C123
1UF
12
+
C283
220UF_D2_4V
12
+
C32
220UF_D2_4V
12
+
C289
220UF_D2_4V
12
C455
.01UF_0402
12
U24
SN74CBT3383
1
23
4 5
67
8 9
1011
1213
14 15
1617
18 19
2021
22 23
24
BE#
C0A0
B0 D0
C1A1
B1 D1
C2A2
GNDBX
B2 D2
C3A3
B3 D3
C4A4
B4 D4
VCC
RP7
8P4R_1K
18
27
36
45
R257
1K_0402
12
AC_VID1<17>
AC_VID3<17>
AC_VID0<17>
PM_GMUXSEL<16,32>
AC_VID2<17>
AC_VID4<17>
CPU_VR_VID3<5>
CPU_VR_VID1<5>
CPU_VR_VID4<5>
CPU_VR_VID2<5>
CPU_VR_VID0<5> CPU_VID0 <32>
CPU_VID1 <32>
CPU_VID2 <32>
CPU_VID3 <32>
CPU_VID4 <32>
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ITP PORT
COMPAL Electronics,Inc
+5VS POWER
Fan Control circuit
ADY11 LA-1181
2
ITP PORT & Fan control
7 41Friday, November 16, 2001
Title
Size Document Number Rev
Date: Sheet of
ITP_PRDY#
ITP_TDI
ITP_TRST#
ITP_TDO
ITP_PREQ#
ITP_TCK
ITP_TMS
+5VFAN
+VTT +3VS
+VTT +VTT+1.5VS +1.5VS
+12VALW
+3V
+5VALW
R85
@56.2_1%
R86
@200
R87
@10K_0402
R96
@56_1%
R95 @240
R94
240
R89
@1.5K
R249 @0_0402
R84 @240
R88
@510
R91
@39
R90
@150
R92
@200
JP18
@AMP104078-4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
U26C
74HCT08
9
10
8
R93
@39
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
D2
1SS355
2 1
D8
1N4148
21
Q10
2SA1036K
2
3
1
Q4
FMMT619
2
3
1
R235
3.48K_1%
1 2
C420
2.2UF_16V_0805
1 2
D1
1N4148
2 1
R375
10K_0402
12
JP17
53398-0310
1
2
3
C99
@1000PF_0402
R245
10K_0402
12
R415 5.6K_0402
1 2
R416 100_0402
1 2
ITP_PREQ# <5>
ITP_TRST# <5>
ITP_TDI <5>
ITP_TDO <5>
ITP_PRDY# <5>
ITP_PWROK<16,30>
ITP_TMS<5>
H_RESETX#<8>
PM_PWROK <16>
ITP_TCK<5>
CLK_ITPP# <14>CLK_ITPP<14>
EN_DFAN<28>
FAN1_TACH <28>
EC_HPOWON <28>
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Almador-M
GMCH
Host
Interface
Host
Interface
VSS
10 mils wide,length <=500 mils.
Close to Ball R6.
HUB Interface Reference
1. Place R_C and R_D in middle of Bus.
2. Place capacitors near GMCH.
Layout note :
R_C
R_D
Place Reference Circuit near GMCH
ADY11 LA-1181
2
Almador-M GMCH(1/3)
8 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
HA#[3..31]HD#[0..63]
HREQ#[0..4]
H_RS#[0..2]
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HD#3
HD#40
HD#23
HD#31
HD#6
HD#38
HD#34
HD#4
HD#19
HD#14
HD#28
HD#24
HD#17
HD#8
HD#25
HD#29
HD#21
HD#10
HD#22
HD#12
HD#26
HD#36
HD#16
HD#13
HD#15
HD#37
HD#1
HD#9
HD#0
HD#35
HD#20
HD#7
HD#41
HD#11
HD#2
HD#30
HD#27
HD#18
HD#5
HD#33
HD#32
HD#39
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD7
HUB_PD6
HUB_PD8
HUB_PD9
HUB_PD10
H_RS#2
H_RS#0
HREQ#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
H_RS#1
CLKGBOUT
CLK_GBIN
+VS_HUBREF
VGAREF
+V_AGTLREF
+1.8VS
+VS_HUBREF
+1.5VS
VGAREF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS,INC.
C178
.01UF_0402
12
R126 27.4_1%
1 2
R127 54.9_1%
1 2
R128 54.9_1%
12
C263
.1UF_0402
12
R116 80.6_1%
1 2
C185
.1UF_0402
12
C190
.1UF_0402
12
R133 @0_0402
1 2
R156 47_0402
1 2
C259
@10PF_0402
R151
@33_0402
1 2
R168
33_0402
1 2
C297
5PF_0402
C277 .01UF_0402
1 2
R138 54.9_1%
1 2
R167
@240K
12
R124
301_1%
12
R125
301_1%
12
C176
.1UF_0402
12
R142
1K_1%
12
R141
1K_1%
12
C261 470PF
1 2
R143
82.5_1%
12
R147
82.5_1%
12
C270 470PF
1 2
U7A
ALMADOR-M
U4
P1
W6
U2
U6
R1
N3
W5
V4
P3
R3
U1
V6
W4
T3
P2
V3
R2
T1
W3
U3
Y4
AA3
W1
V1
Y1
Y6
AD3
AB4
AB5
V2
Y3
Y2
AA4
AA1
AA6
AB1
AC4
AA2
AB3
AD2
AD1
AC2
AB6
AC6
AC1
AF3
AD4
AD6
AC3
AH3
AE5
AE3
AG2
AF4
AF2
AJ3
AE4
AG1
AE1
AG4
AH4
AG3
AF1
H2
E3
G3
N4
M6
F1
F2
J3
F3
P6
G1
N5
H1
P4
T4
M2
J2
L2
R4
K1
L3
L1
J1
N1
T5
H3
M3
M1
K3
R6
C1
E1
L4
G5
J4
F4
D3
D1
J6
G4
K6
M4
K5
K4
L6
H6
H4
G6
AJ4
AH5
AC19
AG26
AD24
G26
H28
H29
H27
F29
F27
E29
E28
G25
G27
H26
G29
H24
F28
AC22
F6
J23
J25
K24
AB24
AA7
J7
C2
AB23
AC23
M12
M13
M17
M18
N12
N13
N14
N15
N16
N17
N18
P13
P14
P15
P16
P17
R13
R14
R15
R16
R17
T13
T14
T15
T16
T17
U12
U13
U14
U15
U16
U17
U18
V12
V13
V17
V18
AJ5
D2
AC5
Y5
U5
P5
L5
H5
AH2
AE2
AB2
W2
T2
N2
K2
G2
AC7
AH19
AH20
AF5
G28
H25
AC26
AD22
AE28
AH24
AF25
AF27
AH26
G8
AD7
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_CPURST#
H_ADS#
H_BNR#
H_BPRI#
H_DBSY#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
CLK_HT
CLK_HT#
CLK_DREF
CLK_GBIN
CLK_GBOUT
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
HUB_PSTRB
HUB_REF
HUB_PSTRB#
DVO_RCOMP
SM_RCOMP
HUB_RCOMP
AGP_REF
AGP_RCOMP/DVOBC_RCOMP
RESET#
H_GTLREF1
H_GTLREF0
H_GTLRCOMP
VSS
VSS
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS_H0
VSS_H1
VSS_H2
VSS_H3
VSS_H4
VSS_H5
VSS_H6
VSS_H7
VSS_H8
VSS_H9
VSS_H10
VSS_H11
VSS_H12
VSS_H13
VSS_H14
VSS_H15
VSS_H16
VSSPCMOS_LM0
VSSPCMOS_LM1
VSSPCMOS_LM2
VSSP_HUB0
VSSP_HUB1
VSSP_IO0
VSSP_IO1
VSSP_IO2
VSSP_DVO0
VSSP_DVO1
VSSP_DVO2
VSSA_DAC
VSSA_CPLL
VSSA_HPLL
HA#[3..31] <4>HD#[0..63]<4>
HREQ#[0..4] <4>
H_RESET# <5>
HADS# <4>
HBNR# <4>
HBPRI# <4>
H_DBSY# <5>
HDEFER# <4>
H_DRDY# <5>
HIT# <4>
HITM# <4>
HLOCK# <4>
H_TRDY# <5>
HUB_PD[0..10]<16>
HUB_PSTRB<16>
HUB_PSTRB#<16>
H_RS#[0..2] <5>
CLK_GHT <14>
CLK_GHT# <14>
CLK_DREF <14>
CLK_GBIN <14>
CLK_GBOUT <14>
PCIRST# <15,16,20,21,26,27,28>
H_RESETX# <7>
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
System Memory Reference
Memory
Almador-M
GMCH
Power
VSS
Layout note :
Layout note
SM_OCLK_RCLK trace length 150mil +-50mil
System
XOR
System
VSS
SDRAM
Layout Note:
F20,E20,F12,E11
ADD Testpoint
for Factory
SDRAM
Close to Ball E5 and F24
near pin A24
Memory
Layout note
Cap near pin A8
Place resistors near GMCH
Layout note :
Place resistors near GMCH
Layout note :
Cap
near pin A12
ADY11 LA-1181
2
Almador-M GMCH(2/3)
9 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
SM_CKE2
SM_CKE3
MMA3
MMA9
MMA5
MMA12
MMA1
SM_D_RAS#
MMA0
MMA11
MMA2
MMA6
MMA7
SM_D_BA1
SM_OCLK_RCLK
SM_D_CLK2
SM_CKE0
SM_CS#3
SM_D_BA0
SM_D_CLK0
MMA8
MMA4
MMA10
SM_CKE1
SM_CS#2
SM_D_WE#
SM_CS#1
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7
SM_CS#0
SM_DQM1
SM_DQM2
SM_DQM0
SM_D_CAS#
SM_DQ56
SM_DQ31
SM_DQ37
SM_DQ10
SM_DQ42
SM_DQ45
SM_DQ16
SM_DQ17
SM_DQ22
SM_DQ2
SM_DQ38
SM_DQ46
SM_DQ33
SM_DQ23
SM_DQ25
SM_DQ61
SM_DQ49
SM_DQ39
SM_DQ54
SM_DQ26
SM_DQ4
SM_DQ21
SM_DQ18
SM_DQ1
SM_DQ40
SM_DQ9
SM_DQ20
SM_DQ5
SM_DQ60
SM_DQ55
SM_DQ28
SM_DQ27
SM_DQ8
SM_DQ14
SM_DQ7
SM_DQ50
SM_DQ47
SM_DQ19
SM_DQ[0..63]
SM_DQ0
SM_DQ15
SM_DQ11
SM_DQ24
SM_DQ41
SM_DQ34
SM_DQ59
SM_DQ57
SM_DQ36
SM_DQ53
SM_DQ58
SM_DQ51
SM_DQ32
SM_DQ63
SM_DQ48
SM_DQ43
SM_DQ13
SM_DQ29
SM_DQ52
SM_DQ62
SM_DQ12
SM_DQ44
SM_DQ35
SM_DQ30
SM_DQ6
SM_DQ3
SM_D_CLK1
SM_D_CLK3
MMA12
MMA1
MMA3
MMA0
MMA11
MMA10
MMA9
MMA7
MMA6
MMA5
MMA8
MMA4
MMA2
SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8
SM_MA9
SM_MA10
SM_MA11
SM_MA12
+3V
+V_SMREF
+V_SMREF
+3V
+3V
+VTT
+3V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS,INC.
R122
249_1%
12
R123
49.9_1%
12
R120 10_0402
1 2
R111 10_0402
1 2
R114 10_0402
1 2
R118 10_0402
1 2
C157
.1UF_0402
12
C132 .1UF_0402
1 2
R115 10_0402
1 2
C160
.1UF_0402
12
C134
@22PF_0402
12
C131
.1UF_0402
12
U7B
ALMADOR-M
D29
C29
D27
C27
A27
B26
E24
C25
E23
B25
C23
F22
B23
C22
E21
B22
C12
D10
C11
A10
C10
C8
A7
E9
C7
E8
A5
F8
C5
D6
B4
C4
E27
C28
B28
E26
C26
D25
A26
D24
F23
A25
G22
D22
A23
F21
D21
A22
F11
A11
B11
F10
B10
B8
D9
B7
F9
A6
C6
D7
B5
E6
A4
D4
A20
B20
B19
C19
A18
A19
C17
C18
B17
A17
A16
C15
C14
F20
E20
F12
E11
C21
F19
E12
A12
B16
C16
F18
D18
D13
D12
E18
F17
F14
F13
E17
F16
D16
D15
E15
E14
A15
B2
B14
A3
A14
C3
A13
C9
C13
A9
B13
A8
C20
D19
A21
A24
C24
E5
F24
AD8
AD9
AD10
AJ21
AE8
AE9
AE10
AE11
AE12
AE13
AE17
AE19
AH21
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AG7
AG15
AG16
AG21
AH6
AH8
AH9
AH11
AH12
AH14
AH17
AH18
B3
B6
B9
B12
B15
B18
B21
B24
B27
E7
E10
E13
E16
E19
E22
E25
G9
G21
E4
D28
K28
N28
T28
W28
AB28
L25
P25
U25
Y25
AE20
G24
H7
H23
K7
K23
L7
N6
T6
W7
Y7
AB7
M24
P24
T24
V24
Y23
M14
M15
M16
P12
R12
T12
P18
R18
T18
SM_DQ0
SM_DQ1
SM_DQ2
SM_DQ3
SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7
SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59
SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63
SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8
SM_MA9
SM_MA10
SM_MA11
SM_MA12
NC
NC
NC
NC
VSS
VSS
VCC_SM
VCC_SM
SM_BA0
SM_BA1
SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7
SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3
VCCQ_SM
VSS
SM_CLK0
SM_CLK1
SM_CLK2
SM_CLK3
VSS
VSS
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
VSS
VCC_SM
SM_RAS#
SM_CAS#
SM_WE#
SM_OCLK
SM_RCLK
SM_VREF0
SM_VREF1
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSSP_SM0
VSSP_SM1
VSSP_SM2
VSSP_SM3
VSSP_SM4
VSSP_SM5
VSSP_SM6
VSSP_SM7
VSSP_SM8
VSSP_SM9
VSSP_SM10
VSSP_SM11
VSSP_SM12
VSSP_SM13
VSSP_SM14
VSSP_SM15
VSSP_SM16
VSSP_SM17
VSSP_SM18
VSSP_SM19
VSSP_AGP0
VSSP_AGP1
VSSP_AGP2
VSSP_AGP3
VSSP_AGP4
VSSP_AGP5
VSSP_AGP6
VSSP_AGP7
VSSP_AGP8
VSSA_DPLL0
VSSA_DPLL1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R113 10_0402
1 2
R119 10_0402
1 2
R109 10_0402
1 2
R110 10_0402
1 2
RP4
8P4R_10
1 8
2 7
3 6
4 5
RP5
8P4R_10
1 8
2 7
3 6
4 5
RP3
8P4R_10
1 8
2 7
3 6
4 5
R112 10_0402
1 2
SM_CKE3 <13>
SM_DQM[0..7] <12,13>
SM_CKE2 <13>
SM_CKE0 <12>
SM_CKE1 <12>
SM_CS#1 <12>
SM_BA1 <12,13>
SM_BA0 <12,13>
SM_WE# <12,13>
SM_CS#3 <13>
SM_CAS# <12,13>
SM_CS#2 <13>
SM_RAS# <12,13>
SM_CS#0 <12>
SM_DQ[0..63] <12,13>
SMD_CLK3 <13>
SMD_CLK2 <13>
SMD_CLK1 <12>
SMD_CLK0 <12>
SM_MA[0..12] <12,13>
VSSA_DPLL1 <10>
VSSA_DPLL0 <10>
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Almador-M
GMCH
Place close to AE16,
AE15 of GMCH
Layout note :
AGP
Interface
Local Memory
Interface
Local Memory
Interface
Interface
Display
Power
Interface
(DVOB/DVOC & ZV port)
(DVOA port)
AGP_PAR : Strapping option for SW detection of
AGP or DVO device.
0 -> DVO B/C device
1 -> AGP device
Layout Note:
AE24,AJ25
ADD Testpoint
for Factory
XOR
1. Place R_I and R_J near GMCH.
R_I
R_J
DVOA_D1 IOQD=1 IOQD=8
DVOA_D5 Desktop Mobile
DVOA_D6 Dual Ended Term Single Ended Term
Strap Name Low High
37.4_1% resistors and cap
must be placed after RGB
pi filter near CRT
connector.
1.5V level clock
ADY11 LA-1181
2
Almador-M GMCH(3/3)
10 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
VCCA_DPLL
DVOA_CLKIN
DVOA_INTR#
DVOA_D6
DVOA_D5
DVOA_D1
DVOA_D1
DVOA_D5
DVOA_D6
VCCADPLL
AGP_PAR
DVOA_INTR#
DVOA_CLKIN
AGP_PAR
AGP_FRAME#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_DEVSEL#
AGP_DEVSEL#
DVO_STALL
AGP_WBF#
AGP_RBF#
AGP_PIPE#
AGP_REQ#
AGP_GNT#
AGP_REQ#
AGP_GNT#
AGP_PIPE#
AGP_WBF#
AGP_RBF#
AGP_ST0
AGP_ST1
AGP_ST2
DVO_INT#
AGP_ST0
AGP_ST1
AGP_ST2
AGP_IRDY#
DVO_INT#
DVO_STALL
CRT_R#
CRT_G#
CRT_B#
CRT_R#
CRT_G#
CRT_B#
DPMS_CLK
VCCA_DPLL0
VCCA_DPLL1
AGP_FRAME#
AGP_TRDY#
AGP_STOP#
+VTT
+VTT
+1.8VS
+VTT
+VS_RIMMREF
+1.8VS
+3V
+1.5VS
+3V
+1.5VS
+VTT
+3V
+1.8VS
+1.5VS
+3VS
+1.5VS
+1.8VS
+VS_RIMMREF
+3VS
+1.5VS
+3VS
+1.5VS
+1.5VS
+VTT
+1.5VS
+3VS
+3VS
+3VS
+1.8VS
+1.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS,INC.
C278
68PF
12
C281 .1UF_0402
12
C170
.1UF_0402
12
C266
68PF
12
R169
10K_0402
1 2
R170
10K_0402
1 2
R132 330
1 2
C632
.01UF_0402
12
C290
.1UF_0402
12
R166
10K_0402
1 2
R146 @2.2K
1 2
R144 2.2K
1 2
R173 @2.2K
1 2
R172 255_1%
1 2
C167
.1UF_0402
12
R162
10K_0402
1 2
R157
100K_0402
1 2
R164
100K_0402
1 2
R154
2K_1%
12
R159
576_1%
12
R152 10K_0402
1 2
R137 8.2K_0402
1 2
R153
10K_0402
1 2
R145 10K_0402
1 2
L49
FBM-11-201209-601T
1 2
R176 0_0402
1 2
RP9
@8P4R_8.2K
1 8
2 7
3 6
4 5
R150 @8.2K_0402
1 2
L45
FBM-11-201209-601T
1 2
R117 0_0402
1 2
C294
.1UF_0402
12
R131 100K_0402
1 2
R155 @8.2K_0402
1 2
R163 @8.2K_0402
1 2
R149 @8.2K_0402
1 2
R160 10K_0402
1 2
R161 10K_0402
1 2
R417 8.2K_0402
1 2
U7C
ALMADOR-M
AA29
AA24
AA25
Y24
Y27
Y26
W24
Y28
AB26
AB29
AB25
AC28
AC29
AB27
L29
L28
U29
U28
AA27
AA28
R29
P26
P27
N25
R28
AC27
AD29
P28
L27
P29
R27
T25
J29
J28
K26
K25
L26
J27
K29
K27
M29
M28
L24
M27
N29
M25
N26
N27
R25
R24
T29
T27
T26
U27
V27
V28
U26
V29
W29
V25
W26
W25
W27
Y29
AD21
AD20
AJ27
AD27
AE27
AH28
AG29
AF29
AE29
AH27
AG28
AF28
AD28
AF23
AF22
AD25
AC25
AG24
AJ24
AJ22
AH22
AG22
AJ23
AH23
AG23
AE23
AE24
AJ25
AH25
AG25
AJ26
AD26
AE26
AE21
AE22
AG17
AJ17
AG18
AJ18
AG19
AJ19
AG20
AJ20
AJ11
AH10
AJ10
AG10
AJ9
AG9
AJ8
AG8
AH7
AF7
AJ7
AG11
AJ12
AG12
AH13
AG13
AJ13
AG14
AJ14
AJ6
AG6
AD14
AE14
AC24
AH15
AJ15
AJ16
AH16
V14
V15
V16
AE16
AE15
AD15
AD16
AE25
AD23
J24
F26
N24
W23
J26
M26
R26
V26
AA26
L23
AA23
U24
AE6
G7
G10
G20
AF6
AE7
AC9
AC8
AF26
AG27
F5
J5
M5
R5
V5
AA5
AD5
AG5
E2
D5
D8
D11
D14
D17
D20
D23
D26
F7
F15
G11
G19
G23
AC10
AC11
AD11
AD12
AD13
AE18
AD17
AD18
AD19
AC20
F25
AC21
AF21
AF24
AGP_SBA0/ZV_D8
AGP_SBA1/ZV_D7
AGP_SBA2/ZV_D6
AGP_SBA3/ZV_D5
AGP_SBA4/ZV_D2
AGP_SBA5/ZV_D1
AGP_SBA6/ZV_D0
AGP_SBA7/ZV_HREF
AGP_PIPE#/ZV_D10
AGP_WBF#/ZV_D9
AGP_RBF#/ZV_D11
AGP_ST0/ZV_D14
AGP_ST1/ZV_D13
AGP_ST2/ZV_D12
AGP_ADSTB0/DVOB_CLK
AGP_ADSTB#0/DVOB_CLK#
AGP_ADSTB1/DVOC_CLK
AGP_ADSTB#1/DVOC_CLK#
AGP_SBSTB/ZV_D4
AGP_SBSTB#/ZV_D3
AGP_FRAME#/M_DDC2_DATA
AGP_IRDY#/M_I2C_CLK
AGP_TRDY#/M_DDC2_CLK
AGP_STOP#
AGP_DEVSEL#/M_I2C_DATA
AGP_REQ#/ZV_CLK
AGP_GNT#/ZV_D15
AGP_PAR
AGP_CBE#0/DVOB_D7
AGP_CBE#1/DVOB_BLANK#
AGP_CBE#2/ZV_VSYNC
AGP_CBE#3/DVOC_D5
AGP_AD0/DVOB_HSYNC
AGP_AD1/DVOB_VSYNC
AGP_AD2/DVOB_D1
AGP_AD3/DVOB_D0
AGP_AD4/DVOB_D3
AGP_AD5/DVOB_D2
AGP_AD6/DVOB_D5
AGP_AD7/DVOB_D4
AGP_AD8/DVOB_D6
AGP_AD9/DVOB_D9
AGP_AD10/DVOB_D8
AGP_AD11/DVOB_D11
AGP_AD12/DVOB_D10
AGP_AD13/DVOBC_CLKINT#
AGP_AD14/DVOB_FLD/STL
AGP_AD15
AGP_AD16/DVOC_VSYNC
AGP_AD17/DVOC_HSYNC
AGP_AD18/DVOC_BLANK#
AGP_AD19/DVOC_D0
AGP_AD20/DVOC_D1
AGP_AD21/DVOC_D2
AGP_AD22/DVOC_D3
AGP_AD23/DVOC_D4
AGP_AD24/DVOC_D7
AGP_AD25/DVOC_D6
AGP_AD26/DVOC_D9
AGP_AD27/DVOC_D8
AGP_AD28/DVOC_D11
AGP_AD29/DVOC_D10
AGP_AD30/DVOC_INT#/DPMS_CLK
AGP_AD31/DVOC_FLD/STL
DVO_BLANK#
DVO_CLKIN
DAC_REFSET
IO_DDC1DATA
IO_DDC1CLK
DAC_BLUE
DAC_GREEN
DAC_RED
DAC_VSYNC
DAC_BLUE#
DAC_GREEN#
DAC_RED#
DAC_HSYNC
DVO_VSYNC
DVO_HSYNC
IO_I2CCLK
IO_I2CDATA
DVO_CLK#
DVO_CLK
DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8
DVO_D9
DVO_D10
DVO_D11
IO_DDC2DATA
IO_DDC2CLK
DVO_INTR#
DVO_FIELD
LM_DQA0
LM_DQA1
LM_DQA2
LM_DQA3
LM_DQA4
LM_DQA5
LM_DQA6
LM_DQA7
LM_DQB0
LM_DQB1
LM_DQB2
LM_DQB3
LM_DQB4
LM_DQB5
LM_DQB6
LM_DQB7
LM_CMD
LM_SCK
LM_SIO
LM_RQ0
LM_RQ1
LM_RQ2
LM_RQ3
LM_RQ4
LM_RQ5
LM_RQ6
LM_RQ7
LM_RCLK
LM_GCLK
LM_RAMREF0
LM_RAMREF1
AGP_BUSY#
LM_CTM
LM_CTM#
LM_CFM
LM_CFM#
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VCCP_IO
VCCP_IO
VCCP_HUB
VCCP_HUB
VCCQ_AGP
VCCQ_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCA_HPLL
VCCA_CPLL
VCCQ_SM
VCCQ_SM
VCCPCMOS_LM
VCCPCMOS_LM
VCCPCMOS_LM
VCCPCMOS_LM
VCCA_DAC
VCCA_DAC
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCCA_DPLL0
VCCA_DPLL1
VCCP_DVO
VCCP_DVO
VCCP_DVO
R129 @100K_0402
1 2
R418 37.4_1%
1 2
R419 37.4_1%
1 2
R420 37.4_1%
1 2
R422
604_1%
1 2
R421
732_1%
12
U47
TC7SH14
1
2
3
4
5
NC
A
GND
Y
VCC
+
C180
100UF_D2_6.3V
12
+
C302
100UF_D2_6.3V
12
R430 8.2K_0402
1 2
R431 8.2K_0402
1 2
R432 @8.2K_0402
1 2
T52
1
T53
1
C627
@.1UF_0402
1 2
C628
@.1UF_0402
1 2
C629
@.1UF_0402
1 2
AGP_BUSY# <16>
DVO_D0<15>
DVO_D1<15>
DVO_D2<15>
DVO_D3<15>
DVO_D4<15>
DVO_D5<15>
DVO_D6<15>
DVO_HSYNC<15>
DVO_VSYNC<15>
DVO_D8<15>
DVO_D7<15>
DVO_D9<15>
DVO_D10<15>
DVO_D11<15>
DVO_CLK<15>
DVO_CLK#<15>
DVO_BL#<15>
CRT_R <15>
CRT_G <15>
CRT_B <15>
CRT_VSYNC <15>
CRT_HSYNC <15>
3VDDCCL <15>
3VDDCDA <15>
VSSA_DPLL1 <9>
LTVCK <15>
LTVDA <15>
DVO_STALL<15>
VSSA_DPLL0 <9>
RTCCLK<16>
GMBSCL <15>
GMBSDA <15>
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Compal Electronics, Inc.
Layout note :
Distribute as close as possible
to GMCH Processor Quadrant .
Layout note :
Distribute as close as possible
to VCCPCMOS_LM. (GMCH pin
AF6, AE7, AC9, AC8)
Layout note :
Distribute as close as possible
to GMCH Local Memory Quadrant .
Distribute as close as possible
to GMCH AGP/DVO Quadrant .
Layout note :
Distribute as close as possible
to GMCH System Memory Quadrant .
Layout note :
Layout note :
Distribute as close as possible
to IO Quadrant .
.1UF Cap Used X7R
ADY11 LA-1181
2
GMCH-M Decoupling
11 41Friday, November 16, 2001
Title
Size Document Number Rev
Date: Sheet of
+VTT
+VTT
+VTT
+VTT
+VTT
+VTT
+3V
+3V
+1.5VS
+1.8VS
+VTT
+3V
+1.8VS
C206
.1UF_0402
12
C220
.1UF_0402
12
C177
.1UF_0402
12
C207
.1UF_0402
12
C224
.1UF_0402
12
C238
.1UF_0402
12
C169
.1UF_0402
12
C208
.1UF_0402
12
C198
.1UF_0402
12
C193
.1UF_0402
12
C237
.1UF_0402
12
C247
.1UF_0402
12
C225
.1UF_0402
12
C291
.1UF_0402
12
C158
.1UF_0402
12
C203
.1UF_0402
12
C239
.1UF_0402
12
C256
.1UF_0402
12
C219
.1UF_0402
12
C286
.1UF_0402
12
+
C27
220UF_D2_4V
12
+
C23
220UF_D2_4V
12
C282
.1UF_0402
12
C288
@.1UF_0402
12
C269
@.01UF_0402
12
C268
.01UF_0402
12
C213
.1UF_0402
12
C223
.1UF_0402
12
C271
.1UF_0402
12
C236
.1UF_0402
12
C163
.1UF_0402
12
C274
.1UF_0402
12
C204
.1UF_0402
12
C246
.1UF_0402
12
C156
.1UF_0402
12
C258
82PF
12
C279
.1UF_0402
12
C254
.1UF_0402
12
C275
.1UF_0402
12
C252
82PF
12
+
C304
22UF_10V_1206
12
+
C273
22UF_10V_1206
12
C296
82PF
12
C214
.1UF_0402
12
C255
.1UF_0402
12
C159
.1UF_0402
12
C168
.1UF_0402
12
C162
.1UF_0402
12
C140
.1UF_0402
12
+
C133
22UF_10V_1206
12
C171
82PF
12
C154
.1UF_0402
12
C139
.1UF_0402
12
C179
82PF
12
C150
.1UF_0402
12
C166
82PF
12
C147
.1UF_0402
12
C148
.1UF_0402
12
C284
82PF
12
C149
.1UF_0402
12
C138
.1UF_0402
12
C280
.1UF_0402
12
+
C122
@220UF_D2_4V
12
C276
.1UF_0402
12
+
C127
@220UF_D2_4V
12
C251
.1UF_0402
12
C264
.1UF_0402
12
C265
.1UF_0402
12
C257
.1UF_0402
12
C181
.1UF_0402
12
C295
.1UF_0402
12
C197
.1UF_0402
12
C221
.1UF_0402
12
C267
.1UF_0402
12
C243
.1UF_0402
12
C245
.1UF_0402
12
+
C125
22UF_10V_1206
12
C155
.1UF_0402
12
C137
.1UF_0402
12
C187
.1UF_0402
12
C244
.1UF_0402
12
C242
.1UF_0402
12
C232
.1UF_0402
12
C272
82PF
12
C250
.1UF_0402
12
C240
.1UF_0402
12
C285
82PF
12
C209
.1UF_0402
12
C262
.1UF_0402
12
C299
82PF
12
C287
.1UF_0402
12
C306
10UF_10V_1206
12
C300
10UF_10V_1206
12
+
C303
220UF_D2_4V
12
C186
.01UF_0402
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
Layout note :
One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 0) pin .
DIMM0
Place closely to DIMM0
System S MBus Select
SM_SEL#
0=SODIMM0 ;
1=SODIMM1
ADY11 LA-1181
2
SO-DIMM SLOT0 /Decoupling & DIMM Select
12 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
SM_DQM4
SM_MA0
SM_MA1
SM_MA2
SMD_CLK0
SM_RAS#
SM_MA9
SODIMM0_SMDAT0
SM_DQM0
SM_MA3
SM_CKE1
SM_MA12
SM_BA0
SM_BA1
SM_MA11
SM_DQM3
SM_DQM5
SM_DQM6
SM_DQM7
SM_DQM2
SM_DQM1
SM_MA6
SM_MA8
SM_MA10
SM_MA7
SM_MA4
SM_MA5
SM_DQ13
SM_DQ9
SM_DQ30
SM_DQ25
SM_DQ24
SM_DQ1
SM_DQ62
SM_DQ4
SM_DQ34
SM_DQ3
SM_DQ29
SM_DQ44
SM_DQ2
SM_DQ7
SM_DQ8
SM_DQ31
SM_DQ58
SM_DQ27
SM_DQ5
SM_DQ35
SM_DQ50
SM_DQ43
SM_DQ60
SM_DQ14
SM_DQ52
SM_DQ47
SM_DQ11
SM_DQ59
SM_DQ33
SM_DQ38
SM_DQ54
SM_DQ6
SM_DQ61
SM_DQ48
SM_DQ42
SM_DQ53
SM_DQ17
SM_DQ12
SM_DQ32
SM_DQ46
SM_DQ26
SM_DQ23
SM_DQ40
SM_DQ37
SM_DQ28
SM_DQ22
SM_DQ56
SM_DQ57
SM_DQ20
SM_DQ51
SM_DQ63
SM_DQ19
SM_DQ49
SM_DQ10
SM_DQ15
SM_DQ0
SM_DQ36
SM_DQ16
SM_DQ21
SM_DQ18
SM_DQ41
SM_DQ55
SM_DQ45
SMD_CLK1
SM_WE#
SM_CS#0
SM_CS#1
SODIMM_SMCLK
SM_CKE0
SM_CAS#
SM_DQ39
SMD_CLK1SMD_CLK0
SODIMM_SMCLK
SM_SEL
SM_SEL#
SM_SEL
SM_SEL#
+3V
+3V
+3V +3V
+5VS
+3V
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS,INC.
C329
.1UF_0402
12
C347
.1UF_0402
12
C69
.1UF_0402
12
C71
.1UF_0402
12
+
C316
22UF_10V_1206
12
C335
.1UF_0402
12
C331
.1UF_0402
12
C334
.1UF_0402
12
C327
.1UF_0402
12
C328
.1UF_0402
12
C72
.1UF_0402
12
C68
.1UF_0402
12
C330
.1UF_0402
12
C70
.1UF_0402
12
C65
.1UF_0402
12
C333
.1UF_0402
12
C67
.1UF_0402
12
C66
.1UF_0402
12
C332
.1UF_0402
12
JP21
SO-DIMM144-Reverse
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CKE0#DQMB0
CKE1#/DQMB1
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RFU/DQ64
RFU/DQ65
RFU/CLK0
VCC
RFU/RAS#
WE#
RE0#/S0#
RE1#/S1#
RFU/EDO_OE#
VSS
RFU/DQ66
RFU/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/DQMB2
CE3#/DQMB3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQMB4/CE4#
DQMB5/CE5#
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
DQ68/RFU
DQ69/RFU
CKE0/RFU
VCC
CAS#/RFU
CKE1/RFU
A12/RFU
A13/RFU
CLK1/RFU
VSS
DQ70/RFU
DQ71/RFU
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQMB6/CE6#
DQMB7/CE7#
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
R50 0_0402
1 2
C326
@15PF
12
C73
@15PF
12
R49
@10
12
R185
@10
12
G
D
S
Q18
2N7002
2
13
G
D
S
Q16
2N7002
2
13
G
D
S
Q19
2N7002
2
13
R183
10K_0402
12
R184
10K_0402
12
R48
10K_0402
12
G
D
S
Q17
2N7002
2
13
R268
10K_0402
12
SM_DQ[0..63] <9,13>
SM_DQM4<9,13>
SM_DQM5<9,13>
SM_DQM6<9,13>
SM_DQM7<9,13>
SM_DQM3 <9,13>
SM_DQM2 <9,13>
SM_DQM1 <9,13>
SM_DQM0 <9,13>
SM_MA0<9,13>
SM_MA1<9,13>
SM_MA2<9,13>
SM_MA6<9,13>
SM_MA8<9,13>
SM_MA10<9,13>
SM_MA9<9,13>
SM_MA7 <9,13>
SM_MA12 <9,13>
SM_MA3 <9,13>
SM_MA4 <9,13>
SM_MA5 <9,13>
SMD_CLK0<9>
SMD_CLK1 <9>
SM_RAS#<9,13>
SM_WE#<9,13>
SM_CS#0<9>
SM_CS#1<9>
SM_MA11 <9,13>
SM_BA1 <9,13>
SM_BA0 <9,13>
SM_CAS# <9,13>
SM_CKE1 <9>
SM_CKE0 <9>
SMB_DATA<14,16,18> SODIMM1_SMDAT1 <13>
SODIMM_SMCLK <13>SMB_CLK<14,16,18>
SM_SEL#<16>
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
EMI Clip PAD for Memory Door
DIMM1
Place closely to DIMM1
Layout note :
One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 1) pin .
ADY11 LA-1181
2
SO-DIMM SLOT1 & Decoupling
13 41Friday, November 16, 2001
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
SM_DQM4
SM_MA3
SM_CKE3
SM_MA12
SM_BA0
SM_BA1
SM_MA11
SM_DQM7
SM_DQM6
SM_DQM5
SM_MA7
SM_MA4
SM_MA5
SM_DQ63
SM_DQ48
SM_DQ57
SM_DQ42
SM_DQ53
SM_DQ32
SM_DQ54
SM_DQ39
SM_DQ40
SM_DQ34
SM_DQ55
SM_DQ43
SM_DQ33
SM_DQ56
SM_DQ35
SM_DQ47
SM_DQ61
SM_DQ52
SM_DQ46
SM_DQ36
SM_DQ45
SM_DQ58
SM_DQ44
SM_DQ38
SM_DQ51
SM_DQ37
SM_DQ60
SM_DQ62
SM_DQ49
SM_DQ59
SM_DQ50
SM_DQ41
SMD_CLK3
SODIMM_SMCLK
SM_CKE2
SM_CAS#
SM_DQM0
SM_MA0
SM_MA1
SM_MA2
SMD_CLK2
SM_RAS#
SM_MA9
SODIMM1_SMDAT1
SM_DQM1
SM_DQM2
SM_DQM3
SM_MA6
SM_MA8
SM_MA10
SM_DQ17
SM_DQ27
SM_DQ16
SM_DQ22
SM_DQ11
SM_DQ18
SM_DQ12
SM_DQ19
SM_DQ31
SM_DQ15
SM_DQ5
SM_DQ29
SM_DQ28
SM_DQ20
SM_DQ3
SM_DQ6
SM_DQ23
SM_DQ8
SM_DQ7
SM_DQ2
SM_DQ30
SM_DQ9
SM_DQ21
SM_DQ13
SM_DQ25
SM_DQ1
SM_DQ26
SM_DQ4
SM_DQ24
SM_DQ14
SM_DQ0
SM_DQ10
SM_WE#
SM_CS#2
SM_CS#3
SMD_CLK2 SMD_CLK3
+3V +3V
+3V
+3V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS,INC.
PAD10
PAD-2.5X3
1
PAD12
PAD-2.5X3
1
PAD18
PAD-2.5X3
1
PAD14
PAD-2.5X3
1
PAD19
PAD-2.5X3
1
PAD11
PAD-2.5X3
1
PAD16
PAD-2.5X3
1
JP13
SO-DIMM144-Normal
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CKE0#DQMB0
CKE1#/DQMB1
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RFU/DQ64
RFU/DQ65
RFU/CLK0
VCC
RFU/RAS#
WE#
RE0#/S0#
RE1#/S1#
RFU/EDO_OE#
VSS
RFU/DQ66
RFU/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/DQMB2
CE3#/DQMB3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQMB4/CE4#
DQMB5/CE5#
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
DQ68/RFU
DQ69/RFU
CKE0/RFU
VCC
CAS#/RFU
CKE1/RFU
A12/RFU
A13/RFU
CLK1/RFU
VSS
DQ70/RFU
DQ71/RFU
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQMB6/CE6#
DQMB7/CE7#
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
R46 0_0402
1 2
R47
@10
12
C64
@15PF
12
C45
@15PF
12
R44
@10
12
C54
.1UF_0402
12
C59
.1UF_0402
12
C62
.1UF_0402
12
C49
.1UF_0402
12
C61
.1UF_0402
12
C46
.1UF_0402
12
C60
.1UF_0402
12
C47
.1UF_0402
12
+
C44
22UF_10V_1206
12
C56
.1UF_0402
12
C52
.1UF_0402
12
C51
.1UF_0402
12
C55
.1UF_0402
12
C48
.1UF_0402
12
C50
.1UF_0402
12
C63
.1UF_0402
12
C53
.1UF_0402
12
C57
.1UF_0402
12
C58
.1UF_0402
12
SMD_CLK3 <9>
SM_CKE3 <9>
SM_CKE2 <9>
SMD_CLK2<9>
SM_CS#2<9>
SM_CS#3<9>
SM_DQ[0..63] <9,12>
SM_MA2<9,12>
SM_MA1<9,12>
SM_MA0<9,12>
SM_DQM1<9,12>
SM_DQM0<9,12>
SM_WE#<9,12>
SM_RAS#<9,12>
SM_MA10<9,12>
SM_MA6<9,12>
SM_MA8<9,12>
SM_MA9<9,12>
SM_DQM2<9,12>
SM_BA1 <9,12>
SM_BA0 <9,12>
SM_MA11 <9,12>
SM_MA7 <9,12>
SM_DQM7 <9,12>
SM_DQM6 <9,12>
SM_MA12 <9,12>
SM_CAS# <9,12>
SM_DQM5 <9,12>
SM_DQM4 <9,12>
SM_MA4 <9,12>
SM_MA3 <9,12>
SM_MA5 <9,12>
SODIMM1_SMDAT1<12> SODIMM_SMCLK <12>
SM_DQM3<9,12>
Loading...