Dell COMPAL LA-1181 Schematics

A

1 1

2 2

B

C

D

E

Tang/TangBTO Schematics Document

uFCBGA/uFCPGA Coppermine-T or Tualatin

2001-11-16

3 3

REV: 2.0

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ADY11 LA-1181

Cover Sheet

E

1 41Friday, November 16, 2001

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

Compal confidential

B

C

D

E

Block Diagram

Model Name :ADY11(Tang)
File Name : LA-1181

CPU Bypass

1 1

Fan Control

page 7

& CPUVID

page 6

ITP Connector

page 7

Coppermine-T or
Tualatin

uFCBGA/uFCPGA CPU

page 4,5

PSB

133MHz

HD#(0..63)HA#(3..31)

Thermal Sensor

Clock Generator

MAX6654 W320-04

page 5

page 14

CRT Connector

page 15

DVO Link

VCH
Board

2 2

VCH Conn

PCI debug
port

page 27

page 15

PCI BUS

IDSEL:AD17
(PIRQA#,GNT# 3,REQ#3)

LAN
3COM -3C920

page 20

A

RJ45

page 30

page 31

page 20

3 3

Power On/Off
Reset & RTC

DC/DC Interface
Suspend

4 4

Power Circuit
DC/DC

page
32,33,34,35,36,37

IDSEL:AD20
(PIRQA/B#,GN T#2,REQ#2)

CardBus Controller

OZ 6912

Slot 0

page 22

14M_5V

Touch Pad

EC I/O Buffer

BIOS

EC 87570

page 27

page 29

page 29 page 27

B

page 21

page 28

3.3V 33MHz

X BUS

Int.KBD

PS/2 conn

page 29

Almador-M
GMCH-M

625 BGA

page 8,9,10

HUB Link

1.8V 66MHz

ICH3-M
421 BGA

page 16,17

LPC BUS

3.3V 33MHz

NS PC87393

LPC to X-BUS
& Super I/O

page 26

SIOPIO

page 27 page 27

FDD

page 19

C

Memory BUS

3.3V 133MHz

3.3V 48MHz

3.3V 24.576MHz

3.3V ATA100

IDE Connector
(HDD/CR-ROM)

SO-DIMM X2

BANK 0, 1, 2, 3

USB conn

page 19

D

page 12,13

page 30

AMP& Phone
Jack

AC-LINK

AC97
Codec

STAC9700

page 23

page 24

Title

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

MDC

page 25

Compal Electronics, Inc.

Block Diagram

E

2 41Friday, November 16, 2001

2

Note:"@" means all model depop
"#" means Tang depop

5

4

3

2

1

Model

Function

TangM2P3

SST-Build

D D

FDD

PS/2

Series port

Parallel port

RJ45

3Com Lan
chipset(3C920)

Note:"@" means all model depop
"&" means M2P3 depop

C C

"#" means Tang depop

YES

YES

NO

YES

YES

NO

YES

NO

YES

NO

NOYES

SST2-Build

PT-Build

ST-Build

FW82830MG FW82801CAM

QB63QB88

QC34 QB62

QC34

QB62 Lot:M28010

QC34 QC42

3C920-ST06CHIPS Rev CHIPS Rev
Lot:M28010

DC:C0117

Lot:M28010
DC:C0117

DC:C0117
Lot:M28010

DC:C0117

B B

A A

Compal Electronics, Inc.

Title

Note & Revision

Size Document Number Rev

5

4

3

2

Date: Sheet of

ADY11 LA-1181

3 41Friday, November 16, 2001

1

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

1 1

+1.5VS

HA#[3..31]

HREQ#[0..4]

R108 1.5K

1 2

R121 10_0402

1 2

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HA#[3..31]<8>

2 2

HREQ#[0..4]<8>

HADS#<8>

3 3

HBPRI#<8>

HBNR#<8>

HLOCK#<8>

HIT#<8>

HITM#<8>

HDEFER#<8>

AF23

AD23

K1

G2

K3
H3

G1

A3
H1

D3

F3
G3
C2

B5

B11

C6

B9

B7
C8

A8

A10

B3

A13

A9
C3

C12
C10

A6

A15
A14
B13
A12

R1

L3

T1

U1

L1

T4

AA3

W2

AB3

P3

C14
AF4

A7
C4

C22

R2

L2

V3

AA2

U2

T3

J1

J2

J3

B

+CPU_CORE

U5A

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
RP#
ADS#

AERR#
AP#0
AP#1
BERR#
BINIT#
IERR#

BREQ0#
NC
NC
NC
BPRI#
BNR#
LOCK#

HIT#
HITM#
DEFER#

TUALATIN

D22

F22

E21

H22

VCC_0

VCC_1

VCC_2

Address

Lines

Request

Signals

Error

Interface

Arbitration

Signals

Snoop

Signals

VSS_0

E16R4E25

G21

VCC_3

VCC_4

VSS_1

VSS_2

K22

VCC_5

VSS_3

G25

J21

VCC_6

VSS_4

J25

M22

VCC_7

VSS_5

L25

L21

VCC_8

VSS_6

N25

P22

VCC_9

VSS_7

R25

N21

T22

VCC_10

VSS_8

U25

W25

R21

V22

VCC_11

VCC_12

VSS_9

VSS_10

AA25

AC25

U21

Y22

VCC_13

VCC_14

VSS_11

VSS_12

AF25

AE26

W21

AB22

VCC_15

VCC_16

VSS_13

VSS_14

C23

F23

AA21

AC21

VCC_17

VCC_18

VSS_15

VSS_16

H23

K23

D20

VCC_19

VCC_20

VSS_17

VSS_18

M23

F20

E19

VCC_21

VSS_19

P23

T23

AB20

VCC_22

VCC_23

VSS_20

VSS_21

V23

AA19

AC19

VCC_24

VSS_22

Y23

AB23

D18

F18

VCC_25

VCC_26

VSS_23

VSS_24

AE23

B22

E17

VCC_27

VCC_28

VSS_25

VSS_26

D21

C

AB18

AA17

AC17

D16

F16

E15

AB16

AA15

AC15

D14

F14

E13

AB14

AA13

AC13

D12

F12

E11

AB12

AA11

AC11

D10

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC

Mobile

Tualatin

VSS VCC

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

F21

E22

H21

G22

K21

J22

M21

L22

P21

N22

T21

R22

V21

U22

Y21

VSS_48

W22

AB21

AA22

AC22

AE21

B20

D19

F10E9AB10

VCC_51

VCC_52

VSS_49

VSS_50

AB19

AA20

AC20

AA9

AC9D8F8E7AB8

VCC_53

VCC_54

VCC_55

VSS_51

VSS_52

VSS_53

AE19

B18

VCC_56

VSS_54

D17

F17

VCC_57

VCC_58

VSS_55

VSS_56

E18

AB17

AA7

VCC_59

VSS_57

D

AC7D6F6E5H6G5K6J5N5T6V6

VCC_61

VCC_62

VCC_63

VCC_64

VCC_65

VCC_66

VCC_67

VCC_68

VCC_69

Data

Signals

VCC_74

VCC_75

VCC_76

VCC_77

VCC_78

VCC_79

VCC_80

U5Y6W5

AB6

AA5

AC5M6P6

VCC_70

VCC_71

VCC_73

VCC_72

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8

D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

A16
B17
A17
D23
B19
C20
C16
A20
A22
A19
A23
A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
M26
P24
AA26
T26
U24
Y25
W26
V26
AB25
T25
Y24
W24
Y26
AB24
AA24
V24

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HD#[0..63]

E

HD#[0..63] <8>

4 4

A

+CPU_CORE

Title

Size Document Number Rev

B

C

D

Date: Sheet of

Compal Electronics, Inc.

Mobile Tualatin uFCPGA

ADY11 LA-1181

4 41Friday, November 16, 2001

E

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

+VTT

+1.8VS

+1.5VS

+1.5VS

PICD0<16>
PICD1<16>

1 8
2 7
3 6
4 5

12
12

R_K

R28

56.2_1%

1 1

2 2

Place
R_K<0.1"
from CPU

H_FERR#<16>

H_PWRGD<16>

H_RESET#<8>

RP6 8P4R_1.5K

+VTT

R136 1.5K

R38 56.2_1%

12

ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK

ITP_PREQ#
ITP_PRDY#

R18

1.5K

+1.5VS

R36

150

12

12

+VS_CMOSREF

R19

3K

+1.5VS

R37

150

12

12

R24

1.5K

12

CLK_CPU_APIC<14>

PM_CPUPERF#<16>

H_RS#0<8>
H_RS#1<8>
H_RS#2<8>

H_TRDY#<8>

H_A20M#<16>

H_IGNNE#<16>

H_SMI#<16>

H_STPCLK#<16>

H_DPSLP#<16,32>

H_INTR<16>

H_NMI<16>

H_INIT#<16>

H_DBSY#<8>

H_DRDY#<8>

H_BSEL0<14>
H_BSEL1<14>

@10PF_0402

ITP_TCK<7>

ITP_TDI<7>
ITP_TDO<7>
ITP_TMS<7>

ITP_TRST#<7>

ITP_PREQ#<7>

ITP_PRDY#<7>

C38

1 2

R30 56.2_1%

If used ITP port mu st depop

3 3

C35
.1UF_0402

1 2

STBY

SMBCLK

ALERT

ADD0

NC

NC

1K_0402

+5VALW

R26

10K_0402

1 2

16
15
14
13
12
11
10

R23

1 2

+5VALW

R27

1 2

W=15mil

Thermal Sensor
MAX6654MEE

U6

1

NC

12

H_THERMDA
H_THERMDC

C34
2200PF

4 4

+5VALW

R29 1K_0402

12

2

VCC

3

DXP

4

DXN

5

NC

SMBDATA

6

ADD1

7

GND

8 9

GND NC

MAX6654MEE

Address :1001_110X

A

H_A20M#

H_IGNNE#

H_INTR
H_NMI

H_THERMDA
H_THERMDC

1 2

R34 110_1%

R35

1 2

@33_0402

ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_PREQ#
ITP_PRDY#

Note :
GHI# Pull-Up internally

SMB_EC_CK1 <15,28,29,33>
SMB_EC_DA1 <15,28,29,33>

THRM# <29>

10K_0402

B

AA18

AC18

AE17

B16

D15

F15

AB15

AA16

AC16

AE15

B14

D13

F13

E14

AB13

AA14

AC14

U5B

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

VSS_63

VSS_64

VSS_65

VSS_66

APIC

Debug
Break

Point

Test

Access

PORT
( ITP )

VCCT_2

VCCT_3

J23

L23

VCCT_4

VCCT_5

N23

R23

+1.5VS

R_E

R_F

VCCT_6

VCCT_7

U23

W23

12

12

VSS_67

VCCT_8

VCCT_9

AA23

R20
499_1%

R22
1K_1%

Y3

RS#0

V1

RS#1

U3

RS#2

M5

Request

RSP#

W1

Signals GND

TRDY#

AC3

A20M#

AF6

FERR#

AF5

FLUSH#

AD9

IGNNE#

AD3

SMI#

AB4

PWRGOOD

AE4

STPCLK#

AF8
AD15
AE14

AE6

B15

AF13
AF14

AE12
AF10
AF16

AD19
AD17
AF20

AF22
AE20
AD22
AD21

AD10

AD7
AD11

AF7
AF15
AF19
AE22

AF12

AD5
AE16

B

W3

Y1

L5

DPSLP#
INTR/LINT0
NMI/LINT1
INIT#
RESET#

DBSY#
DRDY#

THERMDA
THERMDC

SELFSB0
SELFSB1
EDGECTRLP

PICD0
PICD1
PICCLK

RP2#
RP3#
BPM0#
BPM1#

TCK
TDI
TDO
TMS
TRST#
PREQ#
PRDY#

CMOSREF_1
CMOSREF_0
RTTIMPDEP

GHI#

+VTT

Compatibility

VCCT_1

A26

G23

AE13

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

VSS_74

VCCT_10

VCCT_11

VCCT_12

VCCT_13

VCCT_14

VCCT_15

VCCT_16

C21

C19

AD20

C17

AD18

C15

C13

AD14

CMOS Reference Voltage

Layout note :

1. Place R_E1 and R_F near CPU.

2. Place decoupling caps near CPU.

12

C33
.1UF_0402

C

B12

D11

F11

E12

AB11

AA12

AC12

AE11

B10D9F9

E10

AB9

AA10

AC10

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

Mobile

Tualatin

VCCT VID

VCCT_17

VCCT_18

VCCT_19

VCCT_20

VCCT_21

VCCT_22

VCCT_23

VCCT_24

VCCT_25

VCCT_26

VCCT_27

VCCT_28

VCCT_29

VCCT_30

VCCT_31

C11

AD12C9C7

AD8C5AD6

12

C31
.1UF_0402

AC23

C

AA4E4G4J4L4

VCCT_32

AC4V4AE3

+VS_CMOSREF

AE9B8D7F7E8

VSS_91

VSS_92

VSS_93

VCCT_33

VCCT_34

VCCT_35

AF2

AF1

AE18D5E6

AB7

AA8

AC8

AE7B6F5H5G6K5J6N6L6T5R6V5U6Y5W6

VSS_94

VSS_95

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VCCT_36

VCCT_37

VCCT_38

VID0

VID1

VID2

VID3

AB1

AC2

AE2

AF3R3B26M4AF26C1AF17

+VTT

R_A

R_B

D

AB5

AA6

AC6

AE5B4D4F4H4K4M3U4W4B2D2F2H2

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VID4

VSS

VSS

VSSNCNC

GTL Reference Voltage

12

R31

Layout note :

1K_1%

1. Place R_A and R_B between and GMCH and CPU.

2. Place decoupling caps near CPU.(Within 500mils)

12

R21
2K_1%

NC

N4

CPU_VR_VID4 <6>
CPU_VR_VID3 <6>
CPU_VR_VID2 <6>
CPU_VR_VID1 <6>
CPU_VR_VID0 <6>

12

C26

.1UF_0402

VSS_142

E20

F19

12

D

AE1

A25

C25

VTT_PWRGD<32>

C36
.1UF_0402

AD2

VSS_123

VSS_124

VSS_125

Data

Signals

VTT Ref

Analog

VSS_133

VSS_134

VSS_135

12

C41
.1UF_0402

R25 1K_0402

TESTHI1

R10 1K_0402

TESTHI2

R7 1K_0402

VSS_126

VSS_127

VSS_128

VSS_129

AE24

DEP#0

AD25

DEP#1

AE25

DEP#2

AC24

DEP#3

AF24

DEP#4

AD26

DEP#5

AC26

DEP#6

AD24

DEP#7

AF21

VREF_1

AB26

VREF_2

H26

VREF_3

A21

VREF_4

AF9

VREF_5

A4

VREF_6

N1

VREF_7

AA1

VREF_8

Y4

TESTLO

R5

VCC

N3

PLL1

N2

PLL2

P1

NC

P5

NC

E1

NC

F1

NC

AC1

CLK0

AD1

CLK0#

M1

TESTLO

AF18

NC

AD16

NCHCTRLP

AF11

TESTHI

AE8

NC

N24

NC

AE10

NC

E2

TESTHI

P4

NC

AD4

NC_1

A5

NC_2

D1

NC_3

AD13

NC_4

B1

NC_5

P26

NC_6

A11

NC_7

VTTPWRGOOD

VSS_132

E3

D26

NC

VSS_130

VSS_131

TUALATIN

K2M2P2T2V2Y2AB2

R11
1K_0402

VTT_PWRGD

+V_AGTLREF

12

C30
.1UF_0402

Title

Size Document Number Rev

Date: Sheet of

TESTLO1

R9 1K_0402

TESTLO2

+V_AGTLREF

+CPU_CORE

TESTLO1

+VTT_C

CLK_HCLK
CLK_HCLK#
TESTLO2

TESTHI1

TESTHI2

VTT_PWRGD

+VTT

12

12

C25
.1UF_0402

+VTT_PLL

+

R14

1 2

19.6K

C22
33UF_D2_16V

R134 14_1%

1 2

+3VS

2

1 2

L22 FLM-201209-4R7K

CLK_HCLK <14>
CLK_HCLK# <14>

12

Compal Electronics, Inc.

Mobile Tualatin uFCPGA & Thermal sensor

ADY11 LA-1181

E

12

12

12

12

R6
10K_0402

1

Q2
3904

3

E

+VTT

+VTT

12

R15

0_0402

+VTT_PLLIN

+VTT

VTT_PWRGD# <14,28>

5 41Friday, November 16, 2001

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

E

Layout note :

Place close to CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

1 1

+CPU_CORE

12

12

C205

C144

.22UF_X7R

.22UF_X7R

+CPU_CORE

12

12

C194

C145

.22UF_X7R

.22UF_X7R

+CPU_CORE

2 2

3 3

12

+CPU_CORE

12

+CPU_CORE

12

+

+CPU_CORE

12

+

C200
10UF_10V_1206

C183
10UF_10V_1206

C29
220UF_D2_4V

C293
@220UF_D2_4V

Pls used X7R(uFCPGA EMTS Rev0.7)

12

C164
.22UF_X7R

12

C233
.22UF_X7R

12

C142
.22UF_X7R

Pls used X7R(uFCPGA EMTS Rev0.7)

12

12

C141
.22UF_X7R

12

C174
.22UF_X7R

C143
.22UF_X7R

Pls used X7R(uFCPGA EMTS Rev0.7)

12

C202
10UF_10V_1206

12

C28
10UF_10V_1206

12

C201
10UF_10V_1206

Pls used X7R(uFCPGA EMTS Rev0.7)

12

C151
10UF_10V_1206

12

C126

+

@220UF_D2_4V

12

C119

+

220UF_D2_4V

12

C191
10UF_10V_1206

12

C292

+

220UF_D2_4V

12

C210

+

@220UF_D2_4V

12

C24
10UF_10V_1206

12

C260

+

220UF_D2_4V

12

C153

+

220UF_D2_4V

12

C196
.22UF_X7R

12

C192
.22UF_X7R

12

C234
.22UF_X7R

12

C212
.22UF_X7R

12

C182
10UF_10V_1206

12

C184
10UF_10V_1206

12

C230
.22UF_X7R

12

C235
.22UF_X7R

12

C216
.22UF_X7R

12

C231
.22UF_X7R

12

C229
.22UF_X7R

12

C228
.22UF_X7R

12

12

C146

C173

.22UF_X7R

.22UF_X7R

12

12

C188

C165

.22UF_X7R

.22UF_X7R

R257

1K_0402

+3VS

182736

45

12

RP7
8P4R_1K

4 5

8 9
14 15
18 19
22 23

1

CPU Voltage ID

CPU_VR_VID0<5> CPU_VID0 <32>
CPU_VR_VID1<5>
CPU_VR_VID2<5>
CPU_VR_VID3<5>
CPU_VR_VID4<5>

AC_VID0<17>
AC_VID1<17>
AC_VID2<17>
AC_VID3<17>
AC_VID4<17>

PM_GMUXSEL = 0 : for low Voltage A-C

1 : for high Voltage B-C

PM_GMUXSEL<16,32>

+VTT

12

+

+VTT

12

U24

B0 D0
B1 D1
B2 D2
B3 D3
B4 D4

BE#

SN74CBT3383

Layout note :

Place close to CPU,
Use 2 vias per PAD.

C37
220UF_D2_4V

C222
1UF

VCC
GNDBX

12

+

12

C123
1UF

CPU_VID0

23

C0A0

CPU_VID1

67

C1A1

CPU_VID2

1011

C2A2

CPU_VID3

1617

C3A3

CPU_VID4

2021

C4A4

24
1213

C118
@220UF_D2_4V

12

12

C152
1UF

+5VS

12

C455
.01UF_0402

12

C130
1UF

CPU_VID1 <32>
CPU_VID2 <32>
CPU_VID3 <32>
CPU_VID4 <32>

C135
1UF

12

C249
1UF

12

12

C248

C199

1UF

1UF

12

12

C129

C227

1UF

1UF

+CPU_CORE

12

C32

+

220UF_D2_4V

4 4

EMI Clip PAD for CPU

PAD2

1

PAD-2.5X3

PAD6

PAD-2.5X3

A

12

C289

+

220UF_D2_4V

12

C283

+

220UF_D2_4V

PAD7

1

1

PAD-2.5X3

PAD8

PAD-2.5X3

Tualatin Coppermine-T

D4 D3 D2 D1 D0 CPU_Core(V) ES(before MP)

-------------------------------------------------------

0 0 1 0 1 1.50V

-------------------------------------------------------

1.15V0 1 1 0 0

D4 D3 D2 D1 D0 CPU_Core(V) QS ( MP)

-------------------------------------------------------

0 1 1.40V

-------------------------------------------------------

1

B

1.15V0 1 1 0 0

C

D4 D3 D2 D1 D0 CPU_Core(V) ES(before MP)

------------------------------------------------------ -

0 0 0 0 1 1.70V

------------------------------------------------------ -

1.35V0 1 0 0 0

D4 D3 D2 D1 D0 CPU_Core(V) QS ( MP)

------------------------------------------------------ -

0

10

1 000000

------------------------------------------------------ -

D

1.70V0 1 1

1.35V

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

CPU Bypass & CPU VID

ADY11 LA-1181

6 41Friday, November 16, 2001

E

2

5

4

3

2

1

ITP PORT

+VTT +3VS

D D

H_RESETX#<8>

ITP_PWROK<16,30>

C C

9

10

+5VS POWER

U26C

74HCT08

R96
@56_1%

R95 @240

ITP_TCK<5>
ITP_TMS<5>

8

ITP_TCK
ITP_TMS

R94

240

R91
@39

R93

@39

1 2

R415 5.6K_0402

+VTT +VTT+1.5VS +1.5VS

R87

R89
@1.5K

@10K_0402

12

R245
10K_0402

JP18

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

@AMP104078-4

PM_PWROK <16>

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

R90
@150

R84 @240

R88
@510

R86
@200

R92
@200

R85
@56.2_1%

ITP_TDI
ITP_TDO
ITP_TRST#

ITP_PREQ#
ITP_PRDY#

ITP_TDI <5>
ITP_TDO <5>
ITP_TRST# <5>

ITP_PREQ# <5>
ITP_PRDY# <5>

CLK_ITPP# <14>CLK_ITPP<14>

R249 @0_0402

B B

EN_DFAN<28>

A A

5

1 2

R416 100_0402

R235

3.48K_1%

2

4

+12VALW

1 2
21

3
1

EC_HPOWON <28>

Fan Control circuit

2 1

+5VALW

D2
1SS355

2 1

C99
@1000PF_0402

+5VFAN

3

+3V

JP17

1
2
3

53398-0310

12

R375
10K_0402

FAN1_TACH <28>

Q4

FMMT619

D8
1N4148

2.2UF_16V_0805

1 2

Q10
2SA1036K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C420

1

2

3

D1
1N4148

COMPAL Electronics,Inc

Title

ITP PORT & Fan control

Size Document Number Rev

ADY11 LA-1181

2

Date: Sheet of

7 41Friday, November 16, 2001

1

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

1 1

+1.8VS

HUB Interface Reference

12

R125

301_1%

Layout note :

1. Place R_C and R_D in middle of Bus.

R_C

2. Place capacitors near GMCH.

12

R124
301_1%

R_D

2 2

Place Reference Circuit near GMCH

+1.5VS

12

VGAREF

3 3

4 4

12

+VS_HUBREF

12

C176
.1UF_0402

C261 470PF

1 2

R142
1K_1%

R141
1K_1%

C270 470PF

1 2

A

12

12

R143

82.5_1%

R147

82.5_1%

HUB_PD[0..10]<16>

HUB_PSTRB<16>

HUB_PSTRB#<16>

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

B

B

U7A

U4

H_D#0

P1

H_D#1

W6

H_D#2

U2

H_D#3

U6

H_D#4

R1

H_D#5

N3

H_D#6

W5

H_D#7

V4

H_D#8

P3

H_D#9

R3

H_D#10

U1

H_D#11

V6

H_D#12

W4

H_D#13

T3

H_D#14

P2

H_D#15

V3

H_D#16

R2

H_D#17

T1

H_D#18

W3

H_D#19

U3

H_D#20

Y4

H_D#21

AA3

H_D#22

W1

H_D#23

V1

H_D#24

Y1

H_D#25

Y6

H_D#26

AD3

H_D#27

AB4

H_D#28

AB5

H_D#29

V2

H_D#30

Y3

H_D#31

Y2

H_D#32

AA4

H_D#33

AA1

H_D#34

AA6

H_D#35

AB1

H_D#36

AC4

H_D#37

AA2

H_D#38

AB3

H_D#39

AD2

H_D#40

AD1

H_D#41

AC2

H_D#42

AB6

H_D#43

AC6

H_D#44

AC1

H_D#45

AF3

H_D#46

AD4

H_D#47

AD6

H_D#48

AC3

H_D#49

AH3

H_D#50

AE5

H_D#51

AE3

H_D#52

AG2

H_D#53

AF4

H_D#54

AF2

H_D#55

AJ3

H_D#56

AE4

H_D#57

AG1

H_D#58

AE1

H_D#59

AG4

H_D#60

AH4

H_D#61

AG3

H_D#62

AF1

H_D#63

ALMADOR-M

+VS_HUBREF

12

C178
.01UF_0402

M12

M13

M17

M18

N12

VSS0

VSS1

VSS2

VSS3

VSS4

Host

Interface

HUB_PD0

HUB_PD1

HUB_PD2

HUB_PD3

HUB_PD4

HUB_PD5

G26

H28

H29

H27

F29

F27

HUB_PD0

HUB_PD1

HUB_PD2

HUB_PD3

HUB_PD4

HUB_PD5

R138 54.9_1%
R126 27.4_1%
R127 54.9_1%

N13

N14

N15

N16

VSS5

VSS6

VSS7

HUB_PD6

HUB_PD7

HUB_PD8

E29

E28

G25

G27

HUB_PD7

HUB_PD6

HUB_PD8

HUB_PD9

1 2
1 2
1 2

N17

N18

VSS8

VSS9

VSS10

HUB_PD9

HUB_PD10

HUB_PSTRB

H26

G29

HUB_PD10

P13

P14

P15

P16

VSS11

VSS12

VSS13

VSS14

HUB_REF

HUB_PSTRB#

H24

F28

C

P17

R13

R14

R15

R16

R17

T13

T14

T15

T16

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

Almador-M
GMCH

DVO_RCOMP

SM_RCOMP

HUB_RCOMP

AGP_REF

AGP_RCOMP/DVOBC_RCOMP

RESET#

H_GTLREF1

VGAREF

J25

K24

AB24

H_GTLREF0

AA7J7C2

12

C263
.1UF_0402

12

C

AC22F6J23

T17

U12

U13

U14

U15

U16

U17

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS

H_GTLRCOMP

VSS

VSS

AB23

AC23

1 2

R116 80.6_1%

+V_AGTLREF

12

C185
.1UF_0402

12

R128 54.9_1%
C190

.1UF_0402

U18

V12

V13

V17

V18

AJ5D2AC5Y5U5P5L5H5AH2

VSS32

VSS33

VSS34

VSS35

VSS36

VSS_H0

VSS_H1

VSS_H2

VSS_H3

VSSPCMOS_LM0

VSSPCMOS_LM1

VSSPCMOS_LM2

VSSP_HUB0

VSSP_HUB1

VSSP_IO0

AH19

AH20

AF5

VSSP_IO1

G28

H25

AC26

AD22

AE28

PCIRST# <15,16,20,21,26,27,28>

10 mils wide,length <=500 mils.

VSS_H4

VSS_H5

VSS_H6

VSSP_IO2

AE2

AB2W2T2N2K2G2AC7

VSS_H7

VSS_H8

VSS_H9

VSSP_DVO0

VSSP_DVO1

VSSP_DVO2

AH24

AF25

AF27

VSS_H10

VSS_H11

VSS_H12

VSSA_DAC

AH26G8AD7

VSS_H13

VSS_H14

VSS_H15

Host

Interface

VSSA_CPLL

D

VSS_H16

H_CPURST#

H_DBSY#

H_DEFER#

H_DRDY#

H_LOCK#
H_TRDY#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

CLK_HT#

CLK_DREF

CLK_GBIN

CLK_GBOUT

VSSA_HPLL

D

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_ADS#
H_BNR#

H_BPRI#

H_HIT#

H_HITM#

H_RS#0
H_RS#1
H_RS#2

CLK_HT

H2
E3
G3
N4
M6
F1
F2
J3
F3
P6
G1
N5
H1
P4
T4
M2
J2
L2
R4
K1
L3
L1
J1
N1
T5
H3
M3
M1
K3

R6
C1
E1
L4
G5
J4
F4
D3
D1
J6
G4

K6
M4
K5
K4
L6

H6
H4
G6

AJ4
AH5

AC19
AG26
AD24

33_0402

5PF_0402

C297

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

H_RS#0
H_RS#1
H_RS#2

R168

E

HA#[3..31]HD#[0..63]

HA#[3..31] <4>HD#[0..63]<4>

Close to Ball R6.

1 2

R133 @0_0402

HREQ#[0..4]

H_RS#[0..2]

CLKGBOUT

1 2

Title

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

H_RESETX# <7>
H_RESET# <5>
HADS# <4>
HBNR# <4>
HBPRI# <4>
H_DBSY# <5>
HDEFER# <4>
H_DRDY# <5>
HIT# <4>
HITM# <4>
HLOCK# <4>
H_TRDY# <5>
HREQ#[0..4] <4>

H_RS#[0..2] <5>

CLK_GHT <14>
CLK_GHT# <14>

1 2

1 2

R156 47_0402

R151
@33_0402

1 2

C259
@10PF_0402

C277 .01UF_0402

CLK_GBIN

12

R167
@240K

Compal Electronics, Inc.

Almador-M GMCH(1/3)

CLK_DREF <14>
CLK_GBIN <14>

E

CLK_GBOUT <14>

8 41Friday, November 16, 2001

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

AD8

AD9

AD10

AJ21

AE8

AE9

AE10

AE11

AE12

AE13

AE17

AE19

AH21

AF8

AF9

AF10

AF11

AF12

AF13

U7B

SM_DQ0

D29

1 1

2 2

3 3

SM_DQ1
SM_DQ2
SM_DQ3
SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7
SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59
SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

SM_DQ[0..63]

SM_DQ0

C29

SM_DQ1

D27

SM_DQ2

C27

SM_DQ3

A27

SM_DQ4

B26

SM_DQ5

E24

SM_DQ6

C25

SM_DQ7

E23

SM_DQ8

B25

SM_DQ9

C23

SM_DQ10

F22

SM_DQ11

B23

SM_DQ12

C22

SM_DQ13

E21

SM_DQ14

B22

SM_DQ15

C12

SM_DQ16

D10

SM_DQ17

C11

SM_DQ18

A10

SM_DQ19

C10

SM_DQ20

C8

SM_DQ21

A7

SM_DQ22

E9

SM_DQ23

C7

SM_DQ24

E8

SM_DQ25

A5

SM_DQ26

F8

SM_DQ27

C5

SM_DQ28

D6

SM_DQ29

B4

SM_DQ30

C4

SM_DQ31

E27

SM_DQ32

C28

SM_DQ33

B28

SM_DQ34

E26

SM_DQ35

C26

SM_DQ36

D25

SM_DQ37

A26

SM_DQ38

D24

SM_DQ39

F23

SM_DQ40

A25

SM_DQ41

G22

SM_DQ42

D22

SM_DQ43

A23

SM_DQ44

F21

SM_DQ45

D21

SM_DQ46

A22

SM_DQ47

F11

SM_DQ48

A11

SM_DQ49

B11

SM_DQ50

F10

SM_DQ51

B10

SM_DQ52

B8

SM_DQ53

D9

SM_DQ54

B7

SM_DQ55

F9

SM_DQ56

A6

SM_DQ57

C6

SM_DQ58

D7

SM_DQ59

B5

SM_DQ60

E6

SM_DQ61

A4

SM_DQ62

D4

SM_DQ63

ALMADOR-M

SM_DQ[0..63] <12,13>

VSS_LM

SDRAM
System
Memory

VSSP_SM0

VSSP_SM1

VSSP_SM2

B3B6B9

VSS_LM

VSS_LM

VSSP_SM3

VSSP_SM4

B12

B15

B18

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSSP_SM5

VSSP_SM6

VSSP_SM7

VSSP_SM8

B21

B24

B27E7E10

VSS_LM

VSS_LM

VSS_LM

VSS

VSSP_SM9

VSSP_SM10

VSSP_SM11

E13

E16

VSS_LM

VSS_LM

VSSP_SM12

VSSP_SM13

E19

AF14

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

Almador-M
GMCH

VSSP_SM14

VSSP_SM15

VSSP_SM16

VSSP_SM17

VSSP_SM18

VSSP_SM19

E22

E25G9G21E4D28

+VTT

B

AF15

AF16

AF17

AF18

AF19

AF20

AG7

AG15

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

H7

H23K7K23L7N6T6W7Y7AB7

AG16

AG21

VSS_LM

VSS_LM

VCC

VCC

AH6

AH8

VSS_LM

VSS_LM

Power

VCC

VCC

M24

P24

AH9

AH11

VSS_LM

VSS_LM

VCC

VCC

T24

V24

AH12

AH14

VSS_LM

VSS_LM

VCC

VCC

Y23

M14

AH17

AH18

VSS_LM

VSS_LM

VCC

VCC

M15

M16

VSS_LM

VCC

VCC

P12

R12

K28

N28

VSSP_AGP0

VSSP_AGP1

VCC

VCC

VCC

T12

P18

T28

W28

AB28

L25

VSSP_AGP2

VSSP_AGP3

VSSP_AGP4

VCC

VCC

R18

T18

P25

U25

Y25

VSSP_AGP5

VSSP_AGP6

VSSP_AGP7

VSSP_AGP8

SM_VREF0

SM_VREF1

E5

F24

12

C160
.1UF_0402

AE20

G24

VSSA_DPLL0

VSSA_DPLL1

SDRAM
System

Memory

SM_OCLK

SM_RCLK

A24

C24

SM_OCLK_RCLK

12

SM_RAS#

SM_CAS#

SM_WE#

C20

D19

A21

+V_SMREF

C157
.1UF_0402

SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8

SM_MA9
SM_MA10
SM_MA11
SM_MA12

VCC_SM
VCC_SM

SM_BA0

SM_BA1

SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

VCCQ_SM

SM_CLK0
SM_CLK1
SM_CLK2
SM_CLK3

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

VCC_SM

C

VSSA_DPLL0 <10>
VSSA_DPLL1 <10>

A20
B20
B19
C19
A18
A19
C17
C18
B17
A17
A16
C15
C14

F20

NC

E20

NC

F12

NC

E11

NC

C21

VSS

F19

VSS

E12
A12

SM_D_BA0

B16

SM_D_BA1

C16

F18
D18
D13
D12
E18
F17
F14
F13

E17
F16
D16
D15
E15
E14

VSS

A15
B2
B14
A3
A14

VSS

C3

VSS

A13
C9
C13
A9
B13

VSS

A8

SM_D_RAS#
SM_D_CAS#
SM_D_WE#

12

C134
@22PF_0402

Close to Ball E5 and F24

MMA0
MMA1
MMA2
MMA3

MMA4

SM_BA0 <12,13>
SM_BA1 <12,13>

1 2
1 2
1 2
1 2

SM_RAS# <12,13>
SM_CAS# <12,13>
SM_WE# <12,13>

MMA5
MMA6
MMA7

MMA8
MMA9
MMA10
MMA11

MMA12

Cap

near pin A12

MMA0
MMA1
MMA2
MMA3
MMA4
MMA5
MMA6
MMA7
MMA8
MMA9
MMA10
MMA11
MMA12

XOR

Layout Note:
F20,E20,F12,E11
ADD Testpoint
for Factory

C132 .1UF_0402

R114 10_0402

1 2

R115 10_0402

1 2

SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

SM_D_CLK0
SM_D_CLK1
SM_D_CLK2
SM_D_CLK3

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

+3V

12

C131

Layout note
Cap near pin A8

.1UF_0402

R118 10_0402

1 2

R120 10_0402

1 2

R111 10_0402

1 2

Layout note
SM_OCLK_RCLK trace length 150mil +-50mil

+3V

1 2

SM_DQM[0..7] <12,13>

SM_CS#0 <12>
SM_CS#1 <12>
SM_CS#2 <13>
SM_CS#3 <13>

+3V

R110 10_0402
R113 10_0402
R119 10_0402
R109 10_0402

SM_CKE0 <12>
SM_CKE1 <12>
SM_CKE2 <13>
SM_CKE3 <13>

D

RP5

8P4R_10
RP4

8P4R_10
RP3

8P4R_10

SM_MA0
SM_MA1
SM_MA2
SM_MA3

SM_MA4
SM_MA5
SM_MA6
SM_MA7

SM_MA8
SM_MA9
SM_MA10
SM_MA11

SM_MA12

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 2

R112 10_0402

Layout note :

Place resistors near GMCH

SMD_CLK0 <12>
SMD_CLK1 <12>
SMD_CLK2 <13>
SMD_CLK3 <13>

+3V

12

R122

249_1%

12

R123

49.9_1%

E

SM_MA[0..12] <12,13>

Layout note :

Place resistors near GMCH

System Memory Reference

+V_SMREF

Layout note :

near pin A24

4 4

A

Title

Size Document Number Rev

B

C

D

Date: Sheet of

Compal Electronics, Inc.

Almador-M GMCH(2/3)

ADY11 LA-1181

9 41Friday, November 16, 2001

E

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

1 2

1 2

1 2

RP9

@8P4R_8.2K

1
2
3

1 2

R132 330

A

AGP_FRAME#

AGP_TRDY#

AGP_STOP#

AGP_REQ#
AGP_GNT#
AGP_PIPE#
AGP_WBF#

AGP_RBF#
DVO_INT#

DVO_STALL

U47

NC
A
GND

TC7SH14

A

VCC

DVO_HSYNC<15>
DVO_VSYNC<15>

DVO_D7<15>
DVO_BL#<15>

DVO_CLK<15>
DVO_CLK#<15>

DVO_D1<15>
DVO_D0<15>
DVO_D3<15>
DVO_D2<15>
DVO_D5<15>
DVO_D4<15>
DVO_D6<15>
DVO_D9<15>
DVO_D8<15>
DVO_D11<15>
DVO_D10<15>

DVO_STALL<15>

Y

AGP_PAR

5
4

+3VS

R421

+1.5VS

1.5V level clock

12

732_1%

R422

604_1%

1 2

AGP_DEVSEL#

1 2

R137 8.2K_0402

AGP_IRDY#

1 2

R417 8.2K_0402

Layout note :

Place close to AE16,
AE15 of GMCH

12

AGP_FRAME#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_DEVSEL#
AGP_REQ#
AGP_GNT#
AGP_PAR

DVO_INT#
DVO_STALL

DPMS_CLK

1 2

R145 10K_0402

C278
68PF

AA29
AA24
AA25

AA27
AA28

AC27
AD29

W24

M29
M28

M27
M25

W29
W26

W25
W27

+1.5VS

R430 8.2K_0402

R431 8.2K_0402

R432 @8.2K_0402

1 1

+1.5VS

1 8
2 7
3 6
4 5

+1.5VS

R150 @8.2K_0402

1 2
1 2

R131 100K_0402

1 2

R129 @100K_0402

2 2

3 3

RTCCLK<16>

AGP_PAR : Strapping option for SW detection of

4 4

AGP or DVO device.
0 -> DVO B/C device
1 -> AGP device

B

AGP_SBA0/ZV_D8
AGP_SBA1/ZV_D7
AGP_SBA2/ZV_D6

Y24

AGP_SBA3/ZV_D5

Y27

AGP_SBA4/ZV_D2

Y26

AGP_SBA5/ZV_D1
AGP_SBA6/ZV_D0

Y28

AGP_SBA7/ZV_HREF

L27

AGP_CBE#0/DVOB_D7

P29

AGP_CBE#1/DVOB_BLANK#

R27

AGP_CBE#2/ZV_VSYNC

T25

AGP_CBE#3/DVOC_D5

L29

AGP_ADSTB0/DVOB_CLK

L28

AGP_ADSTB#0/DVOB_CLK#

U29

AGP_ADSTB1/DVOC_CLK

U28

AGP_ADSTB#1/DVOC_CLK#
AGP_SBSTB/ZV_D4
AGP_SBSTB#/ZV_D3

R29

AGP_FRAME#/M_DDC2_DATA

P26

AGP_IRDY#/M_I2C_CLK

P27

AGP_TRDY#/M_DDC2_CLK

N25

AGP_STOP#

R28

AGP_DEVSEL#/M_I2C_DATA
AGP_REQ#/ZV_CLK
AGP_GNT#/ZV_D15

P28

AGP_PAR

J29

AGP_AD0/DVOB_HSYNC

J28

AGP_AD1/DVOB_VSYNC

K26

AGP_AD2/DVOB_D1

K25

AGP_AD3/DVOB_D0

L26

AGP_AD4/DVOB_D3

J27

AGP_AD5/DVOB_D2

K29

AGP_AD6/DVOB_D5

K27

AGP_AD7/DVOB_D4
AGP_AD8/DVOB_D6
AGP_AD9/DVOB_D9

L24

AGP_AD10/DVOB_D8
AGP_AD11/DVOB_D11

N29

AGP_AD12/DVOB_D10
AGP_AD13/DVOBC_CLKINT#

N26

AGP_AD14/DVOB_FLD/STL

N27

AGP_AD15

R25

AGP_AD16/DVOC_VSYNC

R24

AGP_AD17/DVOC_HSYNC

T29

AGP_AD18/DVOC_BLANK#

T27

AGP_AD19/DVOC_D0

T26

AGP_AD20/DVOC_D1

U27

AGP_AD21/DVOC_D2

V27

AGP_AD22/DVOC_D3

V28

AGP_AD23/DVOC_D4

U26

AGP_AD24/DVOC_D7

V29

AGP_AD25/DVOC_D6
AGP_AD26/DVOC_D9

V25

AGP_AD27/DVOC_D8
AGP_AD28/DVOC_D11
AGP_AD29/DVOC_D10
AGP_AD30/DVOC_INT#/DPMS_CLK

Y29

AGP_AD31/DVOC_FLD/STL

B

+1.5VS

R155 @8.2K_0402

1 2

R163 @8.2K_0402

1 2

R149 @8.2K_0402

1 2

+VTT

V14

AGP

Interface

V15

VDD_LM

U7C

(DVOB/DVOC & ZV port)

ALMADOR-M

AGP_PIPE#/ZV_D10

AB26

AB29

AGP_WBF#

AGP_PIPE#

AGP_ST0

AGP_ST1

AGP_ST2

+3V

V16

AE16

AE15

AD15

AD16

VDD_LM

VDD_LM

VDD_LM

VDD_LM

VDD_LM

VDD_LM

AGP_WBF#/ZV_D9

AGP_RBF#/ZV_D11

AGP_ST0/ZV_D14

AGP_ST1/ZV_D13

AGP_ST2/ZV_D12

AB25

AC28

AC29

AB27

AGP_RBF#

AGP_ST0

AGP_ST1

AGP_ST2

AE25

AD23

VCCP_IO

VCCP_IO

LM_CMD

LM_SCK

AH7

AF7

+1.8VS

J24

LM_SIO

AJ7

+1.5VS

F26

N24

VCCP_HUB

VCCP_HUB

LM_RQ0

LM_RQ1

AG11

AJ12

AG12

C

C281 .1UF_0402

12
12

C170

.1UF_0402

W23

J26

M26

R26

V26

AA26

L23

AA23

VCCP_AGP

VCCP_AGP

VCCP_AGP

VCCP_AGP

VCCP_AGP

VCCP_AGP

VCCQ_AGP

VCCQ_AGP

VCCP_AGP

Almador-M
GMCH

Local Memory
Interface

LM_RQ2

LM_RQ3

LM_RQ4

LM_RQ5

LM_RQ6

LM_RQ7

LM_RCLK

AG13

AJ13

AG14

AJ14

AJ6

LM_GCLK

AG6

C

AH13

+VTT

U24

AE6G7G10

VCCP_AGP

VCCA_HPLL

VCCA_CPLL

Power

Interface

LM_RAMREF0

LM_RAMREF1

LM_CTM

AD14

AE14

AH15

+3V

G20

VCCQ_SM

LM_CTM#

AJ15

AJ16

+1.8VS

AF6

AE7

VCCQ_SM

VCCPCMOS_LM

VCCPCMOS_LM

LM_CFM

LM_CFM#

VCCP_SM

AH16

D5D8D11

.01UF_0402

AC9

AC8

AF26

AG27F5J5M5R5V5AA5

VCCA_DAC

VCCA_DAC

VCCPCMOS_LM

VCCPCMOS_LM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

D14

D17

D20

12
C632

+VTT

VCC_H

VCCP_SM

VCCP_SM

D23

D26F7F15

R170
R169

+1.8VS

12

.1UF_0402

VCC_H

VCC_H

VCC_H

VCCP_SM

VCCP_SM

VCCP_SM

G11

G19

10K_0402
1 2
1 2

10K_0402

C290

AD5

VCC_H

VCC_H

VCC_H

VCCP_SM

VCCP_SM

G23

AG5

E2

VCC_H

VCC_LM

AC10

AC11

VCC_H

VCC_LM

AD11

12

C294
.1UF_0402

+1.5VS

VCCA_DPLL

VCCADPLL

AC20

F25

AC21

AF21

VCCP_DVO

VCCA_DPLL0

VCCA_DPLL1

Display

Interface

(DVOA port)

Local Memory
Interface

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

AD12

AD13

AE18

AD17

AD18

D

AF24

DAC_VSYNC
DAC_HSYNC

VCCP_DVO

VCCP_DVO

DAC_RED#

DAC_GREEN#

DAC_BLUE#
DAC_GREEN
IO_DDC1CLK

IO_DDC1DATA

DAC_REFSET

DVO_CLKIN

DVO_BLANK#

DVO_VSYNC

DVO_HSYNC

IO_I2CDATA

IO_DDC2DATA

IO_DDC2CLK

DVO_INTR#
DVO_FIELD

AGP_BUSY#

VCC_LM

VCC_LM

AD19

+VS_RIMMREF

D

L49
FBM-11-201209-601T

1 2

12

C302

+

100UF_D2_6.3V

L45
FBM-11-201209-601T

1 2

12

C167

.1UF_0402

DAC_RED

DAC_BLUE

IO_I2CCLK

DVO_CLK#

DVO_CLK

DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8

DVO_D9
DVO_D10
DVO_D11

LM_DQA0
LM_DQA1
LM_DQA2
LM_DQA3
LM_DQA4
LM_DQA5
LM_DQA6
LM_DQA7

LM_DQB0
LM_DQB1
LM_DQB2
LM_DQB3
LM_DQB4
LM_DQB5
LM_DQB6
LM_DQB7

+3V

VCCA_DPLL0

VCCA_DPLL1

12

C180

+

100UF_D2_6.3V

AE29
AD28

CRT_R#

AF28

CRT_G#

AG28

CRT_B#

AH27
AF29
AG29
AH28
AE27
AD27

R172 255_1%

AJ27

DVOA_CLKIN

AD20
AD21
AF23
AF22
AD25
AC25
AG24
AJ24

AJ22

DVOA_D1

AH22
AG22
AJ23
AH23

DVOA_D5

AG23

DVOA_D6

AE23
AE24

1

AJ25

1
AH25
AG25
AJ26

AD26
AE26

DVOA_INTR#

AE21

1 2

AE22

R166

10K_0402
AG17
AJ17
AG18
AJ18
AG19
AJ19
AG20
AJ20

AJ11
AH10
AJ10
AG10
AJ9
AG9
AJ8
AG8

AC24

R152 10K_0402

+1.8VS

12

C266
68PF

E

+VTT

Strap Name Low High

R176 0_0402

1 2

DVOA_D1 IOQD=1 IOQD=8
DVOA_D5 Desktop Mobile
DVOA_D6 Dual Ended Term Single Ended Term

VSSA_DPLL0 <9>

R117 0_0402

1 2

VSSA_DPLL1 <9>

1 2

R162

1 2

R153

1 2

T52
T53

XOR

Layout Note:
AE24,AJ25
ADD Testpoint
for Factory

R159

576_1%

R_I

R154

2K_1%

+1.5VS

R146 @2.2K
R144 2.2K

+VTT

R173 @2.2K

CRT_VSYNC <15>
CRT_HSYNC <15>

10K_0402

+3VS

10K_0402

+3VS

DVOA_CLKIN
DVOA_INTR#

1 2

R161 10K_0402

R160 10K_0402

1 2

+1.8VS

12

1. Place R_I and R_J near GMCH.

12

1 2
1 2

1 2

CRT_R <15>
CRT_G <15>
CRT_B <15>
3VDDCCL <15>
3VDDCDA <15>

GMBSCL <15>
GMBSDA <15>

R157

1 2

R164

1 2

+3VS

+3VS

+VS_RIMMREF

DVOA_D6
DVOA_D5

DVOA_D1

100K_0402

100K_0402

LTVDA <15>
LTVCK <15>

R_J

AGP_BUSY# <16>

1 2

Title

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

37.4_1% resistors and cap
must be placed after RGB
pi filter near CRT

+3VS

connector.

C627

CRT_R#

CRT_G#

CRT_B#

1 2

1 2

R418 37.4_1%

C628

1 2

1 2

R419 37.4_1%

C629

1 2

1 2

R420 37.4_1%

Compal Electronics, Inc.

Almador-M GMCH(3/3)

E

@.1UF_0402

@.1UF_0402

@.1UF_0402

10 41Friday, November 16, 2001

+1.5VS

2

5

4

3

2

1

Layout note :

Distribute as close as possible
to GMCH Processor Quadrant .

+VTT

D D

+VTT

+VTT

+

C C

+VTT

+

+VTT

+

+VTT

+

B B

+VTT

12

C169
.1UF_0402

12

C158
.1UF_0402

12

C27
220UF_D2_4V

12

C303
220UF_D2_4V

12

C122
@220UF_D2_4V

12

C127
@220UF_D2_4V

12

C306
10UF_10V_1206

12

C177
.1UF_0402

12

C203
.1UF_0402

12

C23

+

220UF_D2_4V

12

C163
.1UF_0402

12

C221
.1UF_0402

12

C267
.1UF_0402

12

C300
10UF_10V_1206

12

C193
.1UF_0402

12

C219
.1UF_0402

12

C187
.1UF_0402

12

C244
.1UF_0402

12

C264
.1UF_0402

12

C198
.1UF_0402

12

C237
.1UF_0402

12

C204
.1UF_0402

12

C243
.1UF_0402

12

C181
.1UF_0402

12

C208
.1UF_0402

12

C247
.1UF_0402

12

C213
.1UF_0402

12

C245
.1UF_0402

12

C197
.1UF_0402

12

C207
.1UF_0402

12

C291
.1UF_0402

12

C223
.1UF_0402

12

C257
.1UF_0402

12

C206
.1UF_0402

12

C286
.1UF_0402

12

C236
.1UF_0402

12

C265
.1UF_0402

12

C220
.1UF_0402

12

C256
.1UF_0402

12

C246
.1UF_0402

12

C295
.1UF_0402

12

C224
.1UF_0402

12

C225
.1UF_0402

12

C274
.1UF_0402

12

C276
.1UF_0402

12

C238
.1UF_0402

12

C239
.1UF_0402

12

C271
.1UF_0402

12

C251
.1UF_0402

Layout note :

Distribute as close as possible
to VCCPCMOS_LM. (GMCH pin
AF6, AE7, AC9, AC8)

+1.8VS

12

12

C288

@.1UF_0402

12

C282
.1UF_0402

Layout note :

Distribute as close as possible
to GMCH Local Memory Quadrant .

+1.8VS

12

12

12

C252
82PF

C279
.1UF_0402

C156
.1UF_0402

Layout note :

Distribute as close as possible
to GMCH AGP/DVO Quadrant .

+1.5VS

12

+

22UF_10V_1206

C273

12

C214
.1UF_0402

Layout note :

Distribute as close as possible
to GMCH System Memory Quadrant .

+3V

12

+

22UF_10V_1206

+3V

12

C133

C149
.1UF_0402

12

12

C138
.1UF_0402

C159
.1UF_0402

12

C269

@.01UF_0402

12

C255
.1UF_0402

12

C140
.1UF_0402

C280
.1UF_0402

12

C268
.01UF_0402

12

C240
.1UF_0402

12

+

C304
22UF_10V_1206

12

C262
.1UF_0402

12

C209
.1UF_0402

12

C232
.1UF_0402

12

C272
82PF

12

12

C242

C285

.1UF_0402

82PF

12

C258
82PF

12

C296
82PF

12

C275
.1UF_0402

12

C287
.1UF_0402

12

C254
.1UF_0402

12

C250
.1UF_0402

12
C186

.01UF_0402

12

C299
82PF

.1UF Cap Used X7R

12

12

12

C171
82PF

C162
.1UF_0402

C168
.1UF_0402

12

12

12

C154

C284

.1UF_0402

82PF

C139
.1UF_0402

12

C179
82PF

12

C147
.1UF_0402

12

C150
.1UF_0402

12

12

C166

C148

82PF

.1UF_0402

Layout note :

Distribute as close as possible
to IO Quadrant .

A A

5

4

+3V

12

C125

+

22UF_10V_1206

3

12

C155
.1UF_0402

12

C137
.1UF_0402

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

GMCH-M Decoupling
ADY11 LA-1181

1

11 41Friday, November 16, 2001

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

E

F

G

H

Layout note :

One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 0) pin .

+3V

1 1

2 2

12

C330
.1UF_0402

+3V

12

C316

+

22UF_10V_1206

System S MBus Select

SM_SEL#
0=SODIMM0 ;
1=SODIMM1

+3VS

12

2

G

SM_SEL#

R268
10K_0402

13

D

S

S

2N7002

G

Q17

2

SM_SEL

2N7002

Q19

13

D

B

SM_SEL

+5VS

G

2

Q18

13

D

S

2N7002

3 3

SM_SEL#<16>

4 4

SMB_DATA<14,16,18> SODIMM1_SMDAT1 <13>

A

SM_SEL#

12

S

C72
.1UF_0402

G

2

13

D

2N7002

+3V

Q16

12

C329
.1UF_0402

12

R183
10K_0402

SODIMM_SMCLK

12

C335
.1UF_0402

12

R184
10K_0402

C

12

C331
.1UF_0402

12

R48
10K_0402

12

SODIMM_SMCLK <13>SMB_CLK<14,16,18>

C68
.1UF_0402

SM_DQM4<9,13>
SM_DQM5<9,13>

SM_MA0<9,13>
SM_MA1<9,13>
SM_MA2<9,13>

SMD_CLK0<9>

SM_RAS#<9,13>
SM_WE#<9,13>
SM_CS#0<9>
SM_CS#1<9>

SM_MA6<9,13>
SM_MA8<9,13>

SM_MA9<9,13>

SM_MA10<9,13>

SM_DQM6<9,13>
SM_DQM7<9,13>

12

C71
.1UF_0402

12

C328
.1UF_0402

SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35

SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39

SM_DQM4
SM_DQM5

SM_MA0
SM_MA1
SM_MA2

SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43

SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47

SMD_CLK0
SM_RAS#

SM_WE#
SM_CS#0
SM_CS#1

SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51

SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55

SM_MA6
SM_MA8

SM_MA9
SM_MA10

SM_DQM6
SM_DQM7

SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59

SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

SODIMM0_SMDAT0

D

12

C334
.1UF_0402

JP21

1

VSS

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VCC

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

VSS

23

CKE0#DQMB0

25

CKE1#/DQMB1

27

VCC

29

A0

31

A1

33

A2

35

VSS

37

DQ8

39

DQ9

41

DQ10

43

DQ11

45

VCC

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

VSS

57

RFU/DQ64

59

RFU/DQ65

61

RFU/CLK0

63

VCC

65

RFU/RAS#

67

WE#

69

RE0#/S0#

71

RE1#/S1#

73

RFU/EDO_OE#

75

VSS

77

RFU/DQ66

79

RFU/DQ67

81

VCC

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

VSS

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VCC

103

A6

105

A8

107

VSS

109

A9

111

A10

113

VCC

115

CE2#/DQMB2

117

CE3#/DQMB3

119

VSS

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VCC

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

VSS

141

SDA

143

VCC

SO-DIMM144-Reverse

12

C347
.1UF_0402

12

C327
.1UF_0402

DQMB4/CE4#
DQMB5/CE5#

DQMB6/CE6#
DQMB7/CE7#

DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

VCC

DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

DQ68/RFU
DQ69/RFU

CKE0/RFU

VCC

CAS#/RFU
CKE1/RFU

A12/RFU
A13/RFU

CLK1/RFU

DQ70/RFU
DQ71/RFU

VCC
DQ48
DQ49
DQ50
DQ51

DQ52
DQ53
DQ54
DQ55

VCC

VCC

DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VCC

12

C69
.1UF_0402

+3V +3V

DIMM0

E

12

VSS

VSS

A3
A4
A5

VSS

VSS

VSS

VSS

A7
BA0
VSS
BA1

A11

VSS

VSS
SCL

C65
.1UF_0402

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

12

C332
.1UF_0402

SM_DQ0
SM_DQ1
SM_DQ2
SM_DQ3

SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7

SM_DQM0
SM_DQM1

SM_MA3
SM_MA4
SM_MA5

SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11

SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15

SM_CKE0
SM_CAS#

SM_CKE1
SM_MA12

1 2

R50 0_0402

SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19

SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23

SM_MA7
SM_BA0

SM_BA1
SM_MA11

SM_DQM2
SM_DQM3

SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27

SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31

SODIMM_SMCLK

12

C67
.1UF_0402

F

12

C333
.1UF_0402

12

SMD_CLK1

C70
.1UF_0402

12

C66
.1UF_0402

SM_DQ[0..63] <9,13>

SM_DQM0 <9,13>
SM_DQM1 <9,13>

SM_MA3 <9,13>
SM_MA4 <9,13>
SM_MA5 <9,13>

SM_CKE0 <9>
SM_CAS# <9,13>

SM_CKE1 <9>
SM_MA12 <9,13>

SMD_CLK1 <9>

SM_MA7 <9,13>
SM_BA0 <9,13>

SM_BA1 <9,13>
SM_MA11 <9,13>

SM_DQM2 <9,13>
SM_DQM3 <9,13>

Place closely to DIMM0

12

R185
@10

12

C326
@15PF

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SO-DIMM SLOT0 /Decoupling & DIMM Select

ADY11 LA-1181

G

12

12

SMD_CLK1SMD_CLK0

R49
@10

C73
@15PF

12 41Friday, November 16, 2001

H

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

E

Layout note :

One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 1) pin .

+3V

12

C55
.1UF_0402

SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35

SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39

SM_DQM4
SM_DQM5

SM_MA3
SM_MA4
SM_MA5

SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43

SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47

SM_CKE2
SM_CAS#

SM_CKE3
SM_MA12
1 2

SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51

SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55

SM_MA7
SM_BA0

SM_BA1
SM_MA11

SM_DQM6
SM_DQM7

SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59

SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

SODIMM_SMCLK

12

C54
.1UF_0402

12

C48
.1UF_0402

SMD_CLK3

D

12

12

C56
.1UF_0402

SM_DQ[0..63] <9,12>

SM_DQM4 <9,12>
SM_DQM5 <9,12>

SM_MA3 <9,12>
SM_MA4 <9,12>
SM_MA5 <9,12>

SM_CKE2 <9>
SM_CAS# <9,12>

SM_CKE3 <9>
SM_MA12 <9,12>

12

12

C63

C57

.1UF_0402

.1UF_0402

SMD_CLK3 <9>

SM_MA7 <9,12>
SM_BA0 <9,12>

SM_BA1 <9,12>
SM_MA11 <9,12>

SM_DQM6 <9,12>
SM_DQM7 <9,12>

Title

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

12

C52

C51

.1UF_0402

.1UF_0402

Place closely to DIMM1

SMD_CLK2 SMD_CLK3

12

12

R47
@10

C64
@15PF

12

12

Compal Electronics, Inc.

SO-DIMM SLOT1 & Decoupling

E

R44
@10

C45
@15PF

2

13 41Friday, November 16, 2001

1

12

C59
.1UF_0402

+3V

12

C44

+

22UF_10V_1206

SMD_CLK2<9>

PAD14

PAD-2.5X3

SM_DQM0<9,12>
SM_DQM1<9,12>

SM_MA0<9,12>
SM_MA1<9,12>
SM_MA2<9,12>

SM_RAS#<9,12>
SM_WE#<9,12>
SM_CS#2<9>
SM_CS#3<9>

SM_MA6<9,12>
SM_MA8<9,12>

SM_MA9<9,12>

SM_MA10<9,12>
SM_DQM2<9,12>

SM_DQM3<9,12>

B

1 1

2 2

3 3

4 4

EMI Clip PAD for Memory Door

PAD10

PAD-2.5X3

PAD11

1

PAD-2.5X3

A

PAD12

1

PAD-2.5X3

PAD19

1

PAD-2.5X3

12

12

C60
.1UF_0402

SODIMM1_SMDAT1<12> SODIMM_SMCLK <12>

PAD16

1

PAD-2.5X3

C61
.1UF_0402

1

12

C58
.1UF_0402

SM_DQ0
SM_DQ1
SM_DQ2
SM_DQ3

SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7

SM_DQM0
SM_DQM1

SM_MA0
SM_MA1
SM_MA2

SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11

SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15

SMD_CLK2
SM_RAS#

SM_WE#
SM_CS#2
SM_CS#3

SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19

SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23

SM_MA6
SM_MA8

SM_MA9
SM_MA10

SM_DQM2
SM_DQM3

SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27

SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31

SODIMM1_SMDAT1

PAD18

PAD-2.5X3

12

12

C62

C53

.1UF_0402

.1UF_0402

+3V +3V

JP13

1

VSS

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VCC

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

VSS

23

CKE0#DQMB0

25

CKE1#/DQMB1

27

VCC

29

A0

31

A1

33

A2

35

VSS

37

DQ8

39

DQ9

41

DQ10

43

DQ11

45

VCC

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

VSS

57

RFU/DQ64

59

RFU/DQ65

61

RFU/CLK0

63

VCC

65

RFU/RAS#

67

WE#

69

RE0#/S0#

71

RE1#/S1#

73

RFU/EDO_OE#

75

VSS

77

RFU/DQ66

79

RFU/DQ67

81

VCC

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

VSS

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VCC

103

A6

105

A8

107

VSS

109

A9

111

A10

113

VCC

115

CE2#/DQMB2

117

CE3#/DQMB3

119

VSS

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VCC

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

VSS

141

SDA

143

VCC

SO-DIMM144-Normal

12

C50
.1UF_0402

12

C47
.1UF_0402

DQMB4/CE4#
DQMB5/CE5#

DQ68/RFU
DQ69/RFU

CKE0/RFU
CAS#/RFU

CKE1/RFU

CLK1/RFU
DQ70/RFU

DQ71/RFU

DQMB6/CE6#
DQMB7/CE7#

DIMM1

1

C

12

DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

VCC

DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

VCC

A12/RFU
A13/RFU

VCC
DQ48
DQ49
DQ50
DQ51

DQ52
DQ53
DQ54
DQ55

VCC

VCC

DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VCC

C46
.1UF_0402

VSS

VSS

A3
A4
A5

VSS

VSS

VSS

VSS

A7
BA0
VSS
BA1

A11

VSS

VSS
SCL

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

12

C49
.1UF_0402

R46 0_0402

A

Width=40 m

*BLM21A60

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

E

F

G

H

+3VS

1 1

+3VS

+3VS

+3VS

12

R58

10K_0402

H_BSEL1<5>
H_BSEL0<5>

2 2

R55

@0_0402

12

12

1K_0402

12

@0_0402

CLK_OSC_VCH<15>

12

R62

R60

1K_0402

H_BSEL1
H_BSEL0

12

R54

R61

@0_0402

Please clos ely pin42

CLK_ICH48<16>

CLK_DREF<8>

3 3

CLK_ICH14<16>

CLK_14M_SIO<26>

Place Crystal within 500 mils of CK_Titan

12

C90 @10PF_0402
caps are internal

to CK_TITAN

12

C93 @10PF_0402

SLP_S1#<16,28>
PM_STPPCI#<16>

PM_STPCPU#<16>

VTT_PWRGD#<5,28>

SMB_DATA<12,16,18>
SMB_CLK<12,16,18>

R53 33_0402

R51 221_1%

R52 22_0402

R59 10_0402

R64 33_0402
R63 33_0402

1 2

1 2

1 2

1 2

1 2
1 2

R56 0_0402

1 2

R57 10K_0402

1 2

CLKOSC_VCH

CLK_ICH48M

* 33

CLKDREF

CLK_ICH14M

12

Y1

14.318MHZ

L24
FBM-11-201209-601T

1 2

L64
FBM-11-201209-601T

1 2

40
55
54

25
34
53

28

43

29
30

33
35

42

39

38

56

or ICS 9508-05

Note:
CPU_CLK[2:0] needs to be running in C3, C4.

U9

2

XTAL_IN

SEL2
SEL1
SEL0

PWR_DWN#
PCI_STOP#
CPU_STOP#

VTT_PWRGD#

MULT0

SDATA
SCLK

3V66_0/DRCG
3V66_1/VCH_CLK

IREF

48MHZ_USB

48MHZ_DOT

REF

W320-04

+3V_CLK

181419323746

VDD_REF

GND_REF

491520313641

VDD_PCI

VDD_PCI

VDD_3V66

GND_PCI

GND_PCI

GND_3V66

VDD_3V66

GND_3V66

ils

12

+

C95

22UF_10V_1206

50

VDD_CORE

VDD_CPU

VDD_CPU

VDD_48MHZ

GND_COREXTAL_OUT

CPUCLKT2

CPU_CLKC2

CPUCLKT1

CPUCLKC1

CPUCLKT0

CPUCLKC0

66MHZ_IN/3V66_5

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

PCICLK_F2
PCICLK_F1
PCICLK_F0

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

GND_48MHZ

GND_IREF

GND_CPU

47

12

12

C89
.1UF_0402

+3VS_CLKVDD

26

12

273
45

44
49

48
52

51
24

23

CLKGBIN

22

CLKICHHUB

21

CLKPCI_F2

7

CLKPCI_F1 PCIF1

6

CLKPCI_F0 PCIF0

5

18
17
16

CLKPCI_LPC

13

CLKPCI_SIO

12

CLKPCI_PCM

11

CLKPCI_LAN

10

C87
.1UF_0402

C86
.1UF_0402

12

R70
240K

Close to CLKGEN

R65 33_0402
R71 33_0402

R72 33_0402
R67 33_0402
R66 33_0402

12

C88
.1UF_0402

L23
FBM-11-201209-601T

1 2

12

C94
10UF_10V_1206

1 2
1 2

1 2
1 2
1 2

R75 33_0402
R74 33_0402
R68 33_0402
R73 33_0402

12

1 2
1 2
1 2
1 2

C76
.1UF_0402

+3VS

CLK_BCLK
12

R13

475_1%
CLK_BCLK#
CLK_HT

12

R45

475_1%
CLK_HT#
CLK_ITP

12

R78

475_1%

CLK_ITP#

R433 0_0402

PCIF1

12

C77
.1UF_0402

+3VS_VDD48M

12

C75
.1UF_0402

1 2

R16 33_1%

1 2

R17 61.9_1%

R8 61.9_1%

1 2

R12 33_1%

1 2
1 2

R42 33_1%

1 2

R40 61.9_1%

R41 61.9_1%

1 2

R43 33_1%

1 2
1 2

R81 33_1%

1 2

R80 61.9_1%

R83 61.9_1%

1 2

R82 @33_1%

1 2

1 2

Place near CPU

R33 26.7_1%

1 2

12

C78
.1UF_0402

12

R32

137_1%

12

C82
.1UF_0402

L25

1 2

12

C98
10UF_10V_1206

10_0805

1SPT

CLK_HCLK <5>

CLK_HCLK# <5>
CLK_GHT <8>

CLK_GHT# <8>
CLK_ITPP <7>

CLK_ITPP# <7>

CLK_GBOUT <8>

CLK_GBIN <8>
CLK_ICHHUB <16>

CLK_ICHPCI <16>

CLK_PCI_LPC <27>
CLK_PCI_SIO <26>
CLK_PCI_PCM <21>
CLK_PCI_LAN <20>

+3VS

Place all these Block's
Components near CPU

Place all these Block's
Components near
GMCH

Place all these Block's
Components near ITP
port

R69

33_0402

CLK_CPU_APIC <5>

C92

12

10PF_0402

4 4

A

B

Place near ICH

R354 51.1_1%

PCIF0

1 2

C

D

E

12

R355

348_1%

0 Ohm resistor for ICH3 d oesn't
need to support APIC fu nction

F

CLK_ICHAPIC <16>

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ADY11 LA-1181

G

Clock Generator

14 41Friday, November 16, 2001

H

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

E

+3VS

Please closely to VCH Conn. power pin

B++12VALW

12

1 1

12

C161

.1UF_0402

C172

.1UF_25V

+5VALW +5VS +3VS +1.8VS +1.5VS

12

12

C195

C211

.1UF_0402

.1UF_0402

2 2

C218
.1UF_0402

12

C217
.1UF_0402

12

C241
.1UF_0402

12

DVO_VSYNC<10>

DVO_HSYNC<10>

DVO_D2<10>
DVO_D0<10>
DVO_D1<10>

DVO_D4<10>
DVO_D5<10>
DVO_D8<10>
DVO_D3<10>
DVO_D7<10>

DVO_CLK<10>

DVO_CLK#<10>

DVO_STALL<10>

DVO_D11<10>
DVO_D9<10>
DVO_D6<10>
DVO_D10<10>

DVO_BL#<10>

CLK_OSC_VCH<14>

JP9

1 2

G1 G2

3 4

3 4

5 6

5 6

7 8

7 8

9 10

9 10

11 12

11 12

13 14

13 14

15 16

15 16

17 18

17 18

19 20

19 20

21 22

G21 G22

23 24

23 24

25 26

25 26

27 28

27 28

29 30

29 30

31 32

31 32

33 34

33 34

35 36

35 36

37 38

37 38

39 40

G39 G40

41 42

41 42

43 44

43 44

45 46

45 46

47 48

47 48

49 50

49 50

51 52

51 52

53 54

53 54

55 56

55 56

57 58

57 58

59 60

G59 G60

VCH Conn.

DISPOFF#

M_SEN#

+1.5VS

+12VALW
B+

+5VALW
+5VS
+1.8VS

GMBSDA <10>
GMBSCL <10>

LTVCK <10>
LTVDA <10>
DAC_BRIG <28>

SMB_EC_CK1 <5,28,29,33>
SMB_EC_DA1 <5,28,29,33>
INVT_PWM <28>
ENABKL <29>

VCH_RST#

BKOFF#<28>
ENABKL<29>

R135 0_0402

1 2

R139 @0_0402

1 2

+5VS

5
2

1

U12
TC7ST08FU

4

DISPOFF#

PCIRST# <8,16,20,21,26,27,28>

EC_VCHRST# <29>

CRTVCC

CRTVCC

R1

10K_0402

12

12

R97

10K_0402

12

.1UF_0402

C110

CRTVCC

Q6

12
C2

C106

.1UF_0402

100PF_0402

12
C105

12

100PF_0402

1

D3 @DAN217

12

12

12

C621

C622

@3.3PF

CRTVCC

DDC_MONID0

1

5
2 4

74AHCT1G125GW
U2

3

1

5
2 4

74AHCT1G125GW
U10

3

C3

.1UF_0402

12

CRTVCC

R3
75_1%

12

3 3

CRT_R<10>

CRT_G<10>

CRT_B<10>

+12VALW

12

R261

47K_0402

13

1 2

R264 100K_0402

CRT_ON#<28>

4 4

Q15
2N7002

2

G

D

2

G

Q1
SI2302DS

S

13

D

+5VS

S

CRT_HSYNC<10>

CRT_VSYNC<10>

C623

@3.3PF

@3.3PF

L14 FCM2012C-800(0805)

12

12

R4

R5

75_1%

75_1%

M_SEN#

1 2

L15

1 2

FCM2012C-800(0805)

L13

1 2

FCM2012C-800(0805)

12
C7

3.3PF

2

CRTR

CRTG

CRTB

D4 @DAN217

2

3

12
C8

3.3PF

L4

1 2

FBM-11-160808-121

L5

1 2

FBM-11-160808-121

1

1

D5 @DAN217

3

+1.8VS

2

3

12
C6

3.3PF

12

12

C9

C4

27PF

27PF

100PF_0402

12
C104

100PF_0402

12
C103

2N7002

1 3

D

2N7002

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

R103

0_0402

2

G

S

Q5

JP2

CRT CONN.

+3VS

12

2

1 3

D

+3VS

R101

4.7K_0402

1 2

G

S

12

R98

4.7K_0402

3VDDCDA <10>

3VDDCCL <10>

CRT Connector

A

Title

Size Document Number Rev

B

C

D

Date: Sheet of

Compal Electronics, Inc.

VCH Conn. & CRT

ADY11 LA-1181

15 41Friday, November 16, 2001

2

E

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

D13

ICH_SCI#

SCI#<28>

LID_OUT#<29>

EC_THRM#<28>

1 1

PWRBTN_OUT#<29>

IDE_PATADET

EC_SMI#<26,28>

IAC_BITCLK<23,25>

SDATA_IN0<23>

2 2

3 3

4 4

SDATA_IN1<25> SERR# <18,20,21>

+3VS

IAC_SDATAO<23,25>

IAC_SYNC<23,25>

AC97_RST#<23,25>

Place closely to
ICH3-M

CLK_ICH14

12

R336
@10

12

C554
@15PF

+1.8VS

HUB Interface VSwing Voltage

12

R319

301_1%

1. Place R_G and R_H in middle of Bus.

R_G

12

R318

301_1%

RB751V

D12

RB751V

D14

RB751V

1 2

R285 10K_0402

EC_SMI#

1 2

R396 @10K_0402

1 2

R411 10K_0402

SDATA_IN1

1 2

R409 @10K_0402

IAC_SDATAO

IAC_SYNC

12

C606
@27PF

1 2

R438 33_0402

CLK_ICH48

12

R369
10_0402

12

C574
5PF_0402

+RTCVCC

1 2

R273 1K_0402

12

C532
.1UF_0402

21

ICH_L_OUT#

21

ICH_THRM#

21

D11

RB751V

AD[0..31]<20,21,27>

IAC_BITCLK

SDATA_IN0

R393

22_0402

12

C607
@27PF

AC_RST#

+R_VBAIS

+VS_HUBVSWING

21

+3VS

PT Change la yout pad

R_H

A

1 2

R304 10K_0402

1 2

R300 10K_0402

1 2

R308 10K_0402

PBTN_OUT#

PM_PWROK

SDATAO

12

C/BE#0<20,21,27>
C/BE#1<20,21,27>
C/BE#2<20,21,27>
C/BE#3<20,21,27>

GNT#0<18>
GNT#1<18>
GNT#2<18,21>
GNT#3<18,20>
GNT#4<18>

REQ#0<18>
REQ#1<18>
REQ#2<18,21>
REQ#3<18,20>
REQ#4<18>

C482

1 2

.047UF

1 2

R445 @22M

+3VALW

+3VS

R277

1 2

0_0402

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

VLBA#<29>

ICH_VGATE<7,30>

PM_CPUPERF#<5>

PM_GMUXSEL<6,32>

SUS_STAT#<26>

RTCCLK<10>

PM_STPPCI#<14>

PM_STPCPU#<14>

SLP_S5#<28>
SLP_S3#<28>
SLP_S1#<14,28>

RSMRST#<30>

ICH_RI#<18>

PM_PWROK<7>

PM_DPRSLPVR<32>

PM_CLKRUN#<18,20,21,26> IRQ14 <18,19>

PM_C3_STAT#

AGP_BUSY#<10>

U37A

J2

PCI_AD0

K1

PCI_AD1

J4

PCI_AD2

K3

PCI_AD3

H5

PCI_AD4

K4

PCI_AD5

H3

PCI_AD6

L1

PCI_AD7

L2

PCI_AD8

G2

PCI_AD9

L4

PCI_AD10

H4

PCI_AD11

M4

PCI_AD12

J3

PCI_AD13

M5

PCI_AD14

J1

PCI_AD15

F5

PCI_AD16

N2

PCI_AD17

G4

PCI_AD18

P2

PCI_AD19

G1

PCI_AD20

P1

PCI_AD21

F2

PCI_AD22

P3

PCI_AD23

F3

PCI_AD24

R1

PCI_AD25

E2

PCI_AD26

N4

PCI_AD27

D1

PCI_AD28

P4

PCI_AD29

E1

PCI_AD30

P5

PCI_AD31

K2

PCI_C/BE#0

K5

PCI_C/BE#1

N1

PCI_C/BE#2

R2

PCI_C/BE#3

A4

PCI_GNT#0

E3

PCI_GNT#1

D2

PCI_GNT#2

D5

PCI_GNT#3

B4

PCI_GNT#4

D3

PCI_REQ#0

F4

PCI_REQ#1

A3

PCI_REQ#2

R4

PCI_REQ#3

E4

PCI_REQ#4

ICH3-M

C465
12PF

1 2

R282 10M

12

32.768KHZ

D9 1SS355

1 2

R281 10M

R446
@2.4M_1%

1 2

X2

21

BATTLOW#

PCI

Interface

BATTLOW#

ICH_RI#
PBTN_OUT#

VSS0

A1

12

ICH_THRM#

V4Y5AB3V5AC2

AB21

AB1

PM_BATLOW#

PM_PWRBTN#

PM_DPRSLPVR

PM_AUXPWROK

PM_CLKRUN#/GPIO24

PM_AGPBUSY#/GPIO6

PM_C3_STAT#/GPIO21

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

A13

A16

A17

A20

A23B8B10

RTC_VBIAS
RTC_X1

RTC_X2

C460
12PF

1 2

R266 10K_0402

AA6

AA1

AA7

W20

AA5

PM_RI#

PM_PWROK

PM_RSMRST#

PM_SLP_S1#/GPIO19

VSS8

VSS9

VSS10

VSS11

B13

B14

B15

B18

B19

+RTCVCC

B

AA2

V21

U21

AA4

AB4U5U20

PM_SLP_S3#

PM_SLP_S5#

PM_SUS_CLK

PM_SUS_STAT#

PM_STPPCI#/GPIO18

PM_STPCPU#/GPIO20

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

B20

B22C3C6

F19

CLK_ICH14<14>
CLK_ICH48<14>

+3VALW

B

C595 @33PF_0402

1 2

R391
@22_0402

1 2

AC_RST#

SDATA_IN0

IAC_BITCLK

Y20

V19B7D11

B11

PM_THRM#

GeyservillePower Management

AC_RST#

AC_BITCLK

PM_GMUXSEL/GPIO23

PM_CPUPREF#/GPIO22

AC'97

PM_VGATE/VRMPWRGD

Interface

ICH3-M (1/2)

VSS

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

C14

C15

C16

1 2

R280 15K

VSS27

C17

C18

C19

C20

C21

C22D9D13

CLK_ICH14
CLK_ICH48

C477
1UF

R408

10K_0402

1 2

IAC_SYNC

R392

33_0402

SDATA_IN1

SDATAO

1 2

C11C7A7V1U3T3U2T2U4U1V2W2Y4Y2W3W4Y3

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

AC_SYNC

LPC

Interface

LPC_DRQ#0

AC_SDATAIN0

AC_SDATAIN1

AC_SDATAOUT

Clocks EEPROM

CLK_48

VSS30

D20

12

VSS31

D21

VSS32

D22

VSS33

E5

VSS34

CLK_14

J23

VSS28

VSS29

D16

D17

LPC_DRQ#1

LPC_FRAME#

CLK_RTCX2

CLK_RTCX1

CLK_RTEST#

CLK_VBIAS

AC6

AC7Y7F20

AB7

RTC_X2

RTC_VBIAS

RTC_X1

RTC_RST#

12

J1
JOPEN

12

R265
1K_0402

ICH_L_OUT#

IDE_PATADET

ICH_SCI#

EC_SMI#

PIDEPWR

GPIO_7

GPIO_8

GPIO_12

GPIO_13

unMUX

GPIO

LAN

Interface

LAN_JCLK

LAN_RSTSYNC

A10C9D7

Layout note:
Locate J1 and R265 on bottom side and with
easy access through memo ry door

GPIO_25

GPIO_27

GPIO_28

LAN_TXD0

LAN_TXD1

LAN_TXD2

CLK_ICHAPIC

J20

J19

INT_APICCLK

LAN_RXD0

LAN_RXD1

LAN_RXD2

C8A8A9B9C10

PIRQB#

PIRQA#

J21

INT_PIRQB#

INT_PIRQA#

INT_APICD1

INT_APICD0

Interrupt
Interface

Interface

EEP_DOUT

EEP_SHCLK

D10

@1K_0402
1 2

C

GPIO3

GPIO2

GPIO4

PIRQC#

PIRQD#

INT_PIRQD#

INT_PIRQC#

INT_PIRQF#/GPIO3

INT_PIRQE#/GPIO2

EEP_CS

EEP_DIN

L19

E9D8E8

R440

C

GPIO5

H22

W19

AB14A5C5B5A6A2B2C1B1

INT_IRQ15

INT_IRQ14

INT_SERIRQ

INT_PIRQH#/GPIO5

INT_PIRQG#/GPIO4

PCI_GPIO0/REQA#

PCI_GPIO1/REQB#/REQ5#

PCI_GPIO16/GNTA#

PCI_GPIO17/GNTB#/GNT5#

PCI

Interface

System

Managment

Interface

SMB_ALERT#/GPIO11

CPU

Interface

CPU_PWRGOOD

HubLink

Interface

HUB_CLK

HUB_PAR

HUB_PSTRB

HUB_PSTRB#

HUB_RCOMP

HUB_VREF

HUB_VSWING

T19

R19

N22

P23

K19

L20

CLK_ICHHUB

HUB_ICH_RCOMP

PCI_CLK

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_PAR
PCI_PERR#
PCI_LOCK#

PCI_PME#

PCI_RST#

PCI_SERR#

STOP#

PCI_TRDY#

SM_INTRUDER#

SMLINK0

SMLINK1

SMB_CLK

SMB_DATA

CPU_A20GATE

CPU_A20M#

CPU_DPSLP#

CPU_FERR#

CPU_IGNNE#

CPU_INIT#
CPU_INTR

CPU_NMI

CPU_RCIN#

CPU_SLP#

CPU_SMI#

STPCLK#

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9

HUB_PD10

EC_WAKEUP#<29>

LAD0 <26>
LAD1 <26>
LAD2 <26>
LAD3 <26>
LDRQ#0 <26>
LDRQ#1
LFRAME# <26>
PIDEPWR <19>

SM_SEL# <12>
CLK_ICHAPIC <14>

PICD0 <5>
PICD1 <5>

IRQ15 <18,19>
SIRQ <18,21,26>

CLK_ICHPCI

T5
M3
F1
C4
D4
B6
B3
N3
G5
M2
M1

ICH_WAKE_UP#

W1
Y1
L5
H2
H1

Y6
AC3
AB2
AC4
AB5
AC5

Y22
V23
AB22
J22
AA21
AB23
AA23
Y21
W23
U22
W21
Y23
U23

HUB_PD0

L22

HUB_PD1

M21

HUB_PD2

M23

HUB_PD3

N20

HUB_PD4

P21

HUB_PD5

R22

HUB_PD6

R20

HUB_PD7

T23

HUB_PD8

M19

HUB_PD9

P19

HUB_PD10

N19

CLK_ICHHUB <14>
HUB_PSTRB <8>
HUB_PSTRB# <8>

D25

ICH_WAKE_UP#

21

RB751V

R423 10K_0402

SWI#<29>

GPIO2

1 2

R424 10K_0402

GPIO3

1 2

R425 10K_0402

GPIO4

1 2

R426 10K_0402

GPIO5

1 2

R427 10K_0402

PIRQA#<18,21>
PIRQB#<18,20>
PIRQC#<18>
PIRQD#<18>

R298 33_0402

12

+VS_HUBREF

PIRQA#
PIRQB#
PIRQC#
PIRQD#

CLK_ICHPCI <14>
DEVSEL# <18,20,21>
FRAME# <18,20,21,27>
PCI_REQA# <18>
PCI_REQB# <18>

IRDY# <18,20,21>
PAR <20,21>
PERR# <18,20,21>
PLOCK# <18,21>

STOP# <18,20,21>
TRDY# <18,20,21,27>

SM_INTRUDER# <18>
SMLINK0 <18>
SMLINK1 <18>
SMB_CLK <12,14,18>
SMB_DATA <12,14,18>
SMB_ALERT# <18>

GATEA20 <28>
H_A20M# <5>

H_FERR# <5>
H_IGNNE# <5>
H_INIT# <5>
H_INTR <5>
H_NMI <5>
H_PWRGD <5>
KBRST# <28>

H_SMI# <5>
H_STPCLK# <5>

HUB_PD[0..10]

+VS_HUBVSWING

12

12

C539
.01UF_0402

Title

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

D

1 2

RB751V

PCIRST# <8,15,20,21,26,27,28>

C534
.01UF_0402

+3VALW

D26

ICH_RI#

21

+3VS

R288 0_0402

1 2

HUB_PD[0..10] <8>

1 2

R335 36.5_1%

Close to ICH3-M.

H_DPSLP#<5,32>

(for use if CPU unable
to support DPSLP#)

Compal Electronics, Inc.

Intel ICH3-M

D

Place closely to
ICH3-M

Place closely to
ICH3-M

+1.5VS

1 2

CLK_ICHAPIC

12

R352
10_0402

12

C559
10PF_0402

CLK_ICHPCI

12

R311
10_0402

12

C518
15PF

12

R287
@10K_0402

CLK_ICHHUB

R306
33_0402

C514
5PF_0402

16 41Friday, November 16, 2001

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

+3V

OVCUR#5
OVCUR#4
OVCUR#3
OVCUR#1

1 1

USBP0+<30>

USBP0-<30>

USBP2+<30>

USBP2-<30>

+3VS

12

R363

2 2

1K_0402

AV_VID4

0=I2C CTRL CPUVID select
1=Bus switch CPUVID select

U25

@74AHCT1G125GW

SIDERST#<19>

3 3

+3VS

12

R441
@10K_0402

12

R443
10K_0402

4 4

RP22
1 8
2 7
3 6
4 5

8P4R_10K

1 2

C597 5PF_0402

1 2

C598 5PF_0402

PIDERST#<19>

+5VS

1

3

R254 0_0402

1 2

M/B ID

12

R442
10K_0402

MB_ID0
MB_ID1

12

R444
@10K_0402

USBP0+
USBP0-

USBP2+
USBP2-

Layout note The Cap c lose to
ICH3-M (< 1 inch)

OVCUR#0<30>
OVCUR#2<30>

R453 0_0402

1 2

AC_VID0<6>
AC_VID1<6>
AC_VID2<6>

+3VALW

AC_VID3<6>
AC_VID4<6>

EC_FLASH#<28>

ICH_M_SEN#<18>

ICH_SPKR<24>

+1.8VS

1 2

R395

0_0805

5
24

12

R376

*

18.2_1%

Note:
R376=22.6_1% for B0(QB63 part)
R376=18.2_1% for B0(QB62 & SL5LF pa rt)

USBP0+
USBP2+

USBP0­USBP2-

OVCUR#0
OVCUR#1
OVCUR#2
OVCUR#3
OVCUR#4
OVCUR#5

ICH_IDE_SRST#

AV_VID4
MB_ID0
MB_ID1

ICH_ACIN

ICH_SPKR

VCCPSUS

MB_ID0 MB_ID1
SST
PT
ST
QT

0 0

01
10

1 1

A

+5VS +3VS

12

R248

1K_0402

+1.8VALW

VCC1.8SUS

R389

1 2

0_0805

U37B

D19

USB_PP0

A19

USB_PP1

E17

USB_PP2

B17

USB_PP3

D15

USB_PP4

A15

USB_PP5

D18

USB_PN#0

A18

USB_PN#1

E16

USB_PN#2

B16

USB_PN#3

D14

USB_PN#4

A14

USB_PN#5

E12

USB_OC#0

D12

USB_OC#1

C12

USB_OC#2

B12

USB_OC#3

A12

USB_OC#4

A11

USB_OC#5

H20

USB_LEDA#0/GPIO32

G22

USB_LEDA#1/GPIO33

F21

USB_LEDA#2/GPIO34

G19

USB_LEDA#3/GPIO35

E22

USB_LEDA#4/GPIO36

E21

USB_LEDA#5/GPIO37

H21

USB_LEDG#0/GPIO38

G23

USB_LEDG#1/GPIO39

F23

USB_LEDG#2/GPIO40

G21

USB_LEDG#3/GPIO41

D23

USB_LEDG#4/GPIO42

E23

USB_LEDG#5/GPIO43

B21

USB_RBIAS

H23

SPKR

U19

VCCA

F17

VCCPSUS3/VCCPUSB0

F18

VCCPSUS4/VCCPUSB1

K14

VCCPSUS5/VCCPUSB2

E10

VCCPSUS0

V8

VCCPSUS1

V9

VCCPSUS2

ICH3-M

R346

1 2

+3VS

@1K_0402

Disable Timeo ut feature

B

21

D10
1SS355

12

C488

.1UF_0402

L63

1 2

FBM-11-201209-601T

VCC1.8SUS

E13

F14

K12

P10V6V7

VCC_SUS0

VCC_SUS1

VCC_SUS2

VCC_SUS3

VCC_SUS4

VCC_SUS5

USB

Interface

Misc

Power

VSS35

VSS36

VSS37

VSS38

E14

E15

E18

E19

ICH_SPKR

B

VCC5REF

12

C573
1UF

+V1.8_ICHLAN

+VCC_RTC

F15

F16F7F8

K10

VCC_USB0/VCC_SUS6

VCC_USB1/VCC_SUS7

VCC_AUX0/VCCLAN1_8

VCC_AUX1/VCCLAN1_8

VCC_AUX2/VCCLAN1_8

VSS39

VSS40

VSS41

VSS42

VSS43

VSS44

VSS45

E20

F22G3G20

H19

AA22J5K11

AB6E6W8

VCC_RTC

VSS46

VSS47

K13

K20

VCC5REF1

VCC5REF2

VSS48

VSS49

VSS50

K21

K22

+3VALW

12

+3VALW

VCCREFSUS

C13W5F9

VCC5REFSUS1

VCC5REFSUS2

VSS51

VSS52

VSS53

K23L3L10

L11

R397

0_0402

VSS54

L12

12

C602
.1UF_0402

+1.8VALW

12

+1.5VS

12
R403

0_0805

VCCPAU

F10

VCCPAUX0/VCCLAN3_3

VCCPAUX1/VCCLAN3_3

P14

U18

V22

VCCPCPU0

VCCPCPU1

VCCPCPU2

R402
0_0805

VCC1.8SUS

C23

B23E7T21D6T1C2A21

N/C0

Power

VCCUSBBG/VCC_SUS8

VCCUSBPLL/VCC_SUS9

ICH3-M (2/2)

VSS

VSS55

VSS56

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

L13

L14

L21

L23

VSS66

M11

M12

M13

M20

M22N5N10

N11

N/C1

VSS67

N12

N/C2

VSS68

N13

N/C3

VSS69

N14

N/C4

VSS70

N21

VSS71

N23

A22F6G6H6J6

VSS102

VSS103

VCCPPCI0

VSS72

VSS73

VSS74

VSS75

P11

P13

P20

VCCPPCI1

VCCPPCI2

VSS76

VSS77

P22R3R5

C

12

C631
.1UF_0402

M10R6T6U6G18

VCCPPCI3

VCCPPCI4

VCCPPCI5

VCCPPCI6

VCCPPCI7

VSS78

VSS79

VSS80

VSS81

VSS82

R21

R23T4T20

C

H18

VCCP0

VSS83

VSS84

T22V3AC23

R451

1 2

1K_0402

Closely Pin AB6

+3VS

P12

V15

V16

VCCP1

VCCPIDE0

VCCPIDE1

VSS85

VSS86

VSS87

VSS88

V20W6W7

W10

V17

V18

VCCPIDE2

VCCPIDE3

VCCPIDE4

VSS89

VSS90

VSS91

W14

W18

W22Y8AA3

+RTCVCC+VCC_RTC

J18

VCCPHL0

VSS92

VSS93

M14

R18

VCCPHL1

VCCPHL2

VSS94

VSS95

AA8

T18

VCCPHL3

VSS96

VSS97

AA12

AA16

+1.8VS

E11K6K18P6P18

VCCCORE0

VCCCORE1

VCCCORE2

VCCCORE3

IDE

Interface

VSS98

VSS99

VSS100

VSS101

AA20

AB8

AC1

AC8

V10

V14

IDE_PDCS1#
IDE_PDCS3#

VCCCORE4

VCCCORE5

VCCCORE6

IDE_SDCS1#
IDE_SDCS3#

IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

IDE_PDDACK#
IDE_SDDACK#

IDE_PDDREQ
IDE_SDDREQ

IDE_PDIOR#

IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#

IDE_PIORDY

IDE_SIORDY

D

R370

100K_0402

ACIN<28,33,35>

AC15
AB15
AC21
AC22

AA14

IDE_PDA0

AC14

IDE_PDA1

AA15

IDE_PDA2

AC20

IDE_SDA0

AA19

IDE_SDA1

AB20

IDE_SDA2
IDE_PDD0

IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9

PDD0

W12

PDD1

AB11

PDD2

AA10

PDD3

AC10

PDD4

W11

PDD5

Y9

PDD6

AB9

PDD7

AA9

PDD8

AC9

PDD9

Y10

PDD10

W9

PDD11

Y11

PDD12

AB10

PDD13

AC11

PDD14

AA11

PDD15

AC12

SDD0

Y17

SDD1

W17

SDD2

AC17

SDD3

AB16

SDD4

W16

SDD5

Y14

SDD6

AA13

SDD7

W15

SDD8

W13

SDD9

Y16

SDD10

Y15

SDD11

AC16

SDD12

AB17

SDD13

AA17

SDD14

Y18

SDD15

AC18
Y13

Y19
AB12
AB18
AC13
AC19
Y12
AA18
AB13
AB19

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Intel ICH3-M

ADY11 LA-1181

D

21

D23 RB751V

PDCS1# <19>
PDCS3# <19>
SDCS1# <19>
SDCS3# <19>

PDA0 <19>
PDA1 <19>
PDA2 <19>
SDA0 <19>
SDA1 <19>
SDA2 <19>
PDD[0..15] <19>

SDD[0..15] <19>

PDDACK# <19>
SDDACK# <19>
PDDREQ <19>
SDDREQ <19>
PDIOR# <19>
SDIOR# <19>
PDIOW# <19>
SDIOW# <19>
PDIORDY <19>
SDIORDY <19>

+3VS

12

ICH_ACIN

2

17 41Friday, November 16, 2001

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

+3VS +3VS

RP13

FRAME#<16,20,21,27>
IRDY#<16,20,21> SERR# <16,20,21>
TRDY#<16,20,21,27>
STOP#<16,20,21>

1 1

1
2
3
4
5

+3VS

PCI_REQA#<16>
PCI_REQB#<16>
REQ#0<16>
REQ#1<16>

1
2
3
4
5

+3VS +3VS

GNT#1<16>
GNT#2<16,21>

PIRQD#<16>

IRQ14<16,19>

1
2
3
4
5

GNT#0<16>

2 2

3 3

GNT#3<16,20>
GNT#4<16>

R434 10K_0402

PM_CLKRUN#<16,20,21,26>

ICH_M_SEN#<17>

SMB_DATA<12,14,16>

SMB_CLK<12,14,16>

ICH_RI#<16>

SMB_ALERT#<16>

1 2

R435 10K_0402

1 2

R267 4.7K_0402

1 2

R262 4.7K_0402

1 2

R291 10K_0402

1 2

R289 10K_0402

1 2

10
9
8
7
6

10P8R_8.2K

RP21

10
9
8
7
6

10P8R_8.2K

RP19

10
9
8
7
6

10P8R_8.2K

1 2

R398 @8.2K_0402

1 2

R400 @8.2K_0402

1 2

R399 @8.2K_0402

+3VS

+3VS

+3VS

+3VS

+3VALW

DEVSEL# <16,20,21>
PERR# <16,20,21>
PLOCK# <16,21>

REQ#2 <16,21>
REQ#3 <16,20>
REQ#4 <16>
SIRQ <16,21,26>

IRQ15 <16,19>
PIRQA# <16,21>
PIRQB# <16,20>
PIRQC# <16>

+1.5VS

12

+

+3VS

12

+

+3VS

12

VCCPSUS

12

+

22UF_10V_1206

+1.8VS

12

+

VCC1.8SUS

12

+

22UF_10V_1206

12

C503
1UF

C475
22UF_10V_1206

C576
47PF_0402

C609

C522
100UF_D2_6.3V

C586

C499
.1UF_0402

12

+

12

C524
.1UF_0402

12

12

C583

.1UF_0402

12

C517
.1UF_0402

C596
22UF_10V_1206

12

C611
.1UF_0402

12

C588
.1UF_0402

12

C550
.1UF_0402

12

C589
.1UF_0402

12

C569
.1UF_0402

C590
.1UF_0402

12

C519
33PF_0402

12

12

C603
.1UF_0402

C610
47PF_0402

12

C601
.1UF_0402

12

C545
.1UF_0402

12

C567
.1UF_0402

12

C476
.1UF_0402

12

12

47PF_0402

C600
.1UF_0402

12

C509
.1UF_0402

C608

12

C485
.1UF_0402

12

C530
33PF_0402

12

C566
.1UF_0402

12

C561
.1UF_0402

12

C591
.1UF_0402

12

C497
.1UF_0402

12

C563

47PF_0402

12

C568
.1UF_0402

12

C521
.1UF_0402

12

C479

47PF_0402

12

C523
.1UF_0402

12

C490
.1UF_0402

12

C491
.1UF_0402

+3VALW

R283 4.7K_0402

SMLINK0<16>
SMLINK1<16>

1 2

R284 4.7K_0402

1 2

SM_INTRUDER#<16>

4 4

A

1 2

R263 10K_0402

+RTCVCC

Title

Size Document Number Rev

B

C

Date: Sheet of

Compal Electronics, Inc.

ICH3-M Decoupling & Pull-Up

ADY11 LA-1181

D

18 41Friday, November 16, 2001

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

E

+5VSHDD

SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130 mOHM
VGS: -2.5V, RDS: 190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V

3

2

S

G

D 1

INDEX#<26>

DRV0#<26>

DISKCHG#<26>

MTR0#<26>

FDDIR#<26>

STEP#<26>
WDATA#<26>
WGATE#<26>

TRK0#<26>

WRPRT#<26>

RDATA#<26>

FDD_PRES#<29>

HDSEL#<26>

100K_0402

PHDD_LED#
SHDD_LED#

DRV0#

DISKCHG#
INDEX#
WRPRT#
TRK0#

R79

INDEX#
DRV0#
DISKCHG#

MTR0#
3MODE#_11
FDDIR#
3MODE#_13
STEP#

WDATA#
WGATE#
TRK0#
WRPRT#
RDATA#
HDSEL#

1 2

# means no-pop for Tang
Note: PT-test must pop these component s

FDD Connector

+5VS

JP24

1

+5V

2

INDEX

3

+5V

4

DRIVE SELECT

5

+5V

6

DISK CHANGE

RP20
1 8
2 7
3 6
4 5

8P4R_1K

+5VS

R238

100K_0402

1 2

12
13

7

NC

8

READY

9

DENSITY OUT

10

MOTOR ON

11

NC

12

DIRECTION

13

DENSITY 2

14

STEP

15

GND / NC

16

WRITE DATA

17

GND

18

WRITE GATE

19

GND

20

TRACK 00

21

NC / GND

22

WRITE PROTECT

23

GND

24

READ DATA

25

GND

26

SIDE 1 SELECT

#85201-2605-ACES-FDDCON

3MODE#<26>

+5VS

U26D

74HCT08

11

Placec caps. near FDD CONN.

+5VS

12

C599
#.1UF_0402

1 2

R366 @0_0402

3MODE#

1 2

R365 #0_0402

WDATA#
WGATE#
HDSEL#
FDDIR#

+5VS

+5VS

14

1
2

7

1 2

.1UF_0402

U26A

74HCT08

10

C101

12

RP15
6
7
8
9

10P8R_1K

C592

#10UF_16V_1206

3MODE#_11
3MODE#_13

ACT_LED#

3

5
4
3
2
1

12

C587

#1UF_25V_0805

STEP#
MTR0#
RDATA#
DRV0#

12

+5VS

ACT_LED# <27>

C584
#.1UF_0402

Q14

R237

100K_0402

Q13

2N7002

C364
.1UF_0402

C377
.1UF_0402

+5VS

12

R428
150K

12

C100
1UF_25V_0805

12

C366

1UF_25V_0805

12

C378

1UF_25V_0805

SI2301DS

2

12

C438
.01UF_0402

12

C102
.1UF_0402

12

C81
10UF_16V_1206

12

C85
10UF_16V_1206

13

+12VALW

HDD Connector

PDD[0..15]<17>

1 1

PIDERST#<17>

PDDREQ<17>
PDIOW#<17>
PDIOR#<17>
PDIORDY<17>

PDA1<17>
PDA0<17>
PDCS1#<17>

2 2

3 3

SDIOW#<17>

SDIORDY<17>

SDA1<17>
SDA0<17>
SDCS1#<17>

4 4

Correct HDD pin define ,pls update layout

PDD7
PDD6
PDD5
PDD4 PDD11

R244

@10K_0402

INT_CD_L<23>
SIDERST#<17>

@10K_0402

PDD3 PDD12
PDD2 PDD13
PDD1 PDD14

1 2

PDD0 PDD15
PDDREQ

PDIORDY
RPDDACK#
RIRQ14

PHDD_LED#

+5VSHDD

+3VS

SDD[0..15]<17>

1 2

1 2

C413 47PF_0402

R76

1 2

+5VS

C411 47PF_0402

SDD7
SDD6
SDD5
SDD4 SDD12
SDD3
SDD2
SDD1
SDD0

SDIORDY
RIRQ15

SHDD_LED#

SEC_CSEL

R197
470_0402

1 2

+3VS

PDD[0..15]

JP20

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

HH99221-S6-HDDCON

R243

1 2

4.7K_0402

CD-ROM Connector

SDD[0..15]

JP16

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

CD-ROM CONN.

R212

4.7K_0402

SDIORDY

1 2

PDD8
PDD9
PDD10

PCSEL

PDIORDY

SDD8
SDD9
SDD10
SDD11

SDD13
SDD14
SDD15
SDDREQ

RSDDACK#
PDIAG#

W=80mils

C83 .1UF_0402

CD_AGND <23>

1 2

R239

1 2

470_0402

PDA2 <17>
PDCS3# <17>

+5VSHDD

INT_CD_R <23>

R206

1 2

PDDACK#<17>
IRQ14<16,18>

SDDACK#<17>
IRQ15<16,18>

1 2

C416

SDDREQ <17>
SDIOR# <17>

100K_0402

SDA2 <17>
SDCS3# <17>

PIDEPWR<16>

Placea caps. near HDD
CONN.

+5VSHDD

12

12

C451
1000PF_0402

1 2

R242 22_0402

1 2

R241 22_0402

PDDREQ

1 2

R213 22_0402

1 2

R207 22_0402

SDDREQ

47PF_0402

+5VS

+5VS

C445
10UF_16V_1206

+5VS

+5VS

12

13

D

2

G

S

Layout Note: +5VSHD D trace
width 60 mil

12

C444
10UF_16V_1206

RPDDACK#
RIRQ14

1 2

R240 @5.6K_0402

C443

1 2

33PF_0402

RSDDACK#
RIRQ15

1 2

R217 @5.6K_0402

C399

1 2

33PF_0402

Placea caps. near CDROM
CONN.

12

12

C365
1000PF_0402

12

12

C376
1000PF_0402

A

Title

Size Document Number Rev

B

C

D

Date: Sheet of

Compal Electronics, Inc.

IDE/FDD/CD-ROM Module

ADY11 LA-1181

19 41Friday, November 16, 2001

E

2

5

(LAN_100LI

(LAN_10LI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

12

12

C372

#.01UF_0402

D D

AD[0..31]<16,21,27>

C C

C/BE#0<16,21,27>
C/BE#1<16,21,27>
C/BE#2<16,21,27>
C/BE#3<16,21,27>

PAR<16,21>
PIRQB#<16,18>

PCIRST#<8,15,16,21,26,27,28>

GNT#3<16,18>

REQ#3<16,18>

FRAME#<16,18,21,27>

CLK_PCI_LAN<14>

DEVSEL#<16,18,21>

LAN_PME#<29>

PM_CLKRUN#<16,18,21,26>

R198

1 2

#100_0402

RP10
1 8
2 7
3 6
4 5

@8P4R_10K

IRDY#<16,18,21>
TRDY#<16,18,21,27>

STOP#<16,18,21>
PERR#<16,18,21>
SERR#<16,18,21>

B B

A A

SOS1#
SOS2#
SOS3#
SOS4#

C369
#.01UF_0402

R226

1 2

#10K_0402

+3VASB

12

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

LAN_SOS1#
SOS2#
SOS3#
SOS4#
LAN_SOS5#
SOS6#
SOS7#

LAN_AD17

LAN_RST#

CLK_PCI_LAN

LAN_AD17AD17

5

C374

#.01UF_0402

B11
D11
C11
B12
A12
C12
B13
A14
C13
E11
B14
E12
D13
F11
E13
E14

K11
K12

K13

N14
N13
P14
P12

M11

N12
P11
N11

D12
F12
H13

M13

G12

M12

H11
G13
H12
F14
G11
F13

M10

C10
D10

SOS5#
SOS6#
SOS7#

12

C363

#.01UF_0402

12

C422

#.01UF_0402

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15

J12

AD16

J13

AD17
AD18

L12

AD19
AD20
AD21

L11

AD22

L13

AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE#0
CBE#1
CBE#2
CBE#3

M3

SOS1#

L3

SOS2# / TXCLK

L4

SOS3# / TXEN

K3

SOS4# / CRS

F4

SOS5# / RXOE

C2

SOS6# / RXCLK

B1

SOS7# / MDCLK

PAR
IDSEL

L9

INTA#

N9

RST#

M9

GNT#

L10

REQ#

J11

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#

M8

PME#
CLKRUN#

A1

SMBDATA

C3

SMBCLK

G3

SMBCS#
WPOUT

GRST#

L8

PCICLK

R224 @10K_0402

1 2

R234 @10K_0402

1 2

R232 @10K_0402

1 2

+3VS

K1M2M7

MAINP5

N10

+3VASB

12

C397

#.01UF_0402

AUXP

AUX5PN

VSSPCI1

VSSPCI2

VSSPCI3

VSSPCI4

M14

H14

D14

12

C410

#.01UF_0402

+3VS

P10

L14

VDDPCI1

VDDPCI2

+3VASB+3VASB

C14

A11

G14D1J1

B10A6E1G1H1P9J14B8P2N3N1N5N7

VDDIO1

VDDIO2

VDDPCI3

VDDPCI4

VDDPCI5

3COM
3C920 LAN CONTROLLER

VSSPCI5

VSSIO1

VSSIO2

VSSIO3

VSSIO4

A13D2J2

A10A7E2F2H2P1P7N8K14A8L1N2P3K2P5M6F6F7F8F9G6G7G8G9H6H7H8H9J6J7J8

CLK_PCI_LAN

R199

@33_0402

1 2

C367

@10PF_0402

12

#.01UF_0402

VDDIO3

VDDIO4

VSSX1

VSSX2

C375

VSSX3

VDDX1

VSSX4

VSSX5

LAN_P1

VDDX2

VDDX3

VSSX6

VSSX7

4

VDDX4

VSSX8

LAN_DISABLE#<28>

4

VDDX5

VSSX9

12

C395

#.01UF_0402

+3RX_PWR

VDDX7

VDDRX1

VSSRX1

VSSRX2

VDDRX2

VDDRX3

VSSRX3

SOS5#<29>

SOS1#<29>

+3VS

VDDTX1

VSSTX1

VSSTX2

12

#.01UF_0402

VDDTX2

12

C371

C370

#.01UF_0402

M1

M4

PME

GND

GND

GND

GND

GND

GND

GND

D28 #RB751V

D27 #RB751V

21

D29 #RB751V

R208 @0_0402

1 2

VDDLVDET

GND

GND

GND

GND

LAN_SOS5#

21

LAN_SOS1#

21

LAN_RST#

12

C373

#.01UF_0402

12

DTOEE / 100LNK

DFRAMEE / 10LNK

GND

GND

GND

GND

GND

J9

R236

C419

#10K_0402

#1UF

LD0 / POR0
LD1 / POR1
LD2 / POR2

LD3

LD4 / POR4

LD5

LD6 / POR6

LD7

LA0
LA1

LA2 / POR10

LA3
LA4
LA5

RXD0 / LA6
RXD1 / LA7
RXD2 / LA8
RXD3 / LA9

RXER / LA10

RXDV / LA11

TXD0 / LA12
TXD1 / LA13
TXD2 / LA14
TXD3 / LA15

COL / LA16

ROMCS#

MEMR#

MEMW#

MDIO

EESEL

EECLK / ACT

TXOP
TXON

RXIP
RXIN

REF100

REF10

MEDTEST
GLBTEST#
PHYTEST#

X25L0

X25HI

TXCT (NC)

NC3
NC5
NC6

#3C920-V3

R450 #10K_0402

1 2

R449 #10K_0402

1 2

R452 #10K_0402

1 2

3

12

12

12

+3VASB

U21

B7
C7
B6
D6
C6
C5
A5
B5

A4
D5
B4
C4
A3
A2

C1
D3
E4
E3

F3
G4

H3
H4
J4
J3
K4

D7
B3
D4
B2

D9
A9
C8
D8

N6
P6

N4
P4

M5
L6

L7
C9
B9

G2

F1

L5
L2

P8
P13

R215 #10K_0402

1 2

R218 #10K_0402

1 2
1 2

R222 #10K_0402

R233

1 2

LAN_EESEL
LAN_EECLK
LAN_DTOEE
LAN_DFRMEE

LAN_TX+
LAN_TX-

LAN_RX+
LAN_RX-

LAN_100
LAN_10

LAN_CRY1

LAN_CRY2

C423

#33PF_0402

DSX630G H:1.2mm +-30ppm
(20PF)

+3VASB

12

C427

#.01UF_0402

#10K_0402

#10K_0402

T1

1

#25MHZ

1 2

12

C424

#33PF_0402

R436

Note1

#56.2_1%_0805

Y2

XTAL

C425

C426

#.01UF_0402

#.01UF_0402

+3TX_PWR+3TX_PWR

12

12

C396

C389

#.01UF_0402

#.01UF_0402

Set Standard features

Set SMBus Mandatory

Set 16K EEPROM

U17

1

CS

2

SK

3

DI

4

DO

1 2

R225

12

#AT93C86-10SC2.7

C412

1 2

#4.7PF_NPO

12

R228

#56.2_1%_0805

12

C407

#.1UF_0402

Place closely to Lan chips

Note1:Place this test point in the RAM door area

3

2

+3VASB +3VALW+3RX_PWR

L56

#FBM-11-160808-121T

C428
#2.2UF_16V_0805

C381

#2.2UF_16V_0805

VCC

NC

NC/ORG

GND

#61.9_1%_0805

12

L54

12

#FBM-11-160808-121T

+3VASB

8
7
6
5

#FLM-160808-68NKT

L55

12

R214

#61.9_1%_0805

C356

#2.2UF_16V_0805

R414

#10K_0402

1 2

AT93C66 P in6 (ORG)
1=16 bit ; 0=8 bit

Place closely to Lan chips

12

12

R223

The cap please closely to H0022

U15

LAN_RX+

1

LAN_RX-

12

LAN_TX+
LAN_TX-

Layout Note:
H0022 Pls closely to RJ45 Conn.

2

RD+

2

RD-

3

CT

6

CT

7

TD+

8 9

TD- TX-

#Pulse-H0022

1

L51 @BLM21A601SPT

L52 #FBM-11-201209-601T

FDC6320C
Gate 1: N-MOS
Gate 2: P-MOS

12

12

+3V

12

C361

#.01UF_0402

+3VASB

LAN_DTOEE

NK)

LAN_DFRMEE

NK)

10M LINK : Green LED
100M LINK :O range LED
Activity :
Blink(Y ellow LED)

R448 Closel y AT93C86

LAN_EECLK

(LAN_ACT)

LAN_RJ45T­LAN_RJ45T+

16

RX+

15

RX-

14

CT

11

CT

10

TX+

@1000PF_1206_2KV

LAN_RJ45R+
LAN_RJ45R-

12

R178

R177

#75_1%

#75_1%12R165

R174

1 2

#0_0402

C298

1 2

Compal Electron ics, Inc.

Title

3COM 3C920 LAN

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

+3RX_PWR+3VASB

LAN_100

LAN_P1

LAN_10

Q36

1

G1

D1

2

S2

S1

3 4

G2 D2

#FDC6320C

Q37

1

G1

D1

2

S2

S1

3 4

G2 D2

#FDC6320C

R448

12

#200_0402

12

12

#75_1%

1 2

12

12

12

R158
#75_1%

C253

#1000PF_1206_2KV

1

R231
#11.5K_1%

R209
#1.62K_1%

R204
#1.91K_1%

6
5

6
5

JP10

2

PR1-

1

PR1+

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

#JM36113-L5H7

12

#.1UF_0402

12

#.01UF_0402

R447

#200_0402

R437

#200_0402

20 41Friday, November 16, 2001

C417

C388

12

12

+3VASB

121110

LED_GREEN

LED_ORANGE

SHLD1

13

9

LDE_YELLOW-

LDE_YELLOW+

SHLD2

14

2

A

B

C

D

E

C340
.1UF_0402

+3VS

12

C338
.1UF_0402

S1_IOWR# <22>
S1_IORD# <22>
S1_OE# <22>

S1_CE2# <22>

S1_REG# <22>

S1_CE1# <22>
S1_RST <22>

S1_WAIT# <22>
S1_INPACK# <22>

S1_WE# <22>

S1_BVD1 <22>
S1_WP <22>

S1_RDY# <22>
PCM_SPK# <24>

S1_BVD2 <22>
S1_CD2# <22>

S1_CD1# <22>
S1_VS2 <22>
S1_VS1 <22>

12

C337
.1UF_0402

S1_A16

12

C383
.1UF_0402

12

C357
.1UF_0402

12

C353
.1UF_0402

12

C382
.1UF_0402

S1_VCC

+3VS

12

12

12

74

VCCD0#

VCCD1#

.1UF_0402

C348

717273

VPPD0

VPPD1

PQFP 144

22.2 X

22.2 X

1.60

GND

GND

6

22

C359

S1_A[0..25]

4 4

3 3

2 2

PCM_SUSP#<28>

CLK_PCI_PCM

1 1

S1_D[0..15]

+3VS

12

12

1 2

R192 10K_0402

RB751V

R201
@33_0402

C384
@22PF_0402

AD[0..31]

D7

21

AD[0..31]<16,20,27>

S1_A[0..25] <22>

CLK_PCI_PCM<14>

PCM_PME#<29>

PM_CLKRUN#<16,18,20,26>

PCIRST#<8,15,16,20,26,27,28>

DEVSEL#<16,18,20>

PCM_RI#<27>

V_PRST#<22,28>

FRAME#<16,18,20,27>

AD20

SIRQ<16,18,26>
PLOCK#<16,18>

C/BE#3<16,20,27>
C/BE#2<16,20,27>
C/BE#1<16,20,27>
C/BE#0<16,20,27>

IRDY#<16,18,20>

TRDY#<16,18,20,27>

STOP#<16,18,20>
PERR#<16,18,20>
SERR#<16,18,20>

PAR<16,20>
REQ#2<16,18>
GNT#2<16,18>

PIRQA#<16,18>

4.7UF_10V_0805

VPPD0<22>S1_D[0..15] <22>
VPPD1<22>
VCCD0#<22>
VCCD1#<22>

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

PCIRST#

1 2

R195 0_0402

1 2

R203 100_0402

PCM_RI#

3

AD31

4

AD30

5

AD29

7

AD28

8

AD27

9

AD26

10

AD25

11

AD24

15

AD23

16

AD22

17

AD21

19

AD20

23

AD19

24

AD18

25

AD17

26

AD16

38

AD15

39

AD14

40

AD13

41

AD12

43

AD11

45

AD10

46

AD9

47

AD8

49

AD7

51

AD6

52

AD5

53

AD4

54

AD3

55

AD2

56

AD1

57

AD0

12

C/BE3#

27

C/BE2#

37

C/BE1#

48

C/BE0#

20

PCIRST#

28

PCIFRAME#

29

PCIIRDY#

31

PCITRDY#

32

PCIDEVSEL#

33

PCISTOP#

34

PCIPERR#

35

PCISERR#

36

PCIPAR

1

PCIREQ#

2

PCIGNT#

21

PCIPCLK

59

RI_OUT#/PME#

70

SUSPEND#

13

IDSEL

60

MF0

61

MF1

64

MF2

65

MF3

67

MF4

68

MF5

69

MF6

66

G_RST#

OZ6912

12
C351

.1UF_0402

18

44

90

126

VCCP

VCCP

VCCCB

VCCCB

GND

GND

GND

GND

GND

GND

42

58

78

94

114

130

122

138

VCC

VCC

RSVD/D14

84

102

100

C339
.1UF_0402

+3VALW

+3VS

14

30

50

86

VCC

VCC

VCC

VCCP

VCCP

CAD31/D10

CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0

CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6

CAD19/A25

CAD18/A7
CAD17/A24
CAD16/A17

CAD15/IOWR#

CAD14/A9

CAD13/IORD#

CAD12/A11

CAD11/OE#

CAD10/CE2#

CAD9/A10

CAD8/D15
CAD6/D13
CAD4/D12
CAD2/D11

CCBE3#/REG#

CCBE2#/A12

CCBE1#/A8

CCBE0#/CE1#

CRST#/RESET

CFRAME#/A23

CIRDY#/A15

CTRDY#/A22

CDEVSEL#/A21

CSTOP#/A20
CPERR#/A14

CSERR#/WAIT#

CPAR/A13

CREQ#/INPACK#

CGNT#/WE#

CCCLK/A16

CSTSCHNG/BVD1

CCLKRUN#/WP

CBLOCK#/A19

CINT#/READY

SPKROUT

CAUDIO#/BVD2

CCD2#/CD2#
CCD1#/CD1#

CVS2/VS2#
CVS1/VS1#

RSVD/A18

RSVD/D2

143

63

VCCI

CAD7/D7
CAD5/D6
CAD3/D5
CAD1/D4

CAD0/D3

1 2

C345
.1UF_0402

U18

144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76

125
112
99
88

119
111
110
109
107
105
104
133
101
123
106
108

135
136

103
132
62

134
137

75
117
131

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#

1 2
R186 33_0402
S1_BVD1
S1_WP

S1_A19
S1_RDY#
PCM_SPK#

S1_BVD2
S1_CD2#

S1_CD1#
S1_VS2
S1_VS1

S1_D2
S1_A18
S1_D14

Compal Electronics, Ltd.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

PCMCIA controller OZ6912

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

21 41Friday, November 16, 2001

E

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

1 1

B

C

D

E

PCMCIA Power Controller

S1_VCC

12

13
12
11

C404

4.7UF_10V_0805
S1_VPP

C414

.1UF_0402

+12VALW

9

U22
TPS2211

12V

VCC
VCC
VCC

+5VALW

VCCD0# <21>
VCCD1# <21>
VPPD0 <21>
VPPD1 <21>

V_PRST# <21,28>

+

C362

4.7UF_25V_1206

S1_VCC
S1_VCC

C406
.1UF_0402

S1_VCC

L50

1 2

FBM-11-160808-800LMT

S1_VCCL

12

12

C350

C346

.1UF_0402

10UF_10V_1206

S1_A[0..25]<21>
S1_D[0..15]<21>

S1_D3 S1_CD1#
S1_D4
S1_D5
S1_D6
S1_D7

S1_CE1#<21>
S1_OE#<21> S1_VS1 <21>

S1_WE#<21>
S1_RDY#<21>

S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
S1_VCCL S1_VCCL

S1_VPP S1_VPP

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP

S1_A[0..25]
S1_D[0..15]

CardBus Socket

JP11

1

1

3

3

5

5

7

7

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

21

21

22

23

23

24

25

25

26

27

27

28

29

29

30

31

31

32

33

33

34

35

35

36

37

37

38

39

39

40

41

41

42

43

43

44

45

45

46

47

47

48

49

49

50

51

51

52

53

53

54

55

55

56

57

57

58

59

59

60

61

61

62

63

63

64

65

65

66

67

67

68

69

GND

GND

71

GND

GND

73

GND

GND

75

GND

GND

77

GND

GND

79

GND

GND

81

GND

GND

83

GND

GND

C324

1 2

12

1000PF_0402

S1_CD1# <21>

S1_CE2# <21>
S1_IORD# <21>

S1_IOWR# <21>

S1_VS2 <21>
S1_RST <21>
S1_WAIT# <21>
S1_INPACK# <21>
S1_REG# <21>
S1_BVD2 <21>
S1_BVD1 <21>

S1_CD2# <21>S1_WP<21>

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84

S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21

S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#

C400

1000PF_0402

10

C432

5

5V

6

.1UF_0402

5V

+3VALW

3

3.3V

4

2 2

C431
.1UF_0402

3.3V

VPP

1

VCCD0

2

VCCD1

15

VPPD0

14

VPPD1

8

OC

GND

SHDN

7

16

V_PRST#

+3VALW +5VALW

12

C405
10UF_10V_1206

3 3

12

C435
10UF_10V_1206

S1_VPP

12

C409
1UF_25V_0805

S1_A23
S1_WP

S1_VPP

12

C355
.01UF_0402

1 2

R181 22K_0402

1 2

R193 22K_0402

FOXCONN_1CA415M1-TA_68P

4 4

A

Title

Size Document Number Rev

B

C

D

Date: Sheet of

Compal Electronics, Inc.

ADY11 LA-1181

CardBus Socket

E

22 41Friday, November 16, 2001

2

A

reserve for AC97 coedc us

ing only

short the digital ground and ana

long ground

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

+5VAU

L61

12

R364

1 2

@100K_0402

C572

@.1UF_0402

+5VALW

12

13

D

Q30

S

@2N7002

1 2

R344

2

G

@BLM21A601SPT

12

R353
@2.4K

D20

1 1

@AS2431L

2

1 3

@442_1%

B

SUSP <31>

R343

1 2

@5.11K_0.5%

+12VALW

3
2

12

C571 @68PF

1 2

R340

1 2

@0_0402

1 2

84

U34A

+

-

@LM358

@5.11K_0.5%R341

C548 @220PF

@.1UF_0402
C557

1

R359
@5.1K

12

2

G

12

12

+5VALW

C549

13

D

S

C

12

Q25
@SI2306DS

VDDA

C560
@.1UF_0402

D

C580

@4.7UF_10V_0805

SUSP#<27,28,31,32,36>

W=40Mil

12

12

C582

.1UF_0402

E

U36

4

VIN

VOUT

2

SENSE

DELAY

7 1

ERROR CNOISE

8

ON/OFF#

GND

SI9182DH-AD

F

G

H

VDDA+5VALW

5
6

3

R383

1 2

12

10K_1%

12

C577

R394

28.7K_1%

12

4.7UF_10V_0805

C579

12

C581
.1UF_0402

.01UF_0402

@.1UF_0402

AVDD_AC97

L59

1 2

VDDA

FBM-11-201209-121MT

C473
.1UF_0402

12
12

C512

12

4.7UF_10V_0805

14
15
16
17
23
24
18
20
19
21
22
13
12

11
10

45
46

47
48

5

4
7

U30
STAC9700

25

38

AVCC

AUX_L
AUX_R
VIDEO_L
VIDEO_R
LIN_IN_L
LIN_IN_R
CD_L
CD_R
CD_GNA
MIC1
MIC2
PHONE
PC_BEEP

RESET#
SYNC
SDATA_OUT
ID0#

ID1#
EAPD#
S/PDIF_OUT
GND

GND

AVCC

LINE_OUT_L

LINE_OUT_R

MONO_OUT

HP_OUT_L

HP_OUT_R

BIT_CLK

SDATA_IN

XTL_OUT

VREFOUT

REFFLT

12

12

C515

C510
.1UF_0402

12

2 2

.1UF_0402

CD_L_R

INT_CD_L<19>
INT_CD_R<19>

3 3

MONO_IN<24>

MONO_IN

MD_SPK<25>

47K_0402

R310

1 2

4.7K_0402

R327 6.8K_1%
R328 6.8K_1%
R345 6.8K_1%
R326 6.8K_1%
R320 @1K_0402
R321 1K_0402

12

C516

R309

2700PF

1 2

12
12
12
12
12
12

12

C619
2200PF

CD_GNA

CD_AGND<19>

4 4

R330

3.3K_0402

12

12

R322

3.3K_0402

1 2

C527 1UF_25V_0805

CD_R_R

1 2

C529 1UF_25V_0805

CD_GNA

1 2

C528 2.2UF_16V_0805

MICIN<24>

C618 .1UF_0402

1 2

MDSPK

1 2

C526 1UF_25V_0805

1 2

C507 1UF_25V_0805

AC97_RST#<16,25>

IAC_SYNC<16,25>

IAC_SDATAO<16,25>

R276 @10K_0402
R275 @10K_0402

1

VCC

XTL_IN

AFLT1
AFLT2

FLT3D

BPCFG

FLTO

AGND
AGND

9

VCC

FLTI

NC
NC

NC

VDDC

12

C484
.1UF_0402

LINEL

35

LINER

36

MDMIC

37
39

1 2

C472 @1000PF_0402

41

1 2

C471 @1000PF_0402

1 2

6

R295 22_0402

1 2

8

R296 47_0402

2

3
29

C498 1000PF_0402

30

C495 1000PF_0402

28
27
32

31
33
34
43
44

40
26
42

12

C500
.1UF_0402

1 2
1 2

12

C489

@1000PF_0402

12

C487
@.047UF

1 2

R302 0_0805

12

C501

4.7UF_10V_0805

12

1 2

1 2

1 2

C474 @1000PF_0402

IAC_BITCLK <16,25>
SDATA_IN0 <16>

Y3

24.576 MHz

+

C493
@4.7U_25V_1206

@1UF_25V_0805

+3VS

C467
1000PF_0402
C478
1000PF_0402

C480
@1UF_25V_0805

1 2

R272

@100K_0402

C496
@15PF_0402

C483 22PF_0402

C486 22PF_0402

1UF_25V_0805

12

R299
@100K_0402

1 2

C494

C492

LEFT <24>
RIGHT <24>

MD_MIC <25>

12

12

C620
.1UF_0402

12

C506
.1UF_0402

12

C502
1UF_25V_0805

12

C449
@.1UF_0402

VDDA

12

C450
@4.7UF_10V_0805

A

B

Title

Size Document Number Rev

C

D

E

F

Date: Sheet of

Compal Electronics, Inc.

ADY11 LA-1181

G

AC97 CODEC

23 41Friday, November 16, 2001

2

H

A

10 mils tr

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

E

Speaker Connector

L57

1 2

+5VAMP

1 1

W=40mils

12

C463
.1UF_0402

INTSPK_L+

1 2

LEFT

LEFT<23>

RIGHT<23>

2 2

1 2

C454 .01UF_0402

RIGHT

1 2

C453 .01UF_0402

LEFT

1 2

C457 1UF_25V_0805

RIGHT

1 2

C456 1UF_25V_0805

MUTE<28>

INTSPK_R+

INTSPK_L+

INTSPK_R+

NBA_PLUG

OP_SHUT

1 2
1 2
1 2
1 2
1 2
1 2
1 2

R251150K

4

R25050K
R252150K
R25350K
R256100K
R25575K
R258100K
R25975K

LLINEIN

21

RLINEIN

5

LHPIN

20

RHPIN

16

HO/LINE#

14

SE/BTL#

8

SHUTDW

11

MUTEIN

BLM21A05_0805

@BLM21A05_0805

7

18

LVDD

RVDD

L58

1 2

ROUT+

ROUT-

LOUT+

LOUT-

MUTEOUT

LBYPASS
RBYPASS

GND/HS

GND/HS

GND/HS

GND/HS

TPA0202

11213

24

+3VS

12

R357
100K_0402

U26B

3 3

5

4

BEEP<29>

74HCT08

6

+5V POWER

R360

1 2

10K_0402

C562

.1UF_0402

U35

1

NC

2

A

3

12

GND

PCM_SPK#<21>

ICH_SPKR<17>

4 4

VCC

TC7SH14

+3V POWER

Y

+3VS

5
4

1 2

1 2

1 2

R348

1 2

2K_0402

R339

2K_0402

R331

2K_0402

C556

.1UF_0402

1 2

1 2

C546

1UF_25V_0805

C536

1UF_25V_0805

U27

22

15

3

10

9

2

NC

17

NC

23

NC

6
19

C553

1 2

1UF_25V_0805

R315

@10K_0402

+5VALW

VDDA

12

C464

4.7UF_10V_0805

12

4.7UF_10V_0805

+5VS

12

R356
100K_0402

12

INTSPK_R+

INTSPK_R-

INTSPK_L+

INTSPK_L-

OP_SHUT

OPBPASS

C459

VDDA

2

2 1

12

R329
100K_0402

1
3

D16
1SS355

12

C462
.1UF_0402

12

C461
.1UF_0402

C533

1 2

@.1UF_0402
C525

1 2

1UF_25V_0805

Q21
2SC2411EK

MICIN<23>

MONO_IN

C520

1 2

.22UF_0805

C531

1 2

@.22UF_0805

MONO_IN <23>

AVDD_AC97

R317

0

R312

VDDA

MICSEL

MIC_IN

@1K_0402

R246

2K_0402

R567

49.9

1

SEL

2

OUT

R247
1K_0402

12

1UF_25V_0805

AVDD_MIC

C452

4

U32

VSUP

EXT_MIC
INT_MIC-

INT_MIC+

GND

CMAMP110

7

BIAS

12

C542

.1UF_0402

3
8
6
5

INTSPK_R+

INTSPK_L+

VBIAS

EXTRMIC
MIC­MIC+

C448
220UF_10V_D

12

C633

10UF_10V_1206

+

1 2

+

1 2

C447
220UF_10V_D

.22UF_0805

1 2

1 2
FBM-11-160808-121T
L47

L46

1 2

FBM-11-160808-121T

C446

EXTMIC EXT_MIC

47PF_0402

C538

1 2

VDDA

.22UF_0805

R337
2K_0402

R338

1K_0402

C537

1 2

.22UF_0805

C124

NBA_PLUG
PR_RIGHT

L43 FBM-11-160808-121T
PR_LEFT
L44 FBM-11-160808-121T

47PF_0402
1 2
1 2

C128

47PF_0402

12

C626

12
47PF_0402
MICSEL

C175

12

C552

1UF_25V_0805

VDDA

12

VDDA

12

R269
100K

12

C121
47PF_0402

INTSPK_R+
INTSPK_R­INTSPK_L+
INTSPK_L-

12

R351

100K_0402

BIAS

12
C226

47PF_0402

R350
2K_0402

R349
1K_0402

PR
PL

12

ace

EXT. MIC

JP8

5
4
3

6
2
1

JA6333L-100

INT_MIC- <30>

C558

1UF_25V_0805

INT_MIC+ <30>

LINE OUT

JP7

5
4
3

6
2
1

JA6333L-100

JP19

1

1

2

2

3

3

4

4

Speaker Conn.

A

Title

Size Document Number Rev

B

C

D

Date: Sheet of

Compal Electronics, Inc.

AMP & Audio Jack

ADY11 LA-1181

24 41Friday, November 16, 2001

2

E

5

1: Have primary CODEC on mot

her board

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

12

C379

.1UF_0402

+3VMDC

D D

+3VALW

+3V

1 2

R190 0_0805

1 2

R191 @0_0805

4.7UF_16V_A

C630

4

+3V

C393
@1000PF_0402

IAC_SDATAO<16,23>

AC97_RST#<16,23>

MD_MIC<23>

12

C394
@.1UF_0402

+3VMDC

JP22

1

MONO_OUT/PC_BEEP

3

AGND

5

AUXA_RIGHT

7

AUXA_LEFT

9

CD_GND

11

CD_RIGHT

13

CD_LEFT

15

GND

17

3.3Vaux

19

GND

21

3.3Vmain

23

AC97_SDATA_OUT

25

AC97_RESET#

27

GND

29

AC97_MSTRCLK

AMP-108-5424

12

1 2

3

12

C386
@1000PF_0402

AC97_SDATA_IN1
AC97_SDATA_IN0

12

C380
@.1UF_0402

AUDIO_PWDN

MONO_PHONE

RESERVED

GND

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

AC97_SYNC

GND

AC97_BITCLK

+5VMDC

1 2

R200 @0_0805

2

+5V

MDC Note

1

Pin 1 is NC for Pctel and connexant MDC modem

2
4
6
8
10

+5V

12
14
16
18
20
22
24
26
28
30

MDC_DN# <28>

MD_SPK <23>

1 2

R216 10K_0402

R221
@22_0402
R220
22_0402

12
12

Pin 2 is NC for Pctel and connexant MDC modem

+3V

IAC_SYNC <16,23>
SDATA_IN1 <16>

IAC_BITCLK <16,23>

MDC Conn.

C C

Screw Hole

1

Fiduial Mark

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

SMDC40M80

1

SMDC40M80

1

SMDC40M80

1

SMDC40M80

FD1

FD6

CF3

CF4

CF12

CF8

FD3

1

FIDUCIAL MARK

FD5

1

FIDUCIAL MARK

CF1

1

SMDC40M80

CF13

1

SMDC40M80

CF7

1

SMDC40M80

1

FIDUCIAL MARK

CF14

1

SMDC40M80

CF10

1

SMDC40M80

CF11

1

SMDC40M80

3

FD2

FIDUCIAL MARK

CF18

1

SMDC40M80

CF6

1

SMDC40M80

CF17

1

SMDC40M80

1

FD4

CF2

1

SMDC40M80

CF15

1

SMDC40M80

CF16

1

SMDC40M80

2

H6

H2

H1

H7

C315D126

C315D126

C315D126

1

1

1

H4

C315D157

1

H23

C354D244

B B

1

H19

O106X217D67X177

1

H20

O75X213D40X177

1

H18

S315D118

1

A A

H24

C354D244

1

O106X217D67X177

O75X213D40X177

H14

S315D118

1

H3

C315D157

1

H25

1

H21

1

H9

R256X315D138

1

5

H10

C256D157

1

O75X213D40X177

C315D118

C315D126

1

H11

C256D157

1

H15

O217X106D177X67

1

H26

1

H5

1

H22

C315D118

1

O193X134D193X134N

C315D157

H16

O217X106D177X67

1

H27

C315D110

1

M3

S315D118

1

M1

C315D118

1

H13

1

H8

1

M6

C315D118

1

M9

S276D110

1

S394D138

M10

S315D244

1

H12

S315D118

1

H17

C134D134N

1

M2

1

4

M11

SMDC200M157

Spare Logic Gate

+12VALW

84

U34B

5

+

7

6

-

@LM358

10

U38C

9 8

74LVC125

Title

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

13

U38D

12 11

74LVC125

Compal Electronics, Inc.

MDC connector / Skew Hole

1

25 41Thursday, November 22, 2001

2

A

BASE ADDRESS CONFIG

XBUS RESET CONFIGU

BADDR PULL-UP

BADDR PULL-DO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

+3VALW+3VALW

E

U40C
74LVC14

10K_0402

$0_0402

LPC_RST#

1 2

R429 10K_0402
U40D
74LVC14

LPD0 <27>
LPD1 <27>
LPD2 <27>
LPD3 <27>
LPD4 <27>
LPD5 <27>
LPD6 <27>
LPD7 <27>

LPTSLCT <27>
LPTPE <27>
LPTBUSY <27>
LPTACK# <27>
LPTSLCTIN# <27>
LPTINIT# <27>
LPTERR# <27>
LPTAFD# <27>
LPTSTB# <27>

DCDA# <27>
DSRA# <27>
RXDA <27>
RTSA# <27>
TXDA <27>
CTSA# <27>
DTRA# <27>
RIA# <27>

XD0 <28>
XD1 <28>
XD2 <28>
XD3 <28>
XD4 <28>
XD5 <28>
XD6 <28>
XD7 <28>

XMEMW# <28>
XMEMR# <28>

XIOCHRDY <28>

12

+3VS

R27410K_0402

12

BOARD_ID = HIGH -------> TANGBTO
BOARD_ID = LOW --------> TANG

PD0/INDEX#

PD1/TRK0#

PD2/WP#

PD3/RDATA#

PD4/DSKCHG#

PD5/MSEN0

PD6/DRATE0

PD7/MSEN1

PNF/XRDY

SLCT/WGATE#

PE/WDATA#

ACK#/DR1#

INIT#/DIR#

ERR#/HDSEL#

STB#_WRITE#

DCD1#
DSR1#

SIN1

RTS1#/TEST

SOUT1/XCNF0

CTS1#

RI1#

IRTX

IRRX1

IRRX2_IRSL0

IRSL1

IRSL3/PWUREQ#

XWR#/XCNF1

PCIRST#<8,15,16,20,21,27,28>

52
50
48
46
45
44
43
42

35
36
37
40
41
47
49
51
53
54

55
56
57
58
59
60
61
62

70
69
68
67
66

3
2
1
100
99
98
97
96

4
5
73
71
72

+3VS

1 1

2 2

3 3

12

C505
.1UF_0402

12

C535
.1UF_0402

12

12

12

R324
10_0402

C543
5PF_0402

C511
1000PF_0402

12

C481

4.7UF_10V_0805

SUS_STAT#<16>

12

R325
@33_0402

12

C544
@15PF_0402

IRQ1<28>

IRQ11<28>
IRQ12<28>

R332

4.7K_0402

+3VS

+3VS

4 5

+3VS

1 2

R333 10K_0402

LAD0

LAD0<16>

LAD1

LAD1<16>

LAD2

LAD2<16>

12

2 7

3 6

8P4R_10K

1 8

RP11

CLK_PCI_SIO<14>

LFRAME#<16>

LDRQ#0<16>

PM_CLKRUN#<16,18,20,21>

EC_SMI#<16,28>

CLK_14M_SIO<14>

DISKCHG#<19>

HDSEL#<19>
RDATA#<19>

WRPRT#<19>

WGATE#<19>

WDATA#<19>

FDDIR#<19>

MTR0#<19>

INDEX#<19>

3MODE#<19>

XSTB0#<28>

LAD3<16>

SIRQ<16,18,21>

TRK0#<19>

STEP#<19>

DRV0#<19>

XA0<28>
XA1<28>
XA2<28>
XA3<28>

LAD3
CLK_PCI_SIO

LPC_RST#
LFRAME#
LDRQ#0

SIRQ

1 2

R342 @0_0402

CLK_14M_SIOCLK_PCI_SIO CLK_14M_SIO

1 2

+3VS

R334 @10K_0402

DISKCHG#
HDSEL#
RDATA#
WRPRT#
TRK0#
WGATE#
WDATA#
STEP#
FDDIR#
DRV0#
MTR0#
INDEX#
3MODE#

XA0
XA1
XA2
XA3
XSTB0#
XCNF2

IRQ8

XIOR#<28>

XIOW#<28>

XA12<28>
XA13<28>
XA14<28>
XA15<28>
XA16<28>
XA17<28>
XA18<28>

XIOR#
XIOW#
XA12
XA13
XA14
XA15
XA16
XA17
XA18

U33

15

LAD0

16

LAD1

17

LAD2

18

LAD3

8

LCLK

9

LRESET#

12

LFRAME#

11

LDRQ#

7

LPCPD#

6

CLKRUN#/GPIO36

10

SERIRQ

LPCSMI#

19

SMI#/GPIO35

20

CLKIN

21

DSKCHG#

22

HDSEL#

23

RDATA#

24

WP#

25

TRK0#

26

WGATE#

27

WDATA#

28

SETP#

29

DIR#

30

DR0#

31

MTR0#

32

INDEX#

33

DENSEL

34

DRATE0/IRSL2

95

XA0/GPIO20

94

XA1/GPIO21

93

XA2/GPIO22

92

XA3/GPIO23

91

XA4/GPIO24/XSTB0#

90

XA5/XSTB1#/XCNF2

87

XA6/GPIO26/PRIQA/XSTB2#

86

XA7/GPIO27/PIRQB

85

XA8/GPIO30/PIRQC

84

XA9/GPIO31/MTR1#/PIRQD

83

XA10/GPIO32/XIORD#/MDRX

82

XA11/GPIO33/XIOWR#/MDTX

81

XA12/GPIO10/JOYABTN1/RI2#

80

XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2

79

XA14/GPIO12/JOYAY/CTS2#

78

XA15/GPIO13/JOYBY/SOUT2

77

XA16/GPIO14/JOYBX/RTS2#

76

XA17/GPIO15/JOYAX/SIN2

75

XA18/GPIO16/JOYBBTN0/DSR2#

74

XA19/DCD2#/JOYABTN0/GPIO17

PC87393F

+3VS

143963

88

VDD

VDD

VDD

VDD

PC87393

XIOWR#/XCS1#/MTR1#/DRATE0

VSS

VSS

VSS

VSS

133864

89

BUSY_WAIT#/MTR1#

SLIN#_ASTRB#/STEP#

AFD#_DSTRB#/DENSEL

DTR1#_BOUT1/BADDR

XD0/GPIO00/JOYABTN1
XD1/GPIO01/JOYBBTN1

XD2/GPIO02/JOYAY
XD3/GPIO03/JOYBY
XD4/GPIO04/JOYBX

XD5/GPIO05/JOYAX
XD6/GPIO06/JOYBBTN0
XD7/GPIO07/JOYABTN0

XRD#/GPIO34/WDO#

XIORD#/GPIO37/IRSL2/DR1#

XCS0#/DR1#/XDRY/GPIO25

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTSLCTIN#
LPTINIT#
LPTERR#
LPTAFD#
LPTSTB#

DCDA#
DSRA#
RXDA
RTSA#
TXDA
CTSA#
DTRA#
RIA#

XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7

XMEMW#
XMEMR#

BOARD_ID

XIOCHRDY

9 8

7 14

5 6

C624
.01UF_0402

7 14

$ means no-pop for TANGBTO

+3VS

R565

BOARD_ID

1 2

R566

1 2

Signal Pin # Description

BADDR

61

BASE Address Selection

"0": 2E~2F (Default)
"1": 4E~4F

TEST

XCNF[2:0]

4 4

58

"0": Normal (Default)
"1": Test Mode

90, 4, 59

(default) * 1 ROM SOLUTION

2 1 0 Function
x 0 0 No BIOS
x 0 1 Normal Mode. XRDY dis abled
0 1 0 Latch Mode. XA12-19, XRDY enab led
1 1 0 Latch Mode. GPIO10~17,XRDY enab led
0 1 1 Latch Mode. XA12-19, XRDY disab led
1 1 1 Latch Mode. GPIO10~17,XRDY disab led

TXDA

XCNF0

XMEMW#

XCNF1

XCNF2

+3VS

1 2

R279 @10K_0402

1 2

R323 10K_0402

1 2

R303 @10K_0402

RATION

(DEFAULT)

DTRA#

Pin # 61

:4E
WN:2E

+3VS

1 2

R278 @10K_0402

URATION

A

Title

Size Document Number Rev

B

C

D

Date: Sheet of

Compal Electronics, Inc.

LPC Super I/O NS PC87393

ADY11 LA-1181

26 41Friday, November 16, 2001

E

2

A

from card

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

Touch Pad & Status LED Conn.

TP_CLK TP_DATA

+5VS

ACT_LED#<19>

CHARGE_LED#<29>

1 1

2 2

3 3

PS2_DATA<28>

PS2_CLK<28>

POLYSWITCH_1.1A

KBD_DATA<28>

KBD_CLK<28>

ACT_LED#

CHARGE_LED#

+3VALW

PS2_DATA
PS2_CLK

+5VS

F1

4516

KBD_DATA
KBD_CLK

AD9<16,20,21>

C/BE#2<16,20,21>

AD8<16,20,21>
AD5<16,20,21>
AD1<16,20,21>
AD2<16,20,21>
AD6<16,20,21>

JP15

1 2
3 4
5 6
7 8
9 10

13
15 16
171918

JST BM20B-SRDS-G

C96

1 2

@220PF
C97

1 2

@220PF
CP11

@8P4C_220PF

U4

1

DATA IN

2

GND

3 4

CLK IN CLK OUT

KBMF01SC6

1 2

L41

FBM-11-451616-800T

U3

1

DATA IN

2

GND

3 4

CLK IN CLK OUT

KBMF01SC6

+5VS

JP23

1 2
3 4
5 6
7 8
9 10

13
15 16
171918

@AMP 5-175638-0

121411

20

TP_CLK

TP_DATA

PWR_LED#

45

ACT_LED#

36

BATT_LED#

27

CHARGE_LED#

18

DATA OUT

KB_ASPS2KB_VCC

DATA OUT

121411

20

VCC

W=40milsW=40mils

12

C114
1UF_25V_0805

VCC

+5VS

PWR_LED#
BATT_LED#

6
5

6
5

Debug PORT

4 4

B

TP_DATA <28>TP_CLK<28>

+5VALW
PWR_LED# <29>
BATT_LED# <29>

LID_SW# <29,30>

PS2 CONN.

JP6

4
2
1

KBD/PS2_6
33005A-06T1-01-PS2

I16795326

TRDY# <16,18,20,21>
PCIRST# <8,15,16,20,21,26,28>FRAME#<16,18,20,21>
CLK_PCI_LPC <14>
C/BE#3 <16,20,21>
C/BE#1 <16,20,21>
AD7 <16,20,21>
AD3 <16,20,21>
AD0 <16,20,21>
AD4 <16,20,21>
C/BE#0 <16,20,21>

CLK_PCI_LPC

R564

@33_0402

1 2

C842

@10PF_0402

C

10
9
8
7
6

10
9
8
7
6

+5V_PRN

+5V_PRN

ACK#
BUSY
PE
SLCT

FD7
FD6
FD5
FD4

LPD[0..7]<26>

RP2

FD0

1

FD1

2

FD2

3

FD3

4

+5V_PRN

SLCTIN#
PRNINIT#
ERR#
AFD/3M#

+5V_PRN

563

5

10P8R_2.7K

RP1
1
2
3
4
5

10P8R_2.7K

AFD/3M#
ERR#
PRNINIT#
SLCTIN#

ACK#
BUSY
PE
SLCT

FD0
FD1
FD2
FD3

FD4
FD5
FD6
FD7

CP3
1 8
2 7
3 6
4 5

8P4C_270PF

CP12
1 8
2 7
3 6
4 5

8P4C_270PF

CP4
1 8
2 7
3 6
4 5

8P4C_270PF

CP13
1 8
2 7
3 6
4 5

8P4C_270PF

LPD[0..7]

D

C108

4.7UF_10V_0805

+5V_PRN

12

LPTSLCTIN#<26>

E

Parallel Port

12

C107
.1UF_0402

LPTSTB#<26>

LPTAFD#<26>

LPTERR#<26>

LPTINIT#<26>

LPTACK#<26>

LPTBUSY<26>

LPTPE<26>

LPTSLCT<26>

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

2 1

+5VS

LPTSTB#

1 2

L39 0

1 2

L7 0

1 2

L38 0

1 2

L6 0

1 2

L8 0

1 2

L37 0

1 2

L36 0

1 2

L35 0

1 2

L34 0

1 2

L9 0

1 2

L10 0

1 2

L11 0

1 2

L12 0

1 2

L1 0

1 2

L2 0

1 2

L3 0

D6

1SS355

1 2

w=10mils

R99
33_0402

AFD/3M#
FD0
ERR#
FD1
PRNINIT#
FD2
SLCTIN#
FD3

FD4
FD5
FD6
FD7
ACK#
BUSY
PE
SLCT

+5V_PRN

12

R100

2.7K_0402

PWRPRN

w=10mils

C111

1 2

47PF_0402

1

14

2

15

3

16

JP1

4

17

LPTCN-25-SUYIN

5

18

6

19

7

20

8

21

9
22
10
23
11
24
12
25
13

S/W debug only

JP3

1

bus

D22

RB751V

+

3

+

5

+

7

+

9

+

11 12

+ +

@E&T 2041-012-12

+5VALW

12

21

DCDA#<26>

TXDA<26>

RTSA#<26>

RIA#<26>

SUSP#<23,28,31,32,36>

TXDA
RTSA#

RIA#
SUSP#

2

+

4

+

6

+

8

+

10

+

R374
20K_0402

RXDADCDA#
DTRA#
DSRA#
CTSA#
RIA0

<26>

RXDA

<26>

DTRA#

<26>

DSRA#
CTSA#

<26>

+5VALW

RING# <28>PCM_RI#<21>

ACPI Debug port

A

Title

Size Document Number Rev

B

C

D

Date: Sheet of

Compal Electronics, Inc.

PIO/SIO/PS2 Port/T_P Conn. & LPC Debug Conn.

ADY11 LA-1181

27 41Monday, November 19, 2001

E

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

+5VALW

12

12

C513

C565

.1UF_0402

S

XD[0..7]

G

2

13

D

R361 10K_0402

BATT-OVP<34>

10PF_0402

.1UF_0402

R407

1 2

100K_0402

HMEMR#

HMEMW#

EC_HPOWON<7>

EN_DFAN<7>
MDC_DN#<25>

DAC_BRIG<15>

SLP_S5#<16>
SLP_S3#<16>
SLP_S1#<14,16>

LI/MH#

BATT_TEMP<33>

SCRLED#<30>

NUMLED#<30>

CAPSLED#<30>

CRT_ON#<15>

SUSP#<23,27,31,32,36> G_RST#

SMB_EC_CK1<5,15,29,33>
SMB_EC_DA1<5,15,29,33>

INVT_PWM<15>

ON/OFF<30>

12

C468

1 1

XD[0..7]<26>

XSTB0#<26>

2 2

IREF: Charger current control
ADPREF: Adapter current
control

3 3

4 4

BATT_CHGI ECAGND

10K_0402

GATEA20<16>

KBRST#<16>

XMEMR#<26>

XMEMW#<26>

1 2

C551 .01UF_0402

1 2

C555 .01UF_0402

1 2

C547 .01UF_0402

1 2

C540 .01UF_0402

+5VALW

R316

4.7K_0402

SMB_EC_DA1
SMB_EC_CK1

+3VS

R347

R314

10K_0402

1 2

1 2

2 1

2 1

A

12

R307
10K_0402

2N7002

ECAGNDVBATT

ECAGNDBATT_TEMP

ECAGNDBATT-OVP

12

D15

RB751V

D17

RB751V

G

2

Q22

13

D

S

Q23

2N7002

+5VALW

12

R313

4.7K_0402

G20

RCL#

12

C508
1000PF_0402

XA0<26>
XA1<26>
XA2<26>

XA3<26>
XD0<26>
XD1<26>
XD2<26>
XD3<26>
XD4<26>
XD5<26>
XD6<26>
XD7<26>

XA12<26>
XA13<26>
XA14<26>
XA15<26>
XA16<26>
XA17<26>
XA18<26>

+5VS

XIOCHRDY<26>

XIOR#<26>

XIOW#<26>

IRQ1<26>

IRQ11<26>
IRQ12<26>

12

IREF<34>

RING#<27>

+RTCVCC

R271

1 2

22M

X1

32.768KHZ

B

12

R292

SMB_EC_CK1
SMB_EC_DA1

12

B

C504
.1UF_0402

XA0
XA1
XA2
XA3
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
XA12
XA13
XA14
XA15
XA16
XA17
XA18

XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7

PFAIL#

51RST

12

10K_0402

R260

@0_0402

VBATT

BATT_CHGI
BATT_TEMP

R293

0

G20

RCL#

1 2

R270

C470
33PF_0402

12

C469
1000PF_0402

12

R3051K_0402

12

12

C466
1UF_25V_0805

CRY1

CRY2

12

51K_0402

166

HA0

167

HA1

168

HA2

169

HA3

170

HA4

171

HA5

172

HA6

173

HA7

174

HA8

3

HA9

4

HA10

5

HA11

6

HA12

7

HA13

8

HA14

9

HA15

10

PA3/HA16

11

PA4/HA17

12

PE0/HA18

15

HD0

16

HD1

17

HD2

18

HD3

19

HD4

20

HD5

21

HD6

22

HD7

13

HAEN

14

HIOCHRDY

158

HIOR#

159

HIOW#

157

HMEMCS#/PA0

162

HMEMRD#/PA1

163

HMEMWR#/PA2

156

IRQ1

155

IRQ8#

154

IRQ11

153

IRQ12

79

PFAIL#

164

HMR

165

HPWRON

95

DA0

96

DA1

97

DA2

98

DA3

81

PD0/AD0

82

PD1/AD1

83

PD2/AD2

84

PD3/AD3

85

PD4/AD4

86

PD5/AD5

93

PD6/AD6

94

PD7/AD7

61

PC0

62

PC1

63

PC2

64

PC3/EXINT0

65

PC4/EXINT11

68

PC5/EXINT15

71

PB0/RING#

72

PB1/SCL

73

PB2/SDA

74

PB3/TA

75

PB4/TB/EXINT10

76

PB5/GA20

77

PB6/HRSTO#

78

PB7/SWIN

28

VBAT

25

32KX1/32CLKIN

27

32KX2

PC87570C4-176PIN

161

1086723

VCC

VCC

VCC

VCC

PC87570

U29

KB_VCC

GND

GND

242666

+5VALW

NC: 1,2,43,44,45,46,87,88,89,90,131,132,133,134,175,176

GND

109

GND

91

AVCC

GND

160

12

L62
FBM-11-160808-601T

C541

1 2

.1UF_0402

80

VREF

A15/PG1/CBRD

A16/PA5/FXBUSEN

A18/PE1/SHBM#

HRMS/SEL0#

KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

PSDAT3/PC7
PSCLK3/PC6

PG4/WR1#

PG3/SEL1#

PG0/SELIO

PH0/BST0/ENV0
PH1/BST1/ENV1

PH2/BST2/TRIS

ECAGND

92

AGND

A13/BE0
A14/BE1

A17/PA6

RD/HDEN

WR0#

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9

PSDAT1
PSCLK1
PSDAT2
PSCLK2

PG2/CLK

PH3/PFS

PH4/PLI

PH5/ISE#

D8/PF0

D9/PF1
D10/PF2
D11/PF3
D12/PF4
D13/PF5
D14/PF6
D15/PF7

C

1 2

FBM-11-160808-601T

114

A0

115

A1

116

A2

117

A3

118

A4

119

A5

120

A6

121

A7

122

A8

123

A9

124

A10

125

A11

126

A12

127
128
129
130
135
136

137

D0

138

D1

139

D2

140

D3

141

D4

142

D5

143

D6

144

D7

111
112
105

36
35
34
33
32
31
30
29

56
55
54
53
52
51
50
49
48
47
42
41
40
39
38
37

57
58
59
60
69
70

113
106
107
110

104
103
102
101
100
99

145
146
147
148
149
150
151
152

C

L60

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

FRD#
FWR#
FSEL#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KBD_DATA
KBD_CLK
PS2_DATA
PS2_CLK
TP_DATA
TP_CLK

EC_THRM#

G_RST#

ACOFF
570_SMI#
EC_ON

+5VALW

12

R187
10K_0402

KBD_DATA <27>
KBD_CLK <27>
PS2_DATA <27>
PS2_CLK <27>
TP_DATA <27>
TP_CLK <27>

EC_THRM# <16>
LAN_DISABLE# <20>

SELIO# <29>

KSO17 <30>
ACOFF <34>FAN1_TACH<7>

EC_ON <30>
SCI# <16>

VTT_PWRGD# <5,14>
VR_ON <31,32>
FSTCHG <34>
MUTE <24>
SYSON <31,33>
ACIN <17,33,35>
BKOFF# <15>

FWE#

12
11
10

27
26
23
25

28
29

30
22

24
31

9
8
7
6
5

4

3
2

U16

28F040

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17

CE#
OE#
WE#

U45A

3

74HCT32

Pin 130 PU for
Zero Latch

13

D0

14

D1

15

D2

17

D3

18

D4

19

D5

20

D6

21

D7

1

VPP

32

VCC

10UF_10V_1206

16

GND

+5VALW

R410

100K_0402
14
1

2
7

PCM_SUSP# <21>

TRICKLE

570_SMI#
PCM_SUSP#
KSO17

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

KBA18

+5VALW

FWR#

1 2

PCIRST#<8,15,16,20,21,26,27>

D

1 3

D

G_RST#

D

12

+

C342

R406

1 2

2

G

100K_0402

S

Q33

2N7002

+5VALW

RP18
1 8
2 7
3 6
4 5

8P4R_10K

+5VALW

12

R188
0_0402

C341
.1UF_0402

1 2

EC_FLASH# <17>

12

R372

100K

2
1

1 2

E

+3VALW

570_SMI#

+5VBIOS

+5VS

+5VS

PS2_DATA
PS2_CLK

+3VALW

5

U31

4

V_PRST# <21,22>

7SH32

R297

@0_0402

ADB[0..7]
KBA[0..18]
KSI[0..7]
KSO[0..15]

Title

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

D18

21

RB751V

+5VALW

RP17

1 8

FRD#

2 7

SELIO#

3 6

BKOFF#

4 5

8P4R_10K

RP12

10

9
8
7
6

10P8R_10K

RP16

FSEL#

1 8

KBA18

2 7

KBA15

3 6

KBA17

4 5

8P4R_10K

ADB[0..7] <29>
KBA[0..18] <29>
KSI[0..7] <29,30>
KSO[0..15] <29>

Compal Electronics, Inc.

PC87570

E

12

R301
100K_0402

1
2
3
4
5

EC_SMI# <16,26>

KBD_DATA
KBD_CLK
TP_DATA
TP_CLK

+5VS

28 41Friday, November 16, 2001

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

2/29 01

3/06 01

ADB[0..7]
KBA[0..18]

+5VALW
+5VALW

+5VALW

+3VALW

+3VALW

6C/8C#/4C#<33,34>

THRM#<5>

FDD_PRES#<19>

LAN_PME#<20>
LID_SW#<27,30>
PCM_PME#<21>

ENABKL<15>
AIR_ADP#<33>

SELIO#<28>

KBA2
SELIO#

KBA1
SELIO#

+5VALW

2
1

U44
@7SH32

1 2

1 2

1 2

1 2

@8P4R_100K

5

R378

R384

R390

R404

C614

1 2

100K_0402
100K_0402

100K_0402

100K_0402

100K_0402

@0_0402

PCM_PME#

R380

+5VALW

14

9

10

7

RP25

@.1UF_0402

4

12

U45C

74HCT32

+5VALW +5VALW

45

DD

8

182736

R371

1 2

ADB[0..7]<28>

KBA[0..18]<28>

1 1

2 2

CC

45

B

Input Port

2 18

1A1 1Y1

4 16

1A2 1Y2

6 14

1A3 1Y3

8 12

1A4 1Y4

11 9

2A1 2Y1

13 7

2A2 2Y2

15 5

2A3 2Y3

17 3

2A4 2Y4

1

1G

19

2G

182736

RP23

@8P4R_100K

2 18
4 16
6 14

8 12
11 9
13 7
15 5
17 3

1
19

+5VALW

20

U39

VCC

GND

10

+5VALW

20

1A1 1Y1
1A2 1Y2

VCC
1A3 1Y3
1A4 1Y4
2A1 2Y1
2A2 2Y2
2A3 2Y3
2A4 2Y4

1G
2G

GND

10

C578

1 2
.1UF_0402

74HCT244

C613

1 2

@.1UF_0402

U43

@74HCT244

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

PCM_PME#

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

1 2

R387 100K_0402

C

C575

1 2

.1UF_0402

KBA3
SELIO# LARST#

+5VALW

+3V

KBA4
SELIO# LARST#

+5VALW

U45B

74HCT32

14

4
5

7

1 2

R385 20K_0402

AA
CC
BB
DD

+5VALW

U45D

74HCT32

14
12

13

7

1 8
2 7
3 6
4 5

6

1UF_25V_0805

RP24

8P4R_100K

11

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

AA

C594

1 2

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

BB

+5VALW

D

Output Port

+5VALW

20

U41

3

Q0

D0

4 5

D1 Q1

VCC

7 6

D2 Q2

8 9

D3 Q3

13 12

D4 Q4

14 15

D5 Q5

17 16

D6 Q6

18 19

D7 Q7

11

CLK

1

CLR

GND

74HCT273

10

+5VALW

20

U42

3

Q0

D0

4 5

D1 Q1

VCC

7 6

D2 Q2

8 9

D3 Q3

13 12

D4 Q4

14 15

D5 Q5

17 16

D6 Q6

18 19

D7 Q7

11

CLK

1

CLR

GND

74HCT273

10

C593

1 2

.1UF_0402

2

C612

1 2

.1UF_0402

2

PWR_LED# <27>
CHARGE_LED# <27>
SWI# <16>
LID_OUT# <16>
PWRBTN_OUT# <16>
VLBA# <16>
BATT_LED# <27>
BEEP <24>

EC_VCHRST# <15>
SOS1# <20>
SOS5# <20>
EC_WAKEUP# <16>

E

3 3

INT_KBD CONN.

KSO10

Dummy

KSO15

4 4

A

KSO[0..15]<28>

KSO14

KSO11

KSI[0..7]<28,30>

KSO13

KSO12

KSO3

KSO6

KSO8

KSO7

KSO4

KSO[0..15]
KSI[0..7]

KSO2

KSI0

KSO1

101112131415161718192021222324

KSO5

KSI3

KSI2

B

KSO0

KSI5

KSI4

KSO9

KSI6

KSI7

KSI1

12345678910111213141516171819202122232425

123456789

JP14

INT_KB_CONN.

KSI1
KSI7
KSI6
KSO9

KSI4
KSI5
KSO0
KSI2

KSI3
KSO5
KSO1
KSI0

KSO2
KSO4
KSO7
KSO8

KSO6
KSO3
KSO12
KSO13

KSO14
KSO11
KSO10
KSO15

4 5
3 6
2 7
1 8

4 5
3 6
2 7

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

CP10
8P4C_220PF

CP9

8P4C_220PF1 8

CP8

8P4C_220PF

CP7

8P4C_220PF

CP6
8P4C_220PF

CP5
8P4C_220PF

NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#

GND

+5VALW

12

R286
100K_0402

1

A0

2

A1

3

A2

4

1 2

C458 .1UF_0402

SMB_EC_CK1<5,15,28,33>
SMB_EC_DA1<5,15,28,33>

+5VALW

8
7
6
5

U28

VCC
WC
SCL
SDA

NM24C16

EC I2C Bus Address:

24C164: 1011 xxx R/W#
24C16: 101 0xxx R/W#

Title

Size Document Number Rev

C

D

Date: Sheet of

Compal Electronics, Inc.

ADY11 LA-1181

EC Extend I/O KB Conn. & BIOS

29 41Friday, November 16, 2001

E

2

A

WHEN R=0,Vbe=1

WHEN R=33K,Vbe

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

Power ON Circuit RTC Battery

+3VALW

+3VALW +3VALW

12

R388
150K

R379

12

1 1

2 2

3 3

1M_0402

VGATE<32>

12

C585
.1UF_0402

+3V

12

R373
10K_0402

147

1 2

+3VALW

14

2 3
7

VR_ON#<31>

5 6

U40A

74LVC14

1

U38A

74LVC125

4

U38B

@74LVC125

3 4

U40B
74LVC14

7 14

R377

20K_0402

1 2

13

D

2

G

S

1 2

Q28

@2N7002

R381

@0_0402

12

C117
.1UF_0402

12

1 2

LID Switch & Function Button

INT_MIC-<24>

KSI3<28,29>
KSI1<28,29>

4 4

KSO17<28>

CAPSLED#<28> NUMLED# <28>

LID_SW#<27,29>

+3VALW

A

JP12

1 2
3 4
5 6
7 8
9 10

121411
13
15 16

SUYIN 12750AR-16G2T-9

B

RSMRST# <16>

R401
10K_0402

+3VALW +3VALW

11 10

U40E
74LVC14

7 14

C570

1UF_0805_X7R

+3V

12

R386
@10K_0402

+5VS USB_BS +3VUSB_AS

W=40mils

U11

1

GND

2

IN

3

EN1#

4

EN2#

TPS2042

OC1#

OUT1
OUT2

OC2#

13 12

8
7
6
5

Note:
USB_AS=USB_BS=Trace width=40mils

INT_MIC+ <24>
KSI2 <28,29>

KSI0 <28,29>

ON/OFFBTN#

+5VS

SCRLED# <28>

B

C

BATT1

- +

RTCBATT

U40F
74LVC14

7 14

ITP_PWROK <7,16>

ICH_VGATE <7,16>

+RTCVCC

RTCPWR

12

1

D24

2

3

HSM126S

CHGRTC

EC_ON<28>

USB Over Current

12

12

R105

R106

100K_0402

100K_0402

1 2

R104 47K_0402

1 2

R107 47K_0402

C115

.1UF_0402

OVCUR#0

OVCUR#2
12

12

C116
.1UF_0402

C

OVCUR#0 <17>

OVCUR#2 <17>

D

ON/OFFBTN#

+5VALW

EC_ON

L42

1 2

FBM-11-451616-800T

USBP0-<17>
USBP0+<17>

USB0D­USB0D+

Place close to USB connector.

USB_BS USB_B

L40

1 2

FBM-11-451616-800T

USBP2-<17>
USBP2+<17>

USB2D­USB2D+

Place close to USB connector.

D

D19

3

DAN202U

12

R367

4.7K_0402

22K

2

1 2
R358
22K_0402

4516

.1UF_0402

C18 @150PF_0402

C17 @150PF_0402

4516

22K

Q31
DTC124EK

USB_AUSB_AS

W=40mils

12

+

C19

150UF_10V_E

L19

FBM-11-160808-121

USBP0-

1 2
1 2

FBM-11-160808-121

L18

1 2
1 2

W=40mils

12

C15

.1UF_0402

FBM-11-160808-121

USBP2- USB2D-

1 2

USBP2+ USB2D+

1 2

FBM-11-160808-121

C14 @150PF_0402

1 2
1 2

C13 @150PF_0402

12

D21
RLZ20A

E

.35V
=0.8V

+5VALW

1
2

12

R362
100K_0402

ON/OFF

13

12

C564
1000PF_0402

Power BTN

ON/OFF <28>
EC_ON# <36>

USB Port 0

C112

C21
1000PF_0402

1 2

USB0D­USB0D+USBP0+

JP5

1

VCC

2

D-

3

D+

4

GND

USB_CONN

USB Port 1

+

C113

150UF_10V_E

L21

L20

C20
1000PF_0402

1 2

JP4

1

VCC

2

D-

3

D+

4

GND

USB_CONN

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Power OK/Reset/RTC battery/USB Conn.& Lid Switch

ADY11 LA-1181

E

30 41Friday, November 16, 2001

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

E

2

SYSON#

1

3

Q20

@SMO5

2

G

2

G

+12VALW

12

13

D

S

+12VALW

12

13

D

S

R77
47K_0402

Q3
2N7002

R382
10K_0402

Q32
2N7002

+12VALW

12

R229
100K_0402

12

13

2

G

Q12

2N7002

12

+

R405

100K_0402

2

G

Q34

2N7002

D

1M_0402

S

C307
100UF_D_10V

+12VALW

12

13

D

1M_0402

S

R230

+3VALW

R412

8
7
6
5

12
C317

10UF_10V_A

12

SYSON#

1 1

2 2

3 3

SUSP

+5VALW to +5V Transfer

12

C418
.01UF_0402

C442

4.7UF_16V_A

+3VALW to +3V Transfer

U13

D
D
D
D

SI4800

+3V

1

S

2

S

3

S

4

G

+5VALW to +5VS Transfer

+5VALW

12

C615

.01UF_0402

C604

4.7UF_16V_A

+5VALW

U23

8

D

7

D

6

D

5

G

D

SI4800
SUSON

+5VALW +5VALW

12

12

+

12

C305
22UF_10V_1206

SUSON

U46

SI4800

8

S

D

7

S

D

6

S

D

5

G

D

RUNON

+5VALW

+5VALW

12

1

S

2

S

3

S

4

C440
33UF_D2_16V

12

1
2
3
4

12

C605

+

100UF_D_16V

+5V

C301
.1UF_0402

+5VS

12

C616

.1UF_0402

12
C441

10UF_10V_1206

12

R175
470_0402

13

D

2

G

Q7

S

2N7002

12
C617

22UF_10V_1206

12

SYSON#

C439
.1UF_0402

12

13

D

S

12

13

D

S

R413
470_0402

Q35

2

G

2N7002

R227
470_0402

2

G

Q11
2N7002

SUSP

SYSON#

R368
@100K_0402

VR_ON#

Q27

@2N7002

+CPU_CORE

12

13

D

2

G

S

R140
@330

Q24

@2N7002

+VTT

12

13

D

2

G

S

+3VALW

VR_ON

1 2

13

D

2

G

S

VR_ON#<30>

VR_ON<28,32>

1.8VALW/+1.5VS Power direct prov ide

+1.8VS+1.8VALW

U8

8

D

7

D

6

D

5

D

12

C40
10UF_6.3V_A

SI4800

S
S
S
G

+1.8VALW to +1.8VS Transfer

1
2

12

3
4

C43

22UF_10V_1206

RUNON

12

C42

.1UF_0402

D

S

12

R39
470_0402

13

Q8
2N7002

2

G

SUSP

R179
@330

Q29

@2N7002

SYSON<28,33>

SUSP<23>

SUSP#<23,27,28,32,36>

+3VALW +3VS

U14

SI4800

8

D

7

D

6

D

4 4

12

C325

+

100UF_D_10V

5

D

12

C315
10UF_10V_A

A

+3VALW to +3VS Transfer

1

S

2

S
S
G

12

3
4

22UF_10V_1206

RUNON

C336

12

C421

.1UF_0402

D

S

12

R189
470_0402

13

Q9
2N7002

2

G

B

SUSP

Title

Size Document Number Rev

C

D

Date: Sheet of

Compal Electronics, Inc.

DC/DC Circuit

ADY11 LA-1181

31 41Friday, November 16, 2001

E

2

A

PC149

PC148

PR230

@10K

PC156

1 2

PR207

316K_1%

4700PF

PR188
1M

+5VALWP

12

PR186
@10K

PR208
180K_1%

1 2

PR189
1M

PC150
4700PF

1 2

1 2

PR184
0

PR185

1 2

0

2VREF

PR195 10

PR191

PR190

1M

1M

KC-FBM-L11-322513-201LMAT

1 2

PC151
4700PF

PR182

0

PR183

0

1 2

1 2

51K
PR225

PC157

4.7UF_0805_10V

PC140
1U

B+

PR181

1 2

PC165
470PF_0603

2VREF

PR218

24.9K

PR219

27.4K

+5VALWP

+3VALWP

1 1

PR187
1M

1 2

PC147

4700PF

4700PF

CPU_VID4<6>
CPU_VID3<6>

CPU_VID2<6>
CPU_VID1<6>
CPU_VID0<6>

2 2

VGATE<30>

VR_ON<28,31>

12

3 3

4.7UF_1206_16V

PU3

15

VCC

18
17
10

3
6
2
7

16

SKIP
V+
PGOOD
SHDN
ILIM
N/C
REF
TON

MAX1714A

SB+

VTT_PWRGD<5>

SUSP#<23,27,28,31,36>

4 4

PR209
150K_1%

1 2

PR201

12

14.3K_1%

VTTVILIM

PC128

0.22UF_0805_16V

A

VTTVREF

VDD

PGND

14

VTTBST

19

BST

1

DH

20

LX

13

DL

12
11

N/C

9

N/C

5

OUT

48

FBAGND

PL18

PC164

4.7UF_1210_25V

1 2

0

21
22
23
24
25
14

12

3
2

17

6
20
11
12
15 10

21

PD32
1SS355

12

PR244

0

1 2

PR242 0

VTTVLX
VTTVDL

PC137
150PF

B

4.7UF_1210_25V

PR196

0

PU6 MAX1718

D4
D3
D2
D1
D0
VGATE
TIME
SDN/SKIP
VDD
CC

ZMODE
OVP
REF
ILIM
GND TON

PC155

4.7UF_1206_16V

PC141
1UF_0805_25V

B

PC163

LX

DH

BST

DL
V+

VCC

FB
POS
NEG

SUS

S1

S0

PC1290.1UF_0805

4.7UF_1210_25V

27
28
26
16
1
9
4
13
5
19
18
8
7

SI3456DV

PQ42

SI4810DY

VTTVFB

PC161

PQ43

3

4.7UF_1210_25V

1 2
1 2
1 2

0
PR246

PR243
0

2

1

G

4 5

578

3 6

241

PC160

+5VALWP

PR217
20

1 2

PR1930
PR1920

PR245

1 2

@0

0.1UF_0805_25V

6

D

S

PC162

4.7UF_1210_25V

21

PD33
1SS355

B++

PC132

0.1UF_0805

PC154

4.7UF_0805_10V

PC134

C

PC169

PC131

0.1UF_0805

PC167
@.01U/16V

578

PC153

4.7UF_1210_25V

PL16

4.7UH-SPC-1205P-4R7A

+

PC144
220UF_D_4V

C

B++

12

PC170

2200PF

578

0.1UF_0805_25V

PQ35

IR7811A

VTTLX

PQ37
SI4362DY

3 6

241

B+SB+

PL19
KC-FBM-L11-322513-201LMAT
PC152

4.7UF_1210_25V

+VTTP

PR220
3K_1%

PR206
12K_1%

3 6

241

578

3 6

241

PR226
604K_1%

1 2

PC127

0.01UF

1 2

PR247 @0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D

E

CPU-CORE/VTT

578

PQ36

PQ38
SI4362DY

578

PM_DPRSLPVR <16>

PR211

PR210

16.2K_1%

19.6K_1%
1 2

1 2

PC130

0.1UF_0805_25V

3 6

241

3 6

241

1000PF_0603

PR227

1 2

NC_TEST4

IR7811A

PQ39
SI4362DY

PC136

61.9K_1%

PL17

CEP125-0R8NC-U

PD35
EC31QS04

2 1

1 2

PR236 @0

1 2

PR197 0

12

PR237
@0

PU10

1

NO2
NO3

COM
NO1
INH

ADDA

GND ADDB

V+

NO0

2
3
4
5 6

MAX4524

H_DPSLP#<5,16>

PM_GMUXSEL<6,16>

D

NC_TEST3

12

12

220UF_D_4V

PC145

+

+PC146

220UF_D_4V

+5VALWP

PR229 3mR

PR228 3mR

PC133

1 2

PR232 0
12

PR212
1K_1%

0.1UF_0805

PR216 1K_1%

1

MAX4322

5

PU7

3

+

4

-

2

12

+3VALWP

D3

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

D1

0

0

0

0

1

0

0

1

1

0

0

1

1

1

1

1

0

0

0

0

1

0

0

1

0

1

0

1

1

1

1

1 0.600

E

10
9
8
7

PR203

12

10K

PC171

0.1UF_0805_25V

1 2

13

PQ31

2SC2411K

PR202

2

10K

1 2

Compal Electronics, Ltd.

Title

CPU VCORE

Size Document Number Rev

ADY11 LA-1181

Date: Sheet of

PR214 510_1%

PR215 604_1%

D0D2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OUTPUT

D4 = 1

0.975

0.950

0.925

0.900

0.875

0.850

0.825

0.800

0.775

0.750

0.725

0.700

0.675

0.650

0.625

32 41Friday, November 16, 2001

+CPU_CORE

12
12

VOLTS

D4 = 0

1.75

1.70

1.65

1.60

1.55

1.50

1.45

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.05

1.00

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

+5VALWP

12

PR29
100K_0402

13

100K

12

PQ11
DTC115EUA

ADPIN
FBM-L11-453215-900LMAT

12

PD31

ADPGND

1 1

2 2

AIR_ADP

<34>

PCN1
RP34-8RD-3PDL2J

VIN

1

GND

AIR_ADP

456

PCN3
@2DC-S107B200

1

2

7

1

2

3

2

ADPIN

ADPGND

PC28
100PF

100K

2

PC29
1000PF

12

AIR_ADP# <29>

PL2

1 2

PC25
100PF

@EC10QS04

PL3

1 2

FBM-L11-453215-900LMAT

PCN2 battery connector pin assignm ent

SMART Battery:

1.BAT+

2.LI/MH#

3.B/I

4.TS

5.SMB_EC_DA1

6.SMB_EC_CK1

7.GND

3 3

Vin Detector

17.93V/17.2V

VIN

12

PR157

84.5K_1%

12

PC107
1000PF

4 4

A

PR158
20K_1%

12

PR159
22K

1 2

12

0.1UF_16V

PC108

PU12A

LM393A

3
2

PR161
10K

12

PC26
1000PF

PR160
1M_1%

1 2

84

+

-

12

B

12

12

1

RTCVREF

B

PC109

0.01UF

C

D

E

Detector

+5VALWP

PR34
1K

1 2

PR35

1 2

6.49K_1%

PR37
100

1 2

7

12

PC31
1000PF

PR1
100K

PR3

@1K_1%

BATT_TEMP

PD8

@BAS40-04

PU12B

LM393A

PR2
1K_1%

1

PD7

@BAS40-04

2

3

1

2

3

+5VALWP

PR45
1M_1%

12

5

+

6

-

12

PR50
10K

PC32

0.1UF_16V
1 2

RTCVREF

PQ12

2N7002

Title

Size Document Number Rev

Date: Sheet of

6C/8C#/4C# <29,34>

12

PR48
215K_1%

13

2

PQ13

DTC115EUA

Compal Electronics, Inc.

ADY11 LA-1181

BATT_TEMP <28>

SMB_EC_DA1 <5,15,28,29>

B+

12

PR46
499K_1%

12

PR49
499K_1%

PR54
47K

13

100K

100K

Detector

E

+5VALWP

12

PC111
1000PF

PACIN

12

SYSON

2

PACIN <34>

SYSON <28,31>

2

33 41Friday, November 16, 2001

BATT+

BATT+

PR163
10k

SMB_EC_CK1<5,15,28,29>

12

PC23
470PF_0805_25V

VIN

12

PR170
10_1206

12

PZD6

RLZ24B

VINVS

12

PR162
10K

1 2

12

12

PZD5

PR164

RLZ5.1B

10K

PJP11

4MM

PL4

1 2

FBM-L11-453215-900LMAT

@BAS40-04

ACIN <17,28,35>

PACIN <34>

C

21

12

1

PD9

2

BATT++

PC24
470PF_0805_25V

PJP4

4MM

2 1

PCN2
BTC-07GR4 7P

1
2
3
4
5
6
7

PR43 100

3

+5VP

SHDN#<35>

ACON<34>

BATT++

PF1

@7A

PR36
1K

1 2

12

+5VALWP

PR44
100K

1 2

PD10

RB751V

12

PD11

RB751V

12

Precharge detector

15.9V/13.2V FOR
ADAPTOR

D

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

4

PR131
47K

1 2

1
2
36

2

G

PR132

47K

P2

1
2
3 6

12

PR60
200K_0402

12

PR63
150K_0402

13

D

PQ19

S

2N7002

19.6K_1%

1 2

IREF<28>

PR65

12

PQ15

SI4835DY

4

2

G

PC101
1000PF

8
7

5

10K_1%

1 2

PQ30

13

D

2N7002

S

PQ14

VIN

1 1

ACOFF#

PACIN<33>

ACON<33>

AIR_ADP<33>

2 2

8
7

5

PD12

1SS355

1 2

PR67

47K_0402

1 2

ACON

SI4835DY

IREF=1 .746*Icharge
IREF=0~5V

P3

PR70

12

0.1UF_16V

1 2

PR75

100K_1%

40.2K_1%

PR68

22.6K_1%

PC45

12

PR78

B

Iadp=0~3.07A
Iair=0~2.26A

PR59

0.02_2010_1%

PC117

.01UF_0402_16V

12

12

PR72
@30.1K_1%

PC118

.01UF_0402_16V

12

C

D

E

Charger

B+

12

12

PR66
100K

12

1 2

1 2

PC43

PR69

4700PF

10K

1 2

1 2

PC46

PR71

2200PF

1K

12

PR76
10K

12

PL9

1 2

FBM-L11-322513-151LMAT

PU5
MB3878

1

-INC2

+INC2

2

OUTC2

GND

3

+INE2

CS

4

-INE2

VCC(o)

5

FB2

OUT

6

VREF

VH

7

FB1

VCC

8

-INE1

RT

9

+INE1

-INE3

10

OUTC1

FB3

11

OUTD

CTL

12

-INC1

+INC1

24

23

22

21

20

PC44

0.1UF_16V

19

1 2

18

17

1 2

PR73

66.5K_1%

16

15

1 2

PR77
330K

14

13

1 2

PC112
10PF

4.7UF_1210_25V

12

PR64
0

PC47

0.1UF_0805_25V

1 2

1 2

PC49
1500PF

PC36

PC41

2200PF

1 2

1 2

PC42

0.1UF_0805_25V

12

4.7UF_1210_25V

12

PD13
1SS355

1 2

12

PR79
10K

PC37

FSTCHG <28>

RB051L-40

PD30

36

578

B+++

241

12

PC39

0.1UF_0805_25V

12

PQ17
FDS4435

LXCHRG

1 2

PC40
2200PF

ACOFF#

PL5
SLF12565T-220M

PQ16

SI4835DY
1
2
3 6

4

1 2

PR169

10K

1 2
13

100K

100K

PQ18
DTC115EUA

PR74

0.02_2512_1%

1 2

PR61

47K

2

8
7

5

VIN

ACOFF <28>

BATT+

BATT+

12

12

PC50

PC51

4.7UF_1210_25V

12

4.7UF_1210_25V

+

PC48

68UF_EC_25V

3 3

BATT-OVP<28>

12

12

PC115

4 4

@0.1UF_16V

PR174

2.2K

OVP voltage :

LI-4S :18.0V----BATT-OVP =3.97V

LI-3S :13.5V----BATT-OVP =2.98V

BATT-OVP=0.2 206*BATT++

A

7

PU2B

LM358

12

PR80

2

13

152K_0.1%

13

100K

100K

PR5

100K

DTC115EK

2

PR4

305K_0.1%PQ9

+5VP

PQ10

6C/8C#/4C# <29,33>

C

BATT++

12

PR177

205K_1%

12

PR175

300K_0.5%

5

+

6

-

12

PR176

143K_0.5%

B

PC116

0.01UF

2N7002

PC173

0.1UF

PR81
309K_0.1%

1 2

PC113
22PF

12

Charge voltage

4S LI-ION

NI-MH : 17.00V

3S LI- ION : 12.75V

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

ADY11 LA-1181

Charger

E

34 41Wednesday, November 21, 2001

2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I

NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE

INFORMATION CONTAINS MAY BE

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF

COMPAL ELECTRONICS,INC.

B

C

D

E

+3.3V/+5V/+12V

B+

1 1

+3.3V Ipeak = 6.6 6A ~ 10A

2 2

3 3

4 4

PC103
1000PF

PL12

FBM-L11-322513-151LMAT

1 2

12

PC64

0.1UF_0805_25V

+3VALWP

PC82

150UF_D_6.3V_FP

VL

PR150

2.15K_1%

12

12

+

PH1

10K_1%_0805

A

B++++

12

2200PF

PC65

0.012_2512_1%

12

+

PC83

150UF_D_6.3V_FP

PR152

16.9K_1%

PC104

12

PC66

4.7UF_1210_25V

PL7

SLF12565T-100M

PR100

PD22

EP10QY03

NC_TEST2

1UF_0805_25V

PR154

PC67

4.7UF_1210_25V

12

1M_0402

2 1

PR238
@0

84

5

+

6

-

PR153
100K_1%

100K_1%

12

PR178

47PF_0402

12

PC119

1 2

PR135

3.57K_1%

PR134

1 2

PR155

47K_1%

PU4B

LM393A

7

VL

PC63

0.1UF_0805_25V
1 2

578

PQ21
SI4800DY

DH31

3 6

241

578

PQ23
SI4810DY

12

PC79
@1000PF

3 6

241

ACIN<17,28,33>

12

PC120
100PF_0402

1 2

PC121
@.01UF_0402

12

10K_0402

1 2

1 2

LX3

DL3

CSH3

PR22
0_0402

1 2

PR240
10K_0402

@300K_0402

VS

12

12

BST31

DH3

PR241

PR156
47K_0402

PC106

0.047UF_16V

12

PR97
0_0402

PC78

12

CPU thermal protection at 85 degree C
Recovery at 45 degree C

B

12

0.1UF_0805_25V

25

BST3

27

DH3

26

LX3

24

DL3

1

CSH3

2

CSL3

3

FB3

10

SKIP#

23

SHDN#

7

TIME/ON5

28

RUN/ON3

12

PC172
680PF_0402

PR106

47K_0402_1%

12

PC89

0.047UF_16V

PR98

10_1206

VS

12

VL

12

22

V+

PU9

MAX1632

DAP202U

PD20

2

21

12OUT

VL

PGND

GND

8

VL

VL

SHDN# <33>

3

1

12

PC69

VDD

BST5

DH5

LX5
DL5

CSH5

CSL5

FB5

SEQ

REF

SYNC

RST#

1 2

PR103

PC70

1 2

4.7UF_1206_10V

4
5
18
16
17
19
20
14
13
12
15
9
6
11

0_0402

C

0.1UF_16V

PC75

4.7UF_1210_25V

BST51

+12VALWP

12

12

1 2

PR104
@0_0402

1 2

PD24
@RB751V

PC76

0.1UF_0805_25V

2.5VREF

12

PC81

4.7UF_1206_10V

+5VALWP

0.1UF_0805_25V

PR99
0_0402

1 2

12

PR105
@100K_0402

PC68

1 2

POK

CSL5

PR137

10.2K_0402_1%

12

PR239

@0

PC71

2200PF

1 2

PR23
0_0402

12

12

10K_0402_1%
PR136

NC_TEST1

12

PC72

DL5

D

12

PC73

4.7UF_1210_25V

0.1UF_0805_25V

DH51

PC80
@1000PF

12

PC123

100PF_0402

12

PC124

@100PF_0402

PC61

470PF_0805_100V

B++++

12

PC60

4.7UF_1210_25V

1 2

12

PD19

1 2

PC74

4.7UF_1210_25V

PQ24

SI4810DY

12

PR96
22_1206

PQ22
SI4800DY

578

3 6

578

3 6

PD23
EP10QY03

12

241

241

FLYBACKSNB

4

1

SDT-1205P-100

12

PC122
47PF_0402

12

PR179
2M_0402

2 1

EC11FS2

PT1

12

+

2

3

CSH5

12

12

+

PC86

150UF_D_6.3V_FP

PR101

0.012_2512_1%

PC87

+5V Ipeak = 6. 66A ~ 10A

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

+3.3V/+5V/+12V

ADY11 LA-1181

E

+5VALWP

150UF_D_6.3V_FP

2

35 41Friday, November 16, 2001

A

B

C

D

E

+1.8VALW/+1.5VS

+1.8V+-5%

13

DTC115EK

100K

+1.5VS+-5%

12

+

PR200

200K_1%

PQ26

100K

2

PJP5

4MM

PJP6

3MM

PJP7

3MM

PJP8

3MM

PJP10

3MM

+1.5VSP

PC139
150UF_D_6.3V_KO

2.5VREF

12

+5VALWP

PR198

1 2
13

DTC115EK

100K

100K

21

21

21

21

21

100K

PQ33

2

+VTT

+1.5VS

+5VALW+5VALWP

+3VALW

+12VALW

+1.8VALW

2.5VREF <35>

SUSP# <23,27,28,31,32>

6
2

1

12

PR20

1.5K_1206

PQ40

SI3442DV

D

G

S

45

3

PU2A

LM358

1

PC166

68PF

B+

VS

12

1 2

0.1UF_16V

PC135

84

3

+

2

-

PR224

5.1K

1 2

PR223

5.1K

0

PR194

1 2

PC143

0.01UF

PC125

+VTTP

+1.5VSP

+3VALWP

+12VALWP

+1.8VALWP

220PF

1 2

PR221

300K_0.5%

PC56

+1.8VALWP

12

PR85

1.5K_1206

+1.8VALWP

PC158

4.7UF_1206_25V

12

PR126

1.5K_1206

12

12

PR204

+

2.5VREF

+5VP

12

PC138
150UF_D_6.3V_KO

VS1

12

PR84

1.5K_1206

PZD3
RLZ5.1B

CHGRTC

10K

12

PR235
@10K

12

12

12

PR205
10K

PR173
200_1206

PR83
200_1206

12

4 5

LM393A

PC54

3

PQ41

SI3445DV

D

S

6
2

1

G

3

VL

PU4A

84

+

1

-

PC126

0.01UF

PQ20
TP0610T

13

2

0.22UF_1206_25V

RTCVREF

12

PC59

4.7UF_1206_25V

LX18

12

PC168

3
2

VS

12

1 2

+5VALWP

1 1

12

PD37

PC159

4.7UF_1206_25V

2 2

3 3

4 4

RB751V

PQ32
2SA1036K

BATT+

CHGRTCP

PZD4
RLZ16B

PC142
2200PF

VIN

PR89
200_0805

1 2

12

3
1

12

EC_ON#<30>

12

PR213
1K

1 2

2

PD15

RLS4148

PD17
RLS4148

12

PQ25

2SC2411K

2

12

12

12

PZD2
RLZ4.3B

1 2

PR94
22K

2

PC58
1UF_0805_25V

1
3

PR91
100K

PU8
S-81233SG

IN

1 2

1 2

12

OUT

GND

1

5UH_SPC_06704-5R0A

12

PD36

0.1UF_16V

12

PD16
RLS4148

PR90
10K

1 2

PC55

0.1UF_0805_25V

PR95
200

PL14

RB051L-40

12

12

PR199
100K_1%

12

12

PR222

38.3K_1%

PR92
150K

0.1UF_16V

PR21
200

1 2

Title

Size Document Number Rev

A

B

C

D

Date: Sheet of

Compal Electronics, Inc.

ADY11 LA-1181

+1.8VALW

E

36 41Tuesday, November 20, 2001

2

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 2

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

Core-logic Chipset r evision Revision er ror 0.1B 3 FW82830M should be QB88 and FW8280 1CAM should

1

D D

2 Leakage is sue +5VSHDD is on when plug AC-in and OS en ter S3,S4,S5.

3 Leakage is sue +5VS has about 500mv backdrive on S3;U2 6 is +5VS but

4 Leakage is sue +3VS has about 253mv backdrive on S3;Q 16 is on when

5 Leakage is sue +3VS has about 253mv backdrive on S3;U37 pinU5

6 SM_CLK/DATA read and progr am failed Correct net,U9 pin29 should be connec t to SMB_DATA

we used GPIO25 of ICH3-M to control IDE power,but this
pin is resume plane, keep high af ter RSMRST#.

pin9 pull up to +3V

S3

(ICH_THRM#)is +3VS plane

7 Level shi ft U26 is +5V output,but ICH3(U37 )pinAA 6 is 3V level Change R415 from 100_0402 to 5.6K_04 02;BOM change7
8 Correct Part v aule BOM and schematic vaule d ifferent Change JP20 vaule from"HH9927-S6" t o"HH9921-S6"

9 None Original design, EC_FLASH control by IC H3-M GPIO40 or

10 VR_ON cont rol For EC can control VR_ON after VT T_PWRGD# on 29 VTT_PWRGD# connect to U2 9 pin146

C C

11 Debug ca rd Design change,used PCI port 80 debug card solution 28 Change JP23 connector type from "SUYI N 12793-10G2"

12 None 7 Change Q4 from "2SC2411EK" to "FMMT619"

13 Component pad size Component is 0402 size,but layout pad size is 0603 0.1C 17 Layout modified and correct vaule from"5PF" to

97338 pin 71. Follow compal common desi gn, use ICH3-M
GPIO40 control EC_F LASH#.

Max. power of FMMT619 is 0.615W.

0.1B 19 Q14 pin3 change from +5VALW to +5V S power plan

0.1B

0.1B

0.1B

0.1B

0.1B

0.1B

0.1B

0.1B

0.1B

14 Mechanical limit issue Mechanical limit H:2.2mm,used compone nt over limit 320.1C Change C440 from "100UF_D_16V" to " 33UF_D2_16V"

15 Delect item 11 PT implement PCI port 80 solution 0.1C 28 SST2 don't ch ange

*

16 Clock wavef orm Clock waveform ove r SPEC

1.CLK_HCLK/H CLK#

2.CLK_DR EF

3.CLK_ICHA PIC

0.1C 14 1.Change R16,R12 from"33_1%" to"10_1%"

be QB6 3

7 R94 pull up change t o +3VS

12 R268 pull up change t o +3VS

16 ICH_THRM# pull up change to +3VS

14Signal connect e rror

U9 pin30 should be connect t o SMB_CLK

19

Change JP10 vaule from"JM361 13-L1H" to

20

"JM36113-L5 H7"

27 Change U33(97338) pin7 1 to NC

to "AMP 5-175638-0";BOM change

BOM chan ge

"5PF_0402";BOM needn't change

D2 size H=1.9mm; BOM change

2.Change R59 from"22_0402" to "10_0402"

3.Pop R352 (10_0402) and pop

16

C559(10PF_04 02)
17 None LPC debug card on developer stage , depop it. 0.1C 28 Depop JP23 (S ST2) 0.2 SST-2
18 Correct Part v aule BOM and schematic vaule d ifferent 0.1D 24 Change R383 vaule from "29K_1%" to "28.7K_1%" 0.1 SST
19 Fixed EE issue list item11( 2001/6/5) Intel recommend series resistor on IDERST 0.1D 17 Add R453(0_0402) series resistor on PIDERST #--- BOM modify 0.2 SST-2

B B

20 Fixed EE issue list item10( 2001/6/5) VCCA_DAC should have a 0.1uf and 0 .01uf nearby 0.1D 10,1 1 We check layout file,C290 closely U7 pin AF26,so change

21 Fixed EE issue list item26,27( 2001/7/12) 1.Change CPU thermal skew hole s ize change.

22 CLK_HCLK/HCLK# resistor need n't change 0.1E 14 R12,R16 resistor to restore,de l item16-1 0.1 SST

2.CD-ROM skew hole size change.
Follow Dell's reco mmend*

0.1D 1.Change H1,H2,H6,H7 from 2.8m m to 3.2mm

23 ICH3 revis ion SST2 used QB62 or SL5LF revision 0.1E 17 Change R376 from"22.6_1%" to "18.2_1% ",BOM already

24 CLK EMI is sue Add AC termination on as belo w signals

1.CLK_GB IN

2.CLK_ICHH UB

3.CLK_ICH 48

4.CLK_PCI_S IO

5.CLK_GBO UT

6.CLK_ICHP CI

0.1F 0.2 SST-2

C290 from pag11 to pag10, C156 and C 186 change to

page 11(not change layout),and add C632 [0.01UF_0402]

near AF 26

26

2.Change H9 from 3.5mm long by 3.0mm wide

change O K.

8 1.Pop R168(33_0402) and C297( 5PF_0402)
16 2.Pop R306(33_0402) and C514( 5PF_0402)

3.Pop R369(10_0402) and C574( 5PF_0402)
27 4.Pop R324(10_0402) and C543( 5PF_0402)
14 5.Pop R69(33_0402) and C92(1 0PF_0402)
16 6.Pop R311(10_0402) and C518( 15PF_0402)

25 Gerber rele ase Change Schematic revisio n to 0.20.2None SST-20.2

A A

0.1 SST

0.2

0.2

0.2

0.2

0.2

0.1

0.1

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

SST-2

SST-2

SST-2

SST-2

SST-2

SST
SST

SST-2

SST-2
SST-2

SST-20.1BFAN power transistor change. Max. power of 2 SC2411 is 0.2W.

SST-2

SST-2

SST-2
SST-2

0.2 SST-2

0.2 SST-2

0.2 SST-2

Compal Electronics, Inc.

Title

P.I.R History

Size Document Number Rev

ADY11 LA-1181

5

4

3

2

Date: Sheet of

37 41Friday, November 16, 2001

1

2

5

4

3

2

1

Version change list (P.I.R. List) Page 2 of 2

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

26 None Connector cha nge 0.2A FDD Connector change to ACES 85201-2605 0.3 PT19

D D

27 None Remove OZ6933 PCMCIA Co ntroller 210.2A 1. Del Page 21, and shift down page

0.2A

30 None Remove Serial Port 0.2A 27 De-pop C1, C5, C10, C11, C109, U1, JP3, CP1, CP2, L26,

31 None Lid Switch function change to Touc h-pad Board 0.2A 27 Schematic change, JP15 Pin17 net to +3VS, JP15 Pin18 net

33 None Power on switch board change connector 0.2A 30 Power On switch board change from AM P 4-175638 to

34 None ICH_VGATE de lay 0.2A 30 0.3 PT1. Schematic change, connect R381 pin2 to U40 Pin12

35 None Schematic remove Serial PORT function 0.2A 27 Schematic remove U1, CP1, CP2, C1, C5, C 10, C11, C109,

C C

36 CMOSREF not strong enough t o provide

the target 2/3 ratio devider

37

None 0.2A 0.3 PTM/B ID change t o PT 17 BOM add R441 10K_0402, Depop R4 43 10K_0402
None 0.3 Gerber release, schematic cha nge to 0.3 0.3 PT38

39 PT0.31. BOM depop C126, C120, C293, C210, C283, C118.0.3Cost do wn

Change divider to 0.5K/1K at the ne xt available
opportunity to gain more CMOSR EF margin.

Gerber rele ase
Core_VCC and VTT capacitor reduce.

0.2A 5 BOM change R20 from 1K_1% to 499_1%, R22 from 2K_1% to

40 None Remove Capaci tor 0.3B 6 Schematic remove C120.

25

2. Del CF5, CF9

1. Schematic remove U20, C437, C403, C402 , C436, C434,

C433, C415, C408, C429, R219, R211, C79, C 80, C430, C318,
L53, C358, C343, C401

2. Change PCMCIA Socket vaule to FOXCO NN 1CA415M1-TA

and R566 0_0 402

L27, L28, L29, L30, L31, L32, L33, Q26.

to LID_S W#

AMP 5-17563 8-0

SUYIN 12750AR-16 G2T-9

2. De-pop R386, R381

L26, L27, L28, L29, L30, L31, L32 , L33, Q26.

1K_1%

6

2. BOM change from 150UF_D2_6.3V (45mOhm) to

220U_D2_4V(25mOhm), Location C29, C39, C3 2, C292, C260,
C119, C153, C289, C37.

11 3. BOM depop C122, C127.

4. BOM change from 150UF_D2_6.3V (45mOhm) to

220U_D2_4V(25mOhm), Location C27, C23, C303.

41 None Resister Package e rror. 0.3B 24 Change R351 100K_0603 to R351 100K_0402
42 Suspend from lid switch, ca n't resume

from open L CD.

43 For thermal module difference Mosaic-P4 Add stand-off on mother board. 0.3C 6

None Change Capacitor spec. 0.3C 31 BOM change C307, C325, C605 from 10 0UF_D_16V to

B B

44

CRT connector layout shift. Shift CRT connector 1.33mm 0.3C

45

Factory DXF fix. Layout modi fy. 0.3C

46

Test point rev iew. Layout modi fy. 0.3C ST1.0

47

3COM 3C920 referance RJMA G version

48

update .

49 Poor quality w/static noise on

recording func tion.

51 None Change Back-light gate pow er plan. 1.0 15 1. U12 power plan from +3VS to +5VS.

Change Lid switch power plan from +3 VS to +3VALW. 0.3C 27

1. Schematic JP15 Pin.17 t o +3VALW

2. Schematic JP12 Pin.15 t o +3VALW

29

3. Schematic R404 Pin.1 t o +3VALW

30

Schematic remove C39, add M11 S MDC200M157,
BOM add C283 220U_ 4V_D2.

100UF_D_10 V.

VDDPCI[1:5] pins from +3VASB to +3VS. 0.3C 20 1. Schematic modify, U21 some pin change p ower plan from

Change MIC-AMP power plan. 0.3C 24 ST

+3VASB to +3VS ( VDDPCI [1:5] )

2. Schematic C370, C371, C373 change po wer plan from

+3VASB to +3 VS.

1. Schematic modify, MIC-AMP change power plan from VDDA

to AVDD_MIC with R567 49.9Ohm to AVDD_AC97

2. Schematic add C633 10UF_ 10V_1206

2. U12 from SH08 t o ST08

0.3 PT

0.3 PT0.2A28 None 22Remove Power Switch (2 slot) and change Ca rdBus Connector

0.3 PT29 None Add Board_ID for check Mosaic and Tang 26 Add U33 Pin71 for BOARD_ID, and Add Resiste r R565 10K_0402

0.3 PT

0.3 PT

0.3 PT

0.3 PT

0.3 PT

1.0

1.0

1.0 ST

1.0 ST

1.0 ST

1.0

1.0

1.0 ST

1.0

1.050 None M/B ID change t o ST 0.3D 17

PT0.3None32 0.2A 27Debug Port change con nector Debug Port change connector from SUYIN 12793A-10G2 to

ST
ST

ST
ST

STBOM depop R441, R444, add R442, R4 43 10K_0402

A A

Compal Electronics, Inc.

Title

P.I.R History

Size Document Number Rev

ADY11 LA-1181

5

4

3

2

Date: Sheet of

38 41Friday, November 16, 2001

1

2

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 3

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1

D D

C C

CPU_CORE voltage is unstable

+5VALWP is unstable

2

3

mechanical (switch board)
The time sequency of +1.5VS is error Change REF voltage from 2VREF of MAX1718 to

4

The time sequency between 1.8VALWP

5

and 3.3VALWP is error
RTC battery that will be shortage.We

6

changed RTC battery from Panasonic
VL1220 to Maxell ML1220

7

Correct curreent limited value Modify current limited from 2.86A to 3.22A 0.1E 35 0.1 SST1. Change PR68 from 24.9K_1% to 21K_1%

8

Change PWM frequency from 300KHZ to 200KHz 0.1B 33

Change PWM frequency from 200KHz to 300KHz 36 1.Delete PR104 and add PR103 0_0402

Change PC48 to small size,the height limited is 6mm in
this area

2.5VREF of MAX1632

0.1B

0.1B

0.1B

Change LDO charger to 3.3V for Maxell ML1220
Modify Vin Detector and Precharger Detector circuit

BOM and schematic vaule differentCorrect part vaule 0.1D 37 Change PL14 vaule from"5UH_SPC_06703" to

1.Change PR197 from 100 to 0

2.Connect pin10 of PU6 to pin9 of PU6

2.Connect pin15 of PU9 to ground

35Output capacitor of Charger interfere

Change PC48 from 100UF to 68UF

37

.Change PR200 from 100K_1% to 200K_1%

Add PC172 680PF connected to pin7 of PU936Delay 3.3VALWP start-up time 0.1B

Change PU8 from S-81235SG to S-81233SG0.1B 37 0.2 SST2

34 1.Change PR157 from 78.7K_1% to 84.5K_1%

2.Change PR48 from 249K_1% to 215K_1%

"5UH_SPC_06704-5R0A"

2. Change PR65 from 14.3K_1% to 15.8K_1%

0.1 SST

0.1

0.2

0.2

0.2

SST

SST2

SST2

SST2

0.1 SST

9

Add ferrite bead for EMI

10

B B

11

Plug in AC adapter and battery on

12

time the system can't turn on.

Safety protection for RTC battery Add PR21 to prevent damging PR95 to damage RTC

13

Design margin is not enough increase design margin for battery OVP prevent it

14

A A

5

Modify OCP current from 4.6A to 7A,because peak
current of +VTT is 6A in spec.

Based on EMI dept. test result, we must add bead
and change capacity for EMI issue

prevent NI-MH battery over charge/discharge

Separate precharge path from VS net because leakage
current is larger than p recharge current

battery

misses

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

4

0.1E 33

0.1F 34 Add PF1 7A fuseAdd NI-MH battery

0.1F 37

0.1F

3

1. Change PR201 from 10K_1% to 14.3K_1%

2. Change PR209 from 15K_1% to 150K_1%

1. Add PL4 FBM-L11-453215-900LMAT

340.1F

2. Change PC 24 from 0.1UF to 470PF and add PC23
470PF

1. Connect pad2 of PD16 to VIN

2. Add PR20 1.5K and change PR84,PR85,and PR126 to

1.5K

Change battery OVP from 18.1V to 18.3V and
BATT-OVP will be changed from 4V to 4.04V

35

2

SST0.1Correct OCP of +VTT

PT0.3

0.3 PT

0.3 PT

0.3 PT0.1F 37 1.Add PR21 200 ohm

0.3 PT

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PIR
ADY11 LA-1181

39 41Friday, November 16, 2001

1

2

5

4

3

2

1

Version change list (P.I.R. List)

Item

Fixed Issue

noise issue from DC-DC

15

D D

Implement 6cell li-on

16

Reason for change

Change choice heighter capacitor

Add identifird signal 6C/8C#/4C#

Rev.

0.1F

0.1F

PG#

Change PC60 form 2.2F_1206_25V to 4.7UF_1210_25

35

33

1.Add PR1 100K and PR2 1K_1%

2.Add PR3 no-pop

Modify List

Page 2 of 3

B.Ver#

0.3

0.3

Phase

PT

PT

1. Change PR80 from 100K_0.1% to 152_0.1%

17

modify charge voltage

Change 4S charge voltage to 17V for 4 cell/8 cell
and NI-MH,other 3S is 12.75V for 6cell

0.1F

2. Change PR81 from 316K_0.1% to 309_0.1%

3. Add PR4 305K_0.1% and PR5 100K

34

4. Add PQ9 2N7002 and PQ10 DTC115EK

0.3

PT

5. Add PC173 0.1U

1. No-pop PCN1 and Populate PCN3

33

AC adapter is changed to 60W

18

modify constant power limited to 49W and
disable air adapter

0.1G

34

C C

19

for +5VALWP

The solution will reduce quantity of output
capacitor and increase stability

0.1G

35Add compensation solution

2. No-pop PR29 and PQ11

3. Change PR68 from 21K_1% to 28.7K_1%

4. No-pop PQ30, PR65,PR131,PC101

1. Populate PC122 47PF_0402

2. Populate PR179 2M_0402

3. Populate PR137 10.2K_0402_1%

4. Populate PC123 100PF_0402

0.3

0.3

PT

PT

5. Change PR136 from 0_0402 to
10K_0402_1%

1. No-pop PCN3 and Populate PCN1

2. Populate PR29 and PQ11

3. Change PR68 from 28.7K_1% to21K_1%

4. Populate PQ30, PR65,PR131,PC101

0.3

PT

20

AC adapter is changed to 70W

modify constant power limited to 64W and
support air line adaptor identified

33

0.1H

34

Charger can't charge

21

B B

power limited for airline adapter is

22

disabled

Pin3 of PQ9 isn't connectted pad2 of PR80

The control signal can't turn on PQ30

0.3C

0.3C

34

34

Pin3 of PQ9 isn't connectted pad2 of PR80

1.Change control signal from AIR_ADP# to
AIR_ADP

1.0

1.0

PT2

PT2

2.Change PQ30 from TP0610T to 2N7002

Delete on-pop component

23

24

Add FUSE for safety of battery

Fix Battery OVP protect point Fix the table of Battery OVP and reserve

25

A A

5

Because the reverse component is not need

Support NI-MH battery

PC115 about OP Amps oscillates

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

4

0.3C

0.3D

1.0 34 1.0 STNo-pop PC115

3

35

33

Delete PC84,PC85,PC88

2

1.0

1.0

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PIR
ADY11 LA-1181

PT2

STReverse PF1 and add PJP4

40 41Friday, November 16, 2001

1

2

5

4

3

2

1

Version change list (P.I.R. List)

Item

Fixed Issue B.Ver#

enhance conductivity of connector

26

D D

27

Fix DFX issue 1.0 36 1.0 ST2

28

Fix DFX issue

29

C C

Reason for change

enhance conductivity of battery connector based on
customer's requirement

modify constant power limited from 3.22A to 3.07A

The PL14 and PL15 is co-layout, but PL15 will not
be used.

Delete PJP9 for SMT process. 1.0 36 Delete PJP9

Rev. Modify List

1.0 Change PCN2 from BTC-07GR1 to BTC-07GR4 ST

1.0

PG#

33 1.0

1. Change PR68 from 21K_1% to 22.6_1%

34

2. Change PR65 from 15.8K_1% to19.6K_1%

Delete PL15

Page 3 of 3

Phase

1.0modify constant power limit spec.

ST2

B B

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PIR
ADY11 LA-1181

41 41Tuesday, November 20, 2001

1

2